[Elua-svn] r526 - in branches/eagle_mmc: . doc doc/ddlevelsfiles doc/eluadoc doc/en doc/images doc/pt doc/wb doc/wb_img inc romfs src src/lua src/modules src/platform src/platform/lm3s src/platform/lpc24xx src/platform/str9 test
jbsnyder at BerliOS
jbsnyder at mail.berlios.de
Fri Nov 6 03:08:59 CET 2009
Author: jbsnyder
Date: 2009-11-06 03:08:32 +0100 (Fri, 06 Nov 2009)
New Revision: 526
Added:
branches/eagle_mmc/doc/buildall.lua
branches/eagle_mmc/doc/ddlevelsfiles/
branches/eagle_mmc/doc/ddlevelsfiles/arrow-right.gif
branches/eagle_mmc/doc/docdata.lua
branches/eagle_mmc/doc/eluadoc.lua
branches/eagle_mmc/doc/eluadoc/
branches/eagle_mmc/doc/eluadoc/arch_platform_adc.lua
branches/eagle_mmc/doc/eluadoc/arch_platform_cpu.lua
branches/eagle_mmc/doc/eluadoc/arch_platform_eth.lua
branches/eagle_mmc/doc/eluadoc/arch_platform_ll.lua
branches/eagle_mmc/doc/eluadoc/arch_platform_pio.lua
branches/eagle_mmc/doc/eluadoc/arch_platform_pwm.lua
branches/eagle_mmc/doc/eluadoc/arch_platform_spi.lua
branches/eagle_mmc/doc/eluadoc/arch_platform_timers.lua
branches/eagle_mmc/doc/eluadoc/arch_platform_uart.lua
branches/eagle_mmc/doc/eluadoc/refman_gen_adc.lua
branches/eagle_mmc/doc/eluadoc/refman_gen_bit.lua
branches/eagle_mmc/doc/eluadoc/refman_gen_cpu.lua
branches/eagle_mmc/doc/eluadoc/refman_gen_net.lua
branches/eagle_mmc/doc/eluadoc/refman_gen_pack.lua
branches/eagle_mmc/doc/eluadoc/refman_gen_pd.lua
branches/eagle_mmc/doc/eluadoc/refman_gen_pio.lua
branches/eagle_mmc/doc/eluadoc/refman_gen_pwm.lua
branches/eagle_mmc/doc/eluadoc/refman_gen_spi.lua
branches/eagle_mmc/doc/eluadoc/refman_gen_term.lua
branches/eagle_mmc/doc/eluadoc/refman_gen_tmr.lua
branches/eagle_mmc/doc/eluadoc/refman_gen_uart.lua
branches/eagle_mmc/doc/eluadoc/refman_ps_lm3s_disp.lua
branches/eagle_mmc/doc/eluadoc/template.lua
branches/eagle_mmc/doc/en/modules_lm3s.html
branches/eagle_mmc/doc/en/refman_dep.html
branches/eagle_mmc/doc/images/
branches/eagle_mmc/doc/images/En.jpg
branches/eagle_mmc/doc/images/Pt.jpg
branches/eagle_mmc/doc/images/barlineleft.png
branches/eagle_mmc/doc/images/barlineright.png
branches/eagle_mmc/doc/images/blank.png
branches/eagle_mmc/doc/images/eLuaLogo.png
branches/eagle_mmc/doc/images/eLuaLogo.svg
branches/eagle_mmc/doc/images/elua_arch.png
branches/eagle_mmc/doc/images/google.gif
branches/eagle_mmc/doc/images/hideall.png
branches/eagle_mmc/doc/images/hideall_over.png
branches/eagle_mmc/doc/images/lng_en.png
branches/eagle_mmc/doc/images/lng_en_over.png
branches/eagle_mmc/doc/images/lng_es.png
branches/eagle_mmc/doc/images/lng_es_over.png
branches/eagle_mmc/doc/images/lng_pt.png
branches/eagle_mmc/doc/images/lng_pt_over.png
branches/eagle_mmc/doc/images/minusnode.png
branches/eagle_mmc/doc/images/minusnodelast.png
branches/eagle_mmc/doc/images/next.png
branches/eagle_mmc/doc/images/next_over.png
branches/eagle_mmc/doc/images/node.png
branches/eagle_mmc/doc/images/nodelast.png
branches/eagle_mmc/doc/images/plusnode.png
branches/eagle_mmc/doc/images/plusnodelast.png
branches/eagle_mmc/doc/images/previous.png
branches/eagle_mmc/doc/images/previous_over.png
branches/eagle_mmc/doc/images/sepblank.png
branches/eagle_mmc/doc/images/sepnode.png
branches/eagle_mmc/doc/images/sepvertline.png
branches/eagle_mmc/doc/images/showall.png
branches/eagle_mmc/doc/images/showall_over.png
branches/eagle_mmc/doc/images/stat_not_applicable.png
branches/eagle_mmc/doc/images/stat_not_implemented.png
branches/eagle_mmc/doc/images/stat_not_tested.png
branches/eagle_mmc/doc/images/stat_ok.png
branches/eagle_mmc/doc/images/sync.png
branches/eagle_mmc/doc/images/sync_over.png
branches/eagle_mmc/doc/images/terminalreneseas.jpg
branches/eagle_mmc/doc/images/title_background.png
branches/eagle_mmc/doc/images/vertline.png
branches/eagle_mmc/doc/images/volta-small.jpg
branches/eagle_mmc/doc/images/webbook.png
branches/eagle_mmc/doc/images/webbook_over.png
branches/eagle_mmc/doc/menu.css
branches/eagle_mmc/doc/pt/arch.html
branches/eagle_mmc/doc/pt/arch_coding.html
branches/eagle_mmc/doc/pt/arch_con_term.html
branches/eagle_mmc/doc/pt/arch_ltr.html
branches/eagle_mmc/doc/pt/arch_newport.html
branches/eagle_mmc/doc/pt/arch_overview.html
branches/eagle_mmc/doc/pt/arch_platform.html
branches/eagle_mmc/doc/pt/arch_romfs.html
branches/eagle_mmc/doc/pt/arch_tcpip.html
branches/eagle_mmc/doc/pt/doc.html
branches/eagle_mmc/doc/pt/forum.html
branches/eagle_mmc/doc/pt/installing.html
branches/eagle_mmc/doc/pt/installing_at91sam7x.html
branches/eagle_mmc/doc/pt/installing_avr32.html
branches/eagle_mmc/doc/pt/installing_i386.html
branches/eagle_mmc/doc/pt/installing_lm3s.html
branches/eagle_mmc/doc/pt/installing_lpc2888.html
branches/eagle_mmc/doc/pt/installing_stm32.html
branches/eagle_mmc/doc/pt/installing_str7.html
branches/eagle_mmc/doc/pt/installing_str9.html
branches/eagle_mmc/doc/pt/modules_lm3s.html
branches/eagle_mmc/doc/pt/refman_dep.html
branches/eagle_mmc/doc/pt/refman_gen.html
branches/eagle_mmc/doc/pt/toolchains.html
branches/eagle_mmc/doc/style1.css
branches/eagle_mmc/romfs/EK-LM3S6965.lua
branches/eagle_mmc/romfs/EK-LM3S8962.lua
branches/eagle_mmc/romfs/logo.bin
branches/eagle_mmc/romfs/logo.lua
branches/eagle_mmc/romfs/spaceship.lua
branches/eagle_mmc/romfs/tetrives.lua
branches/eagle_mmc/src/modules/bitarray.c
branches/eagle_mmc/src/platform/lm3s/can.c
branches/eagle_mmc/src/platform/lm3s/can.h
branches/eagle_mmc/src/platform/lm3s/hw_can.h
branches/eagle_mmc/src/platform/lm3s/hw_comp.h
branches/eagle_mmc/src/platform/lm3s/hw_epi.h
branches/eagle_mmc/src/platform/lm3s/hw_hibernate.h
branches/eagle_mmc/src/platform/lm3s/hw_i2c.h
branches/eagle_mmc/src/platform/lm3s/hw_i2s.h
branches/eagle_mmc/src/platform/lm3s/hw_qei.h
branches/eagle_mmc/src/platform/lm3s/hw_udma.h
branches/eagle_mmc/src/platform/lm3s/hw_usb.h
branches/eagle_mmc/src/platform/lm3s/hw_watchdog.h
branches/eagle_mmc/src/platform/lm3s/lm3s-9b92.ld
branches/eagle_mmc/src/platform/lm3s/lm3s6918.h
branches/eagle_mmc/src/platform/lm3s/lm3s6965.h
branches/eagle_mmc/src/platform/lm3s/lm3s8962.h
branches/eagle_mmc/src/platform/lm3s/lm3s9b92.h
branches/eagle_mmc/src/platform/lm3s/rom.h
branches/eagle_mmc/src/platform/lm3s/rom_map.h
branches/eagle_mmc/src/platform/lm3s/uart.c
branches/eagle_mmc/src/platform/lm3s/uart.h
branches/eagle_mmc/src/platform/lpc24xx/
branches/eagle_mmc/src/platform/lpc24xx/LPC23xx.h
branches/eagle_mmc/src/platform/lpc24xx/conf.py
branches/eagle_mmc/src/platform/lpc24xx/irq.c
branches/eagle_mmc/src/platform/lpc24xx/irq.h
branches/eagle_mmc/src/platform/lpc24xx/lpc2468.lds
branches/eagle_mmc/src/platform/lpc24xx/platform.c
branches/eagle_mmc/src/platform/lpc24xx/platform_conf.h
branches/eagle_mmc/src/platform/lpc24xx/stacks.h
branches/eagle_mmc/src/platform/lpc24xx/startup.s
branches/eagle_mmc/src/platform/lpc24xx/target.c
branches/eagle_mmc/src/platform/lpc24xx/target.h
branches/eagle_mmc/src/platform/lpc24xx/type.h
branches/eagle_mmc/src/platform/lpc24xx/uart.h
branches/eagle_mmc/src/platform/str9/str9_pio.c
Removed:
branches/eagle_mmc/README
branches/eagle_mmc/doc/en/dl_binaries.html
branches/eagle_mmc/doc/en/dl_sources.html
branches/eagle_mmc/doc/pt/dl_binaries.html
branches/eagle_mmc/doc/pt/dl_sources.html
branches/eagle_mmc/doc/readme.txt
branches/eagle_mmc/doc/style.css
branches/eagle_mmc/doc/wb/js2lua.bat
branches/eagle_mmc/doc/wb/js2lua.lua
branches/eagle_mmc/doc/wb/make_hh.lua
branches/eagle_mmc/doc/wb/template_index.html
branches/eagle_mmc/doc/wb/template_ssSearch.html
branches/eagle_mmc/doc/wb/template_wb_bar.html
branches/eagle_mmc/doc/wb/template_wb_search.html
branches/eagle_mmc/doc/wb/template_wb_title.html
branches/eagle_mmc/doc/wb/template_wb_tree.html
branches/eagle_mmc/doc/wb/wb2hh.bat
branches/eagle_mmc/doc/wb/wb_build.bat
branches/eagle_mmc/doc/wb/wb_build.lua
branches/eagle_mmc/doc/wb_img/barlineleft.png
branches/eagle_mmc/doc/wb_img/barlineright.png
branches/eagle_mmc/doc/wb_img/blank.png
branches/eagle_mmc/doc/wb_img/eLuaLogo.png
branches/eagle_mmc/doc/wb_img/elua_arch.png
branches/eagle_mmc/doc/wb_img/google.gif
branches/eagle_mmc/doc/wb_img/hideall.png
branches/eagle_mmc/doc/wb_img/hideall_over.png
branches/eagle_mmc/doc/wb_img/lng_en.png
branches/eagle_mmc/doc/wb_img/lng_en_over.png
branches/eagle_mmc/doc/wb_img/lng_es.png
branches/eagle_mmc/doc/wb_img/lng_es_over.png
branches/eagle_mmc/doc/wb_img/lng_pt.png
branches/eagle_mmc/doc/wb_img/lng_pt_over.png
branches/eagle_mmc/doc/wb_img/minusnode.png
branches/eagle_mmc/doc/wb_img/minusnodelast.png
branches/eagle_mmc/doc/wb_img/next.png
branches/eagle_mmc/doc/wb_img/next_over.png
branches/eagle_mmc/doc/wb_img/node.png
branches/eagle_mmc/doc/wb_img/nodelast.png
branches/eagle_mmc/doc/wb_img/plusnode.png
branches/eagle_mmc/doc/wb_img/plusnodelast.png
branches/eagle_mmc/doc/wb_img/previous.png
branches/eagle_mmc/doc/wb_img/previous_over.png
branches/eagle_mmc/doc/wb_img/sepblank.png
branches/eagle_mmc/doc/wb_img/sepnode.png
branches/eagle_mmc/doc/wb_img/sepvertline.png
branches/eagle_mmc/doc/wb_img/showall.png
branches/eagle_mmc/doc/wb_img/showall_over.png
branches/eagle_mmc/doc/wb_img/stat_not_applicable.png
branches/eagle_mmc/doc/wb_img/stat_not_implemented.png
branches/eagle_mmc/doc/wb_img/stat_not_tested.png
branches/eagle_mmc/doc/wb_img/stat_ok.png
branches/eagle_mmc/doc/wb_img/sync.png
branches/eagle_mmc/doc/wb_img/sync_over.png
branches/eagle_mmc/doc/wb_img/terminalreneseas.jpg
branches/eagle_mmc/doc/wb_img/title_background.png
branches/eagle_mmc/doc/wb_img/vertline.png
branches/eagle_mmc/doc/wb_img/volta-small.jpg
branches/eagle_mmc/doc/wb_img/webbook.png
branches/eagle_mmc/doc/wb_img/webbook_over.png
branches/eagle_mmc/romfs/LM3S.lua
branches/eagle_mmc/src/platform/lm3s/usart.c
branches/eagle_mmc/src/platform/lm3s/usart.h
Modified:
branches/eagle_mmc/CHANGELOG
branches/eagle_mmc/LICENSE
branches/eagle_mmc/SConstruct
branches/eagle_mmc/doc/en/arch.html
branches/eagle_mmc/doc/en/arch_coding.html
branches/eagle_mmc/doc/en/arch_con_term.html
branches/eagle_mmc/doc/en/arch_ltr.html
branches/eagle_mmc/doc/en/arch_newport.html
branches/eagle_mmc/doc/en/arch_overview.html
branches/eagle_mmc/doc/en/arch_platform.html
branches/eagle_mmc/doc/en/arch_romfs.html
branches/eagle_mmc/doc/en/arch_tcpip.html
branches/eagle_mmc/doc/en/building.html
branches/eagle_mmc/doc/en/comunity.html
branches/eagle_mmc/doc/en/dl_old.html
branches/eagle_mmc/doc/en/doc.html
branches/eagle_mmc/doc/en/downloads.html
branches/eagle_mmc/doc/en/examples.html
branches/eagle_mmc/doc/en/faq.html
branches/eagle_mmc/doc/en/forum.html
branches/eagle_mmc/doc/en/genericmodules.html
branches/eagle_mmc/doc/en/installing.html
branches/eagle_mmc/doc/en/installing_at91sam7x.html
branches/eagle_mmc/doc/en/installing_avr32.html
branches/eagle_mmc/doc/en/installing_i386.html
branches/eagle_mmc/doc/en/installing_lm3s.html
branches/eagle_mmc/doc/en/installing_lpc2888.html
branches/eagle_mmc/doc/en/installing_stm32.html
branches/eagle_mmc/doc/en/installing_str7.html
branches/eagle_mmc/doc/en/installing_str9.html
branches/eagle_mmc/doc/en/news.html
branches/eagle_mmc/doc/en/overview.html
branches/eagle_mmc/doc/en/refman.html
branches/eagle_mmc/doc/en/refman_gen.html
branches/eagle_mmc/doc/en/status.html
branches/eagle_mmc/doc/en/tc_386.html
branches/eagle_mmc/doc/en/tc_arm.html
branches/eagle_mmc/doc/en/tc_cortex.html
branches/eagle_mmc/doc/en/tchainbuild.html
branches/eagle_mmc/doc/en/tmr_ref.html
branches/eagle_mmc/doc/en/toolchains.html
branches/eagle_mmc/doc/en/tut_bootpc.html
branches/eagle_mmc/doc/en/tut_bootstick.html
branches/eagle_mmc/doc/en/tut_openocd.html
branches/eagle_mmc/doc/en/tutorials.html
branches/eagle_mmc/doc/en/using.html
branches/eagle_mmc/doc/en/versionhistory.html
branches/eagle_mmc/doc/pt/bit_ref.html
branches/eagle_mmc/doc/pt/building.html
branches/eagle_mmc/doc/pt/comunity.html
branches/eagle_mmc/doc/pt/cpu_ref.html
branches/eagle_mmc/doc/pt/disp_ref.html
branches/eagle_mmc/doc/pt/dl_old.html
branches/eagle_mmc/doc/pt/downloads.html
branches/eagle_mmc/doc/pt/eluaapi.html
branches/eagle_mmc/doc/pt/examples.html
branches/eagle_mmc/doc/pt/faq.html
branches/eagle_mmc/doc/pt/genericmodules.html
branches/eagle_mmc/doc/pt/gpio_ref.html
branches/eagle_mmc/doc/pt/net_ref.html
branches/eagle_mmc/doc/pt/news.html
branches/eagle_mmc/doc/pt/overview.html
branches/eagle_mmc/doc/pt/platdependentmodules.html
branches/eagle_mmc/doc/pt/platdepmodules.html
branches/eagle_mmc/doc/pt/pwm_ref.html
branches/eagle_mmc/doc/pt/refman.html
branches/eagle_mmc/doc/pt/spi_ref.html
branches/eagle_mmc/doc/pt/status.html
branches/eagle_mmc/doc/pt/sys_ref.html
branches/eagle_mmc/doc/pt/tc_386.html
branches/eagle_mmc/doc/pt/tc_arm.html
branches/eagle_mmc/doc/pt/tc_cortex.html
branches/eagle_mmc/doc/pt/tchainbuild.html
branches/eagle_mmc/doc/pt/term_ref.html
branches/eagle_mmc/doc/pt/tmr_ref.html
branches/eagle_mmc/doc/pt/tut_bootpc.html
branches/eagle_mmc/doc/pt/tut_bootstick.html
branches/eagle_mmc/doc/pt/tut_openocd.html
branches/eagle_mmc/doc/pt/tutorials.html
branches/eagle_mmc/doc/pt/uart_ref.html
branches/eagle_mmc/doc/pt/using.html
branches/eagle_mmc/doc/pt/versionhistory.html
branches/eagle_mmc/doc/wb/wb_usr_template.lua
branches/eagle_mmc/inc/luarpc_rpc.h
branches/eagle_mmc/inc/romfs.h
branches/eagle_mmc/inc/version.h
branches/eagle_mmc/mkfs.py
branches/eagle_mmc/romfs/adcscope.lua
branches/eagle_mmc/romfs/led.lua
branches/eagle_mmc/romfs/lhttpd.lua
branches/eagle_mmc/romfs/morse.lua
branches/eagle_mmc/romfs/piano.lua
branches/eagle_mmc/romfs/pong.lua
branches/eagle_mmc/romfs/pwmled.lua
branches/eagle_mmc/src/lua/lapi.c
branches/eagle_mmc/src/lua/lauxlib.c
branches/eagle_mmc/src/lua/lbaselib.c
branches/eagle_mmc/src/lua/ldo.c
branches/eagle_mmc/src/lua/lfunc.c
branches/eagle_mmc/src/lua/lgc.c
branches/eagle_mmc/src/lua/lgc.h
branches/eagle_mmc/src/lua/linit.c
branches/eagle_mmc/src/lua/lrotable.c
branches/eagle_mmc/src/lua/lrotable.h
branches/eagle_mmc/src/lua/lstate.c
branches/eagle_mmc/src/lua/lstate.h
branches/eagle_mmc/src/lua/lstring.c
branches/eagle_mmc/src/lua/ltable.c
branches/eagle_mmc/src/lua/lua.c
branches/eagle_mmc/src/lua/lua.h
branches/eagle_mmc/src/lua/luaconf.h
branches/eagle_mmc/src/lua/lvm.c
branches/eagle_mmc/src/luarpc_posix_serial.c
branches/eagle_mmc/src/main.c
branches/eagle_mmc/src/modules/adc.c
branches/eagle_mmc/src/modules/auxmods.h
branches/eagle_mmc/src/modules/luarpc.c
branches/eagle_mmc/src/modules/net.c
branches/eagle_mmc/src/modules/spi.c
branches/eagle_mmc/src/modules/tmr.c
branches/eagle_mmc/src/modules/uart.c
branches/eagle_mmc/src/platform/lm3s/adc.c
branches/eagle_mmc/src/platform/lm3s/adc.h
branches/eagle_mmc/src/platform/lm3s/conf.py
branches/eagle_mmc/src/platform/lm3s/cpu.c
branches/eagle_mmc/src/platform/lm3s/cpu.h
branches/eagle_mmc/src/platform/lm3s/debug.h
branches/eagle_mmc/src/platform/lm3s/ethernet.c
branches/eagle_mmc/src/platform/lm3s/ethernet.h
branches/eagle_mmc/src/platform/lm3s/flash.c
branches/eagle_mmc/src/platform/lm3s/flash.h
branches/eagle_mmc/src/platform/lm3s/gpio.c
branches/eagle_mmc/src/platform/lm3s/gpio.h
branches/eagle_mmc/src/platform/lm3s/hw_adc.h
branches/eagle_mmc/src/platform/lm3s/hw_ethernet.h
branches/eagle_mmc/src/platform/lm3s/hw_flash.h
branches/eagle_mmc/src/platform/lm3s/hw_gpio.h
branches/eagle_mmc/src/platform/lm3s/hw_ints.h
branches/eagle_mmc/src/platform/lm3s/hw_memmap.h
branches/eagle_mmc/src/platform/lm3s/hw_nvic.h
branches/eagle_mmc/src/platform/lm3s/hw_pwm.h
branches/eagle_mmc/src/platform/lm3s/hw_ssi.h
branches/eagle_mmc/src/platform/lm3s/hw_sysctl.h
branches/eagle_mmc/src/platform/lm3s/hw_timer.h
branches/eagle_mmc/src/platform/lm3s/hw_types.h
branches/eagle_mmc/src/platform/lm3s/hw_uart.h
branches/eagle_mmc/src/platform/lm3s/interrupt.c
branches/eagle_mmc/src/platform/lm3s/interrupt.h
branches/eagle_mmc/src/platform/lm3s/platform.c
branches/eagle_mmc/src/platform/lm3s/platform_conf.h
branches/eagle_mmc/src/platform/lm3s/pwm.c
branches/eagle_mmc/src/platform/lm3s/pwm.h
branches/eagle_mmc/src/platform/lm3s/ssi.c
branches/eagle_mmc/src/platform/lm3s/ssi.h
branches/eagle_mmc/src/platform/lm3s/startup_gcc.c
branches/eagle_mmc/src/platform/lm3s/sysctl.c
branches/eagle_mmc/src/platform/lm3s/sysctl.h
branches/eagle_mmc/src/platform/lm3s/systick.c
branches/eagle_mmc/src/platform/lm3s/systick.h
branches/eagle_mmc/src/platform/lm3s/timer.c
branches/eagle_mmc/src/platform/lm3s/timer.h
branches/eagle_mmc/src/platform/str9/conf.py
branches/eagle_mmc/src/platform/str9/platform.c
branches/eagle_mmc/src/platform/str9/platform_conf.h
branches/eagle_mmc/src/romfs.c
branches/eagle_mmc/src/shell.c
branches/eagle_mmc/test/test-rpc.lua
Log:
Merge remote branch 'remotes/trunk' into local_mmc
Conflicts:
SConstruct
src/main.c
src/platform/lm3s/conf.py
src/platform/lm3s/platform.c
src/platform/lm3s/platform_conf.h
src/shell.c
Modified: branches/eagle_mmc/CHANGELOG
===================================================================
--- branches/eagle_mmc/CHANGELOG 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/CHANGELOG 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,17 +1,22 @@
-Trunk Dev Bogdan Marinescu <bogdanm at eluaproject.net>
- Dado Sutter <dado at eluaproject.net>
- James Snyder <jbsnyder at fanplastic.org>
+06.10.2009 Bogdan Marinescu <bogdanm at eluaproject.net>
+ Dado Sutter <dado at eluaproject.net>
+ James Snyder <jbsnyder at fanplastic.org>
+ * Official release 0.6
+ * License changed to MIT
+ * Web page and documentation completely redesigned
+ * Documentation available offline
+ * Added support for AVR32 CPUs
+ * Added support for STM32 Cortex-M3 CPUs
+ * Added ADC module with support for moving average filters
+ * Added support for multiple toolchains
* Added an ls (or dir) shell command
- * Added support for STM32
- * Examples added pong, (morse on RIT128x96x4 ?, snake ?)
- * Documentation now in PDF format (work in progress)
- * added ADC module
- *
- *
+ * Added new examples: pong, tetrives, spaceship (games), logo
+ (graphics), adcpoll, adcscope (ADC operations)
+ * Added the LTR (Lua Tiny RAM) patch
+ * ROM FS content can be specified per board now
+ * API semantic revisions (old code might not be compatible)
-
-
01.11.2008 Bogdan Marinescu <bogdanm at users.berlios.de>
Dado Sutter <dadosutter at esp.puc-rio.br>
Modified: branches/eagle_mmc/LICENSE
===================================================================
--- branches/eagle_mmc/LICENSE 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/LICENSE 2009-11-06 02:08:32 UTC (rev 526)
@@ -11,7 +11,8 @@
is distributed under a MIT license.
The "integer only lua" is based on the "Go Long Lua!" patch by John D.
-Ramsdell (from the Lua Power Patches page).
+Ramsdell (from the Lua Power Patches page) and is placed in the public
+domain.
The multiple memory allocator (dlmalloc) is written by Doug Lea and it's
placed on the public domain.
@@ -19,347 +20,31 @@
uIP (the TCP/IP stack used by eLua) is written by Adam Dunkels and released
under a BSD license. The eLua version is slightly modified.
-The rest of the code is licensed under GPL, listed below.
+Manufacturer provided CPU support libraries are licensed under their own
+terms, check src/platform/<platform> for details.
+The rest of the code is licensed under MIT, listed below.
+
================================================================================
+The MIT License
- GNU GENERAL PUBLIC LICENSE
- Version 2, June 1991
+Copyright (c) 2009 Dado Sutter and Bogdan Marinescu
- Copyright (C) 1989, 1991 Free Software Foundation, Inc.
- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
- Everyone is permitted to copy and distribute verbatim copies
- of this license document, but changing it is not allowed.
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+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
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Deleted: branches/eagle_mmc/README
===================================================================
--- branches/eagle_mmc/README 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/README 2009-11-06 02:08:32 UTC (rev 526)
@@ -1 +0,0 @@
-The project documentation is located in the docs/ subdirectory.
Modified: branches/eagle_mmc/SConstruct
===================================================================
--- branches/eagle_mmc/SConstruct 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/SConstruct 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,11 +1,18 @@
-import os, sys
+import os, sys, shutil
target = ARGUMENTS.get( 'target', 'lua' ).lower()
cputype = ARGUMENTS.get( 'cpu', '' ).upper()
allocator = ARGUMENTS.get( 'allocator', '' ).lower()
boardname = ARGUMENTS.get( 'board' , '').upper()
toolchain = ARGUMENTS.get( 'toolchain', '')
optram = int( ARGUMENTS.get( 'optram', '1' ) )
+boot = ARGUMENTS.get( 'boot', '').lower()
+# Helper: "normalize" a name to make it a suitable C macro name
+def cnorm( name ):
+ name = name.replace( '-', '' )
+ name = name.replace( ' ', '' )
+ return name.upper()
+
# List of toolchains
toolchain_list = {
'arm-gcc' : {
@@ -48,27 +55,29 @@
# Toolchain Aliases
toolchain_list['devkitarm'] = toolchain_list['arm-eabi-gcc']
-
# List of platform/CPU/toolchains combinations
# The first toolchain in the toolchains list is the default one
# (the one that will be used if none is specified)
platform_list = {
'at91sam7x' : { 'cpus' : [ 'AT91SAM7X256', 'AT91SAM7X512' ], 'toolchains' : [ 'arm-gcc', 'codesourcery', 'devkitarm', 'arm-eabi-gcc' ] },
- 'lm3s' : { 'cpus' : [ 'LM3S8962', 'LM3S6965', 'LM3S6918' ], 'toolchains' : [ 'arm-gcc', 'codesourcery', 'devkitarm', 'arm-eabi-gcc' ] },
+ 'lm3s' : { 'cpus' : [ 'LM3S8962', 'LM3S6965', 'LM3S6918', 'LM3S9B92' ], 'toolchains' : [ 'arm-gcc', 'codesourcery', 'devkitarm', 'arm-eabi-gcc' ] },
'str9' : { 'cpus' : [ 'STR912FAW44' ], 'toolchains' : [ 'arm-gcc', 'codesourcery', 'devkitarm', 'arm-eabi-gcc' ] },
'i386' : { 'cpus' : [ 'I386' ], 'toolchains' : [ 'i686-gcc' ] },
'sim' : { 'cpus' : [ 'LINUX' ], 'toolchains' : [ 'i686-gcc' ] },
'lpc288x' : { 'cpus' : [ 'LPC2888' ], 'toolchains' : [ 'arm-gcc', 'codesourcery', 'devkitarm', 'arm-eabi-gcc' ] },
'str7' : { 'cpus' : [ 'STR711FR2' ], 'toolchains' : [ 'arm-gcc', 'codesourcery', 'devkitarm', 'arm-eabi-gcc' ] },
'stm32' : { 'cpus' : [ 'STM32F103ZE', 'STM32F103RE' ], 'toolchains' : [ 'arm-gcc', 'codesourcery', 'devkitarm', 'arm-eabi-gcc' ] },
- 'avr32' : { 'cpus' : [ 'AT32UC3A0512' ], 'toolchains' : [ 'avr32-gcc' ] }
+ 'avr32' : { 'cpus' : [ 'AT32UC3A0512' ], 'toolchains' : [ 'avr32-gcc' ] },
+ 'lpc24xx' : { 'cpus' : [ 'LPC2468' ], 'toolchains' : [ 'arm-gcc', 'codesourcery', 'devkitarm', 'arm-eabi-gcc' ] }
}
# List of board/CPU combinations
board_list = { 'SAM7-EX256' : [ 'AT91SAM7X256', 'AT91SAM7X512' ],
'EK-LM3S8962' : [ 'LM3S8962' ],
'EK-LM3S6965' : [ 'LM3S6965' ],
+ 'EK-LM3S9B92' : [ 'LM3S9B92' ],
'STR9-COMSTICK' : [ 'STR912FAW44' ],
+ 'STR-E912' : [ 'STR912FAW44' ],
'PC' : [ 'I386' ],
'SIM' : [ 'LINUX' ],
'LPC-H2888' : [ 'LPC2888' ],
@@ -76,7 +85,8 @@
'STM3210E-EVAL' : [ 'STM32F103ZE' ],
'ATEVK1100' : [ 'AT32UC3A0512' ],
'ET-STM32' : [ 'STM32F103RE' ],
- 'EAGLE-100' : [ 'LM3S6918' ]
+ 'EAGLE-100' : [ 'LM3S6918' ],
+ 'ELUA-PUC' : ['LPC2468' ]
}
# ROMFS file list "groups"
@@ -86,7 +96,7 @@
romfs = { 'bisect' : [ 'bisect.lua' ],
'hangman' : [ 'hangman.lua' ],
'lhttpd' : [ 'index.pht', 'lhttpd.lua', 'test.lua' ],
- 'pong' : [ 'pong.lua', 'LM3S.lua' ],
+ 'pong' : [ 'pong.lua' ],
'led' : [ 'led.lua' ],
'piano' : [ 'piano.lua' ],
'pwmled' : [ 'pwmled.lua' ],
@@ -97,7 +107,10 @@
'dualpwm' : [ 'dualpwm.lua' ],
'adcscope' : [ 'adcscope.lua' ],
'adcpoll' : [ 'adcpoll.lua' ],
- 'life' : [ 'life.lua' ]
+ 'life' : [ 'life.lua' ],
+ 'logo' : ['logo.lua', 'logo.bin' ],
+ 'spaceship' : [ 'spaceship.lua' ],
+ 'tetrives' : [ 'tetrives.lua' ]
}
# List of platform/CPU combinations
@@ -126,10 +139,11 @@
# List of board/romfs data combinations
file_list = { 'SAM7-EX256' : [ 'bisect', 'hangman' , 'led', 'piano', 'hello', 'info', 'morse' ],
- 'EK-LM3S8962' : [ 'bisect', 'hangman', 'lhttpd', 'pong', 'led', 'piano', 'pwmled', 'tvbgone', 'hello', 'info', 'morse', 'adcscope' ],
- 'EK-LM3S6965' : [ 'bisect', 'hangman', 'lhttpd', 'pong', 'led', 'piano', 'pwmled', 'tvbgone', 'hello', 'info', 'morse', 'adcscope' ],
- 'EAGLE-100' : [ 'led', 'info' ],
+ 'EK-LM3S8962' : [ 'bisect', 'hangman', 'lhttpd', 'pong', 'led', 'piano', 'pwmled', 'tvbgone', 'hello', 'info', 'morse', 'adcscope', 'adcpoll', 'logo', 'spaceship', 'tetrives' ],
+ 'EK-LM3S6965' : [ 'bisect', 'hangman', 'lhttpd', 'pong', 'led', 'piano', 'pwmled', 'tvbgone', 'hello', 'info', 'morse', 'adcscope', 'adcpoll', 'logo', 'spaceship', 'tetrives' ],
+ 'EK-LM3S9B92' : [ 'bisect', 'hangman', 'lhttpd', 'led', 'pwmled', 'hello', 'info', 'adcscope','adcpoll', 'life' ],
'STR9-COMSTICK' : [ 'bisect', 'hangman', 'led', 'hello', 'info' ],
+ 'STR-E912' : [ 'bisect', 'hangman', 'led', 'hello', 'info', 'piano' ],
'PC' : [ 'bisect', 'hello', 'info', 'life', 'hangman' ],
'SIM' : [ 'bisect', 'hello', 'info', 'life', 'hangman' ],
'LPC-H2888' : [ 'bisect', 'hangman', 'led', 'hello', 'info' ],
@@ -137,8 +151,9 @@
'STM3210E-EVAL' : [ 'bisect', 'hello', 'info' ],
'ATEVK1100' : [ 'bisect', 'hangman', 'led', 'hello', 'info' ],
'ET-STM32' : [ 'hello', 'hangman', 'info', 'bisect','adcscope','adcpoll', 'dualpwm', 'pwmled' ],
- 'EAGLE-100' : [ 'bisect', 'hangman', 'lhttpd', 'led', 'hello', 'info' ]
- }
+ 'EAGLE-100' : [ 'bisect', 'hangman', 'lhttpd', 'led', 'hello', 'info' ],
+ 'ELUA-PUC' : [ 'bisect', 'hangman', 'led', 'hello', 'info', 'pwmled' ]
+}
# Variants: board = <boardname>
# cpu = <cpuname>
@@ -209,7 +224,15 @@
print "Allocator can be either 'newlib', 'multiple' or 'simple'"
sys.exit( -1 )
+# Check boot mode selection
+if boot == '':
+ boot = 'standard'
+elif boot not in ['standard', 'luaremote']:
+ print "Unknown boot mode: ", boot
+ print "Boot mode can be either 'standard' or 'luaremote'"
+ sys.exit( -1 );
+
# User report
if not GetOption( 'clean' ):
print
@@ -219,6 +242,7 @@
print "Board: ", boardname
print "Platform: ", platform
print "Allocator: ", allocator
+ print "Boot Mode: ", boot
print "Target: ", target == 'lua' and 'fplua' or 'target'
print "Toolchain: ", toolchain
print "*********************************"
@@ -226,11 +250,16 @@
output = 'elua_' + target + '_' + cputype.lower()
cdefs = '-DELUA_CPU=%s -DELUA_BOARD=%s -DELUA_PLATFORM=%s -D__BUFSIZ__=128' % ( cputype, boardname, platform.upper() )
+# Also make the above into direct defines (to use in conditional C code)
+cdefs = cdefs + " -DELUA_CPU_%s -DELUA_BOARD_%s -DELUA_PLATFORM_%s" % ( cnorm( cputype ), cnorm( boardname ), cnorm( platform ) )
if allocator == 'multiple':
cdefs = cdefs + " -DUSE_MULTIPLE_ALLOCATOR"
elif allocator == 'simple':
cdefs = cdefs + " -DUSE_SIMPLE_ALLOCATOR"
+if boot == 'luaremote':
+ cdefs += " -DELUA_BOOT_REMOTE"
+
# Special macro definitions for the SYM target
if platform == 'sim':
cdefs = cdefs + " -DELUA_SIMULATOR -DELUA_SIM_%s" % cputype
@@ -270,13 +299,15 @@
local_include += ['src/fatfs']
# Lua module files
-module_names = "pio.c spi.c tmr.c pd.c uart.c term.c pwm.c lpack.c bit.c net.c cpu.c adc.c can.c luarpc.c"
+module_names = "pio.c spi.c tmr.c pd.c uart.c term.c pwm.c lpack.c bit.c net.c cpu.c adc.c can.c luarpc.c bitarray.c"
module_files = " " + " ".join( [ "src/modules/%s" % name for name in module_names.split() ] )
# Optimizer flags (speed or size)
#opt = "-O3"
opt = "-Os -fomit-frame-pointer"
+#opt += " -ffreestanding"
+
# Toolset data (filled by each platform in part)
tools = {}
@@ -286,17 +317,27 @@
# Complete file list
source_files = app_files + specific_files + newlib_files + uip_files + lua_full_files + module_files
-# Make filesystem first
+# Make ROM File System first
if not GetOption( 'clean' ):
- print "Building filesystem..."
+ print "Building ROM File System..."
+ romdir = "romfs"
flist = []
for sample in file_list[ boardname ]:
- flist = flist + romfs[ sample ]
+ flist += romfs[ sample ]
+# Automatically includes the autorun.lua file in the ROMFS
+ if os.path.isfile( os.path.join( romdir, 'autorun.lua' ) ):
+ flist += [ 'autorun.lua' ]
+# Automatically includes platform specific Lua module
+ if os.path.isfile( os.path.join( romdir, boardname + '.lua' ) ):
+ flist += [boardname + '.lua']
import mkfs
- mkfs.mkfs( "romfs", "romfiles", flist )
+ mkfs.mkfs( romdir, "romfiles", flist )
print
- os.system( "mv -f romfiles.h inc/" )
- os.system( "rm -f src/fs.o" )
+ if os.path.exists( "inc/romfiles.h" ):
+ os.remove( "inc/romfiles.h" )
+ shutil.move( "romfiles.h", "inc/" )
+ if os.path.exists( "src/fs.o" ):
+ os.remove( "src/fs.o" )
# Env for building the program
comp = Environment( CCCOM = tools[ platform ][ 'cccom' ],
Added: branches/eagle_mmc/doc/buildall.lua
===================================================================
--- branches/eagle_mmc/doc/buildall.lua 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/buildall.lua 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,542 @@
+require "lfs"
+require "eluadoc"
+
+-- Uncomment this when generating offline docs
+-- local is_offline = true
+
+-- Languages in the system
+-- NOTE: "en" must ALWAYS be the first entry in this array!
+-- NOTE: all languages must be given in lowercase only!
+languages = { "en", "pt" }
+
+-- Reverse lookup (language to idx) dictionary
+local langidx = {}
+for k, v in ipairs( languages ) do
+ langidx[ v ] = k
+end
+
+-------------------------------------------------------------------------------
+-- Indexes into our menu table (defined in docdata.lua)
+name_idx, link_idx, submenu_idx , title_idx = 1, 2, 3, 4
+
+-------------------------------------------------------------------------------
+-- "getstr" support (return strings in different languages)
+-- If defaults to english (but gives a warning) if the string isn't found in the given language
+
+-- This table keeps the strings we already emitted warnings for
+-- After all, we don't want to drive the user crazy
+local warned = {}
+function getstr( str, lang )
+ -- Get the language index from langidx
+ local idx = langidx[ lang ]
+ if not idx then error( string.format( "Invalid language %s", lang ) ) end
+ -- Look from the string in the "translations" table
+ local where
+ for _, v in ipairs( translations ) do
+ if v[ 1 ] == str then
+ where = v
+ break
+ end
+ end
+ if not where then error( string.format( "String %s not found in translations" , str ) ) end
+ -- Try to return the value in the specified language
+ -- If not possible, return the value in english, but issue a warning first
+ local res = where[ idx ]
+ if not res then
+ res = where[ 1 ]
+ if not warned[ str ] then
+ print( string.format( "*** WARNING: translation for '%s' in language '%s' not found!", str, lang ) )
+ warned[ str ] = true
+ end
+ end
+ return res
+end
+
+-------------------------------------------------------------------------------
+-- Generic helper functions
+
+-- Remove anchor from a link of the form a/b.../baselink.html#anchor
+local function get_base_link( name )
+ return ( name:gsub( "#.*", "" ) )
+end
+
+-- Get the menu field for a given item and language
+-- Returns the english name is the field for the specified language can't be found
+local function get_menu_field( menuitem, lang, fieldidx )
+ if not menuitem[ fieldidx ] then
+ return nil
+ else
+ if type( menuitem[ fieldidx ] ) == "string" then
+ return menuitem[ fieldidx ]
+ else
+ local lidx = langidx[ lang ]
+ return menuitem[ fieldidx ][ lidx ] or menuitem[ fieldidx ][ 1 ]
+ end
+ end
+end
+
+-- Get the menu name for a given menu item and a language
+-- Returns the english name if the name for the specified language can't be found
+local function get_menu_name( menuitem, lang )
+ return get_menu_field( menuitem, lang, name_idx )
+end
+
+-- Get the link for a given menu item and a language
+-- Returns the english name if the name for the specified language can't be found
+-- If the link field doesn't exists, the name is returned instead
+local function get_menu_title( menuitem, lang )
+ return get_menu_field( menuitem, lang, title_idx ) or get_menu_field( menuitem, lang, name_idx )
+end
+
+-- Set "print" to print indented (with 2 spaces)
+local oldprint
+local function indent_print()
+ oldprint = print
+ print = function( ... ) io.write( " " ); oldprint( ... ) end
+end
+
+-- Restore the "regular" print function
+local function regular_print()
+ print = oldprint
+end
+
+-------------------------------------------------------------------------------
+-- File/directory operations helpers
+
+-- Copy the given file to the 'dest' directory
+-- Doesn't do error checking
+local function copy_file( fname, dst )
+ local destname = fname
+ if fname:find( "/" ) then
+ -- Get only the filename from the path
+ local sidx
+ for f = #fname, 1, -1 do
+ if fname:sub( f, f ) == "/" then
+ sidx = f
+ break
+ end
+ end
+ destname = fname:sub( sidx + 1 )
+ end
+ local fsrc = io.open( fname, "rb" )
+ local fdst = io.open( string.format( "%s/%s", dst, destname ), "wb" )
+ local data = fsrc:read( "*a" )
+ fdst:write( data )
+ fsrc:close()
+ fdst:close()
+end
+
+-- Copy the 'src' directory to the 'dst' directory, going recursively through
+-- its content. Doesn't do error checking.
+local function copy_dir_rec( src, dst )
+ for f in lfs.dir( src ) do
+ local oldf = string.format( "%s/%s", src, f )
+ local attrs = lfs.attributes( oldf )
+ if attrs.mode == 'directory' and f ~= "." and f ~= ".." and f ~= ".svn" then
+ local newdir = string.format( "%s/%s", dst, f )
+ lfs.mkdir( newdir )
+ copy_dir_rec( oldf, newdir )
+ elseif attrs.mode == 'file' then
+ copy_file( oldf, dst )
+ end
+ end
+end
+
+-- Remove a directory recusively
+-- USE WITH CARE!! Doesn't do much checks :)
+local function rm_dir_rec( dirname )
+ for f in lfs.dir( dirname ) do
+ local ename = string.format( "%s/%s", dirname, f )
+ local attrs = lfs.attributes( ename )
+ if attrs.mode == 'directory' and f ~= '.' and f ~= '..' then
+ rm_dir_rec( ename )
+ elseif attrs.mode == 'file' or attrs.mode == 'named pipe' or attrs.mode == 'link' then
+ os.remove( ename )
+ end
+ end
+ lfs.rmdir( dirname )
+end
+
+-- Copy a directory to another directory
+local function copy_dir( src, dst )
+ local newdir = string.format( "%s/%s", dst, src )
+ lfs.mkdir( newdir )
+ copy_dir_rec( src, newdir )
+end
+
+-------------------------------------------------------------------------------
+-- Build the list of files that must be processed starting from the menu data
+
+-- Traverse a second (or higher) level menu and add relevant information to flist
+local function traverse_list( item, parentid, flist )
+ if not item[ link_idx ] then return end
+ local base = get_base_link( item[ link_idx ] )
+ if base ~= "" and not flist[ base ] then
+ flist[ base ] = { parentid = parentid, item = item }
+ end
+ if item[ submenu_idx ] then
+ for i = 1, #item[ submenu_idx ] do
+ traverse_list( item[ submenu_idx ][ i ], parentid, flist )
+ end
+ end
+end
+
+-- Iterate over the menu list, building the list of files that must be
+-- processed by the doc generator. Returns a dictionary with list, parent_id
+-- pairs where parent_id is the parent menu of link in themenu
+local function get_file_list()
+ local flist = {}
+ for i = 1, #themenu do
+ traverse_list( themenu[ i ], i, flist )
+ end
+ return flist
+end
+
+-- Returns true if the given string begins with the given substring, false otherwise
+-- The comparation is case-insensitive
+local function beginswith( str, prefix )
+ return str:sub( 1, #prefix ):lower() == prefix:lower()
+end
+
+-------------------------------------------------------------------------------
+-- Build the navigation data for a given page
+
+-- Helper function: format a link starting from language and link
+-- Links marked as "#" ("null" links) are left alone
+local function get_link( lang, link )
+ return link == "#" and "#" or string.format( "%s_%s", lang, link )
+end
+
+-- Helper for gen_html_nav: generate the submenu(s) for a given top level menu item
+local function gen_submenus( item, lang, level )
+ level = level or 1
+ local data = ''
+ local lidx = langidx[ lang ]
+ local arrptr = '<img class="rightarrowpointer" src="ddlevelsfiles/arrow-right.gif" alt="right arrow" />'
+ for i = 1, #item do
+ local l = item[ i ]
+ if l[ submenu_idx ] then
+ data = data .. string.rep( " ", level * 2 + 8 ) .. string.format( '<li><a href="%s">%s%s</a>\n', get_link( lang, l[ link_idx ] ), arrptr, get_menu_name( l, lang ) )
+ data = data .. string.rep( " ", level * 2 + 8 ) .. "<ul>\n"
+ data = data .. gen_submenus( l[ submenu_idx ], lang, level + 1 )
+ data = data .. string.rep( " ", level * 2 + 8 ) .. "</ul></li>\n"
+ else
+ if get_menu_name( l, lang ) then
+ data = data .. string.rep( " ", level * 2 + 8 ) .. string.format( '<li><a href="%s">%s</a></li>\n',
+ get_link( lang, l[ link_idx ] ), get_menu_name( l, lang ) )
+ end
+ end
+ end
+ return data
+end
+
+-- Generate the HTML menu structure for the given language and parentid
+-- If "is_offline" is true, don't generate links to the counter and the BerliOS logo
+local function gen_html_nav( parentid, lang )
+ local htmlstr = [[
+<div id="nav">
+ <ul id="menu">
+]]
+ local lidx = langidx[ lang ]
+ for i = 1, #themenu do
+ local menudata = ""
+ local imginsert = ""
+ local styledef = i == #themenu and ' style="border-bottom-width: 0"' or ""
+ local link = themenu[ i ][ link_idx ]
+ local name = get_menu_name( themenu[ i ], lang )
+ if not link then
+ htmlstr = htmlstr .. string.format(' <li class="sep"%s>%s</li>\n', styledef, name )
+ else
+ local relname = string.gsub( string.gsub( string.format( "s_%d_%s", i, string.lower( get_base_link( link ) ) ), "%s", "_" ), "%.html", "" )
+ -- If we have a submenu, update the HTML menu content part
+ if themenu[ i ][ submenu_idx ] then
+ menudata = string.format( [[
+ <ul id="%s">
+%s
+ </ul>
+]], relname, string.sub( gen_submenus( themenu[ i ][ submenu_idx ], lang ), 1, -2 ) )
+ imginsert = '<img class="rightarrowpointer" src="ddlevelsfiles/arrow-right.gif" alt="right arrow" />'
+ end
+ if name then
+ if i == parentid then
+ -- If this is the parent, use a special style for it (<a class="current"> or <li class="current">, depending on the item type)
+ if themenu[ i ][ submenu_idx ] then
+ htmlstr = htmlstr .. string.format(' <li><a class="current" href="%s" rel="%s"%s>%s%s</a>\n%s </li>\n', get_link( lang, link ), relname, styledef, imginsert, name, menudata )
+ else
+ htmlstr = htmlstr .. string.format(' <li class="current"%s>%s%s\n%s </li>\n', styledef, imginsert, name, menudata )
+ end
+ else
+ local submenustr = themenu[ i ][ submenu_idx ] and string.format( ' rel="%s"', relname ) or ""
+ htmlstr = htmlstr .. string.format(' <li><a href="%s"%s%s>%s%s</a>\n%s </li>\n', get_link( lang, link ), submenustr, styledef, imginsert, name, menudata )
+ end
+ end
+ end
+ end
+ offline_data = not is_offline and [[
+ <p style="margin-left: 35px;"><a href="http://www.pax.com/free-counters.html"><img src="http://counter.pax.com/counter/image?counter=ctr-zsg80nnmqt" alt="Free Hit Counter" style="border: 0;" /></a></p>
+<p style="margin-left: 18px;"><a href="http://developer.berlios.de" title="BerliOS Developer"> <img src="http://developer.berlios.de/bslogo.php?group_id=9919" width="124px" height="32px" style="border: 0;" alt="BerliOS Developer Logo" /></a></p>
+]] or ""
+ htmlstr = htmlstr .. string.format( [[
+ </ul>
+%s</div>
+]], offline_data )
+ return htmlstr
+end
+
+-------------------------------------------------------------------------------
+-- Build the logo for a given language
+
+local function gen_logo( fname, lang )
+ local numl = #languages
+ local langdata = ''
+ for i = 1, numl do
+ local crtlang = languages[ i ]
+ local hlang = crtlang:sub( 1, 1 ):upper() .. crtlang:sub( 2, -1 )
+ if lang:lower() == crtlang:lower() then
+ langdata = langdata .. string.format(' <td align="center"><h6 class="selected"><img src="images/%s.jpg" alt="%s" style="border: 0;" /></h6></td>\n', hlang, crtlang )
+ else
+ langdata = langdata .. string.format(' <td align="center"><h6><a href="%s_%s" class="lang"><img src="images/%s.jpg" alt="%s" style="border: 0;" /></a></h6></td>\n', crtlang:lower(), fname, hlang, crtlang )
+ end
+ end
+return string.format( [[
+<form method="get" action="http://www.google.com/search">
+<div id="logo">
+ <table border="0" style="width: 100%%%%;" cellspacing="0" cellpadding="0">
+ <tr>
+ <td valign="middle" style="width: 90px;"><img src="images/eLuaLogo.png" alt="eLua logo" class="logo_elua" /></td>
+ <td class="header_title" valign="middle">%s</td>
+
+ <td style="width: 280px;" align="center" valign="middle">
+ <table border="0" cellspacing="0" cellpadding="0">
+ <tr style="height: 40px;">
+ <td colspan="%d">
+ <input type="hidden" name="ie" value="utf-8" />
+ <input type="hidden" name="oe" value="utf-8" />
+ <input type="text" name="q" size="21" maxlength="255" value="" />
+ </td>
+ <td style="padding-left: 5px;">
+ <input type="submit" name="btnG" value="%s" style="height: 21px; font-size: x-small;" />
+ <input type="hidden" name="domains" value="http://www.eluaproject.net" />
+ <input type="hidden" name="sitesearch" value="http://www.eluaproject.net" />
+ </td>
+ </tr>
+ <tr>
+ <td align="center"><h6>%s:</h6></td>
+%s
+ <td align="center"> </td>
+ </tr>
+ </table>
+ </td>
+ </tr>
+ </table>
+</div>
+</form>
+]], getstr( "eLua - Embedded Lua", lang ), numl + 1, getstr( "Search", lang ), getstr( "Language", lang ), langdata:sub( 1, -2 ) )
+end
+
+-------------------------------------------------------------------------------
+-- Generate an actual HTML page starting from a template
+-- Replace the $$HEADER$$ and $$FOOTER$$ with proper data
+local function gen_html_page( fname, lang )
+ local entry = flist[ fname ]
+ local parentid = entry.parentid
+ local item = entry.item
+
+ -- Open and read file
+ local fullname = string.format( "%s/%s", lang, fname )
+ local f = io.open( fullname, "rb" )
+ if not f then
+ return nil, string.format( "Error opening %s", fullname )
+ end
+ local orig = f:read( "*a" )
+ f:close()
+
+ -- Check the presence of $$HEADER$$ and $$FOOTER$$
+ if not orig:find( "%$%$HEADER%$%$" ) or not orig:find( "%$%$FOOTER%$%$" ) then
+ return nil, string.format( "%s not formated properly ($$HEADER$$ or $$FOOTER$$ not found)", fullname )
+ end
+
+ -- Iterate through all the links in the document and change the local ones with
+ -- the correct language option
+ orig = orig:gsub( [==[<a href=["'](.-)["']>]==], function( link )
+ if beginswith( link, "#" ) or beginswith( link, "http://" ) or beginswith( link, "https://" ) or beginswith( link, "ftp://" ) then
+ return string.format( '<a href="%s">', link )
+ else
+ return string.format( '<a href="%s_%s">', lang, link )
+ end
+ end )
+
+ -- Anticipate some common errors and fix them directly
+ orig = orig:gsub( "<br>", "<br />" )
+ orig = orig:gsub( '(<a name=["\'][^\'"]-["\']>)([^\n]-)</a>%s-\n', function( anchor, data )
+ return anchor:gsub( ">", " />" ) .. data .. "\n"
+ end )
+ orig = orig:gsub( '<p><pre><code>(.-)</code></pre></p>', "<pre><code>%1</code></pre>" )
+ orig = orig:gsub( 'target="_blank"', "" )
+
+ -- Generate actual data
+ local header = string.format( [=[
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Strict//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-strict.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+
+<head>
+<title>%s</title>
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+<link href="menu.css" rel="stylesheet" type="text/css" />
+<link href="style1.css" rel="stylesheet" type="text/css" />
+<script type="text/javascript"><!--//--><![CDATA[//><!--
+
+sfHover = function() {
+ var sfEls = document.getElementById("nav").getElementsByTagName("LI");
+ for (var i=0; i<sfEls.length; i++) {
+ sfEls[i].onmouseover=function() {
+ this.className+=" sfhover";
+ }
+ sfEls[i].onmouseout=function() {
+ this.className=this.className.replace(new RegExp(" sfhover\\b"), "");
+ }
+ }
+}
+if (window.attachEvent) window.attachEvent("onload", sfHover);
+
+//--><!]]></script>
+</head>
+
+<body>
+]=], get_menu_title( item, lang ) )
+ header = header .. gen_logo( fname, lang ) .. "\n"
+ local menuitems = gen_html_nav( parentid, lang )
+ header = header .. menuitems .. '<div id="content">\n'
+ local footer = [[
+</div>
+</body>
+</html>
+]]
+ orig = orig:gsub( "%$%$HEADER%$%$", header )
+ orig = orig:gsub( "%$%$FOOTER%$%$", footer )
+ return orig
+end
+
+-------------------------------------------------------------------------------
+-- Documentation generator
+
+-- Helper function: iterate through the menu and replace automatically generated content
+local function replace_auto_content( automenus, item )
+ if type( item[ submenu_idx ] ) == "string" then
+ local r = automenus[ item[ submenu_idx ] ]
+ if not r then
+ return string.format( "Autogenerated menu '%s' not found", item[ submenu_idx ] )
+ else
+ print( string.format( "Replaced autogenerated menu '%s'", item[ submenu_idx ] ) )
+ item[ submenu_idx ] = r
+ end
+ elseif type( item[ submenu_idx ] ) == "table" then
+ for i = 1, #item[ submenu_idx ] do
+ replace_auto_content( automenus, item[ submenu_idx ][ i ] )
+ end
+ end
+end
+
+-- Argument check
+local args = { ... }
+local destdir
+if #args ~= 1 then
+ print "Using 'dist/' as the destination directory"
+ destdir = "dist"
+else
+ destdir = args[ 1 ]
+end
+
+-- Read the documentation data
+themenu, translations, fixed = dofile( "docdata.lua" )
+if not themenu or not translations or not fixed then
+ print "docdata.lua doesn't return the proper data, aborting."
+ return
+end
+
+-- Add the content generated from eluadoc to our menu(s)
+print "Generating HTML documentation..."
+indent_print()
+local automenus, genfiles = eluadoc.gen_html_doc()
+if not automenus then return end
+regular_print()
+-- Replace content generated by gen_html_doc in the menu
+for i = 1, #themenu do
+ local replerr = replace_auto_content( automenus, themenu[ i ] )
+ if replerr then
+ print( replerr )
+ return
+ end
+end
+print( "done" )
+
+-- If the destination directory doesn't exist, create it
+-- If it exists, remove it
+local attr = lfs.attributes( destdir )
+if not attr then
+ if not lfs.mkdir( destdir ) then
+ print( string.format( "Unable to create directory %s", destdir ) )
+ return
+ end
+else
+ if attr.mode ~= "directory" then
+ print( string.format( "%s is not a directory", destdir ) )
+ return
+ end
+ for k in lfs.dir( destdir ) do
+ if k ~= "." and k ~= ".." then
+ rm_dir_rec( destdir )
+ lfs.mkdir( destdir )
+ break
+ end
+ end
+end
+
+print "\nProcessing HTML templates..."
+indent_print()
+flist = get_file_list()
+for _, lang in ipairs( languages ) do
+ for fname, entry in pairs( flist ) do
+ print( string.format( "Processing %s %s...", fname, entry.item[ name_idx ] and "" or "(hidden entry)" ) )
+ local res, err = gen_html_page( fname, lang )
+ if not res then
+ print( "***" .. err )
+ else
+ local g = io.open( string.format( "%s/%s_%s", destdir, lang, fname ), "wb" )
+ if not g then
+ print( string.format( "Unable to open %s for writing", fname ) )
+ else
+ g:write( res )
+ g:close()
+ end
+ end
+ end
+end
+regular_print()
+print "done"
+
+-- Now copy the fixed content in the documentation directory
+print "\nCopying fixed content ..."
+indent_print()
+for _, v in ipairs( fixed ) do
+ print( string.format( "Copying %s", v ) )
+ if v:sub( -1 ) == "/" then
+ copy_dir( v, destdir )
+ else
+ copy_file( v, destdir )
+ end
+end
+regular_print()
+print "done"
+
+-- And delete the files generated by eluadoc
+print "\nCleaning up files generated by eluadoc..."
+indent_print()
+for _, v in pairs( genfiles ) do
+ print( string.format( "Deleting %s...", v ) )
+ os.remove( v )
+end
+regular_print()
+print "done"
+
+print( string.format( "\nEnjoy your documentation in %s :)", destdir ) )
Added: branches/eagle_mmc/doc/ddlevelsfiles/arrow-right.gif
===================================================================
--- branches/eagle_mmc/doc/ddlevelsfiles/arrow-right.gif 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/ddlevelsfiles/arrow-right.gif 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,2 @@
+GIF89a
+@˜P`
\ No newline at end of file
Property changes on: branches/eagle_mmc/doc/ddlevelsfiles/arrow-right.gif
___________________________________________________________________
Name: svn:executable
+ *
Added: branches/eagle_mmc/doc/docdata.lua
===================================================================
--- branches/eagle_mmc/doc/docdata.lua 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/docdata.lua 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,203 @@
+-- eLua Documentation structure is defined here
+
+--[[
+The menu is defined by an array of { name, link, submenu, title } arrays
+
+'name' can be another array. Names must be the same for all languages, in the same order
+as defined in the "languages" from 'buildall.lua'. If 'name' is a string instead
+of a table, it will be used in all languages.
+
+'link' is the relative link corresponding to the menu entry.
+
+'submenu' is optional. If specified, it is an array of arrays, just like the main
+menu.
+
+'title' is the title of the HTML page associated with the menu entry (specified as
+an array in different languages or as a string, just like 'name'). If not given,
+it's the same as 'name'.
+
+If 'link' is nil, the entry defines a menu separator.
+If 'name' is nil, the entry defines a "hidden menu item": they are part of the template to HTML
+generation process, but they don't appear in the menu. These entries NEED A LINK
+AND TITLE FIELDS! See the definition of 'forum.html' below for an example of such item.
+--]]
+local menu =
+{
+ -- "eLua project" (menu separator)
+ { { "eLua project", "Projeto eLua" } },
+
+ -- "Overview"
+ { { "Overview", "Apresentação" }, "overview.html",
+ {
+ { { "About", "O que é eLua ?" }, "overview.html#whatis" },
+ { { "Features", "CaracterÃsticas" }, "overview.html#features" },
+ { { "Audience", "Público Alvo" }, "overview.html#audience" },
+ { { "Authors", "Autores" }, "overview.html#authors" },
+ { { "Contacts","Contatos" }, "overview.html#contacts" },
+ { { "License", "Licença" },"overview.html#license" }
+ }
+ },
+
+ -- "Community"
+ { { "Community", "Comunidade" }, "comunity.html",
+ {
+ { { "Lists", "Listas de Discussão" }, "comunity.html#lists" },
+ { "Forums", "comunity.html#forums" },
+-- { "User's Wiki", "comunity.html#userswiki" },
+ { { "Credits", "Créditos" }, "comunity.html#credits" },
+ { nil, "forum.html", nil, "Forum" } -- "hidden" entry (doesn't appear in the menu)
+ }
+ },
+
+ -- News
+ { { "News", "NotÃcias" }, "news.html" },
+
+ -- "Status"
+ { "Status", "status.html",
+ {
+ { { "Supported platforms", "Plataformas Suportadas" }, "status.html#platforms" },
+ { { "Roadmap", "Planejamento Futuro" }, "status.html#roadmap" }
+ }
+ },
+
+ -- "Using eLua" -- Menu Separator
+ { { "Using eLua", "Usando eLua"}, nil },
+
+-- { { "Overview", "Visão Geral" }, "doc.html" }, ####### Aparently not necessary and taking noble main menu space
+ { { "Platforms", "Plataformas" }, "installing.html",
+ {
+ { "AT91SAM7x", "installing_at91sam7x.html" },
+ { "AVR32", "installing_avr32.html" },
+ { "i386", "installing_i386.html" },
+ { "LM3S", "installing_lm3s.html" },
+ { "LPC2888", "installing_lpc2888.html" },
+ { "STR7", "installing_str7.html" },
+ { "STR9", "installing_str9.html" },
+ { "STM32", "installing_stm32.html" },
+ },
+ },
+ { "Downloads", "downloads.html", -- ### How come it opens downloads.html without specifying here ? :) Nice but unclear.
+ {
+ { { "Binaries", "Binários" }, "downloads.html#binaries" },
+ { { "Source code", "Código Fonte" }, "downloads.html#source",
+ {
+ { { "Official releases", "Versões Oficiais" }, "downloads.html#official" },
+ { "Bleeding edge (SVN)", "downloads.html#svnpublic" },
+ { { "Developers", "Desenvolvedores" }, "downloads.html#svndev" },
+ }
+ },
+ { { "Old versions", "Versões Anteriores" }, "dl_old.html",
+ {
+ { "0.5", "dl_old.html#v050" },
+ { "0.4.1", "dl_old.html#v041" },
+ { "0.4", "dl_old.html#v04" },
+ { "0.3", "dl_old.html#v03" },
+ { "0.2", "dl_old.html#v02" },
+ { "0.1", "dl_old.html#v01" },
+ { { "Version history", "Histórico das Versões" }, "versionhistory.html" },
+ }
+ },
+ },
+ },
+ { { "Help", "Ajuda" }, "using.html",
+ {
+ { { "Building eLua", "Build de eLua" }, "building.html" },
+ { { "Using", "Usando eLua" }, "using.html",
+ {
+ { { "Over UART", "Console via UART" }, "using.html#uart" },
+ { { "Over TCP/IP", "Console via TCP/IP" }, "using.html#tcpip" },
+ { { "On PC", "Num PC" }, "using.html#pc" },
+ { { "The shell", "O Shell" }, "using.html#shell" },
+ { "Cross-compiling", "using.html#cross" },
+ },
+ },
+ { { "Code examples", "Exemplos de Código" }, "examples.html" },
+ { { "FAQ", "Perguntas Frequentes (FAQ)" }, "faq.html" },
+ { { "Tutorials", "Tutoriais" }, "tutorials.html",
+ {
+ { { "Booting on a PC", "Bootando num PC" }, "tut_bootpc.html" },
+ { { "Booting from a PenDrive", "Bootando de um Pen-Drive" }, "tut_bootstick.html" },
+ { { "Using OpenOCD", "Usando OpenOCD" }, "tut_openocd.html" },
+ { { "eLua toolchains", "Toolchains para eLua" }, "toolchains.html" },
+ { { "Building toolchains", "Build de Toolchains" }, "tchainbuild.html",
+ {
+ { "ARM7 and ARM9", "tc_arm.html" },
+ { "ARM Cortex-M3", "tc_cortex.html" },
+ { "i386", "tc_386.html" }
+ },
+ },
+ },
+ },
+ },
+ },
+
+ -- "eLua internals" (menu separator)
+ { { "eLua internals", "Arquitetura de eLua" } },
+
+ -- "Overview"
+ { { "Overview", "Visão Geral" }, "arch_overview.html",
+ {
+ { { "Structure", "Estrutura" }, "arch_overview.html#structure" },
+ { { "Common code", "Código Básico" }, "arch_overview.html#common" },
+ { { "Interface architecture", "Interfaceamento" }, "arch_overview.html#platform" },
+ { { "Platforms/ports", "Portabilização" }, "arch_overview.html#platforms" },
+ { { "Booting eLua", "O Boot de eLua" }, "arch_overview.html#boot" }
+ }
+ },
+
+ -- Platform interface (automatically generated)
+ { { "Platform interface", "Interfaceamento" }, "arch_platform.html", "arch_platform" },
+
+ -- Other WRITE THE arch_platform_other.html file
+ { { "More information", "Informações Adicionais" }, "#",
+ {
+ { { "ROM file system", "O ROM File System" }, "arch_romfs.html" },
+ { { "Adding a new port", "Portando eLua" }, "arch_newport.html" },
+ { { "Modules and LTR", "Modulos e LTR" }, "arch_ltr.html" },
+ { { "Consoles and terminals", "Consoles e Terminais" }, "arch_con_term.html" },
+ { { "TCP/IP in eLua", "TCP/IP em eLua" }, "arch_tcpip.html" },
+ { { "eLua coding style", "Regras de Codificação" }, "arch_coding.html" }
+ }
+ },
+
+ -- "Reference manual" (menu separator)
+ { { "Reference Manual", "Manual de Referência" } },
+
+ -- "Generic modules" (automatically generated)
+ { { "Generic modules", "Módulos Genéricos" }, "refman_gen.html", "refman_gen" },
+
+ -- "Platform modules"
+ { { "Platform modules", "Módulos EspecÃficos" }, "refman_dep.html",
+ {
+ { "lm3s", "modules_lm3s.html", "refman_ps_lm3s" }
+ }
+ }
+}
+
+
+-- Translations for different strings needed by the generator
+-- The order of languages is the same as the one defines in the languages array
+-- defined at the beginning of buildall.lua
+local translations =
+{
+ { "Overview", "Apresentação" },
+ { "Data structures", "Estrutura" },
+ { "Functions", "Funções" },
+ { "eLua - Embedded Lua", "eLua - Embedded Lua" },
+ { "Search", "Pesquisar" },
+ { "Language", "Idioma" }
+}
+
+-- The "fixed part" are the files/directory that must be present in our final
+-- HTML documentation distribution. Directories end with a "/", files don't.
+local fixed =
+{
+ "style1.css",
+ "menu.css",
+ "images/",
+ "ddlevelsfiles/"
+}
+
+-- Return our whole data
+return menu, translations, fixed
+
Added: branches/eagle_mmc/doc/eluadoc/arch_platform_adc.lua
===================================================================
--- branches/eagle_mmc/doc/eluadoc/arch_platform_adc.lua 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/eluadoc/arch_platform_adc.lua 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,126 @@
+-- eLua platform interface - ADC
+-- Make a full description for each language
+
+data_en =
+{
+ -- Menu name
+ menu_name = "ADC",
+
+ -- Title
+ title = "eLua platform interface - ADC",
+
+ -- Overview
+ overview = "This part of the platform interface groups functions related to the ADC interface(s) of the MCU.",
+
+ -- Functions
+ funcs =
+ {
+ { sig = "int #platform_adc_exists#( unsigned id );",
+ desc = [[Checks if the platform has the hardware ADC specified as argument. Implemented in %src/common.c%, it uses the $NUM_ADC$ macro that must be defined in the
+ platform's $platform_conf.h$ file (see @arch_overview.html#platforms at here@ for details). For example:</p>
+ ~#define NUM_ADC 1 $// The platform has 1 ADC interface$~<p> ]],
+ args = "$id$ - ADC interface ID",
+ ret = "1 if the ADC interface exists, 0 otherwise"
+ },
+
+ { sig = "u32 #platform_adc_op#( unsigned id, int op, u32 data );",
+ desc = "Executes an operation on an ADC channel",
+ args =
+ {
+ "$id$ - ADC channel ID",
+ [[$op$ - the operation that must be executed. It can take any value from @#adc_operations at this enum@, as follows:
+ <ul>
+ <li>$PLATFORM_ADC_GET_MAXVAL$: get the maximum conversion value the channel may supply (based on channel resolution)</li>
+ <li>$PLATFORM_ADC_SET_SMOOTHING$: sets the length of the moving average smoothing filter to $data$ </li>
+ <li>$PLATFORM_ADC_SET_BLOCKING$: sets whether or not sample requests should block, waiting for additional samples</li>
+ <li>$PLATFORM_ADC_IS_DONE$: checks whether sampling has completed</li>
+ <li>$PLATFORM_ADC_OP_SET_TIMER$: selects a timer to control sampling frequency</li>
+ <li>$PLATFORM_ADC_OP_SET_CLOCK$: set the frequency of sample acquisition</li>
+ </ul>]],
+ "$data$ - when used with $op$ == $PLATFORM_ADC_SET_SMOOTHING$, specifies the length of the moving average filter (must be a power of 2). If it is 1, filter is disabled.",
+ "$data$ - when used with $op$ == $PLATFORM_ADC_SET_BLOCKING$, specifies whether or not sample requests block. If 1, requests will block until enough samples are available or sampling has ended. If 0, requests will return immediately with up to the number of samples requested.",
+ "$data$ - when used with $op$ == $PLATFORM_ADC_OP_SET_TIMER$, specifies the timer to use to control sampling frequency.",
+ "$data$ - when used with $op$ == $PLATFORM_ADC_OP_SET_CLOCK$, specifies the frequency of sample collection in Hz (number of samples per second). If 0, timer is not used and samples are acquired as quickly as possible."
+ },
+ ret =
+ {
+ "the maximum possible conversion value when $op$ == $PLATFORM_ADC_GET_MAXVAL$",
+ "whether or not sampling has completed (1: yes, 0: no) when $op$ == $PLATFORM_ADC_IS_DONE$. This will return 1 (yes), if no samples have been requested.",
+ "the actual frequency of acquisition that will be used when $op$ == $PLATFORM_ADC_OP_SET_CLOCK$",
+ "irellevant for other operations"
+ }
+ },
+
+ { sig = "int #platform_adc_check_timer_id#( unsigned id, unsigned timer_id );",
+ desc = "Checks whether a timer may be used with a particular ADC channel",
+ args =
+ {
+ "$id$ - ADC channel ID",
+ "$timer_id$ - Timer ID",
+ },
+ ret = "1 if the timer may be used to trigger the ADC channel, 0 if not",
+ }
+ }
+}
+
+data_pt =
+{
+ -- Menu name
+ menu_name = "ADC",
+
+ -- Title
+ title = "eLua API - ADC",
+
+ -- Overview
+ overview = "Interfaceamento com as funcões do ADC da MCU.",
+
+ -- Functions
+ funcs =
+ {
+ { sig = "int #platform_adc_exists#( unsigned id );",
+ desc = [[Checa se a plataforma possui hardware para o Conversor AD especificado no argumento. Implementado em %src/common.c%, utiliza a macro $NUM_ADC$ que deve estar definida no arquivo $platform_conf.h$ da plataforma em questão. (veja @arch_overview.html#platforms at here@ para detalhes). Por exemplo:</p>
+ ~#define NUM_ADC 1 $// A Plataforma possui uma interface para ADC$~<p> ]],
+ args = "$id$ - ADC ID",
+ ret = "1 se a interface do ADC existir, 0 em caso contrário"
+ },
+
+ { sig = "u32 #platform_adc_op#( unsigned id, int op, u32 data );",
+ desc = "Executes an operation on an ADC channel",
+ args =
+ {
+ "$id$ - ID do canal ADC",
+ [[$op$ - A operação que deve ser executada. Valores possÃveis em @#adc_operations at this enum@, conforme:
+ <ul>
+ <li>$PLATFORM_ADC_GET_MAXVAL$: Pega o maior valor de conversão que o canal pode fornecer, dependendo de sua resolução.</li>
+ <li>$PLATFORM_ADC_SET_SMOOTHING$: Seta o tamanho do filtro atenuador de média móvel em $data$ </li>
+ <li>$PLATFORM_ADC_SET_BLOCKING$: Seta se a amostragem deve aguardar novos valores (blocking)</li>
+ <li>$PLATFORM_ADC_IS_DONE$: Checa se a amostragem foi completada</li>
+ <li>$PLATFORM_ADC_OP_SET_TIMER$: Seleciona um Timer para o controle da amostragem</li>
+ <li>$PLATFORM_ADC_OP_SET_CLOCK$: Seta a frequência de amostragem</li>
+ </ul>]],
+ "$data$ - quando usada com $op$ == $PLATFORM_ADC_SET_SMOOTHING$, especifica o tamanho do filtro de média móvel (deve ser potência de 2). O valor 1 desabilita o filtro.",
+ "$data$ - quando usada com $op$ == $PLATFORM_ADC_SET_BLOCKING$, especifica se a amostragem é blocking ou não. Se 1, os pedidos só retornam quando as amostras tiverem sido obtidas ou a amostragem encerrada. Se 0, os pedidos retornam imediatamente, com o número de amostras já obtidas.",
+ "$data$ - quando usada com $op$ == $PLATFORM_ADC_OP_SET_TIMER$, especifica o Timer a ser usado para o controle da frequência de amostragem.",
+ "$data$ - quando usada com $op$ == $PLATFORM_ADC_OP_SET_CLOCK$, especifica a frequência de amostragem em Hz (número de amostras por segundo). Se 0, nenhum Timer é usado e a amostragem é feita o mais rapidamente possÃvel."
+ },
+ ret =
+ {
+ "O maior valor possÃvel de ser obtido do conversor, quando $op$ == $PLATFORM_ADC_GET_MAXVAL$",
+ "Flag informando se a conversão foi completada (1: sim, 0: não), quando $op$ == $PLATFORM_ADC_IS_DONE$. Também retorna 1 se nenhuma conversão foi solicitada.",
+ "A frequência real de conversão que sera usada, quando $op$ == $PLATFORM_ADC_OP_SET_CLOCK$",
+ "Indefinido para outras operações."
+ }
+ },
+
+ { sig = "int #platform_adc_check_timer_id#( unsigned id, unsigned timer_id );",
+ desc = "Checa see um Timer pode ser usado com um ADC especÃfico",
+ args =
+ {
+ "$id$ - ADC ID",
+ "$timer_id$ - Timer ID",
+ },
+ ret = "1 se o Timer pode ser usado para trigar um ADC. 0 em caso contrário",
+ }
+ }
+}
+
Added: branches/eagle_mmc/doc/eluadoc/arch_platform_cpu.lua
===================================================================
--- branches/eagle_mmc/doc/eluadoc/arch_platform_cpu.lua 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/eluadoc/arch_platform_cpu.lua 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,59 @@
+-- eLua platform interface - CPU
+
+data_en =
+{
+ -- Title
+ title = "eLua platform interface - CPU",
+
+ -- Menu name
+ menu_name = "CPU",
+
+ -- Overview
+ overview = "This part of the platform interface groups functions related to the CPU and its functional modules (interrupt controller, memory controller and others).",
+
+ -- Functions
+ funcs =
+ {
+ { sig = "void #platform_cpu_enable_interrupts#();",
+ desc = "Enable global interrupt on the CPU."
+ },
+
+ { sig = "void #platform_cpu_disable_interrupts#();",
+ desc = "Disable global interrupts on the CPU."
+ },
+
+ { sig = "u32 #platform_cpu_get_frequency#();",
+ desc = "Get the CPU frequency.",
+ ret = "the CPU $core$ frequency (in Hertz)."
+ },
+ }
+}
+
+data_pt =
+{
+ -- Title
+ title = "eLua platform interface - CPU",
+
+ -- Menu name
+ menu_name = "CPU",
+
+ -- Overview
+ overview = "This part of the platform interface groups functions related to the CPU and its functional modules (interrupt controller, memory controller and others).",
+
+ -- Functions
+ funcs =
+ {
+ { sig = "void #platform_cpu_enable_interrupts#();",
+ desc = "Enable global interrupt on the CPU."
+ },
+
+ { sig = "void #platform_cpu_disable_interrupts#();",
+ desc = "Disable global interrupts on the CPU."
+ },
+
+ { sig = "u32 #platform_cpu_get_frequency#();",
+ desc = "Get the CPU frequency.",
+ ret = "the CPU $core$ frequency (in Hertz)."
+ },
+ }
+}
Added: branches/eagle_mmc/doc/eluadoc/arch_platform_eth.lua
===================================================================
--- branches/eagle_mmc/doc/eluadoc/arch_platform_eth.lua 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/eluadoc/arch_platform_eth.lua 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,189 @@
+-- eLua platform interface - Ethernet support
+
+data_en =
+{
+ -- Title
+ title = "eLua platform interface - Ethernet support",
+
+ -- Menu name
+ menu_name = "Ethernet",
+
+ -- Overview
+ overview = [[<span style="color: red;">$NOTE$: TCP/IP support is experimental in eLua. Although functional, it's quite incomplete at the moment.</span></p>
+ <p>This part of the platform interface groups functions related to accessing the Ethernet interface (internal or external) of the CPU. Note that unlike the
+ other parts of the platform interface this one is dedicated for TCP/IP support and thus it does not correspond directly to an eLua module, although
+ the @refman_gen_net.html at net module@ is implemented with functions that rely on this part of the platform interface. Currently only
+ the ^http://www.sics.se/~~adam/uip/index.php/Main_Page^uIP^ TCP/IP stack is supported by eLua.</p>
+ <p>uIP is implemented in eLua using two hardware interrupts (that should be available on your platform): the Ethernet receive interrupt (to handle
+ incoming packets) and a timer interrupt (timers are used internally by uIP). However, the uIP main loop is only called from the Ethernet interrupt handler
+ in eLua, so in order to acknowledge the timer interrupt (as well as to provide some optimizations) a function that "forces" an Ethernet interrupt
+ must also be provided by the platform interface (see @#platform_eth_force_interrupt at here@ for details).</p>
+ <p>To put everything together, part of the Ethernet platform interface for the $lm3s$ platform is given below:</p>
+ ~u32 platform_eth_get_elapsed_time()
+ {
+ if( eth_timer_fired )
+ {
+ eth_timer_fired = 0;
+ return SYSTICKMS;
+ }
+ else
+ return 0;
+ }
+
+ void SysTickIntHandler()
+ {
+ // Handle virtual timers
+ cmn_virtual_timer_cb();
+
+ // Indicate that a SysTick interrupt has occurred.
+ eth_timer_fired = 1;
+
+ // Generate a fake Ethernet interrupt. This will perform the actual work
+ // of incrementing the timers and taking the appropriate actions.
+ <b>platform_eth_force_interrupt();</b>
+ }
+
+ void EthernetIntHandler()
+ {
+ u32 temp;
+
+ // Read and Clear the interrupt.
+ temp = EthernetIntStatus( ETH_BASE, false );
+ EthernetIntClear( ETH_BASE, temp );
+
+ // Call the UIP main loop
+ <b>elua_uip_mainloop();</b>
+ }~<p>]],
+
+ -- Functions
+ funcs =
+ {
+ { sig = "void #platform_eth_send_packet#( const void* src, u32 size )",
+ desc = "Sends an Ethernet packet to the network",
+ args =
+ {
+ "$src$ - start address of the Ethernet packet",
+ "$size$ - size of the Ethernet packet"
+ },
+ },
+
+ { sig = "u32 #platform_eth_get_packet_nb#( void* buf, u32 maxlen );",
+ desc = "Non-blocking read of an Ethernet packet from the network",
+ args =
+ {
+ "$buf$ - start address of the receive buffer",
+ "$maxlen$ - maximum length of the Ethernet packet",
+ },
+ ret = "the size of the read packet or 0 if no packet is available"
+ },
+
+ { sig = "void #platform_eth_force_interrupt#();",
+ desc = "Force the Ethernet interrupt on the platform (see @#overview at overview@ above for details)",
+ },
+
+ { sig = "u32 #platform_eth_get_elapsed_time#();",
+ desc = [[Get the elapsed time (in ms) since the last invocation of the uIP main loop ($elua_uip_mainloop$, from which this function is called). See @#overview at overview@ for a possible
+ implementation of this function).]],
+ ret =
+ {
+ "0 if the uIP loop was called because of Ethernet activity, not because a timer expired",
+ "the Ethernet timer perios in ms (which indicates timer activity)"
+ },
+ }
+ }
+}
+
+
+data_pt =
+{
+ -- Title
+ title = "eLua platform interface - Ethernet support",
+
+ -- Menu name
+ menu_name = "Ethernet",
+
+ -- Overview
+ overview = [[<span style="color: red;">$NOTE$: TCP/IP support is experimental in eLua. Although functional, it's quite incomplete at the moment.</span></p>
+ <p>This part of the platform interface groups functions related to accessing the Ethernet interface (internal or external) of the CPU. Note that unlike the
+ other parts of the platform interface this one is dedicated for TCP/IP support and thus it does not correspond directly to an eLua module, although
+ the @refman_gen_net.html at net module@ is implemented with functions that rely on this part of the platform interface. Currently only
+ the ^http://www.sics.se/~~adam/uip/index.php/Main_Page^uIP^ TCP/IP stack is supported by eLua.</p>
+ <p>uIP is implemented in eLua using two hardware interrupts (that should be available on your platform): the Ethernet receive interrupt (to handle
+ incoming packets) and a timer interrupt (timers are used internally by uIP). However, the uIP main loop is only called from the Ethernet interrupt handler
+ in eLua, so in order to acknowledge the timer interrupt (as well as to provide some optimizations) a function that "forces" an Ethernet interrupt
+ must also be provided by the platform interface (see @#platform_eth_force_interrupt at here@ for details).</p>
+ <p>To put everything together, part of the Ethernet platform interface for the $lm3s$ platform is given below:</p>
+ ~u32 platform_eth_get_elapsed_time()
+ {
+ if( eth_timer_fired )
+ {
+ eth_timer_fired = 0;
+ return SYSTICKMS;
+ }
+ else
+ return 0;
+ }
+
+ void SysTickIntHandler()
+ {
+ // Handle virtual timers
+ cmn_virtual_timer_cb();
+
+ // Indicate that a SysTick interrupt has occurred.
+ eth_timer_fired = 1;
+
+ // Generate a fake Ethernet interrupt. This will perform the actual work
+ // of incrementing the timers and taking the appropriate actions.
+ <b>platform_eth_force_interrupt();</b>
+ }
+
+ void EthernetIntHandler()
+ {
+ u32 temp;
+
+ // Read and Clear the interrupt.
+ temp = EthernetIntStatus( ETH_BASE, false );
+ EthernetIntClear( ETH_BASE, temp );
+
+ // Call the UIP main loop
+ <b>elua_uip_mainloop();</b>
+ }~<p>]],
+
+ -- Functions
+ funcs =
+ {
+ { sig = "void #platform_eth_send_packet#( const void* src, u32 size )",
+ desc = "Sends an Ethernet packet to the network",
+ args =
+ {
+ "$src$ - start address of the Ethernet packet",
+ "$size$ - size of the Ethernet packet"
+ },
+ },
+
+ { sig = "u32 #platform_eth_get_packet_nb#( void* buf, u32 maxlen );",
+ desc = "Non-blocking read of an Ethernet packet from the network",
+ args =
+ {
+ "$buf$ - start address of the receive buffer",
+ "$maxlen$ - maximum length of the Ethernet packet",
+ },
+ ret = "the size of the read packet or 0 if no packet is available"
+ },
+
+ { sig = "void #platform_eth_force_interrupt#();",
+ desc = "Force the Ethernet interrupt on the platform (see @#overview at overview@ above for details)",
+ },
+
+ { sig = "u32 #platform_eth_get_elapsed_time#();",
+ desc = [[Get the elapsed time (in ms) since the last invocation of the uIP main loop ($elua_uip_mainloop$, from which this function is called). See @#overview at overview@ for a possible
+ implementation of this function).]],
+ ret =
+ {
+ "0 if the uIP loop was called because of Ethernet activity, not because a timer expired",
+ "the Ethernet timer perios in ms (which indicates timer activity)"
+ },
+ }
+ }
+}
+
Added: branches/eagle_mmc/doc/eluadoc/arch_platform_ll.lua
===================================================================
--- branches/eagle_mmc/doc/eluadoc/arch_platform_ll.lua 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/eluadoc/arch_platform_ll.lua 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,170 @@
+-- eLua platform interface - low level functions
+
+data_en =
+{
+ -- Title
+ title = "eLua platform interface - low level functions",
+
+ -- Menu title
+ menu_name = "Low-level",
+
+ -- Overview
+ overview = [[
+ This part of the platform interface deals contains a small set of "low level functions" that are used to "couple" the eLua port with the
+ target system. No eLua module exposes these functions, as they are strictly used for porting and do not provide any other functionality.
+ ]],
+
+ -- Data structures, constants and types
+ structures =
+ {
+ { text = [[// Error / status codes
+enum
+{
+ PLATFORM_ERR,
+ PLATFORM_OK,
+ PLATFORM_UNDERFLOW = -1
+};]],
+ name = "Status codes",
+ desc = [[
+ This enum defines the possible return values of the @#platform_init at platform_init@ function (although only $PLATFORM_ERR$ and $PLATFORM_OK$ should be
+ returned from $platform_init$).
+ ]]
+ },
+ },
+
+ -- Functions
+ funcs =
+ {
+ { sig = "int #platform_init#();",
+ desc = [[This is the platform-specific initialization code. It is the first function called from %main()% ($src/main.c$) and it should handle
+ all the platform initialization sequence, included (but not limited to) setting up the proper clocks, initializing the interrupt subsystem,
+ setting up various peripherals and so on. Although platform specific, this function has a common part named %cmn_platform_init% (implemented
+ in $src/common.c$) that initializes terminal support over serial connections, as well as the XMODEM and TERM components
+ (see @building.html at here@ for details). If you need any of these, you need to call %cmn_platform_init% at the end of your
+ %platform_init% function, $after$ initializing all the peripherals (in particular the UART used for the serial connection).<br>
+ An implementation skeleton for this function is given below:</p>
+ ~int platform_init()
+ {
+ ............. // perform all your initializations here
+ cmn_platform_init(); // call the common initialiation code
+ return PLATFORM_OK;
+ }~<p>]],
+ ret =
+ {
+ "$PLATFORM_OK$ for success",
+ [[$PLATFORM_ERR$ if an error occured. If $PLATFORM_ERR$ is returned, %main% will block in an infinite loop right
+ after calling this function, so you should return $PLATFORM_ERR$ only for serious errors]],
+ },
+ },
+
+ { sig = "void* #platform_get_last_free_ram#( unsigned id );",
+ desc = [[Returns the start address of a free RAM area in the system (this is the RAM that will be used by any part of the code that uses malloc(),
+ a good example being the Lua interpreter itself). There can be multiple free RAM areas in the system (for example the internal MCU RAM and external
+ RAM chips). Implemented in $src/common.c$, it uses the the $MEM_START_ADDRESS$ macro that must be defined in the platform's $platform_conf.h$
+ file (see @arch_overview.html#platforms at here@ for details). This macro must be defined as an array that contains all the start addresses of
+ free RAM in the system. For internal RAM, this is generally handled by a linker exported symbol (named $end$ in many eLua ports) which
+ points to the firs RAM address after all the constant and non-constant program data. An example is given below:</p>
+ ~#define MEM_START_ADDRESS { ( void* )end }~<p>]],
+ args = "$id$ - the identifier of the RAM area",
+ ret = "the start address of the given memory area",
+ },
+
+ { sig = "void* #platform_get_last_free_ram#( unsigned id );",
+ desc = [[Returns the last address of a free RAM area in the system (this is the RAM that will be used by any part of the code that uses malloc(),
+ a good example being the Lua interpreter itself). There can be multiple free RAM areas in the system (for example the internal MCU RAM and external
+ RAM chips). Implemented in $src/common.c$, it uses the the $MEM_END_ADDRESS$ macro that must be defined in the platform's $platform_conf.h$
+ file (see @arch_overview.html#platforms at here@ for details). This macro must be defined as an array that contains all the end addresses of
+ free RAM in the system. For internal RAM, this is generally set as the last RAM memory address minus the size of the system stack(s). An example is
+ given below:</p>
+ ~#define MEM_END_ADDRESS { ( void* )( SRAM_BASE + 0x10000 - STACK_SIZE_TOTAL - 1 ) }~<p>]],
+ args = "$id$ - the identifier of the RAM area",
+ ret = "the end address of the given memory area",
+ },
+
+ }
+}
+
+data_pt =
+{
+ -- Title
+ title = "eLua platform interface - low level functions",
+
+ -- Menu title
+ menu_name = "Low-level",
+
+ -- Overview
+ overview = [[
+ This part of the platform interface deals contains a small set of "low level functions" that are used to "couple" the eLua port with the
+ target system. No eLua module exposes these functions, as they are strictly used for porting and do not provide any other functionality.
+ ]],
+
+ -- Data structures, constants and types
+ structures =
+ {
+ { text = [[// Error / status codes
+enum
+{
+ PLATFORM_ERR,
+ PLATFORM_OK,
+ PLATFORM_UNDERFLOW = -1
+};]],
+ name = "Status codes",
+ desc = [[
+ This enum defines the possible return values of the @#platform_init at platform_init@ function (although only $PLATFORM_ERR$ and $PLATFORM_OK$ should be
+ returned from $platform_init$).
+ ]]
+ },
+ },
+
+ -- Functions
+ funcs =
+ {
+ { sig = "int #platform_init#();",
+ desc = [[This is the platform-specific initialization code. It is the first function called from %main()% ($src/main.c$) and it should handle
+ all the platform initialization sequence, included (but not limited to) setting up the proper clocks, initializing the interrupt subsystem,
+ setting up various peripherals and so on. Although platform specific, this function has a common part named %cmn_platform_init% (implemented
+ in $src/common.c$) that initializes terminal support over serial connections, as well as the XMODEM and TERM components
+ (see @building.html at here@ for details). If you need any of these, you need to call %cmn_platform_init% at the end of your
+ %platform_init% function, $after$ initializing all the peripherals (in particular the UART used for the serial connection).<br>
+ An implementation skeleton for this function is given below:</p>
+ ~int platform_init()
+ {
+ ............. // perform all your initializations here
+ cmn_platform_init(); // call the common initialiation code
+ return PLATFORM_OK;
+ }~<p>]],
+ ret =
+ {
+ "$PLATFORM_OK$ for success",
+ [[$PLATFORM_ERR$ if an error occured. If $PLATFORM_ERR$ is returned, %main% will block in an infinite loop right
+ after calling this function, so you should return $PLATFORM_ERR$ only for serious errors]],
+ },
+ },
+
+ { sig = "void* #platform_get_last_free_ram#( unsigned id );",
+ desc = [[Returns the start address of a free RAM area in the system (this is the RAM that will be used by any part of the code that uses malloc(),
+ a good example being the Lua interpreter itself). There can be multiple free RAM areas in the system (for example the internal MCU RAM and external
+ RAM chips). Implemented in $src/common.c$, it uses the the $MEM_START_ADDRESS$ macro that must be defined in the platform's $platform_conf.h$
+ file (see @arch_overview.html#platforms at here@ for details). This macro must be defined as an array that contains all the start addresses of
+ free RAM in the system. For internal RAM, this is generally handled by a linker exported symbol (named $end$ in many eLua ports) which
+ points to the firs RAM address after all the constant and non-constant program data. An example is given below:</p>
+ ~#define MEM_START_ADDRESS { ( void* )end }~<p>]],
+ args = "$id$ - the identifier of the RAM area",
+ ret = "the start address of the given memory area",
+ },
+
+ { sig = "void* #platform_get_last_free_ram#( unsigned id );",
+ desc = [[Returns the last address of a free RAM area in the system (this is the RAM that will be used by any part of the code that uses malloc(),
+ a good example being the Lua interpreter itself). There can be multiple free RAM areas in the system (for example the internal MCU RAM and external
+ RAM chips). Implemented in $src/common.c$, it uses the the $MEM_END_ADDRESS$ macro that must be defined in the platform's $platform_conf.h$
+ file (see @arch_overview.html#platforms at here@ for details). This macro must be defined as an array that contains all the end addresses of
+ free RAM in the system. For internal RAM, this is generally set as the last RAM memory address minus the size of the system stack(s). An example is
+ given below:</p>
+ ~#define MEM_END_ADDRESS { ( void* )( SRAM_BASE + 0x10000 - STACK_SIZE_TOTAL - 1 ) }~<p>]],
+ args = "$id$ - the identifier of the RAM area",
+ ret = "the end address of the given memory area",
+ },
+
+ }
+}
+
Added: branches/eagle_mmc/doc/eluadoc/arch_platform_pio.lua
===================================================================
--- branches/eagle_mmc/doc/eluadoc/arch_platform_pio.lua 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/eluadoc/arch_platform_pio.lua 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,213 @@
+-- eLua platform interface - PIO
+
+data_en =
+{
+ -- Title
+ title = "eLua platform interface - PIO",
+
+ -- Menu name
+ menu_name = "PIO",
+
+ -- OverviewA
+ overview = "This part of the platform interface deals with PIO (Programmable Input Output) operations, thus letting the user access the low level input/output facilities of the host MCU.",
+
+ -- Data structures, constants and types
+ structures =
+ {
+ { text = [[enum
+{
+ // Pin operations
+ PLATFORM_IO_PIN_SET, $// Set the pin to 1$
+ PLATFORM_IO_PIN_CLEAR, $// Clear the pin (set it to 0)$
+ PLATFORM_IO_PIN_GET, $// Get the value of the pin$
+ PLATFORM_IO_PIN_DIR_INPUT, $// Make the pin an input$
+ PLATFORM_IO_PIN_DIR_OUTPUT, $// Make the pin an output$
+ PLATFORM_IO_PIN_PULLUP, $// Activate the pullup on the pin$
+ PLATFORM_IO_PIN_PULLDOWN, $// Activate the pulldown on the pin$
+ PLATFORM_IO_PIN_NOPULL, $// Disable all pullups/pulldowns on the pin$
+ // Port operations
+ PLATFORM_IO_PORT_SET_VALUE, $// Set port value$
+ PLATFORM_IO_PORT_GET_VALUE, $// Get port value$
+ PLATFORM_IO_PORT_DIR_INPUT, $// Set port as input$
+ PLATFORM_IO_PORT_DIR_OUTPUT $// Set port as output$
+}; ]],
+ name = "PIO operations",
+ desc = [[These are the operations that can be executed by the PIO subsystem on both ports and pins. They are given as arguments to the @#platform_pio_op at platform_pio_op@ function
+ shown below.]]
+ },
+
+ { text = "typedef u32 pio_type;",
+ name = "PIO data type",
+ desc = [[This is the type used for the actual I/O operations. Currently defined as an unsigned 32-bit type, thus no port can have more than 32 pins. If this happens, it is possible to split
+ it in two or more parts and adding the new parts as "virtual ports" (logical ports that don't have a direct hardware equivalent). The "virtual port" technique is used in the AVR32 backend.]]
+ }
+ },
+
+ -- Functions
+ funcs =
+ {
+ { sig = "int #platform_pio_has_port#( unsigned port );",
+ desc = [[Checks if the platform has the hardware port specified as argument. Implemented in %src/common.c%, it uses the $NUM_PIO$ macro that must be defined in the
+ platform's $platform_conf.h$ file (see @arch_overview.html#platforms at here@ for details). For example:</p>
+ ~#define NUM_PIO 4 $// The platform has 4 hardware PIO ports$~<p> ]],
+ args = "$port$ - the port ID",
+ ret = "1 if the port exists, 0 otherwise",
+ },
+
+ { sig = "int #platform_pio_has_pin#( unsigned port, unsigned pin );",
+ desc = [[Checks if the platform has the hardware port and pin specified as arguments. Implemented in %src/common.c%, it uses the $NUM_PIO$ macro to check the validity
+ of the port and the $PIO_PINS_PER_PORT$ or $PIO_PIN_ARRAY$ macros to check the validity of the pin. The macros must be defined in the platform's $platform_conf.h$ file
+ (see @arch_overview.html#platforms at here@ for details).</p>
+ <ul>
+ <li>use $PIO_PINS_PER_PORT$ when all the ports of the MCU have the same number of pins. For example:
+ ~#define PIO_PINS_PER_PORT 8 $// Each port has 8 pins$~</li>
+ <li>use $PIO_PIN_ARRAY$ when different ports of the MCU have different number of pins. For example:
+ ~#define PIO_PIN_ARRAY { 4, 4, 2, 6 } $// Port 0 has 4 pins, port 1 has 4 pins, port 2 has 2 pins, port 3 has 6 pins$~</li>
+ </ul><p>]],
+ args =
+ {
+ "$port$ - the port ID",
+ "$pin$ - the pin number"
+ },
+ ret = "1 if the pin exists, 0 otherwise",
+ },
+
+ { sig = "const char* #platform_pio_get_prefix#( unsigned port );",
+ desc = [[Get the port prefix. Used to establish if the port notation uses numbers (P0, P1, P2...) or letters (PA, PB, PC...). Implemented in %src/common.c%, it uses the
+ $PIO_PREFIX$ macro that must be defined in the platform's $platform_conf.h$ file (see @arch_overview.html#platforms at here@ for details). The value of this macro can be either '0' (for
+ numeric notation) or 'A' (for letter notation). For example:</p>
+ ~#define PIO_PREFIX 'A' $// Use PA, PB, PC ... for port notation$~<p>]],
+ args = "$port$ - the port ID",
+ ret = "the port prefix (either '0' or 'A')",
+ },
+
+ { sig = "pio_type #platform_pio_op#( unsigned port, pio_type pinmask, int op );",
+ link = "platform_pio_op",
+ desc = "This is the function that does the actual I/O work. It is implemented in the platform's own porting layer (%platform.c%, see @arch_overview.html#ports at here@ for more details).",
+ args =
+ {
+ "$port$ - the port number",
+ [[$pinmask$ - has different meanings:
+ <ul>
+ <li>for $pin operations$ it is the mask of pins in the operation. Each pin on which the function action is executed is encoded with an 1 in the corresponding bit position
+ of the pinmask.</li>
+ <li>for $port operations$ it is only meaningful for $PLATFORM_IO_PORT_SET_VALUE$ and in this case it specifies the new value of the port.</li>
+ </ul>]],
+ "$op$ - specifies the I/O operations, as specified @#pio_operations at here@."
+ },
+ ret =
+ {
+ "an actual value for $PLATFORM_IO_PIN_GET$ (0 or 1) and $PLATFORM_IO_PORT_GET$ (the value of the port).",
+ [[an error flag for all the other operations: 1 if the operation succeeded, 0 otherwise. For example, a platform that doesn't have pulldowns on its ports will always return a 0
+ when caled with the $PLATFORM_IO_PIN_PULLDOWN$ operation.]]
+ }
+ },
+ }
+}
+
+
+data_pt =
+{
+ -- Title
+ title = "eLua platform interface - PIO",
+
+ -- Menu name
+ menu_name = "PIO",
+
+ -- OverviewA
+ overview = "This part of the platform interface deals with PIO (Programmable Input Output) operations, thus letting the user access the low level input/output facilities of the host MCU.",
+
+ -- Data structures, constants and types
+ structures =
+ {
+ { text = [[enum
+{
+ // Pin operations
+ PLATFORM_IO_PIN_SET, $// Set the pin to 1$
+ PLATFORM_IO_PIN_CLEAR, $// Clear the pin (set it to 0)$
+ PLATFORM_IO_PIN_GET, $// Get the value of the pin$
+ PLATFORM_IO_PIN_DIR_INPUT, $// Make the pin an input$
+ PLATFORM_IO_PIN_DIR_OUTPUT, $// Make the pin an output$
+ PLATFORM_IO_PIN_PULLUP, $// Activate the pullup on the pin$
+ PLATFORM_IO_PIN_PULLDOWN, $// Activate the pulldown on the pin$
+ PLATFORM_IO_PIN_NOPULL, $// Disable all pullups/pulldowns on the pin$
+ // Port operations
+ PLATFORM_IO_PORT_SET_VALUE, $// Set port value$
+ PLATFORM_IO_PORT_GET_VALUE, $// Get port value$
+ PLATFORM_IO_PORT_DIR_INPUT, $// Set port as input$
+ PLATFORM_IO_PORT_DIR_OUTPUT $// Set port as output$
+}; ]],
+ name = "PIO operations",
+ desc = [[These are the operations that can be executed by the PIO subsystem on both ports and pins. They are given as arguments to the @#platform_pio_op at platform_pio_op@ function
+ shown below.]]
+ },
+
+ { text = "typedef u32 pio_type;",
+ name = "PIO data type",
+ desc = [[This is the type used for the actual I/O operations. Currently defined as an unsigned 32-bit type, thus no port can have more than 32 pins. If this happens, it is possible to split
+ it in two or more parts and adding the new parts as "virtual ports" (logical ports that don't have a direct hardware equivalent). The "virtual port" technique is used in the AVR32 backend.]]
+ }
+ },
+
+ -- Functions
+ funcs =
+ {
+ { sig = "int #platform_pio_has_port#( unsigned port );",
+ desc = [[Checks if the platform has the hardware port specified as argument. Implemented in %src/common.c%, it uses the $NUM_PIO$ macro that must be defined in the
+ platform's $platform_conf.h$ file (see @arch_overview.html#platforms at here@ for details). For example:</p>
+ ~#define NUM_PIO 4 $// The platform has 4 hardware PIO ports$~<p> ]],
+ args = "$port$ - the port ID",
+ ret = "1 if the port exists, 0 otherwise",
+ },
+
+ { sig = "int #platform_pio_has_pin#( unsigned port, unsigned pin );",
+ desc = [[Checks if the platform has the hardware port and pin specified as arguments. Implemented in %src/common.c%, it uses the $NUM_PIO$ macro to check the validity
+ of the port and the $PIO_PINS_PER_PORT$ or $PIO_PIN_ARRAY$ macros to check the validity of the pin. The macros must be defined in the platform's $platform_conf.h$ file
+ (see @arch_overview.html#platforms at here@ for details).</p>
+ <ul>
+ <li>use $PIO_PINS_PER_PORT$ when all the ports of the MCU have the same number of pins. For example:
+ ~#define PIO_PINS_PER_PORT 8 $// Each port has 8 pins$~</li>
+ <li>use $PIO_PIN_ARRAY$ when different ports of the MCU have different number of pins. For example:
+ ~#define PIO_PIN_ARRAY { 4, 4, 2, 6 } $// Port 0 has 4 pins, port 1 has 4 pins, port 2 has 2 pins, port 3 has 6 pins$~</li>
+ </ul><p>]],
+ args =
+ {
+ "$port$ - the port ID",
+ "$pin$ - the pin number"
+ },
+ ret = "1 if the pin exists, 0 otherwise",
+ },
+
+ { sig = "const char* #platform_pio_get_prefix#( unsigned port );",
+ desc = [[Get the port prefix. Used to establish if the port notation uses numbers (P0, P1, P2...) or letters (PA, PB, PC...). Implemented in %src/common.c%, it uses the
+ $PIO_PREFIX$ macro that must be defined in the platform's $platform_conf.h$ file (see @arch_overview.html#platforms at here@ for details). The value of this macro can be either '0' (for
+ numeric notation) or 'A' (for letter notation). For example:</p>
+ ~#define PIO_PREFIX 'A' $// Use PA, PB, PC ... for port notation$~<p>]],
+ args = "$port$ - the port ID",
+ ret = "the port prefix (either '0' or 'A')",
+ },
+
+ { sig = "pio_type #platform_pio_op#( unsigned port, pio_type pinmask, int op );",
+ link = "platform_pio_op",
+ desc = "This is the function that does the actual I/O work. It is implemented in the platform's own porting layer (%platform.c%, see @arch_overview.html#ports at here@ for more details).",
+ args =
+ {
+ "$port$ - the port number",
+ [[$pinmask$ - has different meanings:
+ <ul>
+ <li>for $pin operations$ it is the mask of pins in the operation. Each pin on which the function action is executed is encoded with an 1 in the corresponding bit position
+ of the pinmask.</li>
+ <li>for $port operations$ it is only meaningful for $PLATFORM_IO_PORT_SET_VALUE$ and in this case it specifies the new value of the port.</li>
+ </ul>]],
+ "$op$ - specifies the I/O operations, as specified @#pio_operations at here@."
+ },
+ ret =
+ {
+ "an actual value for $PLATFORM_IO_PIN_GET$ (0 or 1) and $PLATFORM_IO_PORT_GET$ (the value of the port).",
+ [[an error flag for all the other operations: 1 if the operation succeeded, 0 otherwise. For example, a platform that doesn't have pulldowns on its ports will always return a 0
+ when caled with the $PLATFORM_IO_PIN_PULLDOWN$ operation.]]
+ }
+ },
+ }
+}
+
Added: branches/eagle_mmc/doc/eluadoc/arch_platform_pwm.lua
===================================================================
--- branches/eagle_mmc/doc/eluadoc/arch_platform_pwm.lua 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/eluadoc/arch_platform_pwm.lua 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,150 @@
+-- eLua platform interface - PWM
+
+data_en =
+{
+ -- Title
+ title = "eLua platform interface - PWM",
+
+ -- Menu name
+ menu_name = "PWM",
+
+ -- Overview
+ overview = "This part of the platform interface groups functions related to the PWM channel(s) of the MCU.",
+
+ -- Data structures, constants and types
+ structures =
+ {
+ { text = [[// PWM operations
+enum
+{
+ PLATFORM_PWM_OP_START,
+ PLATFORM_PWM_OP_STOP,
+ PLATFORM_PWM_OP_SET_CLOCK,
+ PLATFORM_PWM_OP_GET_CLOCK
+} ]],
+ name = "PWM operations",
+ desc = "This enum lists all the operations that can be executed on a given PWM channel."
+ },
+ },
+
+ -- Functions
+ funcs =
+ {
+ { sig = "int #platform_pwm_exists#( unsigned id );",
+ desc = [[Checks if the platform has the PWM channel specified as argument. Implemented in %src/common.c%, it uses the $NUM_PWM$ macro that must be defined in the
+ platform's $platform_conf.h$ file (see @arch_overview.html#platforms at here@ for details). For example:</p>
+ ~#define NUM_PWM 4 $// The platform has 4 PWM channels$~<p> ]],
+ args = "$id$ - PWM channel ID",
+ ret = "1 if the specified PWM channel exists, 0 otherwise"
+ },
+
+ { sig = "u32 #platform_pwm_setup#( unsigned id, u32 frequency, unsigned duty );",
+ desc = "Sets up a PWM channel",
+ args =
+ {
+ "$id$ - PWM channel ID",
+ "$frequency$ - PWM channel frequency (in hertz)",
+ "$duty$ - PWM channel duty cycle, specified as percent (from 0 to 100). Note that some platform don't allow the full 0%-100% duty cycle"
+ },
+ ret = "The actual frequency set on the PWM channel, which might differ from the $frequency$ parameter, depeding on the hardware",
+ },
+
+ { sig = "u32 #platform_pwm_op#( unsigned id, int op, u32 data );",
+ desc = "Executes an operation on a PWM channel",
+ args =
+ {
+ "$id$ - PWM channel ID",
+ [[$op$ - the operation that must be executed. It can take any value from @#pwm_operations at this enum@, as follows:
+ <ul>
+ <li>$PLATFORM_PWM_OP_START$: starts PWM generation on the specified channel.</li>
+ <li>$PLATFORM_PWM_OP_STOP$: stops PWM generation on the specified channel.</li>
+ <li>$PLATFORM_PWM_OP_SET_CLOCK$: sets the $base$ clock of the specified PWM channel (which will be used to generate the frequencies requested by
+ @#platform_pwm_setup at platform_pwm_setup@) to $data$ hertz.</li>
+ <li>$PLATFORM_PWM_OP_GET_CLOCK$: get the $base$ clock of the specified PWM channel.</li>
+ </ul>]],
+ "$data$ - when used with $op$ == $PLATFORM_PWM_OP_SET_CLOCK$ it is used to specify the value of the base clock. Not used with other operations."
+ },
+ ret =
+ {
+ "the actual value of the base clock when $op$ == $PLATFORM_PWM_OP_SET_CLOCK$, which might be different than $data$ depending on the hardware",
+ "the value of the base clock when $op$ == $PLATFORM_PWM_OP_GET_CLOCK$",
+ "irellevant for other operations"
+ }
+ }
+ }
+}
+
+data_pt =
+{
+ -- Title
+ title = "eLua platform interface - PWM",
+
+ -- Menu name
+ menu_name = "PWM",
+
+ -- Overview
+ overview = "This part of the platform interface groups functions related to the PWM channel(s) of the MCU.",
+
+ -- Data structures, constants and types
+ structures =
+ {
+ { text = [[// PWM operations
+enum
+{
+ PLATFORM_PWM_OP_START,
+ PLATFORM_PWM_OP_STOP,
+ PLATFORM_PWM_OP_SET_CLOCK,
+ PLATFORM_PWM_OP_GET_CLOCK
+} ]],
+ name = "PWM operations",
+ desc = "This enum lists all the operations that can be executed on a given PWM channel."
+ },
+ },
+
+ -- Functions
+ funcs =
+ {
+ { sig = "int #platform_pwm_exists#( unsigned id );",
+ desc = [[Checks if the platform has the PWM channel specified as argument. Implemented in %src/common.c%, it uses the $NUM_PWM$ macro that must be defined in the
+ platform's $platform_conf.h$ file (see @arch_overview.html#platforms at here@ for details). For example:</p>
+ ~#define NUM_PWM 4 $// The platform has 4 PWM channels$~<p> ]],
+ args = "$id$ - PWM channel ID",
+ ret = "1 if the specified PWM channel exists, 0 otherwise"
+ },
+
+ { sig = "u32 #platform_pwm_setup#( unsigned id, u32 frequency, unsigned duty );",
+ desc = "Sets up a PWM channel",
+ args =
+ {
+ "$id$ - PWM channel ID",
+ "$frequency$ - PWM channel frequency (in hertz)",
+ "$duty$ - PWM channel duty cycle, specified as percent (from 0 to 100). Note that some platform don't allow the full 0%-100% duty cycle"
+ },
+ ret = "The actual frequency set on the PWM channel, which might differ from the $frequency$ parameter, depeding on the hardware",
+ },
+
+ { sig = "u32 #platform_pwm_op#( unsigned id, int op, u32 data );",
+ desc = "Executes an operation on a PWM channel",
+ args =
+ {
+ "$id$ - PWM channel ID",
+ [[$op$ - the operation that must be executed. It can take any value from @#pwm_operations at this enum@, as follows:
+ <ul>
+ <li>$PLATFORM_PWM_OP_START$: starts PWM generation on the specified channel.</li>
+ <li>$PLATFORM_PWM_OP_STOP$: stops PWM generation on the specified channel.</li>
+ <li>$PLATFORM_PWM_OP_SET_CLOCK$: sets the $base$ clock of the specified PWM channel (which will be used to generate the frequencies requested by
+ @#platform_pwm_setup at platform_pwm_setup@) to $data$ hertz.</li>
+ <li>$PLATFORM_PWM_OP_GET_CLOCK$: get the $base$ clock of the specified PWM channel.</li>
+ </ul>]],
+ "$data$ - when used with $op$ == $PLATFORM_PWM_OP_SET_CLOCK$ it is used to specify the value of the base clock. Not used with other operations."
+ },
+ ret =
+ {
+ "the actual value of the base clock when $op$ == $PLATFORM_PWM_OP_SET_CLOCK$, which might be different than $data$ depending on the hardware",
+ "the value of the base clock when $op$ == $PLATFORM_PWM_OP_GET_CLOCK$",
+ "irellevant for other operations"
+ }
+ }
+ }
+}
+
Added: branches/eagle_mmc/doc/eluadoc/arch_platform_spi.lua
===================================================================
--- branches/eagle_mmc/doc/eluadoc/arch_platform_spi.lua 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/eluadoc/arch_platform_spi.lua 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,165 @@
+-- eLua platform interface - SPI
+-- Make a full description for each language
+
+data_en =
+{
+ -- Menu name
+ menu_name = "SPI",
+
+ -- Title
+ title = "eLua platform interface - SPI",
+
+ -- Overview
+ overview = "This part of the platform interface groups functions related to the SPI interface(s) of the MCU.",
+
+ -- Data structures, constants and types
+ structures =
+ {
+ { text = [[// SPI mode
+#define PLATFORM_SPI_MASTER 1
+#define PLATFORM_SPI_SLAVE 0 ]],
+ name = "Chip select",
+ desc = "Constants used to select/deselect the SPI SS pin (if applicable)."
+ },
+
+ { text = [[// SS values
+#define PLATFORM_SPI_SELECT_ON 1
+#define PLATFORM_SPI_SELECT_OFF 0]],
+ name = "SPI mode",
+ desc = "Constants used to select/deselect the SPI SS pin (if applicable)."
+ },
+
+ { text = "typedef u32 spi_data_type;",
+ name = "SPI data type",
+ desc = "This is the type of a SPI data word, thus limiting the maximum size of a SPI data work to 32 bits (which should be enough for all practical purposes)."
+ }
+ },
+
+ -- Functions
+ funcs =
+ {
+ { sig = "int #platform_spi_exists#( unsigned id );",
+ desc = [[Checks if the platform has the hardware SPI specified as argument. Implemented in %src/common.c%, it uses the $NUM_SPI$ macro that must be defined in the
+ platform's $platform_conf.h$ file (see @arch_overview.html#platforms at here@ for details). For example:</p>
+ ~#define NUM_SPI 1 $// The platform has 1 SPI interface$~<p> ]],
+ args = "$id$ - SPI interface ID",
+ ret = "1 if the SPI interface exists, 0 otherwise"
+ },
+
+ { sig = "u32 #platform_spi_setup#( unsigned id, int mode, u32 clock, unsigned cpol, unsigned cpha, unsigned databits );",
+ desc = [[This function is used to initialize the parameters of the SPI interface. <span class="warning">NOTE</span>: currently, only master SPI mode is implemented in eLua.]],
+ args =
+ {
+ "$id$ - SPI interface ID",
+ "$mode$ - SPI port mode ($PLATFORM_SPI_MASTER$ or $PLATFORM_SPI_SLAVE$, see @#spi_mode at here@.",
+ "$clock$ - clock speed for the SPI interface in master mode.",
+ "$cpol$ - SPI clock polarity",
+ "$cpha$ - SPI clock phase",
+ "$databits$ - length of the SPI data word in bits (usually 8, but configurable on some platforms)."
+ },
+ ret = "the actual clock set for the SPI interface. Depending on the hardware, this may have a different value than the $clock$ argument."
+ },
+
+ { sig = "spi_data_type #platform_spi_send_recv#( unsigned id, spi_data_type data );",
+ desc = "Executes a SPI read/write cycle",
+ args =
+ {
+ "$id$ - SPI interface ID",
+ "$data$ - data to be sent to the SPI interface",
+ },
+ ret = "data read from the SPI interface"
+ },
+
+ { sig = "void #platform_spi_select#( unsigned id, int is_select );",
+ desc = [[For platforms that have a dedicates SS (Slave Select) pin in master SPI mode that can be controlled manually, this function should enable/disable this pin. If this functionality
+ does not exist in hardware this function does nothing.]],
+ args =
+ {
+ "$id$ - SPI interface ID.",
+ "$is_select$ - $PLATFORM_SPI_SELECT_ON$ to select, $PLATFORM_SPI_SELECT_OFF$ to deselect , see @#chip_select at here@."
+ },
+ }
+ }
+}
+
+data_pt =
+{
+ -- Menu name
+ menu_name = "SPI",
+
+ -- Title
+ title = "eLua platform interface - SPI",
+
+ -- Overview
+ overview = "This part of the platform interface groups functions related to the SPI interface(s) of the MCU.",
+
+ -- Data structures, constants and types
+ structures =
+ {
+ { text = [[// SPI mode
+#define PLATFORM_SPI_MASTER 1
+#define PLATFORM_SPI_SLAVE 0 ]],
+ name = "Chip select",
+ desc = "Constants used to select/deselect the SPI SS pin (if applicable)."
+ },
+
+ { text = [[// SS values
+#define PLATFORM_SPI_SELECT_ON 1
+#define PLATFORM_SPI_SELECT_OFF 0]],
+ name = "SPI mode",
+ desc = "Constants used to select/deselect the SPI SS pin (if applicable)."
+ },
+
+ { text = "typedef u32 spi_data_type;",
+ name = "SPI data type",
+ desc = "This is the type of a SPI data word, thus limiting the maximum size of a SPI data work to 32 bits (which should be enough for all practical purposes)."
+ }
+ },
+
+ -- Functions
+ funcs =
+ {
+ { sig = "int #platform_spi_exists#( unsigned id );",
+ desc = [[Checks if the platform has the hardware SPI specified as argument. Implemented in %src/common.c%, it uses the $NUM_SPI$ macro that must be defined in the
+ platform's $platform_conf.h$ file (see @arch_overview.html#platforms at here@ for details). For example:</p>
+ ~#define NUM_SPI 1 $// The platform has 1 SPI interface$~<p> ]],
+ args = "$id$ - SPI interface ID",
+ ret = "1 if the SPI interface exists, 0 otherwise"
+ },
+
+ { sig = "u32 #platform_spi_setup#( unsigned id, int mode, u32 clock, unsigned cpol, unsigned cpha, unsigned databits );",
+ desc = [[This function is used to initialize the parameters of the SPI interface. <span class="warning">NOTE</span>: currently, only master SPI mode is implemented in eLua.]],
+ args =
+ {
+ "$id$ - SPI interface ID",
+ "$mode$ - SPI port mode ($PLATFORM_SPI_MASTER$ or $PLATFORM_SPI_SLAVE$, see @#spi_mode at here@.",
+ "$clock$ - clock speed for the SPI interface in master mode.",
+ "$cpol$ - SPI clock polarity",
+ "$cpha$ - SPI clock phase",
+ "$databits$ - length of the SPI data word in bits (usually 8, but configurable on some platforms)."
+ },
+ ret = "the actual clock set for the SPI interface. Depending on the hardware, this may have a different value than the $clock$ argument."
+ },
+
+ { sig = "spi_data_type #platform_spi_send_recv#( unsigned id, spi_data_type data );",
+ desc = "Executes a SPI read/write cycle",
+ args =
+ {
+ "$id$ - SPI interface ID",
+ "$data$ - data to be sent to the SPI interface",
+ },
+ ret = "data read from the SPI interface"
+ },
+
+ { sig = "void #platform_spi_select#( unsigned id, int is_select );",
+ desc = [[For platforms that have a dedicates SS (Slave Select) pin in master SPI mode that can be controlled manually, this function should enable/disable this pin. If this functionality
+ does not exist in hardware this function does nothing.]],
+ args =
+ {
+ "$id$ - SPI interface ID.",
+ "$is_select$ - $PLATFORM_SPI_SELECT_ON$ to select, $PLATFORM_SPI_SELECT_OFF$ to deselect , see @#chip_select at here@."
+ },
+ }
+ }
+}
+
Added: branches/eagle_mmc/doc/eluadoc/arch_platform_timers.lua
===================================================================
--- branches/eagle_mmc/doc/eluadoc/arch_platform_timers.lua 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/eluadoc/arch_platform_timers.lua 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,372 @@
+-- eLua platform interface - timers
+
+data_en =
+{
+ -- Title
+ title = "eLua platform interface - timers",
+
+ -- Menu name
+ menu_name = "Timers",
+
+ -- Overview
+ overview = [[This part of the platform interface groups functions related to the timers of the MCU. It also makes provisions for using $virtual timers$ on any platform, see @#virtual at this section@
+ for details. Keep in mind that in the following paragraphs a $timer id$ can reffer to both a hardware timer or a virtual timer.]],
+
+ -- Data structures, constants and types
+ structures =
+ {
+ { text = "typedef u32 timer_data_type;",
+ name = "Timer data type",
+ desc = "This defines the data type used to specify delays and time intervals (which are always specifide in $microseconds$)."
+ },
+
+ { text = [[// Timer operations
+enum
+{
+ PLATFORM_TIMER_OP_START,
+ PLATFORM_TIMER_OP_READ,
+ PLATFORM_TIMER_OP_SET_CLOCK,
+ PLATFORM_TIMER_OP_GET_CLOCK,
+ PLATFORM_TIMER_OP_GET_MAX_DELAY,
+ PLATFORM_TIMER_OP_GET_MIN_DELAY
+};]],
+ name = "Timer operations",
+ desc = "This enum lists all the operations that can be executed on a given timer."
+ }
+ },
+
+ -- Functions
+ funcs =
+ {
+ { sig = "int #platform_timer_exists#( unsigned id );",
+ desc = [[Checks if the platform has the timer specified as argument. Implemented in %src/common.c%, it uses the $NUM_TIMER$ macro that must be defined in the
+ platform's $platform_conf.h$ file (see @arch_overview.html#platforms at here@ for details) and the virtual timer configuration (@#virtual at here@ for details). For example:</p>
+ ~#define NUM_TIMER 2 $// The platform has 2 hardware timers$~<p>]],
+ args = "$id$ - the timer ID",
+ ret = "1 if the timer exists, 0 otherwise"
+ },
+
+ { sig = "void #platform_timer_delay#( unsigned id, u32 delay_us );",
+ desc = [[Waits on a timer, then returns. This function is "split" in two parts: a platform-independent part implemented in %src/common.c% (that
+ handles virtual timers) and a platform-dependent part that must be implemented by each platform in a function named @#platform_s_timer_delay at platform_s_timer_delay@. This function handles both
+ hardware timer IDs and virtual timer IDs.<br>
+ <a name="limitations" /><span class="warning">IMPORTANT NOTE</span>: the real delay after executing this functions depends on a number of variables, most notably the base clock of the timer
+ and the size of the timer counter register (32 bits on some platforms, 16 bits on most platforms, other values are less common). To ensure that the delay you're requesting is achievable, use
+ @#platform_timer_op at platform_timer_op@ with $PLATFORM_TIMER_OP_GET_MAX_DELAY$ and $PLATFORM_TIMER_OP_GET_MIN_DELAY$ to obtain the maximum and the minimum
+ achievable wait times on your timer, respectively. Even if your delay is within these limits, the $precision$ of this function still varies a lot, mainly as a function of
+ the timer base clock.]],
+ args =
+ {
+ "$id$ - the timer ID",
+ "$delay_us$ - the delay time (in microseconds)"
+ }
+ },
+
+ { sig = "void #platform_s_timer_delay#( unsigned id, u32 delay_us );",
+ desc = [[This function is identical in functionality to @#platform_timer_delay at platform_timer_delay@, but this is the function that must actually be implemented by a platform port,
+ and it must never handle virtual timer IDs, only hardware timer IDs. It has the same @#limitations at limitations@ as @#platform_timer_delay at platform_timer_delay@.]],
+ args =
+ {
+ "$id$ - the timer ID",
+ "$delay_us$ - the delay time (in microseconds)"
+ }
+ },
+
+ { sig = "u32 #platform_timer_op#( unsigned id, int op, u32 data );",
+ desc = [[Executes an operation on a timer. This function is "split" in two parts: a platform-independent part implemented in %src/common.c% (that handles virtual timers) and a
+ platform-dependent part that must be implemented by each platform in a function named @#platform_s_timer_op at platform_s_timer_op@. This function handles both hardware timer IDs and virtual
+ timer IDs.]],
+ args =
+ {
+ "$id$ - the timer ID",
+ [[$op$ - the operation. $op$ can take any value from the @#timer_operations at this enum@, as follows:
+ <ul>
+ <li>$PLATFORM_TIMER_OP_START$: start the specified timer by setting its counter register to a predefined value.</li>
+ <li>$PLATFORM_TIMER_OP_READ$: get the value of the specified timer's counter register.</li>
+ <li>$PLATFORM_TIMER_SET_CLOCK$: set the clock of the specified timer to $data$ (in hertz). You can never set the clock of a virtual timer, which is set at compile time.</li>
+ <li>$PLATFORM_TIMER_GET_CLOCK$: get the clock of the specified timer.</li>
+ <li>$PLATFORM_TIMER_OP_GET_MAX_DELAY$: get the maximum achievable timeout on the specified timer (in us).</li>
+ <li>$PLATFORM_TIMER_OP_GET_MIN_DELAY$: get the minimum achievable timeout on the specified timer (in us).</li>
+ </ul>]],
+ "$data$ - used to specify the timer clock value when $op = PLATFORM_TIMER_SET_CLOCK$, ignored otherwise",
+ },
+ ret =
+ {
+ "the predefined value used when starting the clock if $op = PLATFORM_TIMER_OP_START$",
+ "the timer's counter register if $op = PLATFORM_TIMER_OP_READ$",
+ "the actual clock set on the timer, which might be different than the request clock depending on the hardware if $op = PLATFORM_TIMER_SET_CLOCK$",
+ "the timer clock if $op = PLATFORM_TIMER_GET_CLOCK$",
+ "the maximum achievable delay (in microseconds) if $op = PLATFORM_TIMER_OP_GET_MAX_DELAY$",
+ "the minimum achievable delay (in microseconds) if $op = PLATFORM_TIMER_OP_GET_MIN_DELAY$"
+ }
+ },
+
+ { sig = "u32 #platform_s_timer_op#( unsigned id, int op, u32 data );",
+ desc = [[This function is identical in functionality to @#platform_timer_op at platform_timer_op@, but this is the function that must actually be implemented by a platform port, and it must
+ never handle virtual timer IDs, only hardware timer IDs.]],
+ args =
+ {
+ "$id$ - the timer ID",
+ [[$op$ - the operation. $op$ can take any value from the @#opval at this enum@, as follows:
+ <ul>
+ <li>$PLATFORM_TIMER_OP_START$: start the specified timer by setting its counter register to a predefined value.</li>
+ <li>$PLATFORM_TIMER_OP_READ$: get the value of the specified timer's counter register.</li>
+ <li>$PLATFORM_TIMER_SET_CLOCK$: set the clock of the specified timer to $data$ (in hertz). You can never set the clock of a virtual timer, which is set at compile time.</li>
+ <li>$PLATFORM_TIMER_GET_CLOCK$: get the clock of the specified timer.</li>
+ <li>$PLATFORM_TIMER_OP_GET_MAX_DELAY$: get the maximum achievable timeout on the specified timer (in us).</li>
+ <li>$PLATFORM_TIMER_OP_GET_MIN_DELAY$: get the minimum achievable timeout on the specified timer (in us).</li>
+ </ul>]],
+ "$data$ - used to specify the timer clock value when $op = PLATFORM_TIMER_SET_CLOCK$, ignored otherwise",
+ },
+ ret =
+ {
+ "the predefined value used when starting the clock if $op = PLATFORM_TIMER_OP_START$",
+ "the timer's counter register if $op = PLATFORM_TIMER_OP_READ$",
+ "the actual clock set on the timer, which might be different than the request clock depending on the hardware if $op = PLATFORM_TIMER_SET_CLOCK$",
+ "the timer clock if $op = PLATFORM_TIMER_GET_CLOCK$",
+ "the maximum achievable delay (in microseconds) if $op = PLATFORM_TIMER_OP_GET_MAX_DELAY$",
+ "the minimum achievable delay (in microseconds) if $op = PLATFORM_TIMER_OP_GET_MIN_DELAY$"
+ }
+ },
+
+ { sig = "u32 #platform_timer_get_diff_us#( unsigned id, timer_data_type end, timer_data_type start );",
+ desc = [[Return the time difference (in us) betweeen two timer values. This function is generic for all platforms, thus it is implemented in %src/common.c%.]],
+ args =
+ {
+ "$id$ - the timer ID",
+ "$end$ - the first timer value",
+ "$start$ - the second timer value",
+ },
+ ret = "the time difference (in microseconds)"
+ }
+ },
+
+ auxdata =
+ {
+ { title = "Virtual timers",
+ desc =
+ [[$Virtual timers$ were added to eLua to overcome some limitations:</p>
+ <ul>
+ <li>there are generally few hardware timers available, some of which might be dedicated (thus not usable directly by eLua).</li>
+ <li>many times it is difficult to share a hardware timer between different parts of an application because of conflicting requirements. Generally it's not possible to have timers that can
+ achieve long delays and high accuracy at the same time (this is especially true for systems that have 16 bit or even smaller timers).</li>
+ </ul>
+ <p>In this respect, $virtual timers$ are a set of timers that share a single hardware timer. It is possible, in this way, to have a hardware timer that can implement 4, 8 or more hardware
+ timers. There are a few drawbacks to this approach:</p>
+ <ul>
+ <li>the hardware timer used to implement the virtual timers must generally be dedicated. In fact in cat be still used in "read only mode", which means that the only operations that can
+ be executed on it are $PLATFORM_TIMER_OP_READ$, $PLATFORM_TIMER_GET_CLOCK$, $PLATFORM_TIMER_OP_GET_MAX_DELAY$ and $PLATFORM_TIMER_OP_GET_MIN_DELAY$. However,
+ since the "read only mode" is not enforced by the code, it is advisable to treat this timer as a dedicated resource and thus make it invisible to eLua by not associating it with
+ an ID.</li>
+ <li>the number of virtual timers and their base frequency are fixed at compile time.</li>
+ <li>virtual timers are generally used for large delays with low accuracy, since their base frequency should be fairly low (see below).</li>
+ </ul>
+ <p>To $enable$ virtual timers:</p>
+ <ol>
+ <li>edit $platform_conf.h$ (see @arch_overview.html#platforms at here@ for details) and set $VTMR_NUM_TIMERS$ to the number of desired virtual timers and
+ $VTMR_FREQ_HZ$ to the base frequency of the virtual timers (in hertz). For example:
+ ~#define VTMR_NUM_TIMERS 4 // we need 4 virtual timers
+#define VTMR_FREQ_HZ 4 // the base clock for the virtual timers is 4Hz~</li>
+ <li>in your platform port setup a hardware timer to fire an interrupt at $VTMR_FREQ_HZ$ and call the $cmn_virtual_timer_cb$ function (defined in %src/common.c%) in the
+ timer interrupt handler. For example, if the the interrupt handler is called $timer_int_handler$, do this:
+ ~void timer_int_handler( void )
+{
+ // add code to clear the timer interrupt flag here if needed
+ cmn_virtual_timer_cb();
+}~</li>
+ </ol>
+ <p>Note that because of step 2 above you are limited by practical constraints on the value of $VTMR_FREQ_HZ$. If set too high, the timer interrupt will fire too often, thus taking too much
+ CPU time. The maximum value depends largely on the hardware and the desired behaviour of the virtual timers, but in practice values larger than 10 might visibly change the behaviour of your
+ system.</p>
+ <p>To $use$ a virtual timer, identify it with the constant $VTMR_FIRST_ID$ (defined in %inc/common.h%) plus an offset. For example, $VTMR_FIRST_ID+0$ (or simply
+ $VTMR_FIRST_ID$) is the ID of the first virtual timer in the system, and $VTMR_FIRST_ID+2$ is the ID of the third virtual timer in the system.
+ ]]
+ }
+ }
+}
+
+data_pt =
+{
+ -- Title
+ title = "eLua platform interface - timers",
+
+ -- Menu name
+ menu_name = "Timers",
+
+ -- Overview
+ overview = [[This part of the platform interface groups functions related to the timers of the MCU. It also makes provisions for using $virtual timers$ on any platform, see @#virtual at this section@
+ for details. Keep in mind that in the following paragraphs a $timer id$ can reffer to both a hardware timer or a virtual timer.]],
+
+ -- Data structures, constants and types
+ structures =
+ {
+ { text = "typedef u32 timer_data_type;",
+ name = "Timer data type",
+ desc = "This defines the data type used to specify delays and time intervals (which are always specifide in $microseconds$)."
+ },
+
+ { text = [[// Timer operations
+enum
+{
+ PLATFORM_TIMER_OP_START,
+ PLATFORM_TIMER_OP_READ,
+ PLATFORM_TIMER_OP_SET_CLOCK,
+ PLATFORM_TIMER_OP_GET_CLOCK,
+ PLATFORM_TIMER_OP_GET_MAX_DELAY,
+ PLATFORM_TIMER_OP_GET_MIN_DELAY
+};]],
+ name = "Timer operations",
+ desc = "This enum lists all the operations that can be executed on a given timer."
+ }
+ },
+
+ -- Functions
+ funcs =
+ {
+ { sig = "int #platform_timer_exists#( unsigned id );",
+ desc = [[Checks if the platform has the timer specified as argument. Implemented in %src/common.c%, it uses the $NUM_TIMER$ macro that must be defined in the
+ platform's $platform_conf.h$ file (see @arch_overview.html#platforms at here@ for details) and the virtual timer configuration (@#virtual at here@ for details). For example:</p>
+ ~#define NUM_TIMER 2 $// The platform has 2 hardware timers$~<p>]],
+ args = "$id$ - the timer ID",
+ ret = "1 if the timer exists, 0 otherwise"
+ },
+
+ { sig = "void #platform_timer_delay#( unsigned id, u32 delay_us );",
+ desc = [[Waits on a timer, then returns. This function is "split" in two parts: a platform-independent part implemented in %src/common.c% (that
+ handles virtual timers) and a platform-dependent part that must be implemented by each platform in a function named @#platform_s_timer_delay at platform_s_timer_delay@. This function handles both
+ hardware timer IDs and virtual timer IDs.<br>
+ <a name="limitations" /><span class="warning">IMPORTANT NOTE</span>: the real delay after executing this functions depends on a number of variables, most notably the base clock of the timer
+ and the size of the timer counter register (32 bits on some platforms, 16 bits on most platforms, other values are less common). To ensure that the delay you're requesting is achievable, use
+ @#platform_timer_op at platform_timer_op@ with $PLATFORM_TIMER_OP_GET_MAX_DELAY$ and $PLATFORM_TIMER_OP_GET_MIN_DELAY$ to obtain the maximum and the minimum
+ achievable wait times on your timer, respectively. Even if your delay is within these limits, the $precision$ of this function still varies a lot, mainly as a function of
+ the timer base clock.]],
+ args =
+ {
+ "$id$ - the timer ID",
+ "$delay_us$ - the delay time (in microseconds)"
+ }
+ },
+
+ { sig = "void #platform_s_timer_delay#( unsigned id, u32 delay_us );",
+ desc = [[This function is identical in functionality to @#platform_timer_delay at platform_timer_delay@, but this is the function that must actually be implemented by a platform port,
+ and it must never handle virtual timer IDs, only hardware timer IDs. It has the same @#limitations at limitations@ as @#platform_timer_delay at platform_timer_delay@.]],
+ args =
+ {
+ "$id$ - the timer ID",
+ "$delay_us$ - the delay time (in microseconds)"
+ }
+ },
+
+ { sig = "u32 #platform_timer_op#( unsigned id, int op, u32 data );",
+ desc = [[Executes an operation on a timer. This function is "split" in two parts: a platform-independent part implemented in %src/common.c% (that handles virtual timers) and a
+ platform-dependent part that must be implemented by each platform in a function named @#platform_s_timer_op at platform_s_timer_op@. This function handles both hardware timer IDs and virtual
+ timer IDs.]],
+ args =
+ {
+ "$id$ - the timer ID",
+ [[$op$ - the operation. $op$ can take any value from the @#timer_operations at this enum@, as follows:
+ <ul>
+ <li>$PLATFORM_TIMER_OP_START$: start the specified timer by setting its counter register to a predefined value.</li>
+ <li>$PLATFORM_TIMER_OP_READ$: get the value of the specified timer's counter register.</li>
+ <li>$PLATFORM_TIMER_SET_CLOCK$: set the clock of the specified timer to $data$ (in hertz). You can never set the clock of a virtual timer, which is set at compile time.</li>
+ <li>$PLATFORM_TIMER_GET_CLOCK$: get the clock of the specified timer.</li>
+ <li>$PLATFORM_TIMER_OP_GET_MAX_DELAY$: get the maximum achievable timeout on the specified timer (in us).</li>
+ <li>$PLATFORM_TIMER_OP_GET_MIN_DELAY$: get the minimum achievable timeout on the specified timer (in us).</li>
+ </ul>]],
+ "$data$ - used to specify the timer clock value when $op = PLATFORM_TIMER_SET_CLOCK$, ignored otherwise",
+ },
+ ret =
+ {
+ "the predefined value used when starting the clock if $op = PLATFORM_TIMER_OP_START$",
+ "the timer's counter register if $op = PLATFORM_TIMER_OP_READ$",
+ "the actual clock set on the timer, which might be different than the request clock depending on the hardware if $op = PLATFORM_TIMER_SET_CLOCK$",
+ "the timer clock if $op = PLATFORM_TIMER_GET_CLOCK$",
+ "the maximum achievable delay (in microseconds) if $op = PLATFORM_TIMER_OP_GET_MAX_DELAY$",
+ "the minimum achievable delay (in microseconds) if $op = PLATFORM_TIMER_OP_GET_MIN_DELAY$"
+ }
+ },
+
+ { sig = "u32 #platform_s_timer_op#( unsigned id, int op, u32 data );",
+ desc = [[This function is identical in functionality to @#platform_timer_op at platform_timer_op@, but this is the function that must actually be implemented by a platform port, and it must
+ never handle virtual timer IDs, only hardware timer IDs.]],
+ args =
+ {
+ "$id$ - the timer ID",
+ [[$op$ - the operation. $op$ can take any value from the @#opval at this enum@, as follows:
+ <ul>
+ <li>$PLATFORM_TIMER_OP_START$: start the specified timer by setting its counter register to a predefined value.</li>
+ <li>$PLATFORM_TIMER_OP_READ$: get the value of the specified timer's counter register.</li>
+ <li>$PLATFORM_TIMER_SET_CLOCK$: set the clock of the specified timer to $data$ (in hertz). You can never set the clock of a virtual timer, which is set at compile time.</li>
+ <li>$PLATFORM_TIMER_GET_CLOCK$: get the clock of the specified timer.</li>
+ <li>$PLATFORM_TIMER_OP_GET_MAX_DELAY$: get the maximum achievable timeout on the specified timer (in us).</li>
+ <li>$PLATFORM_TIMER_OP_GET_MIN_DELAY$: get the minimum achievable timeout on the specified timer (in us).</li>
+ </ul>]],
+ "$data$ - used to specify the timer clock value when $op = PLATFORM_TIMER_SET_CLOCK$, ignored otherwise",
+ },
+ ret =
+ {
+ "the predefined value used when starting the clock if $op = PLATFORM_TIMER_OP_START$",
+ "the timer's counter register if $op = PLATFORM_TIMER_OP_READ$",
+ "the actual clock set on the timer, which might be different than the request clock depending on the hardware if $op = PLATFORM_TIMER_SET_CLOCK$",
+ "the timer clock if $op = PLATFORM_TIMER_GET_CLOCK$",
+ "the maximum achievable delay (in microseconds) if $op = PLATFORM_TIMER_OP_GET_MAX_DELAY$",
+ "the minimum achievable delay (in microseconds) if $op = PLATFORM_TIMER_OP_GET_MIN_DELAY$"
+ }
+ },
+
+ { sig = "u32 #platform_timer_get_diff_us#( unsigned id, timer_data_type end, timer_data_type start );",
+ desc = [[Return the time difference (in us) betweeen two timer values. This function is generic for all platforms, thus it is implemented in %src/common.c%.]],
+ args =
+ {
+ "$id$ - the timer ID",
+ "$end$ - the first timer value",
+ "$start$ - the second timer value",
+ },
+ ret = "the time difference (in microseconds)"
+ }
+ },
+
+ auxdata =
+ {
+ { title = "Virtual timers",
+ desc =
+ [[$Virtual timers$ were added to eLua to overcome some limitations:</p>
+ <ul>
+ <li>there are generally few hardware timers available, some of which might be dedicated (thus not usable directly by eLua).</li>
+ <li>many times it is difficult to share a hardware timer between different parts of an application because of conflicting requirements. Generally it's not possible to have timers that can
+ achieve long delays and high accuracy at the same time (this is especially true for systems that have 16 bit or even smaller timers).</li>
+ </ul>
+ <p>In this respect, $virtual timers$ are a set of timers that share a single hardware timer. It is possible, in this way, to have a hardware timer that can implement 4, 8 or more hardware
+ timers. There are a few drawbacks to this approach:</p>
+ <ul>
+ <li>the hardware timer used to implement the virtual timers must generally be dedicated. In fact in cat be still used in "read only mode", which means that the only operations that can
+ be executed on it are $PLATFORM_TIMER_OP_READ$, $PLATFORM_TIMER_GET_CLOCK$, $PLATFORM_TIMER_OP_GET_MAX_DELAY$ and $PLATFORM_TIMER_OP_GET_MIN_DELAY$. However,
+ since the "read only mode" is not enforced by the code, it is advisable to treat this timer as a dedicated resource and thus make it invisible to eLua by not associating it with
+ an ID.</li>
+ <li>the number of virtual timers and their base frequency are fixed at compile time.</li>
+ <li>virtual timers are generally used for large delays with low accuracy, since their base frequency should be fairly low (see below).</li>
+ </ul>
+ <p>To $enable$ virtual timers:</p>
+ <ol>
+ <li>edit $platform_conf.h$ (see @arch_overview.html#platforms at here@ for details) and set $VTMR_NUM_TIMERS$ to the number of desired virtual timers and
+ $VTMR_FREQ_HZ$ to the base frequency of the virtual timers (in hertz). For example:
+ ~#define VTMR_NUM_TIMERS 4 // we need 4 virtual timers
+#define VTMR_FREQ_HZ 4 // the base clock for the virtual timers is 4Hz~</li>
+ <li>in your platform port setup a hardware timer to fire an interrupt at $VTMR_FREQ_HZ$ and call the $cmn_virtual_timer_cb$ function (defined in %src/common.c%) in the
+ timer interrupt handler. For example, if the the interrupt handler is called $timer_int_handler$, do this:
+ ~void timer_int_handler( void )
+{
+ // add code to clear the timer interrupt flag here if needed
+ cmn_virtual_timer_cb();
+}~</li>
+ </ol>
+ <p>Note that because of step 2 above you are limited by practical constraints on the value of $VTMR_FREQ_HZ$. If set too high, the timer interrupt will fire too often, thus taking too much
+ CPU time. The maximum value depends largely on the hardware and the desired behaviour of the virtual timers, but in practice values larger than 10 might visibly change the behaviour of your
+ system.</p>
+ <p>To $use$ a virtual timer, identify it with the constant $VTMR_FIRST_ID$ (defined in %inc/common.h%) plus an offset. For example, $VTMR_FIRST_ID+0$ (or simply
+ $VTMR_FIRST_ID$) is the ID of the first virtual timer in the system, and $VTMR_FIRST_ID+2$ is the ID of the third virtual timer in the system.
+ ]]
+ }
+ }
+}
+
Added: branches/eagle_mmc/doc/eluadoc/arch_platform_uart.lua
===================================================================
--- branches/eagle_mmc/doc/eluadoc/arch_platform_uart.lua 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/eluadoc/arch_platform_uart.lua 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,250 @@
+-- eLua platform interface - UART
+
+data_en =
+{
+ -- Title
+ title = "eLua platform interface - UART",
+
+ -- Menu name
+ menu_name = "UART",
+
+ -- Overview
+ overview = "This part of the platform interface groups functions related to the UART interface(s) of the MCU.",
+
+ -- Data structures, constants and types
+ structures =
+ {
+ { text = [[// Parity
+enum
+{
+ PLATFORM_UART_PARITY_EVEN,
+ PLATFORM_UART_PARITY_ODD,
+ PLATFORM_UART_PARITY_NONE
+};]],
+ name = "UART parity",
+ desc = "Constants used to specify the UART parity mode."
+ },
+
+ { text = [[// Stop bits
+enum
+{
+ PLATFORM_UART_STOPBITS_1,
+ PLATFORM_UART_STOPBITS_1_5,
+ PLATFORM_UART_STOPBITS_2
+};]],
+ name = "UART stop bits",
+ desc = "Constants used to specify the number of UART stop bits.",
+ },
+
+ { text = [[// "Infinite timeout" constant for recv
+#define PLATFORM_UART_INFINITE_TIMEOUT (-1)]],
+ name = "UART timeout",
+ desc = "This constant is used as a special timeout value (infinite timeout) in the UART functions that expect a timeout as argument.",
+ }
+ },
+
+ -- Functions
+ funcs =
+ {
+ { sig = "int #platform_uart_exists#( unsigned id );",
+ desc = [[Checks if the platform has the hardware UART specified as argument. Implemented in %src/common.c%, it uses the $NUM_UART$ macro that must be defined in the
+ platform's $platform_conf.h$ file (see @arch_overview.html#platforms at here@ for details). For example:</p>
+ ~#define NUM_UART 2 $// The platform has 2 UART interfaces$~<p>]],
+ args = "$id$ - UART interface ID",
+ ret = "1 if the specified UART exists, 0 otherwise"
+ },
+
+ { sig = "u32 #platform_uart_setup#( unsigned id, u32 baud, int databits, int parity, int stopbits );",
+ desc = "This function is used to initialize the parameters of the UART interface.",
+ args =
+ {
+ "$id$ - UART interface ID.",
+ "$baud$ - baud rate.",
+ "$databits$ - number of databits (maximum 8).",
+ "$parity$ - parity type (can be either $PLATFORM_UART_PARITY_EVEN$, $PLATFORM_UART_PARITY_ODD$ or $PLATFORM_UART_PARITY_NONE$, see @#uart_parity at here@).",
+ [[$stopbits$ - number of stop bits (can be either $PLATFORM_UART_STOPBITS_1$, $PLATFORM_UART_STOPBITS_1_5$ or $PLATFORM_UART_STOPBITS_2$, see
+ @#uart_stop_bits at here@).]],
+ },
+ ret = "the actual baud rate. Depending on the hardware, this may have a different value than the $baud$ argument.",
+ },
+
+ { sig = "void #platform_uart_send#( unsigned id, u8 data );",
+ desc = "Send data to an UART interface.",
+ args =
+ {
+ "$id$ - UART interface ID.",
+ "$data$ - data to be sent.",
+ },
+ },
+
+ { sig = "int #platform_uart_recv#( unsigned id, unsigned timer_id, s32 timeout );",
+ link = "platform_uart_recv",
+ desc = [[Receive data from the UART interface (blocking/non blocking with timeout/immediate).<br>
+ This function is "split" in two parts: a platform-independent part that is implemented in %src/common.c%, and a platform-dependent part that must be implemented by each
+ platform in a function named @#platform_s_uart_recv at platform_s_uart_recv@.]],
+ args =
+ {
+ "$id$ - UART interface ID.",
+ "$timer_id$ - the ID of the timer used in this operation (see @arch_platform_timers.html at here@ for details). See also the description of the $timeout$ argument.",
+ [[$timeout$ - specifies a timeout for the receive operation as follows:
+ <ul>
+ <li>$timeout > 0$: the timer with the specified $timer_id$ will be used to timeout the receive operation after $timeout$ microseconds.</li>
+ <li>$timeout = 0$: the function returns immediately regardless of data being available or not. $timer_id$ is ignored.</li>
+ <li>$timeout$ = @#uart_timeout at PLATFORM_UART_INFINITE_TIMEOUT@: the function waits indefinitely for UART data to be available and returns it. In this mode the function doesn't
+ time out, so $timer_id$ is ignored.</li>
+ </ul>]],
+ },
+ ret =
+ {
+ "if $timeout > 0$ and data from the UART is available in $timeout$ microseconds of less it is returned, otherwise -1 is returned",
+ "if $timeout = 0$ and data from the UART is available when the function is called it is returned, otherwise -1 is returned",
+ "if $timeout$ = @#uart_timeout at PLATFORM_UART_INIFINITE_TIMEOUT@ it returns the data read from the UART after it becomes available"
+ }
+ },
+
+ { sig = "int #platform_s_uart_recv#( unsigned id, s32 timeout );",
+ link = "platform_s_uart_recv",
+ desc = [[This is the platform-dependent part of the UART receive function @#platform_uart_recv at platform_uart_recv@, and is in fact a "subset" of the full function
+ (thus being easier to implement by each platform in part). In particular, it never needs to deal with the $timeout > 0$ case, which is handled by @#platform_uart_recv at platform_uart_recv@.]],
+ args =
+ {
+ "$id$ - UART interface ID.",
+ [[$timeout$ - specifies a timeout for the receive operation as follows:
+ <ul>
+ <li>$timeout = 0$: the function returns immediately regardless of data being available or not.</li>
+ <li>$timeout$ = @#uart_timeout at PLATFORM_UART_INFINITE_TIMEOUT@: the function waits indefinitely for UART data to be available and returns it.</li>
+ </ul>]],
+ },
+ ret =
+ {
+ "if $timeout = 0$ and data from the UART is available when the function is called it is returned, otherwise -1 is returned",
+ "if $timeout$ = @#uart_timeout at PLATFORM_UART_INIFINITE_TIMEOUT@ it returns the data read from the UART after it becomes available"
+ }
+ }
+ }
+}
+
+data_pt =
+{
+ -- Title
+ title = "eLua platform interface - UART",
+
+ -- Menu name
+ menu_name = "UART",
+
+ -- Overview
+ overview = "This part of the platform interface groups functions related to the UART interface(s) of the MCU.",
+
+ -- Data structures, constants and types
+ structures =
+ {
+ { text = [[// Parity
+enum
+{
+ PLATFORM_UART_PARITY_EVEN,
+ PLATFORM_UART_PARITY_ODD,
+ PLATFORM_UART_PARITY_NONE
+};]],
+ name = "UART parity",
+ desc = "Constants used to specify the UART parity mode."
+ },
+
+ { text = [[// Stop bits
+enum
+{
+ PLATFORM_UART_STOPBITS_1,
+ PLATFORM_UART_STOPBITS_1_5,
+ PLATFORM_UART_STOPBITS_2
+};]],
+ name = "UART stop bits",
+ desc = "Constants used to specify the number of UART stop bits.",
+ },
+
+ { text = [[// "Infinite timeout" constant for recv
+#define PLATFORM_UART_INFINITE_TIMEOUT (-1)]],
+ name = "UART timeout",
+ desc = "This constant is used as a special timeout value (infinite timeout) in the UART functions that expect a timeout as argument.",
+ }
+ },
+
+ -- Functions
+ funcs =
+ {
+ { sig = "int #platform_uart_exists#( unsigned id );",
+ desc = [[Checks if the platform has the hardware UART specified as argument. Implemented in %src/common.c%, it uses the $NUM_UART$ macro that must be defined in the
+ platform's $platform_conf.h$ file (see @arch_overview.html#platforms at here@ for details). For example:</p>
+ ~#define NUM_UART 2 $// The platform has 2 UART interfaces$~<p>]],
+ args = "$id$ - UART interface ID",
+ ret = "1 if the specified UART exists, 0 otherwise"
+ },
+
+ { sig = "u32 #platform_uart_setup#( unsigned id, u32 baud, int databits, int parity, int stopbits );",
+ desc = "This function is used to initialize the parameters of the UART interface.",
+ args =
+ {
+ "$id$ - UART interface ID.",
+ "$baud$ - baud rate.",
+ "$databits$ - number of databits (maximum 8).",
+ "$parity$ - parity type (can be either $PLATFORM_UART_PARITY_EVEN$, $PLATFORM_UART_PARITY_ODD$ or $PLATFORM_UART_PARITY_NONE$, see @#uart_parity at here@).",
+ [[$stopbits$ - number of stop bits (can be either $PLATFORM_UART_STOPBITS_1$, $PLATFORM_UART_STOPBITS_1_5$ or $PLATFORM_UART_STOPBITS_2$, see
+ @#uart_stop_bits at here@).]],
+ },
+ ret = "the actual baud rate. Depending on the hardware, this may have a different value than the $baud$ argument.",
+ },
+
+ { sig = "void #platform_uart_send#( unsigned id, u8 data );",
+ desc = "Send data to an UART interface.",
+ args =
+ {
+ "$id$ - UART interface ID.",
+ "$data$ - data to be sent.",
+ },
+ },
+
+ { sig = "int #platform_uart_recv#( unsigned id, unsigned timer_id, s32 timeout );",
+ link = "platform_uart_recv",
+ desc = [[Receive data from the UART interface (blocking/non blocking with timeout/immediate).<br>
+ This function is "split" in two parts: a platform-independent part that is implemented in %src/common.c%, and a platform-dependent part that must be implemented by each
+ platform in a function named @#platform_s_uart_recv at platform_s_uart_recv@.]],
+ args =
+ {
+ "$id$ - UART interface ID.",
+ "$timer_id$ - the ID of the timer used in this operation (see @arch_platform_timers.html at here@ for details). See also the description of the $timeout$ argument.",
+ [[$timeout$ - specifies a timeout for the receive operation as follows:
+ <ul>
+ <li>$timeout > 0$: the timer with the specified $timer_id$ will be used to timeout the receive operation after $timeout$ microseconds.</li>
+ <li>$timeout = 0$: the function returns immediately regardless of data being available or not. $timer_id$ is ignored.</li>
+ <li>$timeout$ = @#uart_timeout at PLATFORM_UART_INFINITE_TIMEOUT@: the function waits indefinitely for UART data to be available and returns it. In this mode the function doesn't
+ time out, so $timer_id$ is ignored.</li>
+ </ul>]],
+ },
+ ret =
+ {
+ "if $timeout > 0$ and data from the UART is available in $timeout$ microseconds of less it is returned, otherwise -1 is returned",
+ "if $timeout = 0$ and data from the UART is available when the function is called it is returned, otherwise -1 is returned",
+ "if $timeout$ = @#uart_timeout at PLATFORM_UART_INIFINITE_TIMEOUT@ it returns the data read from the UART after it becomes available"
+ }
+ },
+
+ { sig = "int #platform_s_uart_recv#( unsigned id, s32 timeout );",
+ link = "platform_s_uart_recv",
+ desc = [[This is the platform-dependent part of the UART receive function @#platform_uart_recv at platform_uart_recv@, and is in fact a "subset" of the full function
+ (thus being easier to implement by each platform in part). In particular, it never needs to deal with the $timeout > 0$ case, which is handled by @#platform_uart_recv at platform_uart_recv@.]],
+ args =
+ {
+ "$id$ - UART interface ID.",
+ [[$timeout$ - specifies a timeout for the receive operation as follows:
+ <ul>
+ <li>$timeout = 0$: the function returns immediately regardless of data being available or not.</li>
+ <li>$timeout$ = @#uart_timeout at PLATFORM_UART_INFINITE_TIMEOUT@: the function waits indefinitely for UART data to be available and returns it.</li>
+ </ul>]],
+ },
+ ret =
+ {
+ "if $timeout = 0$ and data from the UART is available when the function is called it is returned, otherwise -1 is returned",
+ "if $timeout$ = @#uart_timeout at PLATFORM_UART_INIFINITE_TIMEOUT@ it returns the data read from the UART after it becomes available"
+ }
+ }
+ }
+}
+
Added: branches/eagle_mmc/doc/eluadoc/refman_gen_adc.lua
===================================================================
--- branches/eagle_mmc/doc/eluadoc/refman_gen_adc.lua 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/eluadoc/refman_gen_adc.lua 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,196 @@
+-- eLua reference manual - ADC
+
+data_en =
+{
+
+ -- Title
+ title = "eLua reference manual - ADC",
+
+ -- Menu name
+ menu_name = "adc",
+
+ -- Overview
+ overview = [[This module contains functions that access analog to digital converter (ADC) peripherals.</p>
+ <p>When utilizing this module, acquiring ADC data is a two step process: requesting sample conversions (using $adc.sample$) and extraction of conversion results from a conversion buffer (using $adc.getsample$, $adc.getsamples$ or $adc.insertsamples$). Various configuration parameters are available to set conversion rate, how results are extracted from the buffer and how these results are processed prior to extraction.</p>
+ <p>This module can be utilized if the device in use has a supported ADC peripheral (see @status.html at status@ for details) and if ADC functionality is enabled at build time (see @building.html at building@).]],
+
+ -- Functions
+ funcs =
+ {
+ { sig = "#adc.sample#( id, count )",
+ desc = "Initiate conversion and buffering of samples on an ADC channel.",
+ args =
+ {
+ "$id$ - ADC channel ID. Optionally, this may be a table containing a list of channel IDs (i.e.: {0, 2, 3}), allowing synchronization of acquisition. NOTE: This acceptance of mixed types is only for the sample function.",
+ "$count$ - number of samples to acquire and place in buffer."
+ }
+ },
+ { sig = "sample = #adc.getsample#( id )",
+ desc = "Get a single conversion value from the buffer associated with a given channel.",
+ args =
+ {
+ "$id$ - ADC channel ID."
+ },
+ ret = "$sample$ - numeric value of conversion, or nil if sample was not available."
+ },
+ { sig = "samples = #adc.getsamples#( id, count )",
+ desc = "Get multiple conversion values from the buffer associated with a given channel.",
+ args =
+ {
+ "$id$ - ADC channel ID.",
+ "$count$ - optional parameter to indicate number of samples to return. If not included, all available samples are returned."
+ },
+ ret = "$samples$ - table containing integer conversion values. If not enough samples are available, remaining indices will be nil."
+ },
+ { sig = "#adc.insertsamples#( id, table, idx, count )",
+ desc = "Get multiple conversion values from a channel's buffer, and write them into a table.",
+ args =
+ {
+ "$id$ - ADC channel ID.",
+ "$table$ - table to write samples to. Values at $table$[$idx$] to $table$[$idx$ + $count$ -1] will be overwritten with samples (or nil if not enough samples are available).",
+ "$idx$ - first index to use in the table for writing samples.",
+ "$count$ - number of samples to return. If not enough samples are available (after blocking, if enabled) remaining values will be nil."
+ }
+ },
+ { sig = "maxval = #adc.maxval#( id )",
+ desc = "Get the maximum value (corresponding to the maximum voltage) that can be returned on a given channel.",
+ args =
+ {
+ "$id$ - ADC channel ID."
+ },
+ ret = "$maxval$ - maximum integer conversion value (based on channel resolution)"
+ },
+ { sig = "clock = #adc.setclock#( id, clock, timer_id )",
+ desc = "Set the frequency (number of samples per second) at which voltages will be converted into samples.",
+ args =
+ {
+ "$id$ - ADC channel ID.",
+ "$clock$ - frequency to acquire samples at in Hz (number of samples per second), 0 to acquire as fast as possible.",
+ "$timer_id$ - Timer channel ID to use to control ADC conversion. <strong>Note:</strong> At this time, a timer selection will apply to all channels on a given ADC peripheral."
+ },
+ ret = "$clock$ - actual acquisition frequency to be used"
+ },
+ { sig = "status = #adc.isdone#( id )",
+ desc = "Check whether samples are still being acquired on a channel.",
+ args =
+ {
+ "$id$ - ADC channel ID."
+ },
+ ret = "$status$ - 1 if no samples are being acquired, 0 if samples are pending acquisition."
+ },
+ { sig = "#adc.setblocking#( id, mode )",
+ desc = "Set whether or not functions that request converted samples should wait for requested samples or return immediately with what is available.",
+ args =
+ {
+ "$id$ - ADC channel ID.",
+ "$mode$ - 1 if requests to get samples should block until requested samples are available or sampling has completed, 0 to return immediately with available samples"
+ },
+ },
+ { sig = "#adc.setsmoothing#( id, length )",
+ desc = "Set the length of the moving average filter. When $length$ is greater than 1, samples pulled from the conversion buffer will be averaged with the preceding $length$ - 1 buffered values.",
+ args =
+ {
+ "$id$ - ADC channel ID.",
+ "$length$ - number of preceding samples to include in moving average filter (must be a power of 2). If 1, filter is disabled. When enabled, a filter buffer is filled before the main conversion buffer, so that averages are always over the same number of samples."
+ }
+ }
+ }
+}
+
+data_pt =
+{
+
+ -- Title
+ title = "eLua reference manual - ADC",
+
+ -- Menu name
+ menu_name = "adc",
+
+ -- Overview
+ overview = [[This module contains functions that access analog to digital converter (ADC) peripherals.</p>
+ <p>When utilizing this module, acquiring ADC data is a two step process: requesting sample conversions (using $adc.sample$) and extraction of conversion results from a conversion buffer (using $adc.getsample$, $adc.getsamples$ or $adc.insertsamples$). Various configuration parameters are available to set conversion rate, how results are extracted from the buffer and how these results are processed prior to extraction.</p>
+ <p>This module can be utilized if the device in use has a supported ADC peripheral (see @status.html at status@ for details) and if ADC functionality is enabled at build time (see @building.html at building@).]],
+
+ -- Functions
+ funcs =
+ {
+ { sig = "#adc.sample#( id, count )",
+ desc = "Initiate conversion and buffering of samples on an ADC channel.",
+ args =
+ {
+ "$id$ - ADC channel ID. Optionally, this may be a table containing a list of channel IDs (i.e.: {0, 2, 3}), allowing synchronization of acquisition. NOTE: This acceptance of mixed types is only for the sample function.",
+ "$count$ - number of samples to acquire and place in buffer."
+ }
+ },
+ { sig = "sample = #adc.getsample#( id )",
+ desc = "Get a single conversion value from the buffer associated with a given channel.",
+ args =
+ {
+ "$id$ - ADC channel ID."
+ },
+ ret = "$sample$ - numeric value of conversion, or nil if sample was not available."
+ },
+ { sig = "samples = #adc.getsamples#( id, count )",
+ desc = "Get multiple conversion values from the buffer associated with a given channel.",
+ args =
+ {
+ "$id$ - ADC channel ID.",
+ "$count$ - optional parameter to indicate number of samples to return. If not included, all available samples are returned."
+ },
+ ret = "$samples$ - table containing integer conversion values. If not enough samples are available, remaining indices will be nil."
+ },
+ { sig = "#adc.insertsamples#( id, table, idx, count )",
+ desc = "Get multiple conversion values from a channel's buffer, and write them into a table.",
+ args =
+ {
+ "$id$ - ADC channel ID.",
+ "$table$ - table to write samples to. Values at $table$[$idx$] to $table$[$idx$ + $count$ -1] will be overwritten with samples (or nil if not enough samples are available).",
+ "$idx$ - first index to use in the table for writing samples.",
+ "$count$ - number of samples to return. If not enough samples are available (after blocking, if enabled) remaining values will be nil."
+ }
+ },
+ { sig = "maxval = #adc.maxval#( id )",
+ desc = "Get the maximum value (corresponding to the maximum voltage) that can be returned on a given channel.",
+ args =
+ {
+ "$id$ - ADC channel ID."
+ },
+ ret = "$maxval$ - maximum integer conversion value (based on channel resolution)"
+ },
+ { sig = "clock = #adc.setclock#( id, clock, timer_id )",
+ desc = "Set the frequency (number of samples per second) at which voltages will be converted into samples.",
+ args =
+ {
+ "$id$ - ADC channel ID.",
+ "$clock$ - frequency to acquire samples at in Hz (number of samples per second), 0 to acquire as fast as possible.",
+ "$timer_id$ - Timer channel ID to use to control ADC conversion. <strong>Note:</strong> At this time, a timer selection will apply to all channels on a given ADC peripheral."
+ },
+ ret = "$clock$ - actual acquisition frequency to be used"
+ },
+ { sig = "status = #adc.isdone#( id )",
+ desc = "Check whether samples are still being acquired on a channel.",
+ args =
+ {
+ "$id$ - ADC channel ID."
+ },
+ ret = "$status$ - 1 if no samples are being acquired, 0 if samples are pending acquisition."
+ },
+ { sig = "#adc.setblocking#( id, mode )",
+ desc = "Set whether or not functions that request converted samples should wait for requested samples or return immediately with what is available.",
+ args =
+ {
+ "$id$ - ADC channel ID.",
+ "$mode$ - 1 if requests to get samples should block until requested samples are available or sampling has completed, 0 to return immediately with available samples"
+ },
+ },
+ { sig = "#adc.setsmoothing#( id, length )",
+ desc = "Set the length of the moving average filter. When $length$ is greater than 1, samples pulled from the conversion buffer will be averaged with the preceding $length$ - 1 buffered values.",
+ args =
+ {
+ "$id$ - ADC channel ID.",
+ "$length$ - number of preceding samples to include in moving average filter (must be a power of 2). If 1, filter is disabled. When enabled, a filter buffer is filled before the main conversion buffer, so that averages are always over the same number of samples."
+ }
+ }
+ }
+}
+
Added: branches/eagle_mmc/doc/eluadoc/refman_gen_bit.lua
===================================================================
--- branches/eagle_mmc/doc/eluadoc/refman_gen_bit.lua 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/eluadoc/refman_gen_bit.lua 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,276 @@
+-- eLua reference manual - bit module
+
+data_en =
+{
+
+ -- Title
+ title = "eLua reference manual - bit module",
+
+ -- Menu name
+ menu_name = "bit",
+
+ -- Overview
+ overview = [[Since Lua doesn't have built-in capabilities for bit operations, the $bit$ module was added to eLua to fill this gap. It is based on the ^http://luaforge.net/projects/bitlib^bitlib^
+ library written by Reuben Thomas (slightly adapted to eLua) and provides basic bit operations (like setting and clearing bits) and bitwise operations.]],
+
+ -- Functions
+ funcs =
+ {
+ { sig = "number = #bit.bit#( position )",
+ desc = "Generate a number with a 1 bit (used for mask generation). Equivalent to %1 <<<< position% in C.",
+ args = "$position$ - position of the bit that will be set to 1.",
+ ret = "$number$ - a number with only one 1 bit at $position$ (the rest are set to 0."
+ },
+
+ { sig = "flag = #bit.isset#( value, position )",
+ desc = "Test if a given bit is set.",
+ args =
+ {
+ "$value$ - the value to test.",
+ "$position$ - bit position to test."
+ },
+ ret = "$number$ - 1 if the bit at the given position is 1, 0 otherwise."
+ },
+
+ { sig = "flag = #bit.isclear#( value, position )",
+ desc = "Test if a given bit is cleared.",
+ args =
+ {
+ "$value$ - the value to test.",
+ "$position$ - bit position to test."
+ },
+ ret = "$number$ - 1 if the bit at the given position is 0, 0 othewise."
+ },
+
+ { sig = "number = #bit.set#( value, pos1, pos2, ..., posn )",
+ desc = "Set bits in a number.",
+ args =
+ {
+ "$value$ - the base number.",
+ "$pos1$ - position of the first bit to set.",
+ "$pos2$ - position of the second bit to set.",
+ "$posn$ - position of the nth bit to set."
+ },
+ ret = "$number$ - the number with the bit(s) set in the given position(s)."
+ },
+
+ { sig = "number = #bit.clear#( value, pos1, pos2, ..., posn )",
+ desc = "Clear bits in a number.",
+ args =
+ {
+ "$value$ - the base number.",
+ "$pos1$ - position of the first bit to clear.",
+ "$pos2$ - position of the second bit to clear.",
+ "$posn$ - position of thet nth bit to clear.",
+ },
+ ret = "$number$ - the number with the bit(s) cleared in the given position(s)."
+ },
+
+ { sig = "number = #bit.bnot#( value )",
+ desc = "Bitwise negation, equivalent to %~~value% in C.",
+ args = "$value$ - the number to negate.",
+ ret = "$number$ - the bitwise negated value of the number.",
+ },
+
+ { sig = "number = #bit.band#( val1, val2, ... valn )",
+ desc = "Bitwise AND, equivalent to %val1 & val2 & ... & valn% in C.",
+ args =
+ {
+ "$val1$ - first AND argument.",
+ "$val2$ - second AND argument.",
+ "$valn$ - nth AND argument.",
+ },
+ ret = "$number$ - the bitwise AND of all the arguments."
+ },
+
+ { sig = "number = #bit.bor#( val1, val2, ... valn )",
+ desc = "Bitwise OR, equivalent to %val1 | val2 | ... | valn% in C.",
+ args =
+ {
+ "$val1$ - first OR argument.",
+ "$val2$ - second OR argument.",
+ "$valn$ - nth OR argument."
+ },
+ ret = "$number$ - the bitwise OR of all the arguments."
+ },
+
+ { sig = "number = #bit.bxor#( val1, val2, ... valn )",
+ desc = "Bitwise exclusive OR (XOR), equivalent to %val1 ^^ val2 ^^ ... ^^ valn% in C.",
+ args =
+ {
+ "$val1$ - first XOR argument.",
+ "$val2$ - second XOR argument.",
+ "$valn$ - nth XOR argument."
+ },
+ ret = "$number$ - the bitwise exclusive OR of all the arguments."
+ },
+
+ { sig = "number = #bit.lshift#( value, shift )",
+ desc = "Left-shift a number, equivalent to %value << shift% in C.",
+ args =
+ {
+ "$value$ - the value to shift.",
+ "$shift$ - positions to shift.",
+ },
+ ret = "$number$ - the number shifted left",
+ },
+
+ { sig = "number = #bit.rshift#( value, shift )",
+ desc = "Logical right shift a number, equivalent to %( unsigned )value >>>> shift% in C.",
+ args =
+ {
+ "$value$ - the value to shift.",
+ "$shift$ - positions to shift.",
+ },
+ ret = "$number$ - the number shifted right (logically)."
+ },
+
+ { sig = "number = #bit.arshift#( value, shift )",
+ desc = "Arithmetic right shift a number equivalent to %value >>>> shift% in C.",
+ args =
+ {
+ "$value$ - the value to shift.",
+ "$shift$ - positions to shift."
+ },
+ ret = "$number$ - the number shifted right (arithmetically)."
+ }
+ }
+}
+
+data_pt =
+{
+
+ -- Title
+ title = "eLua reference manual - bit module",
+
+ -- Menu name
+ menu_name = "bit",
+
+ -- Overview
+ overview = [[Since Lua doesn't have built-in capabilities for bit operations, the $bit$ module was added to eLua to fill this gap. It is based on the ^http://luaforge.net/projects/bitlib^bitlib^
+ library written by Reuben Thomas (slightly adapted to eLua) and provides basic bit operations (like setting and clearing bits) and bitwise operations.]],
+
+ -- Functions
+ funcs =
+ {
+ { sig = "number = #bit.bit#( position )",
+ desc = "Generate a number with a 1 bit (used for mask generation). Equivalent to %1 <<<< position% in C.",
+ args = "$position$ - position of the bit that will be set to 1.",
+ ret = "$number$ - a number with only one 1 bit at $position$ (the rest are set to 0."
+ },
+
+ { sig = "flag = #bit.isset#( value, position )",
+ desc = "Test if a given bit is set.",
+ args =
+ {
+ "$value$ - the value to test.",
+ "$position$ - bit position to test."
+ },
+ ret = "$number$ - 1 if the bit at the given position is 1, 0 otherwise."
+ },
+
+ { sig = "flag = #bit.isclear#( value, position )",
+ desc = "Test if a given bit is cleared.",
+ args =
+ {
+ "$value$ - the value to test.",
+ "$position$ - bit position to test."
+ },
+ ret = "$number$ - 1 if the bit at the given position is 0, 0 othewise."
+ },
+
+ { sig = "number = #bit.set#( value, pos1, pos2, ..., posn )",
+ desc = "Set bits in a number.",
+ args =
+ {
+ "$value$ - the base number.",
+ "$pos1$ - position of the first bit to set.",
+ "$pos2$ - position of the second bit to set.",
+ "$posn$ - position of the nth bit to set."
+ },
+ ret = "$number$ - the number with the bit(s) set in the given position(s)."
+ },
+
+ { sig = "number = #bit.clear#( value, pos1, pos2, ..., posn )",
+ desc = "Clear bits in a number.",
+ args =
+ {
+ "$value$ - the base number.",
+ "$pos1$ - position of the first bit to clear.",
+ "$pos2$ - position of the second bit to clear.",
+ "$posn$ - position of thet nth bit to clear.",
+ },
+ ret = "$number$ - the number with the bit(s) cleared in the given position(s)."
+ },
+
+ { sig = "number = #bit.bnot#( value )",
+ desc = "Bitwise negation, equivalent to %~~value% in C.",
+ args = "$value$ - the number to negate.",
+ ret = "$number$ - the bitwise negated value of the number.",
+ },
+
+ { sig = "number = #bit.band#( val1, val2, ... valn )",
+ desc = "Bitwise AND, equivalent to %val1 & val2 & ... & valn% in C.",
+ args =
+ {
+ "$val1$ - first AND argument.",
+ "$val2$ - second AND argument.",
+ "$valn$ - nth AND argument.",
+ },
+ ret = "$number$ - the bitwise AND of all the arguments."
+ },
+
+ { sig = "number = #bit.bor#( val1, val2, ... valn )",
+ desc = "Bitwise OR, equivalent to %val1 | val2 | ... | valn% in C.",
+ args =
+ {
+ "$val1$ - first OR argument.",
+ "$val2$ - second OR argument.",
+ "$valn$ - nth OR argument."
+ },
+ ret = "$number$ - the bitwise OR of all the arguments."
+ },
+
+ { sig = "number = #bit.bxor#( val1, val2, ... valn )",
+ desc = "Bitwise exclusive OR (XOR), equivalent to %val1 ^^ val2 ^^ ... ^^ valn% in C.",
+ args =
+ {
+ "$val1$ - first XOR argument.",
+ "$val2$ - second XOR argument.",
+ "$valn$ - nth XOR argument."
+ },
+ ret = "$number$ - the bitwise exclusive OR of all the arguments."
+ },
+
+ { sig = "number = #bit.lshift#( value, shift )",
+ desc = "Left-shift a number, equivalent to %value << shift% in C.",
+ args =
+ {
+ "$value$ - the value to shift.",
+ "$shift$ - positions to shift.",
+ },
+ ret = "$number$ - the number shifted left",
+ },
+
+ { sig = "number = #bit.rshift#( value, shift )",
+ desc = "Logical right shift a number, equivalent to %( unsigned )value >>>> shift% in C.",
+ args =
+ {
+ "$value$ - the value to shift.",
+ "$shift$ - positions to shift.",
+ },
+ ret = "$number$ - the number shifted right (logically)."
+ },
+
+ { sig = "number = #bit.arshift#( value, shift )",
+ desc = "Arithmetic right shift a number equivalent to %value >>>> shift% in C.",
+ args =
+ {
+ "$value$ - the value to shift.",
+ "$shift$ - positions to shift."
+ },
+ ret = "$number$ - the number shifted right (arithmetically)."
+ }
+ }
+}
+
Added: branches/eagle_mmc/doc/eluadoc/refman_gen_cpu.lua
===================================================================
--- branches/eagle_mmc/doc/eluadoc/refman_gen_cpu.lua 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/eluadoc/refman_gen_cpu.lua 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,198 @@
+-- eLua reference manual - CPU module
+
+data_en =
+{
+
+ -- Title
+ title = "eLua reference manual - CPU module",
+
+ -- Menu name
+ menu_name = "cpu",
+
+ -- Overview
+ overview = [[This module deals with low-level access to CPU (and related modules) functionality, such as reading and writing memory, or
+ enabling and disabling interrupts. It also offers access to platform specific CPU-related constants using a special macro defined in the
+ platform's $platform_conf.h$ file, as exaplained @#cpu_constants at here@.]],
+
+ -- Data structures, constants and types
+ structures =
+ {
+ { text = [[cpu.INT_GPIOA
+cpu.INT_GPIOB
+.............
+cpu.INT_UDMA]],
+ name = "CPU constants",
+ desc = [[eLua has a mechanism that lets the user export an unlimited number of constants to the $cpu$ module. Although in theory any kind of constant can be exposed by this module,
+one should only use constants related to the CPU and its subsystems (as shown above, where a number of CPU specific interrupt masks are exposed to Lua using this mechanism). To use this
+mechanism, just declare the $PLATFORM_CPU_CONSTANTS$ macro in your platform's $platform_conf.h$ file and list all your constants as part of this macro, each enclosed in a special macro called
+$_C$. For example, to get the constants listed above declare your $PLATFORM_CPU_CONSTANTS$ macro like this:</p>
+~#define PLATFORM_CPU_CONSTANTS\
+ _C( INT_GPIOA ),\
+ _C( INT_GPIOB ),\
+ .................
+ _C( INT_UDMA )~
+<p>It's worth to note that adding more constants does not increas RAM usage, only Flash usage, so you can expose as much constants as you need without worrying about RAM consumption.]]
+ },
+ },
+
+ -- Functions
+ funcs =
+ {
+ { sig = "#cpu.w32#( address, data )",
+ desc = "Writes a 32-bit word to memory.",
+ args =
+ {
+ "$address$ - the memory address.",
+ "$data$ - the 32-bit data to write."
+ },
+ },
+
+ { sig = "data = #cpu.r32#( address )",
+ desc = "Read a 32-bit word from memory.",
+ args = "$address$ - the memory address.",
+ ret = "$data$ - the 32-bit word read from memory."
+ },
+
+ { sig = "#cpu.w16#( address, data )",
+ desc = "Writes a 16-bit word to memory.",
+ args =
+ {
+ "$address$ - the memory address.",
+ "$data$ - the 16-bit data to write."
+ },
+ },
+
+ { sig = "data = #cpu.r16#( address )",
+ desc = "Reads a 16-bit word from memory.",
+ args = "$address$ - the memory address.",
+ ret = "$data$ - the 16-bit word read from memory."
+ },
+
+ { sig = "#cpu.w8#( address, data )",
+ desc = "Writes a byte to memory.",
+ args =
+ {
+ "$address$ - the memory address.",
+ "$data$ - the byte to write."
+ }
+ },
+
+ { sig = "data = #cpu.r8#( address )",
+ desc = "Reads a byte from memory.",
+ args = "$address$ - the memory address",
+ ret = "$data$ - the byte read from memory."
+ },
+
+ { sig = "#cpu.cli#()",
+ desc = "Disable CPU interrupts."
+ },
+
+ { sig = "#cpu.sei#()",
+ desc = "Enable CPU interrupts."
+ },
+
+ { sig = "clock = #cpu.clock#()",
+ desc = "Get the CPU core frequency.",
+ ret = "$clock$ - the CPU clock (in Hertz)."
+ }
+ },
+}
+
+data_pt =
+{
+
+ -- Title
+ title = "eLua reference manual - CPU module",
+
+ -- Menu name
+ menu_name = "cpu",
+
+ -- Overview
+ overview = [[This module deals with low-level access to CPU (and related modules) functionality, such as reading and writing memory, or
+ enabling and disabling interrupts. It also offers access to platform specific CPU-related constants using a special macro defined in the
+ platform's $platform_conf.h$ file, as exaplained @#cpu_constants at here@.]],
+
+ -- Data structures, constants and types
+ structures =
+ {
+ { text = [[cpu.INT_GPIOA
+cpu.INT_GPIOB
+.............
+cpu.INT_UDMA]],
+ name = "CPU constants",
+ desc = [[eLua has a mechanism that lets the user export an unlimited number of constants to the $cpu$ module. Although in theory any kind of constant can be exposed by this module,
+one should only use constants related to the CPU and its subsystems (as shown above, where a number of CPU specific interrupt masks are exposed to Lua using this mechanism). To use this
+mechanism, just declare the $PLATFORM_CPU_CONSTANTS$ macro in your platform's $platform_conf.h$ file and list all your constants as part of this macro, each enclosed in a special macro called
+$_C$. For example, to get the constants listed above declare your $PLATFORM_CPU_CONSTANTS$ macro like this:</p>
+~#define PLATFORM_CPU_CONSTANTS\
+ _C( INT_GPIOA ),\
+ _C( INT_GPIOB ),\
+ .................
+ _C( INT_UDMA )~
+<p>It's worth to note that adding more constants does not increas RAM usage, only Flash usage, so you can expose as much constants as you need without worrying about RAM consumption.]]
+ },
+ },
+
+ -- Functions
+ funcs =
+ {
+ { sig = "#cpu.w32#( address, data )",
+ desc = "Writes a 32-bit word to memory.",
+ args =
+ {
+ "$address$ - the memory address.",
+ "$data$ - the 32-bit data to write."
+ },
+ },
+
+ { sig = "data = #cpu.r32#( address )",
+ desc = "Read a 32-bit word from memory.",
+ args = "$address$ - the memory address.",
+ ret = "$data$ - the 32-bit word read from memory."
+ },
+
+ { sig = "#cpu.w16#( address, data )",
+ desc = "Writes a 16-bit word to memory.",
+ args =
+ {
+ "$address$ - the memory address.",
+ "$data$ - the 16-bit data to write."
+ },
+ },
+
+ { sig = "data = #cpu.r16#( address )",
+ desc = "Reads a 16-bit word from memory.",
+ args = "$address$ - the memory address.",
+ ret = "$data$ - the 16-bit word read from memory."
+ },
+
+ { sig = "#cpu.w8#( address, data )",
+ desc = "Writes a byte to memory.",
+ args =
+ {
+ "$address$ - the memory address.",
+ "$data$ - the byte to write."
+ }
+ },
+
+ { sig = "data = #cpu.r8#( address )",
+ desc = "Reads a byte from memory.",
+ args = "$address$ - the memory address",
+ ret = "$data$ - the byte read from memory."
+ },
+
+ { sig = "#cpu.cli#()",
+ desc = "Disable CPU interrupts."
+ },
+
+ { sig = "#cpu.sei#()",
+ desc = "Enable CPU interrupts."
+ },
+
+ { sig = "clock = #cpu.clock#()",
+ desc = "Get the CPU core frequency.",
+ ret = "$clock$ - the CPU clock (in Hertz)."
+ }
+ },
+}
+
Added: branches/eagle_mmc/doc/eluadoc/refman_gen_net.lua
===================================================================
--- branches/eagle_mmc/doc/eluadoc/refman_gen_net.lua 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/eluadoc/refman_gen_net.lua 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,322 @@
+-- eLua reference manual - net module
+
+data_en =
+{
+
+ -- Title
+ title = "eLua reference manual - net module",
+
+ -- Menu name
+ menu_name = "net",
+
+ -- Overview
+ overview = [[This module contains functions for accessing a TCP/IP network from eLua. It can be enabled only if networking support is also enabled
+ (see @building.html at building@ for details).</p>
+ <p><span class="warning">NOTE:</span> TCP/IP support is $experimental$ in eLua. While functional, it's still slow and suffers from a number of
+ other issues. It will most likely change a lot in the future, so expect major changes to this module as well.</p>
+ <p><span class="warning">NOTE:</span> currently, only TCP sockets are supported by eLua.]],
+
+ -- Structures
+ structures =
+ {
+ { text = [[// eLua net error codes
+enum
+{
+ ELUA_NET_ERR_OK = 0, // exported as $net.ERR_OK$
+ ELUA_NET_ERR_TIMEDOUT, // exported as $net.ERR_TIMEDOUT$
+ ELUA_NET_ERR_CLOSED, // exported as $net.ERR_CLOSED$
+ ELUA_NET_ERR_ABORTED, // exported as $net.ERR_ABORTED$
+ ELUA_NET_ERR_OVERFLOW // exported as $net.ERR_OVERFLOW$
+};]],
+ name = "Error codes",
+ desc = "These are the error codes defined by the eLua networking layer and they are also returned by a number of functions in this module.",
+ }
+ },
+
+ -- Functions
+ funcs =
+ {
+ { sig = "ip = #net.packip#( ip1, ip2, ip3, ip4 )",
+ desc = [[Returns an internal representation of an IP address that can be used with all function from the $net$ module that expect an IP address
+argument. The IP is considered to be in the format %ip1.ip2.ip3.ip4%.]],
+ args =
+ {
+ "$ip1$ - the first part of the IP address.",
+ "$ip2$ - the second part of the IP address.",
+ "$ip3$ - the third part of the IP address.",
+ "$ip4$ - the fourth part of the IP address."
+ },
+ ret = "An integer that encodes the IP address in an internal format."
+ },
+
+ { sig = "ip = #net.packip#( 'ip' )",
+ desc = [[Returns an internal representation of an IP address that can be used with all function from the $net$ module that expect an IP address
+argument. The IP is given as a string.]],
+ args = "$ip$ - the IP address in string format.",
+ ret = "An integer that encodes the IP address in an internal format."
+ },
+
+ { sig = "ip1, ip2, ip3, ip4 = #net.unpackip#( ip, '*n' )",
+ desc = "Returns an unpacked representation of an IP address encoded by @#net.packip at net.packip@.",
+ args = "$ip$ - the encoded IP address.",
+ ret =
+ {
+ "$ip1$ - the first part of the IP address.",
+ "$ip2$ - the second part of the IP address.",
+ "$ip3$ - the third part of the IP address.",
+ "$ip4$ - the fourth part of the IP address."
+ }
+ },
+
+ { sig = "ip = #net.unpackip#( ip, '*s' )",
+ desc = "Returns an unpacked representation of an IP address encoded by @#net.packip at net.packip@.",
+ args = "$ip$ - the encoded IP address.",
+ ret = "The IP address in string format."
+ },
+
+
+ { sig = "ip = #net.lookup#( hostname )",
+ desc = "Does a DNS lookup.",
+ args = "$hostname$ - the name of the computer.",
+ ret = "The IP address of the computer."
+ },
+
+ { sig = "socket = #net.socket#( type )",
+ desc = "Create a socket for TCP/IP communication.",
+ args = [[$type$ - can be either $net.SOCK_STREAM$ for TCP sockets or $net.SOCK_DGRAM$ for UDP sockets (<span class="warning">not yet supported</span>).]],
+ ret = "The socket that will be used in subsequent operations."
+ },
+
+ { sig = "res = #net.close#( socket )",
+ desc = "Close a socket.",
+ args = "$socket$ - the socket to close.",
+ ret = "An error code, as defined @#error_codes at here@."
+ },
+
+ { sig = "err = #net.connect#( sock, ip, port )",
+ desc = "Connect a socket to a remote system.",
+ args =
+ {
+ "$sock$ - a socket obtained from @#net.socket at net.socket@.",
+ "$ip$ - the IP address obtained from @#net.packip at net.packip@.",
+ "$port$ - the port to connecto to."
+ },
+ ret = "$err$ - the error code, as defined @#error_codes at here@."
+ },
+
+ { sig = "socket, remoteip, err = #net.accept#( port, [timer_id, timeout] )",
+ desc = "Accept a connection from a remote system with an optional timeout.",
+ args =
+ {
+ "$port$ - the port to wait for connections from the remote system.",
+ [[$timer_id (optional)$ - the timer ID of the timer used to timeout the accept function after a specified time. If this is specified, $timeout$ must also
+be specified.]],
+ [[$timeout (optional)$ - the timeout after which the accept function returns if no connection was requested. If this is specified, $timer_id$ must also
+be specified.]]
+ },
+ ret =
+ {
+ "$socket$ - the socket created after accepting the remote connection.",
+ "$remoteip$ - the IP of the remote system.",
+ "$err$ - an error code, as defined @#error_codes at here@."
+ }
+ },
+
+ { sig = "res, err = #net.send#( sock, str )",
+ desc = "Send data to a socket.",
+ args =
+ {
+ "$sock$ - the socket.",
+ "$str$ - the data to send."
+ },
+ ret =
+ {
+ "$res$ - the number of bytes actually sent or -1 for error.",
+ "$err$ - the error code, as defined @#error_codes at here@."
+ }
+ },
+
+ { sig = "res, err = #net.recv#( sock, format, [timer_id, timeout] )",
+ desc = "Read data from a socket.",
+ args =
+ {
+ "$sock$ - the socket.",
+ [[$format$ - how to read the data. This can be either:
+<ul>
+ <li>$"*l"$: read a line (until the next '\n' character).</li>
+ <li>$an integer$: read up to that many bytes.</li>
+</ul>]],
+ [[$timer_id (optional)$ - the timer ID of the timer used to timeout the recv function after a specified time. If this is specified, $timeout$ must also
+be specified.]],
+ [[$timeout (optional)$ - the timeout after which the recv function returns if no connection was requested. If this is specified, $timer_id$ must also
+be specified.]]
+ },
+ ret =
+ {
+ "$res$ - the number of bytes read.",
+ "$err$ - the error code, as defined @#error_codes at here@."
+ }
+ }
+ },
+}
+
+data_pt =
+{
+
+ -- Title
+ title = "eLua reference manual - net module",
+
+ -- Menu name
+ menu_name = "net",
+
+ -- Overview
+ overview = [[This module contains functions for accessing a TCP/IP network from eLua. It can be enabled only if networking support is also enabled
+ (see @building.html at building@ for details).</p>
+ <p><span class="warning">NOTE:</span> TCP/IP support is $experimental$ in eLua. While functional, it's still slow and suffers from a number of
+ other issues. It will most likely change a lot in the future, so expect major changes to this module as well.</p>
+ <p><span class="warning">NOTE:</span> currently, only TCP sockets are supported by eLua.]],
+
+ -- Structures
+ structures =
+ {
+ { text = [[// eLua net error codes
+enum
+{
+ ELUA_NET_ERR_OK = 0, // exported as $net.ERR_OK$
+ ELUA_NET_ERR_TIMEDOUT, // exported as $net.ERR_TIMEDOUT$
+ ELUA_NET_ERR_CLOSED, // exported as $net.ERR_CLOSED$
+ ELUA_NET_ERR_ABORTED, // exported as $net.ERR_ABORTED$
+ ELUA_NET_ERR_OVERFLOW // exported as $net.ERR_OVERFLOW$
+};]],
+ name = "Error codes",
+ desc = "These are the error codes defined by the eLua networking layer and they are also returned by a number of functions in this module.",
+ }
+ },
+
+ -- Functions
+ funcs =
+ {
+ { sig = "ip = #net.packip#( ip1, ip2, ip3, ip4 )",
+ desc = [[Returns an internal representation of an IP address that can be used with all function from the $net$ module that expect an IP address
+argument. The IP is considered to be in the format %ip1.ip2.ip3.ip4%.]],
+ args =
+ {
+ "$ip1$ - the first part of the IP address.",
+ "$ip2$ - the second part of the IP address.",
+ "$ip3$ - the third part of the IP address.",
+ "$ip4$ - the fourth part of the IP address."
+ },
+ ret = "An integer that encodes the IP address in an internal format."
+ },
+
+ { sig = "ip = #net.packip#( 'ip' )",
+ desc = [[Returns an internal representation of an IP address that can be used with all function from the $net$ module that expect an IP address
+argument. The IP is given as a string.]],
+ args = "$ip$ - the IP address in string format.",
+ ret = "An integer that encodes the IP address in an internal format."
+ },
+
+ { sig = "ip1, ip2, ip3, ip4 = #net.unpackip#( ip, '*n' )",
+ desc = "Returns an unpacked representation of an IP address encoded by @#net.packip at net.packip@.",
+ args = "$ip$ - the encoded IP address.",
+ ret =
+ {
+ "$ip1$ - the first part of the IP address.",
+ "$ip2$ - the second part of the IP address.",
+ "$ip3$ - the third part of the IP address.",
+ "$ip4$ - the fourth part of the IP address."
+ }
+ },
+
+ { sig = "ip = #net.unpackip#( ip, '*s' )",
+ desc = "Returns an unpacked representation of an IP address encoded by @#net.packip at net.packip@.",
+ args = "$ip$ - the encoded IP address.",
+ ret = "The IP address in string format."
+ },
+
+
+ { sig = "ip = #net.lookup#( hostname )",
+ desc = "Does a DNS lookup.",
+ args = "$hostname$ - the name of the computer.",
+ ret = "The IP address of the computer."
+ },
+
+ { sig = "socket = #net.socket#( type )",
+ desc = "Create a socket for TCP/IP communication.",
+ args = [[$type$ - can be either $net.SOCK_STREAM$ for TCP sockets or $net.SOCK_DGRAM$ for UDP sockets (<span class="warning">not yet supported</span>).]],
+ ret = "The socket that will be used in subsequent operations."
+ },
+
+ { sig = "res = #net.close#( socket )",
+ desc = "Close a socket.",
+ args = "$socket$ - the socket to close.",
+ ret = "An error code, as defined @#error_codes at here@."
+ },
+
+ { sig = "err = #net.connect#( sock, ip, port )",
+ desc = "Connect a socket to a remote system.",
+ args =
+ {
+ "$sock$ - a socket obtained from @#net.socket at net.socket@.",
+ "$ip$ - the IP address obtained from @#net.packip at net.packip@.",
+ "$port$ - the port to connecto to."
+ },
+ ret = "$err$ - the error code, as defined @#error_codes at here@."
+ },
+
+ { sig = "socket, remoteip, err = #net.accept#( port, [timer_id, timeout] )",
+ desc = "Accept a connection from a remote system with an optional timeout.",
+ args =
+ {
+ "$port$ - the port to wait for connections from the remote system.",
+ [[$timer_id (optional)$ - the timer ID of the timer used to timeout the accept function after a specified time. If this is specified, $timeout$ must also
+be specified.]],
+ [[$timeout (optional)$ - the timeout after which the accept function returns if no connection was requested. If this is specified, $timer_id$ must also
+be specified.]]
+ },
+ ret =
+ {
+ "$socket$ - the socket created after accepting the remote connection.",
+ "$remoteip$ - the IP of the remote system.",
+ "$err$ - an error code, as defined @#error_codes at here@."
+ }
+ },
+
+ { sig = "res, err = #net.send#( sock, str )",
+ desc = "Send data to a socket.",
+ args =
+ {
+ "$sock$ - the socket.",
+ "$str$ - the data to send."
+ },
+ ret =
+ {
+ "$res$ - the number of bytes actually sent or -1 for error.",
+ "$err$ - the error code, as defined @#error_codes at here@."
+ }
+ },
+
+ { sig = "res, err = #net.recv#( sock, format, [timer_id, timeout] )",
+ desc = "Read data from a socket.",
+ args =
+ {
+ "$sock$ - the socket.",
+ [[$format$ - how to read the data. This can be either:
+<ul>
+ <li>$"*l"$: read a line (until the next '\n' character).</li>
+ <li>$an integer$: read up to that many bytes.</li>
+</ul>]],
+ [[$timer_id (optional)$ - the timer ID of the timer used to timeout the recv function after a specified time. If this is specified, $timeout$ must also
+be specified.]],
+ [[$timeout (optional)$ - the timeout after which the recv function returns if no connection was requested. If this is specified, $timer_id$ must also
+be specified.]]
+ },
+ ret =
+ {
+ "$res$ - the number of bytes read.",
+ "$err$ - the error code, as defined @#error_codes at here@."
+ }
+ }
+ },
+}
+
Added: branches/eagle_mmc/doc/eluadoc/refman_gen_pack.lua
===================================================================
--- branches/eagle_mmc/doc/eluadoc/refman_gen_pack.lua 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/eluadoc/refman_gen_pack.lua 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,270 @@
+-- eLua reference manual - pack
+
+data_en =
+{
+
+ -- Title
+ title = "eLua reference manual - pack",
+
+ -- Menu name
+ menu_name = "pack",
+
+ -- Overview
+ overview = [[This module allows for arbitrary packing of data into Lua strings and unpacking data from Lua strings. In this way, a string can be used to store data in a platform-indepdendent
+manner. It is based on the ^http://www.tecgraf.puc-rio.br/~~lhf/ftp/lua/#lpack^lpack^ module from Luiz Henrique de Figueiredo (with some minor tweaks). </p>
+<p>Both methods of this module (@#pack at pack@ and @#unpack at unpack@) use a $format string$ to describe how to pack/unpack the data. The format string contains one or more $data specifiers$, each
+data specifier is applied to a single variable that must be packed/unpacked. The data specifier has the following general format:</p>
+~[endianness]<<format specifier>>[count]~
+<p>where:</p>
+<ul>
+ <li>$endianness$ is an optional endian flags that specifies how the numbers that are to be packed/unpacked are stored in memory. It can be either:
+ <ol>
+ <li>$'<<'$ for little endian.</li>
+ <li>$'>>'$ for big endian.</li>
+ <li>$'='$ for native endian (the platform's endian order, default).</li>
+ </ol></li>
+ <li>$format specifier$ describes what kind of variable will be packed/unpacked. $The format specifier is case-sensitive$. The possible values of this parameter are summarized in the table below:
+ <table class="table_center" style="margin-top: 4px; margin-bottom: 4px;">
+ <tbody>
+ <tr>
+ <th>Format specifier</th>
+ <th>Corresponding variable type</th>
+ </tr>
+ <tr>
+ <td>'z'</td>
+ <td>zero-terminated string</td>
+ </tr>
+ <tr>
+ <td>'p' </td>
+ <td>string preceded by length byte</td>
+ </tr>
+ <tr>
+ <td>'P' </td>
+ <td>string preceded by length word</td>
+ </tr>
+ <tr>
+ <td>'a' </td>
+ <td>string preceded by length size_t</td>
+ </tr>
+ <tr>
+ <td>'A' </td>
+ <td>string</td>
+ </tr>
+ <tr>
+ <td>'f' </td>
+ <td>float</td>
+ </tr>
+ <tr>
+ <td>'d' </td>
+ <td>double</td>
+ </tr>
+ <tr>
+ <td>'n' </td>
+ <td>Lua number</td>
+ </tr>
+ <tr>
+ <td>'c' </td>
+ <td>char</td>
+ </tr>
+ <tr>
+ <td>'b' </td>
+ <td>byte = unsigned char</td>
+ </tr>
+ <tr>
+ <td>'h' </td>
+ <td>short</td>
+ </tr>
+ <tr>
+ <td>'H' </td>
+ <td>unsigned short</td>
+ </tr>
+ <tr>
+ <td>'i' </td>
+ <td>int</td>
+ </tr>
+ <tr>
+ <td>'I' </td>
+ <td>unsigned int</td>
+ </tr>
+ <tr>
+ <td>'l' </td>
+ <td>long</td>
+ </tr>
+ <tr>
+ <td>'L' </td>
+ <td>unsigned long</td>
+ </tr>
+ </tbody>
+ </table></li>
+ <li>$count$ is an optional counter for the $format specifier$. For example, $i5$ instructs the code to pack/unpack 5 integer variables, as opposed to $i$ that specifies a
+ single integer variable.</li>
+</ul><p>]],
+
+ -- Functions
+ funcs =
+ {
+ { sig = "packed = #pack.pack#( format, val1, val2, ..., valn )",
+ desc = "Packs variables in a string.",
+ args =
+ {
+ "$format$ - format specifier (as described @#overview at here@).",
+ "$val1$ - first variable to pack.",
+ "$val2$ - second variable to pack.",
+ "$valn$ - nth variable to pack.",
+ },
+ ret = "$packed$ - a string containing the packed representation of all variables according to the format."
+ },
+
+ { sig = "nextpos, val1, val2, ..., valn = #pack.unpack#( string, format, [ init ] )",
+ desc = "Unpacks a string",
+ args =
+ {
+ "$string$ - the string to unpack.",
+ "$format$ - format specifier (as described @#overview at here@).",
+ "$init$ - $(optional)$ marks where in $string$ the unpacking should start (1 if not specified)."
+ },
+ ret =
+ {
+ "$nextpos$ - the position in the string after unpacking.",
+ "$val1$ - the first unpacked value.",
+ "$val2$ - the second unpacked value.",
+ "$valn$ - the nth unpacked value."
+ }
+ }
+ },
+}
+
+data_pt =
+{
+
+ -- Title
+ title = "eLua reference manual - pack",
+
+ -- Menu name
+ menu_name = "pack",
+
+ -- Overview
+ overview = [[This module allows for arbitrary packing of data into Lua strings and unpacking data from Lua strings. In this way, a string can be used to store data in a platform-indepdendent
+manner. It is based on the ^http://www.tecgraf.puc-rio.br/~~lhf/ftp/lua/#lpack^lpack^ module from Luiz Henrique de Figueiredo (with some minor tweaks). </p>
+<p>Both methods of this module (@#pack at pack@ and @#unpack at unpack@) use a $format string$ to describe how to pack/unpack the data. The format string contains one or more $data specifiers$, each
+data specifier is applied to a single variable that must be packed/unpacked. The data specifier has the following general format:</p>
+~[endianness]<<format specifier>>[count]~
+<p>where:</p>
+<ul>
+ <li>$endianness$ is an optional endian flags that specifies how the numbers that are to be packed/unpacked are stored in memory. It can be either:
+ <ol>
+ <li>$'<<'$ for little endian.</li>
+ <li>$'>>'$ for big endian.</li>
+ <li>$'='$ for native endian (the platform's endian order, default).</li>
+ </ol></li>
+ <li>$format specifier$ describes what kind of variable will be packed/unpacked. $The format specifier is case-sensitive$. The possible values of this parameter are summarized in the table below:
+ <table class="table_center" style="margin-top: 4px; margin-bottom: 4px;">
+ <tbody>
+ <tr>
+ <th>Format specifier</th>
+ <th>Corresponding variable type</th>
+ </tr>
+ <tr>
+ <td>'z'</td>
+ <td>zero-terminated string</td>
+ </tr>
+ <tr>
+ <td>'p' </td>
+ <td>string preceded by length byte</td>
+ </tr>
+ <tr>
+ <td>'P' </td>
+ <td>string preceded by length word</td>
+ </tr>
+ <tr>
+ <td>'a' </td>
+ <td>string preceded by length size_t</td>
+ </tr>
+ <tr>
+ <td>'A' </td>
+ <td>string</td>
+ </tr>
+ <tr>
+ <td>'f' </td>
+ <td>float</td>
+ </tr>
+ <tr>
+ <td>'d' </td>
+ <td>double</td>
+ </tr>
+ <tr>
+ <td>'n' </td>
+ <td>Lua number</td>
+ </tr>
+ <tr>
+ <td>'c' </td>
+ <td>char</td>
+ </tr>
+ <tr>
+ <td>'b' </td>
+ <td>byte = unsigned char</td>
+ </tr>
+ <tr>
+ <td>'h' </td>
+ <td>short</td>
+ </tr>
+ <tr>
+ <td>'H' </td>
+ <td>unsigned short</td>
+ </tr>
+ <tr>
+ <td>'i' </td>
+ <td>int</td>
+ </tr>
+ <tr>
+ <td>'I' </td>
+ <td>unsigned int</td>
+ </tr>
+ <tr>
+ <td>'l' </td>
+ <td>long</td>
+ </tr>
+ <tr>
+ <td>'L' </td>
+ <td>unsigned long</td>
+ </tr>
+ </tbody>
+ </table></li>
+ <li>$count$ is an optional counter for the $format specifier$. For example, $i5$ instructs the code to pack/unpack 5 integer variables, as opposed to $i$ that specifies a
+ single integer variable.</li>
+</ul><p>]],
+
+ -- Functions
+ funcs =
+ {
+ { sig = "packed = #pack.pack#( format, val1, val2, ..., valn )",
+ desc = "Packs variables in a string.",
+ args =
+ {
+ "$format$ - format specifier (as described @#overview at here@).",
+ "$val1$ - first variable to pack.",
+ "$val2$ - second variable to pack.",
+ "$valn$ - nth variable to pack.",
+ },
+ ret = "$packed$ - a string containing the packed representation of all variables according to the format."
+ },
+
+ { sig = "nextpos, val1, val2, ..., valn = #pack.unpack#( string, format, [ init ] )",
+ desc = "Unpacks a string",
+ args =
+ {
+ "$string$ - the string to unpack.",
+ "$format$ - format specifier (as described @#overview at here@).",
+ "$init$ - $(optional)$ marks where in $string$ the unpacking should start (1 if not specified)."
+ },
+ ret =
+ {
+ "$nextpos$ - the position in the string after unpacking.",
+ "$val1$ - the first unpacked value.",
+ "$val2$ - the second unpacked value.",
+ "$valn$ - the nth unpacked value."
+ }
+ }
+ },
+}
+
Added: branches/eagle_mmc/doc/eluadoc/refman_gen_pd.lua
===================================================================
--- branches/eagle_mmc/doc/eluadoc/refman_gen_pd.lua 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/eluadoc/refman_gen_pd.lua 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,66 @@
+-- eLua reference manual - platform data
+
+data_en =
+{
+
+ -- Title
+ title = "eLua reference manual - platform data",
+
+ -- Menu name
+ menu_name = "Platform data (pd)",
+
+ -- Overview
+ overview = [[This module contains functions that access specific platform data. Useful if the code needs to know on which platform it runs.]],
+
+ -- Functions
+ funcs =
+ {
+ { sig = "platform = #pd.platform#()",
+ desc = "Get platform name.",
+ ret = "$platform$ - the name of the platform on which eLua is running.",
+ },
+
+ { sig = "cpu = #pd.cpu#()",
+ desc = "Get CPU name.",
+ ret = "$cpu$ - the name of the CPU of the platform on which eLua is running.",
+ },
+
+ { sig = "board = #pd.board#()",
+ desc = "Get board name.",
+ ret = "$board$ - the name of the board on which eLua is running.",
+ }
+ },
+}
+
+data_pt =
+{
+
+ -- Title
+ title = "eLua reference manual - platform data",
+
+ -- Menu name
+ menu_name = "Platform data (pd)",
+
+ -- Overview
+ overview = [[This module contains functions that access specific platform data. Useful if the code needs to know on which platform it runs.]],
+
+ -- Functions
+ funcs =
+ {
+ { sig = "platform = #pd.platform#()",
+ desc = "Get platform name.",
+ ret = "$platform$ - the name of the platform on which eLua is running.",
+ },
+
+ { sig = "cpu = #pd.cpu#()",
+ desc = "Get CPU name.",
+ ret = "$cpu$ - the name of the CPU of the platform on which eLua is running.",
+ },
+
+ { sig = "board = #pd.board#()",
+ desc = "Get board name.",
+ ret = "$board$ - the name of the board on which eLua is running.",
+ }
+ },
+}
+
Added: branches/eagle_mmc/doc/eluadoc/refman_gen_pio.lua
===================================================================
--- branches/eagle_mmc/doc/eluadoc/refman_gen_pio.lua 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/eluadoc/refman_gen_pio.lua 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,314 @@
+-- eLua reference manual - pio module
+
+data_en =
+{
+
+ -- Title
+ title = "eLua reference manual - pio module",
+
+ -- Menu name
+ menu_name = "pio",
+
+ -- Overview
+ overview = [[This module contains functions for accessing the CPU's PIO (Programmable Input Output) pins. It contains two set of functions with identical
+ names and behaviour. One set groups the functions used to access individual pins from ports, the other groups the functions used to access full ports.</p>
+ <p>With the $pio$ module, you specifiy names of $ports$ as they appear in your eLua's CPU datasheet. For example, if your CPU's ports are named $PA, PB$
+ and $PC$, you can reffer to them using $pio.PA$, $pio.PB$ and $pio.PC$, respectively. If your CPU uses $P0$, $P1$, $P2$ instead of $PA$, $PB$ and $PC$,
+ you can simply use $pio.P0$, $pio.P1$ and $pio.P2$ instead.</p>
+ <p>You can also reffer to individual $pins$ instead of ports. With the same notation as above, $pio.PA_0$ refers to the first pin of port $PA$,
+ $P0_15$ refers to the 16th pin of port $P0$ and so on.
+ ]],
+
+ -- Functions
+ funcs =
+ {
+ { sig = "#pio.pin.setdir#( direction, pin1, pin2, ..., pinn )",
+ desc = "Set pin(s) direction",
+ args =
+ {
+ "$direction$ - the pin direction, can be either $pio.INPUT$ or $pio.OUTPUT$",
+ "$pin1$ - the first pin",
+ "$pin2 (optional)$ - the second pin",
+ "$pinn (optional)$ - the %n%-th pin"
+ }
+ },
+
+ { sig = "#pio.pin.setpull#( type, pin1, pin2, ..., pinn )",
+ desc = "Enable/disable pullups/pulldowns on the specified pin(s)",
+ args =
+ {
+ [[$type$ - 'pull' type, can be either $pio.PULLUP$ to enable pullups, $pio.PULLDOWN$ to enable pulldowns, or $pio.NOPULL$ to disable both pullups and
+ pulldowns]],
+ "$pin1$ - the first pin",
+ "$pin2 (optional)$ - the second pin",
+ "$pinn (optional)$ - the %n%-th pin",
+ }
+ },
+
+ { sig = "#pio.pin.setval#( value, pin1, pin2, ..., pinn )",
+ desc = "Set pin(s) value",
+ args=
+ {
+ "$value$ - pin value, can be either 0 or 1",
+ "$pin1$ - the first pin",
+ "$pin2 (optional)$ - the second pin",
+ "$pinn (optional)$ - the %n%-th pin"
+ }
+ },
+
+ { sig = "val1, val2, ..., valn = #pio.pin.getval#( pin1, pin2, ..., pinn )",
+ desc = "Get value of pin(s)",
+ args =
+ {
+ "$pin1$ - the first pin",
+ "$pin2 (optional)$ - the second pin",
+ "$pinn (optional)$ - the %n%-th pin",
+ },
+ ret = "The value(s) of the pin(s), either 0 or 1"
+ },
+
+ { sig = "#pio.pin.sethigh#( pin1, pin2, ..., pinn )",
+ desc = "Set pin(s) to 1 (high)",
+ args =
+ {
+ "$pin1$ - the first pin",
+ "$pin2 (optional)$ - the second pin",
+ "$pinn (optinoal)$ - the %n%-th pin"
+ }
+ },
+
+ { sig = "#pio.pin.setlow#( pin1, pin2, ..., pinn )",
+ desc = "Set pin(s) to 0 (low)",
+ args =
+ {
+ "$pin1$ - the first pin",
+ "$pin2 (optional)$ - the second pin",
+ "$pinn (optinoal)$ - the %n%-th pin"
+ }
+ },
+
+ { sig = "#pio.port.setdir#( direction, port1, port2, ..., portn )",
+ desc = "Set port(s) direction",
+ args =
+ {
+ "$direction$ - the port direction, can be either $pio.INPUT$ or $pio.OUTPUT$",
+ "$port1$ - the first port",
+ "$port2 (optional)$ - the second port",
+ "$portn (optional)$ - the %n%-th port"
+ }
+ },
+
+ { sig = "#pio.port.setpull#( type, port1, port2, ..., portn )",
+ desc = "Enable/disable pullups/pulldowns on the specified port(s)",
+ args =
+ {
+ [[$type$ - 'pull' type, can be either $pio.PULLUP$ to enable pullups, $pio.PULLDOWN$ to enable pulldowns, or $pio.NOPULL$ to disable both pullups and
+ pulldowns]],
+ "$port1$ - the first port",
+ "$port2 (optional)$ - the second port",
+ "$portn (optional)$ - the %n%-th port",
+ }
+ },
+
+ { sig = "#pio.port.setval#( value, port1, port2, ..., portn )",
+ desc = "Set port(s) value",
+ args=
+ {
+ "$value$ - port value",
+ "$port1$ - the first port",
+ "$port2 (optional)$ - the second port",
+ "$portn (optional)$ - the %n%-th port"
+ }
+ },
+
+ { sig = "val1, val2, ..., valn = #pio.port.getval#( port1, port2, ..., portn )",
+ desc = "Get value of port(s)",
+ args =
+ {
+ "$port1$ - the first port",
+ "$port2 (optional)$ - the second port",
+ "$portn (optional)$ - the %n%-th port",
+ },
+ ret = "The value(s) of the port(s)"
+ },
+
+ { sig = "#pio.port.sethigh#( port1, port2, ..., portn )",
+ desc = "Set port(s) to all 1 (high)",
+ args =
+ {
+ "$port1$ - the first port",
+ "$port2 (optional)$ - the second port",
+ "$portn (optinoal)$ - the %n%-th port"
+ }
+ },
+
+ { sig = "#pio.port.setlow#( port1, port2, ..., portn )",
+ desc = "Set port(s) to all 0 (low)",
+ args =
+ {
+ "$port1$ - the first port",
+ "$port2 (optional)$ - the second port",
+ "$portn (optinoal)$ - the %n%-th port"
+ }
+ },
+
+ }
+
+}
+
+data_pt =
+{
+
+ -- Title
+ title = "eLua reference manual - pio module",
+
+ -- Menu name
+ menu_name = "pio",
+
+ -- Overview
+ overview = [[This module contains functions for accessing the CPU's PIO (Programmable Input Output) pins. It contains two set of functions with identical
+ names and behaviour. One set groups the functions used to access individual pins from ports, the other groups the functions used to access full ports.</p>
+ <p>With the $pio$ module, you specifiy names of $ports$ as they appear in your eLua's CPU datasheet. For example, if your CPU's ports are named $PA, PB$
+ and $PC$, you can reffer to them using $pio.PA$, $pio.PB$ and $pio.PC$, respectively. If your CPU uses $P0$, $P1$, $P2$ instead of $PA$, $PB$ and $PC$,
+ you can simply use $pio.P0$, $pio.P1$ and $pio.P2$ instead.</p>
+ <p>You can also reffer to individual $pins$ instead of ports. With the same notation as above, $pio.PA_0$ refers to the first pin of port $PA$,
+ $P0_15$ refers to the 16th pin of port $P0$ and so on.
+ ]],
+
+ -- Functions
+ funcs =
+ {
+ { sig = "#pio.pin.setdir#( direction, pin1, pin2, ..., pinn )",
+ desc = "Set pin(s) direction",
+ args =
+ {
+ "$direction$ - the pin direction, can be either $pio.INPUT$ or $pio.OUTPUT$",
+ "$pin1$ - the first pin",
+ "$pin2 (optional)$ - the second pin",
+ "$pinn (optional)$ - the %n%-th pin"
+ }
+ },
+
+ { sig = "#pio.pin.setpull#( type, pin1, pin2, ..., pinn )",
+ desc = "Enable/disable pullups/pulldowns on the specified pin(s)",
+ args =
+ {
+ [[$type$ - 'pull' type, can be either $pio.PULLUP$ to enable pullups, $pio.PULLDOWN$ to enable pulldowns, or $pio.NOPULL$ to disable both pullups and
+ pulldowns]],
+ "$pin1$ - the first pin",
+ "$pin2 (optional)$ - the second pin",
+ "$pinn (optional)$ - the %n%-th pin",
+ }
+ },
+
+ { sig = "#pio.pin.setval#( value, pin1, pin2, ..., pinn )",
+ desc = "Set pin(s) value",
+ args=
+ {
+ "$value$ - pin value, can be either 0 or 1",
+ "$pin1$ - the first pin",
+ "$pin2 (optional)$ - the second pin",
+ "$pinn (optional)$ - the %n%-th pin"
+ }
+ },
+
+ { sig = "val1, val2, ..., valn = #pio.pin.getval#( pin1, pin2, ..., pinn )",
+ desc = "Get value of pin(s)",
+ args =
+ {
+ "$pin1$ - the first pin",
+ "$pin2 (optional)$ - the second pin",
+ "$pinn (optional)$ - the %n%-th pin",
+ },
+ ret = "The value(s) of the pin(s), either 0 or 1"
+ },
+
+ { sig = "#pio.pin.sethigh#( pin1, pin2, ..., pinn )",
+ desc = "Set pin(s) to 1 (high)",
+ args =
+ {
+ "$pin1$ - the first pin",
+ "$pin2 (optional)$ - the second pin",
+ "$pinn (optinoal)$ - the %n%-th pin"
+ }
+ },
+
+ { sig = "#pio.pin.setlow#( pin1, pin2, ..., pinn )",
+ desc = "Set pin(s) to 0 (low)",
+ args =
+ {
+ "$pin1$ - the first pin",
+ "$pin2 (optional)$ - the second pin",
+ "$pinn (optinoal)$ - the %n%-th pin"
+ }
+ },
+
+ { sig = "#pio.port.setdir#( direction, port1, port2, ..., portn )",
+ desc = "Set port(s) direction",
+ args =
+ {
+ "$direction$ - the port direction, can be either $pio.INPUT$ or $pio.OUTPUT$",
+ "$port1$ - the first port",
+ "$port2 (optional)$ - the second port",
+ "$portn (optional)$ - the %n%-th port"
+ }
+ },
+
+ { sig = "#pio.port.setpull#( type, port1, port2, ..., portn )",
+ desc = "Enable/disable pullups/pulldowns on the specified port(s)",
+ args =
+ {
+ [[$type$ - 'pull' type, can be either $pio.PULLUP$ to enable pullups, $pio.PULLDOWN$ to enable pulldowns, or $pio.NOPULL$ to disable both pullups and
+ pulldowns]],
+ "$port1$ - the first port",
+ "$port2 (optional)$ - the second port",
+ "$portn (optional)$ - the %n%-th port",
+ }
+ },
+
+ { sig = "#pio.port.setval#( value, port1, port2, ..., portn )",
+ desc = "Set port(s) value",
+ args=
+ {
+ "$value$ - port value",
+ "$port1$ - the first port",
+ "$port2 (optional)$ - the second port",
+ "$portn (optional)$ - the %n%-th port"
+ }
+ },
+
+ { sig = "val1, val2, ..., valn = #pio.port.getval#( port1, port2, ..., portn )",
+ desc = "Get value of port(s)",
+ args =
+ {
+ "$port1$ - the first port",
+ "$port2 (optional)$ - the second port",
+ "$portn (optional)$ - the %n%-th port",
+ },
+ ret = "The value(s) of the port(s)"
+ },
+
+ { sig = "#pio.port.sethigh#( port1, port2, ..., portn )",
+ desc = "Set port(s) to all 1 (high)",
+ args =
+ {
+ "$port1$ - the first port",
+ "$port2 (optional)$ - the second port",
+ "$portn (optinoal)$ - the %n%-th port"
+ }
+ },
+
+ { sig = "#pio.port.setlow#( port1, port2, ..., portn )",
+ desc = "Set port(s) to all 0 (low)",
+ args =
+ {
+ "$port1$ - the first port",
+ "$port2 (optional)$ - the second port",
+ "$portn (optinoal)$ - the %n%-th port"
+ }
+ },
+
+ }
+
+}
+
Added: branches/eagle_mmc/doc/eluadoc/refman_gen_pwm.lua
===================================================================
--- branches/eagle_mmc/doc/eluadoc/refman_gen_pwm.lua 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/eluadoc/refman_gen_pwm.lua 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,114 @@
+-- eLua reference manual - pwm module
+
+data_en =
+{
+
+ -- Title
+ title = "eLua reference manual - pwm module",
+
+ -- Menu name
+ menu_name = "pwm",
+
+ -- Overview
+ overview = [[This module contains functions for accessing the PWM (Pulse Width Modulation) modules of the eLua CPU.]],
+
+ -- Functions
+ funcs =
+ {
+ { sig = "frequency = #pwm.setup#( id, frequency, duty )",
+ desc = "Setup the PWM modules.",
+ args =
+ {
+ "$id$ - the ID of the PWM module.",
+ "$frequency$ - the frequency of the PWM module (in Hz).",
+ [[$duty$ - the duty cycle of the PWM module given in percents. This must be an integer between 0 and 100. $NOTE$: depending on the hardware, some
+duty cycles (particulary 0 and 100) might not be achievable.]]
+ },
+ ret = "The actual frequenct set on the PWM module. Depending on the hardware, this might have a different value than the $frequency$ argument."
+ },
+
+ { sig = "#pwm.start#( id )",
+ desc = "Start the PWM signal on the given module.",
+ args = "$id$ - the ID of the PWM module."
+ },
+
+ { sig = "#pwm.stop#( id )",
+ desc = "Stop the PWM signal on the given module.",
+ args = "$id$ - the ID of the PWM module."
+ },
+
+ { sig = "clock = #pwm.setclock#( id, clock )",
+ desc = "Set the base clock of the given PWM module.",
+ args =
+ {
+ "$id$ - the ID of the PWM module.",
+ "$clock$ - the desired base clock."
+ },
+ ret = "The actual base clock set on the PWM module. Depending on the hardware, this might have a different value than the $clock$ argument."
+ },
+
+ { sig = "clock = #pwm.getclock#( id )",
+ desc = "Get the base clock of the given PWM module.",
+ args = "$id$ - the ID of the PWM module.",
+ ret = "The base clock of the PWM module."
+ }
+ },
+
+}
+
+data_pt =
+{
+
+ -- Title
+ title = "eLua reference manual - pwm module",
+
+ -- Menu name
+ menu_name = "pwm",
+
+ -- Overview
+ overview = [[This module contains functions for accessing the PWM (Pulse Width Modulation) modules of the eLua CPU.]],
+
+ -- Functions
+ funcs =
+ {
+ { sig = "frequency = #pwm.setup#( id, frequency, duty )",
+ desc = "Setup the PWM modules.",
+ args =
+ {
+ "$id$ - the ID of the PWM module.",
+ "$frequency$ - the frequency of the PWM module (in Hz).",
+ [[$duty$ - the duty cycle of the PWM module given in percents. This must be an integer between 0 and 100. $NOTE$: depending on the hardware, some
+duty cycles (particulary 0 and 100) might not be achievable.]]
+ },
+ ret = "The actual frequenct set on the PWM module. Depending on the hardware, this might have a different value than the $frequency$ argument."
+ },
+
+ { sig = "#pwm.start#( id )",
+ desc = "Start the PWM signal on the given module.",
+ args = "$id$ - the ID of the PWM module."
+ },
+
+ { sig = "#pwm.stop#( id )",
+ desc = "Stop the PWM signal on the given module.",
+ args = "$id$ - the ID of the PWM module."
+ },
+
+ { sig = "clock = #pwm.setclock#( id, clock )",
+ desc = "Set the base clock of the given PWM module.",
+ args =
+ {
+ "$id$ - the ID of the PWM module.",
+ "$clock$ - the desired base clock."
+ },
+ ret = "The actual base clock set on the PWM module. Depending on the hardware, this might have a different value than the $clock$ argument."
+ },
+
+ { sig = "clock = #pwm.getclock#( id )",
+ desc = "Get the base clock of the given PWM module.",
+ args = "$id$ - the ID of the PWM module.",
+ ret = "The base clock of the PWM module."
+ }
+ },
+
+}
+
Added: branches/eagle_mmc/doc/eluadoc/refman_gen_spi.lua
===================================================================
--- branches/eagle_mmc/doc/eluadoc/refman_gen_spi.lua 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/eluadoc/refman_gen_spi.lua 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,136 @@
+-- eLua reference manual - SPI module
+
+data_en =
+{
+
+ -- Title
+ title = "eLua reference manual - SPI module",
+
+ -- Menu name
+ menu_name = "spi",
+
+ -- Overview
+ overview = [[This module contains functions for accessing the SPI interfaces of the eLua CPU.</p>
+ <p><span class="warning">IMPORTANT</span>: right now, only master SPI mode is implemented in eLua.]],
+
+ -- Functions
+ funcs =
+ {
+ { sig = "clock = #spi.setup#( id, type, clock, cpol, cpha, databits )",
+ desc = "Setup the SPI interface",
+ args =
+ {
+ "$id$ - the ID of the SPI interface.",
+ "$type$ - SPI interface type, can be either $spi.MASTER$ or $spi.SLAVE$. $NOTE: currently, only master SPI mode is supported$.",
+ "$clock$ - the clock of the SPI interface.",
+ "$cpol$ - the clock polarity (0 or 1).",
+ "$cpha$ - the clock phase (0 or 1).",
+ "$databits$ - the length of the SPI data word.",
+ },
+ ret = "The actual clock set on the SPI interface. Depending on the hardware, this might have a different value than the $clock$ parameter."
+ },
+
+ { sig = "#spi.sson#( id )",
+ desc = "Select the SS line (Slave Select) of the SPI interface. This is only applicable for SPI interfaces with a dedicated SS pin.",
+ args = "$id$ - the ID of the SPI interface.",
+ },
+
+ { sig = "#spi.ssoff#( id )",
+ desc = "Deselect the SS line (Slave Select) of the SPI interface. This is only applicable for SPI interfaces with a dedicated SS pin.",
+ args = "$id$ - the ID of the SPI interface.",
+ },
+
+ { sig = "#spi.write#( id, data1, [data2], ..., [datan] )",
+ desc = "Write one or more strings/numbers to the SPI interface.",
+ args =
+ {
+ "$id$ - the ID os the SPI interface.",
+ "$data1$ - the first string/number to send.",
+ "$data2 (optional)$ - the second string/number to send.",
+ "$datan (optional)$ - the %n%-th string/number to send."
+ },
+ },
+
+ { sig = "#spi.readwrite#( id, data1, [data2], ..., [datan] )",
+ desc = "Write one or more strings/numbers to the SPI interface and return the data read from the same interface.",
+ args =
+ {
+ "$id$ - the ID os the SPI interface.",
+ "$data1$ - the first string/number to send.",
+ "$data2 (optional)$ - the second string/number to send.",
+ "$datan (optional)$ - the %n%-th string/number to send."
+ },
+ ret = "An array with all the data read from the SPI interface."
+ }
+
+ },
+
+}
+
+data_pt =
+{
+
+ -- Title
+ title = "eLua reference manual - SPI module",
+
+ -- Menu name
+ menu_name = "spi",
+
+ -- Overview
+ overview = [[This module contains functions for accessing the SPI interfaces of the eLua CPU.</p>
+ <p><span class="warning">IMPORTANT</span>: right now, only master SPI mode is implemented in eLua.]],
+
+ -- Functions
+ funcs =
+ {
+ { sig = "clock = #spi.setup#( id, type, clock, cpol, cpha, databits )",
+ desc = "Setup the SPI interface",
+ args =
+ {
+ "$id$ - the ID of the SPI interface.",
+ "$type$ - SPI interface type, can be either $spi.MASTER$ or $spi.SLAVE$. $NOTE: currently, only master SPI mode is supported$.",
+ "$clock$ - the clock of the SPI interface.",
+ "$cpol$ - the clock polarity (0 or 1).",
+ "$cpha$ - the clock phase (0 or 1).",
+ "$databits$ - the length of the SPI data word.",
+ },
+ ret = "The actual clock set on the SPI interface. Depending on the hardware, this might have a different value than the $clock$ parameter."
+ },
+
+ { sig = "#spi.sson#( id )",
+ desc = "Select the SS line (Slave Select) of the SPI interface. This is only applicable for SPI interfaces with a dedicated SS pin.",
+ args = "$id$ - the ID of the SPI interface.",
+ },
+
+ { sig = "#spi.ssoff#( id )",
+ desc = "Deselect the SS line (Slave Select) of the SPI interface. This is only applicable for SPI interfaces with a dedicated SS pin.",
+ args = "$id$ - the ID of the SPI interface.",
+ },
+
+ { sig = "#spi.write#( id, data1, [data2], ..., [datan] )",
+ desc = "Write one or more strings/numbers to the SPI interface.",
+ args =
+ {
+ "$id$ - the ID os the SPI interface.",
+ "$data1$ - the first string/number to send.",
+ "$data2 (optional)$ - the second string/number to send.",
+ "$datan (optional)$ - the %n%-th string/number to send."
+ },
+ },
+
+ { sig = "#spi.readwrite#( id, data1, [data2], ..., [datan] )",
+ desc = "Write one or more strings/numbers to the SPI interface and return the data read from the same interface.",
+ args =
+ {
+ "$id$ - the ID os the SPI interface.",
+ "$data1$ - the first string/number to send.",
+ "$data2 (optional)$ - the second string/number to send.",
+ "$datan (optional)$ - the %n%-th string/number to send."
+ },
+ ret = "An array with all the data read from the SPI interface."
+ }
+
+ },
+
+}
+
Added: branches/eagle_mmc/doc/eluadoc/refman_gen_term.lua
===================================================================
--- branches/eagle_mmc/doc/eluadoc/refman_gen_term.lua 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/eluadoc/refman_gen_term.lua 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,314 @@
+-- eLua reference manual - term module
+
+data_en =
+{
+
+ -- Title
+ title = "eLua reference manual - term module",
+
+ -- Menu name
+ menu_name = "term",
+
+ -- Overview
+ overview = [[This module contains functions for accessing ANSI-compatible terminals (and terminal emulators) from Lua.]],
+
+ -- Functions
+ funcs =
+ {
+ { sig = "#term.clrscr#()",
+ desc = "Clear the screen",
+ },
+
+ { sig = "#term.clreol#()",
+ desc = "Clear from the current cursor position to the end of the line",
+ },
+
+ { sig = "#term.moveto#( x, y )",
+ desc = "Move the cursor to the specified coordinates",
+ args=
+ {
+ "$x$ - the column (starting with 1)",
+ "$y$ - the line (starting with 1)"
+ }
+ },
+
+ { sig = "#term.moveup#( delta )",
+ desc = "Move the cursor up",
+ args = "$delta$ - number of lines to move the cursor up"
+ },
+
+ { sig = "#term.movedown#( delta )",
+ desc = "Move the cursor down",
+ args = "$delta$ - number of lines to move the cursor down",
+ },
+
+ { sig = "#term.moveleft#( delta )",
+ desc = "Move the cursor left",
+ args = "$delta$ - number of columns to move the cursor left",
+ },
+
+ { sig = "#term.moveright#( delta )",
+ desc = "Move the cursor right",
+ args = "$delta$ - number of columns to move the cursor right",
+ },
+
+ { sig = "numlines = #term.getlines#()",
+ desc = "Get the number of lines in the terminal",
+ ret = "The number of lines in the terminal",
+ },
+
+ { sig = "numcols = #term.getcols#()",
+ desc = "Get the number of columns in the terminal",
+ ret = "The number of columns in the terminal",
+ },
+
+ { sig = "#term.print#( [ x, y ], str1, [ str2, ..., strn ] )",
+ desc = "Write one or more strings in the terminal",
+ args =
+ {
+ "$x (optional)$ - write the string at this column. If $x$ is specified, $y$ must also be specified",
+ "$y (optional)$ - write the string at this line. If $y$ is specified, $x$ must also be specified",
+ "$str1$ - the first string to write",
+ "$str2 (optional)$ - the second string to write",
+ "$strn (optional)$ - the nth string to write"
+ }
+ },
+
+ { sig = "cx = #term.getcx#()",
+ desc = "Get the current column of the cursor",
+ ret = "The column of the cursor"
+ },
+
+ { sig = "cy = #term.getcy#()",
+ desc = "Get the current line of the cursor",
+ ret = "The line of the cursor"
+ },
+
+ { sig = "ch = #term.getchar#( [ mode ] )",
+ desc = "Read a char (a key press) from the terminal",
+ args = [[$mode (optional)$ - terminal input mode. It can be either:</p>
+ <ul>
+ <li>$term.WAIT$ - wait for a key to be pressed, then return it. This is the default behaviour if $mode$ is not specified. </li>
+ <li>$term.NOWAIT$ - if a key was pressed on the terminal return it, otherwise return -1.</li>
+ </ul><p>]],
+ ret = [[The char read from a terminal or -1 if no char is available. The 'char' can be an actual ASCII char, or a 'pseudo-char' which encodes special keys on
+ the keyboard. The list of the special chars and their meaning is given in the table below:</p>
+<table style="text-align: left; margin-left: 2em;">
+<tbody>
+<tr>
+ <th style="text-align: left;">Key code</th>
+ <th style="text-align: left;">Meaning</th>
+</tr>
+<tr>
+ <td>$KC_UP$</td>
+ <td>the UP key on the terminal</td>
+</tr>
+<tr>
+ <td>$KC_DOWN$</td>
+ <td>the DOWN key on the terminal</td>
+</tr>
+<tr>
+ <td>$KC_LEFT$</td>
+ <td>the LEFT key on the terminal</td>
+</tr>
+<tr>
+ <td>$KC_RIGHT$</td>
+ <td>the RIGHT key on the terminal</td>
+</tr>
+<tr>
+ <td>$KC_HOME$</td>
+ <td>the HOME key on the terminal</td>
+</tr>
+<tr>
+ <td>$KC_END$</td>
+ <td>the END key on the terminal</td>
+</tr>
+<tr>
+ <td>$KC_PAGEUP$</td>
+ <td>the PAGE UP key on the terminal</td>
+</tr>
+<tr>
+ <td>$KC_PAGEDOWN$</td>
+ <td>the PAGE DOWN key on the terminal</td>
+</tr>
+<tr>
+ <td>$KC_ENTER$</td>
+ <td>the ENTER (CR) key on the terminal</td>
+</tr>
+<tr>
+ <td>$KC_TAB$</td>
+ <td>the TAB key on the terminal</td>
+</tr>
+<tr>
+ <td>$KC_BACKSPACE$</td>
+ <td>the BACKSPACE key on the terminal</td>
+</tr>
+<tr>
+ <td>$KC_ESC$</td>
+ <td>the ESC (escape) key on the terminal</td>
+</tr>
+</tbody>
+</table>
+<p>]]
+ },
+
+ },
+
+}
+
+data_pt =
+{
+
+ -- Title
+ title = "eLua reference manual - term module",
+
+ -- Menu name
+ menu_name = "term",
+
+ -- Overview
+ overview = [[This module contains functions for accessing ANSI-compatible terminals (and terminal emulators) from Lua.]],
+
+ -- Functions
+ funcs =
+ {
+ { sig = "#term.clrscr#()",
+ desc = "Clear the screen",
+ },
+
+ { sig = "#term.clreol#()",
+ desc = "Clear from the current cursor position to the end of the line",
+ },
+
+ { sig = "#term.moveto#( x, y )",
+ desc = "Move the cursor to the specified coordinates",
+ args=
+ {
+ "$x$ - the column (starting with 1)",
+ "$y$ - the line (starting with 1)"
+ }
+ },
+
+ { sig = "#term.moveup#( delta )",
+ desc = "Move the cursor up",
+ args = "$delta$ - number of lines to move the cursor up"
+ },
+
+ { sig = "#term.movedown#( delta )",
+ desc = "Move the cursor down",
+ args = "$delta$ - number of lines to move the cursor down",
+ },
+
+ { sig = "#term.moveleft#( delta )",
+ desc = "Move the cursor left",
+ args = "$delta$ - number of columns to move the cursor left",
+ },
+
+ { sig = "#term.moveright#( delta )",
+ desc = "Move the cursor right",
+ args = "$delta$ - number of columns to move the cursor right",
+ },
+
+ { sig = "numlines = #term.getlines#()",
+ desc = "Get the number of lines in the terminal",
+ ret = "The number of lines in the terminal",
+ },
+
+ { sig = "numcols = #term.getcols#()",
+ desc = "Get the number of columns in the terminal",
+ ret = "The number of columns in the terminal",
+ },
+
+ { sig = "#term.print#( [ x, y ], str1, [ str2, ..., strn ] )",
+ desc = "Write one or more strings in the terminal",
+ args =
+ {
+ "$x (optional)$ - write the string at this column. If $x$ is specified, $y$ must also be specified",
+ "$y (optional)$ - write the string at this line. If $y$ is specified, $x$ must also be specified",
+ "$str1$ - the first string to write",
+ "$str2 (optional)$ - the second string to write",
+ "$strn (optional)$ - the nth string to write"
+ }
+ },
+
+ { sig = "cx = #term.getcx#()",
+ desc = "Get the current column of the cursor",
+ ret = "The column of the cursor"
+ },
+
+ { sig = "cy = #term.getcy#()",
+ desc = "Get the current line of the cursor",
+ ret = "The line of the cursor"
+ },
+
+ { sig = "ch = #term.getchar#( [ mode ] )",
+ desc = "Read a char (a key press) from the terminal",
+ args = [[$mode (optional)$ - terminal input mode. It can be either:</p>
+ <ul>
+ <li>$term.WAIT$ - wait for a key to be pressed, then return it. This is the default behaviour if $mode$ is not specified. </li>
+ <li>$term.NOWAIT$ - if a key was pressed on the terminal return it, otherwise return -1.</li>
+ </ul><p>]],
+ ret = [[The char read from a terminal or -1 if no char is available. The 'char' can be an actual ASCII char, or a 'pseudo-char' which encodes special keys on
+ the keyboard. The list of the special chars and their meaning is given in the table below:</p>
+<table style="text-align: left; margin-left: 2em;">
+<tbody>
+<tr>
+ <th style="text-align: left;">Key code</th>
+ <th style="text-align: left;">Meaning</th>
+</tr>
+<tr>
+ <td>$KC_UP$</td>
+ <td>the UP key on the terminal</td>
+</tr>
+<tr>
+ <td>$KC_DOWN$</td>
+ <td>the DOWN key on the terminal</td>
+</tr>
+<tr>
+ <td>$KC_LEFT$</td>
+ <td>the LEFT key on the terminal</td>
+</tr>
+<tr>
+ <td>$KC_RIGHT$</td>
+ <td>the RIGHT key on the terminal</td>
+</tr>
+<tr>
+ <td>$KC_HOME$</td>
+ <td>the HOME key on the terminal</td>
+</tr>
+<tr>
+ <td>$KC_END$</td>
+ <td>the END key on the terminal</td>
+</tr>
+<tr>
+ <td>$KC_PAGEUP$</td>
+ <td>the PAGE UP key on the terminal</td>
+</tr>
+<tr>
+ <td>$KC_PAGEDOWN$</td>
+ <td>the PAGE DOWN key on the terminal</td>
+</tr>
+<tr>
+ <td>$KC_ENTER$</td>
+ <td>the ENTER (CR) key on the terminal</td>
+</tr>
+<tr>
+ <td>$KC_TAB$</td>
+ <td>the TAB key on the terminal</td>
+</tr>
+<tr>
+ <td>$KC_BACKSPACE$</td>
+ <td>the BACKSPACE key on the terminal</td>
+</tr>
+<tr>
+ <td>$KC_ESC$</td>
+ <td>the ESC (escape) key on the terminal</td>
+</tr>
+</tbody>
+</table>
+<p>]]
+ },
+
+ },
+
+}
+
Added: branches/eagle_mmc/doc/eluadoc/refman_gen_tmr.lua
===================================================================
--- branches/eagle_mmc/doc/eluadoc/refman_gen_tmr.lua 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/eluadoc/refman_gen_tmr.lua 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,184 @@
+-- eLua reference manual - tmr module
+
+data_en =
+{
+
+ -- Title
+ title = "eLua reference manual - tmr module",
+
+ -- Menu name
+ menu_name = "tmr",
+
+ -- Overview
+ overview = [[This module contains functions for accessing the hardware timers of the eLua CPU. In addition, if virtual timers are enabled
+ (see @arch_platform_timers.html#virtual_timers at here@ and @building.html at here@ for details), they can be used just like the "regular" (hardware)
+ timers with a single exception: you can't set the clock of a virtual timer (using @#tmr.setclock at tmr.setclock@). To use virtual timers with this
+ module, specify $tmr.VIRTx$ as the timer ID instead of a number. For example, if the eLua image was configured to support 4 virtual timers, they will
+ be available by using $tmr.VIRT0$ to $tmr.VIRT3$ as timer IDs.</p>
+ <p>All "time units" (delays, differences in time) in this module, as well as in other parts of eLua (timeouts) are expressed in microseconds. However,
+ please keep in mind that the actual timer resolution depends on many factors. For example, it's very likely that the @#tmr.delay at tmr.delay@ function won't
+ be able to delay for the exact amount you specify (in us), as the real delay depends ona number of variables, most notably the base clock of the timer
+ and the size of the timer counter register (32 bits on some platforms, 16 bits on most platforms, other values are less common). To ensure that the delay
+ you're requesting is achievable, use @#tmr.getmindelay at tmr.getmindelay@ and @#tmr.getmaxdelay at tmr.getmaxdelay@ to obtain the maximum and the minimum
+ achievable wait times on your timer, respectively. Even if your delay is within these limits, the $precision$ of this function still varies a lot,
+ mainly as a function of the timer base clock.]],
+
+ -- Functions
+ funcs =
+ {
+ { sig = "#tmr.delay#( id, period )",
+ desc = "Waits for the specified period, then returns.",
+ args =
+ {
+ "$period$ - the timer ID.",
+ "$period$ - how long to wait (in us)."
+ }
+ },
+
+ { sig = "counter = #tmr.read#( id )",
+ desc= "Reads the timer counter register.",
+ args = "$id$ - the timer ID.",
+ ret = "The value of the timer counter register."
+ },
+
+ { sig = "counter = #tmr.start#( id )",
+ desc = "Starts the specified timer.",
+ args = "$id$ - the timer ID.",
+ ret = "The value of the timer counter register when the timer started.",
+ },
+
+ { sig = "delta = #tmr.gettimediff#( id, counter1, counter2 )",
+ desc = "Computes the time difference between two timer counter values (you can get counter values by calling @#tmr.read at tmr.read@ or @#tmr.start at tmr.start@).",
+ args =
+ {
+ "$id$ - the timer ID.",
+ "$counter1$ - the first counter value.",
+ "$counter2$ - the second counter value.",
+ },
+ ret = "The time difference (in us)."
+ },
+
+ { sig = "mindelay = #tmr.getmindelay#( id )",
+ desc = "Get the minimum achieavable delay on the specified timer.",
+ args = "$id$ - the timer ID.",
+ ret = "The minimum achievable delay on the specified timer (in us)."
+ },
+
+ { sig = "maxdelay = #tmr.getmaxdelay#( id )",
+ desc = "Get the maximum achieavable delay on the specified timer.",
+ args = "$id$ - the timer ID.",
+ ret = "The maximum achievable delay on the specified timer (in us)."
+ },
+
+ { sig = "clock = #tmr.setclock#( id, clock )",
+ desc = "Set the timer clock (the clock used to increment the timer counter register).",
+ args =
+ {
+ "$id$ - the timer ID.",
+ "$clock$ - the timer clock (in Hz)."
+ },
+ ret = [[The actual clock set on the timer (in Hz). Depending on the hardware, this might have a different value than the $clock$ argument.
+$NOTE:$ this function does not work with virtual timers.]]
+ },
+
+ { sig = "clock = #tmr.getclock#( id )",
+ desc = "Get the timer clock (the clock used to increment the timer counter register).",
+ args = "$id$ - the timer ID.",
+ ret = "The timer clock (in Hz)."
+ }
+
+ }
+
+}
+
+data_pt =
+{
+
+ -- Title
+ title = "eLua reference manual - tmr module",
+
+ -- Menu name
+ menu_name = "tmr",
+
+ -- Overview
+ overview = [[This module contains functions for accessing the hardware timers of the eLua CPU. In addition, if virtual timers are enabled
+ (see @arch_platform_timers.html#virtual_timers at here@ and @building.html at here@ for details), they can be used just like the "regular" (hardware)
+ timers with a single exception: you can't set the clock of a virtual timer (using @#tmr.setclock at tmr.setclock@). To use virtual timers with this
+ module, specify $tmr.VIRTx$ as the timer ID instead of a number. For example, if the eLua image was configured to support 4 virtual timers, they will
+ be available by using $tmr.VIRT0$ to $tmr.VIRT3$ as timer IDs.</p>
+ <p>All "time units" (delays, differences in time) in this module, as well as in other parts of eLua (timeouts) are expressed in microseconds. However,
+ please keep in mind that the actual timer resolution depends on many factors. For example, it's very likely that the @#tmr.delay at tmr.delay@ function won't
+ be able to delay for the exact amount you specify (in us), as the real delay depends ona number of variables, most notably the base clock of the timer
+ and the size of the timer counter register (32 bits on some platforms, 16 bits on most platforms, other values are less common). To ensure that the delay
+ you're requesting is achievable, use @#tmr.getmindelay at tmr.getmindelay@ and @#tmr.getmaxdelay at tmr.getmaxdelay@ to obtain the maximum and the minimum
+ achievable wait times on your timer, respectively. Even if your delay is within these limits, the $precision$ of this function still varies a lot,
+ mainly as a function of the timer base clock.]],
+
+ -- Functions
+ funcs =
+ {
+ { sig = "#tmr.delay#( id, period )",
+ desc = "Waits for the specified period, then returns.",
+ args =
+ {
+ "$period$ - the timer ID.",
+ "$period$ - how long to wait (in us)."
+ }
+ },
+
+ { sig = "counter = #tmr.read#( id )",
+ desc= "Reads the timer counter register.",
+ args = "$id$ - the timer ID.",
+ ret = "The value of the timer counter register."
+ },
+
+ { sig = "counter = #tmr.start#( id )",
+ desc = "Starts the specified timer.",
+ args = "$id$ - the timer ID.",
+ ret = "The value of the timer counter register when the timer started.",
+ },
+
+ { sig = "delta = #tmr.gettimediff#( id, counter1, counter2 )",
+ desc = "Computes the time difference between two timer counter values (you can get counter values by calling @#tmr.read at tmr.read@ or @#tmr.start at tmr.start@).",
+ args =
+ {
+ "$id$ - the timer ID.",
+ "$counter1$ - the first counter value.",
+ "$counter2$ - the second counter value.",
+ },
+ ret = "The time difference (in us)."
+ },
+
+ { sig = "mindelay = #tmr.getmindelay#( id )",
+ desc = "Get the minimum achieavable delay on the specified timer.",
+ args = "$id$ - the timer ID.",
+ ret = "The minimum achievable delay on the specified timer (in us)."
+ },
+
+ { sig = "maxdelay = #tmr.getmaxdelay#( id )",
+ desc = "Get the maximum achieavable delay on the specified timer.",
+ args = "$id$ - the timer ID.",
+ ret = "The maximum achievable delay on the specified timer (in us)."
+ },
+
+ { sig = "clock = #tmr.setclock#( id, clock )",
+ desc = "Set the timer clock (the clock used to increment the timer counter register).",
+ args =
+ {
+ "$id$ - the timer ID.",
+ "$clock$ - the timer clock (in Hz)."
+ },
+ ret = [[The actual clock set on the timer (in Hz). Depending on the hardware, this might have a different value than the $clock$ argument.
+$NOTE:$ this function does not work with virtual timers.]]
+ },
+
+ { sig = "clock = #tmr.getclock#( id )",
+ desc = "Get the timer clock (the clock used to increment the timer counter register).",
+ args = "$id$ - the timer ID.",
+ ret = "The timer clock (in Hz)."
+ }
+
+ }
+
+}
+
Added: branches/eagle_mmc/doc/eluadoc/refman_gen_uart.lua
===================================================================
--- branches/eagle_mmc/doc/eluadoc/refman_gen_uart.lua 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/eluadoc/refman_gen_uart.lua 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,158 @@
+-- eLua reference manual - uart module
+
+data_en =
+{
+
+ -- Title
+ title = "eLua reference manual - UART module",
+
+ -- Menu name
+ menu_name = "uart",
+
+ -- Overview
+ overview = [[This module contains functions for accessing the serial ports (UARTs) of the eLua CPU.]],
+
+ -- Functions
+ funcs =
+ {
+ { sig = "baud = #uart.setup#( id, baud, databits, parity, stopbits )",
+ desc = "Setup the serial port",
+ args =
+ {
+ "$id$ - the ID of the serial port",
+ "$baud$ - serial baud rate",
+ "$databits$ - number of data bits",
+ "$parity$ - parity type, can be either $uart.PAR_EVEN$, $uart.PAR_ODD$ or $uart.PAR_NONE$",
+ [[$stopbits$ - the number of stop bits, can be either $uart.STOP_1$ (for 1 stop bit), $uart.STOP_1_5$ (for 1.5 stop bits) or $uart.STOP_2$
+(for 2 stop bits)]]
+ },
+ ret = "The actual baud rate set on the serial port. Depending on the hardware, this might have a different value than the $baud$ parameter"
+ },
+
+ { sig = "#uart.write#( id, data1, [data2], ..., [datan] )",
+ desc = [[Write one or more strings or numbers to the serial port. If writing a number, its value must be between 0 and 255.]],
+ args =
+ {
+ "$id$ - the ID of the serial port.",
+ "$data1$ - the first string/number to write.",
+ "$data2 (optional)$ - the second string/number to write.",
+ "$datan (optional)$ - the %n%-th string/number to write."
+ }
+ },
+
+ { sig = "str = #uart.getchar#( id, [timeout], [timer_id] )",
+ desc = "Read a single character from the serial port",
+ args =
+ {
+ "$id$ - the ID of the serial port",
+ [[$timeout (optional)$ - timeout of the receive operation, can be either $uart.NO_TIMEOUT$ or 0 for non-blocking operation, $uart.INF_TIMEOUT$ for
+blocking operation, or a positive number that specifies the timeout in microseconds (in this case, the $timer_id$ parameter is also required). The default
+value of this argument is $uart.INF_TIMEOUT$]],
+ [[$timer_id (optional)$ - the ID of the timer for the receive operation, needed if the $timeout$ parameter specifies an actual timeout (that is,
+$timeout$ is neither $uart.NO_TIMEOUT$, nor $uart.INF_TIMEOUT$).]]
+ },
+ ret = "The character read from the serial port as a string, or the empty string it timeout occured while waiting for the character."
+ },
+
+ { sig = "str = #uart.read#( id, format, [timeout], [timer_id] )",
+ desc = "Reads one or more characters from the serial port according to a format specifier",
+ args =
+ {
+ "$id$ - the ID of the serial port",
+ [[$format$ - format of data to read. This can be either:
+<ul>
+ <li>$'*l'$ - read until an end of line character (a $\n$) is found (the $\n$ is not returned) or a timeout occurs.</li>
+ <li>$'*n'$ - read an integer. The integer can optionally have a sign. Reading continues until the first non-digit character is detected or a timeout occurs. This is the only case in which $read$ returns a number instead of an integer.</li>
+ <li>$'*s'$ - read until a spacing character (like a space or a TAB) is found (the spacing character is not returned) or a timeout occurs.</li>
+ <li>$a positive number$ - read at most this many characters before returning (reading can stop earlier if a timeout occurs).</li>
+</ul>]],
+ [[$timeout (optional)$ - timeout of the receive operation, can be either $uart.NO_TIMEOUT$ or 0 for non-blocking operation, $uart.INF_TIMEOUT$ for
+blocking operation, or a positive number that specifies the inter-char timeout in microseconds (in this case, the $timer_id$ parameter is also required). The default value of this argument is $uart.INF_TIMEOUT$]],
+ [[$timer_id (optional)$ - the ID of the timer for the receive operation, needed if the $timeout$ parameter specifies an actual timeout (that is,
+$timeout$ is neither $uart.NO_TIMEOUT$, nor $uart.INF_TIMEOUT$).]]
+ },
+ ret = [[The data read from the serial port as a string (or as a number if $format$ is $'*n'$). If a timeout occures, only the data read before the timeout is returned. If the function times out while trying to read the first character, the empty string is returned]]
+ }
+
+ },
+
+}
+
+data_pt =
+{
+
+ -- Title
+ title = "eLua reference manual - UART module",
+
+ -- Menu name
+ menu_name = "uart",
+
+ -- Overview
+ overview = [[This module contains functions for accessing the serial ports (UARTs) of the eLua CPU.]],
+
+ -- Functions
+ funcs =
+ {
+ { sig = "baud = #uart.setup#( id, baud, databits, parity, stopbits )",
+ desc = "Setup the serial port",
+ args =
+ {
+ "$id$ - the ID of the serial port",
+ "$baud$ - serial baud rate",
+ "$databits$ - number of data bits",
+ "$parity$ - parity type, can be either $uart.PAR_EVEN$, $uart.PAR_ODD$ or $uart.PAR_NONE$",
+ [[$stopbits$ - the number of stop bits, can be either $uart.STOP_1$ (for 1 stop bit), $uart.STOP_1_5$ (for 1.5 stop bits) or $uart.STOP_2$
+(for 2 stop bits)]]
+ },
+ ret = "The actual baud rate set on the serial port. Depending on the hardware, this might have a different value than the $baud$ parameter"
+ },
+
+ { sig = "#uart.write#( id, data1, [data2], ..., [datan] )",
+ desc = [[Write one or more strings or numbers to the serial port. If writing a number, its value must be between 0 and 255.]],
+ args =
+ {
+ "$id$ - the ID of the serial port.",
+ "$data1$ - the first string/number to write.",
+ "$data2 (optional)$ - the second string/number to write.",
+ "$datan (optional)$ - the %n%-th string/number to write."
+ }
+ },
+
+ { sig = "str = #uart.getchar#( id, [timeout], [timer_id] )",
+ desc = "Read a single character from the serial port",
+ args =
+ {
+ "$id$ - the ID of the serial port",
+ [[$timeout (optional)$ - timeout of the receive operation, can be either $uart.NO_TIMEOUT$ or 0 for non-blocking operation, $uart.INF_TIMEOUT$ for
+blocking operation, or a positive number that specifies the timeout in microseconds (in this case, the $timer_id$ parameter is also required). The default
+value of this argument is $uart.INF_TIMEOUT$]],
+ [[$timer_id (optional)$ - the ID of the timer for the receive operation, needed if the $timeout$ parameter specifies an actual timeout (that is,
+$timeout$ is neither $uart.NO_TIMEOUT$, nor $uart.INF_TIMEOUT$).]]
+ },
+ ret = "The character read from the serial port as a string, or the empty string it timeout occured while waiting for the character."
+ },
+
+ { sig = "str = #uart.read#( id, format, [timeout], [timer_id] )",
+ desc = "Reads one or more characters from the serial port according to a format specifier",
+ args =
+ {
+ "$id$ - the ID of the serial port",
+ [[$format$ - format of data to read. This can be either:
+<ul>
+ <li>$'*l'$ - read until an end of line character (a $\n$) is found (the $\n$ is not returned) or a timeout occurs.</li>
+ <li>$'*n'$ - read an integer. The integer can optionally have a sign. Reading continues until the first non-digit character is detected or a timeout occurs. This is the only case in which $read$ returns a number instead of an integer.</li>
+ <li>$'*s'$ - read until a spacing character (like a space or a TAB) is found (the spacing character is not returned) or a timeout occurs.</li>
+ <li>$a positive number$ - read at most this many characters before returning (reading can stop earlier if a timeout occurs).</li>
+</ul>]],
+ [[$timeout (optional)$ - timeout of the receive operation, can be either $uart.NO_TIMEOUT$ or 0 for non-blocking operation, $uart.INF_TIMEOUT$ for
+blocking operation, or a positive number that specifies the inter-char timeout in microseconds (in this case, the $timer_id$ parameter is also required). The default value of this argument is $uart.INF_TIMEOUT$]],
+ [[$timer_id (optional)$ - the ID of the timer for the receive operation, needed if the $timeout$ parameter specifies an actual timeout (that is,
+$timeout$ is neither $uart.NO_TIMEOUT$, nor $uart.INF_TIMEOUT$).]]
+ },
+ ret = [[The data read from the serial port as a string (or as a number if $format$ is $'*n'$). If a timeout occures, only the data read before the timeout is returned. If the function times out while trying to read the first character, the empty string is returned]]
+ }
+
+ },
+
+}
+
Added: branches/eagle_mmc/doc/eluadoc/refman_ps_lm3s_disp.lua
===================================================================
--- branches/eagle_mmc/doc/eluadoc/refman_ps_lm3s_disp.lua 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/eluadoc/refman_ps_lm3s_disp.lua 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,136 @@
+-- eLua reference manual - platform data
+
+data_en =
+{
+
+ -- Title
+ title = "eLua reference manual - LM3S disp module",
+
+ -- Menu name
+ menu_name = "disp",
+
+ -- Overview
+ overview = [[This module contains functions for working with the RIT OLED display on the Luminary Micro EKx-LM3S8962 boards and others.]],
+
+ -- Functions
+ funcs =
+ {
+ { sig = "#lm3s.disp.init#( frequency )",
+ desc = "Initialize the display.",
+ args = "$frequency$ - Number, the clock frequency (in Hertz) of the SSI interface used to control the display."
+ },
+
+ { sig = "#lm3s.disp.enable#( frequency )",
+ desc = "Enable the display.",
+ args = "$frequency$ - Number, the clock frequency (in Hertz) of the SSI interface used to control the display."
+ },
+
+ { sig = "#lm3s.disp.disable#()",
+ desc = "Disable the display.",
+ },
+
+ { sig = "#lm3s.disp.on#()",
+ desc = "Turn the display on."
+ },
+
+ { sig = "#lm3s.disp.off#()",
+ desc = "Turn the display off."
+ },
+
+ { sig = "#lm3s.disp.clear#()",
+ desc = "Clear the display."
+ },
+
+ { sig = "#lm3s.disp.print#( str, x, y, col )",
+ desc = "Write a string on the display. A 5x7 font (in a 6x8 cell) is used for drawing the text.",
+ args =
+ {
+ "$str$ - String, the text to be written on the display.",
+ "$x$ - Number [0-127], the horizonal position of the text (specified in columns).",
+ "$y$ - Number [0-95], the vertical position of the text (specified in lines).",
+ "$col$ - Number [0-15], the 4-bit gray scale value to be used for the text."
+ }
+ },
+
+ { sig = "#lm3s.disp.draw#( img, x, y, width, height )",
+ desc = "Draw an image on the display.",
+ args =
+ {
+ "$img$ - String, the image to draw in string format.",
+ "$x$ - Number [0-127], the horizontal position of the image (specified in pixels).",
+ "$y$ - Number [0-95], the vertical position of the image (specified in pixels).",
+ "$width$ - Number [1-127], the width of the image.",
+ "$height$ - Number [1-95], the height of the image."
+ }
+ },
+
+ },
+}
+
+data_pt =
+{
+
+ -- Title
+ title = "eLua reference manual - LM3S disp module",
+
+ -- Menu name
+ menu_name = "disp",
+
+ -- Overview
+ overview = [[This module contains functions for working with the RIT OLED display on the Luminary Micro EKx-LM3S8962 boards and others.]],
+
+ -- Functions
+ funcs =
+ {
+ { sig = "#lm3s.disp.init#( frequency )",
+ desc = "Initialize the display.",
+ args = "$frequency$ - Number, the clock frequency (in Hertz) of the SSI interface used to control the display."
+ },
+
+ { sig = "#lm3s.disp.enable#( frequency )",
+ desc = "Enable the display.",
+ args = "$frequency$ - Number, the clock frequency (in Hertz) of the SSI interface used to control the display."
+ },
+
+ { sig = "#lm3s.disp.disable#()",
+ desc = "Disable the display.",
+ },
+
+ { sig = "#lm3s.disp.on#()",
+ desc = "Turn the display on."
+ },
+
+ { sig = "#lm3s.disp.off#()",
+ desc = "Turn the display off."
+ },
+
+ { sig = "#lm3s.disp.clear#()",
+ desc = "Clear the display."
+ },
+
+ { sig = "#lm3s.disp.print#( str, x, y, col )",
+ desc = "Write a string on the display. A 5x7 font (in a 6x8 cell) is used for drawing the text.",
+ args =
+ {
+ "$str$ - String, the text to be written on the display.",
+ "$x$ - Number [0-127], the horizonal position of the text (specified in columns).",
+ "$y$ - Number [0-95], the vertical position of the text (specified in lines).",
+ "$col$ - Number [0-15], the 4-bit gray scale value to be used for the text."
+ }
+ },
+
+ { sig = "#lm3s.disp.draw#( img, x, y, width, height )",
+ desc = "Draw an image on the display.",
+ args =
+ {
+ "$img$ - String, the image to draw in string format.",
+ "$x$ - Number [0-127], the horizontal position of the image (specified in pixels).",
+ "$y$ - Number [0-95], the vertical position of the image (specified in pixels).",
+ "$width$ - Number [1-127], the width of the image.",
+ "$height$ - Number [1-95], the height of the image."
+ }
+ },
+
+ },
+}
+
Added: branches/eagle_mmc/doc/eluadoc/template.lua
===================================================================
--- branches/eagle_mmc/doc/eluadoc/template.lua 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/eluadoc/template.lua 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,52 @@
+-- eLua platform interface - name
+
+data_en =
+{
+
+ -- Title
+ title = "eLua platform interface - name",
+
+ -- Menu name
+ menu_name = "name"
+
+ -- Overview
+ overview = [[
+ ]],
+
+ -- Data structures, constants and types
+ structures =
+ {
+ { text = [[ ]],
+ name = "",
+ desc = [[ ]]
+ },
+ },
+
+ -- Functions
+ funcs =
+ {
+ { sig = "void #functionname#( void )",
+ desc = [[ ]],
+ args =
+ {
+ "$name$ - desc",
+ "$name$ - desc",
+ },
+ ret =
+ {
+ "",
+ [[ ]],
+ },
+ },
+
+ },
+
+ -- Aux data
+ auxdata =
+ {
+ { title = "",
+ desc = [[]]
+ }
+ }
+}
+
Added: branches/eagle_mmc/doc/eluadoc.lua
===================================================================
--- branches/eagle_mmc/doc/eluadoc.lua 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/eluadoc.lua 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,356 @@
+-------------------------------------------------------------------------------
+-- eLua doc builder module (for the eluadoc/ directory)
+
+module( ..., package.seeall )
+
+local sf = string.format
+
+-------------------------------------------------------------------------------
+-- Data structure declarations
+
+-- List here all the sections for which we're generating the documentation
+local doc_sections = { "arch_platform", "refman_gen", "refman_ps_lm3s" }
+
+-- List here all the components of each section
+local components =
+{
+ arch_platform = { "ll", "pio", "spi", "uart", "timers", "pwm", "cpu", "eth", "adc" },
+ refman_gen = { "bit", "pd", "cpu", "pack", "adc", "term", "pio", "uart", "spi", "tmr", "pwm", "net" },
+ refman_ps_lm3s = { "disp" }
+}
+
+-------------------------------------------------------------------------------
+-- Generic helpers and doc text formatting functions
+
+-- Format a name to a link by changing all the spaces to "_" and
+-- making all letters lowercase
+local function name2link( str )
+ str = str:gsub( " ", "_" )
+ return str:lower()
+end
+
+-- Returns the part of the string enclosed between two '#' chars
+-- Used for parsing function sig.
+local function namefromsig( str )
+ local _, _, name = str:find( "#(.*)#" )
+ return name
+end
+
+-- Adds a "." to the end of the string if it's not already present
+local function dot( str )
+ -- return str:sub( -1 ) == "." and str or str .. "."
+ return str
+end
+
+--[[ Process the given string as follows:
+- $string$ becomes <b>string</b>
+- %string% becomes <i>string</i>
+- @ref at text@ becomes <a href="ref">text</a>
+- ^ref^text^ also becomes <a href="ref">text</a>
+- $$, %%, @@, ^^ become $, %, @, ^ respectively
+- the string "eLua" becomes <b>eLua</b>
+- strings between two tildas (~~) get special code-like formatting
+- newlines are changed to ' ' if 'keepnl' isn't true
+- '&' is translated to its corresponding HTML code.
+- '<<' and '>>" are also translated to the corresponding HTML codes (note the repetition).
+--]]
+local function format_string( str, keepnl )
+ -- replace double "special chars" with "temps" for later use
+ str = str:gsub( "%$%$", "\001" )
+ str = str:gsub( "%%%%", "\002" )
+ str = str:gsub( "@@", "\003" )
+ str = str:gsub( "%^%^", "\004" )
+ str = str:gsub( "~~", "\005" )
+
+ -- Translate 'special' HTML chars to their equivalents
+ local tr_table =
+ {
+ [ "%&" ] = "&",
+ }
+ for char, rep in pairs( tr_table ) do
+ str = str:gsub( char, rep )
+ end
+
+ -- some double chars are replaced directly with their HTML codes
+ str = str:gsub( "<<", "<" )
+ str = str:gsub( ">>", ">" )
+
+ -- replace eLua with <b>eLua</b>
+ str = str:gsub( "eLua", "<b>eLua</b>" )
+
+ -- $string$ becomes <b>string></b>
+ str = str:gsub( "%$(.-)%$", "<b>%1</b>" )
+
+ -- %string% becomes <i>string</i>
+ str = str:gsub( "%%(.-)%%", "<i>%1</i>" )
+
+ -- @ref at text@ becomes <a href="ref">text</a>
+ str = str:gsub( "@(.-)@(.-)@", '<a href="%1">%2</a>' )
+
+ -- ^ref^text^ becomes <a href="ref">text</a>
+ str = str:gsub( "%^(.-)%^(.-)%^", '<a href="%1">%2</a>' )
+
+ -- strings between two tildas (~~) get special code-like formatting
+ -- must keep '\n', so replace it with "temps" for now
+ str = str:gsub( "~(.-)~", function( data ) return '<pre class="code">' .. data:gsub( "\n", "\006" ) .. "</pre>" end )
+ str = str:gsub( "~~", "~" )
+
+ -- other "\n" chars should dissapear now
+ if not keepnl then str = str:gsub( "\n", " " ) end
+
+ -- put back the "temps"
+ str = str:gsub( "\001", "%$" )
+ str = str:gsub( "\002", "%%" )
+ str = str:gsub( "\003", "@" )
+ str = str:gsub( "\004", "%^" )
+ str = str:gsub( "\005", "~" )
+ str = str:gsub( "\006", "\n" )
+
+ -- all done
+ return str
+end
+
+-------------------------------------------------------------------------------
+-- Content generation
+
+-- Build the documentation starting from the given file
+local function build_file( fname )
+ dofile( fname )
+ local res = {}
+
+ for _, lang in pairs( languages ) do
+ res[ lang ] = {}
+ res[ lang ].menu = {}
+ local menu = res[ lang ].menu
+
+ -- we need english always
+ -- the other languages will be substituted with english if not found
+ local resname = string.format( "data_%s", lang )
+ local r = _G[ resname ]
+ if not r then
+ if lang == "en" then
+ return false, "data_en must exist in the description"
+ else
+ print( string.format( "'%s': data for language '%s' not found, defaulting to english", fname, lang ) )
+ r = _G.data_en
+ end
+ end
+
+ -- process names
+ if not r.menu_name then
+ return false, "menu_names not found"
+ end
+ menu.name = r.menu_name
+
+ -- process title
+ if not r.title then
+ return false, "title not found"
+ end
+ local page = "$$HEADER$$\n"
+ menu.title = r.title
+
+ -- process overview
+ if not r.overview then
+ return false, "overview not found"
+ end
+ page = page .. '<a name="overview" /><h3>Overview</h3>\n<p>' .. format_string( r.overview ) .. "</p>\n\n"
+
+ -- process structures if needed
+ if r.structures then
+ local structures = r.structures
+ menu.structs = {}
+ page = page .. '<a name="structures" /><h3>Data structures, constants and types</h3>\n'
+ for i = 1, #structures do
+ local s = structures[ i ]
+ menu.structs[ #menu.structs + 1 ] = s.name
+ if not s.text or not s.desc or not s.name then
+ return false, "structure without text, desc or name fields"
+ end
+ -- text/name. The link name is ALWAYS the one in ENGLISH.
+ page = page .. string.format( '<a name="%s" />', name2link( res.en.menu.structs[ i ] ) )
+ page = page .. "<pre><code>" .. format_string( s.text, true ) .. "</code></pre>\n"
+ -- description
+ page = page .. '<div class="docdiv">\n<p>' .. format_string( s.desc ) .. "</p>\n</div>\n\n"
+ end
+ end
+
+ -- process functions now
+ if not r.funcs then
+ return false, "funcs not found"
+ end
+ local funcs = r.funcs
+ page = page .. '<a name="funcs" /><h3>Functions</h3>\n<div class="docdiv">\n'
+ menu.funcs = {}
+ for i = 1, #funcs do
+ local f = funcs[ i ]
+ if not f.sig or not f.desc then
+ return false, "function without sig or desc fields"
+ end
+ local funcname = namefromsig( f.sig )
+ if not funcname then
+ return false, string.format( "'%s' should contain the function name between '*' chars", f.sig )
+ end
+ menu.funcs[ #menu.funcs + 1 ] = funcname
+ -- signature
+ page = page .. string.format( '<a name="%s" />', funcname )
+ page = page .. "<pre><code>" .. f.sig:gsub( '#', '' ) .. "</code></pre>"
+ -- description
+ page = page .. "\n<p>" .. dot( format_string( f.desc ) ) .. "</p>\n"
+ -- arguments
+ page = page .. "<p><b>Arguments</b>: "
+ if f.args then
+ local a = f.args
+ if type( a ) == "string" or ( type( a ) == "table" and #a == 1 ) then
+ local text = type( a ) == "string" and a or a[ 1 ]
+ page = page .. dot( format_string( text ) ) .. "</p>"
+ else
+ page = page .. "</p>\n<ul>\n"
+ for i = 1, #a do page = page .. " <li>" .. dot( format_string( a[ i ] ) ) .. "</li>\n" end
+ page = page .. "</ul>"
+ end
+ else
+ page = page .. "none.</p>"
+ end
+ page = page .. "\n"
+ -- return value
+ page = page .. "<p><b>Returns</b>: "
+ if f.ret then
+ local r = f.ret
+ if type( r ) == "string" or ( type( r ) == "table" and #r == 1 ) then
+ local text = type( r ) == "string" and r or r[ 1 ]
+ page = page .. dot( format_string( text ) ) .. "</p>"
+ else
+ page = page .. "</p>\n<ul>\n"
+ for i = 1, #r do page = page .. " <li>" .. dot( format_string( r[ i ] ) ) .. "</li>\n" end
+ page = page .. "</ul>"
+ end
+ else
+ page = page .. "nothing.</p>"
+ end
+ page = page .. "\n\n"
+ end
+ page = page .. "</div>\n"
+
+ -- aux data (if any)
+ if r.auxdata then
+ local auxdata = r.auxdata
+ menu.auxdata = {}
+ for i = 1, #auxdata do
+ local a = auxdata[ i ]
+ menu.auxdata[ #menu.auxdata + 1 ] = a.title
+ if not a.title or not a.desc then
+ return false, "auxdata without title or desc"
+ end
+ -- the link name is ALWAYS the one in ENGLISH
+ page = page .. string.format( '<a name="%s" />', name2link( res.en.menu.auxdata[ i ] ) )
+ page = page .. "<h3>" .. a.title .. "</h3>"
+ page = page .. "\n<p>" .. format_string( a.desc ) .. "</p>\n\n"
+ end
+ end
+
+ -- footer
+ page = page .. "$$FOOTER$$\n"
+ -- Cleanup: remove "<p></p>" (which might appear due to formatting)
+ page = page:gsub( "<p>%s-</p>", "" )
+ res[ lang ].page = page
+ end
+
+ return res
+end
+
+-------------------------------------------------------------------------------
+-- Menu generation
+
+-- Helper function to get strings in all languages when needed
+local function all_langs( getstr )
+ local langs = {}
+ for _, lang in pairs( languages ) do
+ langs[ #langs + 1 ] = getstr( lang )
+ end
+ return langs
+end
+
+-- Transform the data from the menu dictionary (in 'fulldata') for component 'component' and section 'sect' to a menu structure
+local function gen_menu( fulldata, component, sect )
+ local relfname = sect .. "_" .. component .. ".html"
+ local res = fulldata[ component ]
+ local themenu = { all_langs( function( x ) return res[ x ].menu.name end ), relfname, {}, all_langs( function( x ) return res[ x ].menu.title end ) }
+ local sub = themenu[ submenu_idx ]
+
+ -- Overview
+ sub[ #sub + 1 ] = { all_langs( function( x ) return getstr( "Overview", x ) end ), sf( "%s#overview", relfname ) }
+
+ -- Data structures (if needed)
+ if res.en.menu.structs then
+ sub[ #sub + 1 ] = { all_langs( function( x ) return getstr( "Data structures", x ) end ), sf( "%s#structures", relfname ), {} }
+ local s_sub = sub[ #sub ][ submenu_idx ]
+ for i = 1, #res.en.menu.structs do
+ local v = res.en.menu.structs[ i ]
+ s_sub[ #s_sub + 1 ] = { all_langs( function( x ) return res[ x ].menu.structs[ i ] end ), sf( "%s#%s", relfname, name2link( v ) ) }
+ end
+ end
+
+ -- Functions
+ sub[ #sub + 1 ] = { all_langs( function( x ) return getstr( "Functions", x ) end ), sf( "%s#funcs", relfname ), {} }
+ local f_sub = sub[ #sub ][ submenu_idx ]
+ for _, v in pairs( res.en.menu.funcs ) do
+ f_sub[ #f_sub + 1 ] = { all_langs( function( x ) return v end ), sf( "%s#%s", relfname, name2link( v ) ) }
+ end
+
+ -- Aux data (if needed)
+ if res.en.menu.auxdata then
+ for i = 1, #res.en.menu.auxdata do
+ local v = res.en.menu.auxdata[ i ]
+ sub[ #sub + 1 ] = { all_langs( function( x ) return res[ x ].menu.auxdata[ i ] end ), sf( "%s#%s", relfname, name2link( v ) ) }
+ end
+ end
+
+ return themenu
+end
+
+-------------------------------------------------------------------------------
+-- Generate documentation from eluadoc for all languages
+
+function gen_html_doc()
+ local menu, genfiles = {}, {}
+
+ for _, section in pairs( doc_sections ) do
+ -- Generate documentation for each module in turn
+ local fulldata = {}
+ menu[ section ] = {}
+ local ms = menu[ section ]
+ -- First generate HTML documentation
+ for _, modname in pairs( components[ section ] ) do
+ local descfname = string.format( "eluadoc/%s_%s.lua", section, modname )
+ local res, err = build_file( descfname )
+ if res then
+ fulldata[ modname ] = res
+ -- Write doc for each language
+ for _, lang in pairs( languages ) do
+ local fname = string.format( "%s/%s_%s.html", lang, section, modname )
+ local f = io.open( fname, "wb" )
+ if not f then
+ print( string.format( "Unable to open %s for writing", fname ) )
+ return
+ else
+ f:write( res[ lang ].page )
+ f:close()
+ print( ( "Wrote %s" ):format( fname ) )
+ genfiles[ #genfiles + 1 ] = fname
+ end
+ end
+ else
+ print( string.format( "Error processing module '%s': %s", modname, err ) )
+ return
+ end
+ end
+
+ -- Then generate menu data
+ for _, modname in pairs( components[ section ] ) do
+ local submenu= gen_menu( fulldata, modname, section )
+ ms[ #ms + 1 ] = submenu
+ end
+ end
+ return menu, genfiles
+end
+
Modified: branches/eagle_mmc/doc/en/arch.html
===================================================================
--- branches/eagle_mmc/doc/en/arch.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/en/arch.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,9 +1,9 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8"/>
<meta http-equiv="Content-Language" content="en-us"><title>eLua architecture</title>
-<link rel="stylesheet" type="text/css" href="../style.css"></head>
+<link rel="stylesheet" type="text/css" href="../style.css"></link></head>
<body style="background-color: rgb(255, 255, 255);">
<h3>The eLua architecture</h3>
<p>This section presents in-depth details about the design and implementation of <b>eLua</b>. It's meant as a guide mainly for <b>eLua</b> developers,
Modified: branches/eagle_mmc/doc/en/arch_coding.html
===================================================================
--- branches/eagle_mmc/doc/en/arch_coding.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/en/arch_coding.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,94 +1,88 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>eLua coding style</title>
-
-<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);">
+$$HEADER$$
<h3>The eLua coding style</h3>
-<p>This section presents the <b>eLua</b> coding style that should be followed by every developer working on <b>eLua</b>. The following rules apply:
+<p>This section presents the <b>eLua</b> coding style that should be followed by every developer working on <b>eLua</b>. The following rules apply:</p>
<ol>
<li>Everything should be spaced out properly. Examples (please note the spacing rules, which is basically "space out everything for readability"):
- <p><pre><code>i = 3 (not i=3)
+ <pre><code>i = 3 (not i=3)
a = ( a + 5 ) / 3
for( i = 0; i < 10; i ++ ) ...
if( ( i == 5 ) && ( a == 10 ) ) ...
unsigned i = ( unsigned )p;
-void func( int arg1, const char* arg2 ) ...</code></pre></p></li>
- <li><b>Indentation</b>: indent everything at 2 SPACES. Again, <b>SPACES</b>. <b>DO NOT USE TABS</b>; this is important (and fortunately pretty easy to remember :) ).
+void func( int arg1, const char* arg2 ) ...</code></pre></li>
+ <li><b>Indentation</b>: indent everything at 2 SPACES. Again, <b>SPACES</b>. <span class="warning">DO NOT USE TABS</span>; this is important (and fortunately pretty easy to remember :) ).
There are too many examples where tabs completely destroyed the readability of source code. Most editors have an "insert tabs instead of spaces" option;
use it, and set your "tab size" to 2.<br>
Also, indent "{" and "}" on their own lines:
- <p><pre><code>if( i == 2 )
+ <pre><code>if( i == 2 )
{
// some code here
}
else
{
// some other code here
-}</code></pre></p>
+}</code></pre>
Or:
-<p><pre><code>void f( int i )
+<pre><code>void f( int i )
{
// function code
-}</code></pre></p>
+}</code></pre>
Do not enclose single statements in {} when given a choice. For example, do this:
-<p><pre><code>if( i == 2 )
- return;</code></pre></p>
+<pre><code>if( i == 2 )
+ return;</code></pre>
instead of this:
-<p><pre><code>if( i == 2 )
+<pre><code>if( i == 2 )
{
return;
-}</code></pre></p>
+}</code></pre>
Also, follow the "one statement per line" rule. In other words, don't do this:
-<p><pre><code>if( i == 2 ) return;</code></pre></p>
+<pre><code>if( i == 2 ) return;</code></pre>
Do this instead:
-<p><pre><code>if( i == 2 )
- return;</code></pre></p>
+<pre><code>if( i == 2 )
+ return;</code></pre>
Note that <b>eLua</b> code does not use a space between the function name and its parameter list when calling/defining it (like in the Lua code, for example). So do this:
-<p><pre><code>void f( int i )
+<pre><code>void f( int i )
{
// function code here
}
-f( 2 ); // function call</code></pre></p>
+f( 2 ); // function call</code></pre>
instead of this:
-<p><pre><code>void f ( int i )
+<pre><code>void f ( int i )
{
// function code here
}
-f ( 2 ); // function call</code></pre></p></li>
-<li><b>line terminators</b>: <b>THIS IS IMPORTANT TOO!</b> Use UNIX style (LF) line terminators, not DOS (CR/LF) or old Mac (CR) line terminators.</li>
+f ( 2 ); // function call</code></pre></li>
+<li><b>line terminators</b>: <span class="warning">THIS IS IMPORTANT!</span> Use UNIX style (LF) line terminators, not DOS (CR/LF) or old Mac (CR) line terminators.</li>
<li><b>identifier names</b>: use a "GNU-style" here, with underlines and all lowercase:
- <p><pre><code>int simple;
+ <pre><code>int simple;
double another_identifier;
-char yes_this_is_OK_although_quite_stupid;</code></pre></p>
+char yes_this_is_OK_although_quite_stupid;</code></pre>
As opposed to:
- <p><pre><code>int Simple1;
+ <pre><code>int Simple1;
double AnotherIdentifier;
-char DontEvenThinkAboutWritingSomethingLikeThis;</code></pre></p>
+char DontEvenThinkAboutWritingSomethingLikeThis;</code></pre>
<b>DO NOT USE HUNGARIAN NOTATION</b> (like iNumber, sString, fFloat ... if you don't know what that is, it's fine, as it means that we don't need to worry about it :) ). It has its advantages
when used properly, it's just not for <b>eLua</b>.
</li>
<li><b>constants in code</b>: don't ever write something like this:
- <p><pre><code>if( key == 10 )
+ <pre><code>if( key == 10 )
sys_ok();
else if( key == 5 )
phone_dial( "911" );
@@ -100,11 +94,11 @@
else if( key == 0 )
sys_retry();
else
- sys_error();</code></pre></p>
+ sys_error();</code></pre>
Instead, define some constants with meaningful names (via enums or even #define) and write like this:
- <p><pre><code>if( key == KEY_CODE_OK )
+ <pre><code>if( key == KEY_CODE_OK )
sys_ok();
else if( key == KEY_CODE_FATAL_ERROR )
phone_dial( "911" );
@@ -116,10 +110,10 @@
else if( key == KEY_CODE_NONE )
sys_retry();
else
- sys_error();</code></pre></p>
+ sys_error();</code></pre>
You can see in this example an accepted violation of the "one statement per line" rule: it's OK to write "else if (newcondition)" on the same line.</li>
-<li>use specific data types as much as possible. In this context, <b>specific data types</b> reffers to generic types that have the same size on all
+<li>use specific data types as much as possible. In this context, <b>specific data types</b> refers to generic types that have the same size on all
platforms. They are defined by each platform in turn and their meaning is given below:
<ul>
<li><b>s8</b>: signed 8-bit integer</li>
@@ -138,30 +132,30 @@
<li><b>endianness</b>: remember that <b>eLua</b> runs on both little endian and big endian architectures, and write your code accordingly.</li>
-<li><b>comments</b>: we generally favour C++ style comments (//), but it's perfectly OK to use C style (/**/) comments. Automatic documentation generators like Doxygen aren't encouraged, since
- they tend to make the programmer overdocument the code to the point where it becomes hard to read because of the documentation alone. Ideally, you'd neither overdocument, nor
- underdocument your code; just document it as much as you think it's needed, without getting into too much details, but also without omitting important information. In particular, DON'T do this:
+<li><b>comments</b>: we generally favor C++ style comments (//), but it's perfectly OK to use C style (/**/) comments. Automatic documentation generators like Doxygen aren't encouraged, since
+ they tend to make the programmer over-document the code to the point where it becomes hard to read because of the documentation alone. Ideally, you'd neither over-document, nor
+ under-document your code; just document it as much as you think it's needed, without getting into too much details, but also without omitting important information. In particular, DON'T do this:
- <p><pre><code>// This function returns the sum of two numbers
+ <pre><code>// This function returns the sum of two numbers
// Input: n1 - first number
// Input: n2 - the second number
// Output: the sum of n1 and n2
int sum( int n1, int n2 )
{
return n1 + n2;
-}</code></pre></p>
+}</code></pre>
When something is self-obvious from the context, documenting it more is pointless and decreases readability.</li>
<li><b>pseudo name-spaces</b>: since we don't have namespaces in C, I like to "emulate" them by prefixing anything (constants, variables, functions) in a file with something that identifies that
file uniquely (most likely its name, but this is not a definite rule). For example, a file called "uart.c" would look like this:
- <p><pre><code>int uart_tx_count, uart_rx_count;
+ <pre><code>int uart_tx_count, uart_rx_count;
int uart_receive( unsigned limit )...
-unsigned uart_send( const char *buf, unsigned size )...</code></pre></p>
+unsigned uart_send( const char *buf, unsigned size )...</code></pre>
</li>
-</ol></p>
+</ol>
<p>Also, if you're using 3rd party code (from a library/support package for example) making it follow the above rules is nice, but not mandatory. Focus on functionality and writing your own code properly, and come back to indent other people's code when you really don't have anything better to do with your time.</p>
-</body></html>
+$$FOOTER$$
Modified: branches/eagle_mmc/doc/en/arch_con_term.html
===================================================================
--- branches/eagle_mmc/doc/en/arch_con_term.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/en/arch_con_term.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,29 +1,23 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>eLua consoles and terminals</title>
-
-<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);">
+$$HEADER$$
<h3>eLua consoles and terminals</h3>
-<p>In <b>eLua</b>, a <b>console</b> and a <b>terminal</b> serve two related, but different purposes:
+<p>In <b>eLua</b>, a <b>console</b> and a <b>terminal</b> serve two related, but different purposes:</p>
<ul>
<li>the <b>console</b> takes care of basic user input/output. They come in two flavours: serial consoles and TCP/IP consoles (note that the two can't coexist at the same time).</li>
<li>the <b>terminal</b> enhances the console in order to take advantage of ANSI terminals and their advanced control functions, like explicit cursor positioning, clear screen and others. At this
time, terminals work only over serial connections, not over TCP/IP (like consoles).</li>
-</ul></p>
+</ul>
<p>Both components can be enabled and disabled as needed (they don't rely on each other). See <a href="building.html">building eLua</a> for details on how to enable and disable components.</p>
<h2>Serial consoles</h2>
<p>The serial console input/output is handled by a generic layer (<i>src/newlib/genstd.c</i>) that can be used to easily adapt the console subsystem to a variety of input/output devices.
It needs just two functions, one for displaying characters and another one for receiving input with timeout:</p>
-<p><pre><code>// Send/receive function types
+<pre><code>// Send/receive function types
typedef void ( *p_std_send_char )( int fd, char c );
typedef int ( *p_std_get_char )( s32 to );
-</code></pre></p>
+</code></pre>
<p>(the <b>send</b> faction gets an additional <b>fd</b> parameter that you can use to differentiate between the standard C stdout and stderr output streams).</p>
<p>To set them, use <b>std_set_send_func</b> and <b>std_set_get_func</b>, both defined in <i>inc/newlib/getstd.h</i>. Usually they are called from <i>src/common.c</i> and configured to work
over UART by default:</p>
-<p><pre><code>// *****************************************************************************
+<pre><code>// *****************************************************************************
// std functions and platform initialization
static void uart_send( int fd, char c )
@@ -43,7 +37,7 @@
std_set_send_func( uart_send );
std_set_get_func( uart_recv );
}
-</code></pre></p>
+</code></pre>
<p>If you need another type of serial console device (for example a dedicated console running over a SPI connection) just call <i>std_set_send_func/std_set_get_func</i> with the appropriate
function pointers.</p>
<p>To enable serial consoles, define the <b>BUILD_CON_GENERIC</b> macro in your platform's <b>platform_conf.h</b> file.</p>
@@ -53,8 +47,8 @@
<h2>Terminals</h2>
<p>Besides standard stdio/stdout/stderr support provided by consoles, <b>eLua</b> uses the "term" module to access ANSI compatible terminal emulators. It is designed to be as flexible as
possible, thus allowing a large number of terminal emulators to be used. To enable terminal support, add <b>BUILD_TERM</b> in your platform's <b>platform_conf.h</b> file. To use it, initialize
- it with a call to <b>term_init</b>:
-<p><pre><code>...........................
+ it with a call to <b>term_init</b>:</p>
+<pre><code>...........................
// Terminal output function
typedef void ( *p_term_out )( u8 );
// Terminal input function
@@ -65,25 +59,26 @@
// Terminal initialization
void term_init( unsigned lines, unsigned cols, p_term_out term_out_func,
p_term_in term_in_func, p_term_translate term_translate_func );
-</code></pre></p>
-<p>The initialization function takes the physical size of the terminal emulator window (usually 80 lines and 25 cols) and three function pointers:
+</code></pre>
+<p>The initialization function takes the physical size of the terminal emulator window (usually 80 lines and 25 cols) and three function pointers:</p>
<ul>
<li><b>p_term_out</b>: this function will be called to output characters to the terminal. It receives the character to output as its single parameter.</li>
<li><b>p_term_in</b>: this function will be called to read a character from the terminal. It receives a parameter that can be either TERM_INPUT_DONT_WAIT (in which case the function returns
-1 immediately if no character is available) or TERM_INPUT_WAIT (in which case the function will wait for the character).</li>
<li><b>p_term_translate</b>: this function translates terminal-specific codes to "term" codes. The "term" codes are defined in an enum from <i>inc/term.h</i>:
-<p><pre><code>...........................
+<pre><code>...........................
_D( KC_UP ),\
_D( KC_DOWN ),\
_D( KC_LEFT ),\
...........................
_D( KC_ESC ),\
_D( KC_UNKNOWN )
-...........................</code></pre></p>
+...........................</code></pre>
By using this function, it is possible to adapt a very large number of "term emulators" to <b>eLua</b>. For example, you might want to run eLua in a "standalone
mode" that does not require a PC at all, just an external LCD display and maybe a keyboard for data input. Your <b>eLua</b> board can connect to this standalone terminal using its
I/O pins or built in peripherals, for example via SPI. By writing the three functions described above, the effort of making <b>eLua</b> work with this new type of device is minimal,
and also writing an "ANSI emulator" for your terminal device is not hard.</li></ul>
<p>For an example, see <i>src/main.c</i>, where these functions are implemented for an UART connection with a terminal emulator program running on PC.</p>
-<p><b>eLua</b> also provides a Lua module (called <b>term</b>) that can be used to access ANSI terminal. See <a href="">the term module API</a> for a full description of this module.</p>
-</body></html>
+<p><b>eLua</b> also provides a Lua module (called <b>term</b>) that can be used to access ANSI terminal. See <a href="refman_gen_term.html">the term module API</a> for a full description of this module.</p>
+$$FOOTER$$
+
Modified: branches/eagle_mmc/doc/en/arch_ltr.html
===================================================================
--- branches/eagle_mmc/doc/en/arch_ltr.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/en/arch_ltr.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,10 +1,4 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Modules and LTR</title>
-
-<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);">
+$$HEADER$$
<h3>Modules and LTR</h3>
<p>LTR (Lua Tiny RAM) is a Lua patch (written specifically for <b>eLua</b> by Bogdan Marinescu) that significantly decreases the RAM usage of Lua scripts,
thus making it possible to run large Lua programs on systems with limited RAM. This section gives a full description of LTR. If you're writing <b>eLua</b>
@@ -25,7 +19,7 @@
<h2>Details</h2>
<p>The patch adds two new data types to Lua. Both or them are based on the lightuserdata type already found in Lua, and they share the same basic
attributes: they don't need to be dynamically allocated (as they're just pointers on steroids) and they're compared in the same way lightuserdatas
- are compared (by value). And of course, they are not collectable, so the garbage collector won't have anything to do with them. The new types are:
+ are compared (by value). And of course, they are not collectable, so the garbage collector won't have anything to do with them. The new types are:</p>
<ol>
<li><b>lightfunctions</b>: these are "simple" functions, in the sense that they can't have upvalues or environments. They are just pointers to regular
C functions. Other than that, you can use them from Lua just as you'd use any other function.</li>
@@ -39,8 +33,8 @@
<li>you can use rotables as metatables for both "regular" tables and for Lua types (via debug.setmetatable)</li>
<li>a rotable can have another rotable (or tself) as a metatable</li>
<li>you can iterate over rotables with pairs/ipairs/next just as you do with "regular" tables.</li>
-</ul></li></ol></p>
-<p>Just as with lightuserdata, you can only create lightfunctions and rotables from C code, never from Lua itself.<p>
+</ul></li></ol>
+<p>Just as with lightuserdata, you can only create lightfunctions and rotables from C code, never from Lua itself.</p>
<h2>Testing</h2>
<p>I tested my patch with the (<a target="_blank" href="http://lua-users.org/lists/lua-l/2006-03/msg00723.html">Lua 5.1 test suite</a>). The test suite
was an excellent testing tool. I thought I had the patch ready until I found the test suite and ran it. After another week of work, I had something
@@ -48,7 +42,7 @@
<p>I tested everything via "make generic", which is how I always build Lua for my embedded environments. This means (among other things) that I didn't
test pipes and dynamic module loading, although I don't see why they wouldn't work.</p>
<p>I never tested the patch in a multithreaded environment with more threads running different lua_States. I never even used regular Lua like this,
-so I can't make asumptions about how my patch would behave in a multithreaded environment. It doesn't use any global or static variables, but you
+so I can't make assumptions about how my patch would behave in a multithreaded environment. It doesn't use any global or static variables, but you
might encounter other problems with it.</p>
<h2>Results</h2>
<p>The table below summarizes the RAM usage in KBytes (as obtained by running <i>lua -e "print(collectgarbage'count')"</i> from the <b>eLua</b> shell).
@@ -98,14 +92,14 @@
</tr>
</tbody>
</table>
-</p>
+
<p>As you can see, the differences are significant, and (more important) it doesn't matter how many modules you load in <b>eLua</b>, the RAM consumption
doesn't modify.</p>
<p>Currently, there aren't any performane measurements related to LTR. It's clear from the implementation that the patch slows down the virtual machine,
- but a precise performance penalty figure is not known. Experience suggests that the peformance penalty is minimal, and it certainly can't be observed
+ but a precise performance penalty figure is not known. Experience suggests that the performance penalty is minimal, and it certainly can't be observed
with "regular" (non-computationally intensive) Lua programs.</p>
<h2>How to enable LTR</h2>
-<p>Enabling LTR is very easy: all you need to do is specify the <b>opt=1</b> as a paramater to scons when bulding <b>eLua</b>, as explained
+<p>Enabling LTR is very easy: all you need to do is specify the <b>opt=1</b> as a parameter to scons when building <b>eLua</b>, as explained
<a href="building.html">here</a>. You don't even to specify this explicitly, as LTR is enabled by default for all <b>eLua</b> targets.</p>
<p>When <b>optram</b> is 0, LTR is not active. In this mode the patch just tries to keep the modified version as close as possible to the unpatched version
in terms of speed and functionality. You might want to use this if you want full Lua compatibility (although this is rarely an issue in practice),
@@ -132,21 +126,21 @@
luaL_register( L, "mod", mod_map );
return 1;
}</code></pre></p>
-<p>For the rotables implementation, however, you'd need to define the same thing like this:<p>
+<p>For the rotables implementation, however, you'd need to define the same thing like this:</p>
-<p><pre><code>const luaR_entry mod_map[] = <font color="red">// note: no static this time</font>
+<pre><code>const luaR_entry mod_map[] = <span class="warning">// note: no static this time</span>
{
{ LRO_STRKEY( "f" ), LRO_FUNCVAL( f_implementation ) },
{ LRO_NILKEY, LRO_NILVAL }
};
-<font color="red">// note: in this case the "luaopen_mod" function isn't really needed anymore</font>
+<span class="warning">// note: in this case the "luaopen_mod" function isn't really needed anymore</span>
LUALIB_API int luaopen_mod( lua_State *L )
{
return 0;
-}</code></pre></p>
+}</code></pre>
-<p>A few points about the rotables example above:
+<p>A few points about the rotables example above:</p>
<ul>
<li>a rotable needs a "map" (mod_map) array much like a regular module, but you need to define that array with special macros:
<ul>
@@ -154,29 +148,29 @@
(empty) key</li>
<li><b>for values</b>: <b>LRO_FUNCVAL(f)</b> defines a lightfunction value, <b>LRO_NUMVAL(f)</b> defines a number value, <b>LRO_RO(p)</b> defines a
rotable value (p is the pointer to the rotable) and <b>LRO_NILVAL</b> defines a NULL (empty) value.</li>
- </ul>
+ </ul></li>
<li>all the "global" rotables in the system (the ones that must be visible from <b>_G</b>, like the rotables of all the modules exported to Lua) must be
included in a special array, called <b>lua_rotable</b> (defined in <i>linit.c</i>). Simply including the rotable's definition array (mod_map in this case)
in the lua_rotable array makes it visible globally, thus you don't need to call any kind of register function. This is why <b>luaopen_mod</b> now returns
0.</li>
-</ul></p>
+</ul>
<p>The two forms above (for regular tables and for rotables) are clearly different, but we want to keep them both to be able to work at both <b>optram=0</b>
and <b>optram=2</b>. You can use #ifdefs to differentiate between the two cases in different optimization levels, but this becomes really annoying after
a (short) while. This is why I added another file called <b>lrodefs.h</b> (<i>src/lua</i>) that can be used to give an "universal" definition to our map
arrays. Here's how our example looks after rewriting it to take advantage of <b>lrodefs.h</b>:</p>
-<p><pre><code><font color="red">#define MIN_OPT_LEVEL 2 // the minimum optimization level at which we use rotables</font>
+<pre><code><span class="warning">#define MIN_OPT_LEVEL 2 // the minimum optimization level at which we use rotables</span>
#include "lrodefs.h"
-const <font color="red"> LUA_REG_TYPE</font> mod_map[] = <font color="red">// note: no more luaL_reg or luaR_entry</font>
+const <span class="warning"> LUA_REG_TYPE</span> mod_map[] = <span class="warning">// note: no more luaL_reg or luaR_entry</span>
{
{ LSTRKEY( "f" ), LFUNCVAL( f_implementation ) },
{ LNILKEY, LNILVAL }
};
-// <font color="red">note: no more LRO_something, just Lsomething (for example LRO_STRKEY becomes LSTRKEY)</font>
+// <span class="warning">note: no more LRO_something, just Lsomething (for example LRO_STRKEY becomes LSTRKEY)</span>
LUALIB_API int luaopen_mod( lua_State *L )
{
- <font color="red">LREGISTER</font>( L, "mod", mod_map ); // <font color="red">note: no more luaL_register, no "return 1"</font>
-}</code></pre></p>
+ <span class="warning">LREGISTER</span>( L, "mod", mod_map ); // <span class="warning">note: no more luaL_register, no "return 1"</span>
+}</code></pre>
<p>Now, if <b>LUA_OPTIMIZE_MEMORY</b> (a macro defined by the system as 0 when <b>optram=0</b> and as 2 when <b>optram=1</b>) is less than
<b>MIN_OPT_LEVEL</b>, the above definition will compile in its "regular table" format. If <b>LUA_OPTIMIZE_MEMORY</b> is 2, it compiles to the
rotables format. Problem solved :) <b>LREGISTER</b> will also take care of calling <b>luaL_register</b> and return 1 when <b>optram=0</b> and do
@@ -186,7 +180,7 @@
metatable, it needs a "__metatable" field to point to its metatable (which is also a rotable, not necessarily another rotable) and the usual
metatable functions. For example, let's make our <b>mod</b> rotable its own metatable and declare an <b>__index</b> function. Moreover, let's do
this for both <b>optram=0</b> and <b>optram=1</b>.</p>
-<p><pre><code>static int mod_mt_index( lua_State *L )
+<pre><code>static int mod_mt_index( lua_State *L )
{
return 0;
}
@@ -196,9 +190,9 @@
const LUA_REG_TYPE mod_map[] =
{
{ LSTRKEY( "f" ), LFUNCVAL( f_implementation ) },
-<font color="red">#if LUA_OPTIMIZE_MEMORY > 0
+<span class="warning">#if LUA_OPTIMIZE_MEMORY > 0
{ LSTRKEY( "__metatable" ), LROVAL( mod_map ) },
-#endif</font>
+#endif</span>
{ LSTRKEY( "__index" ), LFUNCVAL( mod_mt_index) },
{ LNILKEY, LNILVAL };
};
@@ -210,16 +204,16 @@
#else
luaL_register( L, "mod", mod_map );
- <font color="red">// Set "mod" as its own metatable
+ <span class="warning">// Set "mod" as its own metatable
lua_pushvalue( L, -1 );
- lua_setmetatable( L, -2 );</font>
+ lua_setmetatable( L, -2 );</span>
return 1;
#endif
-}</code></pre></p>
+}</code></pre>
<p>If you want to register a module using a regular Lua table, but use lightfunctions instead of regular functions, use <i>luaL_register_light</i> instead
of <i>luaL_register</i> (same syntax). </p>
-<p>More important things to keep in mind when working with LTR:
+<p>More important things to keep in mind when working with LTR:</p>
<ul>
<li>currently, <b>MIN_OPT_LEVEL</b> should be always set to 2</li>
<li>you need a C99-compatible compiler to use LTR (because of the compile-time explicit union initialization that's needed to declare const rotables).
@@ -228,13 +222,13 @@
placement (generally you'd declare stext at the beginning of .text definition and etext and the end of .text definition, see for example
<i>src/lua/at91sam7x256/flash256.lds</i>). These are needed by the patch to differentiate between a regular table and a rotable (although this is likely
to change in a future version of the patch.</li>
- <li><b><font color="red">remember to declare all you rotable's definition array as 'const'!!</font></b> Forgetting to do so will not only increase
+ <li><span class="warning">remember to declare all you rotable's definition array as 'const'!!</span> Forgetting to do so will not only increase
memory usage, it will also make the patch not functional, because of the way it recognizes rotables (see above).</li>
-</ul></p>
-<a name="config"><h2>LTR and module configuration at build time</h2></a>
+</ul>
+<a name="config" /><h2>LTR and module configuration at build time</h2>
<p>With unpatched Lua, you can specify what modules to be part of the Lua image by modifying <i>src/lua/linit.c</i>. In the particular case of <b>eLua</b>
one had to declare a list of the modules that must be compiled in <i>src/platform/<name>/platform_conf.h</i> like this:</p>
-<p><pre><code>#define LUA_PLATFORM_LIBS\
+<pre><code>#define LUA_PLATFORM_LIBS\
{ AUXLIB_PIO, luaopen_pio },\
{ AUXLIB_TMR, luaopen_tmr },\
{ AUXLIB_PD, luaopen_pd },\
@@ -244,10 +238,10 @@
{ AUXLIB_PACK, luaopen_pack },\
{ AUXLIB_BIT, luaopen_bit },\
{ LUA_MATHLIBNAME, luaopen_math }
-</code></pre></p>
- Things are a bit more complex with LTR, but not by much. The list of modules that must be compiled is declared via a preprocessor macro in
+</code></pre>
+ <p>Things are a bit more complex with LTR, but not by much. The list of modules that must be compiled is declared via a preprocessor macro in
<i>src/platform/<name>/platform_conf.h</i> and it looks like this:</p>
-<p><pre><code>#define LUA_PLATFORM_LIBS_ROM\
+<pre><code>#define LUA_PLATFORM_LIBS_ROM\
_ROM( AUXLIB_PIO, luaopen_pio, pio_map )\
_ROM( AUXLIB_TMR, luaopen_tmr, tmr_map )\
_ROM( AUXLIB_PD, luaopen_pd, pd_map )\
@@ -256,14 +250,15 @@
_ROM( AUXLIB_PWM, luaopen_pwm, pwm_map )\
_ROM( AUXLIB_PACK, luaopen_pack, pack_map )\
_ROM( AUXLIB_BIT, luaopen_bit, bit_map )\
- _ROM( LUA_MATHLIBNAME, luaopen_math, math_map )</code></pre></p>
+ _ROM( LUA_MATHLIBNAME, luaopen_math, math_map )</code></pre>
<p>(<b>IMPORTANT NOTE</b>: the fact that there are no commas between two different _ROM declarations (as seen above) is NOT an error;
on the contrary, this is very much intended. Try using commas and you'll get in trouble very soon :) ).</p>
<p>Note the 3rd parameter of the <b>_ROM</b> macro, which is the name of the definition array for the (ro)table. That's it. The code in linit.c will take
care of everything else, including initializing the list of modules in LUA_PLATFORM_LIBS_ROM with regular tables instead of rotables at <b>optram=0</b>
- (to maintain compatilibity with regular Lua). You can also have a list of modules that you want to use with regular tables no matter what the
+ (to maintain compatibility with regular Lua). You can also have a list of modules that you want to use with regular tables no matter what the
optimization level is. In that case, list it in the <b>LUA_PLATFORM_LIBS_REG</b> macro via the old syntax for <b>LUA_PLATFORM_LIBS</b>, as shown
above (the regular Lua syntax for defining a module to be registered with luaL_register). If you want this module to use lightfunctions instead of
regular functions (at <b>optram=1</b>), use <i>luaL_register_light</i> instead of <i>luaL_register</i>.
</p>
-</body></html>
+$$FOOTER$$
+
Modified: branches/eagle_mmc/doc/en/arch_newport.html
===================================================================
--- branches/eagle_mmc/doc/en/arch_newport.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/en/arch_newport.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,18 +1,12 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Porting eLua</title>
-
-<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);">
+$$HEADER$$
<h3>Porting eLua</h3>
<p>So, you realized how cool <b>eLua</b> is :), and you'd like to give it a try. Unfortunately, <b>eLua</b> doesn't have a port on your CPU or board of choice.
The solution is simple: write the port yourself. This might seem as a daunting task at first, but it's actually easier than it sounds. <b>eLua</b> was
designed to make the task of implementing new ports as easy and intuitive as possible. This section gives an overview of the porting process. It's not
an exhaustive guide, but it should be enough to point you in the right direction. Before diving into this, it's highly recommended that you take a look
- at the <a href="elua_arch.html">eLua architecture page</a>. </p>
+ at the <a href="arch_overview.html">eLua architecture page</a>. </p>
<h3>Prerequisites</h3>
-<p>Before starting to work on the port, make sure that:
+<p>Before starting to work on the port, make sure that:</p>
<ul>
<li>your CPU has enough resources to run <b>eLua</b>. A very rough estimation (based on ARM Thumb code only) is that you'd need at least 256k
of program memory and 32k of RAM for a complete <b>eLua</b> image, and 128k of program memory for a basic image. It's possible to run <b>eLua</b> in
@@ -25,13 +19,13 @@
</li>
<li>you have a platform library (it usually comes from the CPU manufacturer) that you can use to implement (at least part of) the platform interface.
It's also highly recommended to gain at least a basic understanding of your platform, it will help a lot while writing the port.</li>
-</ul></p>
+</ul>
<p>If all of the above are true, you should continue reading this document to bring your port to life. If not, we're sorry, but (at least at this point)
<b>eLua</b> can't be ported to your CPU. If, on the other hand, you're good to go, please take a bit of time and read
<a href="arch_overview.html#platforms">this section</a> first, as it details the structure of a port and might simplify your work quite a bit.</p>
-<a name="newboard"><h3>Adding a new board</h3></a>
+<a name="newboard" /><h3>Adding a new board</h3>
<p>If all you need is to add a new board that uses a CPU already supported by <b>eLua</b> (check <a href="status.html">here</a> for a complete list), it's
-fairly easy to accomplish this:
+fairly easy to accomplish this:</p>
<ol>
<li>choose a good name for your board :)</li>
<li>edit <b>SConstruct</b> and add your board to the <b>board_list</b> dictionary, specifying its CPU. A part of the definition of <b>board_list</b> is given below:
@@ -44,15 +38,15 @@
</li>
<li>also edit the <b>file_list</b> dictionary in <b>SConstruct</b> to specify the list of ROMFS files that will be compiled for your board (see the
<a href="arch_romfs.html">ROMFS section</a> for details). A part of the definition of <b>file_list</b> is given below:
-<p><pre><code># List of board/romfs data combinations
+<pre><code># List of board/romfs data combinations
file_list = { 'SAM7-EX256' : [ 'bisect', 'hangman' , 'led', 'piano', 'hello', 'info', 'morse' ],
'EK-LM3S8962' : [ 'bisect', 'hangman', 'lhttpd', 'pong', 'led', 'piano', 'pwmled', 'tvbgone', 'hello', 'info', 'morse', 'adcscope' ],
'EK-LM3S6965' : [ 'bisect', 'hangman', 'lhttpd', 'pong', 'led', 'piano', 'pwmled', 'tvbgone', 'hello', 'info', 'morse', 'adcscope' ],
...............................
- }</code></pre></p></li>
+ }</code></pre></li>
<li>if your board has external memory, you'll probably want to use the "multiple" allocator by default to take advantage of that (see <a href="building.html">building</a>)
for details. If so, you need to modify the CPU/allocator mapping code from <b>SConstruct</b>:
-<p><pre><code># CPU/allocator mapping (if allocator not specified)
+<pre><code># CPU/allocator mapping (if allocator not specified)
if allocator == '':
if <b>boardname == 'LPC-H2888'</b> or <b>boardname == 'ATEVK1100'</b>:
allocator = 'multiple'
@@ -62,12 +56,12 @@
print "Unknown allocator", allocator
print "Allocator can be either 'newlib', 'multiple' or 'simple'"
sys.exit( -1 )
-</code></pre></p>
+</code></pre>
</li>
<li>customize the <b>eLua</b> image for this new board. You can use the variable <b>boardname</b> in <b>conf.py</b> to define new preprocessor macros specifically for your board
(that you can use later in <b>platform_conf.h</b>, for example), or to include or exclude certain files from the build, or change the build flags and so on. An example taken from
the <b>lm3s</b> port is given below (part of <b>conf.py</b>):
-<p><pre><code>if boardname == 'EK-LM3S6965' or boardname == 'EK-LM3S8962':
+<pre><code>if boardname == 'EK-LM3S6965' or boardname == 'EK-LM3S8962':
specific_files = specific_files + " rit128x96x4.c disp.c"
cdefs = cdefs + " -DENABLE_DISP"
@@ -77,16 +71,16 @@
linkopts = "-Wl,-Ttext,0x2000"
else:
linkopts = ""
-</code></pre></p>
+</code></pre>
</li>
-</ol></p>
+</ol>
<p>After you edit all the relevant source files, all you have to do is to execute <i>scons board=<boardname></i> and you'll have <b>eLua</b> compiled for your board.</p>
-<a name="newcpu"><h3>Adding a new CPU</h3></a>
+<a name="newcpu" /><h3>Adding a new CPU</h3>
<p>If you want to add a new CPU to <b>eLua</b> and the new CPU happens to be supported by a platform on which <b>eLua</b> already runs (see <a href="status.html">here</a> for a full
-list), your task is still quite easy. Follow the steps below:
+list), your task is still quite easy. Follow the steps below:</p>
<ol>
<li>edit <b>SConstruct</b> and add your new CPU to the <b>platform_list</b> dictionary. Use the "official" name of the CPU (as it appears in its datasheet). An example is given below:
-<p><pre><code># List of platform/CPU/toolchains combinations
+<pre><code># List of platform/CPU/toolchains combinations
# The first toolchain in the toolchains list is the default one
# (the one that will be used if none is specified)
platform_list = {
@@ -94,14 +88,14 @@
'lm3s' : { 'cpus' : [ 'LM3S8962', 'LM3S6965', 'LM3S6918' ], 'toolchains' : [ 'arm-gcc', 'codesourcery', 'devkitarm', 'arm-eabi-gcc' ] },
'str9' : { 'cpus' : [ 'STR912FAW44' ], 'toolchains' : [ 'arm-gcc', 'codesourcery', 'devkitarm', 'arm-eabi-gcc' ] },
..................
-}</code></pre></p></li>
+}</code></pre></li>
<li>you also need to add a new board to <b>eLua</b> (which makes sense, since you're most likely going to run <b>eLua</b> on a board built around the CPU
of your choice, not only on the CPU itself). So follow the instruction from the <a href="arch_newport.html#newboard">previous paragraph</a> to add
your new board.</li>
<li>customize the <b>eLua</b> image for this new CPU. You can use the variable <b>cputype</b> in <b>conf.py</b> to define new preprocessor macros specifically for your CPU
(that you can use later in <b>platform_conf.h</b>, for example), or to include or exclude certain files from the build, or change the build flags and so on. An example taken from
the <b>at91sam7x</b> port is given below (part of <b>conf.py</b>):
-<p><pre><code>if cputype == 'AT91SAM7X256':
+<pre><code>if cputype == 'AT91SAM7X256':
ldscript = "flash256.lds"
cdefs = cdefs + " -Dat91sam7x256"
elif cputype == 'AT91SAM7X512':
@@ -109,25 +103,25 @@
cdefs = cdefs + " -Dat91sam7x512"
else:
print "Invalid AT91SAM7X CPU %s" % cputype
- sys.exit( -1 ) </code></pre></p>
-</ol></p>
+ sys.exit( -1 ) </code></pre></li>
+</ol>
<p>After you edit all the relevant source files, all you have to do is to execute <i>scons board=<boardname></i> and you'll have <b>eLua</b> compiled for your board (and implicitly for
your new CPU).</p>
-<a name="newplatform"><h3>Adding a new platform</h3></a>
+<a name="newplatform" /><h3>Adding a new platform</h3>
<p>If you want to add a new CPU to <b>eLua</b> and the new CPU is not supported by a platform on which <b>eLua</b> already runs (see <a href="status.html">here</a> for a full list), you have to
go the whole way and add a completely new platform to <b>eLua</b>. This is certainly more difficult than the previous cases, but still not that hard. Remember to start small (implement only
minimal support at first) and don't write everything from scratch, start from an already existing platform implementation and work your way up from there. The <b>i386</b> port is the simplest,
but also a bit different from the embedded ports. Another port that is quite simple at this point is the <b>lpc2888</b> port, you might take a look at that too. After you "get a feeling" of
-how a port should look like, and after you read about the architecture of <b>eLua</b> and the structure of a port <a href="arch_overview.html">here</a>, follow the steps below:
+how a port should look like, and after you read about the architecture of <b>eLua</b> and the structure of a port <a href="arch_overview.html">here</a>, follow the steps below:</p>
<ol>
<li>choose the name of your new platform. It should be an easy, descriptive name. For example, all the CPUs from the LM3S series are grouped inside a platform called <b>lm3s</b>.</li>
<li>create the <i>src/platform/<name></i> directory, and add all your platform-specific files here. Check <a href="arch_overview.html#platforms">here</a> for specific details.</li>
- <li>use the instructions from the <a href="arch_newport.html#newcpu">previous paragraph</a> to add your new CPU and board to <b>eLua</b>.</b>
+ <li>use the instructions from the <a href="arch_newport.html#newcpu">previous paragraph</a> to add your new CPU and board to <b>eLua</b>.</li>
<li>implement as much as you need from the <a href="arch_platform.html">platform interface</a>.</li>
<li>if your new platform uses a toolchain that wasn't previously configured in <b>eLua</b>, add it now (see <a href="toolchains.html">here</a> for more details about toolchains).</li>
<li>let <b>SConstruct</b> know about your new platform by modifying the <b>platform_list</b> variable to add information about the CPU(s) available for your platform and about its toolchains.
An example is given below:
-<p><pre><code># List of platform/CPU/toolchains combinations
+<pre><code># List of platform/CPU/toolchains combinations
# The first toolchain in the toolchains list is the default one
# (the one that will be used if none is specified)
platform_list = {
@@ -135,9 +129,9 @@
'lm3s' : { 'cpus' : [ 'LM3S8962', 'LM3S6965', 'LM3S6918' ], 'toolchains' : [ 'arm-gcc', 'codesourcery', 'devkitarm', 'arm-eabi-gcc' ] },
'str9' : { 'cpus' : [ 'STR912FAW44' ], 'toolchains' : [ 'arm-gcc', 'codesourcery', 'devkitarm', 'arm-eabi-gcc' ] },
..................
-}</code></pre></p></li>
- </ul></li>
-</ol></p>
+}</code></pre></li>
+</ol>
<p>After you edit all the relevant source files, all you have to do is to execute <i>scons board=<boardname></i> and you'll have <b>eLua</b> compiled for your board (and implicitly for
your new CPU).</p>
-</body></html>
+$$FOOTER$$
+
Modified: branches/eagle_mmc/doc/en/arch_overview.html
===================================================================
--- branches/eagle_mmc/doc/en/arch_overview.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/en/arch_overview.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,24 +1,13 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>eLua architecture overview</title>
-
-<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);">
-<a name="structure"><h3>eLua architecture overview</h3></a>
+$$HEADER$$
+<a name="structure" /><h3>eLua architecture overview</h3>
<p>The overall logical structure of <b>eLua</b> is shown in the image below:</p>
-<map name="arch">
-<area href="arch_overview.html#common" title="Commond code" shape=rect coords="0, 402, 537, 540">
-<area href="arch_overview.html#platform" title="Platform interface" shape=rect coords="0, 198, 537, 336">
-<area href="arch_overview.html#platforms" title="Platforms" shape=rect coords="9, 0, 537, 132">
-</map>
-<p align="center"><img src="../wb_img/elua_arch.png" usemap="#arch" border=0></img></p>
+<p style="text-align: center; valign:middle;"><img src="images/elua_arch.png" style="border: 0;" alt="eLua architecture"></img></p>
<p><b>eLua</b> uses the notion of <b>platform</b> to denote a group of <b>CPUs</b> that share the same core structure, although their specific silicon
- implementation might differ in terms of intergrated peripherals, internal memory and other such attributes. An <b>eLua</b> port implements one or
+ implementation might differ in terms of integrated peripherals, internal memory and other such attributes. An <b>eLua</b> port implements one or
more CPUs from a given platform. For example, the <b>lm3s port</b> of <b>eLua</b> runs on LM3S8962, LM3S6965 and LM3S6918 CPUs, all of them part of the
<b>lm3s</b> platform. Refer to <a href="status.html">the status page</a> for a full list of platforms and CPUs on which <b>eLua</b> runs.</p>
<p>As can be seen from this image, <b>eLua</b> tries to be as portable as possible between different platforms by using a few simple design
-rules:
+rules:</p>
<ul>
<li>all code that is platform-independent is <b>common code</b> and it should be written in ANSI C as much as possible, this makes it highly portable
among different architectures and compilers, just like Lua itself. </li>
@@ -30,29 +19,29 @@
to group only common attributes of different platforms. If one needs to access the specific functionality on a given platform (like the loopback support
mentioned before) it can do so by using a <b>platform module</b>. These are of course platform specific, and their goal is to fill the gap between the
platform interface and the full set of features provided by a platform.</li>
-</ul></p>
-<a name="common"><h3>Common (generic) code</h3></a>
-<p>The following gives an incomplete set of items that can be classified as <b>common code</b>:
+</ul>
+<a name="common" /><h3>Common (generic) code</h3>
+<p>The following gives an incomplete set of items that can be classified as <b>common code</b>:</p>
<ul>
<li>the Lua code itself (obviously) plus the <a href="arch_ltr.html">LTR patch</a>.</li>
<li>all the <b>components</b> in <b>eLua</b> (like the ROM file system, the XMODEM receive code, the <b>eLua</b> shell, the TCP/IP stack and others).
</li>
<li>all the <b>generic modules</b>, which are Lua modules used to expose the functionality of the platform to Lua.</li>
<li>generic <b>peripheral support code</b>, like the ADC support code (<i>src/common/elua_adc.c</i>) that is <b>independent</b> of the actual ADC
- hardware.
- <li>libc code (for example allocators and Newlib stubs).
- </ul></p>
+ hardware.</li>
+ <li>libc code (for example allocators and Newlib stubs).</li>
+ </ul>
<p>This should give you a pretty good idea about what "common code" means in this context. Note that the generic code layer should be as "greedy" as
-possible; that is, it should absorb as much common code as possible. For example:
+possible; that is, it should absorb as much common code as possible. For example:</p>
<ul>
<li>if you want to add a new file system to <b>eLua</b>, this should definitely be generic code. It's likely that this kind of code will have
dependencies related to the physical medium on which this file system resides. If you're lucky, you can solve these dependencies using only the functions
- defined in the <a href="elua_platform.html">platform interface</a> (this would make sense if you're using a SD card controlled over SPI, since the
+ defined in the <a href="arch_platform.html">platform interface</a> (this would make sense if you're using a SD card controlled over SPI, since the
platform interface already has a SPI layer). If not, you should group the platform specific functions in a separate interface that will be implemented by
all platform that want to use your new file system. This gives the code maximum portability.</li>
<li>if you want to add a driver for a specific ADC chip that works over SPI, the same observations apply: write it as common code as much as you can,
- and use the <a href="elua_platform.html">platform interface</a> for the specific SPI functions you need.</li>
-</ul></p>
+ and use the <a href="arch_platform.html">platform interface</a> for the specific SPI functions you need.</li>
+</ul>
<p>When designing and implementing a new component, keep in mind other <b>eLua</b> design goal: <b>flexibility</b>. The user should be able to
select which components are part of its <b>eLua</b> binary image (as described <a href="building.html">here</a>), and the implementation should take
this into consideration. The same thing holds for the generic modules: the user must have a way to choose the set of modules he needs.</p>
@@ -61,7 +50,7 @@
over a large variety of physical transports (RS-232 for PC, SPI for a separate LCD/keyboard board, a radio link and so on) so it uses pointers for its
send/receive functions (see <a href="arch_con_term.html">this link</a> for more details). The impact on speed and resource consumption is minimum, but
it matters a lot in the portability department.</p>
-<a name="platform"><h3>Platform interface</h3></a>
+<a name="platform" /><h3>Platform interface</h3>
<p>Used properly, the platform interface allows writing extremely portable code over a large variety of different platforms, both from C and from Lua.
An important property of the platform interface is that it tries to group only <b>common</b> attributes of different platforms (as much as possible).
For example, if a platform supported by <b>eLua</b> has an UART that can work in loopback mode, but the others don't, loopback support won't be included
@@ -71,85 +60,85 @@
to implement a generic module and neeeds access to peripherals. An example was given in the previous section: implementing a new file system.</p>
<p>The platform interface definition is always in the <i>inc/platform.h</i> header file. For a full description of its functions, check
<a href="arch_platform.html">the platform interface documentation.</a></p>
-<a name="platforms"><h3>Platforms and ports</h3></a>
+<a name="platforms" /><h3>Platforms and ports</h3>
<p>All the platforms that run <b>eLua</b> (and that implement the platform interface) are implemened in this conceptual layer. A <b>port</b> is a full
<b>eLua</b> implementation on a given platform. The two terms can generally be used interchangeably.</p>
<p>A port can (and generally will) contain specific peripheral drivers, many times taken directly from the platform's CPU support
- package. These drivers are used to implement the platform interface. Note that:
+ package. These drivers are used to implement the platform interface. Note that:</p>
<ul>
<li>a port isn't required to implement <b>all</b> the platform interface functions, just the ones it needs. As explained
<a href="building.html">here</a>, the user must have full control over what's getting built into this <b>eLua</b> image. If you don't need the SPI
module, for example, you don't need to implement its platform interface.</li>
<li>a part of the platform interface is implemented (at least partially) in a file that is common for all the platforms (<i>src/common.c</i>). It
eases the implmentation of some modules (such as the timer module) and also implements common features that are tied to the platform interface,
- but have a common behaviour on all platforms (for example virtual timers, see <a href="">##here</a> for details). You probably won't need to modify
+ but have a common behaviour on all platforms (for example virtual timers, see <a href="arch_platform_timers.html#virtual_timers">here</a> for details). You probably won't need to modify
if you're writing platform specific code, but it's best to keep in mind what it does.</li>
-</ul></p>
+</ul>
<p>A platform implementation might also contain one or more <b>platform dependent modules</b>. As already exaplained, their purpose is to allow Lua
to use the full potential of the platform peripherals, not only the functionality covered by the platform interface, as well as functionality that
is so specific to the platform that it's not even covered by the platform interface. By convention, all the platform dependent modules should be
grouped inside a single module that has the same name as the platform itself. If the platform dependent module augments the functionality of a
- module already found in the platform interface, it should have the same name, otherwise it should be given a different, but meaningful name. For example:
+ module already found in the platform interface, it should have the same name, otherwise it should be given a different, but meaningful name. For example:</p>
<ul>
<li>if implementing new functionality on the UART module of the LM3S platform, the corresponding module should be called <b>lm3s.uart</b>.</li>
<li>if implementing a peripheral driver that for some reason should be specific to the platform on the LPC2888 platform, for example its dual audio
DAC, give it a meaningful name, for example <b>lpc288x.audiodac</b>.</li>
-</ul></p>
+</ul>
<h2>Structure of a port</h2>
<p>All the code for platform <i>name</i> (including peripheral drivers) must reside in a directory called <i>src/platform/<name></i> (for example
<i>src/platform/lm3s</i> for the <i>lm3s</i> platform). Each such platform-specific subdirectory must contain at least these files:</p>
<ul>
<li><b>type.h</b>: this defines the "specific data types", which are integer types with a specific size (see <a href="arch_coding.html">coding style</a>
for details. An example from the <b>i386</b> platform:
-<p><pre><code>typedef unsigned char u8;
+<pre><code>typedef unsigned char u8;
typedef signed char s8;
typedef unsigned short u16;
typedef signed short s16;
typedef unsigned long u32;
typedef signed long s32;
typedef unsigned long long u64;
-typedef signed long long s64;</code></pre></p>
+typedef signed long long s64;</code></pre>
</li>
<li><b>conf.py</b>: this is the platform specific build configuration file, used by the <a href="building.html">build system</a> for a number of purposes:
<ul>
<li>to get the list of platform-specific files that will be compiled in the <b>eLua</b> image. They are exported in the <i>specific_files</i> string,
separated by spaces, and must be prepended with the relative path to the platform subdirectory. An example from the <b>i386</b> platform:
-<p><pre><code>specific_files = "boot.s common.c descriptor_tables.c gdt.s interrupt.s isr.c kb.c monitor.c timer.c platform.c"
+<pre><code>specific_files = "boot.s common.c descriptor_tables.c gdt.s interrupt.s isr.c kb.c monitor.c timer.c platform.c"
# Prepend with path
-specific_files = " ".join( [ "src/platform/%s/%s" % ( platform, f ) for f in specific_files.split() ] )</code></pre></p>
+specific_files = " ".join( [ "src/platform/%s/%s" % ( platform, f ) for f in specific_files.split() ] )</code></pre>
</li>
<li>to get the full command lines of the different toolchain utilities (linker, assembler, compiler) used to compile <b>eLua</b>. They must be declared
inside the <i>tools</i> variable, in a separate dictinoary which key is the same as the platform name, and with specific names for each tool in turn:
<b>cccom</b> for the compiler, <b>linkcom</b> for the linker and <b>ascom</b> for the assembler.
For example, this is how the <i>tools</i> variable is defined for the <b>i386</b> platform:
- <p><pre><code># Toolset data
+ <pre><code># Toolset data
tools[ 'i386' ] = {}
tools[ 'i386' ][ 'cccom' ] = "%s %s %s -march=i386 -mfpmath=387 -m32 -ffunction-sections -fdata-sections -fno-builtin -fno-stack-protector %s -Wall -c $SOURCE -o $TARGET" % ( toolset[ 'compile' ], opt, local_include, cdefs )
tools[ 'i386' ][ 'linkcom' ] = "%s -nostartfiles -nostdlib -march=i386 -mfpmath=387 -m32 -T %s -Wl,--gc-sections -Wl,-e,start -Wl,--allow-multiple-definition -o $TARGET $SOURCES -lc -lgcc -lm %s" % ( toolset[ 'compile' ], ldscript, local_libs )
- tools[ 'i386' ][ 'ascom' ] = "%s -felf $SOURCE" % toolset[ 'asm' ]</code></pre></p>
+ tools[ 'i386' ][ 'ascom' ] = "%s -felf $SOURCE" % toolset[ 'asm' ]</code></pre>
Note how the definition of <b>tools</b> uses the definition of <b>toolset</b>, a dictionary with the names of the tools in the current toolchain. This
is also part of the <b>eLua</b> build system and is documented <a href="toolchains.html">here</a>.</li>
<li>to get the name of a <b>programmning function</b> which receives the name of the <b>eLua</b> executable file (the result of the build step) and
produces a file suitable for programming on the corresponding hardware platform. The name of this function should also be set in the <i>tools</i>
dictionary, as shown below (example taken from the <b>str7</b> platform):
- <p><pre><code># Programming function for STR7
+ <pre><code># Programming function for STR7
def progfunc_str7( target, source, env ):
outname = output + ".elf"
os.system( "%s %s" % ( toolset[ 'size' ], outname ) )
print "Generating binary image..."
os.system( "%s -O binary %s %s.bin" % ( toolset[ 'bin' ], outname, output ) )
- tools[ 'str7' ][ 'progfunc' ] = progfunc_str7</code></pre></p>
+ tools[ 'str7' ][ 'progfunc' ] = progfunc_str7</code></pre>
Note, once again, how this function uses the same <i>toolset</i> variable mentioned in the previous paragraph.
</li>
</ul>
</li>
<li><b>stacks.h</b>: by convention, the stack(s) size(s) used in the system are declared in this file. An example taken from the <b>at91sam7x</b> platform is given below:
-<p><pre><code>#define STACK_SIZE_USR 2048
+<pre><code>#define STACK_SIZE_USR 2048
#define STACK_SIZE_IRQ 64
-#define STACK_SIZE_TOTAL ( STACK_SIZE_USR + STACK_SIZE_IRQ )</code></pre></p></li>
+#define STACK_SIZE_TOTAL ( STACK_SIZE_USR + STACK_SIZE_IRQ )</code></pre></li>
<li><b>platform.c</b>: by convention, the <a href="arch_platform.html">platform interface</a> is implemented in this file. It also contains the platform-specific
- initialization function (<i>platform_init</i>, see the description of the <a href="elua_arch.html#boot">eLua boot process</a> for details).</li>
+ initialization function (<i>platform_init</i>, see the description of the <a href="arch_overview.html#boot">eLua boot process</a> for details).</li>
<li><b>platform_conf.h</b>: this is the platform configuration file, used to give information about both the platform itself and the build configuration for the
platform. This is what you can set inside <b>platform_conf.h</b>:
<ul>
@@ -159,7 +148,7 @@
<li>the <b>static configuration data</b> (see <a href="building.html">building eLua</a> for details).</li>
<li>the <b>number of peripherals</b> on your CPU. See an example below (taken from <b>lm3s</b>) that also shows how to differentiate between different CPUs that belong to the same
platform; the <b>FORxxxx</b> macros are defined in <b>conf.py</b>):
-<p><pre><code></code>// Number of resources (0 if not available/not implemented)
+<pre><code>// Number of resources (0 if not available/not implemented)
#define NUM_PIO 7
#define NUM_SPI 1
#ifdef FORLM3S6965
@@ -173,18 +162,18 @@
#else
#define NUM_PWM 0
#endif
-#define NUM_ADC 4</pre></p></li>
+#define NUM_ADC 4</code></pre></li>
<li><b>specific peripheral configuration</b>: this includes (but it not limited to) enabling buffering on UART, enabling and setting up virtual timers, setting PIO configuration and so on.
- All these parameters are described in detail in the <a href="arch_platform.html">platform interface section</a>.
+ All these parameters are described in detail in the <a href="arch_platform.html">platform interface section</a>.</li>
<li><b>memory configuration</b>: describes the regions of free RAM in the system, which will be later used by the standard system allocator (malloc/realloc/free). Two macros
(<b>MEM_START_ADDRESS</b> and <b>MEM_END_ADDRESS</b>) define two arrays with the beginning and the end of all the free RAM memory in the system. If your board has external RAM memory, you
should define it here. If not, you can only use the internal memory, and you'll generally need to use the linker-defined symbol <b>end</b> to find out where your free memory starts. Following
is an example from the <b>ATEVK1100</b> (AVR32) board that has both on-chip and external RAM:
-<p><pre><code>// Allocator data: define your free memory zones here in two arrays
+<pre><code>// Allocator data: define your free memory zones here in two arrays
// (start address and end address)
#define MEM_START_ADDRESS { ( void* )end, ( void* )SDRAM }
#define MEM_END_ADDRESS { ( void* )( 0x10000 - STACK_SIZE_TOTAL - 1 ), ( void* )( SDRAM + SDRAM_SIZE - 1 ) }
-</code></pre></p>
+</code></pre>
</li>
</ul>
If you want to take a look at a real life example of a <b>platform_conf.h</b> file, see for example <i>src/platform/lm3s/platform_conf.h</i>.
@@ -192,27 +181,28 @@
<li><b>networking configuration</b>: if you need TCP/IP on your board, you need to add networking support to <b>eLua</b> (see <a href="building.html">
building</a> for a list of configuration options related to TCP/IP). You also need to have another file, called <b>uip-conf.h</b> that configures uIP
(the TCP/IP stack in <b>eLua</b>) for your specific architecture. See <a href="arch_tcpip.html">TCP/IP in eLua</a> for details.</li>
-</ul></p>
-<p>Besides the required files, the most common scenario is to include other platform specific files in your port:
+</ul>
+<p>Besides the required files, the most common scenario is to include other platform specific files in your port:</p>
<ul>
<li><b>a "startup sequence"</b>, generally written in assembler, that does very low level
intialization, sets the stack pointer, zeroes the BSS section, copies ROM to
RAM for the DATA section, and then jumps to main.</li>
- <li>a <b>linker command file</b>.
+ <li>a <b>linker command file</b>.</li>
<li>the <b>CPU support package</b> generally comes from the CPU manufacturer, and includes code
for accessing peripherals, configuring the core, setting up interrupts and so on.</li>
-</ul></p>
-<a name="boot"><h3>eLua boot process</h3></a>
-<p>This is what happens when you power up your <b>eLua</b> board:
+</ul>
+<a name="boot" /><h3>eLua boot process</h3>
+<p>This is what happens when you power up your <b>eLua</b> board:</p>
<ol>
<li>the platform initialization code is executed. This is the code that does very low level platform setup (if needed), copies ROM to RAM, zeroes out
the BSS section, sets up the stack pointer and jumps to <b>main</b>.</li>
<li>the first thing <b>main</b> does is call the platform specific initialization function (<b>platform_init</b>). <b>platform_init</b> must fully
- initialize the platform and return a result to main, that can be either <b>PLATFORM_OK</b> if the initialization succeded or <b>PLATFORM_ERR</b>
+ initialize the platform and return a result to main, that can be either <b>PLATFORM_OK</b> if the initialization succeeded or <b>PLATFORM_ERR</b>
otherwise. If <b>PLATFORM_ERR</b> is returned, <b>main</b> blocks immediately in an infinite loop.</li>
<li><b>main</b> then initializes the rest of the system: the ROM file system, XMODEM, and term.</li>
<li>if <b>/rom/autorun.lua</b> (which is a file called <b>autorun.lua</b> in the <a href="arch_romfs.html">ROM file system</a>) is found, it is
executed. If it returns after execution, or if it isn't found, the boot process continues with the next step.</li>
<li>if the <a href="using.html#shell">shell</a> was compiled in the image, it is started, otherwise a standard Lua interpreter is started.</li>
</ol>
-</body></html>
+$$FOOTER$$
+
Modified: branches/eagle_mmc/doc/en/arch_platform.html
===================================================================
--- branches/eagle_mmc/doc/en/arch_platform.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/en/arch_platform.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,10 +1,4 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>eLua platform interface</title>
-
-<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);">
+$$HEADER$$
<h3>The platform interface</h3>
<p>The platform interface is the part of <b>eLua</b> that makes it easily portable between different hardware platforms by grouping the common elements
of all platforms supported by <b>eLua</b> in a common interface. For more details about the platform interface and the overall structure of
@@ -15,8 +9,9 @@
0, PORTB will have 1 and so on. Similarly, the second SPI interface (SPI1) of the MCU will probably have an id equal to 1. However, this is not a strict
rule. The implementation of the platform interface might choose to expose only some of the peripherals (components) of the MCU, thus this rule might be
broken. For example, if a board has 3 UARTs, but for some reason the second UART (UART1) is dedicated and can't be touched by <b>eLua</b>, then UART0 will have the id 0 and UART2 will
- have the id 1, so UART1 won't ever be accesible to the code. Such cases are documented in the <a href="">##specific usage notes</a> section.</p>
+ have the id 1, so UART1 won't ever be accesible to the code. </p>
<p>With some exceptions (most notably the low-level support functions), the different modules supported by the platform interface are
- mirrored more or less accurately in separate Lua modules that can be used directly from <b>eLua</b>. Check <a href="">the reference manual</a> for a
+ mirrored more or less accurately in separate Lua modules that can be used directly from <b>eLua</b>. Check the reference manual for a
complete description of these modules.</p>
-</body></html>
+$$FOOTER$$
+
Modified: branches/eagle_mmc/doc/en/arch_romfs.html
===================================================================
--- branches/eagle_mmc/doc/en/arch_romfs.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/en/arch_romfs.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,21 +1,18 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>The ROM file system</title>
-
-<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);">
+$$HEADER$$
<h3>The ROM file system</h3>
<p>The ROM file system (ROMFS) is a small, read-only file system built for <b>eLua</b>. It is integrated with the C
library, so you can use standard POSIX calls (fopen/fread/fwrite...) to access it. It is also accessible directly from Lua via the <b>io</b> module.
The files in the file system are part of the <b>eLua</b> binary image, thus they can't be modified after the image is
- built. For the seame reason, you can't add/delete files after the image is built. ROMFS doesn't support directories.</p>
+ built. For the same reason, you can't add/delete files after the image is built. ROMFS doesn't support
+ sub-directories.</p>
<p>ROMFS is integrated with <a href="building.html">the build system</a> for maximum flexibility on various platforms. As a result, you can select the ROMFS contents for each board on which
<b>eLua</b> runs. Moreover, you can specify what <b>applications</b> (instead of individual files) go to the file system, as a real application might need more than a single Lua program
to run (for example a HTTP page with all its dependencies).</p>
<h2>Using ROMFS</h2>
-<p>To use ROMFS, you have to copy the required files to the <i>romfs/</i> directory. Keep in mind that the maximum file name of a ROMFS file is 14 characters, including the dot between the file
- name and its extension. Make sure that the file names from <i>romfs/</i> follow this rule. Then edit the main build script (<b>SConstruct</b>) to add a new application/modify an existing one.
+<p>To use ROMFS, you have to copy the required files to the <i>romfs/</i> directory, before building eLua.
+ Keep in mind that the maximum file name of a ROMFS file is 14 characters, including the dot between the file
+ name and its extension. Make sure that the file names from <i>romfs/</i> follow this rule. Then edit the main build script (<b>SConstruct</b>) to add a new application
+ or to modify an existing one.
All the applications that can be included in ROMFS are defined in the <b>romfs</b> array in <b>SConstruct</b>. Each application in the <b>romfs</b> array lists its files, as shown below
(note that <b>ltthpd</b>, <b>tvbgone</b> and <b>pong</b> applications require more than one file in order to run):</p>
<p><pre><code>romfs = {
@@ -50,7 +47,7 @@
'EAGLE-100' : [ 'bisect', 'hangman', 'lhttpd', 'led', 'hello', 'info' ]
}
</code></pre></p>
-<p>What's left to do is <a href="building.html">biuld eLua</a>. As part of the build process, <b>mkfs.py</b> will be called, which will read the contents of the <i>romfs/</i> directory and
+<p>What's left to do is <a href="building.html">build eLua</a>. As part of the build process, <b>mkfs.py</b> will be called, which will read the contents of the <i>romfs/</i> directory and
output a C header file that contains a binary description of the file system. To use ROMFS from C code, whevener you want to access a file, prefix its name with <b>/rom/</b>. For example,
if you want to open the <b>a.txt</b> file in ROMFS, you should call fopen like this:</p>
<p><pre><code>f = fopen( "/rom/a.txt", "rb" )</code></pre></p>
@@ -58,5 +55,5 @@
<p><pre><code>eLua# lua /rom/bisect.lua</code></pre></p>
<p>Or directly from Lua:</p>
<p><pre><code>> dofile "/rom/bisect.lua"</code></pre></p>
-</body></html>
+$$FOOTER$$
Modified: branches/eagle_mmc/doc/en/arch_tcpip.html
===================================================================
--- branches/eagle_mmc/doc/en/arch_tcpip.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/en/arch_tcpip.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,25 +1,21 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>TCP/IP in eLua</title>
-
-<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);">
-<h3>TCP/IP in eLua <font color="red">(WIP)</font></h3>
+$$HEADER$$
+<head><meta http-equiv="Content-Type" content="text/html;charset=utf-8"/>
+<h3>TCP/IP in eLua <span class="warning">(WIP)</span></h3>
<p><b>eLua</b>'s TCP/IP support was designed with flexibility and ease of use in mind. It
might not provide all the functions of a "full-fledged" TCP/IP stack, but it's
-still fully functional and probably easier to use than a "regular" (POSIX) TCP/IP
-stack. These are the services provided by the TCP/IP stack:
+still fully functional, has a much smaller footprint and is probably easier to use than a "regular" (POSIX) TCP/IP
+stack. These are the services provided by the TCP/IP stack:</p>
<ul>
<li>a set of functions for network access (defined in inc/elua_net.h)</li>
<li>a DHCP client</li>
<li>a DNS resolver</li>
- <li>a module (<a href="m_net.html">net</a>) which can be used from Lua to access the network functions</li>
+ <li>a module (<a href="refman_gen_net.html">net</a>) which can be used from Lua to access the network functions</li>
<li>a Telnet miniclient, which is used to support the eLua shell via TCP/IP instead of serial connections.</li>
</ul>
-</p>
+<br />
+
<h2>TCP/IP configuration</h2>
-<p>To configure the TCP/IP subsystem, <i>edit src/platform/<name>platform_conf.h</i> and:
+<p>To configure the TCP/IP subsystem, <i>edit src/platform/<name>platform_conf.h</i> and:</p>
<ol>
<li><b>#define BUILD_UIP</b> to enable TCP/IP support</li>
<li>if you'll be using the DHCP client, just <b>#define BUILD_DHCPC</b> to build the
@@ -30,19 +26,19 @@
<b>#define ELUA_CONF_DEFGW0 ... ELUA_CONF_DEFGW3</b> : the default gateway<br>
<b>#define ELUA_CONF_DNS0 ... ELUA_CONF_DNS3</b> : the DNS server </p>
- Note that you must define both <b>BUILD_DHCPC</b> and the <b>ELUA_CONF_*</b> macros. If the
+ <p>Note that you must define both <b>BUILD_DHCPC</b> and the <b>ELUA_CONF_*</b> macros. If the
DHCP client fails to obtain a valid IP address, the static configuration will
be used instead. To use only the static configuration (and make the eLua image
- size a bit smaller) don't define the BUILD_DHCPC client.</li>
+ size a bit smaller) don't define the BUILD_DHCPC client.</p></li>
<li><b>#define BUILD_DNSM</b> if you want support for the DNS server.</li>
<li><b>#define BUILD_CON_TCP</b> if you want support for shell over telnet instead of
serial. Note that you must NOT define <b>BUILD_CON_GENERIC</b> in this case (see
<a href="arch_con_term.html">here</a> for details).</li>
-</ol></p>
+</ol>
<p>You'll also need an uIP configuration file (<i>src/platform/<name>/uip-conf.h</i>) to configure the TCP/IP
stack. For an example, look at <i>src/platform/<lm3s>/uip-conf.h</i>. The header if quite self-explanatory, below
-you have a list of parameters that you might want to change:
+you have a list of parameters that you might want to change:</p>
<ul>
<li><b>u8_t, u16_t</b>: define these types to match your platform.</li>
<li><b>UIP_CONF_MAX_CONNECTIONS</b>: the maximum number of TCP connections that can be active at a given time.</li>
@@ -54,7 +50,9 @@
be used (for example by DNS/DHCP), so be careful if you disable this.</li>
<li><b>ELUA_DHCP_TIMER_ID</b>: the timer ID used for the TCP/IP subsystem. Note that this should be a dedicated timer, not available to the rest
of the system (or available in "read-only" mode).</li>
-</ul></p>
+</ul>
+<br />
+
<h2>TCP/IP implementation internals</h2>
<p>The TCP/IP support was designed in such a way that it doesn't require a specific
TCP/IP stack implementation. To work with <b>eLua</b>, a TCP/IP stack must simply
@@ -66,7 +64,8 @@
everything in a platform-independent manner, except for some functions (as few as
possible and as simple as possible) that must be implemented by each platform.
To illustrate the above, a short overview of the uIP integration is given below.</p>
-<p><a target="_blank" href="http://www.sics.se/~adam/uip/index.php/Main_Page">uIP</a> is a minimalistic TCP/IP
+
+<p><a href="http://www.sics.se/~adam/uip/index.php/Main_Page">uIP</a> is a minimalistic TCP/IP
stack designed specifically for resource constrained embedded systems. While the
design and implementation of uIP are an excellent example of what can be done
with a few kilobytes of memory, it has a number of quirks that make it hard to
@@ -75,15 +74,17 @@
library that can be used to write uIP applications in a more "traditional" way,
but it's quite restrictive. So, to use it with <b>eLua</b>, a translation layer was
needed. It is implemented in <i>src/elua_uip.c</i>, and its sole purpose is to "adapt"
-the uIP stack to the <B>eLua model</b>: implement the functions in <i>inc/elua_net.h</i> and
+the uIP stack to the <b>eLua</b> model: implement the functions in <i>inc/elua_net.h</i> and
you're ready to use the stack. In this case the "adaption layer" is quite large
-because of uIP's callback-based design.<br>
-To make the uIP implementation as platform-independent as possible, a special
-<a href="">##networking layer</a> is added to the <a href="arch.platform.html">platform interface</a>.
+because of uIP's callback-based design.</p>
+
+<p>To make the uIP implementation as platform-independent as possible, a special
+<a href="arch_platform_eth.html">networking layer</a> is added to the <a href="arch_platform.html">platform interface</a>.
There are only 4 functions that must be implemented by a backend
to use the networking layer. They might change as more TCP/IP stacks are added
to eLua, but probably the networking layer won't get much bigger than it is now.<br>
For a more in-depth understanding of how the networking layer is implemented,
look at the LM3S implementation in <i>src/platform/lm3s/platform.c</i>.
</p>
-</body></html>
+$$FOOTER$$
+
Modified: branches/eagle_mmc/doc/en/building.html
===================================================================
--- branches/eagle_mmc/doc/en/building.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/en/building.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,11 +1,4 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Building eLua</title>
-
-<link rel="stylesheet" type="text/css" href="../style.css">
-</head>
-<body style="background-color: rgb(255, 255, 255);">
+$$HEADER$$
<h3>Building eLua</h3>
<p>If you decide to build your own <b>eLua</b>
binary image (instead of <a href="downloads.html">downloading
@@ -63,8 +56,8 @@
enabled to add functionality to <b>eLua</b> itself,
without modifying its API (which is the part that the programmer uses
to write <b>eLua</b> programs). An example of component configuration from
-<i>platform_conf.h</i> is given below:
-<p><pre><code>// *****************************************************************************
+<i>platform_conf.h</i> is given below:</p>
+<pre><code>// *****************************************************************************
// Define here what components you want for this platform
#define BUILD_XMODEM
@@ -75,9 +68,8 @@
#define BUILD_DHCPC
#define BUILD_DNS
#define BUILD_CON_GENERIC
-#define BUILD_ADC</code></pre></p>
-<p>The components that can be configured in <b>eLua</b> are:
-</p>
+#define BUILD_ADC</code></pre>
+<p>The components that can be configured in <b>eLua</b> are:</p>
<table class="table_center">
<tbody>
<tr>
@@ -92,7 +84,7 @@
target. Works only over RS-232 connections (although in theory it's
possible to make it work over any kind of transport).
To enable:
-<p><pre><code>#define BUILD_XMODEM</code></pre></p>
+<pre><code>#define BUILD_XMODEM</code></pre>
<a href="building.html#static">Static configuration data dependencies:</a> <b>CON_UART_ID, CON_UART_SPEED, CON_TIMER_ID</b>
</td>
</tr>
@@ -103,11 +95,11 @@
and executes it. If this file is not found, a regular Lua intepreter is
started on the target.<br>
To enable the shell over a serial connection:
-<p><pre><code>#define BUILD_SHELL
-#define BUILD_CON_GENERIC</code></pre></p>
+<pre><code>#define BUILD_SHELL
+#define BUILD_CON_GENERIC</code></pre>
To enable the shell over a TCP/IP connection:
-<p><pre><code>#define BUILD_SHELL
-#define BUILD_CON_TCP</code></pre></p>
+<pre><code>#define BUILD_SHELL
+#define BUILD_CON_TCP</code></pre>
</td>
</tr>
<tr>
@@ -116,27 +108,27 @@
filesystem. See the <a href="arch_romfs.html">ROMFS
documentation</a> for details about using the ROM file system.
To enable:
-<p><pre><code>#define BUILD_ROMFS</code></pre></p></td>
+<pre><code>#define BUILD_ROMFS</code></pre></td>
</tr>
<tr>
<td style="color: rgb(255, 102, 0);">BUILD_TERM</td>
<td>Enable ANSI terminal support. It allows <b>eLua</b>
to interact with terminals that support ANSI escape sequences (more details <a href="arch_con_term.html">here</a>).
Currently it works only over RS-232 connections, although this is not a
-strict requirement. You need to enable this if you want to use the <a href="m_term.html">##term module</a>.
+strict requirement. You need to enable this if you want to use the <a href="refman_gen_term.html">term module</a>.
To enable:
-<p><pre><code>#define BUILD_TERM</code></pre></p>
+<pre><code>#define BUILD_TERM</code></pre>
<a href="building.html#static">Static configuration data dependencies:</a> <b>CON_UART_ID, CON_UART_SPEED, CON_TIMER_ID, TERM_LINES, TERM_COLS</b></td>
</tr>
<tr>
<td style="color: rgb(255, 102, 0);">BUILD_UIP</td>
<td>Enable TCP/IP networking support. You need to enable
-this if you want to use the <a href="m_net.html">##net
+this if you want to use the <a href="refman_gen_net.html">net
module</a>. Also, your platform must implement the uIP support
-functions (see the <a href="platform_interface.html">##platform
+functions (see the <a href="arch_platform.html">platform
interface</a> documentation for details).
To enable:
-<p><pre><code>#define BUILD_UIP</code></pre></p>
+<pre><code>#define BUILD_UIP</code></pre>
<a href="building.html#static">Static configuration data dependencies:</a> <b>ELUA_CONF_IPADDR0..3, ELUA_CONF_NETMASK0..3, ELUA_CONF_DEFGW0..3,
ELUA_CONF_DNS0..3</b>
</td>
@@ -146,8 +138,8 @@
<td>If BUILD_UIP is enabled, you can enable this to include
a DHCP client in the TCP/IP networking subsystem.
To enable:
-<p><pre><code>#define BUILD_UIP
-#define BUILD_DHCPC</code></pre></p>
+<pre><code>#define BUILD_UIP
+#define BUILD_DHCPC</code></pre>
</td>
</tr>
<tr>
@@ -155,8 +147,8 @@
<td>If BUILD_UIP is enabled, you can enable this to include
a minimal DNS resolver in the TCP/IP networking subsystem.
To enable:
-<p><pre><code>#define BUILD_UIP
-#define BUILD_DNS</code></pre></p>
+<pre><code>#define BUILD_UIP
+#define BUILD_DNS</code></pre>
</td>
</tr>
<tr>
@@ -167,7 +159,7 @@
input/output over your RS-232 connection. Don't enable this if you need
console input/ouput over Ethernet (see the next option).
To enable:
-<p><pre><code>#define BUILD_CON_GENERIC</code></pre></p>
+<pre><code>#define BUILD_CON_GENERIC</code></pre>
<a href="building.html#static">Static configuration data dependencies:</a> <b>CON_UART_ID, CON_UART_SPEED, CON_TIMER_ID</b></td>
</tr>
<tr>
@@ -177,18 +169,16 @@
telnet session. Don't enable this if you need console input/output over
serial transports (see the previous option).
To enable:
-<p><pre><code>#define BUILD_UIP
-#define BUILD_CON_TCP</code></pre></p>
+<pre><code>#define BUILD_UIP
+#define BUILD_CON_TCP</code></pre>
</td>
</tr>
<tr>
<td style="color: rgb(255, 102, 0);">BUILD_ADC</td>
-<td>Generic ADC support code. You need to enable this if
-you want to use the <a href="m_adc.html">##adc</a>
-module, or simply the ADC functions from the platform interface. You
-don't need it if you're not planning to use the ADC.
+<td>Define this to build support for ADC peripherals. This must be enabled to use the <a href="refman_gen_adc.html">adc module</a>, or the <a href="arch_platform_adc.html">adc platform interface</a>.
To enable:
-<p><pre><code>#define ##BUILD_ADC</code></pre></p>
+<pre><code>#define BUILD_ADC</code></pre>
+<a href="building.html#static">Static configuration data dependencies:</a> <b>ADC_BIT_RESOLUTION, ADC_TIMER_FIRST_ID, ADC_NUM_TIMERS, BUF_ENABLE_ADC, ADC_BUF_SIZE</b>
</td>
</tr>
</tbody>
@@ -230,10 +220,10 @@
it is the most common one). Check the <a href="arch_ltr.html#config">LTR
section</a> for more information about LTR.</p>
<p>For the full list of modules that can be enabled or disabled
-via <i>platform_conf.h</i> check <a href="">##the
+via <i>platform_conf.h</i> check <a href="refman_gen.html">the
eLua reference manual</a>.</p>
<a name="static"><h2>Static configuration data</h2></a>
-<p>"Static configuration" reffers to the compile-time
+<p>"Static configuration" refers to the compile-time
configuration. Static configuration parameters are hard-coded in the
firmware image and can't be changed at run-time. The table below lists
the static configuration parameters and their semantics.
@@ -273,13 +263,13 @@
<td style="color: rgb(255, 102, 0);">VTMR_NUM_TIMERS<br>
VTMR_FREQ_HZ</td>
<td>Specify the virtual timers configuration for the
-platform (reffer to <a href="">##the timer module
+platform (refer to <a href="refman_gen_tmr.html">the timer module
documentation</a> for details). Define VTMR_NUM_TIMERS to 0 if
this feature is not used.</td>
</tr>
<tr>
<td style="color: rgb(255, 102, 0);">PLATFORM_CPU_CONSTANTS</td>
-<td>If the <a href="">##cpu module</a>
+<td>If the <a href="refman_gen_cpu.html">cpu module</a>
is enabled, this defines a list of platform-specific constants (for
example interrupt masks) that can be accessed using the
cpu.<constant name> notation. Each constant name must be
@@ -288,14 +278,45 @@
<pre><code>#define PLATFORM_CPU_CONSTANTS\<br> _C( INT_GPIOA ),\<br> _C( INT_GPIOB ),\<br> _C( INT_GPIOC ),\<br> _C( INT_GPIOD ),\<br> _C( INT_GPIOE )<br></code></pre>
After compilation, you can access these constants using <i>cpu.INT_GPIOx</i>.
Note that the implementation of this feature needs virtually no RAM at
-all, so you can define as many constants as you want here. ##TODO: ADC!!</td>
+all, so you can define as many constants as you want here. </td>
</tr>
+
+<tr>
+<<<<<<< .mine
+<td style="color: rgb(255, 102, 0);">BUF_ENABLE_ADC</td>
+<td>If the <a href="arch_platform_adc.html">adc module</a> is enabled, this controls whether or not the ADC will create a buffer so that more than one sample per channel can be held in a buffer before being returned through adc.getsample or adc.getsamples. If disabled, only one conversion result will be buffered. This option does NOT affect the behavior of the moving average filter.</td>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">ADC_BUF_SIZE</td>
+<td>If the <a href="arch_platform_adc.html">adc module</a> is enabled, and BUF_ENABLE_ADC is defined, this will define the default buffer length allocated at startup. This does not limit buffer sizes, it only defines the default length. Appropriate values range from BUF_SIZE_2 to BUF_SIZE_32768, with the numeric component at the end being in powers of 2.</td>
+ </tr>
+
+<tr>
+<td style="color: rgb(255, 102, 0);">ADC_BIT_RESOLUTION<br>ADC_TIMER_FIRST_ID<br>ADC_NUM_TIMERS
+=======
+<td style="color: rgb(255, 102, 0);">BUF_ENABLE_ADC</td>
+<td>If the <a href="refman_gen_adc.html">adc module</a> is enabled, this controls whether or not the ADC will create a buffer so that more than one sample per channel can be held in a buffer before being returned through adc.getsample or adc.getsamples. If disabled, only one conversion result will be buffered. This option does NOT affect the behavior of the moving average filter.</td>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">ADC_BUF_SIZE</td>
+<td>If the <a href="refman_gen_adc.html">adc module</a> is enabled, and BUF_ENABLE_ADC is defined, this will define the default buffer length allocated at startup. This does not limit buffer sizes, it only defines the default length. Appropriate values range from BUF_SIZE_2 to BUF_SIZE_32768, with the numeric component at the end being in powers of 2.</td>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">ADC_BIT_RESOLUTION
+>>>>>>> .r476
+</td>
+<<<<<<< .mine
+<td>The ADC resolution in bits, the ID of the first timer and the total number of timers used by the ADC subsystem.</td>
+=======
+<td>If the <a href="refman_gen_adc.html">adc module</a> is enabled, this will define the number of bits per adc conversion result. This is used to determine the maximum conversion value that can be returned by the ADC.</td>
+>>>>>>> .r476
+</tr>
</tbody>
</table>
<p>The rest of the static configuration data parameters are meant
to be modified mainly by developers and thus they're not listed here.<br>
One more thing you might want to configure for your build is the
-contents of the ROM file system. See the <a href="">ROMFS
+contents of the ROM file system. See the <a href="arch_romfs.html">ROMFS
documentation</a> for details on how to do this.</p>
<h3>Invoking the build system</h3>
<p>Once you have everything in place, all you have to do is to
@@ -394,6 +415,6 @@
<p>Build the image for the Cortex LM3S8962 CPU, but use the
CodeSourcery toolchain instead of the default toolchain (which is a
"generic" ARM GCC toolchain, usually the one built by following
-the tutorials from this site</p>
-.
-</body></html>
+the tutorials from this site.</p>
+$$FOOTER$$
+
Modified: branches/eagle_mmc/doc/en/comunity.html
===================================================================
--- branches/eagle_mmc/doc/en/comunity.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/en/comunity.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,49 +1,45 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
-
-<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);">
-<a name="lists"></a><h3>Mail lists</h3>
-<p style="text-align: left;"><strong>eLua</strong> currently has a single<strong> Developers and Users Discussion List</strong>. You are very welcomed
-to join it at <a target="_top" href="https://lists.berlios.de/mailman/listinfo/elua-dev">https://lists.berlios.de/mailman/listinfo/elua-dev</a>.
+$$HEADER$$
+<a name="lists" /><h3>Mail lists</h3>
+<p style="text-align: left;"><strong>eLua</strong> currently has a single <strong>developers and users discussion list</strong>. You are very welcomed
+to join us at <a href="https://lists.berlios.de/mailman/listinfo/elua-dev">https://lists.berlios.de/mailman/listinfo/elua-dev</a>.
Please note that the list is moderated in order to avoid spam, so you
need to join it if you want to post. Messages from non-members are
rarely accepted.</p>
-<p style="text-align: left;"></p><p style="text-align: left;">Our development repository is currently maintained in a
-Subversion server. If you want to track SVN activity, you can also subscribe to our <strong>SVN
-Activity List</strong> at <a target="_top" href="https://lists.berlios.de/mailman/listinfo/elua-svn">https://lists.berlios.de/mailman/listinfo/elua-svn</a><a href="https://lists.berlios.de/mailman/listinfo/elua-svn"></a></p>
-<a name="forums"></a><h3>eLua forums</h3>
-<b>eLua</b> doesn't have a dedicated forum at this point. However, starting with 22.02.2009, the <b>Developers and Users Discussion List</b> is "mirrored" in a forum-like format at <a href="http://n2.nabble.com/eLua-Development-f2368040.html">this address</a> (using the services provided by <a href="http://www.nable.com">Nabble</a>). If you want to use the forum interface, but don't want to navigate away from this page, click <a href="forum.html">here</a>.
-<span style="font-style: italic;"><a name="credits"></a><br></span><h3>Credits</h3>
-<div class="content">
+<p>Our development repository is currently maintained in a
+subversion server. If you want to track SVN activity, you can also subscribe to our <strong>SVN
+Activity List</strong> at <a href="https://lists.berlios.de/mailman/listinfo/elua-svn">https://lists.berlios.de/mailman/listinfo/elua-svn</a></p>
+<a name="forums" /><h3>eLua forums</h3>
+<p><b>eLua</b> doesn't have a dedicated forum at this point. However, our Developers
+ and Users Discussion List is "mirrored" in a forum-like format at
+ <a href="http://n2.nabble.com/eLua-Development-f2368040.html">this address</a>
+ (using the services provided by <a href="http://www.nable.com">Nabble</a>).
+</p>
+<a name="credits" /><h3>Credits</h3>
<p>The authors of <strong>eLua</strong> would like
-to thank the colaborative help from the comunity for the
-continuous development of the project. Here's an alphabetical
-ordered non-exhaustive list of contributors:</p><ul>
-<li>Alberto Fabiano</li>
-<li>André Carregal</li><li>Cosmin Filip</li>
-<li>Diego Sueiro</li>
-<li>Everson Denis</li>
-<li>Fabio Pereira</li>
-<li>Fernando Araújo</li>
-<li>Frédéric Thomas</li>
-<li>Ives Cunha</li>
-<li>James Snyder</li>
-<li>Marcelo Tílio</li>
-<li>Marco Meggiolaro</li>
-<li>Mike Panetta</li>
-<li>Pedro Bittencourt</li>
-<li>Rafael Barmak</li>
-<li>Rafael Sabbagh</li>
-<li>Ralph Hempel</li>
-<li>Raul Nunes</li>
-<li>Ricardo Rosa</li>
-<li>Roberto Ierusalimschy</li>
-<li>Téo Benjamin</li>
-<li>Yuri Takhteyev</li></ul>
-... and the whole comunity of our Users & Development List at <a href="https://lists.berlios.de/mailman/listinfo/elua-dev">https://lists.berlios.de/mailman/listinfo/elua-dev</a><strong style="font-weight: normal;"></strong></div>
-<br><br>
-<a name="galery"></a><a name="projects"></a>
-</body></html>
+to thank the colaborative help from the community for the
+continuous development of the project. Here's an alphabetically
+ordered non-exhaustive list of contributors:</p>
+<ul>
+ <li>Everson Denis and Flávio Nogueira - Portuguese translation for the site & doc</li>
+ <li>Fréderic Thomas - Site hosting, LM3S enhancements</li>
+ <li>James Snyder - ADC, CAN, LuaRPC (<a href="http://q12.org/lua/index.html">originaly by Russell Smith</a>), testing</li>
+ <li>Mike Panetta - STM32 port</li>
+ <li>Pedro Bittencourt - RIT OLED, <a href="http://code.google.com/p/vhews/">VHeHS</a>, testing...</li>
+ <li>Raul Nunes - The fundamental support from <a href="http://www.puc-rio.br">PUC-Rio</a>.</li>
+ <li>Roberto Ierusalimschy, Luiz Henrique Figueiredo, Waldemar Celles - for
+ <a href="http://www.lua.org">Lua</a> (!!! :)</li>
+ <li>Téo Benjamin, Ives Cunha, Rafael Barmak - Pong, TetrIves, SpaceShip
+ games and <a href="http://www.giga.puc-rio.br/site/embedded/manfredo">Manfredo</a>, a GPS guided robot, powered by eLua.</li>
+ <li>The whole community of users on our eLua list at <a
+ href="https://lists.berlios.de/mailman/listinfo/elua-dev">https://lists.berlios.de/mailman/listinfo/elua-dev</a></li>
+</ul>
+ ... and the constant help and support from:<br />
+
+Alberto Fabiano, André Carregal, Ângelo Santos, Asko Kauppi, Cosmin Filip,
+Dean Hall, Diego Sueiro, Fabio Pereira, Giovani Balduino, Jesus Alvarez, John Hind, Luiz de Barros, Marcelo TÃio, Marco Meggiolaro,
+Ricardo L. Rosa, Robert Jakabosky, Yuri Takhteyev ....
+...
+</a>
+
+$$FOOTER$$
+
Deleted: branches/eagle_mmc/doc/en/dl_binaries.html
===================================================================
--- branches/eagle_mmc/doc/en/dl_binaries.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/en/dl_binaries.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,140 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
-
-<link rel="stylesheet" type="text/css" href="../style.css">
-</head>
-<body style="background-color: rgb(255, 255, 255);">
-<br>
-<h3><span class="info"><a name="sources"></a>Downloading
-eLua pre-built binary images</span></h3>
-If you have an eLua capable hardware, you
-don't need to be a professional developer of the embedded
-world
-and to understand the details of the eLua building process, to be
-able to have eLua on your nice kits. <br>
-<br>
-eLua project offers pre-built
-binary images for all the supported platforms.<br>
-<br>
-All you have to do is to chose the
-corresponding image file from the table below, flash it into your
-board, connect a serial terminal (or Ethernet if you board supports)
-and enjoy eLua.<br>
-<br>
-eLua binaries, like the <a href="dl_sources.html">source-code
-distributions</a>,
-include some example programs in it's file system, so you can run and
-play (yes! we have games too! :) them, following the instructions in
-our <a href="using.html">Using eLua</a> page. The
-available example programs are described in our <a href="examples.html" target="_top">Examples page<br></a>
-<br>
-If you need a customized binary image for an already supported
-platform (ie: with an autorun program, with some code of yours in the
-File System, with your LAN IP settings, .....) and you don't know how
-to build eLua, feel free to <a href="overview.html#contacts">write
-us</a> explaining what you need. We may (find some time to :)
-build one for you and eventually make it available here too.
-<br>
-<br>
-To understand what's in a file name (for example
-elua_lualong_lm3s8962.bin) check our <a href="building.html">Building
-eLua</a> page, or at least the last part of it, where the meaning
-of the file names coming from the build system is explained.<br><br><br><span style="color: red; font-weight: bold;">## Let's not forget to include links for fresh v0.6 binaries to all platforms ..........<br>##
-Maybe move the table/contents below to an "old versions" section .....
-Ooops, I just saw I'd done it already. It's on dl_old.html</span><br><div><br>
-<table class="table_center">
-<tbody>
-<tr>
-<th>eLua Version</th>
-<th>Target MCU</th>
-<th>Lua Number</th>
-<th>Memory Usage(KB)</th>
-<th>Remarks</th>
-<th>Download File</th>
-</tr>
-<tr>
-<td>0.5</td>
-<td>Atmel ARM7</td>
-<td>Float</td>
-<td>ROM: ~189<br>
-RAM: 32~64</td>
-<td>Official eLua release</td>
-<td><a href="http://prdownload.berlios.de/elua/elua_lua_at91sam7x256.bin">elua_lua_at91sam7x256.bin</a></td>
-</tr>
-<tr>
-<td>0.5</td>
-<td>Atmel ARM7</td>
-<td>Float</td>
-<td>ROM: ~189<br>
-RAM: 32~64</td>
-<td>Official eLua release</td>
-<td><a href="http://prdownload.berlios.de/elua/elua_lua_at91sam7x512g.bin">elua_lua_at91sam7x512g.bin</a></td>
-</tr>
-<tr>
-<td>0.5</td>
-<td>Intel x86<br>
-(for fun :)</td>
-<td>Float</td>
-<td> </td>
-<td>Official eLua release</td>
-<td><a href="http://prdownload.berlios.de/elua/elua_lua_i386.elf">elua_lua_i386.elf</a></td>
-</tr>
-<tr>
-<td>0.5</td>
-<td>Luminary Micro ARM Cortex M3</td>
-<td>Float</td>
-<td>ROM: ~202<br>
-RAM: 32~64</td>
-<td>Official eLua release</td>
-<td><a href="http://prdownload.berlios.de/elua/elua_lua_lm3s6965.bin">elua_lua_lm3s6965.bin</a></td>
-</tr>
-<tr>
-<td>0.5</td>
-<td>Luminary Micro ARM Cortex M3</td>
-<td>Float</td>
-<td>ROM: ~202<br>
-RAM: 32~64</td>
-<td>Official eLua release</td>
-<td><a href="http://prdownload.berlios.de/elua/elua_lua_lm3s8962.bin">elua_lua_lm3s8962.bin</a></td>
-</tr>
-<tr>
-<td>0.5</td>
-<td>NXP ARM7</td>
-<td>Float</td>
-<td>ROM: ~229<br>
-RAM: 32~64</td>
-<td>Official eLua release</td>
-<td><a href="http://prdownload.berlios.de/elua/elua_lua_lpc2888.bin">elua_lua_lpc2888.bin</a></td>
-</tr>
-<tr>
-<td>0.5</td>
-<td>ST Microelectronics ARM7</td>
-<td>Float</td>
-<td>ROM: ~189<br>
-RAM: 32~64</td>
-<td>Official eLua release</td>
-<td><a href="http://prdownload.berlios.de/elua/elua_lua_str711fr2g.bin">elua_lua_str711fr2g.bin</a></td>
-</tr>
-<tr>
-<td>0.5</td>
-<td>ST Microelectronics ARM 9</td>
-<td>Float</td>
-<td>ROM: ~229<br>
-RAM: 32~64</td>
-<td>Official eLua release</td>
-<td><a href="http://prdownload.berlios.de/elua/elua_lua_str912fw44.bin">elua_lua_str912fw44.bin</a></td>
-</tr>
-</tbody>
-</table>
-<br>
-</div>
-<p>Notes:</p>
-<ul>
-<li>Lua Number refers to the built Lua interpreter number type,
-float or integer.</li>
-<li>RAM Memory Usage is based on included Lua examples
-execution.</li>
-</ul>
-</body></html>
\ No newline at end of file
Modified: branches/eagle_mmc/doc/en/dl_old.html
===================================================================
--- branches/eagle_mmc/doc/en/dl_old.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/en/dl_old.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,13 +1,7 @@
-<!DOCTYPE HTML PUBLIC "-//W4C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>eLua downloads (old versions)</title>
-
-<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);">
+$$HEADER$$
<h3>Downloading eLua Old Versions</h3>
<p>The tables below have links to the previous official versions of <b>eLua</b> (both source code and binaries).</p>
-<a name="v041"><h2>0.4.1</h2></a>
+<a name="v050" /><h2>0.5</h2>
<table class="table_center">
<tbody>
<tr>
@@ -18,14 +12,90 @@
<th>Image file</th>
</tr>
<tr>
+<td>0.5</td>
+<td>All (source code)</td>
+<td>All (source code)</td>
+<td>All (source code)</td>
+<td><a href="http://prdownload.berlios.de/elua/elua-0.5.tgz">elua-0.5.tgz</a></td>
+</tr>
+<tr>
+<td>0.5</td>
+<td><a href="http://www.atmel.com/dyn/products/Product_card.asp?part_id=3755">AT91SAM7X256</a></td>
+<td><a href="http://www.olimex.com/dev/sam7-ex256.html">SAM7-EX256</a></td>
+<td>double</td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.5_lua_at91sam7x256.bin">elua0.5_lua_at91sam7x256.bin</a></td>
+</tr>
+<tr>
+<td>0.5</td>
+<td><a href="http://www.atmel.com/dyn/products/Product_card.asp?part_id=4104">AT91SAM7X512</a></td>
+<td>None</td>
+<td>double</td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.5_lua_at91sam7x512.bin">elua0.5_lua_at91sam7x512.bin</a></td>
+</tr>
+<tr>
+<td>0.5</td>
+<td><a href="http://www.intel.com">i386 (generic)</a></td>
+<td>PCs/emulators</td>
+<td>double</td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.5_lua_i386.elf">elua0.5_lua_i386.elf</a></td>
+</tr>
+<tr>
+<td>0.5</td>
+<td><a href="http://www.luminarymicro.com/products/lm3s6965.html">LM3S6965</a></td>
+<td><a href="http://www.luminarymicro.com/products/lm3s6965_ethernet_evaluation_kit.html">EKx-LM3S6965</a></td>
+<td>double</td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.5_lua_lm3s6965.bin">elua0.5.lua_lm3s6965.bin</a></td>
+</tr>
+<tr>
+<td>0.5</td>
+<td><a href="http://www.luminarymicro.com/products/LM3S8962.html">LM3S8962</a></td>
+<td><a href="http://www.luminarymicro.com/products/lm3s8962_can_ethernet_evaluation_kit.html">EKx-LM3S8962</a></td>
+<td>double</td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.5_lua_lm3s8962.bin">elua0.5_lua_lm3s8962.bin</a></td>
+</tr>
+<tr>
+<td>0.5</td>
+<td><a href="http://www.standardics.nxp.com/microcontrollers/to/pip/LPC2880FET180.html">LPC2888</a></td>
+<td><a href="http://www.olimex.com/dev/lpc-h2888.html">LPC-H2888</a></td>
+<td>double</td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.5_lua_lpc2888.bin">elua0.5_lua_lpc2888.bin</a></td>
+</tr>
+<tr>
+<td>0.5</td>
+<td><a href="http://www.st.com/mcu/devicedocs-STR711FR2.html">STR711FR2</a></td>
+<td><a href="http://www.sctec.com.br/content/view/101/30/">MOD711</a></td>
+<td>double</td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.5_lua_str711fr2.bin">elua0.5_lua_str711fr2.bin</a></td>
+</tr>
+<tr>
+<td>0.5</td>
+<td><a href="http://www.st.com/mcu/devicedocs-STR912FAW44-101.html">STR912FAW44</a></td>
+<td><a href="http://www.hitex.com/index.php?id=383">STR9-comStick</a></td>
+<td>double</td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.5_lua_str912fw44.bin">elua0.5_lua_str912fw44.bin</a></td>
+</tr>
+</tbody></table>
+
+<a name="v041" /><h2>0.4.1</h2>
+<table class="table_center">
+<tbody>
+<tr>
+<th>Version</th>
+<th>MCU</th>
+<th>Board</th>
+<th>Lua number type</th>
+<th>Image file</th>
+</tr>
+<tr>
<td>0.4.1</td>
<td>All (source code)</td>
<td>All (source code)</td>
<td>All (source code)</td>
-<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua-0.4.1.tgz">elua-0.4.1.tgz</a></td>
+<td><a href="http://prdownload.berlios.de/elua/elua-0.4.1.tgz">elua-0.4.1.tgz</a></td>
</tr>
</tbody></table>
-<a name="v04"><h2>0.4</h2></a>
+
+<a name="v04" /><h2>0.4</h2>
<table class="table_center">
<tbody>
<tr>
@@ -40,112 +110,110 @@
<td>All (source code)</td>
<td>All (source code)</td>
<td>All (source code)</td>
-<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua_0.4.tgz">elua_0.4.tgz</a></td>
+<td><a href="http://prdownload.berlios.de/elua/elua_0.4.tgz">elua_0.4.tgz</a></td>
</tr>
<tr>
<td>0.4</td>
-<td><a target="_blank" href="http://www.atmel.com/dyn/products/Product_card.asp?part_id=3755">AT91SAM7X256</a></td>
-<td><a target="_blank" href="http://www.olimex.com/dev/sam7-ex256.html">SAM7-EX256</a></td>
+<td><a href="http://www.atmel.com/dyn/products/Product_card.asp?part_id=3755">AT91SAM7X256</a></td>
+<td><a href="http://www.olimex.com/dev/sam7-ex256.html">SAM7-EX256</a></td>
<td>double</td>
-<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.4_lua_at91sam7x256.bin">elua0.4_lua_at91sam7x256.bin</a></td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.4_lua_at91sam7x256.bin">elua0.4_lua_at91sam7x256.bin</a></td>
</tr>
<tr>
<td>0.4</td>
-<td><a target="_blank" href="http://www.atmel.com/dyn/products/Product_card.asp?part_id=4104">AT91SAM7X512</a></td>
+<td><a href="http://www.atmel.com/dyn/products/Product_card.asp?part_id=4104">AT91SAM7X512</a></td>
<td>None</td>
<td>double</td>
-<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.4_lua_at91sam7x512.bin">elua0.4_lua_at91sam7x512.bin</a></td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.4_lua_at91sam7x512.bin">elua0.4_lua_at91sam7x512.bin</a></td>
</tr>
<tr>
<td>0.4</td>
-<td><a target="_blank" href="http://www.intel.com">i386 (generic)</a><br>
+<td><a href="http://www.intel.com">i386 (generic)</a></td>
<td>PCs/emulators</td>
<td>double</td>
-<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.4_lua_i386.elf">elua0.4_lua_i386.elf</a></td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.4_lua_i386.elf">elua0.4_lua_i386.elf</a></td>
</tr>
<tr>
<td>0.4</td>
-<td><a target="_blank" href="http://www.luminarymicro.com/products/lm3s6965.html">LM3S6965</a></td>
-<td><a target="_blank" href="http://www.luminarymicro.com/products/lm3s6965_ethernet_evaluation_kit.html">EKx-LM3S6965</a></td>
+<td><a href="http://www.luminarymicro.com/products/lm3s6965.html">LM3S6965</a></td>
+<td><a href="http://www.luminarymicro.com/products/lm3s6965_ethernet_evaluation_kit.html">EKx-LM3S6965</a></td>
<td>double</td>
-<td><a target="_blank" href=http://prdownload.berlios.de/elua/elua0.4_lua_lm3s6965.bin">elua0.4_lua_lm3s6965.bin</a></td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.4_lua_lm3s6965.bin">elua0.4_lua_lm3s6965.bin</a></td>
</tr>
<tr>
<td>0.4</td>
-<td><a target="_blank" href="http://www.luminarymicro.com/products/LM3S8962.html">LM3S8962</a></td>
-<td><a target="_blank" href="http://www.luminarymicro.com/products/lm3s8962_can_ethernet_evaluation_kit.html">EKx-LM3S8962</a></td>
+<td><a href="http://www.luminarymicro.com/products/LM3S8962.html">LM3S8962</a></td>
+<td><a href="http://www.luminarymicro.com/products/lm3s8962_can_ethernet_evaluation_kit.html">EKx-LM3S8962</a></td>
<td>double</td>
-<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.4_lua_lm3s8962.bin">elua0.4_lua_lm3s8962.bin</a></td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.4_lua_lm3s8962.bin">elua0.4_lua_lm3s8962.bin</a></td>
</tr>
<tr>
<td>0.4</td>
-<td><a target="_blank" href="http://www.standardics.nxp.com/microcontrollers/to/pip/LPC2880FET180.html">LPC2888</a></td>
-<td><a target="_blank" href="http://www.olimex.com/dev/lpc-h2888.html">LPC-H2888</a></td>
+<td><a href="http://www.standardics.nxp.com/microcontrollers/to/pip/LPC2880FET180.html">LPC2888</a></td>
+<td><a href="http://www.olimex.com/dev/lpc-h2888.html">LPC-H2888</a></td>
<td>double</td>
-<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.4_lua_lpc2888.bin">elua0.4_lua_lpc2888.bin</a></td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.4_lua_lpc2888.bin">elua0.4_lua_lpc2888.bin</a></td>
</tr>
<tr>
<td>0.4</td>
-<td><a target="_blank" href="http://www.st.com/mcu/devicedocs-STR912FAW44-101.html">STR912FAW44</a></td>
-<td><a target="_blank" href="http://www.hitex.com/index.php?id=383">STR9-comStick</a></td>
+<td><a href="http://www.st.com/mcu/devicedocs-STR912FAW44-101.html">STR912FAW44</a></td>
+<td><a href="http://www.hitex.com/index.php?id=383">STR9-comStick</a></td>
<td>double</td>
-<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.4_lua_str912fw44.bin">elua0.4_lua_str912fw44.bin</a></td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.4_lua_str912fw44.bin">elua0.4_lua_str912fw44.bin</a></td>
</tr>
-
<tr>
<td>0.4</td>
-<td><a target="_blank" href="http://www.atmel.com/dyn/products/Product_card.asp?part_id=3755">AT91SAM7X256</a></td>
-<td><a target="_blank" href="http://www.olimex.com/dev/sam7-ex256.html">SAM7-EX256</a></td>
+<td><a href="http://www.atmel.com/dyn/products/Product_card.asp?part_id=3755">AT91SAM7X256</a></td>
+<td><a href="http://www.olimex.com/dev/sam7-ex256.html">SAM7-EX256</a></td>
<td>integer (32-bit)</td>
-<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.4_lualong_at91sam7x256.bin">elua0.4_lualong_at91sam7x256.bin</a></td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.4_lualong_at91sam7x256.bin">elua0.4_lualong_at91sam7x256.bin</a></td>
</tr>
<tr>
<td>0.4</td>
-<td><a target="_blank" href="http://www.atmel.com/dyn/products/Product_card.asp?part_id=4104">AT91SAM7X512</a></td>
+<td><a href="http://www.atmel.com/dyn/products/Product_card.asp?part_id=4104">AT91SAM7X512</a></td>
<td>None</td>
<td>integer (32-bit)</td>
-<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.4_lualong_at91sam7x512.bin">elua0.4_lualong_at91sam7x512.bin</a></td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.4_lualong_at91sam7x512.bin">elua0.4_lualong_at91sam7x512.bin</a></td>
</tr>
<tr>
<td>0.4</td>
-<td><a target="_blank" href="http://www.intel.com">i386 (generic)</a><br>
+<td><a href="http://www.intel.com">i386 (generic)</a></td>
<td>PCs/emulators</td>
<td>integer (32-bit)</td>
-<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.4_lualong_i386.elf">elua0.4_lualong_i386.elf</a></td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.4_lualong_i386.elf">elua0.4_lualong_i386.elf</a></td>
</tr>
<tr>
<td>0.4</td>
-<td><a target="_blank" href="http://www.luminarymicro.com/products/lm3s6965.html">LM3S6965</a></td>
-<td><a target="_blank" href="http://www.luminarymicro.com/products/lm3s6965_ethernet_evaluation_kit.html">EKx-LM3S6965</a></td>
+<td><a href="http://www.luminarymicro.com/products/lm3s6965.html">LM3S6965</a></td>
+<td><a href="http://www.luminarymicro.com/products/lm3s6965_ethernet_evaluation_kit.html">EKx-LM3S6965</a></td>
<td>integer (32-bit)</td>
-<td><a target="_blank" href=http://prdownload.berlios.de/elua/elua0.4_lualong_lm3s6965.bin">elua0.4_lualong_lm3s6965.bin</a></td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.4_lualong_lm3s6965.bin">elua0.4_lualong_lm3s6965.bin</a></td>
</tr>
<tr>
<td>0.4</td>
-<td><a target="_blank" href="http://www.luminarymicro.com/products/LM3S8962.html">LM3S8962</a></td>
-<td><a target="_blank" href="http://www.luminarymicro.com/products/lm3s8962_can_ethernet_evaluation_kit.html">EKx-LM3S8962</a></td>
+<td><a href="http://www.luminarymicro.com/products/LM3S8962.html">LM3S8962</a></td>
+<td><a href="http://www.luminarymicro.com/products/lm3s8962_can_ethernet_evaluation_kit.html">EKx-LM3S8962</a></td>
<td>integer (32-bit)</td>
-<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.4_lualong_lm3s8962.bin">elua0.4_lualong_lm3s8962.bin</a></td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.4_lualong_lm3s8962.bin">elua0.4_lualong_lm3s8962.bin</a></td>
</tr>
<tr>
<td>0.4</td>
-<td><a target="_blank" href="http://www.standardics.nxp.com/microcontrollers/to/pip/LPC2880FET180.html">LPC2888</a></td>
-<td><a target="_blank" href="http://www.olimex.com/dev/lpc-h2888.html">LPC-H2888</a></td>
+<td><a href="http://www.standardics.nxp.com/microcontrollers/to/pip/LPC2880FET180.html">LPC2888</a></td>
+<td><a href="http://www.olimex.com/dev/lpc-h2888.html">LPC-H2888</a></td>
<td>integer (32-bit)</td>
-<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.4_lualong_lpc2888.bin">elua0.4_lualong_lpc2888.bin</a></td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.4_lualong_lpc2888.bin">elua0.4_lualong_lpc2888.bin</a></td>
</tr>
<tr>
<td>0.4</td>
-<td><a target="_blank" href="http://www.st.com/mcu/devicedocs-STR912FAW44-101.html">STR912FAW44</a></td>
-<td><a target="_blank" href="http://www.hitex.com/index.php?id=383">STR9-comStick</a></td>
+<td><a href="http://www.st.com/mcu/devicedocs-STR912FAW44-101.html">STR912FAW44</a></td>
+<td><a href="http://www.hitex.com/index.php?id=383">STR9-comStick</a></td>
<td>integer (32-bit)</td>
-<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.4_lualong_str912fw44.bin">elua0.4_lualong_str912fw44.bin</a></td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.4_lualong_str912fw44.bin">elua0.4_lualong_str912fw44.bin</a></td>
</tr>
</tbody>
</table>
-
-<a name="v03"><h2>0.3</h2></a>
+<a name="v03" /><h2>0.3</h2>
<table class="table_center">
<tbody>
<tr>
@@ -159,56 +227,55 @@
<td>0.3</td>
<td>All (source code)</td>
<td>All (source code)</td>
-<td>All (source code)</td>
-<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua_0.3.tgz">elua_0.3.tgz</a></td>
+<td>All (source code) </td>
+<td><a href="http://prdownload.berlios.de/elua/elua_0.3.tgz">elua_0.3.tgz</a></td>
</tr>
<tr>
<td>0.3</td>
-<td><a target="_blank" href="http://www.atmel.com/dyn/products/Product_card.asp?part_id=3755">AT91SAM7X256</a></td>
-<td><a target="_blank" href="http://www.olimex.com/dev/sam7-ex256.html">SAM7-EX256</a></td>
+<td><a href="http://www.atmel.com/dyn/products/Product_card.asp?part_id=3755">AT91SAM7X256</a></td>
+<td><a href="http://www.olimex.com/dev/sam7-ex256.html">SAM7-EX256</a></td>
<td>double</td>
-<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.3_lua_at91sam7x256.bin">elua0.3_lua_at91sam7x256.bin</a></td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.3_lua_at91sam7x256.bin">elua0.3_lua_at91sam7x256.bin</a></td>
</tr>
<tr>
<td>0.3</td>
-<td><a target="_blank" href="http://www.atmel.com/dyn/products/Product_card.asp?part_id=4104">AT91SAM7X512</a></td>
+<td><a href="http://www.atmel.com/dyn/products/Product_card.asp?part_id=4104">AT91SAM7X512</a></td>
<td>None</td>
<td>double</td>
-<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.3_lua_at91sam7x512.bin">elua0.3_lua_at91sam7x512.bin</a></td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.3_lua_at91sam7x512.bin">elua0.3_lua_at91sam7x512.bin</a></td>
</tr>
<tr>
<td>0.3</td>
-<td><a target="_blank" href="http://www.intel.com">i386 (generic)</a><br>
+<td><a href="http://www.intel.com">i386 (generic)</a></td>
<td>PCs/emulators</td>
<td>double</td>
-<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.3_lua_i386.elf">elua0.3_lua_i386.elf</a></td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.3_lua_i386.elf">elua0.3_lua_i386.elf</a></td>
</tr>
<tr>
<td>0.3</td>
-<td><a target="_blank" href="http://www.luminarymicro.com/products/lm3s6965.html">LM3S6965</a></td>
-<td><a target="_blank" href="http://www.luminarymicro.com/products/lm3s6965_ethernet_evaluation_kit.html">EKx-LM3S6965</a></td>
+<td><a href="http://www.luminarymicro.com/products/lm3s6965.html">LM3S6965</a></td>
+<td><a href="http://www.luminarymicro.com/products/lm3s6965_ethernet_evaluation_kit.html">EKx-LM3S6965</a></td>
<td>double</td>
-<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.3_lua_lm3s6965.bin">elua0.3_lua_lm3s6965.bin</a></td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.3_lua_lm3s6965.bin">elua0.3_lua_lm3s6965.bin</a></td>
</tr>
<tr>
<td>0.3</td>
-<td><a target="_blank" href="http://www.luminarymicro.com/products/LM3S8962.html">LM3S8962</a></td>
-<td><a target="_blank" href="http://www.luminarymicro.com/products/lm3s8962_can_ethernet_evaluation_kit.html">EKx-LM3S8962</a></td>
+<td><a href="http://www.luminarymicro.com/products/LM3S8962.html">LM3S8962</a></td>
+<td><a href="http://www.luminarymicro.com/products/lm3s8962_can_ethernet_evaluation_kit.html">EKx-LM3S8962</a></td>
<td>double</td>
-<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.3_lua_lm3s8962.bin">elua0.3_lua_lm3s8962.bin</a></td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.3_lua_lm3s8962.bin">elua0.3_lua_lm3s8962.bin</a></td>
</tr>
<tr>
<td>0.3</td>
-<td><a target="_blank" href="http://www.st.com/mcu/devicedocs-STR912FAW44-101.html">STR912FAW44</a></td>
-<td><a target="_blank" href="http://www.hitex.com/index.php?id=383">STR9-comStick</a></td>
+<td><a href="http://www.st.com/mcu/devicedocs-STR912FAW44-101.html">STR912FAW44</a></td>
+<td><a href="http://www.hitex.com/index.php?id=383">STR9-comStick</a></td>
<td>double</td>
-<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.3_lua_str912fw44.bin">elua0.3_lua_str912fw44.bin</a></td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.3_lua_str912fw44.bin">elua0.3_lua_str912fw44.bin</a></td>
</tr>
</tbody>
</table>
-
-<a name="v02"><h2>0.2</h2></a>
+<a name="v02" /><h2>0.2</h2>
<table class="table_center">
<tbody>
<tr>
@@ -223,55 +290,55 @@
<td>All (source code)</td>
<td>All (source code)</td>
<td>All (source code)</td>
-<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua_0.2.tar.gz">elua_0.2.tar.gz</a></td>
+<td><a href="http://prdownload.berlios.de/elua/elua_0.2.tar.gz">elua_0.2.tar.gz</a></td>
</tr>
<tr>
<td>0.2</td>
-<td><a target="_blank" href="http://www.atmel.com/dyn/products/Product_card.asp?part_id=3755">AT91SAM7X256</a></td>
-<td><a target="_blank" href="http://www.olimex.com/dev/sam7-ex256.html">SAM7-EX256</a></td>
+<td><a href="http://www.atmel.com/dyn/products/Product_card.asp?part_id=3755">AT91SAM7X256</a></td>
+<td><a href="http://www.olimex.com/dev/sam7-ex256.html">SAM7-EX256</a></td>
<td>double</td>
-<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.2_lua_at91sam7x256.bin">elua0.2_lua_at91sam7x256.bin</a></td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.2_lua_at91sam7x256.bin">elua0.2_lua_at91sam7x256.bin</a></td>
</tr>
<tr>
<td>0.2</td>
-<td><a target="_blank" href="http://www.intel.com">i386 (generic)</a><br>
+<td><a href="http://www.intel.com">i386 (generic)</a></td>
<td>PCs/emulators</td>
<td>double</td>
-<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.2_lua_i386.elf">elua0.2_lua_i386.elf</a></td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.2_lua_i386.elf">elua0.2_lua_i386.elf</a></td>
</tr>
<tr>
<td>0.2</td>
-<td><a target="_blank" href="http://www.luminarymicro.com/products/LM3S8962.html">LM3S8962</a></td>
-<td><a target="_blank" href="http://www.luminarymicro.com/products/lm3s8962_can_ethernet_evaluation_kit.html">EKx-LM3S8962</a></td>
+<td><a href="http://www.luminarymicro.com/products/LM3S8962.html">LM3S8962</a></td>
+<td><a href="http://www.luminarymicro.com/products/lm3s8962_can_ethernet_evaluation_kit.html">EKx-LM3S8962</a></td>
<td>double</td>
-<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.2_lua_lm3s8962.bin">elua0.2_lua_lm3s8962.bin</a></td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.2_lua_lm3s8962.bin">elua0.2_lua_lm3s8962.bin</a></td>
</tr>
<tr>
<td>0.2</td>
-<td><a target="_blank" href="http://www.atmel.com/dyn/products/Product_card.asp?part_id=3755">AT91SAM7X256</a></td>
-<td><a target="_blank" href="http://www.olimex.com/dev/sam7-ex256.html">SAM7-EX256</a></td>
+<td><a href="http://www.atmel.com/dyn/products/Product_card.asp?part_id=3755">AT91SAM7X256</a></td>
+<td><a href="http://www.olimex.com/dev/sam7-ex256.html">SAM7-EX256</a></td>
<td>integer (32-bit)</td>
-<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.2_lualong_at91sam7x256.bin">elua0.2_lualong_at91sam7x256.bin</a></td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.2_lualong_at91sam7x256.bin">elua0.2_lualong_at91sam7x256.bin</a></td>
</tr>
<tr>
<td>0.2</td>
-<td><a target="_blank" href="http://www.intel.com">i386 (generic)</a><br>
+<td><a href="http://www.intel.com">i386 (generic)</a></td>
<td>PCs/emulators</td>
<td>integer (32-bit)</td>
-<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.2_lualong_i386.elf">elua0.2_lualong_i386.elf</a></td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.2_lualong_i386.elf">elua0.2_lualong_i386.elf</a></td>
</tr>
<tr>
<td>0.2</td>
-<td><a target="_blank" href="http://www.luminarymicro.com/products/LM3S8962.html">LM3S8962</a></td>
-<td><a target="_blank" href="http://www.luminarymicro.com/products/lm3s8962_can_ethernet_evaluation_kit.html">EKx-LM3S8962</a></td>
+<td><a href="http://www.luminarymicro.com/products/LM3S8962.html">LM3S8962</a></td>
+<td><a href="http://www.luminarymicro.com/products/lm3s8962_can_ethernet_evaluation_kit.html">EKx-LM3S8962</a></td>
<td>integer (32-bit)</td>
-<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.2_lualong_lm3s8962.bin">elua0.2_lualong_lm3s8962.bin</a></td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.2_lualong_lm3s8962.bin">elua0.2_lualong_lm3s8962.bin</a></td>
</tr>
</tbody>
</table>
-<a name="v01"><h2>0.1</h2></a>
+<a name="v01" /><h2>0.1</h2>
<table class="table_center">
<tbody>
<tr>
@@ -286,7 +353,8 @@
<td>All (source code)</td>
<td>All (source code)</td>
<td>All (source code)</td>
-<td><a target="_blank" href="http://luaforge.net/frs/download.php/3564/elua_0.1.tar.gz">elua_0.1.tar.gz</a></td>
+<td><a href="http://luaforge.net/frs/download.php/3564/elua_0.1.tar.gz">elua_0.1.tar.gz</a></td>
</tr>
-</body></html>
+</tbody></table>
+$$FOOTER$$
Deleted: branches/eagle_mmc/doc/en/dl_sources.html
===================================================================
--- branches/eagle_mmc/doc/en/dl_sources.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/en/dl_sources.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,52 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
-
-<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);"><br><h3><span class="info"><a name="sources"></a>Downloading eLua Source Code</span></h3><h2>Official Releases</h2>
-
-<h4>Source code</h4>
-
-<p>The last released version is eLua v0.6 and you can download it here:
-####<br>
-The package includes the complete source code, documentation, building scripts and Lua program examples.<br></p>
-
-
-<p>After downloading and unpacking, you can acess eLua's documentation
-in an offline mode, opening the document index_en.html in the /doc
-folder. It will show you a version of this site at the time eLua v0.6
-was released. The online version is constantly updated though and you
-might check it for <a href="news.html">updated eLua news</a>.</p><p>You will find eLua building instructions on the <a href="building.html">Building eLua</a> page.</p><br><br>
-
-
-<h2><a name="svnpublic"></a>Subversion Public Repository</h2>
-
-<p>If you'd rather have the very last development ("bleeding edge") version, just check it out from our Subversion Repository:</p>
-
-<pre>$ svn checkout svn://svn.berlios.de/elua/trunk<code><br></code></pre>
-
-
-<p>Once checked out, the repository can be easily updated by the svn client command:</p>
-
-<pre>$ svn update<code><br></code></pre>
-<p><br></p>
-
-<h2>Subversion Repository Web Browsing</h2>
-
-If you're looking for an easy and user friendly way of browsing through the SVN repository, use the <a href="http://svn.berlios.de/wsvn/elua">WebSVN interface</a><br><h2></h2><h2><a name="svndev"></a>Subversion Repository for developers</h2>
-
-<p>If you want to contribute to eLua and need write access to the repository, follow these steps:</p>
-
-<ul><li>if you don't have an account on <a href="http://developer.berlios.de/">developer.berlios.de,</a> create one before proceeding.</li><li><a href="../../../../../../websites/elua%20site/www.eluaproject.net/index8603.html?p=Contact">contact us</a>, specifying your BerliOS id and we'll add you to the list of developers.</li></ul>
-
-
-<p>Then checkout the repository:</p>
-
-<pre>$ export SVN_SSH='ssh -l <yourberliosid>'<br style="font-family: Courier New;"><br style="font-family: Courier New;">$ svn checkout svn+ssh://svn.berlios.de/svnroot/repos/elua/trunk<code><br></code></pre>
-
-<p>Once checked out, the repository can be easily updated:</p>
-
-<pre>$ svn update<code><br></code></pre>
-
-<p><br></p><br><br><br><p></p><p></p><p></p><p></p></body></html>
\ No newline at end of file
Modified: branches/eagle_mmc/doc/en/doc.html
===================================================================
--- branches/eagle_mmc/doc/en/doc.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/en/doc.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,22 +1,17 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>eLua documentation</title>
-
-<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);">
+$$HEADER$$
<h3>eLua documentation</h3>
-<p>This section contains the complete <b>eLua</b> documentation for both users and developers, including (but not limited to):
+<p>This section contains the complete <b>eLua</b> documentation for both users and developers, including (but not limited to):</p>
<ul>
<li>how to build <b>eLua</b></li>
<li>how to install (or build) the toolchains needed to build <b>eLua</b></li>
<li>how to use <b>eLua</b></li>
<li>description of the example programs from the <b>eLua</b> source distribution</li>
-</ul></p>
-<p>People who want to contribute to the <b>eLua</b> source code will find a lot of important information here:<ul>
+</ul>
+<p>People who want to contribute to the <b>eLua</b> source code will find a lot of important information here:</p>
+<ul>
<li>a description of the <b>eLua</b> architecture</li>
<li>the <b>eLua</b> coding standard</li>
<li>how to port <b>eLua</b> to a new platform</li>
</ul>
-</p>
-</body></html>
+$$FOOTER$$
+
Modified: branches/eagle_mmc/doc/en/downloads.html
===================================================================
--- branches/eagle_mmc/doc/en/downloads.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/en/downloads.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,30 +1,24 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>eLua downloads</title>
-
-<link rel="stylesheet" type="text/css" href="../style.css">
-</head>
-<body style="background-color: rgb(255, 255, 255);">
+$$HEADER$$
<h3>Downloading eLua</h3>
-<p>You have a few options for downloading <b>eLua</b>:
+<p>You have a few options for downloading <b>eLua</b>:</p>
<ul>
- <li>download a binary <b>eLua</b> image for your platform of choice. Binary images are provided with each official release. This is generally the best option if you have a bord that's officially
+ <li>download a binary <b>eLua</b> image for your platform of choice. Binary images are provided with each official release
+ and also for some specific applications (ie: games). This is generally the best option if you have a bord that's officially
supported by <b>eLua</b> (see <a href="status.html">here</a> for details) and you want to have <b>eLua</b> up and running on your board as quickly as possible.</li>
- <li>download the source code. You can either download the source code of an official release or get the "bleeding edge" version from the SVN repository. Download the source code instead of a
+ <li>download the source code to build <b>eLua</b> yourself. You can either download the source code of an official release or get the "bleeding edge" version from the SVN repository. Download the source code instead of a
binary image if you need to make adjustments to the source code to support your board, or if you want to customize the <b>eLua</b> image, or if you simply want to take a look at what
happens behind the <i>eLua# </i> prompt :)</li>
-</ul></p>
-<h3><a name="binaries">Binary images</a></h3>
+</ul>
+<a name="binaries" /><h3>Binary images</h3>
<p>Pre-built images of <b>eLua</b> can be downloaded for each official release. Only the latest official <b>eLua</b> release is covered in this paragraph; if you want to download a pre-built
image from an older release (although this isn't generally advisable), check <a href="dl_old.html">this page</a>. Choose the corresponding image file from the table below, flash it into your
board, connect a serial terminal (or Ethernet if you board supports) and enjoy <b>eLua</b>. Also note that <b>eLua binaries</b>, like the <a href="#source">source code distribution</a>,
include some example programs in it's file system, so you can run and play them (yes! we have games too! :), following the instructions in our <a href="using.html">Using eLua</a> page. The
available example programs are described in our <a href="examples.html">examples page</a>.</p>
-<p>If you need a customized binary image for an already supported platform (for example with an autorun program, with some code of yours in the File System, with your LAN IP settings) and the
+<p>If you need a customized binary image for an already supported platform (for example with an autorun program, with some code of yours in the file system, with your LAN IP settings) and the
<a href="building.html">instructions for building eLua</a> didn't work for you, feel free to <a href="overview.html#contacts">write us</a> explaining what you need. We may find some time to
build one for you and eventually make it available here too.</p>
-<p>To understand what's in a file name (for example <i>elua_lualong_lm3s8962.bin</i>) check our <a href="building.html">building eLua</a> page.
+<p>To understand what's in a file name (for example <i>elua_lualong_lm3s8962.bin</i>) check our <a href="building.html">building eLua</a> page.</p>
<!-- [NEWVER] -->
<table class="table_center">
<tbody>
@@ -36,76 +30,111 @@
<th>Image file</th>
</tr>
<tr>
-<td>0.5</td>
-<td><a target="_blank" href="http://www.atmel.com/dyn/products/Product_card.asp?part_id=3755">AT91SAM7X256</a></td>
-<td><a target="_blank" href="http://www.olimex.com/dev/sam7-ex256.html">SAM7-EX256</a></td>
+<td>0.6</td>
+<td>All (source code)</td>
+<td>All (source code)</td>
+<td>All (source code)</td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.6.tgz">elua0.6.tgz</a></td>
+</tr>
+<tr>
+<td>0.6</td>
+<td><a href="http://www.atmel.com/dyn/products/Product_card.asp?part_id=3755">AT91SAM7X256</a></td>
+<td><a href="http://www.olimex.com/dev/sam7-ex256.html">SAM7-EX256</a></td>
<td>double</td>
-<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.5_lua_at91sam7x256.bin">elua0.5_lua_at91sam7x256.bin</a></td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.6_lua_at91sam7x256.bin">elua0.6_lua_at91sam7x256.bin</a></td>
</tr>
<tr>
-<td>0.5</td>
-<td><a target="_blank" href="http://www.atmel.com/dyn/products/Product_card.asp?part_id=4104">AT91SAM7X512</a></td>
+<td>0.6</td>
+<td><a href="http://www.atmel.com/dyn/products/Product_card.asp?part_id=4104">AT91SAM7X512</a></td>
<td>None</td>
<td>double</td>
-<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.5_lua_at91sam7x512.bin">elua0.5_lua_at91sam7x512.bin</a></td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.6_lua_at91sam7x512.bin">elua0.6_lua_at91sam7x512.bin</a></td>
</tr>
<tr>
-<td>0.5</td>
-<td><a target="_blank" href="http://www.intel.com">i386 (generic)</a><br>
+<td>0.6</td>
+<td><a href="http://www.intel.com">i386 (generic)</a></td>
<td>PCs/emulators</td>
<td>double</td>
-<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.5_lua_i386.elf">elua0.5_lua_i386.elf</a></td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.6_lua_i386.elf">elua0.6_lua_i386.elf</a></td>
</tr>
<tr>
-<td>0.5</td>
-<td><a target="_blank" href="http://www.luminarymicro.com/products/lm3s6965.html">LM3S6965</a></td>
-<td><a target="_blank" href="http://www.luminarymicro.com/products/lm3s6965_ethernet_evaluation_kit.html">EKx-LM3S6965</a></td>
+<td>0.6</td>
+<td><a href="http://www.luminarymicro.com/products/lm3s6965.html">LM3S6965</a></td>
+<td><a href="http://www.luminarymicro.com/products/lm3s6965_ethernet_evaluation_kit.html">EKx-LM3S6965</a></td>
<td>double</td>
-<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.5_lua_lm3s6965.bin">elua0.5_lua_lm3s6965.bin</a></td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.6_lua_lm3s6965.bin">elua0.6_lua_lm3s6965.bin</a></td>
</tr>
<tr>
-<td>0.5</td>
-<td><a target="_blank" href="http://www.luminarymicro.com/products/LM3S8962.html">LM3S8962</a></td>
-<td><a target="_blank" href="http://www.luminarymicro.com/products/lm3s8962_can_ethernet_evaluation_kit.html">EKx-LM3S8962</a></td>
+<td>0.6</td>
+<td><a href="http://www.luminarymicro.com/products/LM3S8962.html">LM3S8962</a></td>
+<td><a href="http://www.luminarymicro.com/products/lm3s8962_can_ethernet_evaluation_kit.html">EKx-LM3S8962</a></td>
<td>double</td>
-<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.5_lua_lm3s8962.bin">elua0.5_lua_lm3s8962.bin</a></td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.6_lua_lm3s8962.bin">elua0.6_lua_lm3s8962.bin</a></td>
</tr>
<tr>
-<td>0.5</td>
-<td><a target="_blank" href="http://www.standardics.nxp.com/microcontrollers/to/pip/LPC2880FET180.html">LPC2888</a></td>
-<td><a target="_blank" href="http://www.olimex.com/dev/lpc-h2888.html">LPC-H2888</a></td>
+<td>0.6</td>
+<td><a href="http://www.standardics.nxp.com/microcontrollers/to/pip/LPC2880FET180.html">LPC2888</a></td>
+<td><a href="http://www.olimex.com/dev/lpc-h2888.html">LPC-H2888</a></td>
<td>double</td>
-<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.5_lua_lpc2888.bin">elua0.5_lua_lpc2888.bin</a></td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.6_lua_lpc2888.bin">elua0.6_lua_lpc2888.bin</a></td>
</tr>
<tr>
-<td>0.5</td>
-<td><a target="_blank" href="http://www.st.com/mcu/devicedocs-STR711FR2.html">STR711FR2</a></td>
-<td><a target="_blank" href="http://www.sctec.com.br/content/view/101/30/">MOD711</a></td>
+<td>0.6</td>
+<td><a href="http://www.st.com/mcu/devicedocs-STR711FR2.html">STR711FR2</a></td>
+<td><a href="http://www.sctec.com.br/content/view/101/30/">MOD711</a></td>
<td>double</td>
-<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.5_lua_str711fr2.bin">elua0.5_lua_str711fr2.bin</a></td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.6_lua_str711fr2.bin">elua0.6_lua_str711fr2.bin</a></td>
</tr>
<tr>
-<td>0.5</td>
-<td><a target="_blank" href="http://www.st.com/mcu/devicedocs-STR912FAW44-101.html">STR912FAW44</a></td>
-<td><a target="_blank" href="http://www.hitex.com/index.php?id=383">STR9-comStick</a></td>
+<td>0.6</td>
+<td><a href="http://www.st.com/mcu/devicedocs-STR912FAW44-101.html">STR912FAW44</a></td>
+<td><a href="http://www.hitex.com/index.php?id=383">STR9-comStick</a></td>
<td>double</td>
-<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.5_lua_str912fw44.bin">elua0.5_lua_str912fw44.bin</a></td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.6_lua_str912fw44.bin">elua0.6_lua_str912fw44.bin</a></td>
</tr>
+<tr>
+<td>0.6</td>
+<td><a href="http://www.luminarymicro.com/products/LM3S6918.html">LM3S6918</a></td>
+<td><a href="http://www.micromint.com/index.php/SBC/eagle-100.html">Micromint Eagle 100</a></td>
+<td>double</td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.6_lua_lm3s6918.bin">elua0.6_lua_lm3s918.bin</a></td>
+</tr>
+<tr>
+<td>0.6</td>
+<td><a href="http://www.atmel.com/dyn/products/product_card.asp?part_id=4117">AT32UC3A0512</a></td>
+<td><a href="http://www.atmel.com/dyn/Products/tools_card.asp?tool_id=4114">ATEVK1100</a></td>
+<td>double</td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.6_lua_at32uc3a0512.hex">elua0.6_lua_at32uc3a0512.hex</a></td>
+</tr>
+<tr>
+<td>0.6</td>
+<td><a href="http://www.st.com/mcu/devicedocs-STM32F103RE-110.html">STM32F103RE</a></td>
+<td><a href="http://www.futurlec.com/ET-STM32_Stamp.shtml">ET-STM32 Stamp</a></td>
+<td>double</td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.6_lua_stm32f103re.bin">elua0.6_lua_stm32f103re.bin</a></td>
+</tr>
+<tr>
+<td>0.6</td>
+<td><a href="http://www.st.com/mcu/devicedocs-STM32F103ZE-110.html">STM32F103ZE</a></td>
+<td><a href="http://www.st.com/mcu/contentid-100-110-STM3210E_EVAL.html">STM3210E-EVAL</a></td>
+<td>double</td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.6_lua_stm32f103ze.bin">elua0.6_lua_stm32f103ze.bin</a></td>
+</tr>
</tbody>
-</table></p>
-<p><b>NOTE:</b> <i>Lua number type</i> reffers to the built Lua interpreter number type, float or integer, as explained in the <a href="building.html">building eLua</a> page.</p>
-<h3><a name="source">Source code</a></h3>
+</table>
+<p><b>NOTE:</b> <i>Lua number type</i> refers to the built Lua interpreter number type, float or integer, as explained in the <a href="building.html">building eLua</a> page.</p>
+<a name="source" /><h3>Source code</h3>
<p>If all you want is to take a quick peek at <b>eLua</b>'s source code, but you don't need to download it, it's probably enough to use the
-<a target="_blank" href="http://svn.berlios.de/wsvn/elua">BerliOS WebSVN interface</a>. You can browse through the complete source of <b>eLua</b> using this method.<br>
-If you need to download the source code of <b>eLua</b> you can either:
+<a href="http://svn.berlios.de/wsvn/elua">BerliOS WebSVN interface</a>. You can browse through the complete source of <b>eLua</b> using this method.<br />
+If you need to download the source code of <b>eLua</b> you can either:</p>
<ul>
<li>download the source code archive of an official release</li>
<li>checkout the latest (bleeding edge) source code from the SVN repository in read-only mode (anonymous) mode</li>
<li>checkout the latest (bleeding edge) source code from the SVN repository in read-write mode (for developers)</li>
-</ul></p>
-<a name="official"><h2>Source code archives</h2></a>
+</ul>
+<a name="official" /><h2>Source code archives</h2></a>
<p>Check the table below for the download link of the source code associated with the latest official release of <b>eLua</b>. If you want to get the source
-code of an older version, check out <a href="dl_old.html">this page</a>.
+code of an older version, check out <a href="dl_old.html">this page.</p>
<!-- [NEWVER] -->
<table class="table_center">
<tbody>
@@ -114,25 +143,28 @@
<th>Source code archive</th>
</tr>
<tr>
-<td>0.5</td>
-<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua-0.5.tgz">eLua 0.5</a></td>
+<td>0.6</td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.6.tgz">eLua 0.6</a></td>
</tr>
-</tbody></table></p>
-<a name="svnpublic"><h2>SVN public repository (anonymous)</h2></a>
+</tbody></table>
+<a name="svnpublic" /><h2>SVN public repository (anonymous read-only mode)</h2>
<p>If you'd rather have the very last development ("bleeding edge") version, just check it out from our Subversion Repository:</p>
-<p><pre>$ svn checkout svn://svn.berlios.de/elua/trunk</pre></p>
+<pre>$ svn checkout svn://svn.berlios.de/elua/trunk</pre>
<p>Once checked out, the repository can be easily updated by the svn client command:</p>
-<p><pre>$ svn update</pre></p>
-<a name="svndev"><h2>SVN public repository (r/w, for developers)</h2></a>
-<p>Follow the steps below if you need write access to the <b>eLua</b> repository:
+<pre>$ svn update</pre>
+<a name="svndev" /><h2>SVN public repository (authenticated login r/w mode, for developers)</h2>
+<p>Follow the steps below if you need write access to the <b>eLua</b> repository:</p>
<ul>
- <li>if you don't have an account on <a target="_blank" href="http://developer.berlios.de/">developer.berlios.de</a>, create one.</li>
- <li><a href="overview.html#contacts">contact us</a> specifying your BerliOS ID and we'll give you write access to the repository.</li>
-</ul></p>
+ <li>if you don't have an account on <a href="http://developer.berlios.de/">developer.berlios.de</a>
+ and you plan to contribute with code for the project, please create one.</li>
+ <li><a href="overview.html#contacts">contact us</a> specifying your BerliOS ID and we'll give you write
+ (commit) access to the subversion repository.</li>
+</ul>
<p>Then checkout the repository:</p>
-<p><pre>$ export SVN_SSH='ssh -l <yourberliosid>
-$ svn checkout svn+ssh://svn.berlios.de/svnroot/repos/elua/trunk</pre></p>
+<pre>$ export SVN_SSH='ssh -l <yourberliosid>'
+$ svn checkout svn+ssh://svn.berlios.de/svnroot/repos/elua/trunk</pre>
<p>Once checked out, the repository can be easily updated:</p>
-<p><pre>$ svn update</pre></p>
+<pre>$ svn update</pre>
-</body></html>
+$$FOOTER$$
+
Modified: branches/eagle_mmc/doc/en/examples.html
===================================================================
--- branches/eagle_mmc/doc/en/examples.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/en/examples.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,16 +1,11 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>eLua examples</title>
-
-<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);">
+$$HEADER$$
<h3>Lua Code Examples</h3>
<p><b>eLua</b> distros come bundled with nice and fun
(yes! we have games too! :) Lua programs examples in the File System. They are also included in the <b>eLua</b>
source code distribution, under the <i>/romfs</i> subdirectory. As previously explained, you can run them directly from <b>eLua</b>'s file
system or you can use the eLua shell and send them via XMODEM, as
described <a href="using.html#shell">here</a>.</p>
+<br />
<h3>hello.lua: the ubiquitous "Hello, World!"</h3>
<p><strong>Runs on: </strong>all targets</p>
@@ -18,31 +13,35 @@
tradition, so we respect it :) It just prints "Hello, World!" on the terminal and
returns to the shell. Run it from the file system only if you feel too lazy to fire up
the lua interpreter inside eLua and write it yourself :)</p>
+<br />
<h3>info.lua: getting the platform data</h3>
<p><strong>Runs on: </strong>all targets</p>
<p><strong>Description: </strong>this isn't really more advanced than "Hello, World!", but it does show
an <b>eLua</b> specific module: the platform data module (<b>pd</b>). You can read
-more about the platform modules <a href="">##here</a>. The program will display the platform
+more about the platform modules <a href="refman_gen_pd.html">here</a>. The program will display the platform
name, the CPU name, the board name and the CPU clock and then will exit
to the shell.</p>
+<br />
+
<h3>led.lua: the old LED blinker, the new eLua way</h3>
-
<p><strong>Runs on: </strong> all targets except i386</p>
-<p><strong>Description: </strong> now we get to do something "more embedded": blink a LED. The code illustrates a few interesting <b>eLua</b> features:
+<p><strong>Description: </strong> now we get to do something "more embedded": blink a LED. The code illustrates a few interesting <b>eLua</b> features:</p>
<ul><li><b>cross platform code</b>: the code assigns a different pin
to the LED starting from the board name. You can see how the platform
data module makes it very easy to write such portable code.</li>
-<li><b>uart, pio, tmr, pd modules</b>: they are all used here.</li></ul></p>
+<li><b>uart, pio, tmr, pd modules</b>: they are all used here.</li></ul>
<p>Watch it blink, then press any key to return to the eLua shell.</p>
+<br />
<h3>hangman.lua: taking advantage of your terminal</h3>
<p><strong>Runs on: </strong>all targets</p>
<p><strong>Description: </strong>the geekiest example from the <b>eLua</b> distribution (or would it be morse.lua? :), it makes use of
-the <a href="">##term module</a> to let the user play a BSD-like "hangman" directly in his terminal emulator. Run the example
+the <a href="refman_gen_term.html">term module</a> to let the user play a BSD-like "hangman" directly in his terminal emulator. Run the example
and enjoy. Currently it has a very small list of words, as this was
written mainly as a proof of eLua's capabilities, but it's very easy to
-add new words/replace the existing ones. A screenshot can be seen <a href="">##here</a>.</p>
+add new words/replace the existing ones.</p>
+<br />
<h3>pwmled.lua: LED blinker, advanced class</h3>
<p><strong>Runs on: </strong>EK-LM3S8962, EK-LM3S6965</p>
@@ -50,28 +49,24 @@
infinite loop. Not much to say here, the code is very simple, yet the
results are quite spectacular. Press any key to end the sample and
return to the shell.</p>
+<br />
<h3>dualpwm.lua: because a single LED is just not enough</h3>
<p><strong>Runs on: </strong>MOD711</p>
-<p><strong>Description: </strong>My <a target="_blank" href="http://www.sctec.com.br/content/view/101/30/">MOD711 board</a> needed a
+<p><strong>Description: </strong>My <a href="http://www.sctec.com.br/content/view/101/30/">MOD711 board</a> needed a
"motherboard" for a few components (mainly the RS232-TTL level converter and a reset button) so I also added two LEDs to it, connected
to two different PWM channels. With this program, the two LEDs fade at the same type, but in different directions.</p>
+<br />
-<h3>pong.lua: eLua meets a classic</h3>
-<p><strong>Runs on: </strong>EK-LM3S8962, EK-LM3S6965</p>
-<p><strong>Description: </strong>a very simple, incomplete implementation of the famous <a target="_blank" href="http://en.wikipedia.org/wiki/Pong">pong</a>
-game. It uses the display and keys on the EK-LM3S8962 or EK-LM3S6965 boards. It uses a platform dependent module (<b>disp</b>) and also shows how
-<b>require</b> can be used from <b>eLua</b>.You can set different game speeds. Enjoy! :)</p>
-
<h3>tvbgone.lua: yes, eLua can do real time!</h3>
<p><strong>Runs on: </strong>EK-LM3S8962, EK-LM3S6965</p>
<p><strong>Description: </strong>this is more complex, but also very important for <b>eLua</b>, because it
proves that real time applications (with relatively strict timing
requirements) can run from <b>eLua</b> directly. It's the famous TV-B-Gone
-project adapted from <a target="_blank" href="http://www.ladyada.net/make/tvbgone/">LadyAda's kit</a>.
+project adapted from <a href="http://www.ladyada.net/make/tvbgone/">LadyAda's kit</a>.
If you're not familiar with TV-B-Gone, it knows how to do one thing
very well: power off your TV :) Basically it contains a lot of remote
-control codes (for a lot of TVs) that are continously sent via an IR
+control codes (for a lot of TVs) that are continuously sent via an IR
LED. This code uses the PWM module (new in <b>eLua</b> 0.4) and it also does
file I/O from Lua, since the remote control codes are kept in a
separate file (which is also part of the ROM file system). To read the
@@ -85,6 +80,7 @@
board to start sending the IR codes. The on-board LED stays lit while
the codes are transmitted and shuts off afterwards. Press the "down"
button on your board to exit the application and return to the shell.</p>
+<br />
<h3>piano.lua: because PWM is great</h3>
<p><strong>Runs on: </strong>EK-LM3S8962, EK-LM3S6965, SAM7-EX256</p>
@@ -92,7 +88,8 @@
notes via the on-board speaker using the PC keyboard. The on-screen
keyboard shows what keys you must press for different notes, and you
can set your octave and inter-note delay. Press ESC to end your <b>eLua</b>
-musical session :) A screenshot can be seen <a href="##">here</a>.</p>
+musical session :)</p>
+<br />
<h3>bisect.lua: floating point at its best</h3>
<p><strong>Runs on: </strong>all targets</p>
@@ -100,14 +97,16 @@
here to show that <b>eLua</b> can do floating point just like on a desktop
machine, albeit slower. Run it on your target, then run it again, but
this time on the PC, and compare the results. Yes, they are identical.</p>
+<br />
<h3>life.lua: the game of life</h3>
<p><strong>Runs on: </strong>i386</p>
<p><strong>Description: </strong>another example taken directly from the Lua distribution, this time
-the well known <a target="_blank" href="http://en.wikipedia.org/wiki/Conway%27s_Game_of_Life">game of life</a>.
+the well known <a href="http://en.wikipedia.org/wiki/Conway%27s_Game_of_Life">game of life</a>.
Start it and enjoy. Only included on i386 by default because it's faster on i386, but it can run on other
platform too (although it requires quite a bit of memory, which is not a problem for boards with external
memory). </p>
+<br />
<h3>morse.lua: because PWM is great, part II</h3>
<p><strong>Runs on: </strong> EK-LM3S8962, EK-LM3S6965, SAM7-EX256</p>
@@ -116,6 +115,7 @@
letters and Morse codes are also shown on the terminal. Use '+' and
'-'' to change the frequency, up and down arrows to change the speed,
's' to mute/unmute, and ESC to exit.</p>
+<br />
<h3>lhttpd.lua: only with (e)Lua ...</h3>
<p><strong>Runs on: </strong>EK-LM3S8962, EK-LM3S6965</p>
@@ -130,28 +130,72 @@
using "print"), the server knows how to handle this too. When is the
last time you heard about a scripting web server in 256k of Flash/64k
of RAM? </p><p>The full list of features is given below:</p>
-
-<ul><li>completely written in Lua</li><li>can handle a single connection at a time (for now)</li><li>can serve text and images (so far)</li><li>gets its files from the ROM file system (this will be extended when more filesystems are added)</li><li>can
-execute embedded Lua code and replace it with its output (via "print"
-statements). Embed Lua code in your HTML files between tags, make sure
+<ul>
+<li>completely written in Lua</li>
+<li>can handle a single connection at a time (for now)</li>
+<li>can serve text and images (so far)</li>
+<li>gets its files from the ROM file system (this will be extended when more
+ filesystems are added)</li>
+<li>can execute embedded Lua code and replace it with its output (via "print" statements). Embed Lua
+ code in your HTML files between tags, make sure
your HTML file extension is ".pht", and the server will preprocess it
-and replace the Lua code with its output</li><li>if a file with
-".lua" extension is requested, it doesn't send the file, but executes
-it and sends its output (via "print" statements)</li></ul>
-
+and replace the Lua code with its output</li>
+<li>if a file with ".lua" extension is requested, it doesn't send the file, but
+ executes it and sends its output (via "print" statements)</li></ul>
<p>This is still work in progress, but it already works quite well.
Take a look at <i>romfs/index.pht</i> and <i>romfs/test.lua</i> from the source
distribution for an example of how to include Lua code in your HTML
files.</p>
+<br />
<h3>adcscope.lua: ADCs and eLua, part I</h3>
-<p><b>Runs on: </b>##TODO</p>
-<p><b>Description: </b>##TODO
+<p><strong>Runs on: </strong>EK-LM3S8962, EK-LM3S6965, ET-STM32</p>
+<p><strong>Description: </strong>This uses the ADC module to acquire samples as quickly as possible on available ADC channels, and display them using the term module. Additionally, for different channels, different length moving average filters are used to smooth the data being acquired (see the adcchannels and adcsmoothing variables). While running the script also provides the average length of time required to get conversion results from each channel and the amount of memory used by garbage collectable objects in the running Lua environment.
</p>
+<br />
-
<h3>adcpoll.lua: ADCs and eLua, part II</h3>
-<p><b>Runs on: </b>##TODO</p>
-<p><b>Description: </b>##TODO
+<p><strong>Runs on: </strong>EK-LM3S8962, EK-LM3S6965, ET-STM32</p>
+<p><strong>Description: </strong>This is another example of the ADC and term modules. This version uses hardware timers to acquire samples deterministically at a rate of 4 samples per second. When run, note that data from some channels appear before that of others. This is due to the moving average (smoothing) filter being enabled. This filter will only return conversion results after enough samples are acquired to fill the filter length. In addition, this example utilizes a polling mechanism. When adc.getsample or adc.getsamples return nil, no samples were available to be returned. Values for each channel, in this example, are only displayed when there is a non-nil value returned by adc.getsample.
</p>
-</body></html>
+<br />
+
+<h3>logo.lua: graphics and eLua</h3>
+<p><strong>Runs on: </strong>EK-LM3S8962, EK-LM3S6965</p>
+<p><b>Description: </b>a complex example, proving that <b>eLua</b> can do even animations! The <b>eLua</b> logo is shown
+on the on-board OLED display and then <b>rotated in realtime</b>. You can get about 3fps with this example. Not bad for a bitmap
+rotation application that uses quite a lot of emulated floating point computations at 50MHz. Optimizations are still
+possible, but are left (for now) as an exercise for the <b>eLua</b> apprentice. Take a look at the code to discover
+how a highly optimized eLua program looks like, but don't spend too much time with it if your math feels rusty :)
+</p>
+<br />
+
+
+<h3>pong.lua: eLua meets a classic</h3>
+<p><strong>Runs on: </strong>EK-LM3S8962, EK-LM3S6965</p>
+<p><b>Description: </b>a tribute to the classics, as well as an addictive way of spending your time, this examples proves
+without any doubt that you can write games with <strong>eLua</strong>. This variant of the well known "pong" games plays on
+the OLED display of your LM3S board, using the on-board switches to control your paddle. Hit the ball, collect or avoid the
+"bonuses", a keep on trying to beat that highscore :) The code is just complex enough to give you a fair idea about the
+possibilities of <b>eLua</b>.
+</p>
+<br />
+
+<h3>spaceship.lua: even more fun</h3>
+<p><strong>Runs on: </strong>EK-LM3S8962, EK-LM3S6965</p>
+<p><b>Description: </b>tired of hitting a ball? What about hitting a spaceship instead? Or, even better, more spaceships? Defend
+your base with this little game that also plays on the OLED display of your LM3S board and uses the on-board switches as
+paddles. Once again, take a look at the code to get a feeling of <b>eLua</b>.
+</p>
+<br />
+
+<h3>tetrives.lua: don't let it get too addictive</h3>
+<p><strong>Runs on: </strong>EK-LM3S8962, EK-LM3S6965</p>
+<p><b>Description: </b>tetris doesn't need any introduction at all, so just start the game, grab the on-board switches and start
+making lines after lines on your OLED display. Once you're done playing, you might want to take a look at the code. This example
+is fairly complex, large, uses <b>eLua</b> specific techniques (explicit memory management with calls to the garbage collector) and might
+serve as a good base for your own code.
+</p>
+
+$$FOOTER$$
+
Modified: branches/eagle_mmc/doc/en/faq.html
===================================================================
--- branches/eagle_mmc/doc/en/faq.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/en/faq.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,42 +1,38 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>eLua FAQ</title>
+$$HEADER$$
+<h3>eLua Frequently Asked Questions</h3><p>Welcome to the official <b>eLua</b>
+FAQ!<br />
+It is assumed that you already know what <b>eLua</b> is, so here's a list of questions (and their answers) that you might find useful.</p>
-<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);">
-<h3>eLua Frequently Asked Questions</h3><p>Welcome to the official <b>eLua</b> FAQ!
-It is assumed that you already know what <b>eLua</b>, so here's a list of questions (and their answers) that you might find useful.</p>
-
<ul>
- <li><a href="faq.html#learnlua">How can I learn Lua? Is it hard?</a></li>
- <li><a href="faq.html#helpelua">How can I help eLua?</a>
- <li><a href="faq.html#comercial">Can I use eLua in my commercial, closed source project?</a>
- <li><a href="faq.html#fast">Is eLua fast enough?</a>
- <li><a href="faq.html#minimum">What are the minimum requirements for eLua?</a></li>
- <li><a href="faq.html#portability">Since I'm using the Lua platform modules (uart, spi, pwm, tmr...), can I trust my peripheral code to run the
+ <li><a href="#learnlua">How can I learn Lua? Is it hard?</a></li>
+ <li><a href="#helpelua">How can I help eLua?</a></li>
+ <li><a href="#comercial">Can I use eLua in my commercial, closed source project?</a></li>
+ <li><a href="#fast">Is eLua fast enough?</a></li>
+ <li><a href="#minimum">What are the minimum requirements for eLua?</a></li>
+ <li><a href="#portability">Since I'm using the Lua platform modules (uart, spi, pwm, tmr...), can I trust my peripheral code to run the
same on all my platforms?</a></li>
- <li><a href="faq.html#luaversions">What's the deal with floating-point Lua and integer only Lua?</a></li>
- <li><a href="faq.html#windows">All your tutorials give instructions on how to compile eLua under Linux, yet you seem to use a lot of Windows tools.
- How come?</a>
- <li><a href="faq.html#cygwin">Will you ever post instructions about how to compile toolchains under Cygwin in Windows?</a></li>
- <li><a href="faq.html#bytecode">I know that Lua can be compiled to bytecode, so I compiled one of the eLua examples with luac and tried to run it on
- my eLua board, but it didn't work. Is this a bug in eLua?</li>
- <li><a href="faq.html#outofmemory">I get "out of memory" errors when I run my Lua programs, what should I do?</li>
- <li><a href="faq.html#rotables">I enabled the LTR patch, but now all my module tables (math, io, string, spi and so on) are read only. Do I have to
- disable LTR if I want write access to these modules?</a>
+ <li><a href="#luaversions">What's the deal with floating-point Lua and integer only Lua?</a></li>
+ <li><a href="#windows">All your tutorials give instructions on how to compile eLua under Linux, yet you seem to use a lot of Windows tools.
+ How come?</a></li>
+ <li><a href="#cygwin">Will you ever post instructions about how to compile toolchains under Cygwin in Windows?</a></li>
+ <li><a href="#bytecode">I know that Lua can be compiled to bytecode, so I compiled one of the eLua examples with luac and tried to run it on
+ my eLua board, but it didn't work. Is this a bug in eLua?</a></li>
+ <li><a href="#outofmemory">I get "out of memory" errors when I run my Lua programs, what should I do?</a></li>
+ <li><a href="#rotables">I enabled the LTR patch, but now all my module tables (math, io, string, spi and so on) are read only. Do I have to
+ disable LTR if I want write access to these modules?</a></li>
</ul>
-<hr>
-<a name="learnlua"><h2>How can I learn Lua? Is it hard?</h2></a>
+<hr />
+
+<a name="learnlua" /><h2>How can I learn Lua? Is it hard?</h2>
<p>Lua is a minimalistic language (yet very powerful) which is quite easy to learn. Once you understand the basic concepts you'll find yourself writing
- Lua programs in notime. The main resource is the <a target="_blank" href="http://www.lua.org/">Lua homepage</a>. In the
- <a target="_blank" href="http://www.lua.org/docs.html">documentation page</a> you'll find the reference manual and the first version of the excellent
+ Lua programs in notime. The main resource is the <a href="http://www.lua.org/">Lua homepage</a>. In the
+ <a href="http://www.lua.org/docs.html">documentation page</a> you'll find the reference manual and the first version of the excellent
"Programming in Lua" book. I recommend purchasing the second version of this book, since it's likely that this is all you'll ever need to learn
- Lua. Another very good resource is the <a target="_blank" href="http://lua-users.org/wiki/">Lua wiki</a>. If you need more help, check the
- <a target="_blank" href="http://www.lua.org/community.html">community page</a>. Lua has a very friendly and active community.</p>
+ Lua. Another very good resource is the <a href="http://lua-users.org/wiki/">Lua wiki</a>. If you need more help, check the
+ <a href="http://www.lua.org/community.html">community page</a>. Lua has a very friendly and active community.</p>
-<a name="helpelua"><h2>How can I help eLua?</h2></a>
+<a name="helpelua" /><h2>How can I help eLua?</h2>
<p><b>eLua</b> has many ambitious goals, so it would be great to have more people working on it. Take a look at the
<a href="status.html#roadmap">roadmap page</a>, and if you see something there that you'd like to work on, don't hesitate to
<a href="overview.html#contacts">contact us</a>. Also, if you'd like to make a donation to the project (money, or maybe a development board)
@@ -44,32 +40,35 @@
incomplete feature. Or if you just thought about a cool feature that you'd like to see in <b>eLua</b>.
If so, feel free to <a href="overview.html#contacts">contact us</a>.</p>
-<a name="comercial"><h2>Can I use eLua in my commercial, closed source project?</h2></a>
-<p>Starting with version 0.6, <b>eLua</b> distributed under a MIT license, so you can use it in your close source projects. Prior to this it was
- distributed under GPL, which restricted its usage to open source applications only. Be careful though, <b>eLua</b> includes some 3rd party libraries,
+<a name="comercial" /><h2>Can I use eLua in my commercial, closed source project?</h2>
+<p>Starting with version 0.6, <b>eLua</b> is distributed under a MIT license, so you can use it in your close source projects. Prior to this it was
+ distributed under GPL, which restricted its usage to open source applications. Be careful though, <b>eLua</b> includes some
+ (few) 3rd party libraries,
each with its own licensing terms that might be more restrictive than MIT. See <a href="overview.html#license">the eLua license</a> for details.</p>
-<a name="fast"></a><h2>Is eLua fast enough?</h2></a>
+<a name="fast" /><h2>Is eLua fast enough?</h2>
<p>This pretty much depends on what you expect. If you expect your Lua code to run as fast as your compiled C code, this won't happen, simply because C
is a compiled language, while Lua is an interpreted language. That said, you'll be happy to know that Lua is one of the fastest interpreted languages
- out there. If you really need both high speed and Lua, you can write your speed critical code sections in C and export them as a Lua module.
- This way you get the best of both worlds. We don't have any official benchmarks about Lua speed on embedded devices, but you might want to check the
- TV-B-Gone example on the <a href="examples.html">##examples page</a>.TV-B-Gone is a "software remote control" application coded directly in <b>eLua</b>.
+ out there. If you really need both high speed and Lua, you can (very
+ easily in eLua) write your speed critical code sections in C and export them as a Lua module.
+ This way you get the best of both worlds.<br />
+ We don't have any official benchmarks about Lua speed on embedded devices, but you might want to check the
+ TV-B-Gone example on the <a href="examples.html">examples page</a>.TV-B-Gone is a "software remote control" application coded directly in <b>eLua</b>.
If you're familiar with the remote control protocols, you'll know that this kind of application is quite "real time", and delays in the order of
milliseconds or even less can make your software remote control fail. Yet this sample runs without problems on a 50MHz Cortex (Thumb2) CPU. This should
give you a fairly intuitive view on the speed of eLua.</p>
-<a name="minimum"><h2>What are the minimum requirements for eLua?</h2></a>
+<a name="minimum" /><h2>What are the minimum requirements for eLua?</h2>
<p>It's hard to give a precise answer to this. As a general rule for
a 32-bit CPU, we recommend at least 256k of Flash (program memory) and
at least 64k of RAM. However, this isn't a strict requirement. A
-stripped down, integer-only version of eLua can definetely fit in 128k
+stripped down, integer-only version of eLua can definitely fit in 128k
of Flash, and depending on your type of application, 32k of RAM might
prove just fine. It largely depends on your needs.</p>
-<a name="portability"><h2>Since I'm using the Lua platform modules (uart, spi, pwm, tmr...), can I trust my peripheral code to run the same on all my
- platforms?</h2></a>
-<p>Unfortunately, no. While <b>eLua</b> makes it possible to have a common code on different platforms using the <a href="">##platform interface</a>,
+<a name="portability" /><h2>Since I'm using the Lua platform modules (uart, spi, pwm, tmr...), can I trust my peripheral code to run the same on all my
+ platforms?</h2>
+<p>Unfortunately, no. While <b>eLua</b> makes it possible to have a common code on different platforms using the <a href="arch_platform.html">platform interface</a>,
it can't possibly provide the same functionality on all platforms, since all MCUs are not created equal. It is very recommended
(and many times imperative) to have an understanding of the peripherals on your particular MPU before you start writing your code.
This, of course, is not particular to <b>eLua</b>, but it's especially important since the platform interface might give the impression that it
@@ -90,11 +89,11 @@
changing the base clock for channel 1, you're also changing the base clock for channel 0; if channel 0 was already running, you won't like
what will happen next. This time no eLua function can save you, you simply need you know your CPU architecture.</li>
<li><b>GPIO</b>: only some platform have internal pullups for the GPIO pins (others might also have pulldowns). However, in this case you're safe, as
- <b>eLua</b> will signal an error if you try to execute a pullup operatin on a platform that does not support it.</li>
+ <b>eLua</b> will signal an error if you try to execute a pull-up operation on a platform that does not support it.</li>
</ul>
<p>The lesson here is clear: understand your platform first!</p>
-<a name="luaversions"><h2>What's the deal with floating-point Lua and integer only Lua?</h2></a>
+<a name="luaversions" /><h2>What's the deal with floating-point Lua and integer only Lua?</h2>
<p>Lua is build around a number type. Every number in Lua will have this type. By default, this number type is a double. This means that even if your
program only does integer operations, they will still be treated as doubles. On embedded platforms this is a problem, since the floating point
operations are generally emulated in software, thus they are very slow. This is why <b>eLua</b> gives you "integer only Lua": a Lua with the default
@@ -102,26 +101,26 @@
printf/scanf and friends, which has quite a strong impact on the code size) and increased speed. The downside is that you'll loose the ability to do
any floating point operations (although a separate module that will partially overcome this limitation will be provided in the future).</p>
-<a name="windows"><h2>All your tutorials give instructions on how to compile eLua under Linux, yet you seem to use a lot of Windows tools. How come?</h2></a>
+<a name="windows" /><h2>All your tutorials give instructions on how to compile eLua under Linux, yet you seem to use a lot of Windows tools. How come?</h2>
<p>It's true that we do all the <b>eLua</b> development under Linux, since we find Linux an environment much more suited for development. At the same
time it's true that most of the tools that come with my development boards run under Windows. So we choose to use the best of both world: Bogdan runs
- Linux under a <a target="_blank" href="http://www.virtualbox.org">VirtualBox</a> emulator, and does verything else under Windows. Dado does everything on
- Linux and runs Windows under <a href="http://www.vmware.com" target="_blank">VMWare</a>. Both options are nice if you master your environment. To make
+ Linux under a <a href="http://www.virtualbox.org">VirtualBox</a> emulator, and does everything else under Windows. Dado does everything on
+ Linux and runs Windows under <a href="http://www.vmware.com">VMWare</a>. Both options are nice if you master your environment. To make
everything even more flexible, Bogdan keeps his VirtualBox Ubuntu image on an external WD passport disk that he can carry with him wherever he goes,
so he can work on eLua whenever he has a bit of spare time :)</p>
-<a name="cygwin"><h2>Will you ever post instructions about how to compile toolchains under Cygwin in Windows?</h2></a>
+<a name="cygwin" /><h2>Will you ever post instructions about how to compile toolchains under Cygwin in Windows?</h2>
<p>Bogdan: If I ever have way too much spare time on my hands, yes. Otherwise, no. There are many reasons for this. As I already mentioned, I favour Linux
over Windows when it comes to developing applications. Also, I noticed that the GNU based toolchains are noticeable slower on Cygwin than on Linux, so
experimenting with them can prove frustrating. Also, compiling under Linux and Cygwin should be quite similar,so try starting from my Linux based
tutorials, they might work as well on Cygwin.</p>
-<a name="bytecode"><h2>I know that Lua can be compiled to bytecode, so I compiled one of the eLua examples with luac and tried to run it on my eLua
- board, but it didn't work. Is this a bug in eLua?</h2></a>
+<a name="bytecode" /><h2>I know that Lua can be compiled to bytecode, so I compiled one of the eLua examples with luac and tried to run it on my eLua
+ board, but it didn't work. Is this a bug in eLua?</h2>
<p>This is not a bug in <b>eLua</b>, it's a bit more subtle than that. See <a href="using.html#cross">the cross-compile section</a> for a full discussion
about this problem and its fix.</p>
-<a name="outofmemory"><h2>I get "out of memory" errors when I run my Lua programs, what should I do?</h2></a>
+<a name="outofmemory" /><h2>I get "out of memory" errors when I run my Lua programs, what should I do?</h2>
<p>There are a number of things you can try to overcome this:</p>
<ul>
<li><b>enable the LTR patch</b>: you can get very significant improvements if you enable the LTR patch in your <b>eLua</b> image. See
@@ -130,21 +129,22 @@
<li><b>try to avoid using too many strings</b>: strings are immutable in Lua. That means that a statement like <i>s = s .. "\n"</i> (where s is a string)
will create a new string each time it's called. If this happens a lot (for example in a loop), your memory will quickly run out because of all the
strings. If you really need to do frequent string operations, put them in a table and then use
- <a target="_blank" href="http://www.lua.org/manual/5.1/manual.html#5.5">table.concat</a> to make a string from your table.</li>
+ <a href="http://www.lua.org/manual/5.1/manual.html#5.5">table.concat</a> to make a string from your table.</li>
<li><b>control Lua's garbage collection manually</b>: if you're still running out of memory, try calling <i>collectgarbage('collect')</i> from your code,
which will force a garbage collection and thus might free some memory.</li>
</ul>
-<a name="rotables"><h2>I enabled the LTR patch, but now all my module tables (math, io, string, spi and so on) are read only. Do I have to
- disable LTR if I want write access to these modules?</h2></a>
+<a name="rotables" /><h2>I enabled the LTR patch, but now all my module tables (math, io, string, spi and so on) are read only. Do I have to
+ disable LTR if I want write access to these modules?</h2>
<p>You don't really have to disable LTR to get write access to your rotables, you can use some simple Lua "tricks" instead. Let's suppose that you need
write access to the <b>math</b> module. With LTR enabled, <b>math</b> is a rotable, so you can't change its keys/values. But you can use metatables
to overcome this limitation:</p>
-<p><pre><code>local oldmath = math
+<pre><code>local oldmath = math
math = { __index = oldmath }
setmetatable( math, math )
-</code></pre></p>
+</code></pre>
<p>This way you can use <i>math</i> in "write mode" now (since it is a regular table), but you can still access the keys from the original <i>math</i>
rotable. Of course, if you need write access to <b>all</b> your modules (or to most of them) it makes more sense to disable LTR instead, but from our
observations this doesn't happen in practice.</p>
-</body></html>
+$$FOOTER$$
+
Modified: branches/eagle_mmc/doc/en/forum.html
===================================================================
--- branches/eagle_mmc/doc/en/forum.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/en/forum.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,12 +1,5 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>eLua development forum</title>
-
-<link rel="stylesheet" type="text/css" href="../style.css">
-</head>
-<body style="background-color: rgb(255, 255, 255);">
+$$HEADER$$
<a id="nabblelink" href="http://n2.nabble.com/eLua-Development-f2368040.html">eLua Development</a>
<script src="http://n2.nabble.com/embed/f2368040"></script>
-</body></html>
+$$FOOTER$$
Modified: branches/eagle_mmc/doc/en/genericmodules.html
===================================================================
--- branches/eagle_mmc/doc/en/genericmodules.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/en/genericmodules.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,9 +1,9 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8"/>
<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
-<link rel="stylesheet" type="text/css" href="../style.css">
+<link rel="stylesheet" type="text/css" href="../style.css"></link>
</head>
<body style="background-color: rgb(255, 255, 255);">
<h3><a name="over"></a>eLua Generic Modules</h3>
Modified: branches/eagle_mmc/doc/en/installing.html
===================================================================
--- branches/eagle_mmc/doc/en/installing.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/en/installing.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,11 +1,22 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Installing eLua</title>
+$$HEADER$$
+<h3>Installing eLua</h3>
+<p>To use <b>eLua</b> in one of the
+ <a href="status.html#platforms">supported
+platforms</a>, you need to install
+it in your target kit/device or, more precisely, to flash the <b>eLua</b>
+image into the platform of your choice.<br />
+This section shows specific installation instructions and tips, for all the
+CPU/boards supported by <b>eLua</b>.<br />
+<br />
+First, you need to have a suitable <b>eLua</b> image for your target.<br />
+You can either download one of our ready to use
+<a href="downloads.html">binary images</a> or <a href="building.html">build
+eLua</a> to have custom image for your needs.<br />
+<br />
+Please choose the platform of your interest from the "Installing" submenu
+for more instructions.</p>
+<br />
+<br />
+<br />
+$$FOOTER$$
-<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);">
-<h3>Installing eLua</h3>
-<p>After building <b>eLua</b>, you need to install it (flash it to your board of choice) before using it. This section shows specific installation instructions for all the CPU/boards supported by <b>eLua</b>. Make sure that you already have a suitable <b>eLua</b> image for your target (either <a href="downloads.html">dowload one</a> or <a href="building.html">build it yourself</a>), then choose the platform of interest from the "Installing" submenu.</p>
-<p>When building your <b>eLua</b> image, remember to specify "prog" to the scons command line in order to get a binary image file that's suitable for programming.</p>
-</body></html>
Modified: branches/eagle_mmc/doc/en/installing_at91sam7x.html
===================================================================
--- branches/eagle_mmc/doc/en/installing_at91sam7x.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/en/installing_at91sam7x.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,16 +1,10 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Installing eLua on AT91SAM7x CPUs</title>
-
-<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);">
- <h3>Using <b>eLua</b> with the AT91SAM7X CPUs from Atmel</h3>
- <p><a target="_blank" href="http://www.atmel.com">Atmel</a> is a company that doesn't need any kind of introduction :) Their huge product range include some quite nice ARM7TDMI core implementations.
- Among them are the <a target="_blank" href="http://www.atmel.com/dyn/products/Product_card.asp?part_id=3755">AT91SAM7X256</a> and
- <a target="_blank" href="http://www.atmel.com/dyn/products/Product_card.asp?part_id=4104">AT91SAM7X512</a> CPUs. The only difference between them is the ammount of internal memory (256k Flash+64k RAM for
+$$HEADER$$
+<h3>Using <b>eLua</b> with the AT91SAM7X CPUs from Atmel</h3>
+ <p><a href="http://www.atmel.com">Atmel</a> is a company that doesn't need any kind of introduction :) Their huge product range include some quite nice ARM7TDMI core implementations.
+ Among them are the <a href="http://www.atmel.com/dyn/products/Product_card.asp?part_id=3755">AT91SAM7X256</a> and
+ <a href="http://www.atmel.com/dyn/products/Product_card.asp?part_id=4104">AT91SAM7X512</a> CPUs. The only difference between them is the ammount of internal memory (256k Flash+64k RAM for
AT91SAM7X256 vs. 512k Flash+128k RAM for AT91SAM7X512). Loaded with peripherals, and accompanied by a good support package, they make a perfect host for <b>eLua</b>. For this tutorial
- I'm going to use the <a target="_blank" href="http://www.olimex.com/dev/sam7-ex256.html">SAM7-EX256</a> development board from <a target="_blank" href="http://www.olimex.com">Olimex</a>. It's quite a
+ I'm going to use the <a href="http://www.olimex.com/dev/sam7-ex256.html">SAM7-EX256</a> development board from <a href="http://www.olimex.com">Olimex</a>. It's quite a
decent board, and also reasonably priced, although it lacks a proper documentation package in my oppinion. It is equipped with an AT91SAM7X256 CPU. As much as I'd like to get
my hands on a board with a AT91SAM7X512 CPU, this didn't happen so far, so I'm going to stick with AT91SAM7X256. Of course, you can still try this tutorial if you have
a different AT91SAM7X256 development board. Plus, the instructions should be quite similar for AT91SAM7X512 CPUs.
@@ -18,12 +12,12 @@
<h3> Prerequisites</h3>
<p>Before you'll be able to use <b>eLua</b> on the AT91SAM7X256 CPU, make sure that:</p>
<ul>
- <li>you're using Windows. This isn't actually a strict requirement, it just makes life a bit easier. As the Atmel CPU is supported by the <a target="_blank" href="http://openocd.berlios.de/web/">OpenOCD</a> package, programming it from Linux is definitely possible, as OpenOCD runs equally well on Windows and Linux. However, since I'm forced to use Windows anyway because of the restrictions of
+ <li>you're using Windows. This isn't actually a strict requirement, it just makes life a bit easier. As the Atmel CPU is supported by the <a href="http://openocd.berlios.de/web/">OpenOCD</a> package, programming it from Linux is definitely possible, as OpenOCD runs equally well on Windows and Linux. However, since I'm forced to use Windows anyway because of the restrictions of
some of my other development boards, I'm going to take advantage of this and cover the Atmel programming tool instead of OpenOCD. The advantage is that you don't need a JTAG "dongle"
to program your board (which would be the case if you were using OpenOCD). The disadvantage, of course, is that the Atmel tool runs only on Windows. Plus, I personally find OpenOCD
- tedious to use. If you still want to use it though, you might want to check the forementioned <a target="_blank" href="http://www.olimex.com/dev/sam7-ex256.html">Olimex page</a>, they have some OpenOCD related links there.
+ tedious to use. If you still want to use it though, you might want to check the forementioned <a href="http://www.olimex.com/dev/sam7-ex256.html">Olimex page</a>, they have some OpenOCD related links there.
That said, from now on I'm going to assume that you use Windows. I'm using XP, Vista should work too.</li>
- <li>you have installed the <a target="_blank" href="http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3883">AT91 In-system Programmer (ISP)</a> package from Atmel.</li>
+ <li>you have installed the <a href="http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3883">AT91 In-system Programmer (ISP)</a> package from Atmel.</li>
<li>you already have your <b>eLua</b> image for the AT91SAM7X256 CPU (<a href="building.html">built</a> or <a href="downloads.html">downloaded</a>).</li>
</ul>
<h3>Programming eLua on the SAM7-EX256 board</h3>
@@ -49,4 +43,5 @@
</ul>
<p>That's it! A bit tricky, but <b>eLua</b> is now programmed in the CPU, so you can start your terminal emulator and enjoy it, as described in <a href="using.html">using eLua</a>.
</p>
-</body></html>
+$$FOOTER$$
+
Modified: branches/eagle_mmc/doc/en/installing_avr32.html
===================================================================
--- branches/eagle_mmc/doc/en/installing_avr32.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/en/installing_avr32.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,18 +1,13 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);">
-<meta http-equiv="Content-Language" content="en-us"><title> Installing eLua on AVR32 CPUs</title>
- <h3>Installing <b>eLua</b> on the AVR32 CPUs from Atmel</h3>
-<p><a target="_blank" href="http://www.atmel.com/products/AVR32/">AVR32</a> is a family of high performance 32-bit CPUs from <a target="_blank"
+$$HEADER$$
+<h3>Installing <b>eLua</b> on the AVR32 CPUs from Atmel</h3>
+<p><a href="http://www.atmel.com/products/AVR32/">AVR32</a> is a family of high performance 32-bit CPUs from <a
href="http://www.atmel.com">Atmel</a>. They were built as direct competitors for the various ARM core implementation of the market, and offer very good
performance (91 MIPS @ 66MHz) and power efficieny (1.3mW/MHz). Atmel claims that their AVR32 core outperforms ARMv5 (in ARM and Thumb mode) in terms of
both performance and code size. It's a proprietary architecture (so it's only implemented by Atmel), yet it has a very good support package, and an
open source toolchain based on GCC, which made it an ideal candidate for the first non-ARM (and also the first big endian) <b>eLua</b> target. Atmel
also sells a number of development boards based on their AVR23 CPUs. The one used for <b>eLua</b> is the
- <a target="_blank" href="http://www.atmel.com/dyn/Products/tools_card.asp?tool_id=4114">ATEVK1100 board</a>, built around the
- <a target="_blank" href="http://www.atmel.com/dyn/products/product_card.asp?part_id=4117">AT32UC3A0512 AVR32 MCU</a> (512k internal Flash/64k internal ARM).
+ <a href="http://www.atmel.com/dyn/Products/tools_card.asp?tool_id=4114">ATEVK1100 board</a>, built around the
+ <a href="http://www.atmel.com/dyn/products/product_card.asp?part_id=4117">AT32UC3A0512 AVR32 MCU</a> (512k internal Flash/64k internal ARM).
It's a very powerful board, featuring (among other things) an external 32 MByte SDRAM memory, which is more than enough to run any <b>eLua</b>
program I can think of :).</p>
<h3>Prerequisites</h3>
@@ -20,62 +15,62 @@
<ul>
<li>you're using Linux or Windows. It's easier to install and use Atmel's programming software on Windows, so use Windows version if you want to save
yourself from quite a bit of hassle.</li>
- <li>you installed Atmel's <a target="_blank" href="http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3886">FLIP programming software</a>, which is what you need
- in order to install your <b>eLua</b> image. Installation in easy under Windows (you just need to run a setup paclage), but quite tricky under Linux.
- The next paragraph outlines the procedure for installing FLIP in Linux.
+ <li>you installed Atmel's <a href="http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3886">FLIP programming software</a>, which is what you need
+ in order to install your <b>eLua</b> image. Installation in easy under Windows (you just need to run a setup package), but quite tricky under Linux.
+ The next paragraph outlines the procedure for installing FLIP in Linux.</li>
<li>you already have your <b>eLua</b> image for the AT32UC3A0512 CPU (<a href="building.html">built</a> or <a href="downloads.html">downloaded</a>).
Note that unlike other platforms, the ATEVK1100 needs a .hex file for programming, not a .bin.</li>
- </ul></p>
+ </ul>
<h2>Installing FLIP in Ubuntu Linux</h2>
-<p>Follow the steps below to install FLIP under Linux:
+<p>Follow the steps below to install FLIP under Linux:</p>
<ol>
- <li>download the Linux version of FLIP from <a target="_blank" href="http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3886">the Atmel FLIP page</a>. Save it
+ <li>download the Linux version of FLIP from <a href="http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3886">the Atmel FLIP page</a>. Save it
(or move it later) to your <i>/usr/local/</i> directory (you need to have superuser privileges to do that). At the moment of writing this tutorial, the
latest FLIP version is 3.2.1, so this is what we're going to use here.</li>
<li>untar the FLIP archive:
- <p><pre><code>$ cd /usr/local
+ <pre><code>$ cd /usr/local
$ sudo tar xvzf flip_linux_3-2-1.tgz</code></pre>
This will create the <i>/usr/local/flip.3.2.1</i> directory.</li>
<li>you need to install OpenJDK if it is not installed:
- <p><pre><code>$ sudo apt-get install openjdk-6-jre</code></pre></p>
+ <pre><code>$ sudo apt-get install openjdk-6-jre</code></pre>
</li>
<li>edit <i>/usr/local/flip.3.2.1/bin/batchisp3.sh</i> and add the two bolded lines before at the beginning of the file:
- <p><pre><code>#!/bin/bash -f
+ <pre><code>#!/bin/bash -f
<b>export JAVA_HOME=/usr/lib/jvm/java-6-openjdk/jre/
export FLIP_HOME=/usr/local/flip.3.2.1/bin/</b>
-if [ "$FLIP_HOME" = "" ]; then</code></pre></p>
+if [ "$FLIP_HOME" = "" ]; then</code></pre>
</li>
<li>you need to edit a binary file this time (<i>/usr/local/flip.3.2.1/libatlibusbdfu.so</i>). This happens because FLIP comes compiled for RedHat by
- default, and Ubuntu some different system paths. See <a target="_blank" href="http://www.avrfreaks.net/index.php?name=PNphpBB2&file=viewtopic&t=56562">this topic</a>
+ default, and Ubuntu some different system paths. See <a href="http://www.avrfreaks.net/index.php?name=PNphpBB2&file=viewtopic&t=56562">this topic</a>
for full details. All you have to do is change all the <b>/sys/bus/usb</b> strings inside <i>libatlibusbdfu.so</i> to <b>/dev/bus/usb</b>.</li>
<li>add the FLIP directory to your PATH:
- <p><pre><code>$ export PATH=/usr/local/flip.3.2.1/bin:$PATH</code></pre></p>
+ <pre><code>$ export PATH=/usr/local/flip.3.2.1/bin:$PATH</code></pre>
</li>
<li>FLIP interferes with a program that comes pre-installed on Ubuntu system, called <b>brltty</b>. It's meant to help the visually
impaired, so if you're not one of them, simply remove it (as it seems to interfere with a lot of other USB devices too):
- <p><pre><code>$ sudo apt-get remove brltty</code></pre></p>
+ <pre><code>$ sudo apt-get remove brltty</code></pre>
</li>
</ol>
-</p>
+
<h3>Burning <b>eLua</b> to the EVK1100 board</h3>
-<p>After you installed FLIP and added it to your $PATH, burning the <b>eLua</b> image should be quite easy:
+<p>After you installed FLIP and added it to your $PATH, burning the <b>eLua</b> image should be quite easy:</p>
<ul>
<li>connect your ATEVK1100 board with the PC using an USB cable</li>
<li>put your board in DFU mode (this is required for FLIP interaction). To do this:
- <p><ol>
+ <ol>
<li>press <b>on</b> the on-board joystick (and keep it pressed)</li>
<li>press the RESET button on the board briefly</li>
<li>release the RESET button</li>
<li>release the joystick</li>
- </ol></p>
+ </ol>
</li>
<li>if you're using Windows and it asks you for a driver, you should install it manually from <i>c:\Program Files\Atmel\Flip <version>\usb</i></li>
<li>Execute this from the command line (the command is the same on Windows and Linux, with a single exception: the FLIP executable name is <b>batchisp3</b> in Linux and <b>batchisp</b> (without a 3) in Windows):
- <p><pre><code>$ batchisp3 -hardware usb -device at32uc3a0512 -operation erase f memory flash blankcheck
- loadbuffer <image name>.hex program verify start reset 0</code></pre></p>
-</ul></p>
+ <pre><code>$ batchisp3 -hardware usb -device at32uc3a0512 -operation erase f memory flash blankcheck
+ loadbuffer <image name>.hex program verify start reset 0</code></pre></li>
+</ul>
<p>That's all, your <b>eLua</b> image is (finally) installed on your ATEVK1100 board.</p>
-</body></html>
+$$FOOTER$$
Modified: branches/eagle_mmc/doc/en/installing_i386.html
===================================================================
--- branches/eagle_mmc/doc/en/installing_i386.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/en/installing_i386.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,19 +1,15 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);">
-<meta http-equiv="Content-Language" content="en-us"><title>Using eLua on i386 CPUs</title>
- <h3>Using eLua with Intel i386 (or better) CPUs</h3>
- <p>Since the i386 platform was implemented as a proof of concept only, the only things you can do with it are:
+$$HEADER$$
+<h3>Using eLua with Intel i386 (or better) CPUs</h3>
+ <p>Since the i386 platform was implemented as a proof of concept only, the only things you can do with it are:</p>
<ul>
- <li><a href="tut_boot_lua.html">##Boot your PC in eLua</a></li>
- <li><a href="tut_lua_usb.html">##Boot eLua from a stick</a></li>
- </ul></p>
- <p>If you want to do this, <a href="building.html">build your eLua image</a> or download a precompiled image, as explained in the <a href="downloads.html">download page</a>.<br/ >
- However, most of the features that you'd find on an embedded platform won't work. You won't be able to upload programs to your i386 <b>eLua</b> box using the
+ <li><a href="tut_bootpc.html">Boot your PC in eLua</a></li>
+ <li><a href="tut_bootstick.html">Boot eLua from a stick</a></li>
+ </ul>
+ <p>If you want to do this, <a href="building.html">build your eLua image</a> or download a precompiled image, as explained in the <a href="downloads.html">download page</a>.</p>
+ <p>However, most of the features that you'd find on an embedded platform won't work. You won't be able to upload programs to your i386 <b>eLua</b> box using the
XMODEM protocol (not because it's impossible, but simply because this doesn't make sense at all on a desktop PC). Also, you won't be able to control the peripherals that you'd normally find in an
embedded CPU (SPI, I2C, PIO and all the others), because they are not present on the i386 platform (they can be emulated via different means, but this is way beyond
the scope of <b>eLua</b>). So, until further notice, i386 will be nothing more than a spectacular demo platform for <b>eLua</b>. If you think that you can make something
more out of it, please feel free to <a href="overview.html#contacts">contact us</a>. I'm actually very interested in this, but I lack the necessary resources to continue it.</p>
-</body></html>
+$$FOOTER$$
+
Modified: branches/eagle_mmc/doc/en/installing_lm3s.html
===================================================================
--- branches/eagle_mmc/doc/en/installing_lm3s.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/en/installing_lm3s.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,25 +1,19 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Installing eLua on LM3S CPUs</title>
-
-<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);">
- <h3>Using <b>eLua</b> with the LM3S (Cortex-M3) CPUs from Luminary Micro</h3>
- <p><a target="_blank" href="http://www.luminarymicro.com">Luminary Micro</a> is the company that produced the world's first silicon implementation of the Cortex-M3 processor. Their
+$$HEADER$$
+<h3>Using <b>eLua</b> with the LM3S (Cortex-M3) CPUs from Luminary Micro</h3>
+ <p><a href="http://www.luminarymicro.com">Luminary Micro</a> is the company that produced the world's first silicon implementation of the Cortex-M3 processor. Their
device portfolio is quite impressive, ranging from relatively simple devices to full-featured CPUs (with on-chip USB, EMAC, CAN, and many other peripherals). The support
package for these devices is also very good, with drivers for all the CPU peripherals and ports of 3rd party applications. And, on a personal note, I contacted Luminary Micro
some while ago with a request to support this project with one of their evaluation kits, and their response was excellent (thanks again, Luminary!). That's how a
- <a target="_blank" href="http://www.luminarymicro.com/products/lm3s8962_can_ethernet_evaluation_kit.html">EKx-LM3S8962K</a> landed on my desk. This is the development board that I'm going
- to use in this tutorial. <b>eLua</b> also supports the <a target="_blank" href="http://www.luminarymicro.com/products/ekk-lm3s6965_ethernet_evaluation_kit.html">EKx-LM3S6965</a> board from Luminary (which can be programmed exactly like the EKx-LM3S8962) and the <a target="_blank" href="http://www.micromint.com/index.php/products/by-family/sbcs/77">Eagle 100</a> board from <a target="_blank" href="http://www.micromint.com">Micromint</a>, which uses a different installation procedure.
+ <a href="http://www.luminarymicro.com/products/lm3s8962_can_ethernet_evaluation_kit.html">EKx-LM3S8962K</a> landed on my desk. This is the development board that I'm going
+ to use in this tutorial. <b>eLua</b> also supports the <a href="http://www.luminarymicro.com/products/ekk-lm3s6965_ethernet_evaluation_kit.html">EKx-LM3S6965</a> board from Luminary (which can be programmed exactly like the EKx-LM3S8962) and the <a href="http://www.micromint.com/index.php/SBC/eagle-100.html">Eagle 100</a> board from <a href="http://www.micromint.com">Micromint</a>, which uses a different installation procedure.
</p>
- <h3>Prerequisites</h3>
+ <h3>Pre-requisites</h3>
<p>Before you'll be able to use <b>eLua</b> on the LM3S CPU, make sure that:</p>
<ul>
<li>you're using Windows. Yes, I really said <b>Windows</b>. The reason is quite simple: we're going to use Luminary's tools to burn <b>eLua</b> to the board,
and they're Windows specific. This is the case with many CPUs and vendors out there. You can have Windows installed on your HDD, or under
- an emulator in Linux, it doesn't matter, you can even try to run it from <a target="_blank" href="http://www.winehq.org/">Wine</a> if you're really, really brave. I'm using XP, Vista should work too.</li>
- <li>you have installed the LM Flash Programmer tool from Luminary. Look for it on <a target="_blank" href="http://www.luminarymicro.com/products/ekk-lm3s8962_can_ethernet_evaluation_kit.html">this page</a>,
+ an emulator in Linux, it doesn't matter, you can even try to run it from <a href="http://www.winehq.org/">Wine</a> if you're really, really brave. I'm using XP, Vista should work too.</li>
+ <li>you have installed the LM Flash Programmer tool from Luminary. Look for it on <a href="http://www.luminarymicro.com/products/ekk-lm3s8962_can_ethernet_evaluation_kit.html">this page</a>,
for example (the link is in the "Software updates" table).</li>
<li>you already have your <b>eLua</b> image for the LM3S8962 CPU (<a href="building.html">built</a> or <a href="downloads.html">downloaded</a>). </li>
</ul>
@@ -45,9 +39,9 @@
want to use JTAG for programming. Fortunately, it also comes with an Ethernet bootloader, so you can upload your image via Ethernet. The only requirement
to use the bootloader is to start your image at address 0x2000 instead of the usual 0x0, since that's where the bootloader jumps. The
<a href="building.html">eLua build system</a> does this automatically if the "board=eagle-100" parameter is given at build time.<br>
-For a full description of the Ethernet bootloader consult the <a target="_blank" href="http://www.micromint.com/index.php/products/by-family/sbcs/54/118">Eagle 100 board manual</a>, or (more specifically) <a target="_blank" href="http://www.micromint.com/index.php/products/by-family/sbcs/54/122">this link</a> (look for section 2.7, <b>Firmware Updates using the Ethernet Bootloader</b>).<br>
+For a full description of the Ethernet bootloader consult the <a href="http://www.micromint.com/index.php/Download-document/32-Eagle-100-User-s-Manual.html">Eagle 100 board manual</a>, (look for section 2.7, <b>Firmware Updates using the Ethernet Bootloader</b>).<br />
You still need the LM Flash Tool to use the Ethernet bootloader, but since the board can use JTAG for firmware uploading, it should be possible to use it
with OpenOCD (or a similar package) and an external USB to JTAG adapter. The Luminary Micro forums are a good place to look for information if you're exploring the OpenOCD option.
</p>
-</body></html>
+$$FOOTER$$
Modified: branches/eagle_mmc/doc/en/installing_lpc2888.html
===================================================================
--- branches/eagle_mmc/doc/en/installing_lpc2888.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/en/installing_lpc2888.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,30 +1,24 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Installing eLua on LPC288xx CPUs</title>
-
-<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);">
+$$HEADER$$
<h3>Installing <b>eLua</b> with the LPC2888 CPU from NXP</h3>
-<p>The <a target="_blank" href="http://www.standardics.nxp.com/products/lpc2000/all/~LPC2888/">LPC2888 CPU</a> from <a target="_blank" href="http://www.nxp.com">NXP</a> packs some interesting features: huge internal 1Mbyte flash memory,
+<p>The <a href="http://www.standardics.nxp.com/products/lpc2000/all/~LPC2888/">LPC2888 CPU</a> from <a href="http://www.nxp.com">NXP</a> packs some interesting features: huge internal 1Mbyte flash memory,
on-chip USB 2.0 high speed interface, and the most complex (by far) clocking network that I've ever seen on an ATM7TDMI chip. Also, it implements the USB DFU (Device Firmware Update) profile over
- its USB interface, so it's quite easy to program it in-circuit. I'm using the <a target="_blank" href="http://www.olimex.com/dev/lpc-h2888.html">Olimex LPC-H2888</a> development board built around this chip, which packs
+ its USB interface, so it's quite easy to program it in-circuit. I'm using the <a href="http://www.olimex.com/dev/lpc-h2888.html">Olimex LPC-H2888</a> development board built around this chip, which packs
32MBytes of external SDRAM and also 2MBytes of external flash, which is more than enough for my needs. However, it does have its fair share of downsides. For starters, its support package (from NXP) is very poot when
compared to other targets on which <b>eLua</b> runs. You don't even get drivers for all your peripherals, just a a few (quite incomplete) examples. Its datasheet could be much more explit at times, especially when
referring to the clocking section (which is quite complicated). On my board, the DFU download mode (firmware upgrade via USB) stopped working out of the blue, without any apparent reasons, and I was unable to
- use DFU on the chip since then, I had to resort to using OpenOCD (and come up with a configuration file, since it was impossible to find one for LPC2888). The CPU itself has a very interesting limitation: because of a sillicon
+ use DFU on the chip since then, I had to resort to using OpenOCD (and come up with a configuration file, since it was impossible to find one for LPC2888). The CPU itself has a very interesting limitation: because of a silicon
error, it's impossible to run Thumb code from the on-chip flash, you can only run regular ARM code (?!). Also, the board that I got from Olimex completely ignores the fact that this chip can run in DFU mode (it doesn't include
any kind of jumper and/or switch to enable this mode), so I had to build a support board for it. Which is something I had to do also because the board doesn't export a RS232 interface, I had to build one around a MAX232 chip.
- All in all, my experience with this chip (and with the Olimex board) wasn't that pleasant, but this doesn't change the fact that the LPC-H2888 is the most powerful (resource-wise) board on which <b>eLua</b> runs.
+ All in all, my experience with this chip (and with the Olimex board) wasn't that pleasant, but this doesn't change the fact that the LPC-H2888 is one of the most powerful (resource-wise) boards on which <b>eLua</b> runs.
</p>
<h3>Prerequisites</h3>
<p>Before you'll be able to use <b>eLua</b> on the LPC2888 CPU, make sure that:</p>
<ul>
<li>if you're going to use DFU for firmware programming, you'll need Windows (although I heard reports of Linux programs that can program this chip in DFU mode, but I won't cover them here). If you're going to use OpenOCD, Linux, Windows,
- or any other OS that has support for <a target="_blank" href="http://openocd.berlios.de/web/">OpenOCD</a> will do. In this case, you might want to have a look at my <a href="tut_openocd.html">OpenOCD tutorial</a> before continuing.</li>
+ or any other OS that has support for <a href="http://openocd.berlios.de/web/">OpenOCD</a> will do. In this case, you might want to have a look at my <a href="tut_openocd.html">OpenOCD tutorial</a> before continuing.</li>
<li>also, if you're going to use DFU, you'll need a way to boot the chip in DFU firmware upgrade mode. This is done by pulling up (tie to VCC) the P2.3 pin at startup. On my board I included a switch for this. Press the switch, press RESET
while holding the switch pressed, then release the switch. You chip is now in DFU mode.</li>
- <li>if you're using DFU, you have installed the LPC2888 flash programming utility from <a target="_blank" href="http://www.standardics.nxp.com/support/documents/microcontrollers/zip/flash.utility.mass.dfu.lpc2888.zip">here</a> (the package also
+ <li>if you're using DFU, you have installed the LPC2888 flash programming utility from <a href="http://www.standardics.nxp.com/support/documents/microcontrollers/zip/flash.utility.mass.dfu.lpc2888.zip">here</a> (the package also
contains the Windows DFU drivers).</li>
<li>if you're using OpenOCD, you have followed the instructions from my <a href="tut_openocd.html">OpenOCD</a> tutorial.</li>
<li>you already have your <b>eLua</b> image for the LPC2888 CPU (<a href="building.html">built</a> or <a href="downloads.html">downloaded</a>).</li>
@@ -32,10 +26,11 @@
<h3>Burning <b>eLua</b> to the LPC2888 using the DFU tool from NXP</h3>
<p>The DFU flashing application doesn't work directly on the .bin files you get after building <b>eLua</b>, you need to run them though NXP's "hostcrypt" program (which is part of the LPC2888 DFU package). After you have your <b>eLua</b> .bin file,
do this from a Windows command prompt (make sure that hostcryptv2.exe is in the path):</p>
- <div class="code"><pre>C:> hostcryptv2 elua_lua_lpc2888.bin elua.ebn -K0 -F0</pre></div>
+ <pre>C:> hostcryptv2 elua_lua_lpc2888.bin elua.ebn -K0 -F0</pre>
<p>As a result, you'll have a new file (<i>elua.ebn</i>). Now boot your chip in DFU firmware upgrade mode (see above) and use the DFU utility (<i>MassDFUApplication.exe</i>) to load <i>elua.ebn</i> into your chip (the instructions on
using MassDFUApplication are in a PDF file that's included in the LPC2888 DFU package). Reset the board and enjoy.
</p>
<h3>Burning <b>eLua</b> to the LPC2888 using OpenOCD</h3>
<p>If you're as lucky as me and your board refuses to use DFU anymore, follow my <a href="tut_openocd.html">OpenOCD tutorial</a> to burn your image using OpenOCD.</p>
-</body></html>
+$$FOOTER$$
+
Modified: branches/eagle_mmc/doc/en/installing_stm32.html
===================================================================
--- branches/eagle_mmc/doc/en/installing_stm32.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/en/installing_stm32.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,47 +1,53 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Installing eLua on STM32 CPUs</title>
-
-<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);">
- <h3>Using <b>eLua</b> with the STM32 CPUs from ST</h3>
- <p>The <a target="_blank" href="http://www.st.com/mcu/inchtml-pages-stm32.html">STM32 family</a> of MCUs from
- <a target="_blank" href="http://www.st.com">ST</a> is a line of Cortex-M3 based chips with a lot of neat features, including (but not limited to) high
+$$HEADER$$
+<h3>Using <b>eLua</b> with the STM32 CPUs from ST</h3>
+ <p>The <a href="http://www.st.com/mcu/inchtml-pages-stm32.html">STM32 family</a> of MCUs from
+ <a href="http://www.st.com">ST</a> is a line of Cortex-M3 based chips with a lot of neat features, including (but not limited to) high
amounts of on-chip Flash/RAM (up to 512k Flash and 64k RAM), external memory controller that covers (P)SRAM, NAND Flash and NOR flash, integrated ADC and
DACs, advanced timers and many others. They also feature an integrated serial boot loader, so it's extremely easy to program them from anything that has
a serial port. ST provides a tool that can be used to download a program to the STM32 using this serial bootloader, but it only works in Windows. Their
bootloader protocol is documented in a separate application note though, so one can easily write a programming application for any other OS.</p>
<p><b>eLua</b> currently works on two STM32F103 variants of the STM32 family, specifically on these boards:
- <a target="_blank" href="http://www.st.com/mcu/contentid-100-110-STM3210E_EVAL.html">the STM3210E-EVAL</a> from
- <a target="_blank" href="http://www.st.com">ST</a> and the
- <a target="_blank" href="http://www.futurlec.com/ET-STM32_Stamp.shtml">ETM-STM32 stamp</a>
- from <a target="_blank" href="http://www.futurlec.com">Futurlec</a>. Instruction for installing <b>eLua</b> on each of them are provided below.
+ <a href="http://www.st.com/mcu/contentid-100-110-STM3210E_EVAL.html">the STM3210E-EVAL</a> from
+ <a href="http://www.st.com">ST</a> and the
+ <a href="http://www.futurlec.com/ET-STM32_Stamp.shtml">ETM-STM32 stamp</a>
+ from <a href="http://www.futurlec.com">Futurlec</a>. Instruction for installing <b>eLua</b> on each of them are provided below.
</p>
<h3> Prerequisites</h3>
<p>Before you'll be able to use <b>eLua</b> on the STM32F103 CPU, make sure that:</p>
<ul>
<li>you're using Windows. As already explained, the software provided by ST for serial firmware downloading works only under Windows. It's quite likely
that similar tools for Linux and other operating systems already exist or will be available shortly.</li>
- <li>you have installed the "Flash loader demonstrator" from <a target="_blank" href="http://www.st.com/mcu/modules.php?name=mcu&file=familiesdocs&FAM=110">
+ <li>you have installed the "Flash loader demonstrator" from <a href="http://www.st.com/mcu/modules.php?name=mcu&file=familiesdocs&FAM=110">
this page</a> (look for it in the "Software - PC" section).</li>
<li>you already have your <b>eLua</b> image for the STM32F103 CPU (<a href="building.html">built</a> or <a href="downloads.html">downloaded</a>).</li>
</ul>
<h3>Programming eLUa on the STM3210E-EVAL board</h3>
- <p>##TODO</p>
+ <p>Follow the steps below to install <b>eLua</b> on your STM3210-EVAL board:</p>
+ <ul>
+ <li>make sure you have a proper cable. You need a null modem cable for this board (a cable with two DB-9 female connectors, that connects RX to TX and TX to RX).
+ <li>connect the board to one of your PC serial ports using the null modem cable.</li>
+ <li>locate the two adjacent BOOT0 and BOOT1 switches, make sure that BOOT0 is set to 1 and BOOT1 to 0.</li>
+ <li>reset the board by pressing on the RESET button.</li>
+ <li>start the ST Flash loader demonstrator. Choose your serial port in the first screen, make sure that the communication parameters are 57600 8E1 and press "Next" 3 times.</li>
+ <li>select the "Download to device" radio button, then choose your <b>eLua</b> image file and hit "Next".</li>
+ <li>wait until programming is over and press "Finish".</li>
+ <li>move the BOOT0 switch to position 0.</li>
+ <li>reset the board by pressing the RESET button again.</li>
+ </ul>
<h3>Programming eLua on the ET-STM32 stamp</h3>
- <p>Follow the steps below to install <b>eLua</b> on your ET-STM32 stamp:
+ <p>Follow the steps below to install <b>eLua</b> on your ET-STM32 stamp:</p>
<ul>
- <li>connect the board to one of your PC serial ports using the provided serial cable.</li>
- <li>put the BOOT1 jumper on your board in the ISP position (it should come like that from the factory, and must likely you won't need to change this).</li>
- <li>press on the BOOT0 switch. The green "BOOT0=1" LED should light up.</li>
- <li>reset the board by pressing on the RESET button.</li>
- <li>start the ST Flash loader demonstrator. Choose your serial port in the first screen, don't change the communication parameters (57600 8E1) and press "Next" 3 times.</li>
- <li>select the "Download to device" radio button, then choose your <b>eLua</b> image file and hit "Next".</li>
- <li>wait until programming is over and press "Finish".</li>
- <li>press on the BOOT0 switch again.</li>
- <li>reset the board by pressing the RESET button again.</li>
+ <li>connect the board to one of your PC serial ports using the provided serial cable.</li>
+ <li>put the BOOT1 jumper on your board in the ISP position (it should come like that from the factory, and must likely you won't need to change this).</li>
+ <li>press on the BOOT0 switch. The green "BOOT0=1" LED should light up.</li>
+ <li>reset the board by pressing on the RESET button.</li>
+ <li>start the ST Flash loader demonstrator. Choose your serial port in the first screen, make sure that the communication parameters are 57600 8E1 and press "Next" 3 times.</li>
+ <li>select the "Download to device" radio button, then choose your <b>eLua</b> image file and hit "Next".</li>
+ <li>wait until programming is over and press "Finish".</li>
+ <li>press on the BOOT0 switch again.</li>
+ <li>reset the board by pressing the RESET button again.</li>
</ul>
- <p>Now you have <b>eLua</b> installed on your board, and you can choose the same port you used for programming as a general purpose serial port for <b>eLua</b>.
- </p>
-</body></html>
+ <p>Now you have <b>eLua</b> installed on your board, and you can choose the same port you used for programming as a general purpose serial port for <b>eLua</b> (but remember to use 115200
+8N1 as the communication parameters this time).</p>
+$$FOOTER$$
+
Modified: branches/eagle_mmc/doc/en/installing_str7.html
===================================================================
--- branches/eagle_mmc/doc/en/installing_str7.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/en/installing_str7.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,16 +1,11 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);">
-<meta http-equiv="Content-Language" content="en-us"><title> Installing eLua on STR7 CPUs</title>
- <h3>Installing <b>eLua</b> on the STR7 CPU family from ST</h3>
- <p><a target="_blank" href="http://www.st.com/mcu/inchtml-pages-str7.html">STR7</a> is a family of ATM7TDMI based CPUs from <a target="_blank" href="http://www.st.com">ST</a>. They are small, low power MCUs, with a well balanced set of on-chip peripherals. I'm using the <a target="_blank" href="http://www.sctec.com.br/content/view/101/30/">MOD711</a> header board from <a target="_blank" href="http://www.sctec.com.br">ScTec</a>. The board is
+$$HEADER$$
+<h3>Installing <b>eLua</b> on the STR7 CPU family from ST</h3>
+ <p><a href="http://www.st.com/mcu/inchtml-pages-str7.html">STR7</a> is a family of ATM7TDMI based CPUs from <a href="http://www.st.com">ST</a>. They are small, low power MCUs, with a well balanced set of on-chip peripherals. I'm using the <a href="http://www.sctec.com.br/content/view/101/30/">MOD711</a> header board from <a href="http://www.sctec.com.br">ScTec</a>. The board is
based on this STR711FR2 variant of the STR7 family. Since this is not a full-fledged development board, I had to add a few things around it: a MAX3232 RS232 to TTL converter for the serial interface, a couple of LEDs and a reset button. After that, the board was ready for some <b>eLua</b> :) </p>
<h3>Prerequisites</h3>
<p>Before you'll be able to use <b>eLua</b> on the STR711FR2 CPU, make sure that:</p>
<ul>
- <li>you're using Linux, Windows, or any other OS that has support for <a target="_blank" href="http://openocd.berlios.de/web/">OpenOCD</a>. You might have a look at my <a href="tut_openocd.html">OpenOCD tutorial</a> before continuing.</li>
+ <li>you're using Linux, Windows, or any other OS that has support for <a href="http://openocd.berlios.de/web/">OpenOCD</a>. You might have a look at my <a href="tut_openocd.html">OpenOCD tutorial</a> before continuing.</li>
<li>you already have your <b>eLua</b> image for the STR711FR2 CPU (<a href="building.html">built</a> or <a href="downloads.html">downloaded</a>).</li>
</ul>
<h3>Burning <b>eLua</b> to the MOD711 board</h3>
@@ -18,4 +13,5 @@
configuration files that I'm using for burning <b>eLua</b> to the MOD711 board. And that's it! <b>eLua</b> is now programmed in the CPU, so you can start your terminal emulator and enjoy it, as described in <a href="using.html">using eLua</a>.</p>
<p><b>IMPORTANT NOTE</b>: for this board you need to set your COM port speed to 38400 baud (as opposed to 115200 baud for the other boards). All the other parameters are the same (8 data bits,
no parity, one stop bit).</p>
-</body></html>
+$$FOOTER$$
+
Modified: branches/eagle_mmc/doc/en/installing_str9.html
===================================================================
--- branches/eagle_mmc/doc/en/installing_str9.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/en/installing_str9.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,29 +1,25 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Installing eLua on STR9 CPUs</title>
-<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);">
+$$HEADER$$
<h3>Installing <b>eLua</b> on the STR9 CPU family from ST</h3>
- <p>Among the ARM based MCUs available today, the <a target="_blank" href="http://www.st.com/mcu/inchtml-pages-str9.html">STR9</a> CPUs from <a target="_blank" href="http://www.st.com">ST</a> stand up because of a few unique features.
+ <p>Among the ARM based MCUs available today, the <a href="http://www.st.com/mcu/inchtml-pages-str9.html">STR9</a> CPUs from <a href="http://www.st.com">ST</a> stand up because of a few unique features.
First, their core is an ARM966-E, as opposed to the very popular ARM7TDMI core. This, together with some cleverly chosen on-chip hardware blocks, allows the CPU to run at 96MHz, which is very fast for a
general purpose MCU. The particular CPU I'm using (STR912FAW44) ) also has 512k of flash (and another bank of 32k flash) and 96k of internal RAM, so you won't be running out of memory anytime soon. It is accompanied by a very good support library,
and ST provides a lot of nice tools for STR9, including a graphical tool that you can use to configure the chip exactly how you want. When I wrote to ST about <b>eLua</b>, they
- agreed to send me a <a target="_blank" href="http://www.hitex.com/str9-comstick/">STR9-comStick</a> board to run <b>eLua</b> on it. Thank you very much for your help, once again. This is the board that I'm going to
+ agreed to send me a <a href="http://www.hitex.com/str9-comstick/">STR9-comStick</a> board to run <b>eLua</b> on it. Thank you very much for your help, once again. This is the board that I'm going to
use through this tutorial.</p>
<h3>Prerequisites</h3>
<p>Before you'll be able to use <b>eLua</b> on the STR912FAW44 CPU, make sure that:</p>
<ul>
- <li>you're using Linux, Windows, or any other OS that has support for <a target="_blank" href="http://openocd.berlios.de/web/">OpenOCD</a>. You might have a look at my <a href="tut_openocd.html">OpenOCD tutorial</a> before continuing.</li>
+ <li>you're using Linux, Windows, or any other OS that has support for <a href="http://openocd.berlios.de/web/">OpenOCD</a>. You might have a look at my <a href="tut_openocd.html">OpenOCD tutorial</a> before continuing.</li>
<li>if you're on Windows, you have installed the STR9-comStick support package from the accompanying CD.</li>
<li>you already have your <b>eLua</b> image for the STR912FAW44 CPU (<a href="building.html">built</a> or <a href="downloads.html">downloaded</a>).</li>
</ul>
<h3>Burning <b>eLua</b> to the STR9-comStick</h3>
<p>You need OpenOCD to do this. Just follow the instructions from my <a href="tut_openocd.html">OpenOCD tutorial </a>. On the tutorial page you'll also find links to the OpenOCD
configuration files that I'm using for burning <b>eLua</b> to the comstick.</p>
- <p><b>IMPORTANT NOTE</b>: for some very strage reasons (probably related to the on-board USB to JTAG converter) my comstick does NOT start to execute the code from its internal flash after being
+ <p><b>IMPORTANT NOTE</b>: for some very strange reasons (probably related to the on-board USB to JTAG converter) my comstick does NOT start to execute the code from its internal flash after being
powered up via the USB cable (faulty reset sequence?). To overcome this, you'll find a special OpenOCD configuration file on my <a href="tut_openocd.html">OpenOCD tutorial</a> page. It is called <i>comrst.cfg</i>,
and you can use it to reset your comstick after it is powered up.</p>
<p>That's it! <b>eLua</b> is now programmed in the CPU, so you can start your terminal emulator and enjoy it, as described in <a href="using.html">using eLua</a>.
</p>
-</body></html>
+$$FOOTER$$
+
Added: branches/eagle_mmc/doc/en/modules_lm3s.html
===================================================================
--- branches/eagle_mmc/doc/en/modules_lm3s.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/en/modules_lm3s.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,5 @@
+$$HEADER$$
+<h3>Reference manual - LM3S platform dependent modules</h3>
+<p>This paragraph presents all the modules specific to the <a href="status.html">LM3S</a> platform.</p>
+$$FOOTER$$
+
Modified: branches/eagle_mmc/doc/en/news.html
===================================================================
--- branches/eagle_mmc/doc/en/news.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/en/news.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,16 +1,48 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
+$$HEADER$$
-<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);">
-<h3>eLua Project News</h3><div class="content">
+<h3>eLua Project News</h3>
+<h2>##TODO ?? November 2009</h2>
+<p>Version ##TODO is released. The main changes are described below and the
+full list can be seen in our Version History page:</p>
+<ul>
+ <li>Added support for STR-E912 board</li>
+ <li>More PT content</li>
+ <li>Added the Lua EGC (Emergency Garbage Collection) patch</li>
+ <li>Please check our <a href="versionhistory.html">Version History page</a>
+ to see the full details of the changes.</li>
+</ul>
+
+<h2>06 October 2009</h2>
+<p>Version 0.6 is (finally) released. Here is the changelog:</p>
+<ul>
+ <li>License changed to MIT</li>
+ <li>Web page and documentation completely redesigned</li>
+ <li>Documentation available offline</li>
+ <li>Added support for AVR32 CPUs</li>
+ <li>Added support for STM32 Cortex-M3 CPUs</li>
+ <li>Added ADC module with support for moving average filters</li>
+ <li>Added support for multiple toolchains</li>
+ <li>Added an ls (or dir) shell command</li>
+ <li>Added new examples: pong, tetrives, spaceship (games), logo (graphics), adcpoll, adcscope (ADC operations)</li>
+ <li>Added the LTR (Lua Tiny RAM) patch</li>
+ <li>ROM FS content can be specified per board now</li>
+ <li>API semantic revisions (old code might not be compatible)</li>
+</ul>
+
+<h2>27 July 2009</h2>
+<p>We would like to invite all eLua users to the Lua Workshop 2009. This
+will be the first one to be held at PUC-Rio, in Rio de Janeiro, Brazil, on october 6-7 2009.
+Bogdan and Dado will make a presentation and show demos on the first day of
+the event. eLua demos will also be presented in the second day of the event.
+The activities on October 7th will be dedicated to the use of Lua in games,
+as part of Lua Games 2009, a pre-event of SBGames 2009.
+We will also proudly offer a "little surprise" for the <b>eLua comunity</b>.</p>
+
<h2>02 February 2009</h2>
<p>We know that we haven't had an official release in a while now, but
there's a lot of stuff going on with the project. The next release will
-definitely happen before the enf of February and it will come with a
+definitely happen before the end of February and it will come with a
lot of interesting new features, including support for two new
platforms, a completely redesigned documentation system, and a few
surprises that I won't mention just yet :) So stay tuned, we're working
@@ -22,16 +54,16 @@
<ul><li>Added support for STR7 CPUs from ST </li><li>Added TCP/IP support using the uIP stack </li><li>Added support for console and shell over TCP/IP besides the previous serial link</li><li>Added the "net" module (eLua's interface to TCP/IP functions) </li><li>Added the "cpu" module (eLua's interface to the target CPU) </li><li>New samples: morse.lua (Morse code encoder), lhttpd.lua (Lua scripting HTTP server) </li><li>Added support for cross-compiling Lua code (compile on PC, run on target)</li><li>XMODEM can now receive Lua bytecode in addition to Lua source code </li><li>The XMODEM buffer is now dynamic (grows as needed) instead of fixed size</li><li>Project documentation updated</li></ul>
-<p>Also, there's a new tutorial about <a href="http://www.eluaproject.net/?p=eLua_on_STR7_CPUs">how to use eLua with STR7 CPUs</a>. The rest of the project page was updated to reflect the current project status, most notably the <a href="http://www.eluaproject.net/?p=Faq">FAQ</a>, <a href="http://www.eluaproject.net/?p=Examples">examples</a> and <a href="http://www.eluaproject.net/?p=Status">status pages</a>).</p>
+<p>Also, there's a new tutorial about <a href="installing_str7.html">how to use eLua with STR7 CPUs</a>. The rest of the project page was updated to reflect the current project status, most notably the <a href="faq.html">FAQ</a>, <a href="examples.html">examples</a> and <a href="status.html">status pages</a>).</p>
-<p><strong>IMPORTANT NOTE:</strong> you'll need to update your binutils to version 2.19 to use this release with Cortex CPUs. The <a href="http://www.eluaproject.net/?p=Building_GCC_for_Cortex">Cortex GCC tutorial</a> was updated with this information.</p>
+<p><strong>IMPORTANT NOTE:</strong> you'll need to update your binutils to version 2.19 to use this release with Cortex CPUs. The <a href="tc_cortex.html">Cortex GCC tutorial</a> was updated with this information.</p>
<p>Enjoy this new release. The next one will be focused on reducing the
memory footprint (both Flash and RAM) of eLua, and (hopefully) will
also come with a nice surprise :)</p>
<h2>16 October 2008</h2>
-<p>The <a href="http://www.eluaproject.net/?p=Using_OpenOCD">OpenOCD tutorial</a> was updated with a new section about how to use OpenOCD with a STR7 CPU from ST. Also, the <a href="http://www.eluaproject.net/?p=Overview">about page</a> was updated with more information about the authors of eLua. Expect a new eLua version towards the end of October.</p>
+<p>The <a href="tut_openocd.html">OpenOCD tutorial</a> was updated with a new section about how to use OpenOCD with a STR7 CPU from ST. Also, the <a href="overview.html">about page</a> was updated with more information about the authors of eLua. Expect a new eLua version towards the end of October.</p>
<h2>10 September 2008</h2>
<p>Version 0.4.1 is released! This is a minor release, its main purpose
@@ -58,10 +90,10 @@
<h2>02 September 2008</h2>
-<p>The eLua site was updated in anticipation of the new 0.4 release, which will come soon (very soon, in fact). Now there's a <a href="http://www.eluaproject.net/?p=Faq">FAQ page</a>. Also, the <a href="http://www.eluaproject.net/?p=Status">status and roadmap</a>, <a href="http://www.eluaproject.net/?p=Building_eLua">building eLua</a>, <a href="http://www.eluaproject.net/?p=Example">example programs</a> and <a href="http://www.eluaproject.net/?p=Using_OpenOCD">using OpenOCD</a> pages were updated. And there's yet another new page on <a href="http://www.eluaproject.net/?p=eLua_on_LPC2888_CPUs">how to use eLua with LPC2888 CPUs</a>. Expect the 0.4 release later today.</p>
+<p>The eLua site was updated in anticipation of the new 0.4 release, which will come soon (very soon, in fact). Now there's a <a href="faq.html">FAQ page</a>. Also, the <a href="status.html">status and roadmap</a>, <a href="building.html">building eLua</a>, <a href="examples.html">example programs</a> and <a href="tut_openocd.html">using OpenOCD</a> pages were updated. And there's yet another new page on <a href="installing_lpc2888.html">how to use eLua with LPC2888 CPUs</a>. Expect the 0.4 release later today.</p>
<h2>09 August 2008</h2>
-<p>OK, this took less time than I expected :) The page on how to use eLua with STR9 CPUs is available <a href="http://www.eluaproject.net/?p=eLua_on_STR9_CPUs">here</a>.</p>
+<p>OK, this took less time than I expected :) The page on how to use eLua with STR9 CPUs is available <a href="installing_str9.html">here</a>.</p>
<h2>09 August 2008</h2>
<p>Version 0.3 is released! The project page was updated, with more
@@ -72,7 +104,7 @@
<h2>06 August 2008</h2>
-<p>The web page was updated with an <a href="http://www.eluaproject.net/?p=Using_OpenOCD">OpenOCD tutorial</a>
+<p>The web page was updated with an <a href="tut_openocd.html">OpenOCD tutorial</a>
that will continue to grow as more and more targets are added. This
update is also an informal announcement of the soon to come eLua 0.3
release, which (among other things) brings support for the <a href="http://www.hitex.com/index.php?id=383">STR9-comStick</a>.</p>
@@ -85,7 +117,7 @@
about the new eLua download locations.</p>
<h2>28 July 2008</h2>
-<p>I got a report that compiling a simple C++ program for a Cortex CPU with a compiler built after <a href="http://www.eluaproject.net/?p=Building_GCC_for_Cortex">my instructions</a>
+<p>I got a report that compiling a simple C++ program for a Cortex CPU with a compiler built after <a href="tc_cortex.html">my instructions</a>
failed with a linker error. I checked and I found out that the gcc's
C++ library (libstdc++) wasn't even build properly for Cortex-M3. My
bad. I updated the tutorial page. The only modification is in step 4,
@@ -101,19 +133,19 @@
<h2>25 July 2008</h2>
-<p>Project page updated to reflect the current eLua <a href="http://www.eluaproject.net/?p=Status">status and roadmap</a>.
+<p>Project page updated to reflect the current eLua <a href="status.html">status and roadmap</a>.
Now there is a separate status and roadmap page. Also, version 0.2 is
about to be released soon, with many new features, improvements and
support for a new platform. More documentation is on the way, too.</p>
<h2>15 July 2008</h2>
-<p>Added a <a href="http://www.eluaproject.net/?p=Booting_eLua_from_a_stick">tutorial</a> on how to make your own eLua USB bootable stick! Get it while it's hot! :)</p>
+<p>Added a <a href="tut_bootstick.html">tutorial</a> on how to make your own eLua USB bootable stick! Get it while it's hot! :)</p>
<h2>11 July 2008</h2>
-<p>eLua version 0.1 is finally out! Be sure to check the <a href="http://www.eluaproject.net/?p=Downloads">download page</a>,
+<p>eLua version 0.1 is finally out! Be sure to check the <a href="downloads.html">download page</a>,
and also the project page. The build instructions are included in the
eLua archive. Also, new tutorials (building cross compilers for ARM and
-i386) were added, and the <a href="http://www.eluaproject.net/?p=Booting_your_PC_in_eLua">boot into Lua</a> page was updated to reflect the fact that you can build the eLua ELF file yourself now!</p>
+i386) were added, and the <a href="tut_bootpc.html">boot into Lua</a> page was updated to reflect the fact that you can build the eLua ELF file yourself now!</p>
<h2>07 July 2008</h2>
<p>I'm still "brushing" the source code and adding more documentation
@@ -121,7 +153,7 @@
(hopefully) nice surprise for all of you who showed interest in eLua
(and for those of you who didn't, hopefully this will make you curious
:) ). So, if you ever wanted to boot your PC directly in Lua, take a
-look <a href="http://www.eluaproject.net/?p=Booting_your_PC_in_eLua">here</a>.
+look <a href="tut_bootpc.html">here</a>.
That's right: no OS, just GRUB loading a multiboot compliant ELF file!
The ELF file is build from the exact source tree I'm using to build
eLua for embedded devices, I only needed to change the platform layer
@@ -133,6 +165,7 @@
"BIOS scripting with Lua", <a href="http://en.wikipedia.org/wiki/Open_Firmware">Open Firmware</a> with Lua instead of Forth, educational applications and many others.)</p>
<h2>05 July 2008</h2>
-<p>The web page is up! For now you can only read the <a href="http://www.eluaproject.net/?p=Overview">project description</a>. Also, a tutorial about how to compile a GCC toolchain for the Cortex architecture is available <a href="http://www.eluaproject.net/?p=Building_GCC_for_Cortex">here</a>.</p>
-</div>
-</body></html>
+<p>The web page is up! For now you can only read the <a href="overview.html">project description</a>. Also, a tutorial about how to compile a GCC toolchain for the Cortex architecture is available <a href="tc_cortex.html">here</a>.</p>
+
+$$FOOTER$$
+
Modified: branches/eagle_mmc/doc/en/overview.html
===================================================================
--- branches/eagle_mmc/doc/en/overview.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/en/overview.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,63 +1,59 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
+$$HEADER$$
+<a name="whatis" /><h3>What is eLua ?</h3>
+<p><strong>eLua</strong>
+stands for <strong>Embedded Lua</strong> and the project
+aims to offer the full set of features of the <a href="http://www.lua.org">Lua Programming Language</a> to the embedded world. </p>
-<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);">
-<a name="whatis"></a><h3>What is eLua ?</h3>
<p><strong>eLua</strong>
-stands for <strong>Embedded Lua</strong> and the project
-aims to offer the full set of features of the <a href="http://www.lua.org">Lua Programming Language</a> to the embedded world. </p><p><span style="font-weight: bold;">eLua</span>
is not a stripped down set of Lua; much on the contrary, it strives to
offer the same features as the desktop version of Lua, but complementing them with
specific features for embedded use.
Besides offering different flavors of the full Lua implementation
-(like the possiblity of choosing between an integer-only and a floating
+(like the possibility of choosing between an integer-only and a floating
point numbers implementation),
a lot of work was and will be done in the direction of making Lua
more "embedded-friendly" by augmenting the core language with features
that allow lower memory requirements.</p>
+
<p>Lua is the perfect example of a
minimal, yet fully
functional language. Although generally advertised as a "scripting
language" (and used accordingly especially in the game industry), it is
-also fully capable of running stand-alone programs. Its limited
+also fully capable of running stand-alone programs. (ex: Adobe Lightroom, World of Warcraft,
+...). Its limited
resource requirements make it suitable to a lot of microcontroller
families. The intrinsic high portability of the original Lua code
(which is ANSI C and runs virtually on every platform for which an ANSI
C compiler is available) combined with the highly portable software
architecture of <b>eLua</b> allow for easy porting of the project to a large variety or architectures. The peripheral access libraries exported by <b>eLua</b> are also portable by design, so one could run a Lua program (without or with very few modifications) on every <span style="font-weight: bold;">eLua</span> supported platform (the <a href="status.html">project status & roadmap</a> shows a constantly growing list of platforms on which <b>eLua</b> is supported). <b>eLua</b> inherits the minimalistic and functional design of Lua, staying in line with the well known <b>KISS</b>, <i>Keep It Small and Simple</i> philosophy.</p>
+
<p>The aim of the project is to have a fully functional Lua development
environment <strong>on the microcontroller itself</strong>,
-without the need to install a specific development environment on
-the PC side. This includes the ability to both edit and debug programs
-directly on target.
-Initially, a PC will still be needed in order to edit the Lua programs
-for the microcontroller. But as the project evolves this requirement
-will be relaxed, as a basic editor (also residing on the
-microcontroller) will be usable with a variety of input/output devices.</p>
-<p>We can't end this short presentation without presenting our project motto: No matter what you do with <b>eLua</b>, always remember to have fun with it :)</p>
+without the need to install a specific development environment on
+the PC side, other than a serial or ehternet console/terminal emulator.</p>
+<p>We can't end this short presentation without presenting our project motto: No matter what you do with <b>eLua</b>, always remember to have
+Fun with it :)</p>
+<br />
+<br />
<a name="features"></a><h3>Features</h3>
<p>As already stated, <b>eLua</b> allows you to run Lua completely on
the
target microcontroller. A fast-growing set of complementary modules is also
-provided, for programming <strong>eLua</strong>'s peripherals. </p>
+provided, for programming <strong>eLua</strong> microcontroller's peripherals. </p>
<p>The following important features are ready or being implemented:</p>
<ul>
-<li>a flexible, configurable build system.</li>
-<li>access to the Lua interpreter on the target MCU via a variety of physical transports (RS-232 being the most popular).</li>
-<li>a (mostly) platform independent peripheral library (PIO,
-UART, PWM, SPI, TMR, ADC, NET, I2C...)</li>
-<li>a very low footprint embedded ROM file system, easy to port to different types of memory chips and other storage devices</li>
-<li>a small FAT R/W file system layer for SD cards</li>
-<li>an embedded editor, to edit Lua programs directly via a serial connection or other input devices</li>
-<li>a minimal "shell" (for file operations, environment configuration and other facilities)</li>
-<li>network support</li>
-<li>an embedded http server</li>
-<li>Terminal / Console over Ethernet</li>
-<li>debugging (directly on the MCU or remotely with the PC).
-</li></ul>
+ <li>a flexible, configurable build system.</li>
+ <li>access to the Lua interpreter on the target MCU via a variety of physical transports (RS-232 being the most popular).</li>
+ <li>a (mostly) platform independent peripheral library (PIO,
+ UART, PWM, SPI, TMR, ADC, NET, I2C...)</li>
+ <li>a very low footprint embedded ROM file system, easy to port to different types of memory chips and other storage devices</li>
+ <li>a small FAT R/W file system layer for SD cards</li>
+ <li>a minimal "shell" (for file operations, environment configuration and other facilities)</li>
+ <li>network support</li>
+ <li>an embedded http server</li>
+ <li>Terminal / Console over Ethernet</li>
+ <li>debugging (directly on the MCU or remotely with the PC).</li>
+</ul>
<p>For more information about the functionality (implemented and planned) in <strong>eLua</strong> check <a href="status.html">the status page</a>.</p>
<p>Porting <strong>eLua</strong> to another compatible platform should be as easy
and
@@ -73,6 +69,8 @@
while "integer Lua" will only be able to perform operations with
integer numbers (but support for fixed and even floating point can be
added with separate modules) and thus will be faster.</p>
+<br />
+<br />
<a name="audience"></a><h3>Audience</h3>
<p><span style="font-weight: bold;">eLua</span> has a wide and varied audience, starting from newcomers to the embedded world who want an
easy and powerful environment for prototyping, rapid application
@@ -87,39 +85,61 @@
configuration and data registers, as the platform libraries already
take care of this. This increases productivity and eliminates the often
frustrating task of dealing with platform-specific drivers. </p>
-<p>The list below summarizes <b>eLua</b>'s target audience:<br></p><ul><li>Embedded developers that are looking for a fast, easy to use and powerful way of coding.</li><li>First-time
-embedded programmers (or simply first time programmers) that are
+<p>The list below summarizes <b>eLua</b>'s target audience:</p>
+<ul>
+ <li>Embedded developers that are looking for a fast, easy to use and powerful way of coding.</li>
+ <li>First-time
+embedded programmers (or simply first time programmers) who are
looking for an easy way to "dive" into the embedded programming world.
-eLua is a great learning tool.</li><li>People that aren't really
-developers, but want to be able to prototype an embedded system
-fast and painless, without having to learn C for that.</li><li>Embedded
+eLua is a great learning tool.</li>
+ <li>People that aren't really
+developers, but still want to be able to prototype an embedded system
+fast and painless, without having to learn C for that.</li>
+ <li>Embedded
developers who need powerful meta-language mechanisms for complex code
-algorithms and data description.</li><li>Field
+algorithms and data description.</li>
+ <li>Field
engineers that can go to their customer site and debug an eLua module on
site, without any preparation at all, since the whole development
-environment resides on chip already.</li></ul><a name="authors"></a>
-<h3>Authors</h3>
+environment resides on chip already.</li>
+</ul>
+<br />
+<br />
+<a name="authors" /><h3>Authors</h3>
<p><strong>eLua</strong> is a joint project of <strong><a href="#contacts">Bogdan Marinescu</a></strong>,
-a software developer from Bucharest (Romania) and <strong><a href="#contacts">Dado Sutter</a></strong>,
-head of the Led Lab at <a href="http://www.puc-rio.br/">PUC-Rio
-University</a>, in Rio de Janeiro (Brazil). </p>
+a software developer from Bucharest, Romania and <strong><a href="#contacts">Dado Sutter</a></strong>,
+head of the Led Lab at <a href="http://www.puc-rio.br/">PUC-Rio University</a>, in Rio de Janeiro (Brazil). </p>
<p>Its origins come from the <a href="http://www.circuitcellar.com/renesas2005m16c/winners/1685.htm">ReVaLuaTe</a>
project also developed by Bogdan Marinescu (as a contest entry for the
-2005 Renesas M16CDesign Contest), and the Volta Project, managed by
+2005 Renesas M16C Design Contest), and the Volta Project, managed by
Dado Sutter at PUC-Rio from 2005 to 2007.</p>
-<p><strong>eLua</strong> is Open Source and an always growing list of collaborators can be found in our <a href="#credits">Credits Page</a></p>
-<div style="text-align: center;"><span style="font-weight: bold;"></span><br><span style="font-weight: bold;"></span></div><table style="width: 578px; height: 256px; text-align: left; margin-left: auto; margin-right: auto;" border="1" cellpadding="2" cellspacing="2"><tbody><tr><td style="text-align: center; font-family: Verdana; font-weight: bold;" valign="undefined"><big>ReVaLuaTe Project</big></td><td style="text-align: center; font-family: Verdana; font-weight: bold;" valign="undefined"><big>Volta Project</big></td></tr><tr><td style="text-align: center;" valign="undefined"><img style="width: 278px; height: 188px;" alt="ReVaLuaTe project picture" src="../wb_img/terminalreneseas.jpg"></td><td style="text-align: center;" valign="undefined"><img style="width: 278px; height: 209px;" alt="Volta project picture" src="../wb_img/volta-small.jpg"></td></tr></tbody></table><div style="text-align: center;"><span style="font-weight: bold;"></span><br><span style="font-weight: bold;"!
></span><br><span style="font-weight: bold;"></span><br><span style="font-weight: bold;"></span></div><a name="contacts"></a>
-<h3>Contacts</h3>
+<p><strong>eLua</strong> is Open Source and an always growing list of collaborators can be found in our <a
+href="en_comunity.html#credits">Credits Page</a></p>
+<br />
+<table style="width: 578px; height: 256px; text-align: left; margin-left: auto; margin-right: auto;" border="1" cellpadding="2" cellspacing="2">
+<tbody>
+<tr>
+ <td style="text-align: center; font-family: Verdana; font-weight: bold;"><big>ReVaLuaTe Project</big></td>
+ <td style="text-align: center; font-family: Verdana; font-weight: bold;"><big>Volta Project</big></td>
+</tr>
+<tr>
+ <td style="text-align: center;"><img style="width: 278px; height: 188px;" alt="ReVaLuaTe project picture" src="images/terminalreneseas.jpg" /></td>
+ <td style="text-align: center;"><img style="width: 278px; height: 209px;" alt="Volta project picture" src="images/volta-small.jpg" /></td>
+</tr>
+</tbody>
+</table>
+<br />
+<br />
+<br />
+<a name="contacts" /><h3>Contacts</h3>
<p><strong>eLua</strong> authors can be contacted at:</p><p><strong>Bogdan Marinescu:</strong> bogdan.marinescu -at- gmail.com</p>
-
<p><strong>Dado Sutter:</strong> dadosutter -at- gmail.com</p><p>You are also welcomed to share your questions and suggestions on our <a href="comunity.html#lists">Mail Discussion List</a></p>
-<a name="license"></a>
-<h3>License</h3>
-<div class="content">
+<br />
+<br />
+<a name="license" /><h3>License</h3>
<p><strong>eLua</strong> is Open Source and is freely
distributed under the MIT licence.</p>
-<p>The Lua code (with all the <b>eLua</b> specific changes) is included in the source tree and is, of course, licensed under the same <a href="http://en.wikipedia.org/wiki/MIT_License">MIT license that Lua uses.</p>
-<p>There may be other components with different licenses in <b>eLua</b>, see <b>COPYING</b> in the source distribution for details.</p>
-</a></p><br><p></p><p></p><p></p><p></p><p></p><p></p><p></p><p></p><p></p><p></p><p></p><p></p><p></p><p></p><p></p><p></p><p></p>
-</div>
-</body></html>
+<p>The Lua code (with all the <strong>eLua</strong> specific changes) is included in the source tree and is, of course, licensed under the same <a href="http://en.wikipedia.org/wiki/MIT_License">MIT license that Lua uses.</a></p>
+<p>There may be other components with different licenses in <strong>eLua</strong>, see <strong>COPYING</strong> in the source distribution for details.</p>
+$$FOOTER$$
+
Modified: branches/eagle_mmc/doc/en/refman.html
===================================================================
--- branches/eagle_mmc/doc/en/refman.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/en/refman.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,9 +1,9 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8"/>
<meta http-equiv="Content-Language" content="en-us"><title>eLua reference manual</title>
-<link rel="stylesheet" type="text/css" href="../style.css"></head>
+<link rel="stylesheet" type="text/css" href="../style.css"></link></head>
<body style="background-color: rgb(255, 255, 255);">
<h3>The reference manual</h3>
<p>The <b>eLua</b> reference manual presents in details all the modules that can be used from a Lua program running inside <b>eLua</b>. It doesn't cover the
@@ -13,7 +13,7 @@
in this section:
<ul>
<li><b>generic modules</b>: they are available on all platforms and should behave the same on all platforms.</li>
- <li><b>platform-depedent modules</b>: they can be found only on specific platforms. Using them sacrifices portability, but gives access to platform
+ <li><b>platform-dependent modules</b>: they can be found only on specific platforms. Using them sacrifices portability, but gives access to platform
internals that aren't covered by the generic modules (for example specific hardware features).</b>
</ul></p>
<p>Remember that in order to use a module (generic or not) in <b>eLua</b> you must first include it in your <b>eLua</b> binary image, check
Added: branches/eagle_mmc/doc/en/refman_dep.html
===================================================================
--- branches/eagle_mmc/doc/en/refman_dep.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/en/refman_dep.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,6 @@
+$$HEADER$$
+<h3>Reference manual - platform dependent modules</h3>
+<p>This part of the reference manual presents the platform specifics in <b>eLua</b> (see <a href="arch_overview.html">here</a> for more information about platform
+specific modules).</p>
+$$FOOTER$$
+
Modified: branches/eagle_mmc/doc/en/refman_gen.html
===================================================================
--- branches/eagle_mmc/doc/en/refman_gen.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/en/refman_gen.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,11 +1,6 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>eLua reference manual - generic modules</title>
-
-<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);">
+$$HEADER$$
<h3>Reference manual - generic modules</h3>
-<p>This part of the reference manual presents the generic modules in <b>eLua</b> (see <a href="refman.html">here</a> for more information about generic
+<p>This part of the reference manual presents the generic modules in <b>eLua</b> (see <a href="arch_overview.html">here</a> for more information about generic
modules).</p>
-</body></html>
+$$FOOTER$$
+
Modified: branches/eagle_mmc/doc/en/status.html
===================================================================
--- branches/eagle_mmc/doc/en/status.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/en/status.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,43 +1,37 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
-
-<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);">
-<a name="platforms"></a><h3>eLua platforms and modules status</h3>
+$$HEADER$$
+<a name="platforms" /><h3>eLua platforms and modules status</h3>
<p>The current status of <b>eLua</b> is given by the list of the
currently supported platforms, together with a list of
modules-per-platform and their development phase. For better
formatting, the lists are organized as tables that use the graphical
-notation given below:
-</p><table style="width: 325px;" class="table_center">
+notation given below:</p>
+<table style="width: 325px;" class="table_center">
<tbody>
<tr>
<th style="text-align: center;">Symbol</th>
<th style="text-align: center;">Meaning</th>
</tr>
<tr>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
<td style="text-align: left;">Implemented and tested</td>
</tr>
<tr>
-<td style="text-align: center;"><img src="../wb_img/stat_not_tested.png"></td>
+<td style="text-align: center;"><img src="images/stat_not_tested.png" alt="Status: not tested" /></td>
<td style="text-align: left;">Implemented, not tested</td>
</tr>
<tr>
-<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
<td style="text-align: left;">Not yet implemented</td>
</tr>
<tr>
-<td style="text-align: center;"><img src="../wb_img/stat_not_applicable.png"></td>
+<td style="text-align: center;"><img src="images/stat_not_applicable.png" alt="Status: not applicable" /></td>
<td style="text-align: left;">Not applicable</td>
</tr>
</tbody>
</table>
-<br>
-<p>The list of CPUs/boards currently supported by <b>eLua</b> is given below:
-</p><table style="text-align: left; width: 620px;" class="table_center">
+
+<p>The list of CPUs/boards currently supported by <b>eLua</b> is given below:</p>
+<table style="text-align: left; width: 620px;" class="table_center">
<tbody>
<tr>
<th style="text-align: left;">CPU</th>
@@ -47,94 +41,95 @@
<th style="text-align: center;">Status</th>
</tr>
<tr>
- <td><a target="_blank" href="http://www.luminarymicro.com/products/LM3S8962.html">LM3S8962</a></td>
+ <td><a href="http://www.luminarymicro.com/products/LM3S8962.html">LM3S8962</a></td>
<td>Cortex-M3</td>
<td style="color: rgb(255, 102, 0);">lm3s</td>
- <td><a target="_blank" href="http://www.luminarymicro.com/products/lm3s8962_can_ethernet_evaluation_kit.html">EKx-LM3S8962</a></td>
- <td><img src="../wb_img/stat_ok.png"></td>
+ <td><a href="http://www.luminarymicro.com/products/lm3s8962_can_ethernet_evaluation_kit.html">EKx-LM3S8962</a></td>
+ <td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
</tr>
<tr>
- <td><a target="_blank" href="http://www.luminarymicro.com/products/lm3s6965.html">LM3S6965</a></td>
+ <td><a href="http://www.luminarymicro.com/products/lm3s6965.html">LM3S6965</a></td>
<td>Cortex-M3</td>
<td style="color: rgb(255, 102, 0);">lm3s</td>
- <td><a target="_blank" href="http://www.luminarymicro.com/products/lm3s6965_ethernet_evaluation_kit.html">EKx-LM3S6965</a></td>
- <td><img src="../wb_img/stat_ok.png"></td>
+ <td><a href="http://www.luminarymicro.com/products/lm3s6965_ethernet_evaluation_kit.html">EKx-LM3S6965</a></td>
+ <td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
</tr>
<tr>
- <td><a target="_blank" href="http://www.luminarymicro.com/products/lm3s6918.html">LM3S6918</a></td>
+ <td><a href="http://www.luminarymicro.com/products/lm3s6918.html">LM3S6918</a></td>
<td>Cortex-M3</td>
<td style="color: rgb(255, 102, 0);">lm3s</td>
- <td><a target="_blank" href="http://www.micromint.com/index.php/products/by-family/sbcs/77">Eagle 100</a></td>
- <td><img src="../wb_img/stat_ok.png"></td>
+ <td><a href="http://www.micromint.com/index.php/SBC/eagle-100.html">Eagle 100</a></td>
+ <td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
</tr>
<tr>
- <td><a target="_blank" href="http://www.atmel.com/dyn/products/Product_card.asp?part_id=3755">AT91SAM7X256</a></td>
+ <td><a href="http://www.atmel.com/dyn/products/Product_card.asp?part_id=3755">AT91SAM7X256</a></td>
<td>ARM7TDMI</td>
<td style="color: rgb(255, 102, 0);">at91sam7x</td>
- <td><a target="_blank" href="http://www.olimex.com/dev/sam7-ex256.html">SAM7-EX256</a></td>
- <td><img src="../wb_img/stat_ok.png"></td>
+ <td><a href="http://www.olimex.com/dev/sam7-ex256.html">SAM7-EX256</a></td>
+ <td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
</tr>
<tr>
- <td><a target="_blank" href="http://www.atmel.com/dyn/products/Product_card.asp?part_id=4104">AT91SAM7X512</a></td>
+ <td><a href="http://www.atmel.com/dyn/products/Product_card.asp?part_id=4104">AT91SAM7X512</a></td>
<td>ARM7TDMI</td>
<td style="color: rgb(255, 102, 0);">at91sam7x</td>
<td>None</td>
- <td><img src="../wb_img/stat_not_tested.png"></td>
+ <td style="text-align: center;"><img src="images/stat_not_tested.png" alt="Status: not tested" /></td>
</tr>
<tr>
- <td><a target="_blank" href="http://www.intel.com">i386 (generic)</a></td>
+ <td><a href="http://www.intel.com">i386 (generic)</a></td>
<td>x86</td>
<td style="color: rgb(255, 102, 0);">i386</td>
<td>PCs/emulators</td>
- <td><img src="../wb_img/stat_ok.png"></td>
+ <td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
</tr>
<tr>
- <td><a target="_blank" href="http://www.st.com/mcu/devicedocs-STR912FAW44-101.html">STR912FAW44</a></td>
+ <td><a href="http://www.st.com/mcu/devicedocs-STR912FAW44-101.html">STR912FAW44</a></td>
<td>ARM966E-S</td>
<td style="color: rgb(255, 102, 0);">str9</td>
- <td><a target="_blank" href="http://www.hitex.com/index.php?id=383">STR9-comStick</a></td>
- <td><img src="../wb_img/stat_ok.png"></td>
+ <td><a href="http://www.hitex.com/index.php?id=383">STR9-comStick</a>
+ <a href="http://www.olimex.com/dev/str-e912.html">STR-E912</a></td>
+ <td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
</tr>
<tr>
- <td><a target="_blank" href="http://www.standardics.nxp.com/microcontrollers/to/pip/LPC2880FET180.html">LPC2888</a></td>
+ <td><a href="http://www.standardics.nxp.com/microcontrollers/to/pip/LPC2880FET180.html">LPC2888</a></td>
<td>ARM7TDMI</td>
<td style="color: rgb(255, 102, 0);">lpc288x</td>
- <td><a target="_blank" href="http://www.olimex.com/dev/lpc-h2888.html">LPC-H2888</a></td>
- <td><img src="../wb_img/stat_ok.png"></td>
+ <td><a href="http://www.olimex.com/dev/lpc-h2888.html">LPC-H2888</a></td>
+ <td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
</tr>
<tr>
- <td><a target="_blank" href="http://www.st.com/mcu/devicedocs-STR711FR2.html">STR711FR2</a></td>
+ <td><a href="http://www.st.com/mcu/devicedocs-STR711FR2.html">STR711FR2</a></td>
<td>ARM7TDMI</td>
<td style="color: rgb(255, 102, 0);">str7</td>
- <td><a target="_blank" href="http://www.sctec.com.br/content/view/101/30/">MOD711</a></td>
- <td><img src="../wb_img/stat_ok.png"></td>
+ <td><a href="http://www.sctec.com.br/content/view/101/30/">MOD711</a></td>
+ <td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
</tr>
<tr>
- <td><a target="_blank" href="http://www.atmel.com/dyn/products/product_card.asp?part_id=4117">AT32UC3A0512</a></td>
+ <td><a href="http://www.atmel.com/dyn/products/product_card.asp?part_id=4117">AT32UC3A0512</a></td>
<td>AVR32</td>
<td style="color: rgb(255, 102, 0);">avr32</td>
- <td><a target="_blank" href="http://www.atmel.com/dyn/Products/tools_card.asp?tool_id=4114">ATEVK1100</a></td>
- <td><img src="../wb_img/stat_ok.png"></td>
+ <td><a href="http://www.atmel.com/dyn/Products/tools_card.asp?tool_id=4114">ATEVK1100</a></td>
+ <td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
</tr>
<tr>
- <td><a target="_blank" href="http://http://www.st.com/mcu/devicedocs-STM32F103ZE-110.html">STM32F103ZE</a></td>
+ <td><a href="http://www.st.com/mcu/devicedocs-STM32F103ZE-110.html">STM32F103ZE</a></td>
<td>Cortex-M3</td>
<td style="color: rgb(255, 102, 0);">stm32</td>
- <td><a target="_blank" href="http://www.st.com/mcu/contentid-100-110-STM3210E_EVAL.html">STM3210E-EVAL</a></td>
- <td><img src="../wb_img/stat_ok.png"></td>
+ <td><a href="http://www.st.com/mcu/contentid-100-110-STM3210E_EVAL.html">STM3210E-EVAL</a></td>
+ <td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
</tr>
<tr>
- <td><a target="_blank" href="http://www.st.com/mcu/devicedocs-STM32F103RE-110.html">STM32F103RE</a></td>
+ <td><a href="http://www.st.com/mcu/devicedocs-STM32F103RE-110.html">STM32F103RE</a></td>
<td>Cortex-M3</td>
<td style="color: rgb(255, 102, 0);">stm32</td>
- <td><a target="_blank" href="http://www.futurlec.com/ET-STM32_Stamp.shtml">ET-STM32 Stamp</a></td>
- <td><img src="../wb_img/stat_ok.png"></td>
+ <td><a href="http://www.futurlec.com/ET-STM32_Stamp.shtml">ET-STM32 Stamp</a></td>
+ <td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
</tr>
</tbody>
</table>
-<br>
-<p>The following table shows a list of the generic modules currently implemented (and planned to be implemented) in <b>eLua</b>.
-</p><table style="text-align: left; width: 620px;" class="table_center">
+
+<p>The following table shows a list of the generic modules currently implemented (and planned to be implemented) in <b>eLua</b>.</p>
+<table style="text-align: left; width: 620px;" class="table_center">
<tbody>
<tr>
<th style="text-align: left;">Name</th>
@@ -144,91 +139,91 @@
<tr>
<td style="color: rgb(255, 102, 0);">pio</td>
<td>Programmable Input/Output</td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
</tr>
<tr>
<td style="color: rgb(255, 102, 0);">tmr</td>
<td>timers</td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
</tr>
<tr>
<td style="color: rgb(255, 102, 0);">pwm</td>
<td>Pulse Width Modulation</td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
</tr>
<tr>
<td style="color: rgb(255, 102, 0);">uart</td>
<td>Universal Asynchronous Receiver Transmitter</td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
</tr>
<tr>
<td style="color: rgb(255, 102, 0);">spi</td>
<td>Serial Peripheral Interface</td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
</tr>
<tr><td style="color: rgb(255, 102, 0);">net</td>
<td>TCP/IP networking</td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
</tr>
<tr>
<td style="color: rgb(255, 102, 0);">adc</td>
<td>Analog to Digital Converter</td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
</tr>
<tr>
<td style="color: rgb(255, 102, 0);">cpu</td>
<td>low level system access</td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
</tr>
<tr>
<td style="color: rgb(255, 102, 0);">pd</td>
<td>platform data</td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
</tr>
<tr>
<td style="color: rgb(255, 102, 0);">term</td>
<td>ANSI terminal access</td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
</tr>
<tr>
<td style="color: rgb(255, 102, 0);">bit</td>
<td>bitwise operations</td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
</tr>
<tr>
<td style="color: rgb(255, 102, 0);">pack</td>
<td>pack/unpack binary data</td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
</tr>
<tr>
<td style="color: rgb(255, 102, 0);">cmp</td>
<td>analog comparator</td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
</tr>
<tr>
<td style="color: rgb(255, 102, 0);">i2c</td>
<td>I2C bus access module</td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
</tr>
<tr>
<td style="color: rgb(255, 102, 0);">cnt</td>
<td>event counter</td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
</tr>
<tr>
<td style="color: rgb(255, 102, 0);">can</td>
<td>Controller Area Network</td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_tested.png"></td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
</tr>
<td style="color: rgb(255, 102, 0);">rpc</td>
<td>remote procedure call / remote control</td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_tested.png"></td>
+<td style="text-align: center;"><img src="images/stat_not_tested.png" alt="Status: not tested" /></td>
</tr>
</tbody>
</table>
-<br>
-<p>The relationship between a module and its implementation on a particular platform is given in the next table.
-</p><table style="text-align: left; width: 620px;" class="table_center">
+
+<p>The relationship between a module and its implementation on a particular platform is given in the next table.</p>
+<table style="text-align: left; width: 620px;" class="table_center">
<tbody>
<tr>
<th>Module</th>
@@ -249,211 +244,218 @@
<tr><td style="color: rgb(255, 102, 0);">MCU</td>
</tr><tr>
<td style="color: rgb(255, 102, 0);">LM3S8962</td>
-<td style="text-align: center;"><img style="width: 16px; height: 16px;" alt="Implemented" src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img style="width: 16px; height: 16px;" alt="Not Tested" src="../wb_img/stat_not_tested.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_tested.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
+<td style="text-align: center;"><img style="width: 16px; height: 16px;" src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img style="width: 16px; height: 16px;" src="images/stat_not_tested.png" alt="Status: not tested" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_not_tested.png" alt="Status: not tested" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
</tr>
<tr>
<td style="color: rgb(255, 102, 0);">LM3S6965</td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_tested.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_tested.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_tested.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_applicable.png"></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_not_tested.png" alt="Status: not tested" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_not_tested.png" alt="Status: not tested" /></td>
+<td style="text-align: center;"><img src="images/stat_not_tested.png" alt="Status: not tested" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_not_applicable.png" alt="Status: not applicable" /></td>
</tr>
<tr>
<td style="color: rgb(255, 102, 0);">LM3S6918</td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_tested.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_applicable.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_tested.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_tested.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_applicable.png"></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_not_tested.png" alt="Status: not tested" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_not_applicable.png" alt="Status: not applicable" /></td>
+<td style="text-align: center;"><img src="images/stat_not_tested.png" alt="Status: not tested" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_not_tested.png" alt="Status: not tested" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_not_applicable.png" alt="Status: not applicable" /></td>
</tr>
<tr>
<td style="color: rgb(255, 102, 0);">i386</td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_applicable.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_applicable.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_applicable.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
-<td style="text-align: center;"><img style="height: 16px; width: 16px;" alt="Not Implemented" src="../wb_img/stat_not_applicable.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
-<td style="text-align: center;"><img style="height: 16px; width: 16px;" alt="Not Implemented" src="../wb_img/stat_not_applicable.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_applicable.png"></td>
+<td style="text-align: center;"><img src="images/stat_not_applicable.png" alt="Status: not applicable" /></td>
+<td style="text-align: center;"><img src="images/stat_not_applicable.png" alt="Status: not applicable" /></td>
+<td style="text-align: center;"><img src="images/stat_not_applicable.png" alt="Status: not applicable" /></td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img style="height: 16px; width: 16px;" src="images/stat_not_applicable.png" alt="Status: not applicable" /></td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img style="height: 16px; width: 16px;" src="images/stat_not_applicable.png" alt="Status: not applicable" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img src="images/stat_not_applicable.png" alt="Status: not applicable" /></td>
</tr>
<tr>
<td style="color: rgb(255, 102, 0);">AT91SAM7X256</td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
</tr>
<tr>
<td style="color: rgb(255, 102, 0);">AT91SAM7X512</td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_tested.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_tested.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_tested.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_tested.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;" valign="undefined"><img src="../wb_img/stat_not_implemented.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
+<td style="text-align: center;"><img src="images/stat_not_tested.png" alt="Status: not tested" /></td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img src="images/stat_not_tested.png" alt="Status: not tested" /></td>
+<td style="text-align: center;"><img src="images/stat_not_tested.png" alt="Status: not tested" /></td>
+<td style="text-align: center;"><img src="images/stat_not_tested.png" alt="Status: not tested" /></td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;" ><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+
</tr>
<tr>
<td style="color: rgb(255, 102, 0);">STR912FAW44</td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;" valign="undefined"><img src="../wb_img/stat_not_implemented.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;" ><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+
</tr>
<tr>
<td style="color: rgb(255, 102, 0);">LPC2888</td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_applicable.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;" valign="undefined"><img src="../wb_img/stat_not_implemented.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_applicable.png"></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_not_applicable.png" alt="Status: not applicable" /></td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;" ><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_not_applicable.png" alt="Status: not applicable" /></td>
+
</tr>
<tr>
<td style="color: rgb(255, 102, 0);">STR711FR2</td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"> </td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"> </td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_tested.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_applicable.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"> </td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_applicable.png"></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /> </td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /> </td>
+<td style="text-align: center;"><img src="images/stat_not_tested.png" alt="Status: not tested" /></td>
+<td style="text-align: center;"><img src="images/stat_not_applicable.png" alt="Status: not applicable" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /> </td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_not_applicable.png" alt="Status: not applicable" /></td>
+
</tr>
<tr>
<td style="color: rgb(255, 102, 0);">AT32UC3A0512</td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"> </td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"> </td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"> </td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_applicable.png"></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /> </td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /> </td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /> </td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_not_applicable.png" alt="Status: not applicable" /></td>
+
</tr>
-<tr><td style="color: rgb(255, 102, 0);">##STM32F103ZE</td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_tested.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"> </td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"> </td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"> </td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
+<tr><td style="color: rgb(255, 102, 0);">STM32F103ZE</td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /> </td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /> </td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /> </td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+
</tr>
-<tr><td style="color: rgb(255, 102, 0);">##STM32F103RE</td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"> </td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"> </td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"> </td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_tested.png"></td>
+<tr><td style="color: rgb(255, 102, 0);">STM32F103RE</td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /> </td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /> </td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /> </td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_not_tested.png" alt="Status: not tested" /></td>
+
</tr>
</tbody>
</table>
-<br>
+
<p>For some platforms, a number of platform dependent modules are
implemented (or in the works) and are listed below. To understand the
difference between generic modules and platform specific modules, check
-<a href="">##the eLua architecture page</a>.
-</p><table style="width: 620px;" class="table_center">
+<a href="arch_overview.html">the eLua architecture page</a>.</p>
+<table style="width: 620px; margin-bottom: 10px;" class="table_center">
<tbody>
<tr>
<th style="text-align: left;">Name</th>
@@ -465,87 +467,88 @@
<td style="color: rgb(255, 102, 0);">disp</td>
<td>OLED display support</td>
<td>EKx-LM3S8962<br>EKx-LM3S6965</td>
- <td><img src="../wb_img/stat_ok.png"></td>
+ <td><img src="images/stat_ok.png" alt="Status: OK" /></td>
</tr>
</tbody>
</table>
-<h3><a name="roadmap"></a>Status of features and roadmap</h3>
-<p>The following table shows the status of some existing and planned <b>eLua</b> features.
-</p><table style="text-align: left; width: 620px;" class="table_center">
+<a name="roadmap" /><h3>Status of features and roadmap</h3>
+<p>The following table shows the status of some existing and planned <b>eLua</b> features.</p>
+<table style="text-align: left; width: 620px;" class="table_center">
<tbody><tr>
<th style="text-align: left;">eLua Features</th>
<th style="text-align: center;">Status</th>
</tr>
<tr>
<td style="text-align: left;">Full Lua interpreter running on target</td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
</tr>
<tr>
<td>Various Lua examples running properly</td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
</tr>
<tr>
<td style="text-align: left;">Choose floating point or integer Lua</td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
</tr>
<tr>
<td style="text-align: left;">XMODEM transfer over UART</td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
</tr>
<tr>
<td style="text-align: left;">Embedded ROM (Flash) file system</td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
</tr>
<tr>
-<td style="text-align: left;">Terminal / Console over UART or Ethernet</td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: left;">Terminal / Console over UART and Ethernet</td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
</tr>
<tr>
<td style="text-align: left;">eLua command shell</td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
</tr>
<tr>
<td style="text-align: left;">eLua complete interrupt support</td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
</tr>
<tr>
<td style="text-align: left;"><a href="arch_ltr.html">eLua LTR (Lua Tiny RAM) patch</a></td>
-<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
</tr>
<tr>
<td style="text-align: left;">FAT File System layer for mmc/sd cards</td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_tested.png"></td>
+<td style="text-align: center;"><img src="images/stat_not_tested.png" alt="Status: not tested" /></td>
</tr>
<tr>
<td style="text-align: left;">Minimal R/W file system</td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
</tr>
<tr>
<td style="text-align: left;">eLua FP module (for integer Lua)</td>
-<td style="color: rgb(255, 102, 0); text-align: center;"><img src="../wb_img/stat_not_implemented.png">
+<td style="color: rgb(255, 102, 0); text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" />
</td>
</tr>
<tr>
<td style="text-align: left;">Embedded text editor</td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
</tr>
<tr>
<td style="text-align: left;">Lua debugging (remote/on target)</td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
</tr>
<tr>
<td style="text-align: left;">GUI/IDE interface for eLua</td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
</tr>
<tr>
<td style="text-align: left;">GUI eLua build configuration tool<br></td>
-<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
</tr>
<tr>
-<td align="undefined" valign="undefined">Embedded HTTP web server</td>
-<td style="text-align: center;" valign="undefined"><img src="../wb_img/stat_ok.png"></td></tr>
+<td style="text-align: left;" >Embedded HTTP web server</td>
+<td style="text-align: center;" ><img src="images/stat_ok.png" alt="Status: OK" /></td></tr>
</tbody>
-</table><br><br>
+</table>
-</body></html>
+$$FOOTER$$
+
Modified: branches/eagle_mmc/doc/en/tc_386.html
===================================================================
--- branches/eagle_mmc/doc/en/tc_386.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/en/tc_386.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,53 +1,48 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Building GCC for i386</title>
-
-<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);">
+$$HEADER$$
<h3>Building GCC for i386</h3>
<p>At first, the idea of an i386 "cross" compiler under Linux seems
strange. After all, you're already running Linux on a i386 compatible
-architecture. But the compiler is sometimes tied in misterious ways
-with the operating system it's running on (see for example <a htarget="_blank" ref="http://wiki.osdev.org/GCC_Cross-Compiler">this page</a>
+architecture. But the compiler is sometimes tied in mysterious ways
+with the operating system it's running on (see for example <a href="http://wiki.osdev.org/GCC_Cross-Compiler">this page</a>
for some possible symptoms). And after all, you want to use Newlib, not
libc, and to customize your development environment as much as
possible. This tutorial will show you how to do that.</p>
-<p><strong>DISCLAIMER: I'm by no means a specialist in the
+<p><span class="warning">DISCLAIMER</span>: I'm by no means a specialist in the
GCC/newlib/binutils compilation process. I'm sure that there are better
ways to accomplish what I'm describing here, however I just wanted a
quick and dirty way to build a toolchain, I have no intention in
becoming too intimate with the build process. If you think that what I
-did is wrong, innacurate, or simply outrageously ugly, feel free to
+did is wrong, inaccurate, or simply outrageously ugly, feel free to
<a href="overview.html#contacts">contact us</a> and I'll make the necessary corrections.
-And of course, this tutorial comes without any guarantees whatsoever.</strong></p>
+And of course, this tutorial comes without any guarantees whatsoever.</p>
<h2>Prerequisites</h2>
<p>To build your toolchain you'll need:</p>
<ul>
<li><b>GNU binutils</b>: as I'm writing this, the latest binutils version is 2.19.1, which
-I'll be using in this tutorial. get it from <a target="_blank" href="http://ftp.gnu.org/gnu/binutils/">here</a>.</li>
+I'll be using in this tutorial. get it from <a href="http://ftp.gnu.org/gnu/binutils/">here</a>.</li>
<li><b>GCC</b>:as I'm writing this, the latest GCC version is
-4.3.3, which I'll be using for this tutorial. Download it from <a target="_blank" href="http://gcc.gnu.org/mirrors.html">here</a> after choosing a suitable mirror.</li>
+4.3.3, which I'll be using for this tutorial. Download it from <a href="http://gcc.gnu.org/mirrors.html">here</a> after choosing a suitable mirror.</li>
<li><b>Newlib</b>: as I'm writing this, the latest official Newlib version is 1.17.0, which I'll be using for this tutorial.
-Download it from <a target="_blank" href="ftp://sources.redhat.com/pub/newlib/index.html">here</a>.</li>
+Download it from <a href="ftp://sources.redhat.com/pub/newlib/index.html">here</a>.</li>
<li>The tutorial assumes that you're using bash as your shell. If you use
-something else, you might need to adjust some shell-specific commands. </li></ul></p>
+something else, you might need to adjust some shell-specific commands. </li></ul>
+
<p>You need some support programs/libraries in order to compile the toolchain. To install them:</p>
-<p><pre><code>$ sudo apt-get install flex bison libgmp3-dev libmpfr-dev autoconf texinfo build-essential</code></pre></p>
+<pre><code>$ sudo apt-get install flex bison libgmp3-dev libmpfr-dev autoconf texinfo build-essential</code></pre>
<p>Next, decide where you want to install your toolchain. They
generally go in <i>/usr/local/</i>, so I'm going to assume
<i>/usr/local/cross-i686</i> for this tutorial. To save yourself some
typing, set this path into a shell variable:</p>
-<p><pre><code>$ export TOOLPATH=/usr/local/cross-i686</code></pre></p>
+<pre><code>$ export TOOLPATH=/usr/local/cross-i686</code></pre>
-<h2>› Step 1: binutils</h2>
+<h2>Step 1: binutils</h2>
<p>This is the easiest step: unpack, configure, build.</p>
-<p><pre><code>$ tar -xvjf binutils-2.19.1.tar.bz2
+<pre><code>$ tar -xvjf binutils-2.19.1.tar.bz2
$ cd binutils-2.19.1
$ mkdir build
$ cd build
@@ -55,7 +50,7 @@
$ make all
$ sudo make install
$ export PATH=${TOOLPATH}/bin:$PATH
-$ cd ../..</code></pre></p>
+$ cd ../..</code></pre>
<p>Now you have your i386 "binutils" (assembler, linker, disassembler ...) in your PATH. </p>
@@ -64,9 +59,9 @@
<p>In this step we build a "basic" GCC (that is, a GCC without any
support libs, which we'll use in order to build all the libraries for
our target). Let's compile it (and note that the install step is
-a bit different from Newlib's):</p?
+a bit different from Newlib's):</p>
-<p><pre><code>$ tar -xvjf gcc-4.3.3.tar.bz2
+<pre><code>$ tar -xvjf gcc-4.3.3.tar.bz2
$ cd gcc-4.3.3
$ mkdir build
$ cd build
@@ -76,7 +71,7 @@
# export PATH=/usr/local/cross-i686/bin:$PATH
# make install-gcc
# exit
-$ cd ../..</code></pre></p>
+$ cd ../..</code></pre>
<h2>Step 3: Newlib</h2>
@@ -86,7 +81,7 @@
executable, so I added the "-ffunction-sections -fdata-sections" flags
to allow the linker to perform dead code stripping:</p>
-<p><pre><code>$ tar -xvzf newlib-1.17.0.tar.gz
+<pre><code>$ tar -xvzf newlib-1.17.0.tar.gz
$ cd newlib-1.17.0
$ mkdir build
$ cd build
@@ -96,17 +91,17 @@
# export PATH=/usr/local/cross-i686/bin:$PATH
# make install
# exit
-$ cd ../..</code></pre></p>
+$ cd ../..</code></pre>
-<p>Some notes about the flags used in the above sequence:
+<p>Some notes about the flags used in the above sequence:</p>
<ul>
<li><code>--disable-newlib-supplied-syscalls</code>: this deserves a page of its own, but I won't cover it here. For an explanation, see for example
- <a target="_blank" href="http://openhardware.net/Embedded_ARM/NewLib_Stubs/">this page</a></li>
+ <a href="http://openhardware.net/Embedded_ARM/NewLib_Stubs/">this page</a></li>
<li><code>-DPREFER_SIZE_OVER_SPEED -D__OPTIMIZE_SIZE__</code>: compile Newlib for size, not for speed (these are Newlib specific).</li>
<li><code>-Os -fomit-frame-pointer</code>: tell GCC to optimize for size, not for speed.</li>
<li><code>-D__BUFSIZ__=256</code>: again Newlib specific, this is the buffer size allocated by default for files opened via fopen(). The default is 1024, which I find too much
- for <b>eLua</b>, so I'm using 256 here. Of course, you can change this value.</li></ul></p>
+ for <b>eLua</b>, so I'm using 256 here. Of course, you can change this value.</li></ul>
<h2>Step 4: full GCC</h2>
@@ -115,10 +110,10 @@
(most notably libgcc.a). Fortunately this is simpler that the Newlib
compilation step:</p>
-<p><pre><code>$ cd gcc-4.3.3/build
+<pre><code>$ cd gcc-4.3.3/build
$ make all
$ sudo make install
-</code></pre></p>
+</code></pre>
<h2>Step 5: all done!</h2>
@@ -126,4 +121,4 @@
it :) After you do, you'll be able to boot <b>eLua</b> directly on your PC, as
described <a href="tut_bootpc.html">here</a>, but you won't need to download the ELF file from the <b>eLua</b> project page, since you just generated it using your own toolchain!
If you need further clarification, or if the above instructions didn't work for you, feel free to <a href="overview.html#contacts">contact us</a>.</p>
-</body></html>
+$$FOOTER$$
Modified: branches/eagle_mmc/doc/en/tc_arm.html
===================================================================
--- branches/eagle_mmc/doc/en/tc_arm.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/en/tc_arm.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,10 +1,4 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Building GCC for ARM</title>
-
-<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);">
+$$HEADER$$
<h3>Building GCC for ARM</h3>
<p> This tutorial explains how you can create a GCC+Newlib toolchain
@@ -14,16 +8,16 @@
ARM CPUs. Please note that you can also use a
pre-built toolchain to compile <b>eLua</b> (see <a href="toolchains.html">toolchains</a> for details) so building
one yourself is not strictly required. This tutorial is similar to many others you'll find on the
-Internet (particulary the one from <a target="_blank" href="http://www.gnuarm.com/">gnuarm</a>, on which it's based), but it's a bit more detailed and shows some "tricks"
+Internet (particulary the one from <a href="http://www.gnuarm.com/">gnuarm</a>, on which it's based), but it's a bit more detailed and shows some "tricks"
(specifying parameters at compile time) you can use when compiling Newlib.</p>
-<p><strong>DISCLAIMER: I'm by no means a specialist in the
+<p><span class="warning">DISCLAIMER</span>: I'm by no means a specialist in the
GCC/newlib/binutils compilation process. I'm sure that there are better
ways to accomplish what I'm describing here, however I just wanted a
quick and dirty way to build a toolchain, I have no intention in
becoming too intimate with the build process. If you think that what I
-did is wrong, innacurate, or simply outrageously ugly, feel free to <a href="overview.html#contacts">contact us</a> and
-I'll make the necessary corrections. And of course, this tutorial comes without any guarantees whatsoever.</strong></p>
+did is wrong, inaccurate, or simply outrageously ugly, feel free to <a href="overview.html#contacts">contact us</a> and
+I'll make the necessary corrections. And of course, this tutorial comes without any guarantees whatsoever.</p>
<h2>Prerequisites</h2>
<p>To build your toolchain you'll need:</p>
@@ -36,30 +30,30 @@
system already has a "basic" native toolchain installed (gcc/make and
related).This is true for Ubuntu after installation. Again, you might
need to check your specific distribution.</li>
-<li><b>GNU binutils</b>: get it from <a target="_blank" href="http://ftp.gnu.org/gnu/binutils/">here</a>.
+<li><b>GNU binutils</b>: get it from <a href="http://ftp.gnu.org/gnu/binutils/">here</a>.
At the moment of writing this, the latest versions is 2.19.1, but it refuses to compile for ARM. Same goes for
2.19. In fact, the only newer version of Binutils that seems to work properly is
-2.19.50, it can be downloaded from <a target="_blank" href="ftp://sourceware.org/pub/binutils/snapshots/">here</a>.
+2.19.50, it can be downloaded from <a href="ftp://sourceware.org/pub/binutils/snapshots/">here</a>.
This is the version that we are going to use in this tutorial.</li>
<li><b>GCC</b>:as I'm writing this, the latest GCC version is
-4.3.3, which I'll be using for this tutorial. Download it from <a target="_blank" href="http://gcc.gnu.org/mirrors.html">here</a> after choosing a suitable mirror.</li>
+4.3.3, which I'll be using for this tutorial. Download it from <a href="http://gcc.gnu.org/mirrors.html">here</a> after choosing a suitable mirror.</li>
<li><b>Newlib</b>: as I'm writing this, the latest official Newlib version is 1.17.0, which I'll be using for this tutorial.
-Download it from <a target="_blank" href="ftp://sources.redhat.com/pub/newlib/index.html">here</a>.</li>
+Download it from <a href="ftp://sources.redhat.com/pub/newlib/index.html">here</a>.</li>
<li>The tutorial assumes that you're using bash as your shell. If you use
-something else, you might need to adjust some shell-specific commands. </li></ul></p>
+something else, you might need to adjust some shell-specific commands. </li></ul>
<p>You need some support programs/libraries in order to compile the toolchain. To install them:</p>
-<p><pre><code>$ sudo apt-get install flex bison libgmp3-dev libmpfr-dev autoconf texinfo build-essential</code></pre></p>
+<pre><code>$ sudo apt-get install flex bison libgmp3-dev libmpfr-dev autoconf texinfo build-essential</code></pre>
<p>Next, decide where you want to install your toolchain. They
generally go in <i>/usr/local/</i>, so I'm going to assume
<i>/usr/local/cross-arm</i> for this tutorial. To save yourself some
typing, set this path into a shell variable:</p>
-<p><pre><code>$ export TOOLPATH=/usr/local/cross-arm</code></pre></p>
+<pre><code>$ export TOOLPATH=/usr/local/cross-arm</code></pre>
<h2>Step 1: binutils</h2>
<p>This is the easiest step: unpack, configure, build.</p>
-<p><pre><code>$ tar -xvjf binutils-2.19.50.tar.bz2
+<pre><code>$ tar -xvjf binutils-2.19.50.tar.bz2
$ cd binutils-2.19.50
$ mkdir build
$ cd build
@@ -67,7 +61,7 @@
$ make all
$ sudo make install
$ export PATH=${TOOLPATH}/bin:$PATH
-$ cd ../..</code></pre></p>
+$ cd ../..</code></pre>
<p>Now you have your ARM "binutils" (assembler, linker, disassembler ...) in your PATH. </p>
@@ -76,9 +70,9 @@
<p>In this step we build a "basic" GCC (that is, a GCC without any
support libs, which we'll use in order to build all the libraries for
our target). Let's compile it (and note that the install step is
-a bit different from Newlib's):</p?
+a bit different from Newlib's):</p>
-<p><pre><code>$ tar -xvjf gcc-4.3.3.tar.bz2
+<pre><code>$ tar -xvjf gcc-4.3.3.tar.bz2
$ cd gcc-4.3.3
$ mkdir build
$ cd build
@@ -88,7 +82,7 @@
# export PATH=/usr/local/cross-arm/bin:$PATH
# make install-gcc
# exit
-$ cd ../..</code></pre></p>
+$ cd ../..</code></pre>
<h2>Step 3: Newlib</h2>
@@ -98,7 +92,7 @@
executable, so I added the "-ffunction-sections -fdata-sections" flags
to allow the linker to perform dead code stripping:</p>
-<p><pre><code>$ tar -xvzf newlib-1.17.0.tar.gz
+<pre><code>$ tar -xvzf newlib-1.17.0.tar.gz
$ cd newlib-1.17.0
$ mkdir build
$ cd build
@@ -108,17 +102,18 @@
# export PATH=/usr/local/cross-arm/bin:$PATH
# make install
# exit
-$ cd ../..</code></pre></p>
+$ cd ../..</code></pre>
-<p>Some notes about the flags used in the above sequence:
+<p>Some notes about the flags used in the above sequence:</p>
<ul>
<li><code>--disable-newlib-supplied-syscalls</code>: this deserves a page of its own, but I won't cover it here. For an explanation, see for example
- <a target="_blank" href="http://openhardware.net/Embedded_ARM/NewLib_Stubs/">this page</a></li>
+ <a href="http://openhardware.net/Embedded_ARM/NewLib_Stubs/">this page</a></li>
<li><code>-DPREFER_SIZE_OVER_SPEED -D__OPTIMIZE_SIZE__</code>: compile Newlib for size, not for speed (these are Newlib specific).</li>
<li><code>-Os -fomit-frame-pointer</code>: tell GCC to optimize for size, not for speed.</li>
<li><code>-D__BUFSIZ__=256</code>: again Newlib specific, this is the buffer size allocated by default for files opened via fopen(). The default is 1024, which I find too much
- for <b>eLua</b>, so I'm using 256 here. Of course, you can change this value.</li></ul></p>
+ for <b>eLua</b>, so I'm using 256 here. Of course, you can change this value.</li>
+</ul>
<h2>Step 4: full GCC</h2>
@@ -127,13 +122,14 @@
(most notably libgcc.a). Fortunately this is simpler that the Newlib
compilation step:</p>
-<p><pre><code>$ cd gcc-4.3.3/build
+<pre><code>$ cd gcc-4.3.3/build
$ make all
$ sudo make install
-</code></pre></p>
+</code></pre>
<h2>Step 5: all done!</h2>
<p>Now you can finally enjoy your ARM toolchain, and compile <b>eLua</b> with it :)
If you need further clarification, or if the above instructions didn't work for you, feel free to <a href="overview.html#contacts">contact us</a>.</p>
-</body></html>
+$$FOOTER$$
+
Modified: branches/eagle_mmc/doc/en/tc_cortex.html
===================================================================
--- branches/eagle_mmc/doc/en/tc_cortex.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/en/tc_cortex.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,17 +1,10 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Bulding GCC for Cortex</title>
-
-<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);">
-
+$$HEADER$$
<h3>Building GCC for Cortex</h3>
<p>This tutorial explains how you can create a GCC+Newlib toolchain
that can be used to compile programs for the Cortex (Thumb2)
architecture, thus making it possible to use GCC to compile programs
-for the increasingly number of Cortex CPUs out there (<a target="_blank" href="http://www.luminarymicro.com/">Luminary Micro</a>, i
-<a target="_blank" href="http://www.st.com/mcu/inchtml-pages-stm32.html">ST</a>, with new Cortex CPUs being announced by Atmel and other companies). I
+for the increasingly number of Cortex CPUs out there (<a href="http://www.luminarymicro.com/">Luminary Micro</a>, i
+<a href="http://www.st.com/mcu/inchtml-pages-stm32.html">ST</a>, with new Cortex CPUs being announced by Atmel and other companies). I
am writing this tutorial because I needed to work on a Cortex CPU for
the eLua project and I couldn't find anywhere a complete set of
instructions for building GCC for this architecture. You'll need such a
@@ -19,16 +12,16 @@
pre-built toolchain to compile <b>eLua</b> (see <a href="toolchains.html">toolchains</a> for details) so building
one yourself is not strictly required.</p>
-<p><strong>DISCLAIMER: I'm by no means a specialist in the
+<p><span class="warning">DISCLAIMER</span>: I'm by no means a specialist in the
GCC/newlib/binutils compilation process. I'm sure that there are better
ways to accomplish what I'm describing here, however I just wanted a
quick and dirty way to build a toolchain, I have no intention in
becoming too intimate with the build process. If you think that what I
-did is wrong, innacurate, or simply outrageously ugly, feel free to <a href="overview.html#contacts">contact us</a> and I'll make the necessary corrections.
-And of course, this tutorial comes without any guarantees whatsoever.</strong></p>
+did is wrong, inaccurate, or simply outrageously ugly, feel free to <a href="overview.html#contacts">contact us</a> and I'll make the necessary corrections.
+And of course, this tutorial comes without any guarantees whatsoever.</p>
<h2>Prerequisites</h2>
-<p>To build your toolchain you'll need:
+<p>To build your toolchain you'll need:</p>
<ul><li><b>a computer running Linux</b>: I use Ubuntu, but any Linux
will do as long as you know how to find the equivalent of "apt-get" for
@@ -37,30 +30,30 @@
system already has a "basic" native toolchain installed (gcc/make and
related). This is true for Ubuntu after installation. Again, you might
need to check your specific distribution.</li>
-<li><b>GNU binutils</b>: get it from <a target="_blank" href="http://ftp.gnu.org/gnu/binutils/">here</a>.
+<li><b>GNU binutils</b>: get it from <a href="http://ftp.gnu.org/gnu/binutils/">here</a>.
At the moment of writing this, the latest versions is 2.19.1, but it refuses to compile for ARM. Same goes for
2.19. In fact, the only newer version of Binutils that seems to work properly is
-2.19.50, it can be downloaded from <a target="_blank" href="ftp://sourceware.org/pub/binutils/snapshots/">here</a>.
+2.19.50, it can be downloaded from <a href="ftp://sourceware.org/pub/binutils/snapshots/">here</a>.
This is the version that we are going to use in this tutorial.</li>
<li><b>GCC</b>:as I'm writing this, the latest GCC version is
-4.3.3, which I'll be using for this tutorial. Download it from <a target="_blank" href="http://gcc.gnu.org/mirrors.html">here</a> after choosing a suitable mirror.</li>
+4.3.3, which I'll be using for this tutorial. Download it from <a href="http://gcc.gnu.org/mirrors.html">here</a> after choosing a suitable mirror.</li>
<li><b>Newlib</b>: as I'm writing this, the latest official Newlib version is 1.17.0, which I'll be using for this tutorial.
-Download it from <a target="_blank" href="ftp://sources.redhat.com/pub/newlib/index.html">here</a>.</li>
+Download it from <a href="ftp://sources.redhat.com/pub/newlib/index.html">here</a>.</li>
<li>The tutorial assumes that you're using bash as your shell. If you use
-something else, you might need to adjust some shell-specific commands. </li></ul></p>
+something else, you might need to adjust some shell-specific commands. </li></ul>
<p>You need some support programs/libraries in order to compile the toolchain. To install them:</p>
-<p><pre><code>$ sudo apt-get install flex bison libgmp3-dev libmpfr-dev autoconf texinfo build-essential</code></pre></p>
+<pre><code>$ sudo apt-get install flex bison libgmp3-dev libmpfr-dev autoconf texinfo build-essential</code></pre>
<p>Next, decide where you want to install your toolchain. They
generally go in <i>/usr/local/</i>, so I'm going to assume
<i>/usr/local/cross-cortex</i> for this tutorial. To save yourself some
typing, set this path into a shell variable:</p>
-<p><pre><code>$ export TOOLPATH=/usr/local/cross-cortex</code></pre></p>
+<pre><code>$ export TOOLPATH=/usr/local/cross-cortex</code></pre>
<h2>Step 1: binutils</h2>
<p>This is the easiest step: unpack, configure, build.</p>
-<p><pre><code>$ tar -xvjf binutils-2.19.50.tar.bz2
+<pre><code>$ tar -xvjf binutils-2.19.50.tar.bz2
$ cd binutils-2.19.50
$ mkdir build
$ cd build
@@ -68,7 +61,7 @@
$ make all
$ sudo make install
$ export PATH=${TOOLPATH}/bin:$PATH
-$ cd ../..</code></pre></p>
+$ cd ../..</code></pre>
<p>Now you have your ARM "binutils" (assembler, linker, disassembler ...) in your PATH. They are fully capable of handling Thumb2.</p>
@@ -77,9 +70,9 @@
<p>In this step we build a "basic" GCC (that is, a GCC without any
support libs, which we'll use in order to build all the libraries for
our target). Let's compile it (and note that the install step is
-a bit different from Newlib's):</p?
+a bit different from Newlib's):</p>
-<p><pre><code>$ tar -xvjf gcc-4.3.3.tar.bz2
+<pre><code>$ tar -xvjf gcc-4.3.3.tar.bz2
$ cd gcc-4.3.3
$ mkdir build
$ cd build
@@ -89,14 +82,14 @@
# export PATH=/usr/local/cross-cortex/bin:$PATH
# make install-gcc
# exit
-$ cd ../..</code></pre></p>
+$ cd ../..</code></pre>
<h2>Step 3: Newlib</h2>
<p>Some modifications are in order before we start compiling. Namely, we need to tell Newlib to skip some of its
libraries when compiling (I'm using <b>vim</b> to edit, feel free to use your editor of choice instead):</p>
-<p><pre><code>$ tar -xvzf newlib-1.17.0.tar.gz
+<pre><code>$ tar -xvzf newlib-1.17.0.tar.gz
$ cd newlib-1.17.0
$ vim configure.ac
@@ -122,7 +115,7 @@
well with 2.61 (the version of autoconf on the system that gave the
error). If this happens to you, first execute <i>autoconf --version</i> to
find the actual version of your autoconf, then do this:</b>
-<p><pre><code>$ vim config/override.m4
+$ vim config/override.m4
<b>Look for this line:</b>
[m4_define([_GCC_AUTOCONF_VERSION], [2.59])])
@@ -130,19 +123,19 @@
<b>And replace [2.59] with your actual version ([2.61] in my case).
Save the modified file and exit the text editor.</b>
-$ autoconf</code></pre></p></code></pre></p>
+$ autoconf</code></pre>
<p>Once again, now we're ready to actually compile Newlib. But we need
to tell it to compile for Thumb2. As already specified, I'm not a
-specialist when it comes to Newlib's build system, so I chosed the
+specialist when it comes to Newlib's build system, so I chose the
quick, dirty and not so elegant solution of providing the compilation
flags directly from the command line. Also, as I wanted my library to
be as small as possible (as opposed to as fast as possible) and I only
wanted to keep what's needed from it in the final executable, I added
the "-ffunction-sections -fdata-sections" flags to allow the linker to
perform dead code stripping:</p>
-<p><pre><code>$ mkdir build
+<pre><code>$ mkdir build
$ cd build
$ ../configure --target=arm-elf --prefix=$TOOLPATH --enable-interwork --disable-newlib-supplied-syscalls --with-gnu-ld --with-gnu-as --disable-shared
$ make CFLAGS_FOR_TARGET="-ffunction-sections -fdata-sections -DPREFER_SIZE_OVER_SPEED -D__OPTIMIZE_SIZE__ -Os -fomit-frame-pointer -mcpu=cortex-m3 -mthumb -D__thumb2__ -D__BUFSIZ__=256" CCASFLAGS="-mcpu=cortex-m3 -mthumb -D__thumb2__"
@@ -150,18 +143,18 @@
# export PATH=/usr/local/cross-cortex/bin:$PATH
# make install
# exit
-$ cd ../..</code></pre></p>
-<p>Some notes about the flags used in the above sequence:
+$ cd ../..</code></pre>
+<p>Some notes about the flags used in the above sequence:</p>
<ul><li><code>--disable-newlib-supplied-syscalls:</code> this deserves a page of its own, but I won't cover it here.
- For an explanation, see for example <a target="_blank" href="http://openhardware.net/Embedded_ARM/NewLib_Stubs/">this page</a>.</li>
+ For an explanation, see for example <a href="http://openhardware.net/Embedded_ARM/NewLib_Stubs/">this page</a>.</li>
<li><code>-DPREFER_SIZE_OVER_SPEED -D__OPTIMIZE_SIZE__:</code> compile Newlib for size, not for speed (these are Newlib specific).</li>
<li><code>-mcpu=cortex-m3 -mthumb:</code> this tells GCC that you want to compile for Cortex. Note that you need both flags.</li>
<li><code>-D__thumb2__:</code> again, this is Newlib specific, and seems to be required when compiling Newlib for Cortex.</li>
<li><code>-Os -fomit-frame-pointer:</code> tell GCC to optimize for size, not for speed.</li>
<li><code>-D__BUFSIZ__=256:</code>again Newlib specific, this is the buffer size allocated by default for
files opened via fopen(). The default is 1024, which I find too much
-for <b>eLua</b>, so I'm using 256 here. Of course, you can change this value.</li></ul></p>
+for <b>eLua</b>, so I'm using 256 here. Of course, you can change this value.</li></ul>
<h2>Step 4: full GCC</h2>
@@ -170,16 +163,16 @@
(most notably libgcc.a). Fortunately this is simpler that the Newlib
compilation step, as long as you remember that we want to build our
compiler support libraries for the Cortex architecture:</p>
-<p><pre><code>$ cd gcc-4.3.3/build
+<pre><code>$ cd gcc-4.3.3/build
$ make CFLAGS="-mcpu=cortex-m3 -mthumb" CXXFLAGS="-mcpu=cortex-m3 -mthumb" LIBCXXFLAGS="-mcpu=cortex-m3 -mthumb" all
$ sudo make install
-</code></pre></p>
+</code></pre>
<h2>All Done!</h2>
<p>Phew! That was quite a disturbing tutorial, with all that confusing
flags lurking in every single shell line :) But at this point you
-should have a fully functional Cortex GCC toolchain, which seems to be
-something very rare, so enjoy it with pride.
+should have a fully functional Cortex GCC toolchain, so enjoy it!
If you need further clarification, or if the above instructions didn't
work for you, feel free to <a href="overview.html#contacts">contact us</a>.</p>
-</body></html>
+$$FOOTER$$
+
Modified: branches/eagle_mmc/doc/en/tchainbuild.html
===================================================================
--- branches/eagle_mmc/doc/en/tchainbuild.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/en/tchainbuild.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,18 +1,13 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Toolchain building tutorials</title>
-
-<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);">
+$$HEADER$$
<h3>Toolchain building tutorials</h3>
<p>Although not strictly required, you can roll your own toolchain that can be used to build <b>eLua</b>. As explained <a href="toolchains.html">here</a>, <b>eLua</b> can generally be built with
-ready-made toolchains (with the exception of the i386 port), but you might still want to build your own toolchain for various reasons:
+ready-made toolchains (with the exception of the i386 port), but you might still want to build your own toolchain for various reasons:</p>
<ul>
<li>have a better control over the compilation options of different libraries (most notably libc).</li>
<li>use a specific version of gcc/newlib.</li>
<li>your toolchain might generate smaller code than a pre-built toolchain.</li>
<li>get familiar with the binutils/gcc/newlib build system (not related to <b>eLua</b>, but still a good reason).</li>
-</ul></p>
+</ul>
<p>Three separate tutorials explain the procedure of building a regular ARM toolchain, a Cortex-M3 toolchain and an i386 toolchain, respectively.</p>
-</body></html>
+$$FOOTER$$
+
Modified: branches/eagle_mmc/doc/en/tmr_ref.html
===================================================================
--- branches/eagle_mmc/doc/en/tmr_ref.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/en/tmr_ref.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,9 +1,9 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8"/>
<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
-<link rel="stylesheet" type="text/css" href="../style.css">
+<link rel="stylesheet" type="text/css" href="../style.css"></link>
</head>
<body style="background-color: rgb(255, 255, 255);">
<h3><a name="over"></a>tmr</h3>
Modified: branches/eagle_mmc/doc/en/toolchains.html
===================================================================
--- branches/eagle_mmc/doc/en/toolchains.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/en/toolchains.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,66 +1,61 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Toolchains for eLua</title>
-<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);">
+$$HEADER$$
<h3>Toolchains for eLua</h3>
<p>You need (at least) a toolchain if you decide to build <b>eLua</b> yourself. The toolchain must contain at least a compiler, an assembler, a linker and (most likely) a tool to extract binary
data from the compiled image (in order to build the actual firmware). Also, a program that reports the sizes of different sections in the compiled image is often used to give an idea about the
resource consumption of <b>eLua</b>. You can use as many toolchains as you want for a given target, as long as the build scripts know to handle them. This
- section outlines the different toolchain choices available for compiling <b>eLua</b>. Use the links below to navigate directly to your target of interest.
+ section outlines the different toolchain choices available for compiling <b>eLua</b>. Use the links below to navigate directly to your target of interest.</p>
<ul>
<li><a href="#armcortex">Toolchains for ARM and Cortex</a></li>
<li><a href="#avr32">Toolchains for AVR32</a></li>
<li><a href="#i386">Toolchains for i386</a></li>
-</ul></p>
+</ul>
<p>If you have a different toolchain, reffer to the <a href="#configuration">toolchain configuration</a> paragraph in this document.</p>
<a name="armcortex"><h2>Toolcains for ARM and Cortex</h2></a>
-<p>You have multiple options when building <b>eLua</b> for ARM and Cortex CPUs:
+<p>You have multiple options when building <b>eLua</b> for ARM and Cortex CPUs:</p>
<ul>
<li>build your own toolchain. Even if you have a toolchain already available, you might want to do this for maximum flexibility and control (for example to control the libc build flags, or to
- use specific version of the tools). Check <a href="">##this link</a> for a step by step tutorial on building your own toolchain.</li>
+ use specific version of the tools). Check <a href="tchainbuild.html">this link</a> for a step by step tutorial on building your own toolchain.</li>
<li>use a readily available toolchain. This saves you the hassle of building the toolchain yourself, which makes the process quicker and less error-prone.</li>
-</ul></p>
+</ul>
<p>Because building a toolchain is already covered in another section of the documentation, we'll focus on installing a pre-compiled toolchain here. ARM is a very popular architecture, and because
-of this there are a lot of toolchains available for download free of charge. One of the most popular ones comes from <a href="http://www.codesourcery.com">CodeSourcery</a>, and we'll cover it here for a number of important reasons:
+of this there are a lot of toolchains available for download free of charge. One of the most popular ones comes from <a href="http://www.codesourcery.com">CodeSourcery</a>, and we'll cover it here for a number of important reasons:</p>
<ul>
<li>it has support for both "traditional" ARM targets and Cortex-M3 (Thumb2) targets</li>
<li>it comes with user-friendly installers for both Linux and Windows</li>
- <li>it has fairlygood documentation</li>
+ <li>it has fairly good documentation</li>
<li><b>eLua</b> supports this toolchain for all its ARM and Cortex targets</li>
-</ul></p>
-<p>Obtaining and installing the toolchain is very easy:
+</ul>
+<p>Obtaining and installing the toolchain is very easy:</p>
<ol>
<li>go to <a href="http://www.codesourcery.com/sgpp/lite/arm/portal/subscription?@template=lite">the CodeSourcery download location</a> for the toolchain.</li>
<li>select from the table the current version in the "EABI" line (the link to the current version is just above the "All versions..." link).</li>
<li>download and run the installer.</li>
-</ol></p>
+</ol>
<p>That's all! Make sure that the location of the toolchain is in your $PATH and build <b>eLua</b> with the <b>toolchain=codesourcery</b> option.</p>
<a name="avr32"><h2>Toolchains for AVR32</h2></a>
<p>Currently you have only one option for AVR32: download and install the toolchain from <a href="http://www.atmel.com">Atmel</a>. Unfortuntely they don't provide an installer, just a bunch of
- Linux packages with some dependencies, so the installation process might be a bit tricky. These are the steps you should follow to install Atmel's AVR32 toolchain:
+ Linux packages with some dependencies, so the installation process might be a bit tricky. These are the steps you should follow to install Atmel's AVR32 toolchain:</p>
<ul>
<li>download the correct version for your Linux distribution (in this case Ubuntu) from <a href="http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4118">here</a>.</li>
<li>unzip the downloaded archive to a temporary directory, you'll get a bunch of .deb packages</li>
<li>install the packages from this command line (the package names are based on version 2.1.4 of the toolchain, change them as needed if you're using a different version):
- <p><pre><code>$ sudo dpkg -i libavr32ocd1_3.0.9-1_i386.deb libavr32sim_0.2.1-1_i386.deb
+ <pre><code>$ sudo dpkg -i libavr32ocd1_3.0.9-1_i386.deb libavr32sim_0.2.1-1_i386.deb
$ sudo dpkg -i libavrtools1_3.0.9-1_i386.deb libelfdwarfparser_2.0.7-1_i386.deb
$ sudo dpkg -i avr32headers_1.9.11-1_all.deb
$ sudo dpkg -i avr32parts_1.9.9-1_all.deb
$ sudo dpkg -i avr32-binutils_2.17.atmel.1.2.6-2_i386
$ sudo dpkg -i avr32-gcc-newlib_4.2.2-atmel.1.0.8-2_i386.deb
-$ sudo dpkg -i avr32program_3.0.4-1_i386.deb</p></pre></code>
+$ sudo dpkg -i avr32program_3.0.4-1_i386.deb</code></pre>
If dpkg complains about missing dependencies, install them as required and resume the installation process.
</li>
-</ul></p>
+</ul>
<p>That's it. Your toolchain is already be in $PATH (since it installs itself in /usr/bin) so you should be ready to build <b>eLua</b> for AVR32.</p>
<a name="i386"><h2>Toolchains for i386</h2></a>
-<p>Currently the only tested procedure for building <b>eLua</b> for i386 is to <a href="">##build an i386 toolchain</a>. Other toolchains might work equally well though, but none was tested so far.
+<p>Currently the only tested procedure for building <b>eLua</b> for i386 is to <a href="tc_386.html">build an i386 toolchain</a>. Other toolchains might work equally well though, but none was tested so far.
</p>
-<a name="configuration"><h3>Toolchain configuration in eLua <font color="red">(WIP)</font></h3></a>
+<a name="configuration"><h3>Toolchain configuration in eLua <span style="color: red;">(WIP)</span></h3></a>
<p>The <b>eLua</b> build system makes provisions for specifying an unlimited number of toolchains for a given target, selectable via the scons <b>toolchain=...</b> option. The default structure
- of each of the toolchains supported by default is listed in the table below.
+ of each of the toolchains supported by default is listed in the table below.</p>
<table class="table_center">
<tbody>
<tr>
@@ -131,8 +126,8 @@
</tr>
</tbody>
</table>
-</p>
-<p>If you need to add a new toolchain or modify an existing one, take a look at the scons build script (SConstruct). A toolchain-related fragment of SConstruct is shown below:
+
+<p>If you need to add a new toolchain or modify an existing one, take a look at the scons build script (SConstruct). A toolchain-related fragment of SConstruct is shown below:</p>
<pre><code># List of toolchains
toolchain_list = {
<b># This defines a toolchain with the name "arm-elf"</b>
@@ -161,15 +156,15 @@
'at91sam7x' : { 'cpus' : [ 'AT91SAM7X256', 'AT91SAM7X512' ], <b>'toolchains' : [ 'arm-gcc', 'codesourcery' ]</b> },
'lm3s' : { 'cpus' : [ 'LM3S8962', 'LM3S6965', 'LM3S6918' ], <b>'toolchains' : [ 'arm-gcc', 'codesourcery' ]</b> },
................
-}</pre></code></p>
-<p>From this fragment it's easy to undertand that there are at most two places in SConstruct that must be taken into account when dealing with toolchain:
+}</code></pre>
+<p>From this fragment it's easy to understand that there are at most two places in SConstruct that must be taken into account when dealing with toolchain:</p>
<ul>
<li>the definition of <b>toolchain_list</b>. This is a list of all the supported toolchains with all their relevant components (compiler, linker, assembler, image copy tool and size tool).</li>
<li>each <b>eLua</b> platform has a list of permitted toolchains (only the toolchains specified in this list can be used to build an <b>eLua</b> image for that target). The first element of
this list will be automatically used if a <b>toolchain=...</b> option is not specified on the command line.</li>
-</ul></p>
+</ul>
<p>Please note that in order to add a new toolchain to <b>eLua</b> it's generally not enough to edit just SConstruct. As different toolchains have different command line options, one should also
edit the platform's build configuration file (<i>src/platform/<platform name>/conf.py</i>) and make it aware of the new toolchain. The exact procedure for doing this is highly dependent on
the toolchain and it's well beyond the scope of this tutorial.</p>
-</body></html>
+$$FOOTER$$
Modified: branches/eagle_mmc/doc/en/tut_bootpc.html
===================================================================
--- branches/eagle_mmc/doc/en/tut_bootpc.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/en/tut_bootpc.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,10 +1,4 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Booting your PC in eLua</title>
-
-<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);">
+$$HEADER$$
<h3>Booting your PC in eLua</h3>
<p>That's right: after following this tutorial, your PC will boot
directly into Lua! No OS there (this explains why the boot process is
@@ -14,8 +8,8 @@
<h2>Details</h2>
-<p>Booting <b>eLua</b> involves using the well known <a target="_blank" href="http://www.gnu.org/software/grub/">GRUB</a> that will be used to load
-a <a target="_blank" href="http://www.gnu.org/software/grub/manual/multiboot/">multiboot</a>
+<p>Booting <b>eLua</b> involves using the well known <a href="http://www.gnu.org/software/grub/">GRUB</a> that will be used to load
+a <a href="http://www.gnu.org/software/grub/manual/multiboot/">multiboot</a>
compliant ELF file that contains our <b>eLua</b> code. The code runs in protected mode, so you
have access to your whole memory. The code does not access any kind of
storage device (HDD, CDROM, floppy), so if you're worried that it might
@@ -25,41 +19,41 @@
(be sure to use the hardware reset though, CTRL+ALT+DEL is not handled
by the code). But just in case, see also the next section.</p>
-<h2>Disclaimer</h2>
+<h2 style="background-color: orangered;">Disclaimer</h2>
-<p><strong>As already mentioned, the code won't try to access any kind
+<p>As already mentioned, the code won't try to access any kind
of storage (HDD, CDROM, floppy), not even for reading, so you don't
need to worry about that. Also it doesn't try to reprogram your video
card registers, so it can't harm it or your monitor. It only implements
a "protected mode keyboard driver" that can't physically damage
anything in your system. In short, I made every effort to make the code
-as harmless as possible. I tested it on 5 different computers and in 2 <a target="_blank" href="http://www.virtualbox.org/">VirtualBox</a>
+as harmless as possible. I tested it on 5 different computers and in 2 <a href="http://www.virtualbox.org/">VirtualBox</a>
emulators, and nothing bad happened. That said, there are no warranties
of any kind. In the very unlikely event that something bad does happen
to your system, you have my sincere sympathy, but I can't be held
-responsible for that.</strong></p>
+responsible for that.</p>
<h2>Prerequisites</h2>
-<p>To boot your computer in Lua you'll need:
+<p>To boot your computer in Lua you'll need:</p>
<ul>
<li>a 386 or better computer running Linux. I actually tested
this only on Pentium class computers, but it should run on a 386
without problems.</li>
-<li><a target="_blank" href="http://www.gnu.org/software/grub/">GRUB</a>.
+<li><a href="http://www.gnu.org/software/grub/">GRUB</a>.
Since you're running Linux, chances are you're already using GRUB as
your bootloader. If not, you must install it. You don't need to install
it on your HDD; a floppy, an USB stick or even a CDROM will work as
well. I won't cover the GRUB installation procedure here, just google
for "install grub on floppy/usb/cdrom" and you'll sure find what you're
-looking for. You can try for example <a target="_blank" href="http://orgs.man.ac.uk/documentation/grub/grub_3.html">here</a>,
-<a target="_blank" href="http://www.freesoftwaremagazine.com/articles/grub_intro/">here</a> or
-<a target="_blank" href="http://www.mayrhofer.eu.org/Default.aspx?pageindex=6&pageid=45">here</a>.</li>
+looking for. You can try for example <a href="http://orgs.man.ac.uk/documentation/grub/grub_3.html">here</a>,
+<a href="http://www.freesoftwaremagazine.com/articles/grub_intro/">here</a> or
+<a href="http://www.mayrhofer.eu.org/Default.aspx?pageindex=6&pageid=45">here</a>.</li>
<li>The <b>eLua</b> i386 ELF file, see <a href="downloads.html">here</a> for instructions on how to obtain it. OR <a href="downloads.html">download the eLua source distribution</a> and compile it
for the i386 architecture using a toolchain that you can build by following <a href="tc_386.html">this tutorial</a>.</li>
<li>a text editor to edit your GRUB configuration file.</li>
-</ul></p>
+</ul>
<p>The rest of this tutorial assumes that you're using Linux with GRUB,
and that GRUB is located in <i>/boot/grub</i>, which is true for many Linux
@@ -68,14 +62,14 @@
<h2>Let's do this</h2>
<p>First, copy the eLua ELF file to your "/boot" directory:</p>
-<p><pre><code>$ sudo cp surprise /boot<br></code></pre></p>
+<pre><code>$ sudo cp surprise /boot<br></code></pre>
<p>Next you need to add another entry to your GRUB menu file (<i>/boot/grub/menu.lst</i>). Edit it and add this entry:</p>
-<p><pre><code> title eLua
+<pre><code> title eLua
root (hd0,0)
kernel /boot/elua_lua_i386.elf <b>(change this if the eLua file name is different)</b>
- boot</code></pre></p>
+ boot</code></pre>
<p>You may need to modify the <i>root (hd0,0)</i> line above to match your
@@ -83,11 +77,11 @@
for the entry that boots your Linux kernel. It should look similar to
this:</p>
-<p><pre><code> title Ubuntu, kernel 2.6.20-16-generic
+<pre><code> title Ubuntu, kernel 2.6.20-16-generic
<b>root (hd0,2)</b>
kernel /boot/vmlinuz-2.6.20-16-generic
initrd /boot/initrd.img-2.6.20-16-generic
- savedefault</code></pre></p>
+ savedefault</code></pre>
<p>After you find it, simply use the <i>root (hdx,y)</i> line from that entry
@@ -98,4 +92,5 @@
instructions on how to use your newly installed self-booting programming language :)</p>
<p>As usual, if you need more details, you can <a href="overview.html#contacts">contact us</a>.
Also, if you want to go one step ahead and have you own USB stick that boots <b>eLua</b>, check <a href="tut_bootstick.html">this tutorial</a>.</p>
-</body></html>
+$$FOOTER$$
+
Modified: branches/eagle_mmc/doc/en/tut_bootstick.html
===================================================================
--- branches/eagle_mmc/doc/en/tut_bootstick.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/en/tut_bootstick.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,10 +1,4 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Booting eLua from an USB stick</title>
-
-<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);">
+$$HEADER$$
<h3>Booting eLua from an USB stick</h3>
<p>This is follow up of <a href="tut_bootpc.html">this tutorial</a>.
After completing it you'll be able to boot <b>eLua</b> directly from your USB
@@ -15,16 +9,16 @@
don't use anymore, and/or the shear geekness of this idea makes you
feel curious, this tutorial is definitely for you :)</p>
-<h2>Disclaimer</h2>
+<h2 style="background-color: orangered;">Disclaimer</h2>
-<p><strong>As mentioned <a href="tut_bootpc.html">here</a>,
+<p>As mentioned <a href="tut_bootpc.html">here</a>,
the code won't try to access any kind of storage (HDD, CDROM, floppy),
not even for reading, so you don't need to worry about that. Also it
doesn't try to reprogram your video card registers, so it can't harm it
or your monitor. It only implements a "protected mode keyboard driver"
that can't physically damage anything in your system. In short, I made
every effort to make the code as harmless as possible. I tested it on 5
-different computers and in 2 <a htarget="_blank" ref="http://www.virtualbox.org/">VirtualBox</a>
+different computers and in 2 <a href="http://www.virtualbox.org/">VirtualBox</a>
emulators, and nothing bad happened. That said, there are no warranties
of any kind. In the very unlikely event that something bad does happen
to your system, you have my sincere sympathy, but I can't be held
@@ -32,17 +26,17 @@
your HDD by failing the GRUB installation procedure (even though, once
again, this shouldn't be possible unless you really insist on messing
it up). If you're new to computers or Linux, this tutorial might not be for you.
-Your call.</strong></p>
+Your call.</p>
<h2>Prerequisites</h2>
-<p>To have your own bootable <b>eLua</b> USB stick you'll need:
+<p>To have your own bootable <b>eLua</b> USB stick you'll need:</p>
<ul><li>an USB stick. I tested this on an 128M USB stick, because
it's the smallest I could find. You should be OK with a 4M stick or
even a 2M stick</li>
<li>a computer running Linux. I use Ubuntu, but any other distribution is fine.</li>
-<li><a target="_blank" href="http://www.gnu.org/software/grub/">GRUB</a>.
+<li><a href="http://www.gnu.org/software/grub/">GRUB</a>.
Since you're running Linux, chances are you're already using GRUB as
your bootloader. If not, you must install it on your HDD, or at least
know how to install it directly on the USB stick. I won't go into
@@ -50,7 +44,7 @@
GRUB. This tutorial assumes that you're using GRUB as your bootloader.</li>
<li>The <b>eLua</b> i386 ELF file, see <a href="downloads.html">here</a> for instructions on how to obtain it. OR <a href="downloads.html">download the eLua source distribution</a> and compile it
for the i386 architecture using a toolchain that you can build by following <a href="tc_386.html">this tutorial</a>.</li>
-<li>a text editor to edit your GRUB configuration file.</li></ul></p>
+<li>a text editor to edit your GRUB configuration file.</li></ul>
<p>The rest of this tutorial assumes that you're using Linux with GRUB,
@@ -71,38 +65,38 @@
looked at the original partition table of my <b>eLua</b> USB stick and it scared me to
death, so I had to follow this procedure. In short, you'll need to
delete all the partitions from your stick, create a new partition, and
-then format it. For a step by step tutorial check <a target="_blank" href="http://www.4p8.com/eric.brasseur/suse9.1_usb_stick.html">here</a>.</p>
+then format it. For a step by step tutorial check <a href="http://www.4p8.com/eric.brasseur/suse9.1_usb_stick.html">here</a>.</p>
<h2>Install GRUB on your stick</h2>
<p>First, mount your freshly formatted stick (I'm going to assume that the mount directory is <i>/mnt</i>):</p>
-<p><pre><code>$ sudo mount /dev/sda1 /mnt<br></code></pre></p>
+<pre><code>$ sudo mount /dev/sda1 /mnt<br></code></pre>
<p>(of course, you'll need to change <i>/dev/sda1</i> to reflect the physical location of your USB stick. You should know the physical location from the previous step).
Then copy the required GRUB files to your stick:</p>
-<p><pre><code>$ cd /mnt
+<pre><code>$ cd /mnt
$ mkdir boot
$ mkdir boot/grub
$ cd /boot/grub
-$ cp stage1 fat_stage1_5 stage2 /mnt/boot/grub</code></pre></p>
+$ cp stage1 fat_stage1_5 stage2 /mnt/boot/grub</code></pre>
<p>Copy the <b>eLua</b> ELF file (<i>elua_lua_i386.elf</i> in this example, change the name if needed) to the GRUB directory as well:</p>
-<p><pre><code>$ cp elua_lua_i386.elf /mnt/boot/grub</code></pre></p>
+<pre><code>$ cp elua_lua_i386.elf /mnt/boot/grub</code></pre>
<p>Create a <i>menu.lst</i> file for GRUB with you favorite text editori (I'm using vim):</p>
-<p><pre><code>$ cd /mnt/boot/grub
+<pre><code>$ cd /mnt/boot/grub
$ vim menu.lst
title eLua
root (hd0,0)
kernel /boot/grub/elua_lua_i386.elf
- boot</code></pre></p>
+ boot</code></pre>
<p>Now it's time to actually install GRUB on the stick.</p>
-<p><pre><code>$ sudo -s -H
+<pre><code>$ sudo -s -H
# grub
<b>Now we need to find the GRUB name of our USB stick. We'll use the "find" command from
@@ -127,10 +121,11 @@
Running "install /boot/grub/stage1 (hd2) (hd2)1+15 p (hd2,0)/boot/grub/stage2
/boot/grub/menu.lst"... succeeded
Done.
-grub> quit</code></pre></p>
+grub> quit</code></pre>
<p>That's it! Now reboot your computer, make sure that your BIOS is set
to boot from USB, and enjoy! See <a href="using.html">using eLua</a> for
instructions on how to use your new toy :).</p>
<p>As usual, if you need more details, you can <a href="overview.html#contacts">contact us</a>.</p>
-</body></html>
+$$FOOTER$$
+
Modified: branches/eagle_mmc/doc/en/tut_openocd.html
===================================================================
--- branches/eagle_mmc/doc/en/tut_openocd.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/en/tut_openocd.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,29 +1,23 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Using OpenOCD</title>
-
-<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);">
+$$HEADER$$
<h3>Using OpenOCD</h3>
-<p>This section presents <a target="_blank" href="http://openocd.berlios.de">OpenOCD</a>, a tool used to program <b>eLua</b> on some of its targets.
+<p>This section presents <a href="http://openocd.berlios.de">OpenOCD</a>, a tool used to program <b>eLua</b> on some of its targets.
If you'd rather skip the long and boring OpenOCD introduction and
-skip directly to the OpenOCD script downloads, use the links below.
+skip directly to the OpenOCD script downloads, use the links below.</p>
<ul>
<li><a href="#str9files">Configuration files for STR9-comStick</a></li>
<li><a href="#lpc2888files">Configuration files for LPC2888</a></li>
<li><a href="#str7files">Configuration files for STR7</a></li>
-</ul></p>
+</ul>
<h2>About OpenOCD</h2>
-<p><a target="_blank" href="http://openocd.berlios.de">OpenOCD</a> is an open source tool that can be used to connect to a CPU's
-<a target="_blank" href="http://en.wikipedia.org/wiki/JTAG">JTAG</a>
+<p><a href="http://openocd.berlios.de">OpenOCD</a> is an open source tool that can be used to connect to a CPU's
+<a href="http://en.wikipedia.org/wiki/JTAG">JTAG</a>
interface. Using OpenOCD and a physical JTAG connection allows you to
burn the on-chip flash memory of your CPU (or to load your code
directly to RAM), to read the internal CPU memory (Flash/RAM) and to
-use <a target="_blank" href="http://sourceware.org/gdb/">gdb</a> or other debuggers to debug your code.
+use <a href="http://sourceware.org/gdb/">gdb</a> or other debuggers to debug your code.
Needless to say, this is a very handy tool (and especially handy if
your CPU happens to be built around an ARM core, since in this case you
can be almost certain that it has a JTAG interface that you can use).
@@ -41,27 +35,27 @@
only for targets that lack a proper firmware burning tool. If you need
to debug your code, however, you probably want to use OpenOCD, since
the alternatives aren't cheap.
-To summarize, you can forget about OpenOCD when:
+To summarize, you can forget about OpenOCD when:</p>
<ul>
<li>your CPU manufacturer provides a special tool for
firmware burning. This is quite often the case, but more often that not
-the forementioned tools work only in Windows.</li>
+the aforementioned tools work only in Windows.</li>
<li>you must debug your code, but you have a good intuition about where the
problem is located. In this case, simply connecting a LED to a PIO port
and turning it on and off from different parts of your code until you
figure out exactly what's the problem can work wonders. I can't
remember when was the last time I used gdb for debugging, since "LED
debugging" was all I needed. </li>
-</ul></p>
+</ul>
-<p>On the other hand, you should probably use OpenOCD when:
+<p>On the other hand, you should probably use OpenOCD when:</p>
<ul>
<li>your CPU manufacturer doesn't provide a special tool for firmware burning (or it does, but it's not what you need).</li>
<li>you're using Linux, MacOS or another OS that is not supported by the firmware burning tool.</li>
<li>you need to do some serious debugging in order to understand what's wrong with your application.</li>
-</ul></p>
+</ul>
<p>If you decided that you don't need OpenOCD after all, now it's a
good time to navigate away from this page and save yourself from some
@@ -73,9 +67,9 @@
firmware burning. And, before we begin, please read and understand the
next paragraph.</p>
-<h2>Disclaimer</h2>
+<h2 style="background-color: orangered;">Disclaimer</h2>
-<p><b>Using OpenOCD improperly may force your CPU to behave
+<p>Using OpenOCD improperly may force your CPU to behave
unexpectedly. While physically damaging your CPU as a result of using
OpenOCD is very hard to accomplish, you might end up with a locked
chip, or you might erase a memory area that was not supposed to be
@@ -84,18 +78,19 @@
I'm going to provide, make sure that you know what you're doing. Also,
I'm not at all an OpenOCD expert, so my configuration scripts might
have errors, even though I tested them. In short, this tutorial comes
-without any guarantees whatsoever.</b></p>
+without any guarantees whatsoever.</p>
+
<h2>Getting OpenOCD</h2>
<p>If you're on Windows, the best way to get OpenOCD already compiled and ready to run is to
-visit the <a target="_blank" href="http://www.yagarto.de/">Yagarto home page</a>.
+visit the <a href="http://www.yagarto.de/">Yagarto home page</a>.
They provide a very nice OpenOCD installer, and they seem to keep up
with OpenOCD progress (the versions on the Yagarto site are not
"bleeding edge", but there are quite fresh nevertheless). If you're on
Linux, you can always use apt-get or your distribution-specific package
manager:</p>
-<p><pre><code>$ sudo apt-get install openocd<br></code></pre></p>
+<pre><code>$ sudo apt-get install openocd</code></pre>
<p>There is a catch here though: the OpenOCD version that I get from
apt-get is dated 2007-09-05, while the Yagarto OpenOCD version is from
@@ -105,9 +100,9 @@
introduction, the meaning and parameters of different commands might
change between OpenOCD version, so if you want to use the Yagarto
version on your non Windows system, you'll have to build it from source
-(see below).<br>
-The main resource on how to build OpenOCD from source is the <a target="_blank" href="http://openfacts.berlios.de/index-en.phtml?title=Building_OpenOCD">OpenOCD build page</a>
-from the OpenOCD wiki. Also, a very good tutorial can be found <a target="_blank" href="http://forum.sparkfun.com/viewtopic.php?t=11221">here</a>.
+(see below).</p>
+<p>The main resource on how to build OpenOCD from source is the <a href="http://openfacts.berlios.de/index-en.phtml?title=Building_OpenOCD">OpenOCD build page</a>
+from the OpenOCD wiki. Also, a very good tutorial can be found <a href="http://forum.sparkfun.com/viewtopic.php?t=11221">here</a>.
I'm not going to provide step by step build instructions, since the two
links that I mentioned cover this very well, and the build process is
relatively straightforward. However, since both tutorials describe how
@@ -115,11 +110,11 @@
modification do build the Yagarto version instead. The modification is
in the SVN checkout step. Replace this step:</p>
-<p><pre><code>$ svn checkout svn://svn.berlios.de/openocd/trunk<br></code></pre></p>
+<pre><code>$ svn checkout svn://svn.berlios.de/openocd/trunk</code></pre>
<p>with this step ('717' is the SVN revision of the Yagarto OpenOCD build):</p>
-<p><pre><code>$ svn checkout <b>-r 717</b> svn://svn.berlios.de/openocd/trunk<br></code></pre></p>
+<pre><code>$ svn checkout <b>-r 717</b> svn://svn.berlios.de/openocd/trunk</code></pre>
<p>Follow the rest of the build instructions, and in the end you should have a working OpenOCD.</p>
@@ -131,13 +126,13 @@
described in the previous section) and listing the
trunk/src/target/target directory:</p>
-<p><pre><code>$ ls trunk/src/target/target
+<pre><code>$ ls trunk/src/target/target
at91eb40a.cfg
at91r40008.cfg
....
str9comstick.cfg
....
-</code></pre></p>
+</code></pre>
<p>If this listing has something that looks like your CPU name, you're lucky. OpenOCD has support for LPC from NXP, AT91SAM cfrom Atmel, STR7/STR9 from ST, and many others.</p>
@@ -153,27 +148,27 @@
</ul>
<p>In some cases, your CPU board might provide a built in JTAG adapter. For example,
-my <a target="_blank" href="http://www.luminarymicro.com/products/lm3s8962_can_ethernet_evaluation_kit.html">LM3S8962</a>
+my <a href="http://www.luminarymicro.com/products/lm3s8962_can_ethernet_evaluation_kit.html">LM3S8962</a>
board provides both an USB-to-JTAG and an USB-to-serial converter built
on board, switching between them automagically. The same is true for my
-<a target="_blank" href="http://www.hitex.com/index.php?id=383">STR9-comStick</a>.
-On the other hand, my <a target="_blank" href="http://www.olimex.com/dev/sam7-ex256.html">SAM7-EX256</a> board has only a JTAG connector, I need a separate JTAG adapter to connect to it.
-I'm using <a target="_blank" href="http://www.olimex.com/dev/arm-usb-tiny.html">ARM-USB-TINY</a> from Olimex, but there are other affordable USB-to-JTAG adapters out there,
-like the <a target="_blank" href="http://www.amontec.com/jtagkey-tiny.shtml">Amontec JTAGKey-Tiny</a>. Not to mention that you can
-<a target="_blank" href="http://www.hs-augsburg.de/%7Ehhoegl/proj/usbjtag/usbjtag.html">build your own</a>. Although USB is my interface of choice, you'll find JTAG adapters for
+<a href="http://www.hitex.com/index.php?id=383">STR9-comStick</a>.
+On the other hand, my <a href="http://www.olimex.com/dev/sam7-ex256.html">SAM7-EX256</a> board has only a JTAG connector, I need a separate JTAG adapter to connect to it.
+I'm using <a href="http://www.olimex.com/dev/arm-usb-tiny.html">ARM-USB-TINY</a> from Olimex, but there are other affordable USB-to-JTAG adapters out there,
+like the <a href="http://www.amontec.com/jtagkey-tiny.shtml">Amontec JTAGKey-Tiny</a>. Not to mention that you can
+<a href="http://www.hs-augsburg.de/%7Ehhoegl/proj/usbjtag/usbjtag.html">build your own</a>. Although USB is my interface of choice, you'll find JTAG adapters for
PC LPT ports too. The good news is that once you buy a JTAG adapter,
chances are that it will work with many boards with different CPUs,
since the JTAG connector layout is standardized and the JTAG adapters
-are generally able to work with different voltages.<br>
-To actually use OpenOCD, the next thing you'll need is a configuration file. The
+are generally able to work with different voltages.</p>
+<p>To actually use OpenOCD, the next thing you'll need is a configuration file. The
configuration file is the one that lets OpenOCD know about your setup,
-such as:
+such as:</p>
<ul>
<li>the kind of JTAG interface that you're using.</li>
<li>the actual hardware platform you're using (ATM7TDMI, ARM966 and so on).</li>
<li>the memory configuration of your CPU (flash banks).</li>
<li>the script used to program the flash memory.</li>
-</ul></p>
+</ul>
<p>Presenting a list of all the possible configuration options and
@@ -185,58 +180,58 @@
we need to tell OpenOCD that we're using a the STR9-comStick
USB-to-JTAG adapter:</p>
-<p><pre><code>interface ft2232
+<pre><code>interface ft2232
ft2232_device_desc "STR9-comStick A"
ft2232_layout comstick
ft2232_vid_pid 0x0640 0x002C
jtag_speed 4
jtag_nsrst_delay 100
jtag_ntrst_delay 100
-</code></pre></p>
+</code></pre>
<p>Also, OpenOCD needs to know what's our target and its memory layout:</p>
-<p><pre><code>target arm966e little run_and_init 1 arm966e
+<pre><code>target arm966e little run_and_init 1 arm966e
run_and_halt_time 0 50
working_area 0 0x50000000 32768 nobackup
flash bank str9x 0x00000000 0x00080000 0 0 0
-flash bank str9x 0x00080000 0x00008000 0 0 0</code></pre></p>
+flash bank str9x 0x00080000 0x00008000 0 0 0</code></pre>
<p>This tells OpenOCD that our target is an ARM966-E running in little
endian mode, with two flash memory banks, one that starts at 0x0 and
it's 0x80000 bytes in size, and another one that starts at 0x80000 and
it's 0x8000 bytes in size. Finally, OpenOCD must know what's the name
-of our script file (this is the file that is used to pysically program
+of our script file (this is the file that is used to physically program
the CPU memory):</p>
-<p><pre><code>#Script used for FLASH programming
-target_script 0 reset str91x_flashprogram.script</code></pre></p>
+<pre><code>#Script used for FLASH programming
+target_script 0 reset str91x_flashprogram.script</code></pre>
<p>The contents of the str91x_flashprogram.script is very target-dependent:</p>
-<p><pre><code>wait_halt
+<pre><code>wait_halt
str9x flash_config 0 4 2 0 0x80000
flash protect 0 0 7 off
flash erase_sector 0 0 7
flash write_bank 0 main.bin 0
reset run
sleep 10
-shutdown</code></pre></p>
+shutdown</code></pre>
<p>I'm not even going to attempt to explain this one :) Basically it
unprotects the flash, erases it, writes the contents of "main.bin" to
flash, and then resets the CPU. If you need to flash a file with a
different name, the only thing you need to modify is the "main.bin" in
-the "flash write_bank" line.<br>
-To use all this, you need to tell OpenOCD to use our configuration file:</p>
+the "flash write_bank" line.</p>
+<p>To use all this, you need to tell OpenOCD to use our configuration file:</p>
-<p><pre><code>openocd-ftd2xx -f comstick.cfg<br></code></pre></p>
+<pre><code>openocd-ftd2xx -f comstick.cfg</code></pre>
<p>(<b>note</b>: under Windows, the OpenOCD executable name is often
@@ -244,47 +239,44 @@
the actualy name with your executable).</p>
<p>That's it for your OpenOCD crash course. I realise that there's much
more to learn, so here's a list of links with much better information
-on the subject:
+on the subject:</p>
<ul>
- <li><a target="_blank" href="http://www.hs-augsburg.de/%7Ehhoegl/proj/openocd/oocd-quickref.pdf">OpenOCD quick reference</a> card. (slightly outdated)</li>
- <li><a target="_blank" href="http://openfacts.berlios.de/index-en.phtml?title=OpenOCD_scripts">OpenOCD configuration examples</a> from the official OpenOCD wiki.</li>
- <li>An excellent page about using <a target="_blank" href="http://www.siwawi.arubi.uni-kl.de/avr_projects/arm_projects/openocd_intro/index.html">OpenOCD with ARM controllers</a>, with lots
+ <li><a href="http://www.hs-augsburg.de/%7Ehhoegl/proj/openocd/oocd-quickref.pdf">OpenOCD quick reference</a> card. (slightly outdated)</li>
+ <li><a href="http://openfacts.berlios.de/index-en.phtml?title=OpenOCD_scripts">OpenOCD configuration examples</a> from the official OpenOCD wiki.</li>
+ <li>An excellent page about using <a href="http://www.siwawi.arubi.uni-kl.de/avr_projects/arm_projects/openocd_intro/index.html">OpenOCD with ARM controllers</a>, with lots
of real life examples.</li>
- <li>An interesting <a target="_blank" href="http://forum.sparkfun.com/viewtopic.php?p=42079">topic on the SparkFun forum</a> about STR9 and OpenOCD.</li>
-</ul></p>
+ <li>An interesting <a href="http://forum.sparkfun.com/viewtopic.php?p=42079">topic on the SparkFun forum</a> about STR9 and OpenOCD.</li>
+</ul>
-<p><a name="str9files"></a></p>
-<h2>##Configuration files for STR9-comStick</h2>
+<a name="str9files" /><h2>Configuration files for STR9-comStick</h2>
<p>Download them below:</p>
-<p><a href="http://elua.berlios.de/other/comstick.cfg">comstick.cfg</a></p>
+<ul>
+ <li><a href="http://elua.berlios.de/other/comstick.cfg">comstick.cfg</a></li>
+ <li><a href="http://elua.berlios.de/other/str91x_flashprogram.script">str91x_flashprogram.script</a></li>
+ <li><a href="http://elua.berlios.de/other/comrst.cfg">comrst.cfg</a></li>
+ <li><a href="http://elua.berlios.de/other/str91x_reset.script">str91x_reset.script</a></li>
+</ul>
-<p><a href="http://elua.berlios.de/other/str91x_flashprogram.script">str91x_flashprogram.script</a></p>
-
-<p><a href="http://elua.berlios.de/other/comrst.cfg">comrst.cfg</a></p>
-
-<p><a href="http://elua.berlios.de/other/str91x_reset.script">str91x_reset.script</a></p>
-
-<p>The <b>comstick.cfg</b> configuration file is for prorgramming the
+<p>The <b>comstick.cfg</b> configuration file is for programming the
STR9-comStick. <b>comrst.cfg</b> is for resetting it. The comStick has a very
interesting habit: after you power it (via USB) it does not start
executing the code from the internal flash, you need to execute OpenOCD
with the comreset.cfg script to start it. <b>comrst.cfg</b> does exactly what
it says: executes a CPU reset (since the board doesn't have a RESET
-button). This is a very peculiar behaviour, and I'm not sure if it's
+button). This is a very peculiar behavior, and I'm not sure if it's
generic or it's only relevant to my particular comStick. I suspect that
the CPU RESET line isn't properly handled by the on-board USB-to-JTAG
converter, and the only solution I have for this is to execute this
script everytime you power the board and everytime you need to do a
-RESET.<br>
-Also, be sure to modify <b>str91x_flashprogram.script</b> if your image name is
+RESET.</p>
+<p>Also, be sure to modify <b>str91x_flashprogram.script</b> if your image name is
not <b>main.bin</b></p>
-<p><a name="lpc2888files"></a></p>
-<h2>##Configuration files for LPC2888</h2>
+<a name="lpc2888files" /><h2>Configuration files for LPC2888</h2>
<p>LPC2888 is quite a different animal. I couldn't find any "official"
LPC2888 configuration file for OpenOCD, so I had to learn how to write
@@ -301,41 +293,41 @@
corresponding line (<i>flash write_bank 0 main.bin 0</i>), then invoke openocd
like this:</p>
-<p><pre><code>openocd -f lpc2888.cfg<br></code></pre></p>
+<pre><code>openocd -f lpc2888.cfg</code></pre>
-<p>I'm using <a target="_blank" href="http://www.olimex.com/dev/arm-usb-tiny.html">ARM-USB-TINY</a>
+<p>I'm using <a href="http://www.olimex.com/dev/arm-usb-tiny.html">ARM-USB-TINY</a>
from Olimex, but it should be easy to use the script with any other
JTAG adapter (don't forget to change the script to match your adapter).</p>
-<h2><a name="str7files">##Configuration files for STR711FR2 (STR7 from ST)</a></h2>
+<a name="str7files" /><h2>#Configuration files for STR711FR2 (STR7 from ST)</h2>
<p>Download them below:</p>
-<p><a href="http://elua.berlios.de/other/str7prg.cfg">str7prg.cfg</a></p>
+<ul>
+ <li><a href="http://elua.berlios.de/other/str7prg.cfg">str7prg.cfg</a></li>
+ <li><a href="http://elua.berlios.de/other/str7_flashprogram.script">str7_flashprogram.script</a></li>
+ <li><a href="http://elua.berlios.de/other/str7rst.cfg">str7rst.cfg</a></li>
+ <li><a href="http://elua.berlios.de/other/str7_reset.script">str7_reset.script</a></li>
+</ul>
-<p><a href="http://elua.berlios.de/other/str7_flashprogram.script">str7_flashprogram.script</a></p>
-
-<p><a href="http://elua.berlios.de/other/str7rst.cfg">str7rst.cfg</a></p>
-
-<p><a href="http://elua.berlios.de/other/str7_reset.script">str7_reset.script</a></p>
-
<p>For STR7 I'm using the Yagarto OpenOCD build for Windows (repository
version 717, as described at the beginning of this tutorial). The
-<b>str7prg.cfg</b> configuration file is for prorgramming the STR9-comStick.
+<b>str7prg.cfg</b> configuration file is for programming the STR9-comStick.
<b>str7rst.cfg</b> is for resetting it (you probably won't need this one). I'm using a STR711FR2 heard board from
-<a target="_blank" href="http://www.sctec.com.br/content/view/101/30/">ScTec</a> to
+<a href="http://www.sctec.com.br/content/view/101/30/">ScTec</a> to
which I attached a few LEDs and a MAX3232 TTL to RS232 converter for
-the serial communication. The board comes with its own JTAG adadpter,
+the serial communication. The board comes with its own JTAG adapter,
but it uses a parallel interface, and since my computer doesn't have
-one, I used the <a target="_blank" href="http://www.olimex.com/dev/arm-usb-tiny.html">ARM-USB-TINY</a> from Olimex. To use them, invoke the OpenOCD executable like this:</p>
+one, I used the <a href="http://www.olimex.com/dev/arm-usb-tiny.html">ARM-USB-TINY</a> from Olimex. To use them, invoke the OpenOCD executable like this:</p>
-<p><pre><code>openocd-ftd2xx -f str7prg.cfg<br></code></pre></p>
+<pre><code>openocd-ftd2xx -f str7prg.cfg</code></pre>
<p>(<b>note</b>: under Windows, the OpenOCD executable name is often
"openocd-ftd2xx". Under Linux it's simply "openocd". Replace it with
-the actualy name with your executable).<br>
-Also, be sure to modify <b>str7_flashprogram.script</b> if your image name is
+the actualy name with your executable).</p>
+<p>Also, be sure to modify <b>str7_flashprogram.script</b> if your image name is
not <b>main.bin</b></p>
-</body></html>
+$$FOOTER$$
+
Modified: branches/eagle_mmc/doc/en/tutorials.html
===================================================================
--- branches/eagle_mmc/doc/en/tutorials.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/en/tutorials.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,15 +1,10 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Tutorials</title>
-
-<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);">
+$$HEADER$$
<h3>Tutorials</h3>
-<p>This section contains information about different tools and procedures related to <b>eLua</b>:
+<p>This section contains information about different tools and procedures related to <b>eLua</b>:</p>
<ul>
<li>building toolchains that can be used to build <b>eLua</b> itself.</li>
<li>running the standalone <b>eLua</b> (i386) version in different scenarios.</li>
<li>using OpenOCD to program <b>eLua</b> to various hardware platforms.</li>
-</ul></p>
-</body></html>
+</ul>
+$$FOOTER$$
+
Modified: branches/eagle_mmc/doc/en/using.html
===================================================================
--- branches/eagle_mmc/doc/en/using.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/en/using.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,17 +1,12 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Using eLua</title>
-
-<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);">
-<h3>Using eLua</h3><p> So, you already <a href="building.html">built</a> and <a href="installing.html">installed</a> <b>eLua</b>, and now it is time to (finally) have some fun with it :)
+$$HEADER$$
+<h3>Using eLua</h3>
+<p> So, you already <a href="building.html">built</a> and <a href="installing.html">installed</a> <b>eLua</b>, and now it is time to (finally) have some fun with it :)
You can compile <b>eLua</b> with either console over UART (by far the most popular) and console over TCP/IP (still experimental, but working quite well), so there are two different usage
scenarios for this (see <a href="building.html">building eLua</a> for details on how to select serial or TCP/IP console).</p>
<a name="uart"><h3>Using eLua over serial connections</h3></a>
<p>All you need to use <b>eLua</b> over a serial connection is your <b>eLua</b>
board connected to a PC running a terminal emulator program.<br>If
-you're using Windows, I strongly recommend <a target="_blank" href="http://www.ayera.com/teraterm/">TeraTerm</a>.
+you're using Windows, I strongly recommend <a href="http://www.ayera.com/teraterm/">TeraTerm</a>.
It's a freeware, it's very powerful and also easy to use. The native Hyper Terminal progam can do too, but give TeraTerm a chance, it's much better than HyperTerm IMO.<br>On
Linux,
you'll probably be stucked with minicom. It is not exactly intuitive
@@ -37,7 +32,7 @@
There's no universal rule here, it all depends on your board.
</p>
<a name="tcpip"><h3>Using eLua over TCP/IP connections</h3></a>
-<p>Things are even easier if you decide to enable console over TCP/IP:
+<p>Things are even easier if you decide to enable console over TCP/IP:</p>
<ul>
<li>make sure you know the address of your board. If you enabled static IPs (see <a href="building.html">building</a>) remember what you chose for the static IP; if DHCP is used instead, your
DHCP server should've added the address of the <b>eLua</b> board to your DNS. The board name is always "elua", so if you execute "ping elua" from a shell you should see that the board is
@@ -45,19 +40,19 @@
<li>telnet to the address of the board (or simply "telnet elua" if DHCP is used), and you'll be greeted with the shell prompt (if the shell is enabled, see the next paragraph for details).
Note that you can only have an active telnet session to the <b>eLua</b> board at a given time.</li>
</ul>
-</p>
+
<p>If you're under Windows, make sure you're using a proper telnet client, which basically means "just about everything <b>but</b> the build-in telnet client".
- <a target="_blank" href="http://www.chiark.greenend.org.uk/~sgtatham/putty/">PuTTY</a> is a very good and popular choice.</p>
+ <a href="http://www.chiark.greenend.org.uk/~sgtatham/putty/">PuTTY</a> is a very good and popular choice.</p>
<a name="pc"><h3>Using standalone eLua on PC</h3></a>
<p>If you build <b>eLua</b> for the i386 platform, you can boot your PC directly in <b>eLua</b>! No underlying OS, nothing but plain <b>eLua</b>. It won't have any actual peripherals to
access, but it can use the <b>term</b> module to run <i>hangman.lua</i> and <i>life.lua</i>, as well as other samples, which makes it a nice demo :) Follow <a href="installing_i386.html">
this link</a> for specific informations about the i386 port. </p>
-<a name="shell"><h3><a name="shell"></a>The eLua shell</h3></a>
+<a name="shell"><h3>The eLua shell</h3></a>
<p>No matter what's your physical connection (serial, TCP/IP or you PC's monitor after booting <b>eLua</b>), after you setup the PC-<b>eLua</b> board connection (if applicable) and press
the "RESET" button on your board or simply press ENTER if you're using the serial connection, you should see the <b>eLua</b> shell prompt (if you enabled the shell in your build, as described <a href="building.html">here</a>). The shell is a simple
- interactive command interpreter that allows you to:
+ interactive command interpreter that allows you to:</p>
<ul>
<li>get help on shell usage with the help command</li>
<li>run the Lua interpreter in interactive mode just like you'd do on a desktop machine</li>
@@ -65,7 +60,7 @@
<li>upload a Lua source file via XMODEM and execute in on board</li>
<li>query the eLua version</li>
<li>list files on eLua file systems</li>
-</ul></p>
+</ul>
<p>A detailed description of all the shell commands is given below.</p>
<h2>help</h2>
@@ -76,7 +71,7 @@
<h2>recv</h2>
<p>Allows you to receive a Lua file (either source or compiled bytecode) via
-XMODEM and execute it on your board. To use this, your <b>eLua</b> taret image must be built with support for XMODEM
+XMODEM and execute it on your board. To use this, your <b>eLua</b> target image must be built with support for XMODEM
(see <a href="building.html">building</a> for details).Also, your terminal emulation program must
support sending files via the XMODEM protocol. Both XMODEM with checksum and XMODEM with CRC are supported, but only XMODEM with 128
byte packets is allowed (XMODEM with 1K packets won't work).
@@ -99,18 +94,18 @@
<li>character escaping is not implemented. For example, the next command won't work
because of the ' (simple quotes) escape sequences:
-<p><pre><code>eLua# lua -e 'print(\'Hello, World!\')' -i<br>
-Press CTRL+Z to exit Lua<br>
-lua: (command line):1: unexpected symbol near ''</code></pre></p>
+<pre><code>eLua# lua -e 'print(\'Hello, World!\')' -i
+Press CTRL+Z to exit Lua
+lua: (command line):1: unexpected symbol near ''</code></pre>
<p>However, if you use both '' (simple quotes) and "" (double quotes) for string quotin , it will work:</p>
-<p><pre><code>eLua# lua -e 'print("Hello, World")' -i
+<pre><code>eLua# lua -e 'print("Hello, World")' -i
Press CTRL+Z to exit Lua
Lua 5.1.4 Copyright (C) 1994-2008 Lua.org, PUC-Rio
-Hello,World</code></pre></p></li></ul>
-<p>If you want to execute a file from the <a href="">##ROM file system</a>, remember to prefix it with <i>/rom</i>. For example, to execute <b>hello.lua</b>, do this:</p>
-<p><pre><code>$ lua /rom/hello.lua</code></pre></p>
+Hello,World</code></pre></li></ul>
+<p>If you want to execute a file from the <a href="arch_romfs.html">ROM file system</a>, remember to prefix it with <i>/rom</i>. For example, to execute <b>hello.lua</b>, do this:</p>
+<pre><code>$ lua /rom/hello.lua</code></pre>
<h2>ls or dir</h2>
<p>Shows a list of all the files in the filesystems used by <b>eLua</b> (currently only the ROM file system), as well as their size and the total size of the given file system.</p>
<h2>exit</h2>
@@ -121,7 +116,7 @@
different hardware platform. For example, the process of compiling the <b>eLua</b> binary image on
a PC for your <b>eLua</b> board is cross-compiling. Lua can be cross-compiled, too. By cross-compiling Lua
to bytecode on a PC and executing the resulting bytecode directly on your <b>eLua</b>
-board you have some important advantages:
+board you have some important advantages:</p>
<ul>
<li><b>speed</b>: the Lua compiler on the <b>eLua</b> board doesn't have to compile your Lua
source code, it just executes the compiled bytecode.</li>
@@ -133,27 +128,27 @@
running the bytecode instead. Also, compiling large Lua programs on your
<b>eLua</b> board can lead to stack overflows, which in turn leads to very
hard to find errors.</li>
-</ul></p>
+</ul>
<p>In order to use cross-compilation, the two Lua targets (in this case your desktop PC and your <b>eLua</b> board) must be compatible
(they should have the same data types, with the same size and the same memory
representation). This isn't true all the time. For example, some gcc toolchains for ARM targets use a very specific representation for double precision numbers (called FPA
format) by default, which makes bytecode files generated on the PC with the regular Lua compiler useless on
-ARM boards. Other toolchains don't have this problem. Other targets (like AVR32) are big endian, as opposed to Intel PCs that are little endian.<br>
-To overcome this kind of problems, a "Lua cross-compilation patch" was posted on the
+ARM boards. Other toolchains don't have this problem. Other targets (like AVR32) are big endian, as opposed to Intel PCs that are little endian.</p>
+<p>To overcome this kind of problems, a "Lua cross-compilation patch" was posted on the
Lua mailing list a while ago, and it was further modified as part of the <b>eLua</b>
project to work with ARM targets. This is how to use it (the following
instructions were tested on Linux, not Windows, but they should work on Windows
-too with little or no tweaking):
+too with little or no tweaking):</p>
<ul>
-<li>first, make sure that your PC has already a build system intalled (gcc,
+<li>first, make sure that your PC has already a build system installed (gcc,
binutils, libc, headers...). You'll also need scons. The good news is that
you should have it already installed, since otherwise you won't be able to
build even regular <b>eLua</b> (see <a href="building.html">building</a> for more in-depth instructions).</li>
-<li>from the <b>eLua</b> base directory, issue this command:</li>
- <p><pre><code>$ scons -f cross-lua.py</code></pre></p></ul>
-<p>You should get a file called <i>luac</i> in the same directory after this. It's almost the same as the regular Lua compiler, but it has a few arguments that deal with differences between
-different targets (shown below in bold):</p>
-<p><pre><code>usage: ./luac [options] [filenames].
+<li>from the <b>eLua</b> base directory, issue this command:
+ <pre><code>$ scons -f cross-lua.py</code></pre></li>
+</ul>
+<p>You should get a file called <i>luac</i> in the same directory after this. It's almost the same as the regular Lua compiler, but it has a few arguments that deal with differences between different targets (shown below in bold):</p>
+<pre><code>usage: ./luac [options] [filenames].
Available options are:
- process stdin
-l list
@@ -164,9 +159,9 @@
<b>-cci bits cross-compile with given integer size
-ccn type bits cross-compile with given lua_Number type and size
-cce endian cross-compile with given endianness ('big' or 'little')</b>
--- stop handling options</code></pre></p>
+-- stop handling options</code></pre>
<p>All it's left to do now is to use the table below to figure out what are the right parameters for using the cross-compiler:</p>
-</p><table style="text-align: left;" class="table_center">
+<table style="text-align: left;" class="table_center">
<tbody>
<tr>
<th style="text-align: left;">eLua image type</th>
@@ -177,31 +172,31 @@
<tr>
<td>Floating point (lua)</td>
<td>ARM7TDMI<br>Cortex-M3<br>ARM966E-S</td>
- <td><a href="toolchains.html">arm-gcc</a>
+ <td><a href="toolchains.html">arm-gcc</a></td>
<td><code>./luac -ccn float_arm 64 -cce little -o <script.luac> -s <script.lua></code></td>
</tr>
<tr>
<td>Floating point (lua)</td>
<td>ARM7TDMI<br>Cortex-M3<br>ARM966E-S</td>
- <td><a href="toolchains.html">codesourcery</a>
+ <td><a href="toolchains.html">codesourcery</a></td>
<td><code>./luac -ccn float 64 -cce little -o <script.luac> -s <script.lua></code></td>
</tr>
<tr>
<td>Integer (lualong)</td>
<td>ARM7TDMI<br>Cortex-M3<br>ARM966E-S</td>
- <td><a href="toolchains.html">arm-gcc<br>codesourcery</a>
+ <td><a href="toolchains.html">arm-gcc<br>codesourcery</a></td>
<td><code>./luac -ccn int 32 -cce little -o <script.luac> -s <script.lua></code></td>
</tr>
<tr>
<td>Floating point (lua)</td>
<td>AVR32</td>
- <td><a href="toolchains.html">avr32-gcc</a>
+ <td><a href="toolchains.html">avr32-gcc</a></td>
<td><code>./luac -ccn float 64 -cce big -o <script.luac> -s <script.lua></code></td>
</tr>
<tr>
<td>Integer (lualong)</td>
<td>AVR32</td>
- <td><a href="toolchains.html">avr32-gcc</a>
+ <td><a href="toolchains.html">avr32-gcc</a></td>
<td><code>./luac -ccn int 32 -cce big -o <script.luac> -s <script.lua></code></td>
</tr>
</tbody>
@@ -213,7 +208,5 @@
<li>write it to <a href="arch_romfs.html">the ROM file system</a> and execute it from there.</li>
<li>use the <i>recv</i> command from <a href="using.html#shell">the shell</a> to upload it to the board using a serial connection.</li>
</ul>
-<p>
-</p>
-</body></html>
+$$FOOTER$$
Modified: branches/eagle_mmc/doc/en/versionhistory.html
===================================================================
--- branches/eagle_mmc/doc/en/versionhistory.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/en/versionhistory.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,20 +1,52 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>eLua version history</title>
-
-<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);">
+$$HEADER$$
<h3>eLua version history</h3>
<p>The table below presents the history of all official <b>eLua</b> releases (in reversed order, newest to oldest).</p>
-</p><table style="text-align: left" class="table_center">
+<table style="text-align: left" class="table_center">
<tbody>
<tr>
<th style="text-align: left;">Version</th>
<th style="text-align: center;">Release date</th>
<th style="text-align: center;">Description</th>
+</tr>
<tr>
+ <td align="center" style="color: rgb(255, 102, 0);">##TODO</td>
+ <td align="center">##TODO.11.2009</td>
+ <td>
+ <ul>
+ <li>Added support for STR-E912 board</li>
+ <li>Examples extended to support STR-E912 board</li>
+ <li>Doc/site content enhancements</li>
+ <li>More PT content</li>
+ <li>Platform Specific PIO module added to support STR9 goodies</li>
+ <li>Added the Lua EGC (Emergency Garbage Collection) patch</li>
+ <li>(Added initial support for generic interrupt handling)</li>
+ <li>(Added support for NXP)</li>
+ <li>(##Added support for FAT FS on SD/MMC Cards## {may not come in the
+ next minor release yet})</li>
+</ul>
+</td>
+<tr>
+ <td align="center" style="color: rgb(255, 102, 0);">0.6</td>
+ <td align="center">06.10.2009</td>
+ <td>
+ <ul>
+ <li>License changed to MIT</li>
+ <li>Web page and documentation completely redesigned</li>
+ <li>Documentation available offline</li>
+ <li>Added support for AVR32 CPUs</li>
+ <li>Added support for STM32 Cortex-M3 CPUs</li>
+ <li>Added ADC module with support for moving average filters</li>
+ <li>Added support for multiple toolchains</li>
+ <li>Added an ls (or dir) shell command</li>
+ <li>Added new examples: pong, tetrives, spaceship (games), logo (graphics), adcpoll, adcscope (ADC operations)</li>
+ <li>Added the LTR (Lua Tiny RAM) patch</li>
+ <li>ROM FS content can be specified per board now</li>
+ <li>API semantic revisions (old code might not be compatible)</li>
+</ul>
+</td>
+</tr>
+<tr>
<td align="center" style="color: rgb(255, 102, 0);">0.5</td>
<td align="center">01.11.2008</td>
<td><ul>
@@ -79,7 +111,6 @@
<li>You can download binary file images from the "files" section, so you don't need to compile <b>eLua</b> yourself</li>
</ul></td>
</tr>
-</tr>
<tr>
<td align="center" style="color: rgb(255, 102, 0);">0.1</td>
<td align="center">11.08.2008</td>
@@ -87,4 +118,4 @@
</tr>
</tbody>
</table>
-</body></html>
+$$FOOTER$$
Added: branches/eagle_mmc/doc/images/En.jpg
===================================================================
--- branches/eagle_mmc/doc/images/En.jpg 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/images/En.jpg 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1 @@
+ÿØÿà
\ No newline at end of file
Added: branches/eagle_mmc/doc/images/Pt.jpg
===================================================================
--- branches/eagle_mmc/doc/images/Pt.jpg 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/images/Pt.jpg 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1 @@
+ÿØÿà
\ No newline at end of file
Copied: branches/eagle_mmc/doc/images/barlineleft.png (from rev 525, branches/eagle_mmc/doc/wb_img/barlineleft.png)
===================================================================
(Binary files differ)
Copied: branches/eagle_mmc/doc/images/barlineright.png (from rev 525, branches/eagle_mmc/doc/wb_img/barlineright.png)
===================================================================
(Binary files differ)
Copied: branches/eagle_mmc/doc/images/blank.png (from rev 525, branches/eagle_mmc/doc/wb_img/blank.png)
===================================================================
(Binary files differ)
Added: branches/eagle_mmc/doc/images/eLuaLogo.png
===================================================================
--- branches/eagle_mmc/doc/images/eLuaLogo.png 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/images/eLuaLogo.png 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,32 @@
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+++ branches/eagle_mmc/doc/images/eLuaLogo.svg 2009-11-06 02:08:32 UTC (rev 526)
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Copied: branches/eagle_mmc/doc/images/elua_arch.png (from rev 525, branches/eagle_mmc/doc/wb_img/elua_arch.png)
===================================================================
--- branches/eagle_mmc/doc/wb_img/elua_arch.png 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/images/elua_arch.png 2009-11-06 02:08:32 UTC (rev 526)
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--- branches/eagle_mmc/doc/menu.css 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/menu.css 2009-11-06 02:08:32 UTC (rev 526)
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+.rightarrowpointer {
+ border:0 none;
+ left: 149px;
+ width: 12px;
+ height: 12px;
+ padding-top: 3px;
+ position: absolute;
+}
+
+#nav {
+ font: bold 12px "Lucida Grande", "Trebuchet MS", Verdana, Helvetica, sans-serif;
+ float: left;
+ margin-left: 8px;
+ padding-top: 5px;
+}
+
+#nav ul { /* all lists */
+ padding: 0;
+ margin: 0;
+ margin-top: 5px;
+ margin-bottom: 10px;
+ list-style: none;
+ float : left;
+ border: 1px solid #9A9A9A;
+ width: 164px;
+}
+
+#nav li { /* all list items */
+ position : relative;
+ float : left;
+ line-height : 1.25em;
+ background: #F2F2F2; /*light gray background*/
+ width: 164px;
+}
+
+#nav li ul { /* second-level lists */
+ font-size:11px;
+ font-weight:normal;
+ color: black;
+ border-color:black;
+ border-style:solid;
+ position : absolute;
+ left: -999em;
+ margin-top : -21px;
+ margin-left: 164px;
+}
+#nav li ul a { /* second-level lists */
+ padding:4px 5px;
+ color: black;
+}
+
+#nav li ul ul { /* third-and-above-level lists */
+ left: -999em;
+}
+
+#nav li ul ul ul, #nav li ul ul ul li { /* third-and-above-level lists */
+ width: 200px;
+}
+
+#nav li ul ul ul li ul {
+ margin-left: 200px;
+}
+
+#nav li ul ul ul .rightarrowpointer { /* third-and-above-level lists */
+ left: 185px;
+}
+
+#nav li a {
+ display: block;
+ width: auto;
+ color: #00014e;
+ padding: 2px 0;
+ padding-left: 5px;
+ text-decoration: none;
+ border-bottom: 1px solid #B5B5B5;
+}
+
+#nav li a.current{
+ text-decoration: none;
+ text-align: left;
+ background: #FFCC33;
+ color: #00014e;
+}
+
+#nav ul li.sep {
+ padding: 2px 0;
+ text-decoration: none;
+ text-align: center;
+ border-bottom: 1px solid #B5B5B5;
+ background: #0B0C79;
+ color: white;
+}
+
+#nav ul li.current{
+ padding: 2px 0;
+ padding-left: 5px;
+ width: 159px;
+ text-decoration: none;
+ text-align: left;
+ border-bottom: 1px solid #B5B5B5;
+ background: #FFCC33;
+ color: #00014e;
+}
+
+#nav li a:hover {
+ color : white;
+ background-color : black;
+}
+
+#nav ul li a:visited, #nav ul li a:active{
+color: #00014e;
+}
+
+#nav li ul a:visited, #nav li ul a:active{
+color: black;
+}
+
+#nav li:hover ul ul, #nav li:hover ul ul ul, #nav li.sfhover ul ul, #nav li.sfhover ul ul ul {
+ left: -999em;
+}
+
+#nav li:hover ul, #nav li li:hover ul, #nav li li li:hover ul, #nav li.sfhover ul, #nav li li.sfhover ul, #nav li li li.sfhover ul { /* lists nested under hovered list items */
+ left: auto;
+}
+
+#nav li a:hover, #nav li a.selected{
+/* color: white; */
+/* background-color: black; */
+/* save ##### */
+background: #FFCC33;
+color: 00014e;
+}
+
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--- branches/eagle_mmc/doc/pt/arch.html 2009-11-06 02:08:17 UTC (rev 525)
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+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
+<html><head>
+<h3>A arquitetura eLua</h3>
+<p>Esta seção apresenta em detalhes, a concepção e implementação de <b>eLua</b>. Foi concebida como um guia, principalmente para os desenvolvedores <b>eLua</b>,
+ mas contém informação que pode ser também útil também para usuários de <b>eLua</b>. Um exemplo é o capítulo sobre o <a href="arch_romfs.html">sistema de arquivos ROM</a>.
+ Além disso, ao ler a <a href="arch_overview.html">visão geral da arquitetura eLua</a> você vai ter uma boa visão da estrutura geral de <b>eLua</b>,
+ que irá ajudar, não importa se você é um desenvolvedor ou não.</p>
+<p>Antes de nos aprofundarmos nisso, vá para a <a href="downloads.html">seção de downloads</a> e baixe o código fonte do <b>eLua</b>, é muito mais fácil seguir esta seção acompanhando pelo código-fonte.</p>
+</body></html>
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--- branches/eagle_mmc/doc/en/arch_coding.html 2009-11-06 02:08:17 UTC (rev 525)
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+$$HEADER$$
+<h3>Estilo de codificação em eLua</h3>
+<p>Esta seção tem o objetivo de apresentar o estilo de codificação em <b>eLua</b> que deve ser seguido por todo desenvolvedor. Segue abaixo as regras de codificação <b>eLua</b>:
+<ol>
+ <li>Deve-se formatar o texto adequadamente. Exemplos ("por favor, preste atenção nas regras de espaçamento, pois resumem-se em acrescentar espaços em tudo, com o objetivo de tornar mais fácil a leitura do código"):
+ <p><pre><code>i = 3 (not i=3)
+a = ( a + 5 ) / 3
+for( i = 0; i < 10; i++ ) ...
+if( ( i == 5 ) && ( a == 10 ) ) ...
+unsigned i = ( unsigned )p;
+void func( int arg1, const char* arg2 ) ...</code></pre></p></li>
+ <li><b>Indentação</b>: Use dois espaços para toda identação. Novamente, <b>ESPAÇOS</b>. <b>NÃO USE TABS</b>; isto é importante (e felizmente fácil de lembrar :) ).
+ Existem muitos exemplos onde tabs estragam completamente a clareza do código fonte. A maioria dos editores de texto têm a opção de "inserção de tabs ao invés de espaços";
+ utilize-a e configure o tamanho do TAB para 2.<br>
+ Além disso, idente "{" e "}" sobre suas prórias linhas:
+ <p><pre><code>if( i == 2 )
+{
+ // algum código aqui
+}
+else
+{
+ // mais algum código aqui
+}</code></pre></p>
+
+ Ou:
+<p><pre><code>void f( int i )
+{
+ // function code
+}</code></pre></p>
+
+Sempre que possÃvel, não cerque um comando com {}. Por exemplo, faça isso:
+
+<p><pre><code>if( i == 2 )
+ return;</code></pre></p>
+
+ ao invés disso:
+<p><pre><code>if( i == 2 )
+{
+ return;
+}</code></pre></p>
+
+Além disso, siga a regra de "um comando por linha". Em outras palavras, não faça isso:
+
+<p><pre><code>if( i == 2 ) return;</code></pre></p>
+
+ao invé disso, faça:
+
+<p><pre><code>if( i == 2 )
+ return;</code></pre></p>
+
+Observe que o código <b>eLua</b> não usa espaço entre o nome da função e sua lista de parâmetros quando de sua chamada/definição (como no código Lua, por exemplo). So do this:
+
+<p><pre><code>void f( int i )
+{
+ // function code here
+}
+
+f( 2 ); // function call</code></pre></p>
+
+instead of this:
+
+<p><pre><code>void f ( int i )
+{
+ // function code here
+}
+
+f ( 2 ); // function call</code></pre></p></li>
+<li><b>line terminators</b>: <b>THIS IS IMPORTANT TOO!</b> Use UNIX style (LF) line terminators, not DOS (CR/LF) or old Mac (CR) line terminators.</li>
+<li><b>identifier names</b>: use a "GNU-style" here, with underlines and all lowercase:
+
+ <p><pre><code>int simple;
+double another_identifier;
+char yes_this_is_OK_although_quite_stupid;</code></pre></p>
+
+As opposed to:
+
+ <p><pre><code>int Simple1;
+double AnotherIdentifier;
+char DontEvenThinkAboutWritingSomethingLikeThis;</code></pre></p>
+<b>DO NOT USE HUNGARIAN NOTATION</b> (like iNumber, sString, fFloat ... if you don't know what that is, it's fine, as it means that we don't need to worry about it :) ). It has its advantages
+when used properly, it's just not for <b>eLua</b>.
+</li>
+<li><b>constants in code</b>: don't ever write something like this:
+
+ <p><pre><code>if( key == 10 )
+ sys_ok();
+else if( key == 5 )
+ phone_dial( "911" );
+else if( key == 666 )
+{
+ while( user_is_evil() )
+ exorcize_user();
+}
+else if( key == 0 )
+ sys_retry();
+else
+ sys_error();</code></pre></p>
+
+Instead, define some constants with meaningful names (via enums or even #define) and write like this:
+
+ <p><pre><code>if( key == KEY_CODE_OK )
+ sys_ok();
+else if( key == KEY_CODE_FATAL_ERROR )
+ phone_dial( "911" );
+else if( key == KEY_CODE_COMPLETELY_EVIL )
+{
+ while( user_is_evil() )
+ exorcize_user();
+}
+else if( key == KEY_CODE_NONE )
+ sys_retry();
+else
+ sys_error();</code></pre></p>
+You can see in this example an accepted violation of the "one statement per line" rule: it's OK to write "else if (newcondition)" on the same line.</li>
+
+<li>use specific data types as much as possible. In this context, <b>specific data types</b> refers to generic types that have the same size on all
+ platforms. They are defined by each platform in turn and their meaning is given below:
+ <ul>
+ <li><b>s8</b>: signed 8-bit integer</li>
+ <li><b>u8</b>: unsigned 8-bit integer</li>
+ <li><b>s16</b>: signed 16-bit integer</li>
+ <li><b>u16</b>: unsigned 16-bit integer</li>
+ <li><b>s32</b>: signed 32-bit integer</li>
+ <li><b>u32</b>: unsigned 32-bit integer</li>
+ <li><b>s64</b>: signed 64-bit integer</li>
+ <li><b>u64</b>: unsigned 64-bit integer</li>
+ </ul>
+ By writing your code to take advantage of these specific data types you ensure high portability of the code amongst different hardware platforms. Don't
+ overuse this rule though. For example, a <b>for</b> loop has generally an <b>int</b> index, which is perfectly fine. But when you specify a timeout that
+ must fit in 32 bits, definitely declare it as <b>u32 to</b> instead of <b>unsigned int to</b>.
+</li>
+
+<li><b>endianness</b>: remember that <b>eLua</b> runs on both little endian and big endian architectures, and write your code accordingly.</li>
+
+<li><b>comments</b>: we generally favour C++ style comments (//), but it's perfectly OK to use C style (/**/) comments. Automatic documentation generators like Doxygen aren't encouraged, since
+ they tend to make the programmer overdocument the code to the point where it becomes hard to read because of the documentation alone. Ideally, you'd neither overdocument, nor
+ underdocument your code; just document it as much as you think it's needed, without getting into too much details, but also without omitting important information. In particular, DON'T do this:
+
+ <p><pre><code>// This function returns the sum of two numbers
+// Input: n1 - first number
+// Input: n2 - the second number
+// Output: the sum of n1 and n2
+int sum( int n1, int n2 )
+{
+ return n1 + n2;
+}</code></pre></p>
+
+ When something is self-obvious from the context, documenting it more is pointless and decreases readability.</li>
+<li><b>pseudo name-spaces</b>: since we don't have namespaces in C, I like to "emulate" them by prefixing anything (constants, variables, functions) in a file with something that identifies that
+ file uniquely (most likely its name, but this is not a definite rule). For example, a file called "uart.c" would look like this:
+
+ <p><pre><code>int uart_tx_count, uart_rx_count;
+
+int uart_receive( unsigned limit )...
+unsigned uart_send( const char *buf, unsigned size )...</code></pre></p>
+</li>
+
+</ol></p>
+<p>Also, if you're using 3rd party code (from a library/support package for example) making it follow the above rules is nice, but not mandatory. Focus on functionality and writing your own code properly, and come back to indent other people's code when you really don't have anything better to do with your time.</p>
+$$FOOTER$$
+
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--- branches/eagle_mmc/doc/en/arch_con_term.html 2009-11-06 02:08:17 UTC (rev 525)
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+$$HEADER$$
+<h3>eLua consoles and terminals</h3>
+<p>In <b>eLua</b>, a <b>console</b> and a <b>terminal</b> serve two related, but different purposes:</p>
+<ul>
+ <li>the <b>console</b> takes care of basic user input/output. They come in two flavours: serial consoles and TCP/IP consoles (note that the two can't coexist at the same time).</li>
+ <li>the <b>terminal</b> enhances the console in order to take advantage of ANSI terminals and their advanced control functions, like explicit cursor positioning, clear screen and others. At this
+ time, terminals work only over serial connections, not over TCP/IP (like consoles).</li>
+</ul>
+<p>Both components can be enabled and disabled as needed (they don't rely on each other). See <a href="building.html">building eLua</a> for details on how to enable and disable components.</p>
+<h2>Serial consoles</h2>
+<p>The serial console input/output is handled by a generic layer (<i>src/newlib/genstd.c</i>) that can be used to easily adapt the console subsystem to a variety of input/output devices.
+ It needs just two functions, one for displaying characters and another one for receiving input with timeout:</p>
+<pre><code>// Send/receive function types
+typedef void ( *p_std_send_char )( int fd, char c );
+typedef int ( *p_std_get_char )( s32 to );
+</code></pre>
+<p>(the <b>send</b> faction gets an additional <b>fd</b> parameter that you can use to differentiate between the standard C stdout and stderr output streams).</p>
+<p>To set them, use <b>std_set_send_func</b> and <b>std_set_get_func</b>, both defined in <i>inc/newlib/getstd.h</i>. Usually they are called from <i>src/common.c</i> and configured to work
+ over UART by default:</p>
+<pre><code>// *****************************************************************************
+// std functions and platform initialization
+
+static void uart_send( int fd, char c )
+{
+ fd = fd;
+ platform_uart_send( CON_UART_ID, c );
+}
+
+static int uart_recv( s32 to )
+{
+ return platform_uart_recv( CON_UART_ID, TERM_TIMER_ID, to );
+}
+
+void cmn_platform_init()
+{
+ // Set the send/recv functions
+ std_set_send_func( uart_send );
+ std_set_get_func( uart_recv );
+}
+</code></pre>
+<p>If you need another type of serial console device (for example a dedicated console running over a SPI connection) just call <i>std_set_send_func/std_set_get_func</i> with the appropriate
+ function pointers.</p>
+<p>To enable serial consoles, define the <b>BUILD_CON_GENERIC</b> macro in your platform's <b>platform_conf.h</b> file.</p>
+<h2>TCP/IP consoles</h2>
+<p>TCP/IP consoles have the same functionality as serial consoles, but they work over a TCP/IP connection using the telnet protocol. As they integrate directly with the TCP/IP subsystem,
+ they don't have the same generic function based mechanism as serial consoles. To enable TCP/IP consoles, define the <b>BUILD_CON_TCP</b> macro in your platform's <b>platform_conf.h</b> file.</p>
+<h2>Terminals</h2>
+<p>Besides standard stdio/stdout/stderr support provided by consoles, <b>eLua</b> uses the "term" module to access ANSI compatible terminal emulators. It is designed to be as flexible as
+ possible, thus allowing a large number of terminal emulators to be used. To enable terminal support, add <b>BUILD_TERM</b> in your platform's <b>platform_conf.h</b> file. To use it, initialize
+ it with a call to <b>term_init</b>:</p>
+<pre><code>...........................
+// Terminal output function
+typedef void ( *p_term_out )( u8 );
+// Terminal input function
+typedef int ( *p_term_in )( int );
+// Terminal translate input function
+typedef int ( *p_term_translate )( u8 );
+...........................
+// Terminal initialization
+void term_init( unsigned lines, unsigned cols, p_term_out term_out_func,
+ p_term_in term_in_func, p_term_translate term_translate_func );
+</code></pre>
+<p>The initialization function takes the physical size of the terminal emulator window (usually 80 lines and 25 cols) and three function pointers:</p>
+<ul>
+ <li><b>p_term_out</b>: this function will be called to output characters to the terminal. It receives the character to output as its single parameter.</li>
+ <li><b>p_term_in</b>: this function will be called to read a character from the terminal. It receives a parameter that can be either TERM_INPUT_DONT_WAIT (in which case the function returns
+ -1 immediately if no character is available) or TERM_INPUT_WAIT (in which case the function will wait for the character).</li>
+ <li><b>p_term_translate</b>: this function translates terminal-specific codes to "term" codes. The "term" codes are defined in an enum from <i>inc/term.h</i>:
+<pre><code>...........................
+_D( KC_UP ),\
+_D( KC_DOWN ),\
+_D( KC_LEFT ),\
+...........................
+_D( KC_ESC ),\
+_D( KC_UNKNOWN )
+...........................</code></pre>
+By using this function, it is possible to adapt a very large number of "term emulators" to <b>eLua</b>. For example, you might want to run eLua in a "standalone
+ mode" that does not require a PC at all, just an external LCD display and maybe a keyboard for data input. Your <b>eLua</b> board can connect to this standalone terminal using its
+ I/O pins or built in peripherals, for example via SPI. By writing the three functions described above, the effort of making <b>eLua</b> work with this new type of device is minimal,
+ and also writing an "ANSI emulator" for your terminal device is not hard.</li></ul>
+<p>For an example, see <i>src/main.c</i>, where these functions are implemented for an UART connection with a terminal emulator program running on PC.</p>
+<p><b>eLua</b> also provides a Lua module (called <b>term</b>) that can be used to access ANSI terminal. See <a href="refman_gen_term.html">the term module API</a> for a full description of this module.</p>
+$$FOOTER$$
+
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--- branches/eagle_mmc/doc/en/arch_ltr.html 2009-11-06 02:08:17 UTC (rev 525)
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+$$HEADER$$
+<h3>Modules and LTR</h3>
+<p>LTR (Lua Tiny RAM) is a Lua patch (written specifically for <b>eLua</b> by Bogdan Marinescu) that significantly decreases the RAM usage of Lua scripts,
+ thus making it possible to run large Lua programs on systems with limited RAM. This section gives a full description of LTR. If you're writing <b>eLua</b>
+ modules, this page will certainly be of interest to you, as it shows how to interact with LTR in a portable and easy to configure way.</p>
+<h2>Motivation</h2>
+<p>The main thing that drove me to write this patch is the relatively high Lua memory consumption at startup (obtained by running
+ <i>lua -e "print(collectgarbage'count')"</i>). It's about 17k for regular Lua 5.1.4, and more than 25k for some of eLua's platforms. These figures are
+ mainly a result of registering many different modules to Lua. Each time you register a module (via luaL_register) you create a new table and populate
+ it with the module's methods. But a table is a read/write datatype, so luaL_register is quite inefficient if you don't plan to do any write operations
+ on that table later (adding new elements or manipulating existing ones). I found that I almost never have to do any such operations on a module's
+ table after it was created, I just query it for its elements. So, from the perspective of someone worried about memory usage, I'd rather have a
+ different type of table in this case, one that wouldn't need any RAM at all, since it would be read only, so it could reside entirely in ROM.</p>
+ <p>There's one more thing related to this context: Lua's functions. While Lua does have the concept of C functions, they still require data structures
+ that need to be allocated (see lua_pushcclosure in lapi.c for details), as they can have upvalues or environments. Once again, this isn't something I
+ use often with eLua. Most of the times my functions (especially the ones exported by a C module) are very simple, and they don't need upvalues or
+ environments at all. In conclusion, having a "simpler" function type would improve memory usage.
+</p>
+<h2>Details</h2>
+<p>The patch adds two new data types to Lua. Both or them are based on the lightuserdata type already found in Lua, and they share the same basic
+ attributes: they don't need to be dynamically allocated (as they're just pointers on steroids) and they're compared in the same way lightuserdatas
+ are compared (by value). And of course, they are not collectable, so the garbage collector won't have anything to do with them. The new types are:</p>
+<ol>
+<li><b>lightfunctions</b>: these are "simple" functions, in the sense that they can't have upvalues or environments. They are just pointers to regular
+ C functions. Other than that, you can use them from Lua just as you'd use any other function.</li>
+
+<li><b>rotables</b>: these are read-only tables, but unlike the read-only tables that one can already implement in Lua with metamethods, they have a
+ very specific property: they don't need any RAM at all. They are fully constant, so they can be read directly from ROM. They have a number of
+ special features and limitations when compared with a regular table:
+<ul>
+ <li>rotables can only contain values of type "lightfunction", lua_Number or pointers to other rotables.</li>
+ <li>you can't add/delete/modify elements from rotables (obviously). However, rotables will honour the "__newindex" metamethod.</li>
+ <li>you can use rotables as metatables for both "regular" tables and for Lua types (via debug.setmetatable)</li>
+ <li>a rotable can have another rotable (or tself) as a metatable</li>
+ <li>you can iterate over rotables with pairs/ipairs/next just as you do with "regular" tables.</li>
+</ul></li></ol>
+<p>Just as with lightuserdata, you can only create lightfunctions and rotables from C code, never from Lua itself.</p>
+<h2>Testing</h2>
+<p>I tested my patch with the (<a target="_blank" href="http://lua-users.org/lists/lua-l/2006-03/msg00723.html">Lua 5.1 test suite</a>). The test suite
+ was an excellent testing tool. I thought I had the patch ready until I found the test suite and ran it. After another week of work, I had something
+ that could be called functional :)</p>
+<p>I tested everything via "make generic", which is how I always build Lua for my embedded environments. This means (among other things) that I didn't
+test pipes and dynamic module loading, although I don't see why they wouldn't work.</p>
+<p>I never tested the patch in a multithreaded environment with more threads running different lua_States. I never even used regular Lua like this,
+so I can't make asumptions about how my patch would behave in a multithreaded environment. It doesn't use any global or static variables, but you
+might encounter other problems with it.</p>
+<h2>Results</h2>
+<p>The table below summarizes the RAM usage in KBytes (as obtained by running <i>lua -e "print(collectgarbage'count')"</i> from the <b>eLua</b> shell).
+ <b>OPT=0</b> is LTR's "compatibility mode" (basically this means that the patch is disabled, so you're running plain Lua) and <b>OPT=2</b> is the
+ patch in action.</p>
+<table style="width: 325px;" class="table_center">
+<tbody>
+<tr>
+<th style="text-align: left;">Platform</th>
+<th style="text-align: center;">OPT=0</th>
+<th style="text-align: center;">OPT=2</th>
+</tr>
+<tr>
+ <td>AVR32</td>
+ <td style="text-align: center;">23.75</td>
+ <td style="text-align: center;">5.42</td>
+</tr>
+<tr>
+ <td>AT91SAM7X</td>
+ <td style="text-align: center;">25.16</td>
+ <td style="text-align: center;">5.42</td>
+</tr>
+<tr>
+ <td>STR7</td>
+ <td style="text-align: center;">24.92</td>
+ <td style="text-align: center;">5.42</td>
+</tr>
+<tr>
+ <td>STR9</td>
+ <td style="text-align: center;">22.23</td>
+ <td style="text-align: center;">5.42</td>
+</tr>
+<tr>
+ <td>LPC2888</td>
+ <td style="text-align: center;">22.23</td>
+ <td style="text-align: center;">5.42</td>
+</tr>
+<tr>
+ <td>i386</td>
+ <td style="text-align: center;">16.90</td>
+ <td style="text-align: center;">5.42</td>
+</tr>
+<tr>
+ <td>LM3S</td>
+ <td style="text-align: center;">27.14</td>
+ <td style="text-align: center;">5.42</td>
+</tr>
+</tbody>
+</table>
+
+<p>As you can see, the differences are significant, and (more important) it doesn't matter how many modules you load in <b>eLua</b>, the RAM consumption
+ doesn't modify.</p>
+<p>Currently, there aren't any performane measurements related to LTR. It's clear from the implementation that the patch slows down the virtual machine,
+ but a precise performance penalty figure is not known. Experience suggests that the peformance penalty is minimal, and it certainly can't be observed
+ with "regular" (non-computationally intensive) Lua programs.</p>
+<h2>How to enable LTR</h2>
+<p>Enabling LTR is very easy: all you need to do is specify the <b>opt=1</b> as a paramater to scons when bulding <b>eLua</b>, as explained
+ <a href="building.html">here</a>. You don't even to specify this explicitly, as LTR is enabled by default for all <b>eLua</b> targets.</p>
+<p>When <b>optram</b> is 0, LTR is not active. In this mode the patch just tries to keep the modified version as close as possible to the unpatched version
+ in terms of speed and functionality. You might want to use this if you want full Lua compatibility (although this is rarely an issue in practice),
+ or need to overcome the read-only limitations of rotables (but check <a href="faq.html#rotables">this</a> first). If your program behaves weird and you
+ suspect that LTR might be the cause of your problems, recompiling with <b>optram=0</b> is a quick way to eliminate or confirm your suspicions.</p>
+<p>When <b>optram</b> is 1 (default), all the LTR optimizations are enabled. The implementation of the Lua standard libraries is modified to take advantage
+ of the new datatypes. In particular, the IO library is modified to use the registry instead of environments, thus making it more resource-friendly,
+ the side effect being that this mode doesn't support pipes in the <b>io</b> module (which isn't an issue for <b>eLua</b>).
+ It also leaves the <b>_G</b> (globals) table with a single method (<i>__index</i>) and sets it as its own metatable, so all accesses to globals are
+ now sligthly slower because of the <i>__index</i> metamethod call.</p>
+<h2>Writing LTR-compatible modules</h2>
+<p>The LTR patch introduces a specific method for writing modules in such a way that they're fully compatible with both <b>optram=0</b> and <b>optram=1</b>.
+ If you're writing a new <b>eLua</b> module you should use this method, as it keeps code coherency. </p>
+<p>We'll show this method using a simple example. Let's assume that you want to register a simple module called "mod" that has a single function named "f".
+ For regular Lua, you'd do something like this:</p>
+<p><pre><code>static const luaL_reg mod_map[] =
+{
+ { "f", f_implementation },
+ { NULL, NULL }
+};
+
+LUALIB_API int luaopen_mod( lua_State *L )
+{
+ luaL_register( L, "mod", mod_map );
+ return 1;
+}</code></pre></p>
+<p>For the rotables implementation, however, you'd need to define the same thing like this:</p>
+
+<pre><code>const luaR_entry mod_map[] = <span class="warning">// note: no static this time</span>
+{
+ { LRO_STRKEY( "f" ), LRO_FUNCVAL( f_implementation ) },
+ { LRO_NILKEY, LRO_NILVAL }
+};
+
+<span class="warning">// note: in this case the "luaopen_mod" function isn't really needed anymore</span>
+LUALIB_API int luaopen_mod( lua_State *L )
+{
+ return 0;
+}</code></pre>
+
+<p>A few points about the rotables example above:</p>
+<ul>
+ <li>a rotable needs a "map" (mod_map) array much like a regular module, but you need to define that array with special macros:
+ <ul>
+ <li><b>for keys</b>: <b>LRO_STRKEY("str")</b> defines a string key, <b>LRO_NUMKEY(n)</b> defines an integer key, and <b>LRO_NILKEY</b> defines a NULL
+ (empty) key</li>
+ <li><b>for values</b>: <b>LRO_FUNCVAL(f)</b> defines a lightfunction value, <b>LRO_NUMVAL(f)</b> defines a number value, <b>LRO_RO(p)</b> defines a
+ rotable value (p is the pointer to the rotable) and <b>LRO_NILVAL</b> defines a NULL (empty) value.</li>
+ </ul></li>
+ <li>all the "global" rotables in the system (the ones that must be visible from <b>_G</b>, like the rotables of all the modules exported to Lua) must be
+ included in a special array, called <b>lua_rotable</b> (defined in <i>linit.c</i>). Simply including the rotable's definition array (mod_map in this case)
+ in the lua_rotable array makes it visible globally, thus you don't need to call any kind of register function. This is why <b>luaopen_mod</b> now returns
+ 0.</li>
+</ul>
+<p>The two forms above (for regular tables and for rotables) are clearly different, but we want to keep them both to be able to work at both <b>optram=0</b>
+ and <b>optram=2</b>. You can use #ifdefs to differentiate between the two cases in different optimization levels, but this becomes really annoying after
+ a (short) while. This is why I added another file called <b>lrodefs.h</b> (<i>src/lua</i>) that can be used to give an "universal" definition to our map
+ arrays. Here's how our example looks after rewriting it to take advantage of <b>lrodefs.h</b>:</p>
+<pre><code><span class="warning">#define MIN_OPT_LEVEL 2 // the minimum optimization level at which we use rotables</span>
+#include "lrodefs.h"
+const <span class="warning"> LUA_REG_TYPE</span> mod_map[] = <span class="warning">// note: no more luaL_reg or luaR_entry</span>
+{
+ { LSTRKEY( "f" ), LFUNCVAL( f_implementation ) },
+ { LNILKEY, LNILVAL }
+};
+// <span class="warning">note: no more LRO_something, just Lsomething (for example LRO_STRKEY becomes LSTRKEY)</span>
+
+LUALIB_API int luaopen_mod( lua_State *L )
+{
+ <span class="warning">LREGISTER</span>( L, "mod", mod_map ); // <span class="warning">note: no more luaL_register, no "return 1"</span>
+}</code></pre>
+<p>Now, if <b>LUA_OPTIMIZE_MEMORY</b> (a macro defined by the system as 0 when <b>optram=0</b> and as 2 when <b>optram=1</b>) is less than
+ <b>MIN_OPT_LEVEL</b>, the above definition will compile in its "regular table" format. If <b>LUA_OPTIMIZE_MEMORY</b> is 2, it compiles to the
+ rotables format. Problem solved :) <b>LREGISTER</b> will also take care of calling <b>luaL_register</b> and return 1 when <b>optram=0</b> and do
+ absolutely nothing when <b>optram=1</b>. You can see more examples of this in any module from <i>src/modules</i>, and you're encouraged to do so,
+ as this is only a very basic example; <i>src/modules</i> contains real life examples that can serve as a good basis for a new module.</p>
+<p>As you know by now, rotables can have metatables, and also you can set a rotable as a metatable for a regular table. If a rotable must have a
+ metatable, it needs a "__metatable" field to point to its metatable (which is also a rotable, not necessarily another rotable) and the usual
+ metatable functions. For example, let's make our <b>mod</b> rotable its own metatable and declare an <b>__index</b> function. Moreover, let's do
+ this for both <b>optram=0</b> and <b>optram=1</b>.</p>
+<pre><code>static int mod_mt_index( lua_State *L )
+{
+ return 0;
+}
+
+#define MIN_OPT_LEVEL 2 // the minimum optimization level at which we use rotables
+#include "lrodefs.h"
+const LUA_REG_TYPE mod_map[] =
+{
+ { LSTRKEY( "f" ), LFUNCVAL( f_implementation ) },
+<span class="warning">#if LUA_OPTIMIZE_MEMORY > 0
+ { LSTRKEY( "__metatable" ), LROVAL( mod_map ) },
+#endif</span>
+ { LSTRKEY( "__index" ), LFUNCVAL( mod_mt_index) },
+ { LNILKEY, LNILVAL };
+};
+
+LUALIB_API int luaopen_mod( lua_State *L )
+{
+#if LUA_OPTIMIZE_MEMORY > 0
+ return 0;
+#else
+ luaL_register( L, "mod", mod_map );
+
+ <span class="warning">// Set "mod" as its own metatable
+ lua_pushvalue( L, -1 );
+ lua_setmetatable( L, -2 );</span>
+
+ return 1;
+ #endif
+}</code></pre>
+<p>If you want to register a module using a regular Lua table, but use lightfunctions instead of regular functions, use <i>luaL_register_light</i> instead
+ of <i>luaL_register</i> (same syntax). </p>
+<p>More important things to keep in mind when working with LTR:</p>
+<ul>
+ <li>currently, <b>MIN_OPT_LEVEL</b> should be always set to 2</li>
+ <li>you need a C99-compatible compiler to use LTR (because of the compile-time explicit union initialization that's needed to declare const rotables).
+ Fortunately this isn't a issue right now, as all current eLua targets use GCC and GCC knows how to handle this.</li>
+ <li>your linker command file should export two symbols: <b>stext</b> and <b>etext</b>. They should be declared before and after the .rodata* section
+ placement (generally you'd declare stext at the beginning of .text definition and etext and the end of .text definition, see for example
+ <i>src/lua/at91sam7x256/flash256.lds</i>). These are needed by the patch to differentiate between a regular table and a rotable (although this is likely
+ to change in a future version of the patch.</li>
+ <li><span class="warning">remember to declare all you rotable's definition array as 'const'!!</span> Forgetting to do so will not only increase
+ memory usage, it will also make the patch not functional, because of the way it recognizes rotables (see above).</li>
+</ul>
+<a name="config" /><h2>LTR and module configuration at build time</h2>
+<p>With unpatched Lua, you can specify what modules to be part of the Lua image by modifying <i>src/lua/linit.c</i>. In the particular case of <b>eLua</b>
+ one had to declare a list of the modules that must be compiled in <i>src/platform/<name>/platform_conf.h</i> like this:</p>
+<pre><code>#define LUA_PLATFORM_LIBS\
+ { AUXLIB_PIO, luaopen_pio },\
+ { AUXLIB_TMR, luaopen_tmr },\
+ { AUXLIB_PD, luaopen_pd },\
+ { AUXLIB_UART, luaopen_uart },\
+ { AUXLIB_TERM, luaopen_term },\
+ { AUXLIB_PWM, luaopen_pwm },\
+ { AUXLIB_PACK, luaopen_pack },\
+ { AUXLIB_BIT, luaopen_bit },\
+ { LUA_MATHLIBNAME, luaopen_math }
+</code></pre>
+ <p>Things are a bit more complex with LTR, but not by much. The list of modules that must be compiled is declared via a preprocessor macro in
+ <i>src/platform/<name>/platform_conf.h</i> and it looks like this:</p>
+<pre><code>#define LUA_PLATFORM_LIBS_ROM\
+ _ROM( AUXLIB_PIO, luaopen_pio, pio_map )\
+ _ROM( AUXLIB_TMR, luaopen_tmr, tmr_map )\
+ _ROM( AUXLIB_PD, luaopen_pd, pd_map )\
+ _ROM( AUXLIB_UART, luaopen_uart, uart_map )\
+ _ROM( AUXLIB_TERM, luaopen_term, term_map )\
+ _ROM( AUXLIB_PWM, luaopen_pwm, pwm_map )\
+ _ROM( AUXLIB_PACK, luaopen_pack, pack_map )\
+ _ROM( AUXLIB_BIT, luaopen_bit, bit_map )\
+ _ROM( LUA_MATHLIBNAME, luaopen_math, math_map )</code></pre>
+<p>(<b>IMPORTANT NOTE</b>: the fact that there are no commas between two different _ROM declarations (as seen above) is NOT an error;
+ on the contrary, this is very much intended. Try using commas and you'll get in trouble very soon :) ).</p>
+<p>Note the 3rd parameter of the <b>_ROM</b> macro, which is the name of the definition array for the (ro)table. That's it. The code in linit.c will take
+ care of everything else, including initializing the list of modules in LUA_PLATFORM_LIBS_ROM with regular tables instead of rotables at <b>optram=0</b>
+ (to maintain compatilibity with regular Lua). You can also have a list of modules that you want to use with regular tables no matter what the
+ optimization level is. In that case, list it in the <b>LUA_PLATFORM_LIBS_REG</b> macro via the old syntax for <b>LUA_PLATFORM_LIBS</b>, as shown
+ above (the regular Lua syntax for defining a module to be registered with luaL_register). If you want this module to use lightfunctions instead of
+ regular functions (at <b>optram=1</b>), use <i>luaL_register_light</i> instead of <i>luaL_register</i>.
+</p>
+$$FOOTER$$
+
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===================================================================
--- branches/eagle_mmc/doc/en/arch_newport.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/pt/arch_newport.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,137 @@
+$$HEADER$$
+<h3>Porting eLua</h3>
+<p>So, you realized how cool <b>eLua</b> is :), and you'd like to give it a try. Unfortunately, <b>eLua</b> doesn't have a port on your CPU or board of choice.
+ The solution is simple: write the port yourself. This might seem as a daunting task at first, but it's actually easier than it sounds. <b>eLua</b> was
+ designed to make the task of implementing new ports as easy and intuitive as possible. This section gives an overview of the porting process. It's not
+ an exhaustive guide, but it should be enough to point you in the right direction. Before diving into this, it's highly recommended that you take a look
+ at the <a href="arch_overview.html">eLua architecture page</a>. </p>
+<h3>Prerequisites</h3>
+<p>Before starting to work on the port, make sure that:</p>
+<ul>
+ <li>your CPU has enough resources to run <b>eLua</b>. A very rough estimation (based on ARM Thumb code only) is that you'd need at least 256k
+ of program memory and 32k of RAM for a complete <b>eLua</b> image, and 128k of program memory for a basic image. It's possible to run <b>eLua</b> in
+ less than 32k of RAM (especially when <a href="arch_ltr.html">LTR</a> is enabled), but you'll probably run out of memory fast.
+ 64k of RAM (or more) is recommended.</li>
+ <li><a target="_blank" href="http://sourceware.org/newlib">Newlib</a> is available for your CPU. <b>eLua</b> depends on Newlib currently
+ (although this limitation will be eliminated in a future version), so if Newlib is not available for your CPU, you're out of luck. </li>
+ <li>you have a C compiler for your target. Ideally you'd use GCC, but if this isn't possible other compilers might work as well. Keep in mind that
+ <a href="arch_ltr.html">LTR</a> needs a C99 C compiler (or at least a partially C99 compliant C compiler than supports C99-style union initialization).
+ </li>
+ <li>you have a platform library (it usually comes from the CPU manufacturer) that you can use to implement (at least part of) the platform interface.
+ It's also highly recommended to gain at least a basic understanding of your platform, it will help a lot while writing the port.</li>
+</ul>
+<p>If all of the above are true, you should continue reading this document to bring your port to life. If not, we're sorry, but (at least at this point)
+<b>eLua</b> can't be ported to your CPU. If, on the other hand, you're good to go, please take a bit of time and read
+ <a href="arch_overview.html#platforms">this section</a> first, as it details the structure of a port and might simplify your work quite a bit.</p>
+<a name="newboard" /><h3>Adding a new board</h3>
+<p>If all you need is to add a new board that uses a CPU already supported by <b>eLua</b> (check <a href="status.html">here</a> for a complete list), it's
+fairly easy to accomplish this:</p>
+<ol>
+ <li>choose a good name for your board :)</li>
+ <li>edit <b>SConstruct</b> and add your board to the <b>board_list</b> dictionary, specifying its CPU. A part of the definition of <b>board_list</b> is given below:
+<p><pre><code># List of board/CPU combinations
+board_list = { 'SAM7-EX256' : [ 'AT91SAM7X256', 'AT91SAM7X512' ],
+ 'EK-LM3S8962' : [ 'LM3S8962' ],
+ 'EK-LM3S6965' : [ 'LM3S6965' ],
+ ..............................
+ }</code></pre></p>
+ </li>
+ <li>also edit the <b>file_list</b> dictionary in <b>SConstruct</b> to specify the list of ROMFS files that will be compiled for your board (see the
+ <a href="arch_romfs.html">ROMFS section</a> for details). A part of the definition of <b>file_list</b> is given below:
+<pre><code># List of board/romfs data combinations
+file_list = { 'SAM7-EX256' : [ 'bisect', 'hangman' , 'led', 'piano', 'hello', 'info', 'morse' ],
+ 'EK-LM3S8962' : [ 'bisect', 'hangman', 'lhttpd', 'pong', 'led', 'piano', 'pwmled', 'tvbgone', 'hello', 'info', 'morse', 'adcscope' ],
+ 'EK-LM3S6965' : [ 'bisect', 'hangman', 'lhttpd', 'pong', 'led', 'piano', 'pwmled', 'tvbgone', 'hello', 'info', 'morse', 'adcscope' ],
+ ...............................
+ }</code></pre></li>
+ <li>if your board has external memory, you'll probably want to use the "multiple" allocator by default to take advantage of that (see <a href="building.html">building</a>)
+ for details. If so, you need to modify the CPU/allocator mapping code from <b>SConstruct</b>:
+<pre><code># CPU/allocator mapping (if allocator not specified)
+if allocator == '':
+ if <b>boardname == 'LPC-H2888'</b> or <b>boardname == 'ATEVK1100'</b>:
+ allocator = 'multiple'
+ else:
+ allocator = 'newlib'
+elif allocator not in [ 'newlib', 'multiple', 'simple' ]:
+ print "Unknown allocator", allocator
+ print "Allocator can be either 'newlib', 'multiple' or 'simple'"
+ sys.exit( -1 )
+</code></pre>
+ </li>
+ <li>customize the <b>eLua</b> image for this new board. You can use the variable <b>boardname</b> in <b>conf.py</b> to define new preprocessor macros specifically for your board
+ (that you can use later in <b>platform_conf.h</b>, for example), or to include or exclude certain files from the build, or change the build flags and so on. An example taken from
+ the <b>lm3s</b> port is given below (part of <b>conf.py</b>):
+<pre><code>if boardname == 'EK-LM3S6965' or boardname == 'EK-LM3S8962':
+ specific_files = specific_files + " rit128x96x4.c disp.c"
+ cdefs = cdefs + " -DENABLE_DISP"
+
+# The default for the Eagle 100 board is to start the image at 0x2000,
+# so that the built in Ethernet boot loader can be used to upload it
+if boardname == 'EAGLE-100':
+ linkopts = "-Wl,-Ttext,0x2000"
+else:
+ linkopts = ""
+</code></pre>
+</li>
+</ol>
+<p>After you edit all the relevant source files, all you have to do is to execute <i>scons board=<boardname></i> and you'll have <b>eLua</b> compiled for your board.</p>
+<a name="newcpu" /><h3>Adding a new CPU</h3>
+<p>If you want to add a new CPU to <b>eLua</b> and the new CPU happens to be supported by a platform on which <b>eLua</b> already runs (see <a href="status.html">here</a> for a full
+list), your task is still quite easy. Follow the steps below:</p>
+<ol>
+ <li>edit <b>SConstruct</b> and add your new CPU to the <b>platform_list</b> dictionary. Use the "official" name of the CPU (as it appears in its datasheet). An example is given below:
+<pre><code># List of platform/CPU/toolchains combinations
+# The first toolchain in the toolchains list is the default one
+# (the one that will be used if none is specified)
+platform_list = {
+ 'at91sam7x' : { 'cpus' : [ 'AT91SAM7X256', 'AT91SAM7X512' ], 'toolchains' : [ 'arm-gcc', 'codesourcery', 'devkitarm', 'arm-eabi-gcc' ] },
+ 'lm3s' : { 'cpus' : [ 'LM3S8962', 'LM3S6965', 'LM3S6918' ], 'toolchains' : [ 'arm-gcc', 'codesourcery', 'devkitarm', 'arm-eabi-gcc' ] },
+ 'str9' : { 'cpus' : [ 'STR912FAW44' ], 'toolchains' : [ 'arm-gcc', 'codesourcery', 'devkitarm', 'arm-eabi-gcc' ] },
+ ..................
+}</code></pre></li>
+ <li>you also need to add a new board to <b>eLua</b> (which makes sense, since you're most likely going to run <b>eLua</b> on a board built around the CPU
+ of your choice, not only on the CPU itself). So follow the instruction from the <a href="arch_newport.html#newboard">previous paragraph</a> to add
+ your new board.</li>
+ <li>customize the <b>eLua</b> image for this new CPU. You can use the variable <b>cputype</b> in <b>conf.py</b> to define new preprocessor macros specifically for your CPU
+ (that you can use later in <b>platform_conf.h</b>, for example), or to include or exclude certain files from the build, or change the build flags and so on. An example taken from
+ the <b>at91sam7x</b> port is given below (part of <b>conf.py</b>):
+<pre><code>if cputype == 'AT91SAM7X256':
+ ldscript = "flash256.lds"
+ cdefs = cdefs + " -Dat91sam7x256"
+elif cputype == 'AT91SAM7X512':
+ ldscript = "flash512.lds"
+ cdefs = cdefs + " -Dat91sam7x512"
+else:
+ print "Invalid AT91SAM7X CPU %s" % cputype
+ sys.exit( -1 ) </code></pre></li>
+</ol>
+<p>After you edit all the relevant source files, all you have to do is to execute <i>scons board=<boardname></i> and you'll have <b>eLua</b> compiled for your board (and implicitly for
+ your new CPU).</p>
+<a name="newplatform" /><h3>Adding a new platform</h3>
+<p>If you want to add a new CPU to <b>eLua</b> and the new CPU is not supported by a platform on which <b>eLua</b> already runs (see <a href="status.html">here</a> for a full list), you have to
+go the whole way and add a completely new platform to <b>eLua</b>. This is certainly more difficult than the previous cases, but still not that hard. Remember to start small (implement only
+minimal support at first) and don't write everything from scratch, start from an already existing platform implementation and work your way up from there. The <b>i386</b> port is the simplest,
+but also a bit different from the embedded ports. Another port that is quite simple at this point is the <b>lpc2888</b> port, you might take a look at that too. After you "get a feeling" of
+how a port should look like, and after you read about the architecture of <b>eLua</b> and the structure of a port <a href="arch_overview.html">here</a>, follow the steps below:</p>
+<ol>
+ <li>choose the name of your new platform. It should be an easy, descriptive name. For example, all the CPUs from the LM3S series are grouped inside a platform called <b>lm3s</b>.</li>
+ <li>create the <i>src/platform/<name></i> directory, and add all your platform-specific files here. Check <a href="arch_overview.html#platforms">here</a> for specific details.</li>
+ <li>use the instructions from the <a href="arch_newport.html#newcpu">previous paragraph</a> to add your new CPU and board to <b>eLua</b>.</li>
+ <li>implement as much as you need from the <a href="arch_platform.html">platform interface</a>.</li>
+ <li>if your new platform uses a toolchain that wasn't previously configured in <b>eLua</b>, add it now (see <a href="toolchains.html">here</a> for more details about toolchains).</li>
+ <li>let <b>SConstruct</b> know about your new platform by modifying the <b>platform_list</b> variable to add information about the CPU(s) available for your platform and about its toolchains.
+An example is given below:
+<pre><code># List of platform/CPU/toolchains combinations
+# The first toolchain in the toolchains list is the default one
+# (the one that will be used if none is specified)
+platform_list = {
+ 'at91sam7x' : { 'cpus' : [ 'AT91SAM7X256', 'AT91SAM7X512' ], 'toolchains' : [ 'arm-gcc', 'codesourcery', 'devkitarm', 'arm-eabi-gcc' ] },
+ 'lm3s' : { 'cpus' : [ 'LM3S8962', 'LM3S6965', 'LM3S6918' ], 'toolchains' : [ 'arm-gcc', 'codesourcery', 'devkitarm', 'arm-eabi-gcc' ] },
+ 'str9' : { 'cpus' : [ 'STR912FAW44' ], 'toolchains' : [ 'arm-gcc', 'codesourcery', 'devkitarm', 'arm-eabi-gcc' ] },
+ ..................
+}</code></pre></li>
+</ol>
+<p>After you edit all the relevant source files, all you have to do is to execute <i>scons board=<boardname></i> and you'll have <b>eLua</b> compiled for your board (and implicitly for
+ your new CPU).</p>
+$$FOOTER$$
+
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+$$HEADER$$
+<a name="structure" /><h3>eLua architecture overview</h3>
+<p>The overall logical structure of <b>eLua</b> is shown in the image below:</p>
+<p style="text-align: center; valign:middle;"><img src="images/elua_arch.png" style="border: 0;" alt="eLua architecture"></img></p>
+<p><b>eLua</b> uses the notion of <b>platform</b> to denote a group of <b>CPUs</b> that share the same core structure, although their specific silicon
+ implementation might differ in terms of intergrated peripherals, internal memory and other such attributes. An <b>eLua</b> port implements one or
+ more CPUs from a given platform. For example, the <b>lm3s port</b> of <b>eLua</b> runs on LM3S8962, LM3S6965 and LM3S6918 CPUs, all of them part of the
+ <b>lm3s</b> platform. Refer to <a href="status.html">the status page</a> for a full list of platforms and CPUs on which <b>eLua</b> runs.</p>
+<p>As can be seen from this image, <b>eLua</b> tries to be as portable as possible between different platforms by using a few simple design
+rules:</p>
+<ul>
+ <li>all code that is platform-independent is <b>common code</b> and it should be written in ANSI C as much as possible, this makes it highly portable
+ among different architectures and compilers, just like Lua itself. </li>
+ <li>all the code that can't possibly be generic (mostly peripheral and CPU specific code) must still be made as portable as possible by using a common
+ interface that must be implemented by all platforms on which <b>eLua</b> runs. This interface is called <b>platform interface</b> and is discussed in
+ detail <a href="arch_platform.html">here</a> (but please see also <a href="arch_overview.html#platform">"The platform interface"</a>
+ paragraph in this document).</li>
+ <li>all platforms (and their peripherals) are not created equal and vary greatly in capabilities. As already mentioned, the platform interface tries
+ to group only common attributes of different platforms. If one needs to access the specific functionality on a given platform (like the loopback support
+ mentioned before) it can do so by using a <b>platform module</b>. These are of course platform specific, and their goal is to fill the gap between the
+ platform interface and the full set of features provided by a platform.</li>
+</ul>
+<a name="common" /><h3>Common (generic) code</h3>
+<p>The following gives an incomplete set of items that can be classified as <b>common code</b>:</p>
+ <ul>
+ <li>the Lua code itself (obviously) plus the <a href="arch_ltr.html">LTR patch</a>.</li>
+ <li>all the <b>components</b> in <b>eLua</b> (like the ROM file system, the XMODEM receive code, the <b>eLua</b> shell, the TCP/IP stack and others).
+ </li>
+ <li>all the <b>generic modules</b>, which are Lua modules used to expose the functionality of the platform to Lua.</li>
+ <li>generic <b>peripheral support code</b>, like the ADC support code (<i>src/common/elua_adc.c</i>) that is <b>independent</b> of the actual ADC
+ hardware.</li>
+ <li>libc code (for example allocators and Newlib stubs).</li>
+ </ul>
+<p>This should give you a pretty good idea about what "common code" means in this context. Note that the generic code layer should be as "greedy" as
+possible; that is, it should absorb as much common code as possible. For example:</p>
+<ul>
+ <li>if you want to add a new file system to <b>eLua</b>, this should definitely be generic code. It's likely that this kind of code will have
+ dependencies related to the physical medium on which this file system resides. If you're lucky, you can solve these dependencies using only the functions
+ defined in the <a href="arch_platform.html">platform interface</a> (this would make sense if you're using a SD card controlled over SPI, since the
+ platform interface already has a SPI layer). If not, you should group the platform specific functions in a separate interface that will be implemented by
+ all platform that want to use your new file system. This gives the code maximum portability.</li>
+ <li>if you want to add a driver for a specific ADC chip that works over SPI, the same observations apply: write it as common code as much as you can,
+ and use the <a href="arch_platform.html">platform interface</a> for the specific SPI functions you need.</li>
+</ul>
+<p>When designing and implementing a new component, keep in mind other <b>eLua</b> design goal: <b>flexibility</b>. The user should be able to
+ select which components are part of its <b>eLua</b> binary image (as described <a href="building.html">here</a>), and the implementation should take
+ this into consideration. The same thing holds for the generic modules: the user must have a way to choose the set of modules he needs.</p>
+<p>For maximum portability, make your code work in a variety of scenarios if possible (and if that makes sense from a practical point of view).
+ Take for example the code for stdio/stdout/stderr handling (<i>src/newlib/genstd.c</i>): it acknowledges the fact that a terminal can be implemented
+ over a large variety of physical transports (RS-232 for PC, SPI for a separate LCD/keyboard board, a radio link and so on) so it uses pointers for its
+ send/receive functions (see <a href="arch_con_term.html">this link</a> for more details). The impact on speed and resource consumption is minimum, but
+ it matters a lot in the portability department.</p>
+<a name="platform" /><h3>Platform interface</h3>
+<p>Used properly, the platform interface allows writing extremely portable code over a large variety of different platforms, both from C and from Lua.
+ An important property of the platform interface is that it tries to group only <b>common</b> attributes of different platforms (as much as possible).
+ For example, if a platform supported by <b>eLua</b> has an UART that can work in loopback mode, but the others don't, loopback support won't be included
+ in the platform interface.</p>
+<p>A special emphasis on the platform interface usage: remember to use it not only for Lua, but also for C. The platform interface is mainly used by the
+ generic modules to allow Lua code to access platform peripherals, but this isn't its only use. It can (and it should) also be used by C code that wants
+ to implement a generic module and neeeds access to peripherals. An example was given in the previous section: implementing a new file system.</p>
+<p>The platform interface definition is always in the <i>inc/platform.h</i> header file. For a full description of its functions, check
+ <a href="arch_platform.html">the platform interface documentation.</a></p>
+<a name="platforms" /><h3>Platforms and ports</h3>
+<p>All the platforms that run <b>eLua</b> (and that implement the platform interface) are implemened in this conceptual layer. A <b>port</b> is a full
+ <b>eLua</b> implementation on a given platform. The two terms can generally be used interchangeably.</p>
+<p>A port can (and generally will) contain specific peripheral drivers, many times taken directly from the platform's CPU support
+ package. These drivers are used to implement the platform interface. Note that:</p>
+<ul>
+ <li>a port isn't required to implement <b>all</b> the platform interface functions, just the ones it needs. As explained
+ <a href="building.html">here</a>, the user must have full control over what's getting built into this <b>eLua</b> image. If you don't need the SPI
+ module, for example, you don't need to implement its platform interface.</li>
+ <li>a part of the platform interface is implemented (at least partially) in a file that is common for all the platforms (<i>src/common.c</i>). It
+ eases the implmentation of some modules (such as the timer module) and also implements common features that are tied to the platform interface,
+ but have a common behaviour on all platforms (for example virtual timers, see <a href="arch_platform_timers.html#virtual_timers">here</a> for details). You probably won't need to modify
+ if you're writing platform specific code, but it's best to keep in mind what it does.</li>
+</ul>
+<p>A platform implementation might also contain one or more <b>platform dependent modules</b>. As already exaplained, their purpose is to allow Lua
+ to use the full potential of the platform peripherals, not only the functionality covered by the platform interface, as well as functionality that
+ is so specific to the platform that it's not even covered by the platform interface. By convention, all the platform dependent modules should be
+ grouped inside a single module that has the same name as the platform itself. If the platform dependent module augments the functionality of a
+ module already found in the platform interface, it should have the same name, otherwise it should be given a different, but meaningful name. For example:</p>
+<ul>
+ <li>if implementing new functionality on the UART module of the LM3S platform, the corresponding module should be called <b>lm3s.uart</b>.</li>
+ <li>if implementing a peripheral driver that for some reason should be specific to the platform on the LPC2888 platform, for example its dual audio
+ DAC, give it a meaningful name, for example <b>lpc288x.audiodac</b>.</li>
+</ul>
+<h2>Structure of a port</h2>
+<p>All the code for platform <i>name</i> (including peripheral drivers) must reside in a directory called <i>src/platform/<name></i> (for example
+<i>src/platform/lm3s</i> for the <i>lm3s</i> platform). Each such platform-specific subdirectory must contain at least these files:</p>
+<ul>
+ <li><b>type.h</b>: this defines the "specific data types", which are integer types with a specific size (see <a href="arch_coding.html">coding style</a>
+ for details. An example from the <b>i386</b> platform:
+<pre><code>typedef unsigned char u8;
+typedef signed char s8;
+typedef unsigned short u16;
+typedef signed short s16;
+typedef unsigned long u32;
+typedef signed long s32;
+typedef unsigned long long u64;
+typedef signed long long s64;</code></pre>
+ </li>
+ <li><b>conf.py</b>: this is the platform specific build configuration file, used by the <a href="building.html">build system</a> for a number of purposes:
+<ul>
+ <li>to get the list of platform-specific files that will be compiled in the <b>eLua</b> image. They are exported in the <i>specific_files</i> string,
+ separated by spaces, and must be prepended with the relative path to the platform subdirectory. An example from the <b>i386</b> platform:
+<pre><code>specific_files = "boot.s common.c descriptor_tables.c gdt.s interrupt.s isr.c kb.c monitor.c timer.c platform.c"
+# Prepend with path
+specific_files = " ".join( [ "src/platform/%s/%s" % ( platform, f ) for f in specific_files.split() ] )</code></pre>
+ </li>
+ <li>to get the full command lines of the different toolchain utilities (linker, assembler, compiler) used to compile <b>eLua</b>. They must be declared
+ inside the <i>tools</i> variable, in a separate dictinoary which key is the same as the platform name, and with specific names for each tool in turn:
+ <b>cccom</b> for the compiler, <b>linkcom</b> for the linker and <b>ascom</b> for the assembler.
+ For example, this is how the <i>tools</i> variable is defined for the <b>i386</b> platform:
+ <pre><code># Toolset data
+ tools[ 'i386' ] = {}
+ tools[ 'i386' ][ 'cccom' ] = "%s %s %s -march=i386 -mfpmath=387 -m32 -ffunction-sections -fdata-sections -fno-builtin -fno-stack-protector %s -Wall -c $SOURCE -o $TARGET" % ( toolset[ 'compile' ], opt, local_include, cdefs )
+ tools[ 'i386' ][ 'linkcom' ] = "%s -nostartfiles -nostdlib -march=i386 -mfpmath=387 -m32 -T %s -Wl,--gc-sections -Wl,-e,start -Wl,--allow-multiple-definition -o $TARGET $SOURCES -lc -lgcc -lm %s" % ( toolset[ 'compile' ], ldscript, local_libs )
+ tools[ 'i386' ][ 'ascom' ] = "%s -felf $SOURCE" % toolset[ 'asm' ]</code></pre>
+ Note how the definition of <b>tools</b> uses the definition of <b>toolset</b>, a dictionary with the names of the tools in the current toolchain. This
+ is also part of the <b>eLua</b> build system and is documented <a href="toolchains.html">here</a>.</li>
+ <li>to get the name of a <b>programmning function</b> which receives the name of the <b>eLua</b> executable file (the result of the build step) and
+ produces a file suitable for programming on the corresponding hardware platform. The name of this function should also be set in the <i>tools</i>
+ dictionary, as shown below (example taken from the <b>str7</b> platform):
+ <pre><code># Programming function for STR7
+ def progfunc_str7( target, source, env ):
+ outname = output + ".elf"
+ os.system( "%s %s" % ( toolset[ 'size' ], outname ) )
+ print "Generating binary image..."
+ os.system( "%s -O binary %s %s.bin" % ( toolset[ 'bin' ], outname, output ) )
+
+ tools[ 'str7' ][ 'progfunc' ] = progfunc_str7</code></pre>
+ Note, once again, how this function uses the same <i>toolset</i> variable mentioned in the previous paragraph.
+ </li>
+ </ul>
+ </li>
+<li><b>stacks.h</b>: by convention, the stack(s) size(s) used in the system are declared in this file. An example taken from the <b>at91sam7x</b> platform is given below:
+<pre><code>#define STACK_SIZE_USR 2048
+#define STACK_SIZE_IRQ 64
+#define STACK_SIZE_TOTAL ( STACK_SIZE_USR + STACK_SIZE_IRQ )</code></pre></li>
+<li><b>platform.c</b>: by convention, the <a href="arch_platform.html">platform interface</a> is implemented in this file. It also contains the platform-specific
+ initialization function (<i>platform_init</i>, see the description of the <a href="arch_overview.html#boot">eLua boot process</a> for details).</li>
+<li><b>platform_conf.h</b>: this is the platform configuration file, used to give information about both the platform itself and the build configuration for the
+ platform. This is what you can set inside <b>platform_conf.h</b>:
+<ul>
+ <li>the list of <b>components</b> that will be part of the build (see <a href="building.html">building eLua</a> for details).</li>
+ <li>the list of <b>modules</b> that will be part of the build (see <a href="building.html">building eLua</a> and <a href="arch_ltr.html#config">LTR configuration</a>
+ for details.</li>
+ <li>the <b>static configuration data</b> (see <a href="building.html">building eLua</a> for details).</li>
+ <li>the <b>number of peripherals</b> on your CPU. See an example below (taken from <b>lm3s</b>) that also shows how to differentiate between different CPUs that belong to the same
+ platform; the <b>FORxxxx</b> macros are defined in <b>conf.py</b>):
+<pre><code>// Number of resources (0 if not available/not implemented)
+#define NUM_PIO 7
+#define NUM_SPI 1
+#ifdef FORLM3S6965
+ #define NUM_UART 3
+#else
+ #define NUM_UART 2
+#endif
+#define NUM_TIMER 4
+#ifndef FORLM3S6918
+ #define NUM_PWM 6
+#else
+ #define NUM_PWM 0
+#endif
+#define NUM_ADC 4</code></pre></li>
+ <li><b>specific peripheral configuration</b>: this includes (but it not limited to) enabling buffering on UART, enabling and setting up virtual timers, setting PIO configuration and so on.
+ All these parameters are described in detail in the <a href="arch_platform.html">platform interface section</a>.</li>
+ <li><b>memory configuration</b>: describes the regions of free RAM in the system, which will be later used by the standard system allocator (malloc/realloc/free). Two macros
+ (<b>MEM_START_ADDRESS</b> and <b>MEM_END_ADDRESS</b>) define two arrays with the beginning and the end of all the free RAM memory in the system. If your board has external RAM memory, you
+ should define it here. If not, you can only use the internal memory, and you'll generally need to use the linker-defined symbol <b>end</b> to find out where your free memory starts. Following
+ is an example from the <b>ATEVK1100</b> (AVR32) board that has both on-chip and external RAM:
+<pre><code>// Allocator data: define your free memory zones here in two arrays
+// (start address and end address)
+#define MEM_START_ADDRESS { ( void* )end, ( void* )SDRAM }
+#define MEM_END_ADDRESS { ( void* )( 0x10000 - STACK_SIZE_TOTAL - 1 ), ( void* )( SDRAM + SDRAM_SIZE - 1 ) }
+</code></pre>
+ </li>
+</ul>
+ If you want to take a look at a real life example of a <b>platform_conf.h</b> file, see for example <i>src/platform/lm3s/platform_conf.h</i>.
+</li>
+ <li><b>networking configuration</b>: if you need TCP/IP on your board, you need to add networking support to <b>eLua</b> (see <a href="building.html">
+ building</a> for a list of configuration options related to TCP/IP). You also need to have another file, called <b>uip-conf.h</b> that configures uIP
+ (the TCP/IP stack in <b>eLua</b>) for your specific architecture. See <a href="arch_tcpip.html">TCP/IP in eLua</a> for details.</li>
+</ul>
+<p>Besides the required files, the most common scenario is to include other platform specific files in your port:</p>
+<ul>
+ <li><b>a "startup sequence"</b>, generally written in assembler, that does very low level
+ intialization, sets the stack pointer, zeroes the BSS section, copies ROM to
+ RAM for the DATA section, and then jumps to main.</li>
+ <li>a <b>linker command file</b>.</li>
+ <li>the <b>CPU support package</b> generally comes from the CPU manufacturer, and includes code
+ for accessing peripherals, configuring the core, setting up interrupts and so on.</li>
+</ul>
+<a name="boot" /><h3>eLua boot process</h3>
+<p>This is what happens when you power up your <b>eLua</b> board:</p>
+<ol>
+ <li>the platform initialization code is executed. This is the code that does very low level platform setup (if needed), copies ROM to RAM, zeroes out
+ the BSS section, sets up the stack pointer and jumps to <b>main</b>.</li>
+ <li>the first thing <b>main</b> does is call the platform specific initialization function (<b>platform_init</b>). <b>platform_init</b> must fully
+ initialize the platform and return a result to main, that can be either <b>PLATFORM_OK</b> if the initialization succeded or <b>PLATFORM_ERR</b>
+ otherwise. If <b>PLATFORM_ERR</b> is returned, <b>main</b> blocks immediately in an infinite loop.</li>
+ <li><b>main</b> then initializes the rest of the system: the ROM file system, XMODEM, and term.</li>
+ <li>if <b>/rom/autorun.lua</b> (which is a file called <b>autorun.lua</b> in the <a href="arch_romfs.html">ROM file system</a>) is found, it is
+ executed. If it returns after execution, or if it isn't found, the boot process continues with the next step.</li>
+ <li>if the <a href="using.html#shell">shell</a> was compiled in the image, it is started, otherwise a standard Lua interpreter is started.</li>
+</ol>
+$$FOOTER$$
+
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+$$HEADER$$
+<h3>The platform interface</h3>
+<p>The platform interface is the part of <b>eLua</b> that makes it easily portable between different hardware platforms by grouping the common elements
+ of all platforms supported by <b>eLua</b> in a common interface. For more details about the platform interface and the overall structure of
+ <b>eLua</b> in general, check <a href="arch_overview.html">this link</a>.</p>
+ <p>The platform interface is defined in the <i>inc/platform.h</i> header file from the <b>eLua</b> source distribution. It is a collection of various
+ components (UART, SPI, timers ...), each of them is detailed in the next subsections. Each such component has an <b>id</b> which is a number that
+ identifies that component in <b>eLua</b>. Generally, numbers are assigned to components in their "natural" order; for example, PORTA will have the id
+ 0, PORTB will have 1 and so on. Similarly, the second SPI interface (SPI1) of the MCU will probably have an id equal to 1. However, this is not a strict
+ rule. The implementation of the platform interface might choose to expose only some of the peripherals (components) of the MCU, thus this rule might be
+ broken. For example, if a board has 3 UARTs, but for some reason the second UART (UART1) is dedicated and can't be touched by <b>eLua</b>, then UART0 will have the id 0 and UART2 will
+ have the id 1, so UART1 won't ever be accesible to the code.</p>
+ <p>With some exceptions (most notably the low-level support functions), the different modules supported by the platform interface are
+ mirrored more or less accurately in separate Lua modules that can be used directly from <b>eLua</b>. Check <a href="refman_gen.html">the reference manual</a> for a
+ complete description of these modules.</p>
+$$FOOTER$$
+
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+$$HEADER$$
+<h3>The ROM file system</h3>
+<p>The ROM file system (ROMFS) is a small, read-only file system built for <b>eLua</b>. It is integrated with the C
+ library, so you can use standard POSIX calls (fopen/fread/fwrite...) to access it. It is also accessible directly from Lua via the <b>io</b> module.
+ The files in the file system are part of the <b>eLua</b> binary image, thus they can't be modified after the image is
+ built. For the same reason, you can't add/delete files after the image is built. ROMFS doesn't support
+ sub-directories.</p>
+<p>ROMFS is integrated with <a href="building.html">the build system</a> for maximum flexibility on various platforms. As a result, you can select the ROMFS contents for each board on which
+ <b>eLua</b> runs. Moreover, you can specify what <b>applications</b> (instead of individual files) go to the file system, as a real application might need more than a single Lua program
+ to run (for example a HTTP page with all its dependencies).</p>
+<h2>Using ROMFS</h2>
+<p>To use ROMFS, you have to copy the required files to the <i>romfs/</i> directory, before building eLua.
+ Keep in mind that the maximum file name of a ROMFS file is 14 characters, including the dot between the file
+ name and its extension. Make sure that the file names from <i>romfs/</i> follow this rule. Then edit the main build script (<b>SConstruct</b>) to add a new application
+ or to modify an existing one.
+ All the applications that can be included in ROMFS are defined in the <b>romfs</b> array in <b>SConstruct</b>. Each application in the <b>romfs</b> array lists its files, as shown below
+ (note that <b>ltthpd</b>, <b>tvbgone</b> and <b>pong</b> applications require more than one file in order to run):</p>
+<p><pre><code>romfs = {
+ 'bisect' : [ 'bisect.lua' ],
+ 'hangman' : [ 'hangman.lua' ],
+ 'lhttpd' : [ 'index.pht', 'lhttpd.lua', 'test.lua' ],
+ 'pong' : [ 'pong.lua', 'LM3S.lua' ],
+ 'led' : [ 'led.lua' ],
+ 'piano' : [ 'piano.lua' ],
+ 'pwmled' : [ 'pwmled.lua' ],
+ 'tvbgone' : [ 'tvbgone.lua', 'codes.bin' ],
+ 'hello' : [ 'hello.lua' ],
+ 'info' : [ 'info.lua' ],
+ 'morse' : [ 'morse.lua' ],
+ 'dualpwm' : [ 'dualpwm.lua' ],
+ 'adcscope' : [ 'adcscope.lua' ],
+ 'life' : [ 'life.lua' ]
+}</code></pre></p>
+<p>After this, you need to decide the application-to-board mapping. This is defined in another array in <b>SConsctruct</b>, named <b>file_list</b>. The definition of this array is shown below,
+ the format is self-explanatory:</p>
+<p><pre><code>file_list = {
+ 'SAM7-EX256' : [ 'bisect', 'hangman' , 'led', 'piano', 'hello', 'info', 'morse' ],
+ 'EK-LM3S8962' : [ 'bisect', 'hangman', 'lhttpd', 'pong', 'led', 'piano', 'pwmled', 'tvbgone', 'hello', 'info', 'morse', 'adcscope' ],
+ 'EK-LM3S6965' : [ 'bisect', 'hangman', 'lhttpd', 'pong', 'led', 'piano', 'pwmled', 'tvbgone', 'hello', 'info', 'morse', 'adcscope' ],
+ 'STR9-COMSTICK' : [ 'bisect', 'hangman', 'led', 'hello', 'info' ],
+ 'PC' : [ 'bisect', 'hello', 'info', 'life' ],
+ 'LPC-H2888' : [ 'bisect', 'hangman', 'led', 'hello', 'info' ],
+ 'MOD711' : [ 'bisect', 'hangman', 'led', 'hello', 'info', 'dualpwm' ],
+ 'STM3210E-EVAL' : [ 'bisect', 'hello', 'info' ],
+ 'ATEVK1100' : [ 'bisect', 'hangman', 'led', 'hello', 'info' ],
+ 'ET-STM32' : [ 'hello', 'hangman', 'info', 'bisect' ],
+ 'EAGLE-100' : [ 'bisect', 'hangman', 'lhttpd', 'led', 'hello', 'info' ]
+}
+</code></pre></p>
+<p>What's left to do is <a href="building.html">build eLua</a>. As part of the build process, <b>mkfs.py</b> will be called, which will read the contents of the <i>romfs/</i> directory and
+ output a C header file that contains a binary description of the file system. To use ROMFS from C code, whevener you want to access a file, prefix its name with <b>/rom/</b>. For example,
+ if you want to open the <b>a.txt</b> file in ROMFS, you should call fopen like this:</p>
+<p><pre><code>f = fopen( "/rom/a.txt", "rb" )</code></pre></p>
+<p>If you want to execute one file from the ROM file system with Lua, simply do this from the shell:</p>
+ <p><pre><code>eLua# lua /rom/bisect.lua</code></pre></p>
+<p>Or directly from Lua:</p>
+ <p><pre><code>> dofile "/rom/bisect.lua"</code></pre></p>
+$$FOOTER$$
+
Copied: branches/eagle_mmc/doc/pt/arch_tcpip.html (from rev 525, branches/eagle_mmc/doc/en/arch_tcpip.html)
===================================================================
--- branches/eagle_mmc/doc/en/arch_tcpip.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/pt/arch_tcpip.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,90 @@
+$$HEADER$$
+<head><meta http-equiv="Content-Type" content="text/html;charset=utf-8"/>
+<h3>TCP/IP in eLua <span class="warning">(WIP)</span></h3>
+<p><b>eLua</b>'s TCP/IP support was designed with flexibility and ease of use in mind. It
+might not provide all the functions of a "full-fledged" TCP/IP stack, but it's
+still fully functional, has a much smaller footprint and is probably easier to use than a "regular" (POSIX) TCP/IP
+stack. These are the services provided by the TCP/IP stack:</p>
+<ul>
+ <li>a set of functions for network access (defined in inc/elua_net.h)</li>
+ <li>a DHCP client</li>
+ <li>a DNS resolver</li>
+ <li>a module (<a href="refman_gen_net.html">net</a>) which can be used from Lua to access the network functions</li>
+ <li>a Telnet miniclient, which is used to support the eLua shell via TCP/IP instead of serial connections.</li>
+</ul>
+<br />
+
+<h2>TCP/IP configuration</h2>
+<p>To configure the TCP/IP subsystem, <i>edit src/platform/<name>platform_conf.h</i> and:</p>
+<ol>
+<li><b>#define BUILD_UIP</b> to enable TCP/IP support</li>
+<li>if you'll be using the DHCP client, just <b>#define BUILD_DHCPC</b> to build the
+ DHCP client. In any case, you must also define a static network configuration:
+
+<p><b>#define ELUA_CONF_IPADDR0 ... ELUA_CONF_IPADDR3</b> : the IP address<br>
+ <b>#define ELUA_CONF_NETMASK0 ... ELUA_CONF_NETMASK3</b> : the network mask<br>
+ <b>#define ELUA_CONF_DEFGW0 ... ELUA_CONF_DEFGW3</b> : the default gateway<br>
+ <b>#define ELUA_CONF_DNS0 ... ELUA_CONF_DNS3</b> : the DNS server </p>
+
+ <p>Note that you must define both <b>BUILD_DHCPC</b> and the <b>ELUA_CONF_*</b> macros. If the
+ DHCP client fails to obtain a valid IP address, the static configuration will
+ be used instead. To use only the static configuration (and make the eLua image
+ size a bit smaller) don't define the BUILD_DHCPC client.</p></li>
+
+<li><b>#define BUILD_DNSM</b> if you want support for the DNS server.</li>
+<li><b>#define BUILD_CON_TCP</b> if you want support for shell over telnet instead of
+ serial. Note that you must NOT define <b>BUILD_CON_GENERIC</b> in this case (see
+ <a href="arch_con_term.html">here</a> for details).</li>
+</ol>
+<p>You'll also need an uIP configuration file (<i>src/platform/<name>/uip-conf.h</i>) to configure the TCP/IP
+stack. For an example, look at <i>src/platform/<lm3s>/uip-conf.h</i>. The header if quite self-explanatory, below
+you have a list of parameters that you might want to change:</p>
+<ul>
+ <li><b>u8_t, u16_t</b>: define these types to match your platform.</li>
+ <li><b>UIP_CONF_MAX_CONNECTIONS</b>: the maximum number of TCP connections that can be active at a given time.</li>
+ <li><b>UIP_CONF_UDP_CONNS</b>: same thing for UDP connections.</li>
+ <li><b>UIP_CONF_BYTE_ORDER</b>: <b>LITTLE_ENDIAN</b> or <b>BIG_ENDIAN</b>, it's very important to match this with your architecture.</li>
+ <li><b>UIP_CONF_BUFFER_SIZE</b>: the size of the buffer used by uIP for all its connections. You should keep it small to avoid memory consumption,
+ but doing so when you have to transfer large amounts of data will slow the transfer speed. 1k seems to be a good compromise.</li>
+ <li><b>UIP_CONF_UDP</b>: turn off UDP support. While <b>eLua</b> doesn't have support for UDP via its <b>net</b> module at this time, UDP can still
+ be used (for example by DNS/DHCP), so be careful if you disable this.</li>
+ <li><b>ELUA_DHCP_TIMER_ID</b>: the timer ID used for the TCP/IP subsystem. Note that this should be a dedicated timer, not available to the rest
+ of the system (or available in "read-only" mode).</li>
+</ul>
+<br />
+
+<h2>TCP/IP implementation internals</h2>
+<p>The TCP/IP support was designed in such a way that it doesn't require a specific
+TCP/IP stack implementation. To work with <b>eLua</b>, a TCP/IP stack must simply
+implement all the functions defined in the inc/elua_net.h file. This allows for
+easy integration of more than one TCP/IP stack. Currently only uIP is used in
+eLua, but lwIP (and possibly others) are planned to be added at some point.
+Another key point of the TCP/IP implementation (and of the whole <b>eLua</b> design
+for that matter) is that it should be as platform independent as possible: write
+everything in a platform-independent manner, except for some functions (as few as
+possible and as simple as possible) that must be implemented by each platform.
+To illustrate the above, a short overview of the uIP integration is given below.</p>
+
+<p><a href="http://www.sics.se/~adam/uip/index.php/Main_Page">uIP</a> is a minimalistic TCP/IP
+stack designed specifically for resource constrained embedded systems. While the
+design and implementation of uIP are an excellent example of what can be done
+with a few kilobytes of memory, it has a number of quirks that make it hard to
+integrate with <b>eLua</b>. First, it uses a callback approach, as opposed to the
+sequential approach of "regular" TCP/IP stacks. It provides a "protosocket"
+library that can be used to write uIP applications in a more "traditional" way,
+but it's quite restrictive. So, to use it with <b>eLua</b>, a translation layer was
+needed. It is implemented in <i>src/elua_uip.c</i>, and its sole purpose is to "adapt"
+the uIP stack to the <b>eLua</b> model: implement the functions in <i>inc/elua_net.h</i> and
+you're ready to use the stack. In this case the "adaption layer" is quite large
+because of uIP's callback-based design.</p>
+
+<p>To make the uIP implementation as platform-independent as possible, a special
+<a href="arch_platform_eth.html">networking layer</a> is added to the <a href="arch_platform.html">platform interface</a>.
+There are only 4 functions that must be implemented by a backend
+to use the networking layer. They might change as more TCP/IP stacks are added
+to eLua, but probably the networking layer won't get much bigger than it is now.<br>
+For a more in-depth understanding of how the networking layer is implemented,
+look at the LM3S implementation in <i>src/platform/lm3s/platform.c</i>.
+</p>
+$$FOOTER$$
+
Modified: branches/eagle_mmc/doc/pt/bit_ref.html
===================================================================
--- branches/eagle_mmc/doc/pt/bit_ref.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/pt/bit_ref.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,98 +1,93 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Produto</title>
-
-<link rel="stylesheet" type="text/css" href="../style.css">
</head>
-<body style="background-color: rgb(255, 255, 255);">
<h3><a name="over"></a>bit</h3>
<p class="MsoNormal" style="font-family: Verdana;"><a name="bnot"></a>Res = bit.bnot( value ):
-negação
+negação
</p>
<p class="MsoNormal" style="font-family: Verdana;">
-
+
</p>
-<p class="MsoNormal" style="font-family: Verdana;"><a name="band"></a> Res = bit.band( v1, v2, ... ): <b>operação binária
+<p class="MsoNormal" style="font-family: Verdana;"><a name="band"></a> Res = bit.band( v1, v2, ... ): <b>operação binária
</b>"and"
</p>
<p class="MsoNormal" style="font-family: Verdana;">
-
+
</p>
-<p class="MsoNormal" style="font-family: Verdana;"><a name="bor"></a> Res = bit.bor( v1, v2, ... ): <b>operação binária</b><b>
+<p class="MsoNormal" style="font-family: Verdana;"><a name="bor"></a> Res = bit.bor( v1, v2, ... ): <b>operação binária</b><b>
</b>"or"
</p>
<p class="MsoNormal" style="font-family: Verdana;">
-
+
</p>
-<p class="MsoNormal" style="font-family: Verdana;"><a name="bxor"></a> Res = bit.bxor( v1, v2, ... ): <b>operação binária</b><b>
+<p class="MsoNormal" style="font-family: Verdana;"><a name="bxor"></a> Res = bit.bxor( v1, v2, ... ): <b>operação binária</b><b>
</b>"exclusive or"
</p>
<p class="MsoNormal" style="font-family: Verdana;">
-
+
</p>
<p class="MsoNormal" style="font-family: Verdana;"><a name="lshift"></a> Res = bit.lshift( value, pos ):
-desloca "value" em "pos" posições a esquerda.
+desloca "value" em "pos" posições a esquerda.
</p>
<p class="MsoNormal" style="font-family: Verdana;">
-
+
</p>
<p class="MsoNormal" style="font-family: Verdana;"><a name="rshift"></a> Res = bit.rshift( value, pos ):
-desloca "value" em "pos" posições a direita. O sinal não
+desloca "value" em "pos" posições a direita. O sinal não
</p>
<p class="MsoNormal" style="font-family: Verdana;">
- é propagado.
+ é propagado.
</p>
<p class="MsoNormal" style="font-family: Verdana;">
-
+
</p>
<p class="MsoNormal" style="font-family: Verdana;"><a name="arshift"></a> Res = bit.arshift( value, pos ):
-desloca "value" em "pos" posições a direita. O sinal
+desloca "value" em "pos" posições a direita. O sinal
</p>
<p class="MsoNormal" style="font-family: Verdana;">
- é propagado ("arithmetic shift").
+ é propagado ("arithmetic shift").
</p>
<p class="MsoNormal" style="font-family: Verdana;">
-
+
</p>
<p class="MsoNormal" style="font-family: Verdana;"><a name="bit"></a> Res = bit.bit( bitno ): um atalho para
bit.lshift( 1, bitno )
</p>
<p class="MsoNormal" style="font-family: Verdana;">
-
+
</p>
<p class="MsoNormal" style="font-family: Verdana;"><a name="set"></a> Res1, Res2, ... = bit.set( bitno, v1,
-v2, ... ): configura o bit na posição "bitno"
+v2, ... ): configura o bit na posição "bitno"
</p>
<p class="MsoNormal" style="font-family: Verdana;">
- em v1, v2, ... to 1.
+ em v1, v2, ... to 1.
</p>
<p class="MsoNormal" style="font-family: Verdana;">
-
+
</p>
<p class="MsoNormal" style="font-family: Verdana;"><a name="clear"></a> Res1, Res2, ... = bit.clear( bitno,
-v1, v2, ... ): configura o bit na posição
+v1, v2, ... ): configura o bit na posição
</p>
<p class="MsoNormal" style="font-family: Verdana;">
- "bitno" em v1, v2, ... para 0.
+ "bitno" em v1, v2, ... para 0.
</p>
<p class="MsoNormal" style="font-family: Verdana;">
-
+
</p>
<p class="MsoNormal" style="font-family: Verdana;"><a name="isset"></a> Res = bit.isset( value, bitno ):
-retorna verdadeiro se o bit na posição "bitno" em
+retorna verdadeiro se o bit na posição "bitno" em
</p>
<p class="MsoNormal" style="font-family: Verdana;">
- "value" é igual a 1, caso contrário retorna falso.
+ "value" é igual a 1, caso contrário retorna falso.
</p>
<p class="MsoNormal" style="font-family: Verdana;">
-
+
</p>
<p class="MsoNormal" style="font-family: Verdana;"><a name="isclear"></a> Res = bit.isclear( value, bitno ):
-retorna verdadeiro se o bit na posição "bitno" em
+retorna verdadeiro se o bit na posição "bitno" em
</p>
<p class="MsoNormal" style="font-family: Verdana;">
- "value" é igual a 0, caso contrário retorna falso.
+ "value" é igual a 0, caso contrário retorna falso.
</p>
<br style="font-family: Verdana;">
<br style="font-family: Verdana;">
Modified: branches/eagle_mmc/doc/pt/building.html
===================================================================
--- branches/eagle_mmc/doc/pt/building.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/pt/building.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,114 +1,238 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
+$$HEADER$$
+<h3>Gerando eLua</h3>
+<p>Se você chegou a conclusão que fica melhor gerar o seu próprio arquivo binário <b>eLua</b>
+ (ao invés de <a href="downloads.html">baixá-lo</a>), então será necessário verificarmos algumas coisas antes:
+</p>
+<ul>
+<li>você está usando Linux. É possível a compilação em windows, no entanto, ainda não foi testada. Usamos Ubuntu e o comando que utilizamos é o "apt-get". Caso você esteja com uma distro que possua um gerenciador de pacotes diferente, você terá que alterar o comando "apt-get" para um compatível com a sua distro.</li>
+<li>você possui um toolchain (compilador, linker e bibliotecas de assembler e C padrão) para o seu hardware. Dê uma olhada na página
+<a href="toolchains.html">toolchains</a> para obter ajuda. É importante observar que, mesmo que você já tenha um toolchain compilado, diferenças nos parâmetros de configuração da NewLib (principalmente os --disable-newlib-supplied-syscalls flags) podem gerar problemas e impedir que <b>eLua</b> seja gerada na sua máquina.</li>
+<li>você configurou a sua plataforma corretamente. Leia o próximo parágrafo para obter instruções de como configurar a geração de <b>eLua</b>.</li>
+<li>Python - Este deve estar previamente instalado. Caso contrário, execute o apt-get para instalá-lo:
+<pre><code>$ sudo apt-get install python</code></pre>
+</li>
+<li>Scons - <b>eLua</b> usa scons ao invés do make
+e makefiles, porque achamos que o scons é muito mais "natural" e fácil de usar do que o make. Para instalá-lo:
+<pre><code>$ sudo apt-get install scons</code></pre>
+</li>
+<li>o diretório "bin" do seu toolchain (normalmente algo como /usr/local/cross-arm/bin, onde /usr/local/cross-arm é o diretório de sua instalação toolchain) e deve estar definido no $PATH.
+</li>
+<li>se você está gerando para a plataforma i386, precisará também do "nasm":
+<pre><code>$ sudo apt-get install nasm</code></pre>
+</li>
+</ul>
+<p>Para cada plataforma, <b>eLua</b> assume um nome para os componentes do toolchain, como relacionado abaixo.
+</p>
+<p>Se seu toolchain utiliza nomes diferentes, entã você terá que modificar a definição do toolchain no SConstruct. Leia as <a href="toolchains.html">instruções</a> para maiores detalhes.</p>
+<h3>Configurando a imagem gerada</h3>
+<p><b>eLua</b> possui um sistema de geração de sua imagem bastante flexível, e que pode ser usado para selecionar os componentes desejados que farão parte do arquivo binário de <b>eLua</b> e também para configuração(estática) durante a compilação. Para usá-lo, será necessário editar somente um único arquivo (<i>platform_conf.h</i>)
+localizado no diretório da plataforma que está sendo utilizada (<i>src/platform/<platform
+name>/platform_conf.h)</i>. Os parâmetros de configuração estão descritos em detalhes nos próximos parágrafos.</p>
+<a name="components"><h2>Configurando os componentes</h2></a>
+<p>Um <b>componente</b> é um recurso que pode ser habilitado para adicionar funcionalidade a <b>eLua</b>, sem modificar sua API (rotinas usadas pelos programadores para escrever programas em <b>eLua</b>). Segue abaixo um exemplo da configuração de um componente em <i>platform_conf.h</i>:
+<p><pre><code>// *****************************************************************************
+// Define here what components you want for this platform
-<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);">
-<h3>Building eLua</h3>
-
-Up to date documentation of how to build eLua is always included in the <a href="http://www.eluaproject.net/?p=Downloads">eLua distributions</a>, in the docs directory).<br><p>For your convenience, the building instructions are also provided on this page.</p>
-
-<h2>Prerequisites</h2>
-
-<p>Before you start, you might want to check if the list of platform modules and
-eLua components are set according to your needs. See platform_modules
-and elua_components in the distro doc for details. </p>
-
-<h2>Building eLua</h2>
-
-<p>To build <strong>eLua</strong> you'll need:</p>
-
-<ul><li><p>a GCC/Newlib toolchain for your target. Please note that even if
- you already have a compiled toolchain, the differences in the Newlib configure
- flags (mainly the --disable-newlib-supplied-syscalls flags) might prevent
- eLua for building properly on your machine.</p></li><li><p>Linux. Compiling under windows should be possible, however this isn't tested.
- I'm using Ubuntu, so I'm also using "apt-get". If you're using a distro with a
- different package manager you'll need to translate the "apt-get" calls to your
- specific distribution.</p></li><li><p>python. It should be already installed; if it's not:</p>
-
- <p>$ sudo apt-get install python</p></li><li><p>scons. eLua uses scons instead of make and makefiles, because I find scons
- much more "natural" and easier to use than make. To install it:</p>
-
- <p>$ sudo apt-get install scons</p></li><li><p>your toolchain's "bin" directory (this is generally something like
- /usr/local/cross-arm/bin, where /usr/local/cross-arm is the directory in which
- you installed your toolchain) must be in $PATH. </p></li><li><p>if you're building for the i386 platform, you'll also need "nasm":</p>
-
- <p>$ sudo apt-get install nasm</p></li></ul>
-
-<p>For each platform, eLua assumes a certain name for the compiler/linker/assembler
-executable files, as shown below.</p>
-
-<pre><code>================================================================================<br>| Tool | Compiler | Linker | Assembler | <br>|------------|---------------------|----------------------|--------------------| <br>| Platform | | | |<br>|============|=====================|======================|====================|<br>| ARM (all) | arm-elf-gcc | arm-elf-gcc | arm-elf-gcc |<br>|============|=====================|======================|====================|<br>| i386 | i686-elf-gcc | i686-elf-gcc | nasm |<br>|============|=====================|======================|====================|<br>| Cortex-M3 | arm-elf-gcc | arm-elf-gcc | arm-elf-gcc |<br>|============|=====================|======================|====================|<br></code></pre>
-
-<p>If your toolchain uses different names, you have to modify the "conf.py" file
-from src/platform/[your platform].</p>
-
-<p>To build, go to the directory where you unpacked your eLua distribution and
-invoke scons:</p>
-
-<pre><code>$ scons [target=lua | lualong] <br> [cpu=at91sam7x256 | at91sam7x512 | i386 | str912fw44 | lm3s8962 | <br> lm3s6965 | lpc2888 | str711fr2 ]<br> [board=ek-lm3s8962 | ek-lm3s6965 | str9-comstick | sam7-ex256 | lpc-h2888 | <br> | mod711 | pc]<br> [cpumode=arm | thumb] <br> [allocator = newlib | multiple]<br> [prog]<br></code></pre>
-
-<p>Your build target is specified by two paramters: cpu and board. "cpu" gives the
-name of your CPU, and "board" the name of the board. A board can be associated
-with more than one CPU. This allows the build system to be very flexible. You
-can use these two options together or separately, as shown below:</p>
-
-<ul><li>cpu=name: build for the specified CPU. A board name will be assigned by the
- build system automatically.</li><li>board=name: build for the specified board. The CPU name will be inferred by
- the build system automatically.</li><li>cpu=name board=name: build for the specified board and CPU.</li></ul>
-
-<p>For board/CPU assignment look at the beginning of the SConstruct file from the
-base directory, it's self-explanatory.</p>
-
-<p>The other options are as follows:</p>
-
-<ul><li>target=lua | lualong: specify if you want to build full Lua (with floating
- point support) or integer only Lua (lualong). The default is "lua".</li><li>cpumode=arm | thumb: for ARM target (not Cortex) this specifies the
- compilation mode. Its default value is 'thumb' for AT91SAM7X targets and
- 'arm' for STR9 and LPC2888 targets.</li><li>allocator = newlib | multiple: choose between the default newlib allocator
- (newlib) and the multiple memory spaces allocator (multiple). You should
- use the 'multiple' allocator only if you need to support multiple memory
- spaces, as it's larger that the default Newlib allocator (newlib). For more
- information about this reffer to platform_interface. The default value
- is 'newlib' for all CPUs except 'lpc2888', since my lpc-h2888 comes with
- external SDRAM memory and thus it's an ideal target for 'multiple'.</li><li>prog: by default, the above 'scons' command will build only the 'elf' file.
- Specify "prog" to build also the platform-specific programming file where
- appropriate (for example, on a AT91SAM7X256 this results in a .bin file that
- can be programmed in the CPU). </li></ul>
-
-<p>The output will be a file named elua<em>[target]</em>[cpu].elf (and also another
-file with the same name but ending in .bin if "prog" was specified for platforms
-that need .bin files for programming).
-If you want the equivalent of a "make clean", invoke "scons" as shown above,
-but add a "-c" at the end of the command line. "scons -c" is also recommended
-after you change the list of modules/components to build for your target (see
-section "prerequisites" of this document), as scons seems to "overlook" the
-changes to these files on some occasions.</p>
-
-<p>A few examples:</p>
-
-<p>Clear previously built intermediate files.</p>
-
+#define BUILD_XMODEM
+#define BUILD_SHELL
+#define BUILD_ROMFS
+#define BUILD_TERM
+#define BUILD_UIP
+#define BUILD_DHCPC
+#define BUILD_DNS
+#define BUILD_CON_GENERIC
+#define BUILD_ADC</code></pre></p>
+<p>Os componentes que podem ser configurados em <b>eLua</b> são:
+</p>
+<table class="table_center">
+<tbody>
+<tr>
+<th style="text-align: left;">Nome</th>
+<th style="text-align: center;">Descrição</th>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">BUILD_XMODEM</td>
+<td>Estabelece a função de recepção XMODEM. Se habilitada, você pode usar o comando "recv" do shell para receber um arquivo Lua (tanto código fonte quanto código précompilado) e executá-lo no seu hardware. Funciona somente com conexões RS-232 (apesar de que, em teoria, é possível fazê-lo funcionar em qualquer tipo de protocolo de transporte).
+Para habilitar:
+<p><pre><code>#define BUILD_XMODEM</code></pre></p>
+<a href="building.html#static">Dependências da configuração de dados estáticos:</a> <b>CON_UART_ID, CON_UART_SPEED, CON_TIMER_ID</b>
+</td>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">BUILD_SHELL</td>
+<td>Etabelece a função de gerar um shell de <b>eLua</b> (veja <a href="using.html">usando eLua</a> para detalhes sobre o shell). Caso o shell não esteja habilitado, o código busca o arquivo chamado <i>/rom/autorun.lua</i> e executa-o. Se este arquivo não for encontrado, um interpretador Lua é iniciado automaticamente no seu hardware.<br>
+Para habilitar o shell usando uma conexão serial:
+<p><pre><code>#define BUILD_SHELL
+#define BUILD_CON_GENERIC</code></pre></p>
+Para habilitar o shell usando uma conexão TCP/IP:
+<p><pre><code>#define BUILD_SHELL
+#define BUILD_CON_TCP</code></pre></p>
+</td>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">BUILD_ROMFS</td>
+<td>Habilita o sistema de arquivos <b>eLua</b> somente para leitura. Veja a <a href="arch_romfs.html">documentação ROMFS</a> para maiores detalhes sobre como usar este sistema de arquivos.
+Para habilitar:
+<p><pre><code>#define BUILD_ROMFS</code></pre></p></td>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">BUILD_TERM</td>
+<td>Habilita o suporte ao terminal ANSI. Este recurso permite que <b>eLua</b> interaja com terminais que suportem sequências ANSI (mais detalhes <a href="arch_con_term.html">aqui</a>). Atualmente, este recurso funciona somente em conexões R-232, apesar desta não ser uma obrigação estrita. Você precisa habilitar este recurso, caso seja necessário usar o <a href="refman_gen_term.html">term module</a>.
+Para habilitar:
+<p><pre><code>#define BUILD_TERM</code></pre></p>
+<a href="building.html#static">Dependências da configuração de dados estáticos:</a> <b>CON_UART_ID, CON_UART_SPEED, CON_TIMER_ID, TERM_LINES, TERM_COLS</b></td>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">BUILD_UIP</td>
+<td>Habilita o suporte para o TCP/IP. Você precisa habilitar este recurso, caso seja necessário usar o <a href="refman_gen_net.html">net
+module</a>. Além disso, sua plataforma deve implementar o suporte para as funções uIP (veja a documentação <a href="arch_platform.html">platforminterface</a> para mais detalhes).
+Para habilitar:
+<p><pre><code>#define BUILD_UIP</code></pre></p>
+<a href="building.html#static">Dependências da configuração de dados estáticos:</a> <b>ELUA_CONF_IPADDR0..3, ELUA_CONF_NETMASK0..3, ELUA_CONF_DEFGW0..3,
+ ELUA_CONF_DNS0..3</b>
+</td>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">BUILD_DHCPC</td>
+<td>Se BUILD_UIP está ativado, você pode habilitar este recurso para incluir um cliente DHCP na rede TCP/IP.
+Para habilitar:
+<p><pre><code>#define BUILD_UIP
+#define BUILD_DHCPC</code></pre></p>
+</td>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">BUILD_DNS</td>
+<td>Se BUILD_UIP está ativado, você pode habilitar este recurso para incluir um servidor DNS mínimo na rede TCP/IP.
+Para habilitar:
+<p><pre><code>#define BUILD_UIP
+#define BUILD_DNS</code></pre></p>
+</td>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">BUILD_CON_GENERIC</td>
+<td>Suporte genérico para console (detalhes <a href="arch_con_term.html">aqui</a>). Habilita o acesso a console (stdio/stdout/stderr) via protocolo de transporte serial (atualmente RS-232, mas outros podem ser suportados). Ative este recurso caso você queira usar uma console de entrada/saída com sua conexão RS-232. Não ative este recurso caso você queira usar uma console de entrada/saída com Ethernet (veja a próxima opção).
+Para habilitar:
+<p><pre><code>#define BUILD_CON_GENERIC</code></pre></p>
+<a href="building.html#static">Dependências da configuração de dados estáticos:</a> <b>CON_UART_ID, CON_UART_SPEED, CON_TIMER_ID</b></td>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">BUILD_CON_TCP</td>
+<td>Console de entrada/saída sobre uma conexão TCP/IP (detalhes <a href="arch_con_term.html">aqui</a>). Use este recurso se você quiser usar sua placa <b>eLua</b> sobre uma conexão telnet. Não ative este recurso caso você precise de uma console com protocolo de transporte serial (veja a opção anterior).
+Para habilitar:
+<p><pre><code>#define BUILD_UIP
+#define BUILD_CON_TCP</code></pre></p>
+</td>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">BUILD_ADC</td>
+<td>Suporte genérico para código ADC. Você precisa ativar este recurso caso queira usar o módulo <a href="refman_gen_adc.html">adc</a>, ou simplesmente as funções ADC da interface da plataforma. Por outro lado, você não precisa ativar este recurso caso não esteja pensando em usar as funções ADC.
+Para habilitar:
+<p><pre><code>#define BUILD_ADC</code></pre></p>
+</td>
+</tr>
+</tbody>
+</table>
+<a name="confmodules"><h2>Configurando os módulos</h2></a>
+<p>Você pode selecionar os módulos que farão parte do arquivo imagem de <b>eLua</b>. Ao contrário dos componentes, os módulos têm um impacto direto na API de <b>eLua</b>, logo tenha cuidado ao selecioná-los. Ao desativar um módulo, você gera um espaço de memória flash (e possivelmente RAM), mas também irá remover completamente a possibilidade de usar este módulo de <b>eLua</b>.</p>
+<p>Os módulos incluídos na geração são epecificados pela macro LUA_PLATFORM_LIBS_ROM. Veja um exemplo abaixo: </p>
+<pre><code>#define LUA_PLATFORM_LIBS_ROM\
+ _ROM( AUXLIB_PIO, luaopen_pio, pio_map )\
+ _ROM( AUXLIB_TMR, luaopen_tmr, tmr_map )\
+ _ROM( AUXLIB_PD, luaopen_pd, pd_map )\
+ _ROM( AUXLIB_UART, luaopen_uart, uart_map )\
+ _ROM( AUXLIB_TERM, luaopen_term, term_map )\
+ _ROM( AUXLIB_PWM, luaopen_pwm, pwm_map )\
+ _ROM( AUXLIB_PACK, luaopen_pack, pack_map )\
+ _ROM( AUXLIB_BIT, luaopen_bit, bit_map )\
+ _ROM( AUXLIB_CPU, luaopen_cpu, cpu_map )\
+ ROM( LUA_MATHLIBNAME, luaopen_math, math_map )</code></pre>
+<p>Cada módulo é definido por uma macro <b>_ROM( module_name,
+module_init_function, module_map_array )</b>, onde:
+</p>
+<ul>
+<li><b>module_name</b> é o nome pelo qual o módulo pode ser usado a partir de eLua</li>
+<li><b>module_init_function</b> é uma função chamada pelo programa Lua em tempo de execução quando o módulo é inicializado</li>
+<li><b>module_map_array</b> é uma lista de todas as funções e constantes exportadas pelo módulo</li>
+</ul>
+<p>Por favor, observe que esta notação é específica para LTR (o patch <b>L</b>ua <b>T</b>iny <b>R</b>AM) e não é a única forma de especificar a lista dos módulos incluídos na geração (apesar desta ser uma forma comum). Verifique a <a href="arch_ltr.html#config">seção LTR</a> para mais informações sobre LTR.</p>
+<p>Para uma lista completa de todos os módulos que podem ser ativados ou desativados via <i>platform_conf.h</i>, veja <a href="refman_gen.html">the
+eLua reference manual</a>.</p>
+<a name="static"><h2>Dados da configuração estática</h2></a>
+<p>"Configuração estática" refere-se a configuração durante o tempo de compilação. Os parâmetros da configuração estática estão gravados na imagem do firmware e não podem ser alterados em tempo de execução. A tabela abaixo relaciona os parâmetros de configuração estática e suas semânticas.
+</p>
+<table class="table_center">
+<tbody>
+<tr>
+<th style="text-align: left;">Nome</th>
+<th style="text-align: center;">Descrição</th>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">CON_UART_ID<br>CON_UART_SPEED<br>CON_TIMER_ID<br></td>
+<td>Usado para configurar console de entrada/saída sobre a UART. Um id específico da UART será usado para a console de entrada/saída, a uma velocidade específica. O formato dos dados é sempre é 8N1 (8 bits de dados, sem paridade, 1 stop bit) neste ponto. O timer ID especificado será usado para o subsistema da console. Essas variáveis são usadas também pelas implementações do XMODEM e do TERM.</td>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">TERM_LINES<br>TERM_COLS<br>
+</td>
+<td>Usado para configurar o suporte ao terminal ANSI (caso esteja habilitado). Usado para especificar (respectivamente) o número de linhas e colunas do terminal ANSI.</td>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">ELUA_CONF_IPADDR0..3<br>
+ELUA_CONF_NETMASK0..3<br>
+ELUA_CONF_DEFGW0..3<br>
+ELUA_CONF_DNS0..3</td>
+<td>Usado pelo protocolo TCP/IP caso o cliente DHCP não esteja ativado, ou quando mesmo ativado, este náo tenha como ser contactado. Especifique o endereço IP, a máscara de rede, o gateway padrão e o servidor DNS. Necessário somente quando o BUILD_UIP for habilitado.</td>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">VTMR_NUM_TIMERS<br>
+VTMR_FREQ_HZ</td>
+<td>Especifique a configuração dos timers virtuais da plataforma (acesse a <a href="arch_platform_timers.html#virtual_timers">documentação do módulo timer</a> para detalhes). Defina VTMR_NUM_TIMERS como 0 caso este recurso não seja utilizado.</td>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">PLATFORM_CPU_CONSTANTS</td>
+<td>Se o <a href="refman_gen_cpu.html">cpu module</a>
+estiver ativado, este define uma relação de constantes da plataforma específica(por exempo máscaras de interrupção) que podem ser acessadas usando a notaço cpu.<constant name>. Os nomes de cada constante devem ser especificados ao invés de uma construção específica (<i>_C(<constantname></i>). Por exemplo:
+<pre><code>#define PLATFORM_CPU_CONSTANTS\<br> _C( INT_GPIOA ),\<br> _C( INT_GPIOB ),\<br> _C( INT_GPIOC ),\<br> _C( INT_GPIOD ),\<br> _C( INT_GPIOE )<br></code></pre>
+Após a compilação, você poderá acessar essas constantes usando <i>cpu.INT_GPIOx</i>.
+Observe que a implementação desses recursos não precisa de memória RAM, logo você poderá definir quantas constantes desejar.</td>
+</tr>
+</tbody>
+</table>
+<p>Os parâmetros da configuração estática restantes foram deixados para serem alterados pelos desenvolvedores e por este motivo, não estão relacionados aqui.<br>Outra coisa que você poderá querer configurar é o conteúdo do sistema de arquivo de sua ROM. Veja a <a href="arch_romfs.html">documentação ROMFS</a> para detalhes de como fazer isso.</p>
+<h3>Iniciando o "build system"</h3>
+<p>Agora, que você está com tudo em seu lugar, resta então executar o "build system" (scons) com os argumentos corretos. Este é um passo fácil, apesar da aparência intimidadora devido as múltiplas opções existentes no scons. São usadas para se ajustarem às suas necessidades específicas, mas a menos que suas necessidades sejam muito especiais, você não precisará modificá-las, logo não se preocupe com a aparente complexidade. Os exemplos no fim desta seção mostrarão como é fácil usar o "build system" na prática.</p>
+<pre><code>$ scons <br> [target=lua | lualong]<br> [cpu=at91sam7x256 | at91sam7x512 | i386 | str912fw44 | lm3s8962 | <br> lm3s6965 | lm3s6918 | lpc2888 | str711fr2 | at32uc3a0512 | stm32f103ze<br> [board=ek-lm3s8962 | ek-lm3s6965 | eagle-100 | str9-comstick | sam7-ex256 | <br> lpc-h2888 | mod711 | pc | atevk1100 | stm3210e-eval ]<br> [cpumode=arm | thumb] <br> [allocator = newlib | multiple | simple]<br> [toolchain = <toolchain name>]<br> [optram = 0 | 1]<br> [prog]<br></code></pre>
+<p>Seu hardware está especificado por dois parâmetros: cpu e placa. "cpu" representa o nome da cpu, e "placa" o nome de sua placa. Uma placa pode ser associada a mais de uma CPU. Esta característica permite ao "build system" ter bastante flexibilidade. Você pode usar estas duas opções juntas ou separadas, como mostrado a seguir:</p>
+<ul>
+<li><b>cpu=name</b>: gera para uma CPU específica. Um nome para a placa será gerado automaticamente pelo sistema.</li>
+<li><b>board=name</b>: gera para uma placa específica. Um nome para a CPU será inferido automaticamente pelo sistema.</li>
+<li><b>cpu=name board=name</b>: gera para uma placa e uma CPU. O script de geração não permitirá combinações invalidas de CPU/placa.</li>
+</ul>
+<p>Veja no inicio do arquivo SConstruct (<i>platform_list</i>) como configurar os parâmetros placa/CPU, são auto-explicativos.<br>
+As outras opções são mostradas a seguir:</p>
+<ul>
+<li><b>target=lua | lualong</b>: especifica se você deseja gerar Lua como "regular" (com suporte a ponto flutuante) ou somente "inteiro longo" (lualong). O default é "lua". "lualong" roda mais rápido em hardware que não possua co-processador para ponto flutuante (o que é o caso de todos os atuais hardwares que rodam <b>eLua</b>) mas não permite o suporte para operações de ponto flutuante, somente opera com inteiros.</li>
+<li><b>cpumode=arm | thumb</b>: para CPUs ARM (não use Cortex) especifica o modo de compilação. O valor default é 'thumb' para as CPUs AT91SAM7X e 'arm' para as CPUs STR9 e LPC2888.</li>
+<li><b>allocator = newlib | multiple | simple</b>: escolha entre o valor default (newlib) que é uma versão mais antiga do alocador dlmalloc, o alocador mútiplo de espaços de memória (multiple) que é uma versão mais recente do dlmalloc que permite tratar múltiplos espaços de memória, e um alocador de memória muito simples (simple) que é lento e não trata muito bem fragmentação, mas requer muito pouco recurso (Flash/RAM). Você só deve usar o alocador 'multiple' nos casos em que prescise de a espaços múltiplos de memória. O valor default é 'newlib' para todas as CPUs exceto a 'lpc2888' e a 'at32uc3a0512', desde que a LPC-H2888 e a placa ATEVK1100 venham com memória externa SDRAM e dessa maneira se tornam o hardware ideal para o uso do 'multiple'. Você deve utilizar 'simple' somente em sistemas com muita restriç&at!
ilde;o de recursos de hardware.</li>
+<li><b>toolchain=<toolchain name></b>:
+especifica o nome do toolchain usado para gerar a imagem. Veja <a href="toolchains.html#configuration">este link</a> para mais detalhes.</li>
+<li><b>optram=0 | 1</b>: habilita ou desabilita o patch LTR, veja a <a href="arch_ltr.html">documentação LTR</a> pra mais detalhes. O valor default é 1, que habilita o patch LTR.</li>
+<li><b>prog</b>: por default, o comando 'scons' acima gerará somente o arquivo 'elf' (executável). Quando necessário, acrescente o parâmetro "prog" para gerar também um arquivo de programação da plataforma específica (por exemplo, usando o AT91SAM7X256, este parâmetro resulta na geração de um arquivo .bin que poderá ser programado nesta CPU). </li>
+</ul>
+<p>O resultado será um arquivo chamado elua_<i>[target]</i>_<i>[cpu]</i>.elf
+(se o parâmetro "prog" foi especificado, no caso de plataformas que precisam deste parâmetro para programação, um outro arquivo também é gerado com o mesmo nome, porém terminando com .bin/.hex).<br>
+Se você deseja um comando equivalente a um "make clean", execute o "scons" como mostrado acima, mas acrescente um "-c" ao final da linha de comando. "scons -c" é também recomendado após você reconfigurar sua imagem gerada, já que o scons parece omitir as mudanças feitas nestes arquivos em alguns momentos.</p>
+<p><b>Alguns exemplos:</b></p>
<pre><code>$ scons cpu=at91sam7x256 -c <br></code></pre>
-
-<p>Build eLua for the AT91SAM7X256 CPU. The board name is detected as sam7-ex256.</p>
-
+<p>Apaga os arquivos gerados anteriormente.</p>
<pre><code>$ scons cpu=at91sam7x256<br></code></pre>
-
-<p>Build eLua for the SAM7-EX256 board. The CPU is detected as AT91SAM7X256.</p>
-
+<p>Gera eLua para uma CPU AT91SAM7X256. O nome da placa é detectado como sendo a sam7-ex256.</p>
<pre><code>$ scons board=sam7-ex256<br></code></pre>
-
-<p>Build eLua for the SAM7-EX256 board, but "overwrite" the default CPU. This is
-useful when you'd like to see how the specified board would behave with a
-different CPU (in the case of the SAM7-EX256 board it's possible to switch the
-on-board AT91SAM7X256 CPU for an AT91SAM7X512 which has the same pinout but
-comes with more Flash/RAM memory).</p>
-
+<p>Gera eLua para uma placa SAM7-EX256. A CPU AT91SAM7X256 é detectada.</p>
<pre><code>$ scons board=sam7-ex256 cpu=at91sam7x512<br></code></pre>
-
-<p>Build eLua for the lpc2888 CPU. The board name is detected as LPC-H2888. Also,
-the bin file required for target programming is generated.</p>
-
-<pre><code>$ scons cpu=lpc2888 prog </code></pre><br><br></body></html>
\ No newline at end of file
+<p>Gera eLua para a placa SAM7-EX256, porém define uma CPU específica. Isto é interessante quando você gostaria de saber como a placa especificada se comportará (em termos de recursos) com uma CPU diferente (no caso da placa SAM7-EX256 é possível mudar a CPU AT91SAM7X256 por uma AT91SAM7X512 a qual possui a mesma pinagem mas vem com mais memória Flash/RAM).</p>
+<pre><code>$ scons cpu=lpc2888 prog </code></pre>
+<p>Gera eLua para a CPU lpc2888. A placa é detectada como LPC-H2888. Aém disso, é gerado um arquivo bin necessário para a programação da CPU. O parâmetro allocator é detectado automaticamente como "multiple".</p>
+<pre><code>$ scons cpu=lm3s8962 toolchain=codesourcery prog</code></pre>
+<p>Gera a imagem para a CPU Cortex LM3S8962, mas usa o CodeSourcery toolchain ao invés do toolchain default (que é a toolchain "genérica" ARM GCC, normalmente a única gerada seguindo as instruções dos tutoriais deste site.</p>
+$$FOOTER$$
+
Modified: branches/eagle_mmc/doc/pt/comunity.html
===================================================================
--- branches/eagle_mmc/doc/pt/comunity.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/pt/comunity.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,55 +1,49 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Produto</title>
-
-<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);">
-<a name="lists"></a><h3>Lista de Discussão</h3>
-<p><strong></strong></p><p style="text-align: left;"><strong>eLua</strong> tem atualmente uma única lista de discussão. Você é bem-vindo em participar de nossa lista em
+$$HEADER$$
+<a name="lists"></a><h3>Lista de Discussão</h3>
+<p><strong></strong></p><p style="text-align: left;">O projeto <strong>eLua</strong> tem uma
+<strong>Lista de Discussão</strong> oficial e você é bem-vindo a visita-la em:
<a target="_top" href="https://lists.berlios.de/mailman/listinfo/elua-dev">https://lists.berlios.de/mailman/listinfo/elua-dev</a>.
-É importante observar que essa lista possui um moderador com o objetivo de se evitar o uso de spam, sendo assim necessário, que você faça a sua inscrição, caso decida participar de nossa lista. Mensagens de usuáros não inscritos são raramente aceitas.</p>
-<p style="text-align: left;"></p><p style="text-align: left;">Nosso repositório para desenvolvimento do projeto eLua encontra-se em um subversion server.
-Se você quiser manter-se informado sobre as atividades do nosso servidor SVN, inscreva-se também na nossa <strong>lista de atividades do servidor SVN</strong> em <a target="_top" href="https://lists.berlios.de/mailman/listinfo/elua-svn">https://lists.berlios.de/mailman/listinfo/elua-svn</a>.</p>
+Pedidos de inscrição são muito bem vindos e rapidamente processados. Mensagens de
+usuários não inscritos raramente são aceitas.</p>
+<p style="text-align: left;"></p><p style="text-align: left;">Nosso repositório para desenvolvimento do código de eLua encontra-se em um
+Servidor Subversion (SVN). Se você desejar se manter informado sobre as atividades do
+desenvolvimento, basta se inscrever também na nossa <strong>Lista de Atividade do servidor SVN</strong> em:<a target="_top" href="https://lists.berlios.de/mailman/listinfo/elua-svn">https://lists.berlios.de/mailman/listinfo/elua-svn</a>.</p>
<p></p><p><a href="https://lists.berlios.de/mailman/listinfo/elua-svn"></a></p>
-<span style="font-style: italic;"><a name="credits"></a></span><h3>Elua forums</h3>
+<span style="font-style: italic;"><a name="credits"></a></span><h3>Forum</h3>
<div class="content">
-<p>Ainda não temos um forum dedicado a <strong>eLua</strong>. No entanto, a partir de 22/2/2009, nossa lista de discussão foi copiada e disponibilizada em formato de forum <a target="_top" href="http://n2.nabble.com/eLua-Development-f2368040.html">neste endereço</a> (através do serviço <a target="_top" href="http://nabble.com">Nabble</a>).
-Se você quiser utilizar esta opção, <a target="_top" href="forum.html">clique aqui</a>.
+<p>O projeto <strong>eLua</strong> não tem um Forum dedicado a discussões. No entanto, desde 22/2/2009, nossa
+Lista de Discussão possui um Mirror em formato de Forum <a href="http://n2.nabble.com/eLua-Development-f2368040.html">neste
+endereço</a> (através do serviço <a href="http://nabble.com">Nabble</a>).:
+Se você desejar utilizar esta opção, <a href="forum.html">clique aqui</a>.
</p>
-
-<span style="font-style: italic;"><a name="credits"></a></span><h3>Créditos</h3>
-<div class="content">
-<p>Os autores de <strong>eLua</strong> agradecem a colaboração da comunidade pela esforço contínuo de desenvolvimento do projeto. Abaixo segue uma lista parcial em ordem alfabética com os nomes de alguns de nossos colaboradores:</p>
-
+<a name="credits" /><h3>Créditos</h3>
+<p>Os autores de <strong>eLua</strong> agradecem a colaboração de toda a
+comunidade de usuários com o desenvolvimento contÃnuo do projeto.<br />
+Apresentamos a seguir uma lista incompleta e ordenada alfabeticamente de
+contribuidores:</p>
<ul>
-<li>Alberto Fabiano</li>
-<li>André Carregal</li>
-<li>Cosmin Filip</li>
-<li>Diego Sueiro</li>
-<li>Everson Denis</li>
-<li>Fabio Pereira</li>
-<li>Fernando Araújo</li>
-<li>Frédéric Thomas</li>
-<li>Ives Cunha,</li>
-<li>James Snyder</li>
-<li>Marcelo Tílio</li>
-<li>Marco Meggiolaro</li>
-<li>Mike Panetta</li>
-<li>Pedro Bittencourt</li>
-<li>Rafael Barmak</li>
-<li>Rafael Sabbagg</li>
-<li>Ralph Hempel</li>
-<li>Raul Nunes</li>
-<li>Ricardo Rosa</li>
-<li>Roberto Ierusalimschy</li>
-<li>Téo Beijamin</li>
-<li>Yuri Takhteyev</li>
+ <li>Everson Denis and Flávio Nogueira - Tradução para português do site e
+ da documentação</li>
+ <li>Fréderic Thomas - Site hosting, melhorias para LM3S</li>
+ <li>James Snyder - Módulos ADC, CAN, LuaRPC (<a href="http://q12.org/lua/index.html">originalmente por Russell Smith</a>), testes</li>
+ <li>Mike Panetta - Portabilização para STM32</li>
+ <li>Pedro Bittencourt - Módulo para display RIT OLED para LM3S, <a href="http://code.google.com/p/vhews/">VHeHS</a>, Testes</li>
+ <li>Raul Nunes - Sustentabilidade e o apoio fundamental da <a href="http://www.puc-rio.br">PUC-Rio</a>.</li>
+ <li>Roberto Ierusalimschy, Luiz Henrique Figueiredo e Waldemar Celles - por <a href="http://www.lua.org">Lua</a> (!!! :)</li>
+ <li>Téo Benjamin, Ives Cunha, Rafael Barmak - Pong, TetrIves, SpaceShip e <a href="http://www.giga.puc-rio.br/site/embedded/manfredo">Manfredo</a>,
+ um robô autônomo, com navegação baseada em GPS, controlado por
+ <strong>eLua</strong>.</li>
+ <li>Toda a comunidade de usuários e desenvolvedores de nossa Lista de
+ Discussão em <a href="https://lists.berlios.de/mailman/listinfo/elua-dev">https://lists.berlios.de/mailman/listinfo/elua-dev</a></li>
</ul>
+ ... e a constante ajuda, incentivo e suporte de:<br />
+
+Alberto Fabiano, André Carregal, Ângelo Santos, Asko Kauppi, Cosmin Filip,
+Dean Hall, Diego Sueiro, Fabio Pereira, Giovani Balduino, Jesus Alvarez,
+John Hind, Luiz de Barros, Marcelo TÃio, Marco Meggiolaro, Ricardo
+L. Rosa, Robert Jakabosky, Yuri Takhteyev ...
-... e toda a comunidade de nossa lista de Discussão em <a href="https://lists.berlios.de/mailman/listinfo/elua-dev">https://lists.berlios.de/mailman/listinfo/elua-dev</a>.<strong style="font-weight: normal;"></strong></div>
-<br><br>
-<a name="galery"></a><a name="projects"></a>
-</body></html>
\ No newline at end of file
+</a>
+$$FOOTER$$
Modified: branches/eagle_mmc/doc/pt/cpu_ref.html
===================================================================
--- branches/eagle_mmc/doc/pt/cpu_ref.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/pt/cpu_ref.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,11 +1,6 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Produto</title>
-
-<link rel="stylesheet" type="text/css" href="../style.css">
</head>
-<body style="background-color: rgb(255, 255, 255);">
<h3><a name="over"></a>cpu</h3>
<p class="MsoNormal" style="font-family: Verdana;"><br>
</p>
Modified: branches/eagle_mmc/doc/pt/disp_ref.html
===================================================================
--- branches/eagle_mmc/doc/pt/disp_ref.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/pt/disp_ref.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,9 +1,6 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Produto</title>
-
-<link rel="stylesheet" type="text/css" href="../style.css">
+<link rel="stylesheet" type="text/css" href="../style.css"></link>
</head>
<body style="background-color: rgb(255, 255, 255);">
<h3><a name="over"></a>disp</h3>
Deleted: branches/eagle_mmc/doc/pt/dl_binaries.html
===================================================================
--- branches/eagle_mmc/doc/pt/dl_binaries.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/pt/dl_binaries.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,105 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
-
-<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);"><br><h3><span class="info"><a name="sources"></a>Downloading eLua pre-built binary images</span></h3>
-
-If you have an eLua capable hardware, you
-don't need to be a professional developer of the embedded world
-and to understand the details of the eLua building process, to be
-able to have eLua on your nice kits. <br><br>eLua project offers pre-built
-binary images for all the supported platforms.<br><br>All you have to do is to chose the
-corresponding image file from the table below, flash it into your
-board, connect a serial terminal (or Ethernet if you board supports)
-and enjoy eLua.<br><br>
-
-eLua binaries, like the <a href="dl_sources.html">source-code distributions</a>,
-include some example programs in it's file system, so you can run and
-play (yes! we have games too! :) them, following the instructions in
-our <a href="using.html">Using eLua</a> page. The available example programs are described in our <a href="examples.html">Examples</a> page.<br><br>
-
-If you need a customized binary image for an already supported
-platform (ie: with an autorun program, with some code of yours in the
-File System, with your LAN IP settings, .....) and you don't know how to build eLua, feel free to <a href="overview.html#contacts">write us</a> explaining what you need. We may (find some time to :) build one for you and eventually make it available here too.
-
-<br><br>To understand what's in a file name (for example elua_lualong_lm3s8962.bin) check our <a href="building.html">Building eLua</a> page, or at least the last part of it, where the meaning of the file names coming from the build system is explained.<br>
-
-
-<p><br></p><div><br><table class="table_center">
- <tbody><tr>
- <th>eLua Version</th>
- <th>Target MCU</th>
- <th>Lua Number</th>
- <th>Memory Usage(KB)</th>
- <th>Remarks</th>
- <th>Download File</th>
- </tr>
- <tr>
- <td>0.5</td>
- <td>Atmel ARM7</td>
- <td>Float</td>
- <td>ROM: ~189<br> RAM: 32~64</td>
- <td>Official eLua release</td>
- <td><a href="http://prdownload.berlios.de/elua/elua_lua_at91sam7x256.bin">elua_lua_at91sam7x256.bin</a></td>
- </tr>
- <tr>
- <td>0.5</td>
- <td>Atmel ARM7</td>
- <td>Float</td>
- <td>ROM: ~189<br> RAM: 32~64</td>
- <td>Official eLua release</td>
- <td><a href="http://prdownload.berlios.de/elua/elua_lua_at91sam7x512g.bin">elua_lua_at91sam7x512g.bin</a></td>
- </tr>
- <tr>
- <td>0.5</td>
- <td>Intel x86<br>(for fun :)</td>
- <td>Float</td>
- <td> </td>
- <td>Official eLua release</td>
- <td><a href="http://prdownload.berlios.de/elua/elua_lua_i386.elf">elua_lua_i386.elf</a></td>
- </tr>
- <tr>
- <td>0.5</td>
- <td>Luminary Micro ARM Cortex M3</td>
- <td>Float</td>
- <td>ROM: ~202<br> RAM: 32~64</td>
- <td>Official eLua release</td>
- <td><a href="http://prdownload.berlios.de/elua/elua_lua_lm3s6965.bin">elua_lua_lm3s6965.bin</a></td>
- </tr>
- <tr>
- <td>0.5</td>
- <td>Luminary Micro ARM Cortex M3</td>
- <td>Float</td>
- <td>ROM: ~202<br> RAM: 32~64</td>
- <td>Official eLua release</td>
- <td><a href="http://prdownload.berlios.de/elua/elua_lua_lm3s8962.bin">elua_lua_lm3s8962.bin</a></td>
- </tr>
- <tr>
- <td>0.5</td>
- <td>NXP ARM7</td>
- <td>Float</td>
- <td>ROM: ~229<br> RAM: 32~64</td>
- <td>Official eLua release</td>
- <td><a href="http://prdownload.berlios.de/elua/elua_lua_lpc2888.bin">elua_lua_lpc2888.bin</a></td>
- </tr>
- <tr>
- <td>0.5</td>
- <td>ST Microelectronics ARM7</td>
- <td>Float</td>
- <td>ROM: ~189<br> RAM: 32~64</td>
- <td>Official eLua release</td>
- <td><a href="http://prdownload.berlios.de/elua/elua_lua_str711fr2g.bin">elua_lua_str711fr2g.bin</a></td>
- </tr>
- <tr>
- <td>0.5</td>
- <td>ST Microelectronics ARM 9</td>
- <td>Float</td>
- <td>ROM: ~229<br> RAM: 32~64</td>
- <td>Official eLua release</td>
- <td><a href="http://prdownload.berlios.de/elua/elua_lua_str912fw44.bin">elua_lua_str912fw44.bin</a></td>
- </tr>
-</tbody></table><br></div><p>Notes:</p>
-
-<ul><li>Lua Number refers to the built Lua interpreter number type, float or integer.</li><li>RAM Memory Usage is based on included Lua examples execution.</li></ul></body></html>
\ No newline at end of file
Modified: branches/eagle_mmc/doc/pt/dl_old.html
===================================================================
--- branches/eagle_mmc/doc/pt/dl_old.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/pt/dl_old.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,82 +1,303 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
+$$HEADER$$
+<h3>Download de versões anteriores de eLua</h3>
+<p>As tabelas abaixo possuem links para as versões oficiais anteriores de <b>eLua</b> (código fonte e os binários).</p>
+<a name="v050" /><h2>0.5</h2>
+<table class="table_center">
+<tbody>
+<tr>
+<th>Version</th>
+<th>MCU</th>
+<th>Board</th>
+<th>Lua number type</th>
+<th>Image file</th>
+</tr>
+<tr>
+<td>0.5</td>
+<td>Todas (código fonte)</td>
+<td>Todas (código fonte)</td>
+<td>Todas (código fonte)</td>
+<td><a href="http://prdownload.berlios.de/elua/elua-0.5.tgz">elua-0.5.tgz</a></td>
+</tr>
+</tbody></table>
+<a name="v041" /><h2>0.4.1</h2>
+<table class="table_center">
+<tbody>
+<tr>
+<th>Versão</th>
+<th>MCU</th>
+<th>Placa</th>
+<th>Tipo Número-Lua</th>
+<th>Arquivo Imagem</th>
+</tr>
+<tr>
+<td>0.4.1</td>
+<td>Todas (código fonte)</td>
+<td>Todas (código fonte)</td>
+<td>Todas (código fonte)</td>
+<td><a href="http://prdownload.berlios.de/elua/elua-0.4.1.tgz">elua-0.4.1.tgz</a></td>
+</tr>
+</tbody></table>
-<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);"><br><h3><span class="info"><a name="old"></a>Downloading eLua Old Versions</span></h3><br><h2>Source Code</h2>Previous eLua versions, both for source code and binaries, can be downloaded from the <a href="http://developer.berlios.de/project/showfiles.php?group_id=9919">BerliOS files page</a><br><br><br><h2>Binaries</h2><br><p><br></p><div><br><table class="table_center">
- <tbody><tr>
- <th>eLua Version</th>
- <th>Target MCU</th>
- <th>Lua Number</th>
- <th>Memory Usage(KB)</th>
- <th>Remarks</th>
- <th>Download File</th>
- </tr>
- <tr>
- <td>0.5</td>
- <td>Atmel ARM7</td>
- <td>Float</td>
- <td>ROM: ~189<br> RAM: 32~64</td>
- <td>Official eLua release</td>
- <td><a href="http://prdownload.berlios.de/elua/elua_lua_at91sam7x256.bin">elua_lua_at91sam7x256.bin</a></td>
- </tr>
- <tr>
- <td>0.5</td>
- <td>Atmel ARM7</td>
- <td>Float</td>
- <td>ROM: ~189<br> RAM: 32~64</td>
- <td>Official eLua release</td>
- <td><a href="http://prdownload.berlios.de/elua/elua_lua_at91sam7x512g.bin">elua_lua_at91sam7x512g.bin</a></td>
- </tr>
- <tr>
- <td>0.5</td>
- <td>Intel x86<br>(for fun :)</td>
- <td>Float</td>
- <td> </td>
- <td>Official eLua release</td>
- <td><a href="http://prdownload.berlios.de/elua/elua_lua_i386.elf">elua_lua_i386.elf</a></td>
- </tr>
- <tr>
- <td>0.5</td>
- <td>Luminary Micro ARM Cortex M3</td>
- <td>Float</td>
- <td>ROM: ~202<br> RAM: 32~64</td>
- <td>Official eLua release</td>
- <td><a href="http://prdownload.berlios.de/elua/elua_lua_lm3s6965.bin">elua_lua_lm3s6965.bin</a></td>
- </tr>
- <tr>
- <td>0.5</td>
- <td>Luminary Micro ARM Cortex M3</td>
- <td>Float</td>
- <td>ROM: ~202<br> RAM: 32~64</td>
- <td>Official eLua release</td>
- <td><a href="http://prdownload.berlios.de/elua/elua_lua_lm3s8962.bin">elua_lua_lm3s8962.bin</a></td>
- </tr>
- <tr>
- <td>0.5</td>
- <td>NXP ARM7</td>
- <td>Float</td>
- <td>ROM: ~229<br> RAM: 32~64</td>
- <td>Official eLua release</td>
- <td><a href="http://prdownload.berlios.de/elua/elua_lua_lpc2888.bin">elua_lua_lpc2888.bin</a></td>
- </tr>
- <tr>
- <td>0.5</td>
- <td>ST Microelectronics ARM7</td>
- <td>Float</td>
- <td>ROM: ~189<br> RAM: 32~64</td>
- <td>Official eLua release</td>
- <td><a href="http://prdownload.berlios.de/elua/elua_lua_str711fr2g.bin">elua_lua_str711fr2g.bin</a></td>
- </tr>
- <tr>
- <td>0.5</td>
- <td>ST Microelectronics ARM 9</td>
- <td>Float</td>
- <td>ROM: ~229<br> RAM: 32~64</td>
- <td>Official eLua release</td>
- <td><a href="http://prdownload.berlios.de/elua/elua_lua_str912fw44.bin">elua_lua_str912fw44.bin</a></td>
- </tr>
-</tbody></table><br></div><p>Notes:</p>
+<a name="v04" /><h2>0.4</h2>
+<table class="table_center">
+<tbody>
+<tr>
+<th>Versão</th>
+<th>MCU</th>
+<th>Placa</th>
+<th>Tipo Número-Lua</th>
+<th>Arquivo Imagem</th>
+</tr>
+<tr>
+<td>0.4</td>
+<td>Todas (código fonte)</td>
+<td>Todas (código fonte)</td>
+<td>Todas (código fonte)</td>
+<td><a href="http://prdownload.berlios.de/elua/elua_0.4.tgz">elua_0.4.tgz</a></td>
+</tr>
+<tr>
+<td>0.4</td>
+<td><a href="http://www.atmel.com/dyn/products/Product_card.asp?part_id=3755">AT91SAM7X256</a></td>
+<td><a href="http://www.olimex.com/dev/sam7-ex256.html">SAM7-EX256</a></td>
+<td>double</td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.4_lua_at91sam7x256.bin">elua0.4_lua_at91sam7x256.bin</a></td>
+</tr>
+<tr>
+<td>0.4</td>
+<td><a href="http://www.atmel.com/dyn/products/Product_card.asp?part_id=4104">AT91SAM7X512</a></td>
+<td>Nenhum</td>
+<td>double</td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.4_lua_at91sam7x512.bin">elua0.4_lua_at91sam7x512.bin</a></td>
+</tr>
+<tr>
+<td>0.4</td>
+<td><a href="http://www.intel.com">i386 (generic)</a></td>
+<td>PCs/emulators</td>
+<td>double</td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.4_lua_i386.elf">elua0.4_lua_i386.elf</a></td>
+</tr>
+<tr>
+<td>0.4</td>
+<td><a href="http://www.luminarymicro.com/products/lm3s6965.html">LM3S6965</a></td>
+<td><a href="http://www.luminarymicro.com/products/lm3s6965_ethernet_evaluation_kit.html">EKx-LM3S6965</a></td>
+<td>double</td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.4_lua_lm3s6965.bin">elua0.4_lua_lm3s6965.bin</a></td>
+</tr>
+<tr>
+<td>0.4</td>
+<td><a href="http://www.luminarymicro.com/products/LM3S8962.html">LM3S8962</a></td>
+<td><a href="http://www.luminarymicro.com/products/lm3s8962_can_ethernet_evaluation_kit.html">EKx-LM3S8962</a></td>
+<td>double</td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.4_lua_lm3s8962.bin">elua0.4_lua_lm3s8962.bin</a></td>
+</tr>
+<tr>
+<td>0.4</td>
+<td><a href="http://www.standardics.nxp.com/microcontrollers/to/pip/LPC2880FET180.html">LPC2888</a></td>
+<td><a href="http://www.olimex.com/dev/lpc-h2888.html">LPC-H2888</a></td>
+<td>double</td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.4_lua_lpc2888.bin">elua0.4_lua_lpc2888.bin</a></td>
+</tr>
+<tr>
+<td>0.4</td>
+<td><a href="http://www.st.com/mcu/devicedocs-STR912FAW44-101.html">STR912FAW44</a></td>
+<td><a href="http://www.hitex.com/index.php?id=383">STR9-comStick</a></td>
+<td>double</td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.4_lua_str912fw44.bin">elua0.4_lua_str912fw44.bin</a></td>
+</tr>
+<tr>
+<td>0.4</td>
+<td><a href="http://www.atmel.com/dyn/products/Product_card.asp?part_id=3755">AT91SAM7X256</a></td>
+<td><a href="http://www.olimex.com/dev/sam7-ex256.html">SAM7-EX256</a></td>
+<td>inteiro (32-bit)</td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.4_lualong_at91sam7x256.bin">elua0.4_lualong_at91sam7x256.bin</a></td>
+</tr>
+<tr>
+<td>0.4</td>
+<td><a href="http://www.atmel.com/dyn/products/Product_card.asp?part_id=4104">AT91SAM7X512</a></td>
+<td>Nenhum</td>
+<td>inteiro (32-bit)</td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.4_lualong_at91sam7x512.bin">elua0.4_lualong_at91sam7x512.bin</a></td>
+</tr>
+<tr>
+<td>0.4</td>
+<td><a href="http://www.intel.com">i386 (genérico)</a></td>
+<td>PCs/emuladores</td>
+<td>inteiro (32-bit)</td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.4_lualong_i386.elf">elua0.4_lualong_i386.elf</a></td>
+</tr>
+<tr>
+<td>0.4</td>
+<td><a href="http://www.luminarymicro.com/products/lm3s6965.html">LM3S6965</a></td>
+<td><a href="http://www.luminarymicro.com/products/lm3s6965_ethernet_evaluation_kit.html">EKx-LM3S6965</a></td>
+<td>inteiro (32-bit)</td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.4_lualong_lm3s6965.bin">elua0.4_lualong_lm3s6965.bin</a></td>
+</tr>
+<tr>
+<td>0.4</td>
+<td><a href="http://www.luminarymicro.com/products/LM3S8962.html">LM3S8962</a></td>
+<td><a href="http://www.luminarymicro.com/products/lm3s8962_can_ethernet_evaluation_kit.html">EKx-LM3S8962</a></td>
+<td>inteiro (32-bit)</td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.4_lualong_lm3s8962.bin">elua0.4_lualong_lm3s8962.bin</a></td>
+</tr>
+<tr>
+<td>0.4</td>
+<td><a href="http://www.standardics.nxp.com/microcontrollers/to/pip/LPC2880FET180.html">LPC2888</a></td>
+<td><a href="http://www.olimex.com/dev/lpc-h2888.html">LPC-H2888</a></td>
+<td>inteiro (32-bit)</td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.4_lualong_lpc2888.bin">elua0.4_lualong_lpc2888.bin</a></td>
+</tr>
+<tr>
+<td>0.4</td>
+<td><a href="http://www.st.com/mcu/devicedocs-STR912FAW44-101.html">STR912FAW44</a></td>
+<td><a href="http://www.hitex.com/index.php?id=383">STR9-comStick</a></td>
+<td>inteiro (32-bit)</td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.4_lualong_str912fw44.bin">elua0.4_lualong_str912fw44.bin</a></td>
+</tr>
+</tbody>
+</table>
-<ul><li>Lua Number refers to the built Lua interpreter number type, float or integer.</li><li>RAM Memory Usage is based on included Lua examples execution.</li></ul><br><br><br><br></body></html>
\ No newline at end of file
+<a name="v03" /><h2>0.3</h2>
+<table class="table_center">
+<tbody>
+<tr>
+<th>Versão</th>
+<th>MCU</th>
+<th>Placa</th>
+<th>Tipo Número-Lua</th>
+<th>Arquivo Imagem</th>
+</tr>
+<tr>
+<td>0.3</td>
+<td>Todas (código fonte)</td>
+<td>Todas (código fonte)</td>
+<td>Todas (código fonte)</td>
+<td><a href="http://prdownload.berlios.de/elua/elua_0.3.tgz">elua_0.3.tgz</a></td>
+</tr>
+<tr>
+<td>0.3</td>
+<td><a href="http://www.atmel.com/dyn/products/Product_card.asp?part_id=3755">AT91SAM7X256</a></td>
+<td><a href="http://www.olimex.com/dev/sam7-ex256.html">SAM7-EX256</a></td>
+<td>double</td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.3_lua_at91sam7x256.bin">elua0.3_lua_at91sam7x256.bin</a></td>
+</tr>
+<tr>
+<td>0.3</td>
+<td><a href="http://www.atmel.com/dyn/products/Product_card.asp?part_id=4104">AT91SAM7X512</a></td>
+<td>Nenhum</td>
+<td>double</td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.3_lua_at91sam7x512.bin">elua0.3_lua_at91sam7x512.bin</a></td>
+</tr>
+<tr>
+<td>0.3</td>
+<td><a href="http://www.intel.com">i386 (generic)</a></td>
+<td>PCs/emuladores</td>
+<td>double</td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.3_lua_i386.elf">elua0.3_lua_i386.elf</a></td>
+</tr>
+<tr>
+<td>0.3</td>
+<td><a href="http://www.luminarymicro.com/products/lm3s6965.html">LM3S6965</a></td>
+<td><a href="http://www.luminarymicro.com/products/lm3s6965_ethernet_evaluation_kit.html">EKx-LM3S6965</a></td>
+<td>double</td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.3_lua_lm3s6965.bin">elua0.3_lua_lm3s6965.bin</a></td>
+</tr>
+<tr>
+<td>0.3</td>
+<td><a href="http://www.luminarymicro.com/products/LM3S8962.html">LM3S8962</a></td>
+<td><a href="http://www.luminarymicro.com/products/lm3s8962_can_ethernet_evaluation_kit.html">EKx-LM3S8962</a></td>
+<td>double</td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.3_lua_lm3s8962.bin">elua0.3_lua_lm3s8962.bin</a></td>
+</tr>
+<tr>
+<td>0.3</td>
+<td><a href="http://www.st.com/mcu/devicedocs-STR912FAW44-101.html">STR912FAW44</a></td>
+<td><a href="http://www.hitex.com/index.php?id=383">STR9-comStick</a></td>
+<td>double</td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.3_lua_str912fw44.bin">elua0.3_lua_str912fw44.bin</a></td>
+</tr>
+</tbody>
+</table>
+
+<a name="v02" /><h2>0.2</h2>
+<table class="table_center">
+<tbody>
+<tr>
+<th>Versão</th>
+<th>MCU</th>
+<th>Placa</th>
+<th>Tipo Número-Lua</th>
+<th>Arquivo Imagem</th>
+</tr>
+<tr>
+<td>0.2</td>
+<td>Todas (código fonte)</td>
+<td>Todas (código fonte)</td>
+<td>Todas (código fonte)</td>
+<td><a href="http://prdownload.berlios.de/elua/elua_0.2.tar.gz">elua_0.2.tar.gz</a></td>
+</tr>
+<tr>
+<td>0.2</td>
+<td><a href="http://www.atmel.com/dyn/products/Product_card.asp?part_id=3755">AT91SAM7X256</a></td>
+<td><a href="http://www.olimex.com/dev/sam7-ex256.html">SAM7-EX256</a></td>
+<td>double</td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.2_lua_at91sam7x256.bin">elua0.2_lua_at91sam7x256.bin</a></td>
+</tr>
+<tr>
+<td>0.2</td>
+<td><a href="http://www.intel.com">i386 (generic)</a></td>
+<td>PCs/emulaores</td>
+<td>double</td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.2_lua_i386.elf">elua0.2_lua_i386.elf</a></td>
+</tr>
+<tr>
+<td>0.2</td>
+<td><a href="http://www.luminarymicro.com/products/LM3S8962.html">LM3S8962</a></td>
+<td><a href="http://www.luminarymicro.com/products/lm3s8962_can_ethernet_evaluation_kit.html">EKx-LM3S8962</a></td>
+<td>double</td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.2_lua_lm3s8962.bin">elua0.2_lua_lm3s8962.bin</a></td>
+</tr>
+<tr>
+<td>0.2</td>
+<td><a href="http://www.atmel.com/dyn/products/Product_card.asp?part_id=3755">AT91SAM7X256</a></td>
+<td><a href="http://www.olimex.com/dev/sam7-ex256.html">SAM7-EX256</a></td>
+<td>inteiro (32-bit)</td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.2_lualong_at91sam7x256.bin">elua0.2_lualong_at91sam7x256.bin</a></td>
+</tr>
+<tr>
+<td>0.2</td>
+<td><a href="http://www.intel.com">i386 (generic)</a></td>
+<td>PCs/emuladores</td>
+<td>inteiro (32-bit)</td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.2_lualong_i386.elf">elua0.2_lualong_i386.elf</a></td>
+</tr>
+<tr>
+<td>0.2</td>
+<td><a href="http://www.luminarymicro.com/products/LM3S8962.html">LM3S8962</a></td>
+<td><a href="http://www.luminarymicro.com/products/lm3s8962_can_ethernet_evaluation_kit.html">EKx-LM3S8962</a></td>
+<td>inteiro (32-bit)</td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.2_lualong_lm3s8962.bin">elua0.2_lualong_lm3s8962.bin</a></td>
+</tr>
+</tbody>
+</table>
+
+
+<a name="v01" /><h2>0.1</h2>
+<table class="table_center">
+<tbody>
+<tr>
+<th>Versão</th>
+<th>MCU</th>
+<th>Placa</th>
+<th>Tipo Número-Lua</th>
+<th>Arquivo Imagem</th>
+</tr>
+<tr>
+<td>0.1</td>
+<td>Todas (código fonte)</td>
+<td>Todas (código fonte)</td>
+<td>Todas (código fonte)</td>
+<td><a href="http://luaforge.net/frs/download.php/3564/elua_0.1.tar.gz">elua_0.1.tar.gz</a></td>
+</tr>
+</tbody></table>
+$$FOOTER$$
+
Deleted: branches/eagle_mmc/doc/pt/dl_sources.html
===================================================================
--- branches/eagle_mmc/doc/pt/dl_sources.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/pt/dl_sources.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,50 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Produto</title>
-
-<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);"><br><h3><span class="info"><a name="sources"></a>Baixando código fonte de eLua</span></h3><h2>Versões Oficiais</h2>
-
-<h4>Código Fonte</h4>
-
-<p>A última versão liberada é a v0.6 e está disponível para download aqui:
-####<br>
-O pacote inclui o código fonte completo, documentação, scripts e exemplos de programa em Lua.<br></p>
-
-
-<p>Depois de baixar e descompactar os arquivos para o seu computador, abra o documento index_pt.html na pasta /doc e você terá acesso a documentação. São os arquivos deste site quando da liberação da versão v0.6.
- Como este site é atualizado frequentemente, verifique sempre a versão online por <a href="news.html">novidades e atualizações de eLua</a>.</p><p>Você encontrará instruções de como compilar eLua na página <a href="building.html">Montando eLua</a>.</p><br><br>
-
-
-<h2><a name="svnpublic"></a>Repositório Público Subversion </h2>
-
-<p>Caso você prefira ter a última versão que ainda está em desenvolvimento ("bleeding edge"), simplesmente baixe-a em nosso repositório Subversion com o seguinte comando:</p>
-
-<pre>$ svn checkout svn://svn.berlios.de/elua/trunk<code><br></code></pre>
-
-
-<p>Para atualizar os seus arquivos use o seguinte comando:</p>
-
-<pre>$ svn update<code><br></code></pre>
-<p><br></p>
-
-<h2>Navegando pelo Repositório Subversion</h2>
-Caso você esteja procurando uma maneira mais fácil de ter acesso ao repositório SVN, use a <a href="http://svn.berlios.de/wsvn/elua">interface WebSVN</a><br><h2></h2>
-
-<h2><a name="svndev"></a>Repositório Subversion para desenvolvedores</h2>
-
-<p>Se você deseja contribuir para o desenvolvimento de eLua e precisa salvar arquivos no repositório, siga os seguintes passos:</p>
-
-<ul><li>se você não tem uma conta no <a href="http://developer.berlios.de/">developer.berlios.de,</a> crie uma antes de passar para o próximo passo.</li><li><a href="../../../../../../websites/elua%20site/www.eluaproject.net/index8603.html?p=Contact">entre em contato</a>, especificando a sua identificação no BerliOS e nós iremos incluí-lo na lista de desenvovedores.</li></ul>
-
-
-<p>Faça o download do repositório:</p>
-
-<pre>$ export SVN_SSH='ssh -l <yourberliosid>'<br style="font-family: Courier New;"><br style="font-family: Courier New;">$ svn checkout svn+ssh://svn.berlios.de/svnroot/repos/elua/trunk<code><br></code></pre>
-
-<p>Para atualizar os seus arquivos use o seguinte comando:</p>
-
-<pre>$ svn update<code><br></code></pre>
-
-<p><br></p><br><br><br><p></p><p></p><p></p><p></p></body></html>
\ No newline at end of file
Added: branches/eagle_mmc/doc/pt/doc.html
===================================================================
--- branches/eagle_mmc/doc/pt/doc.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/pt/doc.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,17 @@
+$$HEADER$$
+<h3>Documentação</h3>
+<p>Nesta seção você encontrará; a documentação completa de <b>eLua</b> tanto para usuá;rios quanto para desenvolvedores, incluindo (mas não se limitando a):
+<ul>
+ <li>como fazer um build de <b>eLua</b></li>
+ <li>como compilar e instalar os toolchains necessá;rios para um
+ build de <b>eLua</b></li>
+ <li>como utilizar <b>eLua</b></li>
+ <li>descrição de exemplos de programas-fontes de <b>eLua</b></li>
+</ul></p>
+<p>Aquele que desejar contribuir com o código fonte de <b>eLua</b> encontrará; aqui muita informação importante:<ul>
+ <li>descrição da arquitetura de <b>eLua</b></li>
+ <li>as regras de codificação padrão de <b>eLua</b></li>
+ <li>como portar <b>eLua</b> para uma nova plataforma</li>
+</ul>
+</p>
+$$FOOTER$$
Modified: branches/eagle_mmc/doc/pt/downloads.html
===================================================================
--- branches/eagle_mmc/doc/pt/downloads.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/pt/downloads.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,7 +1,132 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Produto</title>
+$$HEADER$$
+<h3>Baixando eLua</h3>
+<p>Existem algumas opções para você fazer o download de <b>eLua</b>:</p>
+<ul>
+ <li>download do arquivo de imagem binário de <b>eLua</b> para a sua plataforma escolhida. Imagens binárias são fornecidas a cada lançamento de versão oficial e também para algumas aplicações especÃficas (ex: jogos). Esta é geralmente a melhor opção caso você tenha uma placa que é oficialmente suportada por <b>eLua</b> (veja <a href="status.html">aqui</a> para mais detalhes) e você quer ter <b>eLua</b> instalada e funcionando em sua placa o mais rápido possÃvel.</li>
+ <li>download do código-fonte para a geração de <b>eLua</b>. Você pode tanto baixar o código fonte de uma versão oficial ou obter
+ a versão em desenvolvimento do repositório SVN. Baixe o código fonte em vez de uma imagem binária, caso você precise fazer ajustes no código fonte para suportar sua placa ou se você quiser personalizar a imagem de <b>eLua</b>, ou ainda se você simplesmente quer dar uma olhada no que acontece por trás do prompt <i>eLua# </i> :)</li>
+</ul>
+<br />
+<br />
+<a name="binaries" /><h3>Imagens Binárias</h3>
+<p>Podem ser baixadas imagens binárias de <b>eLua</b> de cada lançamento oficial. Aqui abordaremos somente a última versão oficial de <b>eLua</b>, mas caso você queira baixar uma imagem de uma versão mais antiga (embora isso não seja aconselhável), visite <a href="dl_old.html">esta página</a>. Escolha o arquivo imagem correspondente na tabela abaixo, grave-o em sua placa, ligue um terminal serial (ou ethernet se sua placa aceitar) e aproveite <b>eLua</b>. Observe que tanto os <b>arquivos binários</b> quanto a distribuição do código fonte de <b>eLua</b>, incluem alguns programas de exemplos, sendo assim, você poderá rodar e jogar (sim, existem jogos também!:), seguindo as instruções na nossa página <a href="using.html">Usando eLua</a>. Os programas de exemplos disponÃveis estão descritos na nossa <a href="examples.html">página de exemplos</a>.</p><br />
+<p>Se você precisa de uma imagem binária personalizada para uma plataforma já suportada (por exemplo, com um programa de execução automática, com algum código especÃfico criado por você já incluÃdo no sistema, com as configurações da sua rede IP) e as <a href="building.html">instruções para a geração eLua</a> não servem para você, sinta-se a vontade para <a href="overview.html#contacts">escrever-nos</a> explicando o que você precisa exatamente. Assim, tentaremos encontrar algum tempo para gerar uma imagem para você e, eventualmente, também disponibilizá-la aqui.</p><br />
+<p>Para entender como é feita a formação de um nome de arquivo (por exemplo <i>elua_lualong_lm3s8962.bin</i>) consulte nossa página <a href="building.html">Gerando eLua</a>.</p>
+<!-- [NEWVER] -->
+<table class="table_center">
+<tbody>
+<tr>
+<th>Versão</th>
+<th>MCU</th>
+<th>Placa</th>
+<th>Tipo Num. Lua</th>
+<th>arquivo imagem</th>
+</tr>
+<tr>
+<td>0.6</td>
+<td><a href="http://www.atmel.com/dyn/products/Product_card.asp?part_id=3755">AT91SAM7X256</a></td>
+<td><a href="http://www.olimex.com/dev/sam7-ex256.html">SAM7-EX256</a></td>
+<td>double</td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.6_lua_at91sam7x256.bin">elua0.6_lua_at91sam7x256.bin</a></td>
+</tr>
+<tr>
+<td>0.6</td>
+<td><a href="http://www.atmel.com/dyn/products/Product_card.asp?part_id=4104">AT91SAM7X512</a></td>
+<td>Nenhum</td>
+<td>double</td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.6_lua_at91sam7x512.bin">elua0.6_lua_at91sam7x512.bin</a></td>
+</tr>
+<tr>
+<td>0.6</td>
+<td><a href="http://www.intel.com">i386 (genérico)</a></td>
+<td>PCs/emuladores</td>
+<td>double</td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.6_lua_i386.elf">elua0.6_lua_i386.elf</a></td>
+</tr>
+<tr>
+<td>0.6</td>
+<td><a href="http://www.luminarymicro.com/products/lm3s6965.html">LM3S6965</a></td>
+<td><a href="http://www.luminarymicro.com/products/lm3s6965_ethernet_evaluation_kit.html">EKx-LM3S6965</a></td>
+<td>double</td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.6_lua_lm3s6965.bin">elua0.6_lua_lm3s6965.bin</a></td>
+</tr>
+<tr>
+<td>0.6</td>
+<td><a href="http://www.luminarymicro.com/products/LM3S8962.html">LM3S8962</a></td>
+<td><a href="http://www.luminarymicro.com/products/lm3s8962_can_ethernet_evaluation_kit.html">EKx-LM3S8962</a></td>
+<td>double</td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.6_lua_lm3s8962.bin">elua0.6_lua_lm3s8962.bin</a></td>
+</tr>
+<tr>
+<td>0.6</td>
+<td><a href="http://www.standardics.nxp.com/microcontrollers/to/pip/LPC2880FET180.html">LPC2888</a></td>
+<td><a href="http://www.olimex.com/dev/lpc-h2888.html">LPC-H2888</a></td>
+<td>double</td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.6_lua_lpc2888.bin">elua0.6_lua_lpc2888.bin</a></td>
+</tr>
+<tr>
+<td>0.6</td>
+<td><a href="http://www.st.com/mcu/devicedocs-STR711FR2.html">STR711FR2</a></td>
+<td><a href="http://www.sctec.com.br/content/view/101/30/">MOD711</a></td>
+<td>double</td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.6_lua_str711fr2.bin">elua0.6_lua_str711fr2.bin</a></td>
+</tr>
+<tr>
+<td>0.6</td>
+<td><a href="http://www.st.com/mcu/devicedocs-STR912FAW44-101.html">STR912FAW44</a></td>
+<td><a href="http://www.hitex.com/index.php?id=383">STR9-comStick</a></td>
+<td>double</td>
+<td><a href="http://prdownload.berlios.de/elua/elua0.6_lua_str912fw44.bin">elua0.6_lua_str912fw44.bin</a></td>
+</tr>
+</tbody>
+</table>
+<p><b>NOTA:</b> <i>Tipo numérico de Lua</i> refere-se ao tipo numérico do interpretador Lua gerado, ponto-flutuante ou inteiro, como já explicado na página <a href="building.html">Gerando eLua</a>.</p>
+<br />
+<br />
+<a name="source" /><h3>Código Fonte</h3>
+<p>Mas se tudo o que você quer, é dar uma espiada no código-fonte de <b>eLua</b>, então não é preciso baixá-lo, veja a <a href="http://svn.berlios.de/wsvn/elua">interface BerliOS WebSVN</a>. Você pode dessa maneira navegar através do fonte completo de <b>eLua</b>. Se realmente você precisa baixar o código fonte de <b>eLua</b>, poderá tanto:</p>
+<ul>
+ <li>Baixar o código-fonte de uma versão oficial</li>
+ <li>Baixar o código-fonte do repositório SVN no modo só de leitura (modo anônimo)</li>
+ <li>Baixar o código-fonte do repositório SVN no modo de gravação (para desenvolvedores)</li>
+</ul>
+<br />
+<br />
+<a name="official" /><h2>Arquivos do código fonte</h2>
+<p>Verifique na tabela abaixo o link de download do código-fonte associado com a última versão oficial de <b>eLua</b>. Se você deseja obter o código fonte de uma versão mais antiga, confira <a href="dl_old.html">esta página</a>.</p>
+<!-- [NEWVER] -->
+<table class="table_center">
+<tbody>
+<tr>
+<th>Version</th>
+<th>Arquivos do código fonte</th>
+</tr>
+<tr>
+<td>0.6</td>
+<td><a href="http://prdownload.berlios.de/elua/elua-0.6.tgz">eLua 0.6</a></td>
+</tr>
+</tbody></table>
+<br />
+<br />
+<a name="svnpublic" /><h2>Repositório público SVN (modo anônimo somente-leitura)</h2>
+<p>Caso você prefira a última versão em desenvolvimento ("bleeding edge"), basta verificar em nosso repositório Subversion da seguinte maneira:</p>
+<pre>$ svn checkout svn://svn.berlios.de/elua/trunk</pre>
+<p>Uma vez feita a verificação, o repositório pode ser facilmente atualizado através do comando:</p>
+<pre>$ svn update</pre>
+<br />
+<br />
+<a name="svndev" /><h2>Repositório público SVN (modo de gravação com login de autenticação, para desenvolvedores)</h2>
+<p>Siga os passos abaixo, caso você precise de acesso de gravação para o repositório <b>eLua</b>:</p>
+<ul>
+ <li>Crie uma conta de acesso ao <a href="http://developer.berlios.de/">developer.berlios.de</a>
+ caso você planeje contribuir com código para o projeto.</li>
+ <li><a href="overview.html#contacts">Entre em contato conosco</a> para identificar o seu ID e lhe daremos acesso de gravação
+ (commit) ao repositório subversion.</li>
+</ul>
+<p>Então, faça uma verificação no repositório:</p>
+<pre>$ export SVN_SSH='ssh -l <yourberliosid>'
+$ svn checkout svn+ssh://svn.berlios.de/svnroot/repos/elua/trunk</pre>
+<p>Uma vêz feito, o repositório poderá ser facilmente atualizado com:</p>
+<pre>$ svn update</pre>
+$$FOOTER$$
-<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);"><h3><a name="title" href="http://www.eluaproject.net/en/Booting_eLua_from_a_stick"></a><span class="info">Downloads</span></h3><br></body></html>
\ No newline at end of file
Modified: branches/eagle_mmc/doc/pt/eluaapi.html
===================================================================
--- branches/eagle_mmc/doc/pt/eluaapi.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/pt/eluaapi.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,11 +1,6 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Produto</title>
-
-<link rel="stylesheet" type="text/css" href="../style.css">
</head>
-<body style="background-color: rgb(255, 255, 255);">
<h3><a name="over"></a>API eLua</h3>
<br>
<br>
Modified: branches/eagle_mmc/doc/pt/examples.html
===================================================================
--- branches/eagle_mmc/doc/pt/examples.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/pt/examples.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,53 +1,47 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Exemplos de eLua</title>
-
-<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);">
-<h3>Exemplos de código Lua</h3>Distribuições eLua trazem ótimos e interessantes (claro! tem jogos também! :) exemplos de programas em Lua.
-Eles estão incluídos também na distribuição que vem com os códigos fontes, no subdiretório /romfs. <br>Programas Lua para eLua são mostrados e comentados aqui também. <br>Como já foi dito, você pode rodá-los a partir do sistema de arquivos de eLua ou pode usar o shell de eLua e enviá-los através do XMODEM, como or you can use the eLua shell and send them via XMODEM, as
+$$HEADER$$
+<h3>Exemplos de código Lua</h3>Distribuições eLua trazem ótimos e interessantes (claro! tem jogos também! :) exemplos de programas em Lua.
+Eles estão incluÃdos também na distribuição que vem com os códigos fontes, no subdiretório /romfs. <br>Programas Lua para eLua são mostrados e comentados aqui também. <br>Como já foi dito, você pode rodá-los a partir do sistema de arquivos de eLua ou pode usar o shell de eLua e enviá-los através do XMODEM, como or you can use the eLua shell and send them via XMODEM, as
descrito <a href="using.html#shell">aqui</a>.<br><br>
-<h3><a name="hello"></a>hello.lua: o obíquo "Hello, World!"</h3>
+<h3><a name="hello"></a>hello.lua: o obÃquo "Hello, World!"</h3>
<p><strong>Roda em: </strong><br>Todas as arquiteturas</p><p><strong></strong>
-<strong>Descrição:<br></strong>Chamar isto de um "programa" é um grande exagero, mas já é uma
-tradição, logo, vamos mantê-la :) Este programa imprime "Hello, World!" em um terminal e
-retorna para o shell. Baixe-o somente se sentir-se muito incomodado em executar o interpretador Lua inserido em eLua e digitá-lo você mesmo :)</p><p><strong>Código fonte comentado:</strong><br></p><p>print("Hello World")</p>
+<strong>Descrição:<br></strong>Chamar isto de um "programa" é um grande exagero, mas já é uma
+tradição, logo, vamos mantê-la :) Este programa imprime "Hello, World!" em um terminal e
+retorna para o shell. Baixe-o somente se sentir-se muito incomodado em executar o interpretador Lua inserido em eLua e digitá-lo você mesmo :)</p><p><strong>Código fonte comentado:</strong><br></p><p>print("Hello World")</p>
<h2><br></h2><h3><a name="info"></a>info.lua: Obtendo os dados sobre a plataforma</h3>
-<p><strong>Roda em: </strong><br>Todas as arquiteturas</p><p><strong>Descrição:<br></strong>
-Este programa não é muito mais complicado do que o "Hello, World!", porém ele mostra um módulo específico de eLua: o módulo "platform data" (pd). Você pode ler
-mais sobre os módulos "platform" na distribuição do código fonte
-(docs/platform_modules.txt). O programa mostrará o nome da plataforma, o nome da CPU, o nome da placa e o clock da CPU e então finaliza e volta para o shell.</p><p><strong>Código fonte comentado:</strong></p><p><span>-- Usa o módulo pd para ter acesso aos dados da plataforma e mostrá-lo no Terminal </span><br><span>print( "Estou usando a platforma " .. pd.platform() ) </span><br><span>print( "A CPU é uma " .. pd.cpu() )</span><br><span><span>print( "A placa é uma " .. pd.board(</span>) )</span><br></p><p></p>
+<p><strong>Roda em: </strong><br>Todas as arquiteturas</p><p><strong>Descrição:<br></strong>
+Este programa não é muito mais complicado do que o "Hello, World!", porém ele mostra um módulo especÃfico de eLua: o módulo "platform data" (pd). Você pode ler
+mais sobre os módulos "platform" na distribuição do código fonte
+(docs/platform_modules.txt). O programa mostrará o nome da plataforma, o nome da CPU, o nome da placa e o clock da CPU e então finaliza e volta para o shell.</p><p><strong>Código fonte comentado:</strong></p><p><span>-- Usa o módulo pd para ter acesso aos dados da plataforma e mostrá-lo no Terminal </span><br><span>print( "Estou usando a platforma " .. pd.platform() ) </span><br><span>print( "A CPU é uma " .. pd.cpu() )</span><br><span><span>print( "A placa é uma " .. pd.board(</span>) )</span><br></p><p></p>
<h3><a name="led"></a>led.lua: o velho LED que pisca, jeito novo de fazer com eLua</h3>
-<p><strong>Roda em: </strong><br>Todas as arquiteturas exceto i386</p><p><strong>Descrição:<br></strong><strong></strong>
-Agora temos que fazer algo com "cara" de embarcado: piscar um LED. O código a seguir ilustra alguns recursos interessantes de eLua:</p>
+<p><strong>Roda em: </strong><br>Todas as arquiteturas exceto i386</p><p><strong>Descrição:<br></strong><strong></strong>
+Agora temos que fazer algo com "cara" de embarcado: piscar um LED. O código a seguir ilustra alguns recursos interessantes de eLua:</p>
-<ul><li><p>código portátil entre plataformas: o código atribue um pino diferente
-para o LED começando pelo nome da placa. Você pode ver como o módulo de dados da plataforma torna a portabilidade do código muito fácil.</p></li><li><p>uart, pio, tmr, pd modules: todas eles são usados aqui.</p></li></ul>
+<ul><li><p>código portátil entre plataformas: o código atribue um pino diferente
+para o LED começando pelo nome da placa. Você pode ver como o módulo de dados da plataforma torna a portabilidade do código muito fácil.</p></li><li><p>uart, pio, tmr, pd modules: todas eles são usados aqui.</p></li></ul>
-<p>Observe ele piscando, então pressione qualquer tecla para voltar ao shell de eLua.</p><p><strong>Código fonte comentado:</strong></p>
+<p>Observe ele piscando, então pressione qualquer tecla para voltar ao shell de eLua.</p><p><strong>Código fonte comentado:</strong></p>
<h3><a name="hangman"></a>hangman.lua: tirando vantagem de seu terminal</h3>
<p><strong>Roda em: </strong><br>Todas as arquiteturas exceto i386</p><strong></strong>
-<strong></strong><p><strong>Descrição:<br></strong>Muito longe de ser o melhor exemplo da distribuição eLua (ou poderia ser o morse.lua? :), ele faz uso do
-módulo term (docs/terminal_support.txt) para deixar o usuário jogar como no
+<strong></strong><p><strong>Descrição:<br></strong>Muito longe de ser o melhor exemplo da distribuição eLua (ou poderia ser o morse.lua? :), ele faz uso do
+módulo term (docs/terminal_support.txt) para deixar o usuário jogar como no
BSD "hangman" diretamente no seu emulador de terminal. Rode o exemplo
-e aproveite. Atualmente existe uma pequena lista de palavras, pois este programa foi escrito principalmente com o propósito de testar a capacidade de eLua, mas é muito fácil
+e aproveite. Atualmente existe uma pequena lista de palavras, pois este programa foi escrito principalmente com o propósito de testar a capacidade de eLua, mas é muito fácil
acrescentar e substituir palavras na lista atual. Uma tela de exemplo pode ser vista <a href="http://elua.berlios.de/other/elua_hangman.png">aqui</a>.</p><p></p>
-<h3><a name="pwmled"></a>pwmled.lua: Piscador de LED, classe avançada</h3><p><strong>Roda em: </strong><br>EK-LM3S8962, EK-LM3S6965</p><strong></strong>
+<h3><a name="pwmled"></a>pwmled.lua: Piscador de LED, classe avançada</h3><p><strong>Roda em: </strong><br>EK-LM3S8962, EK-LM3S6965</p><strong></strong>
-<strong></strong><p><strong>Descrição:<br></strong>
-Este programa usa o módulo PWM para acender/apagar a luz do LED gradualmente, indefinidamente. Nada mais a dizer aqui, o código é bem simples, ainda que os
+<strong></strong><p><strong>Descrição:<br></strong>
+Este programa usa o módulo PWM para acender/apagar a luz do LED gradualmente, indefinidamente. Nada mais a dizer aqui, o código é bem simples, ainda que os
resultados sejam bem interessantes. Presione qualquer tecla para finalizar o programa e retornar ao shell.</p><p></p>
<h3><a name="tvbgone"></a>tvbgone.lua: yes, eLua can do real time!</h3>
@@ -130,4 +124,6 @@
<p>This is still work in progress, but it already works quite well.
Take a look at romfs/index.pht and romfs/test.lua from the source
distribution for an example of how to include Lua code in your HTML
-files.</p><p></p><p></p><p></p></body></html>
\ No newline at end of file
+files.</p>
+$$FOOTER$$
+
Modified: branches/eagle_mmc/doc/pt/faq.html
===================================================================
--- branches/eagle_mmc/doc/pt/faq.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/pt/faq.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,209 +1,143 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
+$$HEADER$$
+<h3>Perguntas mais Frequentes de eLua</h3><p>Bem-vindo à FAQ oficial de <b>eLua</b><br />
+Assumimos aqui que você já conhece o básico de <b>eLua</b> e que esta lista de perguntas (e respectivas respostas) poderão ser úteis.</p>
-<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);">
-<h3>eLua Frequently Asked Questions</h3><br><p>Welcome to the official eLua FAQ!
-It is assumed that you already know <a>what eLua is</a>, so here's a list of questions you might find useful while exploring eLua.</p>
+<ul>
+ <li><a href="#learnlua">Como posso aprender Lua? É difÃcil?</a></li>
+ <li><a href="#helpelua">Como posso ajudar o Projeto eLua?</a></li>
+ <li><a href="#comercial">Posso usar eLua no meu projeto comercial de código fechado?</a></li>
+ <li><a href="#fast">eLua é rápida o bastante para minha aplicação?</a></li>
+ <li><a href="#minimum">Quais são os pré-requisitos mÃnimos para eLua?</a></li>
+ <li><a href="#portability">Tenho usado os módulos da plataforma Lua (uart, spi, pwm, tmr...), posso realmente usar o mesmo código em todas as minhas diferentes plataformas?</a></li>
+ <li><a href="#luaversions">Qual a diferença entre Lua Ponto-Flutuante e Lua Inteiro?</a></li>
+ <li><a href="#windows">Todos os seus tutoriais fornecem instruções sobre como compilar eLua sob o Linux, mas parece que você usa muitas ferramentas do Windows. Como pode isso?</a></li>
+ <li><a href="#cygwin">Voces irão fornecer intruções sobre como montar toolchains sob Cygwin no Windows?</a></li>
+ <li><a href="#bytecode">Sei que um programa Lua pode ser compilado para bytecode, então fiz a compilação de um dos exemplos eLua com o luac e tentei executá-lo em minha placa eLua, mas não funcionou. Isso é um bug no eLua?</a></li>
+ <li><a href="#outofmemory">Quando tento executar meus programas em Lua, recebo a mensagem de erro "falta de memória", o que devo fazer?</a></li>
+ <li><a href="#rotables">Instalei o patch LTR, mas agora todas as tabelas dos meus módulos (math, io, string, spi e assim por diante) estão como somente para leitura. Terei que desinstalar o patch LTR, se quiser ter permissão de gravação nesses módulos?</a></li>
+</ul>
-<ul><li><p><a href="faq.html#learnlua">How can I learn Lua? Is it hard?</a><br></p></li><li><p><a href="faq.html#helpelua">How can I help eLua?</a><br></p></li><li><p><a href="faq.html#comercial">Can I use eLua in my commercial, closed source project?</a><br></p></li><li><p><a href="faq.html#fast">Is eLua fast enough?</a><br></p></li><li><p><a href="faq.html#minimuns">What are the minimum requirements for eLua?</a><br></p></li><li><p><a href="faq.html#portability">Since
-I'm using the Lua platform modules (uart, spi, pwm, tmr...), can I
-trust my peripheral code to run the same on all my platforms?</a><br></p></li><li><p><a href="faq.html#luaversions">What's the deal with floating-point Lua and integer only Lua?</a><br></p></li><li><p><a href="faq.html#windows">All your tutorials give instructions on how to compile eLua under Linux, yet you seem to use a lot of Windows tools. How come?</a><br></p></li><li><p><a href="faq.html#cygwin">Will you ever post instructions about how to compile toolchains under Cygwin in Windows?</a><br></p></li><li><p><a href="faq.html#bytecode">I
-know that Lua can be compiled to bytecode, so I compiled one of the
-eLua examples with luac and tried to run it on my eLua board, but it
-didn't work. Is this a bug in eLua?</a><br></p></li><li><p><a href="faq.html#outofmemory">I get "out of memory" errors when I run my Lua programs, what should I do?</a><br></p></li></ul>
+<hr />
-<p><br></p>
+<a name="learnlua" /><h2>Como posso aprender Lua? É difÃcil?</h2>
+<p>Lua é uma linguagem minimalista (e mesmo assim muito poderosa) e muito fácil de se aprender. Uma vêz
+entendidos os conceitos básicos, você começará a programar em Lua imediatamente. A <a href="http://www.lua.org/">página de Lua na internet</a> é sua principal fonte de informação.
-<hr>
+Na <a href="http://www.lua.org/docs.html">página de documentação</a> do site, você vai encontrar o manual de referência e a primeira edição do excelente livro versão "Programando em Lua". Recomendamos que você adquira a segunda edição deste livro, já que você irá encontrar tudo que você realmente precisa aprender de Lua. Outra fonte muito interessante é
+a <a href="http://lua-users.org/wiki/">wiki Lua</a>. Se você precisar de mais ajuda, consulte a <a href="http://www.lua.org/community.html">página da comunidade</a>. Lua tem uma comunidade muito amigável e bastante ativa.
-<p><a name="learnlua"></a>
-<strong>Q: How can I learn Lua? Is it hard?</strong></p>
+<a name="helpelua" /><h2>Como posso ajudar eLua?</h2>
+<p><b>eLua</b> tem muitas metas ambiciosas, por isso seria ótimo ter mais pessoas trabalhando
+conosco. Dê uma olhada na <a href="status.html#roadmap">página roadmap</a>
+e, se houver interesse em colaborar, não hesite em <a href="overview.html#contacts">contactar-nos</a>. Além disso, se você quiser fazer uma doação para o projeto (dinheiro, ou talvez uma placa para desenvolvimento) esteja certo que não iremos
+recusar :) Seus reports de bugs encontrados em testes de <b>eLua</b> em suas
+placas e suas idéias sobre recursos legais são tão valiosos quanto. Se assim for, não hesite em <a href="overview.html#contacts">nos contactar</a>.
-<p>A: Lua is a minimalistic language (yet very powerful) which is quite
-easy to learn. Once you understand the basic concepts you'll find
-yourself writing Lua programs in notime. The main resource is the <a target="_top" href="http://www.lua.org/">Lua homepage</a>. In the <a target="_top" href="http://www.lua.org/docs.html">documentation page</a>
-you'll find the reference manual and the first version of the excellent
-"Programming in Lua" book. I recommend purchasing the second version of
-this book, since it's likely that this is all you'll ever need to learn
-Lua. Another very good resource is the <a target="_top" href="http://lua-users.org/wiki/">Lua wiki</a>. If you need more help, check the <a target="_top" href="http://www.lua.org/community.html">community page</a>. Lua has a very friendly and active community.</p><p></p><br><p><a name="helpelua"></a>
-<strong>Q: How can I help eLua?</strong></p>
+<a name="comercial" /><h2>Posso usar eLua no meu projeto comercial de código fechado?</h2>
+<p>A partir da versão 0.6, <b>eLua</b> é distribuÃda sob a licença MIT e
+isto permite que seja usada em projetos comerciais e de código proprietário.
+Antes disso, foi distribuÃda sob a GPL, o que restringia seu a aplicações open source.
+Fique atento entretando, porque <b>eLua</b> atualmente contém algumas (poucas) bibliotecas de terceiros, cada uma com seus próprios termos de licença que podem ser mais restritos que do MIT. Veja a <a href="overview.html#license">licença eLua</a> para mais detalhes.</p>
-<p>A: OK, so I lied, this is NOT a frequently asked question :)
-However, if you really want to help eLua, keep in mind that we're
-looking for developers. eLua has many ambitious goals, so it would be
-great to have more people working on it. Take a look at the <a href="status.html#roadmap">roadmap page</a>, and if you see something there that you'd like to implement, don't hesitate to <a href="overview.html#contacts">contact us</a>.
-Also, if you'd like to make a donation to the project (money, or maybe
-a development board) rest assured that wwe won't say no :) It also
-helps a lot if you test eLua on your own board and you find a bug or an
-incomplete feature. Or if you just thought about a cool feature that
-you'd like to see in eLua. If so, feel free to <a href="overview.html#contacts">contact us</a>.</p><p></p>
+<a name="fast" /><h2>eLua é rápida o bastante para minha aplicação?</h2>
+<p>Isso depende muito de suas expectativas. Se você espera que o seu código
+em Lua rode tão rápido quanto o seu código C compilado isso não irá acontecer, simplesmente porque C é uma linguagem compilada enquanto a Lua é uma linguagem interpretada. Dito isso, você vai ficar feliz em saber que a Lua é uma das linguagens interpretadas mais rápidas que existem por aÃ. Se você realmente precisa de muita velocidade e de Lua, você pode (muito
+facilmente em eLua) escrever as seções crÃticas em seções de código C e exportá-los como um módulo Lua. Desta forma, você terá o melhor de dois mundos.<br />
-<p><a name="comercial"></a>
-<strong>Q: Can I use eLua in my commercial, closed source project?</strong></p>
-<p>A: ### This needs to be updated for the BSD license .........</p><p></p>
+ Atualmente não temos nenhuma referência oficial sobre a velocidade de Lua em dispositivos embarcados mas você
+ pode dar uma olhada no exemplo TV-B-Gone na página <a href="examples.html">examplos</a>. TV-B-Gone é uma aplicação de controle remoto escrita em <b>eLua</b>.
+ Se você estiver familiarizado com os protocolos de controle remoto, você vai saber que esse tipo de aplicação é executada em "tempo real" e atrasos na ordem de milisegundos ou até menos
+ podem fazer o seu software de controle remoto falhar. No entanto, este exemplo é executado sem problemas em uma CPU
+ Cortex-M3 50MHz (em modo Thumb2). Este exemplo deve fornecer-lhe uma visão bastante intuitiva sobre a velocidade da eLua.
-<p><a name="fast"></a>
-<strong>Q: Is eLua fast enough?</strong></p>
-
-<p>A: This pretty much depends on what you expect. If you expect your
-Lua code to run as fast as your compiled C code, this won't happen,
-simply because C is a compiled language, while Lua is an interpreted
-language. That said, you'll be happy to know that Lua is one of the
-fastest interpreted languages out there. If you really need both high
-speed and Lua, you can write your speed critical code sections in C and
-export them as a Lua module. This way you get the best of both worlds.
-We don't have any official benchmarks about Lua speed on embedded
-devices, but you might want to check the TV-B-Gone example on the <a href="examples.html">examples page</a>.
-TV-B-Gone is a "software remote control" application coded directly in
-eLua. If you're familiar with the remote control protocols, you'll know
-that this kind of application is quite "real time", and delays in the
-order of milliseconds or even less can make your software remote
-control fail. Yet this sample runs without problems on a 50MHz Cortex
-(Thumb2) CPU. This should give you a fairly intuitive view on the speed
-of eLua.</p><p></p>
-
-<p><a name="minimuns"></a>
-<strong>Q: What are the minimum requirements for eLua?</strong></p>
-
-<p>A: It's hard to give a precise answer to this. As a general rule for
+<a name="minimum" /><h2>What are the minimum requirements for eLua?</h2>
+<p>It's hard to give a precise answer to this. As a general rule for
a 32-bit CPU, we recommend at least 256k of Flash (program memory) and
at least 64k of RAM. However, this isn't a strict requirement. A
stripped down, integer-only version of eLua can definetely fit in 128k
of Flash, and depending on your type of application, 32k of RAM might
-prove just fine. It largely depends on your needs.</p><p></p>
+prove just fine. It largely depends on your needs.</p>
-<p><a name="portability"></a>
-<strong>Q: Since I'm using the Lua platform modules (uart, spi, pwm,
-tmr...), can I trust my peripheral code to run the same on all my
-platforms?</strong></p>
+<a name="portability" /><h2>Since I'm using the Lua platform modules (uart, spi, pwm, tmr...), can I trust my peripheral code to run the same on all my
+ platforms?</h2>
+<p>Unfortunately, no. While <b>eLua</b> makes it possible to have a common code on different platforms using the <a href="arch_platform.html">platform interface</a>,
+ it can't possibly provide the same functionality on all platforms, since all MCUs are not created equal. It is very recommended
+ (and many times imperative) to have an understanding of the peripherals on your particular MPU before you start writing your code.
+ This, of course, is not particular to <b>eLua</b>, but it's especially important since the platform interface might give the impression that it
+ offers an uniform functionality over all platforms, when in fact the only thing in common is often just the interface itself (that is, the methods and
+ variables you can access in a given module). <b>eLua</b> tries to help here by giving you an error when you try to access a physical resource that is
+ not available (for example a timer, a PWM channel, or a PIO pin/port), but it doesn't try to cover all the possible platform-related issues, since this
+ would increase the code size and complexity too much. These are some caveats that come to mind (note that these are only a few examples, the complete
+ list is much longer):</p>
+<ul>
+ <li><b>timers</b>: from all the platforms on which <b>eLua</b> runs, only the Luminary Cortex CPUs has rock solid 32-bit timers. You can do pretty much
+ everything you need with them. All the other platforms have 16-bit timers, which imposes some limits on the range of delays you can achieve with them.
+ Make sure to use tmr.mindelay(id) and tmr.maxdelay(id) to check the actual resolution of your timers, and adapt your code accordingly. To 'compensate'
+ for this, it's not possible to change the base timer frequency on the Cortex CPUs, but it is possible on most other platforms :) So be sure to also check
+ the result of tmr.setclock(id)</li>
+ <li>also, when using timers, remember that if you're using XMODEM and/or the "term" module, one of them (generall TMR0) is used by both of them. So, if
+ you change the TMR0 base clock in your code, be sure to restore the original setting before returning to the <b>eLua</b> shell.</li>
+ <li><b>PWM</b>: the Cortex CPUs have 6 PWM channels, but channels 0/1, 2/3 and 4/5 respectively share the same base clock setting. So, when you're
+ changing the base clock for channel 1, you're also changing the base clock for channel 0; if channel 0 was already running, you won't like
+ what will happen next. This time no eLua function can save you, you simply need you know your CPU architecture.</li>
+ <li><b>GPIO</b>: only some platform have internal pullups for the GPIO pins (others might also have pulldowns). However, in this case you're safe, as
+ <b>eLua</b> will signal an error if you try to execute a pullup operatin on a platform that does not support it.</li>
+</ul>
+<p>The lesson here is clear: understand your platform first!</p>
-<p>A: Unfortunately, no. While eLua makes it possible to have a common
-code on different platforms using the platform interface
-(docs/platform_interface.txt), it can't possibly provide the same
-functionality on all platforms, since all CPUs are not created equal.
-It is very recommended (and many times imperative) to have an
-understanding of the peripherals on your particular CPU before you
-write your code. This, of course, is not particular to eLua, but it's
-especially important since the platform interface might give the
-impression that it offers an uniform functionality over all platforms,
-when in fact the only thing in common is often just the interface
-itself (that is, the methods and variables you can access in a given
-module). eLua tries to help here by giving you an error when you try to
-access a physical resource that is not available (for example a timer,
-a PWM channel, or a PIO pin/port), but it doesn't try to cover all the
-possible platform-related issues, since this would increase the code
-size and complexity too much. These are some caveats that come to mind
-(note that these are only a few examples, the complete list is much
-longer):</p>
+<a name="luaversions" /><h2>What's the deal with floating-point Lua and integer only Lua?</h2>
+<p>Lua is build around a number type. Every number in Lua will have this type. By default, this number type is a double. This means that even if your
+ program only does integer operations, they will still be treated as doubles. On embedded platforms this is a problem, since the floating point
+ operations are generally emulated in software, thus they are very slow. This is why <b>eLua</b> gives you "integer only Lua": a Lua with the default
+ number type changed to long. The advantages are increased speed and smaller code size (since we can force Newlib to "cut" the floating point code from
+ printf/scanf and friends, which has quite a strong impact on the code size) and increased speed. The downside is that you'll loose the ability to do
+ any floating point operations (although a separate module that will partially overcome this limitation will be provided in the future).</p>
+<a name="windows" /><h2>All your tutorials give instructions on how to compile eLua under Linux, yet you seem to use a lot of Windows tools. How come?</h2>
+<p>It's true that we do all the <b>eLua</b> development under Linux, since we find Linux an environment much more suited for development. At the same
+ time it's true that most of the tools that come with my development boards run under Windows. So we choose to use the best of both world: Bogdan runs
+ Linux under a <a href="http://www.virtualbox.org">VirtualBox</a> emulator, and does verything else under Windows. Dado does everything on
+ Linux and runs Windows under <a href="http://www.vmware.com">VMWare</a>. Both options are nice if you master your environment. To make
+ everything even more flexible, Bogdan keeps his VirtualBox Ubuntu image on an external WD passport disk that he can carry with him wherever he goes,
+ so he can work on eLua whenever he has a bit of spare time :)</p>
-<ul><li>timers: from all the platforms on which eLua runs, only
-the Luminary Cortex CPUs has rock solid 32-bit timers. You can do
-pretty much everything you need with them. All the other platforms have
-16-bit timers, which imposes some limits on the range of delays you can
-achieve with them. Make sure to use tmr.mindelay(id) and
-tmr.maxdelay(id) to check the actual resolution of your timers, and
-adapt your code accordingly. To 'compensate' for this, it's not
-possible to change the base timer frequency on the Cortex CPUs, but it
-is possible on most other platforms :) So be sure to also check the
-result of tmr.setclock(id)</li><li>also, when using timers,
-remember that if you're using XMODEM and/or the "term" module, TMR0 is
-used by both of them. So, if you change the TMR0 base clock in your
-code, be sure to restore the original setting before returning to the
-shell. You can change this static timer assignment by modifying
-src/main.c. It might also be possible to change it dynamically in the
-future, although I see little use for this.</li><li>PWM: the
-Cortex CPUs have 6 PWM channels, but channels 0/1, 2/3 and 4/5
-respectively share the same base clock setting. So, when you're
-changing the base clock for channel 1, you're also changing the base
-clock for channel 0; if channel 0 was already running, you won't like
-what will happen next. This time no eLua function can save you, you
-simply need you know your CPU architecture.</li><li>GPIO: only
-some platform have internal pullups for the GPIO pins, while Cortex is
-the only platform that also provides pulldowns for its GPIOs. However,
-in this case you're safe, as eLua will signal an error if you try to
-execute a pullup operatin on a platform that does not support it.</li></ul>
+<a name="cygwin" /><h2>Will you ever post instructions about how to compile toolchains under Cygwin in Windows?</h2>
+<p>Bogdan: If I ever have way too much spare time on my hands, yes. Otherwise, no. There are many reasons for this. As I already mentioned, I favour Linux
+ over Windows when it comes to developing applications. Also, I noticed that the GNU based toolchains are noticeable slower on Cygwin than on Linux, so
+ experimenting with them can prove frustrating. Also, compiling under Linux and Cygwin should be quite similar,so try starting from my Linux based
+ tutorials, they might work as well on Cygwin.</p>
-<p>The lesson here is clear: understand your platform first!</p><p></p>
+<a name="bytecode" /><h2>I know that Lua can be compiled to bytecode, so I compiled one of the eLua examples with luac and tried to run it on my eLua
+ board, but it didn't work. Is this a bug in eLua?</h2>
+<p>This is not a bug in <b>eLua</b>, it's a bit more subtle than that. See <a href="using.html#cross">the cross-compile section</a> for a full discussion
+ about this problem and its fix.</p>
+<a name="outofmemory" /><h2>I get "out of memory" errors when I run my Lua programs, what should I do?</h2>
+<p>There are a number of things you can try to overcome this:</p>
+<ul>
+ <li><b>enable the LTR patch</b>: you can get very significant improvements if you enable the LTR patch in your <b>eLua</b> image. See
+ <a href="arch_ltr.html">here</a> for more details about LTR, and <a href="building.html">here</a> for instructions about enabling LTR.</li>
+ <li><b>precompile your source to bytecode</b>: if you use bytecode instead of source code Lua won't need to compile your source, so you save some RAM.</li>
+ <li><b>try to avoid using too many strings</b>: strings are immutable in Lua. That means that a statement like <i>s = s .. "\n"</i> (where s is a string)
+ will create a new string each time it's called. If this happens a lot (for example in a loop), your memory will quickly run out because of all the
+ strings. If you really need to do frequent string operations, put them in a table and then use
+ <a href="http://www.lua.org/manual/5.1/manual.html#5.5">table.concat</a> to make a string from your table.</li>
+ <li><b>control Lua's garbage collection manually</b>: if you're still running out of memory, try calling <i>collectgarbage('collect')</i> from your code,
+ which will force a garbage collection and thus might free some memory.</li>
+</ul>
-<p><a name="luaversions"></a>
-<strong>Q: What's the deal with floating-point Lua and integer only Lua?</strong></p>
+<a name="rotables" /><h2>I enabled the LTR patch, but now all my module tables (math, io, string, spi and so on) are read only. Do I have to
+ disable LTR if I want write access to these modules?</h2>
+<p>You don't really have to disable LTR to get write access to your rotables, you can use some simple Lua "tricks" instead. Let's suppose that you need
+ write access to the <b>math</b> module. With LTR enabled, <b>math</b> is a rotable, so you can't change its keys/values. But you can use metatables
+ to overcome this limitation:</p>
+<pre><code>local oldmath = math
+math = { __index = oldmath }
+setmetatable( math, math )
+</code></pre>
+<p>This way you can use <i>math</i> in "write mode" now (since it is a regular table), but you can still access the keys from the original <i>math</i>
+ rotable. Of course, if you need write access to <b>all</b> your modules (or to most of them) it makes more sense to disable LTR instead, but from our
+ observations this doesn't happen in practice.</p>
+$$FOOTER$$
-<p>A: Lua is build around a number type. Every number in Lua will have
-this type. By default, this number type is a double. This means that
-even if your program only does integer operations, they will still be
-treated as doubles. On embedded platforms this is a problem, since the
-floating point operations are generally emulated in software, thus they
-are very slow. This is why eLua gives you "integer only Lua": a Lua
-with the default number type changed to long. The advantages are
-increased speed and smaller code size (since we can force Newlib to
-"cut" the floating point code from printf/scanf and friends, which has
-quite a strong impact on the code size) and increased speed. The
-downside is that you'll loose the ability to do any floating point
-operations.</p><p></p>
-
-
-<p><a name="windows"></a>
-<strong>Q: All your tutorials give instructions on how to compile eLua
-under Linux, yet you seem to use a lot of Windows tools. How come?</strong></p>
-
-<p>A: It's true that we do all the eLua development under Linux, since we
-find Linux an environment much more suited for development. At the same
-time it's true that most of the tools that come with my development
-boards run under Windows. So we choose to use the best of both world: Bogdan runs Linux under an Virtual Machine Manager (<a target="_top" href="http://www.virtualbox.org/">VirtualBox</a>) and do everything else under Windows. Dado does everything on Linux and runs Windows under <a href="http://www.vmware.com" target="_top">VMWare</a>. Both options are nice if you master your environment. To make everything even more flexible, Bogdan keeps his
-VirtualBox Ubuntu image on an external WD passport disk that he can
-carry with him wherever he goes, so he can work on eLua whenever he has a
-bit of spare time :)</p><p></p>
-
-
-<p><a name="cygwin"></a>
-<strong>Q: Will you ever post instructions about how to compile toolchains under Cygwin in Windows?</strong></p>
-
-<p>A: Bogdan: If I ever have way too much spare time on my hands, yes.
-Otherwise, no. There are many reasons for this. As I already mentioned,
-I favour Linux over Windows when it comes to developing applications.
-Also, I noticed that the GNU based toolchains are noticeable slower on
-Cygwin than on Linux, so experimenting with them can prove frustrating.
-Also, compiling under Linux and Cygwin should be quite similar, so try
-starting from my Linux based tutorials, they might work as well on
-Cygwin.</p><p></p>
-
-
-<p><a name="bytecode"></a>
-<strong>Q: I know that Lua can be compiled to bytecode, so I compiled
-one of the eLua examples with luac and tried to run it on my eLua
-board, but it didn't work. Is this a bug in eLua?</strong></p>
-
-<p>A: This is not a bug in eLua, it's a bit more subtle than that. It's
-true that ARM and i386 are very similar when it comes to data types:
-all the fundamental data types have the same length, and they are both
-little endian. So, in theory, if you compile a Lua source file on PC
-you should be able to run the compiled bytecode on your eLua board
-without any modifications. But there's a problem here: the default
-double precision floating point representation is different on ARM and
-PC. So, while the two data types have the same endianess and size, they
-are represented differently in memory. This means that you can't use
-the "regular" luac compiler for this task. However, starting with
-version 0.5, you can cross-compile Lua code on PC to run on target. </p><p></p>
-
-
-<p><a name="outofmemory"></a>
-<strong>Q: I get "out of memory" errors when I run my Lua programs, what should I do?</strong></p>
-
-<p>A: There are a number of things you can try to overcome this:</p>
-
-<ul><li>precompile your source to bytecode: If you use bytecode instead of
-source code Lua won't need to compile your source, so you save some RAM.</li><li>try
-to avoid using too many strings: strings are immutable in Lua. That
-means that a statement like s = s .. "\n" (where s is a string) will
-create a new string each time it's called. If this happens a lot (for
-example in a loop), your memory will quickly run out because of all the
-strings. If you really need to do frequent string operations, put them
-in a table and then use <a href="http://www.lua.org/manual/5.1/manual.html#5.5">table.concat</a> to make a string from your table.</li><li>controll Lua's garbage collection manually: if you're still running out of memory, try
-calling collectgarbage('collect') from your code, which will force a
-garbage collection and thus might free some memory.</li></ul><br><br></body></html>
\ No newline at end of file
Added: branches/eagle_mmc/doc/pt/forum.html
===================================================================
--- branches/eagle_mmc/doc/pt/forum.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/pt/forum.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,5 @@
+$$HEADER$$
+<a id="nabblelink" href="http://n2.nabble.com/eLua-Development-f2368040.html">eLua Development</a>
+<script src="http://n2.nabble.com/embed/f2368040"></script>
+$$FOOTER$$
+
Modified: branches/eagle_mmc/doc/pt/genericmodules.html
===================================================================
--- branches/eagle_mmc/doc/pt/genericmodules.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/pt/genericmodules.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,11 +1,6 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
-
-<link rel="stylesheet" type="text/css" href="../style.css">
</head>
-<body style="background-color: rgb(255, 255, 255);">
<h3><a name="over"></a>eLua Generic Modules</h3>
<br>
<br>
Modified: branches/eagle_mmc/doc/pt/gpio_ref.html
===================================================================
--- branches/eagle_mmc/doc/pt/gpio_ref.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/pt/gpio_ref.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,11 +1,6 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Produto</title>
-
-<link rel="stylesheet" type="text/css" href="../style.css">
</head>
-<body style="background-color: rgb(255, 255, 255);">
<h3><a name="over">gpio</a></h3>
<p class="MsoNormal" style="font-family: Verdana;">
<b>[gpio] pio</b><br>
@@ -139,16 +134,4 @@
</p>
<p class="MsoNormal" style="font-family: Verdana;">
[gpio.configpin(gpio.PULL, gpio.PULL_NO, [Pin1], [Pin2], ...)]
-pio.nopull( Pin1, Pin2, ... ): desabilita "internal pullups/pulldowns" para os pinos
-especificados na lista. É importante observar que algumas CPUs podem não ter este recurso disponível.
-</p>
-<br>
-<br>
-Qual a real vantagem/razão de usarmos uma "lista" de pinos
-em algumas dessas funções ? Como não podemos criar
-uma tabela com eles, não existe realmente vantagem em usá-la,
-já que não podemos criar a lista em tempo de execução e algumas
-outras funções propostas resolvem o problema de evitar mais de uma chamada para vários pinos.<br>
-A: É útil e as vezes necessária, logo continuará.....<br>
-<br>
-</body></html>
+pio.nopull( Pin1, Pin2, ... ): d
\ No newline at end of file
Added: branches/eagle_mmc/doc/pt/installing.html
===================================================================
--- branches/eagle_mmc/doc/pt/installing.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/pt/installing.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,11 @@
+$$HEADER$$
+<h3>Instalando eLua</h3>
+<p>Para utilizar eLua em sua plataforma preferida, será preciso "instalar" no seu dispositivo/kit ou, mais precisamente, gravar a
+imagem de <b>eLua</b> na memória Flash. Nesta seção apresentamos instruções especÃficas para a instalação em todas as plataformas por <b>eLua</b>.
+Certifique-se que você já possui uma imagem de <b>eLua</b> gerada para funcionar no seu hardware (tanto <a href="downloads.html">baixando uma
+já pronta</a> ou <a href="building.html">gerando você mesmo</a>), então escolha a plataforma que lhe interessa a partir das
+opções menu "Instalando" aqui ao lado.</p>
+<p>Para obter o arquivo binário necessário no formato necessário para a
+programação de sua CPU durante a geraçãoo de <b>eLua</b>, lembre-se de especificar o
+parâmetro "prog" na linha do comando do scons.</p>
+$$FOOTER$$
Added: branches/eagle_mmc/doc/pt/installing_at91sam7x.html
===================================================================
--- branches/eagle_mmc/doc/pt/installing_at91sam7x.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/pt/installing_at91sam7x.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,48 @@
+$$HEADER$$
+<h3>Usando <b>eLua</b> com as CPUs AT91SAM7X da Atmel</h3>
+
+<p>A <a href="http://www.atmel.com">Atmel</a> é uma empresa que não precisa de nenhum tipo de apresentação:)
+Sua enorme variedade de produtos, inclui algumas implementações do núcleo do ARM7TDMI.
+Entre elas estão as CPUs <a href="http://www.atmel.com/dyn/products/Product_card.asp?part_id=3755">AT91SAM7X256</a>
+e <a href="http://www.atmel.com/dyn/products/Product_card.asp?part_id=4104">AT91SAM7X512</a>.
+A única diferença entre elas é a quantidade de memória interna (256k Flash RAM + 64k para a AT91SAM7X256 e 512k Flash RAM + 128k para a AT91SAM7X512).
+Com muitos periféricos e acompanhada por um aplicativo de apoio ao
+desenvolvimento, elas oferecem um ótimo hardware para <b>eLua</b>.
+Para este tutorial, vamos usar a placa de desenvolvimento <a href="http://www.olimex.com/dev/sam7-ex256.html">SAM7-EX256</a>
+da <a href="http://www.olimex.com">Olimex</a>.
+Em nossa opinião, está é realmente uma boa placa, com um preço razoável, mas que carece de um pacote de documentação
+adequada.
+É equipada com uma CPU AT91SAM7X256. Gostariamos de colocar as mãos numa placa com a CPU
+AT91SAM7X512 mas, como não produziram uma ainda, vamos ficar com a AT91SAM7X256
+por enquanto :)
+Certamente você ainda poderá usar este tutorial com uma placa diferente da AT91SAM7X256.
+Além disso, as instruções devem ser bastante semelhantes para CPUs AT91SAM7X512.</p>
+ <h3>Pré-requisitos</h3>
+ <p>Antes de você usar <b>eLua</b> com a CPU AT91SAM7X256, certifique-se que:</p>
+ <ul>
+ <li>esteja usando Linux ou Windows. Na realidade não é um pré-requisito, só faz com que a vida fique mais fácil. Já que a CPU é suportada pelo aplicativo <a href="http://openocd.berlios.de/web/">OpenOCD</a>, programá-la com o Linux é perfeitamente possÃvel, já que o OpenOCD roda tanto no Windows quanto no Linux. No entanto, devido a restrições de algumas das minhas placas de desenvolvimento, aproveito a situação e fico com a ferramenta de programação da Atmel, ao invés do OpenOCD. A vantagem é que você não precisa de um JTAG "dongle" para programar sua placa (que seria o caso se você estivesse usando o OpenOCD). A desvantagem, claro, é que a ferramenta Atmel é executada apenas no Windows. Além disso, eu pessoalmente acho o OpenOCD tedioso. Mesmo assim, se você ainda quiser usá-lo, veja a <a href="http://www.olimex.com/dev/sam7-ex256.html">página da Olimex</a>, existem alguns links relacionados ao OpenOCD. Dito isto, a partir de agora assumo que !
você está usando o Windows. Uso o XP, o Vista deve funcionar também.</li>
+ <li>o aplicativo <a href="http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3883">AT91 In-system Programmer (ISP)</a> da Atmel.</li>
+ <li>você já tem sua imagem de <b>eLua</b> para a CPU AT91SAM7X256 CPU (<a href="building.html">gerada</a> ou <a href="downloads.html">baixada</a>).</li>
+ </ul>
+ <h3>Programando eLua na placa SAM7-EX256</h3>
+<p>Isto envolve alguns truques com jumpers, mas ainda assim, é muito fácil de fazer. Usaremos quatro jumpers: o jumper "USB/EXT" (localizado à direita do conector USB na parte inferior esquerda da placa), o jumper "ERASE" (localizado no lado direito do conector "cabeçalho Uext" na parte superior esquerda da mesa, em frente a quartzo), e uma dupla de jumpers "RS232" (localizados ao lado do conector Ethernet em seu lado direito, e <b>NÃO</b> a um chamado "CAN", que está mais próximo da borda direita da placa).</p>
+ <ul>
+ <li>Ligue sua placa a um PC usando um cabo USB.</li>
+ <li>Se você tem um programa de emulação de terminal conectado à placa, feche-o (ou, pelo menos, desconecte-o da porta).</li>
+ <li>Certifique-se que o conjumto de dois jumpers mencionados antes estão configurados nas posições "RXD0" e "TXD0", respectivamente, não "DRXD" e "DTXD".</li>
+ <li>Certifique-se que o conector "USB/EXT" esteja configurado como "USB" (posição 1-2) e que o jumper "ERASE" está desconectado.</li>
+ <li>Ligue o jumper "ERASE" e esperar um segundo ou mais.</li>
+ <li>Desligue o jumper "USB/EXT" completamente, em seguida, desligue o jumper "ERASE" também.</li>
+ <li>Ligue o jumper "USB/EXT" novamente na posição "USB" (1-2).</li>
+ <li>Inicie a aplicação da Atmel. Caso, você não tinha instalado a sua placa ainda, você será solicitado a fazê-lo neste momento.</li>
+ <li>Selecione "\usb\ARMx", como sua conexão (para mim é \usb\ARM0) e "AT91SAM7X256-EK", como a placa.</li>
+ <li>Selecione a guia "Flash" do meio da janela.</li>
+ <li>No campo "Send File Name" selecione o arquivo binário de <b>eLua</b> (.bin), que você gerou a partir da compilação e clique no botão "Send File".</li>
+ <li>Aguarde o arquivo ser enviado e responda "No" para a solicitação de "Lock region(s)".</li>
+ <li>Abaixo de ("Scripts"), selecione o "Boot from Flash (GPNVM2)" e pressione "Execute".</li>
+ <li>Saia da aplicação.</li>
+ </ul>
+ <p>Pronto! Um pouco complicado, mas <b>eLua</b> está agora programada na
+ CPU. Agora você pode iniciar o seu emulador de terminal e se divertir, conforme descrito em <a href="using.html">usandp eLua</a>.</p>
+$$FOOTER$$
+
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+$$HEADER$$
+<h3>Instalando <b>eLua</b> nas CPUs AVR32 CPUs da Atmel</h3>
+<p><a href="http://www.atmel.com/products/AVR32/">AVR32</a> é uma famÃlia de CPUs de 32 bits de alta performance da <a href="http://www.atmel.com">Atmel</a>. Foram construÃdas visando a concorrência direta no mercado com a implementação da ARM, e oferece uma performance muito boa (91 MIPS com 66MHz) e fonte de energia eficiente (1.3mW/MHz). A Atmel alega que o seu núcleo AVR32 supera o ARMv5 (tanto em modo ARM como em Thumb) em termos de desempenho e tamanho do código. É uma arquitetura proprietária (só implementada pela Atmel), mas tem um pacote de software de apoio muito bom, e um conjunto de ferramentas de código aberto baseado em GCC, o que a faz ser uma candidata ideal para se usar eLua com uma CPU não-ARM. Atmel vende também várias placas de desenvolvimento com base em suas CPUs AVR23. A utilizada para eLua é a placa <a href="http://www.atmel.com/dyn/Products/tools_card.asp?tool_id=4114">ATEVK1100</a>, construÃda em torno do <a href="http://www.atmel.!
com/dyn/products/product_card.asp?part_id=4117">MCU AT32UC3A0512 AVR32</a> (512k Flash interno/64k RAM interno). É uma placa muito poderosa, com (entre outras coisas) 32 MBytes de memória SDRAM externa, o que é mais do que suficiente para rodar qualquer programa <b>eLua</b> que eu possa imaginar:).</p>
+
+
+<h3>Pré-requisitos</h3>
+ <p>Antes de você usar <b>eLua</b> com a CPU AT32UC3A0512, certifique-se que:</p>
+ <ul>
+ <li>usando Linux ou Windows. É mais fácil instalar e usar o software de programação da Atmel no Windows, portanto use o Windows caso você não queira ter muitas dificuldades durante a instalação.</li>
+ <li>o programa <a href="http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3886">FLIP da Atmel</a> instalado, é exatamente o que você precisa para instalar seu arquivo de imagem de <b>eLua</b>. De fácil instalação no Windows (é só executar o pacote de instalação), mas bastante complicado no Linux.
+ No parágrafo abaixo, segue uma descrição dos procedimentos para instalação do FLIP em Linux..</li>
+ <li>Você já tem sua imagem de <b>eLua</b> para a CPU AT32UC3A0512 (<a href="building.html">gerada</a> ou <a href="downloads.html">baixada</a>). Note que ao contrário das outras plataformas, o ATEVK1100 precisa de um arquivo .hex para a programação, e não um .bin.</li>
+ </ul>
+
+<h2>Instalando FLIP no Linux Ubuntu</h2>
+<p>Siga os passos abaixo para instalar o FLIP no Linux:</p>
+<ol>
+ <li>baixe a versão do FLIP para Linux da <a href="http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3886">página da Atmel</a>. Salve-o (ou mova-o depois) para a pasta <i>/usr/local/</i> (para isso é necessário privilégios de superusuário). No momento da elaboração deste tutorial, a última versão do FLIP é a 3.2.1, portanto vamos utilizar aqui esta versão.</li>
+ <li>descompacte o arquivo FLIP:
+ <pre><code>$ cd /usr/local
+$ sudo tar xvzf flip_linux_3-2-1.tgz</code></pre>
+ Isto criará o diretório <i>/usr/local/flip.3.2.1</i>.</li>
+ <li>é necessário instalar o OpenJDK caso ele não esteja instalado:
+ <pre><code>$ sudo apt-get install openjdk-6-jre</code></pre>
+ </li>
+ <li>edite <i>/usr/local/flip.3.2.1/bin/batchisp3.sh</i> e inclua as duas linhas em negrito no inicio do arquivo:
+ <pre><code>#!/bin/bash -f
+
+<b>export JAVA_HOME=/usr/lib/jvm/java-6-openjdk/jre/
+export FLIP_HOME=/usr/local/flip.3.2.1/bin/</b>
+
+if [ "$FLIP_HOME" = "" ]; then</code></pre>
+ </li>
+ <li>edite o arquivo binário <i>/usr/local/flip.3.2.1/libatlibusbdfu.so</i>. Isto é necessário, porque o programa FLIP vem compilado para o RedHat por default, e o Ubuntu possui algumas arquivos de sua instalação localizados em diretórios diferentes . Veja <a href="http://www.avrfreaks.net/index.php?name=PNphpBB2&file=viewtopic&t=56562">este tópico</a> para mais detalhes. Tudo que você tem a fazer, é alterar todas as referências do string <b>/sys/bus/usb</b> contidas no arquivo <i>libatlibusbdfu.so</i> para <b>/dev/bus/usb</b>.</li>
+ <li>inclua o diretório FLIP no seu PATH:
+ <pre><code>$ export PATH=/usr/local/flip.3.2.1/bin:$PATH</code></pre>
+ </li>
+ <li>FLIP interfere com um programa que vem pré-instalado no sistema Ubuntu, chamado <b>brltty</b>. Este programa é destinado a ajudar os deficientes visuais, por isso, se você não for um deles, basta removê-lo (como parece também interferir com uma série de outros dispositivos USB):
+
+ <pre><code>$ sudo apt-get remove brltty</code></pre>
+ </li>
+</ol>
+
+ <h3>Gravando <b>eLua</b> na placa EVK1100</h3>
+<p>Após a instalação do FLIP e de tê-lo incluÃdo no seu PATH, gravar o arquivo imagem de <b>eLua</b> deve ser bem fácil:</p>
+<ul>
+ <li>conecte sua placa ATEVK1100 a um PC usando um cabo USB</li>
+ <li>coloque a placa no modo DFU (isto é necessário para a utilização do FLIP). Para fazer isso:
+ <ol>
+ <li>pressione o botão <b>on</b> do joystick (e mantenha-o pressionado)</li>
+ <li>pressione o botão RESET da placa rapidamente</li>
+ <li>solte o botão RESET</li>
+ <li>solte o joystick</li>
+ </ol>
+ </li>
+ <li>Se você estiver usando o Windows e este lhe pedir um driver, você deve instalá-lo manualmente a partir de <i>c:\Program Files\Atmel\Flip<version>\usb\</i></li>
+ <li>chame o programa FLIP pela linha de comando (o comando é o mesmo no Windows e no Linux, com uma única exceção:, o nome do executável é FLIP <b>batchisp3</b> em Linux e <b>batchisp</b> (sem a 3) no Windows) abaixo:
+ <pre><code>$ batchisp3 -hardware usb -device at32uc3a0512 -operation erase f memory flash blankcheck
+ loadbuffer <image name>.hex program verify start reset 0</code></pre></li>
+</ul>
+<p>Terminou, o arquivo imagem de <b>eLua</b> está finalmente instalado na sua placa ATEVK1100.</p>
+$$FOOTER$$
+
Added: branches/eagle_mmc/doc/pt/installing_i386.html
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+$$HEADER$$
+<h3>Usando eLua com as CPUs Intel i386 (ou mais recentes)</h3>
+ <p>Como a plataforma i386 foi implementada somente como uma prova de conceito, as únicas coisas que você pode fazer com ela são:</p>
+ <ul>
+ <li><a href="tut_bootpc.html">Inicializar seu PC com eLua</a></li>
+ <li><a href="tut_bootstick.html">Inicializar eLua de um pendrive</a></li>
+ </ul>
+ <p>Se você quiser fazer isso, <a href="building.html">construa sua imagem de eLua</a> ou faça o download de uma imagem pré-compilada, como explicado na <a href="downloads.html">página de download</a>.</p>
+ <p>No entanto, a maioria dos recursos que você encontraria em uma plataforma embutida não funciona aqui.
+Você não será capaz de carregar programas para o seu hardware <b>eLua</b> i386 usando o protocolo XMODEM (não porque é impossÃvel, mas simplesmente porque isso não faz sentido algum em um PC). Além disso, você não será capaz de controlar os periféricos que normalmente encontram-se embutidos em uma CPU (SPI, I2C, PIO e todos os outros), porque eles não estão presentes na plataforma i386 (que podem ser emulados através de diferentes meios, mas este é um assunto que vai além do escopo de <b>eLua</b>). Assim, até novo aviso, i386 será nada mais do que uma plataforma de demonstração para <b>eLua</b>. Se você acha que pode fazer algo além disso, não hesite em contactar-nos. Estou realmente muito interessado nisso, mas me faltam recursos necessários para dar continuidade.</p>
+$$FOOTER$$
+
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--- branches/eagle_mmc/doc/pt/installing_lm3s.html 2009-11-06 02:08:17 UTC (rev 525)
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+$$HEADER$$
+<h3>Usando <b>eLua</b> com as CPUs LM3S (Cortex-M3) da Luminary Micro</h3>
+ <p><a href="http://www.luminarymicro.com">Luminary Micro</a> é a empresa que produziu a primeira implementação de silicone do mundo para o processador Cortex-M3. A relação de produtos da Luminary é bastante variada, que vão desde dispositivos relativamente simples até CPUs com recursos completos (com on-chip USB, EMAC, CAN, e muitos outros periféricos). O software que acompanha estes dispositivos também é muito bom, com drivers para todos os periféricos da CPU e aplicativos de terceiros. A algum tempo atrás, entramos em contato com a Luminary Micro, solicitando um apoio a este projeto através de um de seus kits de avaliação, a resposta foi excelente (obrigado mais uma vêz, Luminary!). Foi assim que uma <a href="http://www.luminarymicro.com/products/lm3s8962_can_ethernet_evaluation_kit.html">EKx-LM3S8962K</a> veio parar na minha mesa. Esta é a placa de desenvolvimento que eu vou usar neste tutorial. <b>eLua</b> também suporta a placa <a href="http://www.l!
uminarymicro.com/products/ekk-lm3s6965_ethernet_evaluation_kit.html">EKx-LM3S6965</a> da Luminary (que pode ser programada exatamente como a EKX-LM3S8962) e a placa <a href="http://www.micromint.com/index.php/SBC/eagle-100.html">Eagle 100</a> da <a href="http://www.micromint.com">Micromint</a>, que usa um procedimento de instalação diferente.
+</p>
+ <h3>Pré-requisitos</h3>
+ <p>Antes de começar a utilizar <b>eLua</b> com a CPU LM3S, certifique-se de que:</p>
+ <ul>
+ <li>você está usando Windows. Isso mesmo, eu disse <b>Windows</b>. O motivo é bastante simples: vamos utilizar as ferramentas da Luminary para gravar <b>eLua</b> na placa, e estas são especÃficas para Windows. Este é o caso de muitas CPUs e fabricantes que existem por aÃ. Pode-se ter o Windows instalado no seu disco rÃgido, ou debaixo de emulador no Linux, não importa, caso você esteja bastante irritado, pode-se rodá-lo também a partir do <a href="http://www.winehq.org/">Wine</a>. Uso o XP, Vista deve funcionar também.</li>
+ <li>você instalou o programa LM Flash Programmer da Luminary. Procure-o <a href="http://www.luminarymicro.com/products/ekk-lm3s8962_can_ethernet_evaluation_kit.html">nesta página</a>, por exemplo (o link está na guia "Software Updates").</li>
+ <li>você já tem a imagem de <b>eLua</b> para a CPU LM3S8962 (<a href="building.html">gerada</a> ou <a href="downloads.html">baixada</a>).</li>
+ </ul>
+ <h3>Instalando <b>eLua</b> nas CPUs EKx-LM3S8962EK e EKx-LM3S6965</h3>
+ <p>Felizmente, esta instalação está mais fácil do que nunca. Uma das coisas agradáveis sobre esses dois kits é que eles usam a porta USB on-board, tanto para baixar o firmware quanto para emular uma porta serial (através de um conversor USB/UART, sendo assim, você não precisa de nenhum software especial para a CPU ter acesso a essa porta UART). Além disso, a placa sabe automaticamente como (e quando) alternar entre o modo de download do firmware para o modo de emulação UART, assim você não precisa trocar jumpers de lá para cá, ou qualquer coisa assim. O esforço de atualização do firmware é nenhum mesmo. Então, vamos fazê-lo:</p>
+ <ul>
+ <li>conecte sua board no seu PC usando um cabo USB. Caso não tenha instalado ainda os drivers, você será solicitado a fazê-lo neste momento.</li>
+ <li>se você já estiver usando a conexão USB na placa no modo de emulação UART, feche o programa do terminal (ou, pelo menos, desconecte-o da porta USB).</li>
+ <li>inicie a aplicação "Luminary Micro Flash programmer".</li>
+ <li>na guia "Configuração", selecione "LM3S8962 Ethernet and CAN Evaluation board" ou "LM3S6965 Ethernet Evaluation Board" (dependendo da placa).</li>
+ <li>na guia "Programa", selecione o arquivo <b>eLua</b>.bin que você gerou na etapa de compilação.</li>
+ <li>selecione as "opções" da maneira que achar melhor (geralmente escolho "Erase entire flash" e "Reset MCU after program").</li>
+ <li>pressione o botão "Program".</li>
+ <li>espere até que a gravação tenha terminado, em seguida, saia do aplicativo.</li>
+ </ul>
+<p>Vale a pena mencionar que uma vez que essas placas vem com um conversor USB JTAG, deve ser possÃvel usar o OpenOCD (ou um pacote similar) em vez do programa da Luminary para gravar a imagem de <b>eLua</b>. Os fóruns da Luminary Micro são um bom lugar para procurar informações, se você está explorando a opção OpenOCD.</p>
+<h3>Instalando eLua na Eagle 100</h3>
+<p>A placa Eagle 100 também pode ser programada via JTAG, mas não inclui um adaptador USB para JTAG onboard, assim você precisará de um adaptador externo, se você pretende utilizar JTAG para programação. Felizmente, ele também vem com um carregador Ethernet, assim você pode carregar a sua imagem através da Ethernet. O único requisito para utilizar o bootloader é para iniciar a sua imagem no endereço 0x2000 em vez do 0x0 de costume, já que é onde ficam os jumpers do bootloader. O <a href="building.html">sistema de geração do eLua</a> faz isso automaticamente se a placa "= eagle-100" parâmetro é dado em tempo de compilação. Para uma descrição completa do bootloader Ethernet consulte o <a href="http://www.micromint.com/index.php/Download-document/32-Eagle-100-User-s-Manual.html">manual da placa Eagle 100</a> (procure pela seção 2.7, <b>atualizações do firmware usando o gerenciador de inicialização Ethernet</b>).<br>
+Você ainda precisa do programa Flash LM para usar o bootloader Ethernet, mas desde que a placa pode utilizar JTAG para fazer upload do firmware, deve ser possÃvel usá-lo com OpenOCD (ou com um pacote similar) e um adaptador USB externo JTAG. Os fóruns da Luminary Micro são um bom lugar para procurar informações, se você está explorando a opção OpenOCD.</p>
+$$FOOTER$$
+
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+$$HEADER$$
+<h3>Instalando <b>eLua</b> com o processador LPC2888 da NXP</h3>
+<p>O processador <a href="http://www.standardics.nxp.com/products/lpc2000/all/~LPC2888/">LPC2888</a> da <a href="http://www.nxp.com">NXP</a>
+possui algumas caracterÃsticas interessantes: uma enorme memória flash interna de 1Mbyte, USB 2.0 on-chip de alta velocidade
+e o mais complexo (de longe) clock de rede que já vimos em um chip ATM7TDMI.
+Além disso, implementa o USB DFU (Device Firmware Update) através de sua interface USB
+e por isso fica bastante fácil de programá-lo direto no hardware. Estamos usando a placa de desenvolvimento
+<a href="http://www.olimex.com/dev/lpc-h2888.html">Olimex LPC-H2888</a> baseada nesse
+processador, que vem com 32M Bytes de SDRAM externo e também 2M Bytes de flash externo,
+o que é mais que suficiente para nossas necessidades.
+No entanto, existem algumas desvantagens. Para começar, seu aplicativo de suporte (da Panasonic) é muito
+fraco, quando comparado a outros concorrentes que aceitam <b>eLua</b>.
+Não possui nem mesmo todos os drivers, somente uns poucos e bastante imcompletos. O esquema do processador poderia ser mais detalhado,
+especialmente quando se refere a clock (que é bastante complicado). Em nossa placa, a atualização do firmware via USB (DFU download mode)
+parou de funcionar de repente, sem qualquer razão aparente e não conseguimos
+mais usar a DFU no chip, desde então, tivemos que recorrer ao uso do OpenOCD (e preparar um arquivo de configuração, já que era impossÃvel encontrar um para LPC2888).
+A CPU em si tem uma limitação muito interessante: por causa de um erro estrutural é impossÃvel executar código
+Thumb da memória flash on-chip, só é possÃvel executar código ARM comum (?!).
+Além disso, a placa que temos da Olimex ignora completamente o fato de que esse chip é capaz de rodar no modo DFU
+(a placa não inclui nenhum tipo de jumper e/ou switch para habilitar este modo), logo,
+tivemos que construir uma placa complementar. Era algo que já precisaria ser
+feito mesmo, pois a placa também não possui uma interface RS232, que foi
+construÃda baseada no chip MAX232. Depois de tudo isso, concluimos que nossa
+que nossa experiência com este chip (e com a placa Olimex) não foi tão agradável assim mas isso não muda o fato de que o LPC-H2888
+é uma das mais poderosas placas em que <b>eLua</b> pode ser executada.</p>
+ <h3>Pré-requisitos</h3>
+ <p>Antes de utilizar <b>eLua</b> na CPU LPC2888, certifique-se de que:</p>
+ <ul>
+ <li>se você vai usar DFU para a programação do firmware, você precisa do Windows (embora eu tenha ouvido relatos de programas Linux que podem programar o chip no modo DFU, não vou comentá-los aqui). Se você pretende utilizar OpenOCD no Linux, Windows, ou qualquer outro sistema operacional que tem suporte para <a href="http://openocd.berlios.de/web/">OpenOCD</a>, talvez queira dar uma olhada no <a href="tut_openocd.html">tutorial do OpenOCD</a> antes de continuar.</li>
+ <li>se você vai usar DFU, precisará de uma forma de inicializar o chip no modo DFU para atualização do firmware. Isso é feito, puxando para cima o pino P2.3 (ligado ao VCC) na inicialização. Na minha placa, incluà um switch para isso. Pressione o switch, pressione RESET enquanto mantém o switch pressionado, solte o switch. Você chip está agora em modo DFU.</li>
+ <li>Se você estiver usando DFU, instale o utilitário de programação de flash do LPC2888, que pode ser encontrado <a href="http://www.standardics.nxp.com/support/documents/microcontrollers/zip/flash.utility.mass.dfu.lpc2888.zip">aqui</a> (o pacote contém os drivers DFU para Windows).</li>
+ <li>se você estiver usando OpenOCD, siga as instruções do meu tutorial OpenOCD.</li>
+ <li>você já tem o arquivo com a imagem <b>eLua</b> para a CPU LPC2888 (<a href="building.html">gerada</a> or <a href="downloads.html">baixada</a>)..</li>
+ </ul>
+ <h3>Gravando <b>eLua</b> no LPC2888 usando a ferramenta DFU da NXP</h3>
+ <p>O software DFU para gravação em memória Flash não trabalha diretamente nos arquivos binários que você obteve após ter gerado <b>eLua</b>, é preciso executá-los através do programa "hostcrypt" da NXP (que faz parte do pacote LPC2888 DFU). Depois de já ter gerado o seu arquivo binário de <b>eLua</b>, execute os seguintes comandos a partir do prompt do Windows (certifique-se que hostcryptv2.exe está definido no path):</p>
+<div class="code"><pre>C:> hostcryptv2 elua_lua_lpc2888.bin elua.ebn -K0 -F0</pre></div>
+<p>Como resultado, você terá um novo arquivo (<i>elua.ebn</i>). Agora, inicialize seu chip no modo DFU (veja acima) e use o utilitário DFU (<i>MassDFUApplication.exe</i>) para carregar <i>elua.ebn</i> em seu chip (as instruções sobre como usar o MassDFUApplication estão em um arquivo PDF que está incluÃdo no pacote de LPC2888 DFU). Reinicie a placa e divirta-se.</p>
+ <h3>Gravando <b>eLua</b> no LPC2888 usando o OpenOCD</h3>
+<p>Se você tiver tanta sorte quanto nós, e sua placa se recusa a funcionar no modo DFU, siga este <a href="tut_openocd.html">tutorial do OpenOCD</a> para gravar sua imagem usando OpenOCD.</p>
+$$FOOTER$$
+
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+$$HEADER$$
+<h3>Usando <b>eLua</b> com as CPUs STM32 da ST</h3>
+ <p>A <a href="http://www.st.com/mcu/inchtml-pages-stm32.html">famÃlia STM32</a> de MCUs da <a href="http://www.st.com">ST</a> é uma linha de Cortex-M3 baseada em chips com um monte de recursos, incluindo (mas não limitado a) bastante memória Flash/RAM on-chip (até 512k Flash e 64k RAM), controlador de memórias externas incluindo as (P)SRAM, NAND Flash e NOR Flash, ADC e DAC integrados, temporizadores avançados e muitos outros. Eles também possuem um carregador de boot serial integrado (um bootloader), por isso é extremamente fácil de programá-los a partir de um dispositivo que possua uma porta serial. A ST fornece uma ferramenta de suporte que pode ser usada para baixar um programa para o STM32 usando este bootloader, mas só funciona no Windows. O protocolo desse bootloader está documentado em uma nota separada, logo, qualquer um poderá facilmente escrever um aplicativo para qualquer outro sistema operacional.</p>
+ <p><b>eLua</b> funciona atualmente em duas variantes do STM32F103 da famÃlia STM32, especificamente para essas placas:
+ <a href="http://www.st.com/mcu/contentid-100-110-STM3210E_EVAL.html">a STM3210E-EVAL</a> da <a href="http://www.st.com">ST</a> e a
+ <a href="http://www.futurlec.com/ET-STM32_Stamp.shtml">ETM-STM32 stamp</a> da <a href="http://www.futurlec.com">Futurlec</a>. Instruções para a instalação de <b>eLua</b> em cada uma dessas placas é apresentado mais abaixo.</p>
+ <h3>Pré-requisitos</h3>
+ <p>Antes de começar a usar <b>eLua</b> com a CPU STM32F103, certifique-se
+ de que:</p>
+ <ul>
+ <li>você está usando Windows. Como já foi dito antes, o software fornecido pela ST para baixar o firmware via serial funciona apenas no Windows. É provável que já existam ferramentas similares para a utilizaçãp com Linux e outros sistemas operacionais, ou que venham a ficar disponÃveis brevemente.</li>
+ <li>você instalou o "demonstrador Flash loader" <a href="http://www.st.com/mcu/modules.php?name=mcu&file=familiesdocs&FAM=110">
+desta página</a> (procure-o na seção "Software - PC").</li>
+ <li>você já tem o arquivo com a imagem de <b>eLua</b> para a CPU STM32F103 (<a href="building.html">gerado</a> ou <a href="downloads.html">baixado</a>).</li>
+ </ul>
+
+ <h3>Gravando eLua na placa STM3210E-EVAL</h3>
+ <p>##TODO</p>
+ <h3>Gravando eLua na placa ET-STM32 stamp</h3>
+ <p>Siga os passos abaixo para instalar <b>eLua</b> na sua ET-STM32 stamp:</p>
+
+ <ul>
+ <li>conecte a placa em uma das portas seriais de seu computador com um cabo serial fornecido pelo fabricante.</li>
+ <li>na placa, coloque o jumper BOOT1 para a posição ISP (esta configuração já deve vir assim de fábrica e provavelmente não precisará ser alterada).</li>
+ <li>pressione o switch BOOT0. O LED verde "BOOT0=1" deve acender.</li>
+ <li>reinicie a placa pressionando o botão RESET.</li>
+ <li>execute o programa ST Flash Loader. Selecione a sua porta serial na primeira tela, não altere os parâmetros de comunicação (57600 8E1) e pressione "Next" 3 vezes.</li>
+ <li>selecione o "Download to device", escolha o arquivo imagem de <b>eLua</b> e aperte "Next".</li>
+ <li>aguarde até a gravação terminar e então pressiona "Finish".</li>
+ <li>pressione novamente o switch BOOT0.</li>
+ <li>reinicie novamente a placa pressionando o botão RESET.</li>
+ </ul>
+
+ <p>A partir de agora você está com <b>eLua</b> instalada em sua placa, e pode escolher a mesma porta que utilizou para a gravação acima como uma porta comum para seu uso com <b>eLua</b>.</p>
+$$FOOTER$$
+
Added: branches/eagle_mmc/doc/pt/installing_str7.html
===================================================================
--- branches/eagle_mmc/doc/pt/installing_str7.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/pt/installing_str7.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,30 @@
+$$HEADER$$
+<h3>Instalando <b>eLua</b> na famÃlia de CPUs STR7 da ST</h3>
+ <p><a href="http://www.st.com/mcu/inchtml-pages-str7.html">STR7</a> é uma famÃlia de processadores baseados no ATM7TDMI da <a href="http://www.st.com">ST</a>.
+ Eles são pequenos, MCUs de baixa potência, com um conjunto equilibrado de periféricos embutidos no chip.
+ Para este tutorial, estamos usando a placa <a href="http://www.sctec.com.br/content/view/101/30/">MOD711</a> da
+ empresa brasileira <a href="http://www.sctec.com.br">ScTec Automação e
+ Projetos Especiais</a>. A placa está baseada na variante STR711FR2 da famÃlia STR7.
+ Fomos preciso adicionar algumas coisas à este kit:
+ <ul>
+ <li>um conversor MAX3232 RS232 para TTL para a interface serial</li>
+ <li>um par de LEDs</li>
+<li> um botão de reset</li>
+</ul>
+Depois disso, a placa estava pronta para <b>eLua</b>:)</p>
+ <h3>Pré-requisitos</h3>
+ <p>Antes de começar a usar <b>eLua</b> na CPU STR711FR2, certifique-se de que:</p>
+ <ul>
+ <li>você está usando Linux, Windows, ou qualquer outro sistema operacional que tenha suporte para <a href="http://openocd.berlios.de/web/">OpenOCD</a>. Você pode dar uma olhada no
+ nosso <a href="tut_openocd.html">tutorial do OpenOCD</a> antes de continuar.</li>
+ <li>você já tem o seu arquivo com a imagem de <b>eLua</b> para a CPU STR711FR2 (<a href="building.html">gerado</a> ou <a href="downloads.html">baixado</a>).</li>
+ </ul>
+ <h3>Gravando <b>eLua</b> na placa MOD711:</h3>
+ <p>Você precisa do OpenOCD para fazer isso. Basta seguir as instruções do
+ nosso <a href="tut_openocd.html">tutorial OpenOCD</a>. Na página do tutorial, você também encontrará links para os arquivos de configuração do OpenOCD que
+ estamos usando para gravar <b>eLua</b> na placa MOD711.
+ E é isto ! <b>eLua</b> está gravado na CPU. Agora é só iniciar o emulador de terminal e se divertir, conforme descrito em <a href="using.html">using eLua</a>.</p>
+<p><b>NOTA IMPORTANTE:</b> Para esta placa, você precisa configurar a velocidade de sua porta serial para 38400 (ao contrário de 115.200 baud para a
+ maioria das outras placas). Todos os outros parâmetros continuam os mesmos (8 bits de dados, sem paridade, um stop bit).</p>
+$$FOOTER$$
+
Added: branches/eagle_mmc/doc/pt/installing_str9.html
===================================================================
--- branches/eagle_mmc/doc/pt/installing_str9.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/pt/installing_str9.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,35 @@
+$$HEADER$$
+<h3>Instalando <b>eLua</b> na famÃlia de CPUs STR9 da ST</h3>
+ <p>Entre os MCUs baseados em ARM disponÃveis atualmente, as CPUs <a href="http://www.st.com/mcu/inchtml-pages-str9.html">STR9</a> da <a href="http://www.st.com">ST</a> continua em
+ alta, devido à algumas caracterÃsticas únicas.
+ Primeiro, seu núcleo é um ARM966-E e não o popular núcleo ARM7TDMI.
+ Isto, juntamente com alguns blocos de hardware habilmente escolhidos e embutidos no chip, permite que a CPU rode a 96MHz,
+ o que é muito rápido para uma MCU de propósito geral.
+ A CPU que estamos usando (uma STR912FAW44) também tem 512K de flash (e um outro banco de 32K de flash) e 96k de memória RAM
+ interna. Assim você não vai ficar sem memória tão cedo. A placa é acompanhada de uma biblioteca de apoio muito boa e a
+ ST fornece uma série de boas ferramentas para o STR9, incluindo uma ferramenta gráfica que você pode usar para configurar o chip,
+ exatamente como você deseja. GostarÃamos de agradecer especialmente à ST, que nos enviou um
+ <a href="http://www.hitex.com/str9-comstick/">STR9-comStick</a> para rodar <b>eLua</b> nela. Muito obrigado pela ajuda de voces, mais uma vez.
+ Esta é a placa que vamos usar neste tutorial.</p>
+ <h3>Pré-requisitos</h3>
+ <p>Antes de você começar a usar <b>eLua</b> na CPU STR912FAW44, certifique-se
+ de que:</p>
+ <ul>
+ <li>você está usando Linux, Windows, ou qualquer outro sistema operacional que tem suporte para <a href="http://openocd.berlios.de/web/">OpenOCD</a>. Você pode dar uma olhada no meu tutorial <a href="tut_openocd.html">OpenOCD tutorial</a> antes de continuar.</li>
+ <li>se você estiver usando Windows, instalou o pacote de apoio STR9-comStick a partir do CD que acompanha a placa..</li>
+ <li>você já tem o arquivo com a imagem de <b>eLua</b> para a CPU STR912FAW44 (<a href="building.html">gerado</a> ou <a href="downloads.html">baixado</a>).</li>
+ </ul>
+ <h3>Gravando <b>eLua</b> na STR9-comStick:</h3>
+ <p>Você precisa OpenOCD para fazer isso. Basta seguir as instruções do
+ nosso <a href="tut_openocd.html">tutorial OpenOCD</a>.
+ Na página do tutorial você também encontrará links para os arquivos de configuração do OpenOCD que
+ estamos usando para gravar <b>eLua</b> no comStick.</p>
+ <p><b>NOTA IMPORTANTE:</b> devido à algumas razões desconhecidas (talvez relacionados com o conversor USB/JTAG
+ on-board), nosso comStick não inicia a execução do código da memória flash
+ interna. Depois de ter sido ligado via cabo USB (sequência de reset com defeito?). Para superarmos isso, acesse um arquivo de
+ configuração especial do OpenOCD na nossa <a href="tut_openocd.html">página do tutorial</a>.
+ Chama-se comrst.cfg e você poderá usá-lo para reiniciar a sua comStick depois que ela for ligada.</p>
+ <p>É isso! <b>eLua</b> está gravado na CPU. Inicie agora o seu emulador de terminal e divirta-se, como descrito em <a href="using.html">usando eLua</a>.
+</p>
+$$FOOTER$$
+
Added: branches/eagle_mmc/doc/pt/modules_lm3s.html
===================================================================
--- branches/eagle_mmc/doc/pt/modules_lm3s.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/pt/modules_lm3s.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,5 @@
+$$HEADER$$
+<h3>Reference manual - LM3S platform dependent modules</h3>
+<p>This paragraph presents all the modules specific to the <a href="status.html">LM3S</a> platform.</p>
+$$FOOTER$$
+
Modified: branches/eagle_mmc/doc/pt/net_ref.html
===================================================================
--- branches/eagle_mmc/doc/pt/net_ref.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/pt/net_ref.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,11 +1,6 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Produto</title>
-
-<link rel="stylesheet" type="text/css" href="../style.css">
</head>
-<body style="background-color: rgb(255, 255, 255);">
<h3><a name="over"></a>rede</h3>
<br>
</body></html>
Modified: branches/eagle_mmc/doc/pt/news.html
===================================================================
--- branches/eagle_mmc/doc/pt/news.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/pt/news.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,138 +1,160 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
+$$HEADER$$
+<h3>eLua Project News</h3>
+<h2>06 de Outubro de 2009</h2>
+<p>A versão 0.6 de <strong>eLua</strong> foi lançada. As principais
+caracterÃsticas estão descritas a seguir. Para uma lista mais completa das
+novidades, por favor consulte nossa página de <a href="versionhistory.html">Histórico das Versões:</a></p>
+<ul>
+ <li>Licença alterada para MIT</li>
+ <li>Estrutura do site/doc completamente redesenhada</li>
+ <li>Documentação incluÃda na doc das distros para acesso offline</li>
+ <li>Adicionado suporte para CPUs AVR32</li>
+ <li>Adicionado suporte para CPUs STM32 Cortex-M3</li>
+ <li>Adicionado módulo ADC (conversor analógico-digital) com suporte a filtros de média móvel</li>
+ <li>Adicionado suporte a múltiplos toolchains</li>
+ <li>Novo comando ls (ou dir) para o shell</li>
+ <li>Novos exemplos de código incluÃdos na distro: pong, tetrives, spaceship (games), logo (graphics), adcpoll, adcscope</li>
+ <li>LTR (Lua Tiny RAM) patch adicionado (opcionalmente) Ã Lua</li>
+ <li>O conteúdo do ROM File System agora pode ser detalhado por
+ placa/kit</li>
+ <li>Semântica de funções da API revisada (código anterior pode precisar de adaptações)</li>
+</ul>
-<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);">
-<h3>eLua Project News</h3><div class="content">
+<h2>27 de Julho de 2009</h2>
+<p>GostarÃamos de convidar toda a comunidade de <b>eLua</b> para o Lua
+Workshop 2009, o primeiro a ser realizado no Brasil, nos dias 6 e 7 de
+outubro próximos. Bogdan e Dado farão apresentarão uma palestra e
+demonstrações no primeiro dia do evento. Outras demonstrações também serão
+apresentadas no segundo dia do evento, dedicado ao uso de Lua em jogos, como
+parte do Lua Games 2009, um pré-evento do SBGames 2009.<br />
+Teremos também o prazer de oferecer uma pequena surpresa para a comunidade
+<b>eLua</b> :)</p>
<h2>02 de Fevereiro de 2009</h2>
-<p>Ainda não temos uma versão oficial liberada, no entanto, estamos avançando muito com o projeto. A próxima versão será liberada,
-até o fim deste mês e virá com uma grande quantidade de novos recursos, incluindo suporte para duas novas plataformas, o sistema
-de documentação foi totalmente redesenhado, e algumas surpresas que não mencionarei no momento :) Estamos trabalhando muito para
-tornar <strong>eLua</strong> cada vez melhor para você.</p>
+<p>Ainda não temos uma versão oficial liberada, no entanto, estamos avançando muito com o projeto.
+Esperamos publicar a próxima versão até o final deste mês e ela virá com uma grande quantidade de novos recursos, incluindo suporte para duas novas plataformas, o sistema
+de documentação foi totalmente redesenhado, e mais surpresas como sempre :) </p>
<h2>01 de Novembro de 2008</h2>
-<p>A versão 0.5 foi lançada! Dentre outras novidades, essa versão vem com suporte TCP/IP para eLua (!!!!). Segue a lista das atualizações:</p>
+<p>A versão 0.5 foi lançada! Dentre outras novidades, essa versão vem com suporte TCP/IP para eLua (!!!!). Segue a lista das atualizações:</p>
<ul>
<li>Suporte para microcontroladores STR7 da ST Microeletronics</li>
<li>Suporte TCP/IP usando o stack uIP</li>
-<li>Suporte do console e do *shell* sobre TCP/IP além da conexão serial.</li>
-<li>Módulo "net" (interface **eLua** para as funções TCP/IP)</li>
-<li>Módulo "cpu" (interface **eLua** para o dados do microcontrolador escolhido)</li>
-<li>Novos exemplos: morse.lua (código morse), lhttpd.lua (script Lua para servidor HTTP)</li>
+<li>Suporte do console e do *shell* sobre TCP/IP além da conexão serial.</li>
+<li>Módulo "net" (interface **eLua** para as funções TCP/IP)</li>
+<li>Módulo "cpu" (interface **eLua** para o dados do microcontrolador escolhido)</li>
+<li>Novos exemplos: morse.lua (código morse), lhttpd.lua (script Lua para servidor HTTP)</li>
<li>Cross Compiling Lua (compila no computador, roda na plataforma)</li>
-<li>XMODEM pode agora receber o *bytecode*, além de código fonte Lua</li>
-<li>Um *buffer* dinâmico para o XMODEM (cresce se necessário) ao invés de tamanho fixo</li>
-<li>Documentação atualizada do projeto</li>
+<li>XMODEM pode agora receber o *bytecode*, além de código fonte Lua</li>
+<li>Um *buffer* dinâmico para o XMODEM (cresce se necessário) ao invés de tamanho fixo</li>
+<li>Documentação atualizada do projeto</li>
</ul>
-<p>Adicionado também um novo tutorial sobre como usar <a href="http://www.eluaproject.net/?p=eLua_on_STR7_CPUs"><strong>eLua</strong> com o microcontrolador STR7</a> da ST. O restante da página do projeto foi atualizada refletindo o Status atual do projeto (isso fica mais evidente nas páginas de <a href="/pt/Faq.html">Perguntas mais frequentes</a>, <a href="/pt//pt/examples.html">Exemplos</a> e <a href="/pt//pt/status.html">Status</a>.</p>
+<p>Adicionado também um novo tutorial sobre como usar <a href="installing_str7.html"><strong>eLua</strong> com o microcontrolador STR7</a> da ST. O restante da página do projeto foi atualizada refletindo o Status atual do projeto (isso fica mais evidente nas páginas de <a href="faq.html">Perguntas mais frequentes</a>, <a href="examples.html">Exemplos</a> e <a href="status.html">Status</a>.</p>
-<p><strong>Importante:</strong> não é necessário atualizar o binutils para a versão 2.19 para os microcontroladores Cortex. O tutorial do <a href="http://www.eluaproject.net/?p=Building_GCC_for_Cortex">Cortex GCC para Cortex</a> já foi atualizado com esta informação.</p>
+<p><strong>Importante:</strong> não é necessário atualizar o binutils para a versão 2.19 para os microcontroladores Cortex. O tutorial do <a href="tc_cortex.html">Cortex GCC para Cortex</a> já foi atualizado com esta informação.</p>
-<p>Desfrute dessa nova atualização. A próxima versão será focada na redução das memórias Flash e RAM de <strong>eLua</strong>, além de muitas outras surpresas :)</p>
+<p>Desfrute dessa nova atualização. A próxima versão será focada na redução das memórias Flash e RAM de <strong>eLua</strong>, além de muitas outras surpresas :)</p>
<h2>16 de Outubro de 2008</h2>
-<p>O <a href="http://www.eluaproject.net/?p=Using_OpenOCD">tutorial OpenOCD</a> foi atualizado com uma nova seção sobre como usar o OpenOCD com CPU's STR7 da ST. Além disso, a <a href="http://www.eluaproject.net/?p=Overview">página sobre</a> foi atualizada com mais informações sobre os autores de eLua. É esperada uma nova versão de Elua para até o fim de Outubro.</p>
+<p>O <a href="tut_openocd.html">tutorial OpenOCD</a> foi atualizado com uma nova seção sobre como usar o OpenOCD com CPU's STR7 da ST. Além disso, a <a href="overview.html">página sobre</a> foi atualizada com mais informações sobre os autores de eLua. É esperada uma nova versão de eLua para até o fim de Outubro.</p>
<h2>10 de Setembro de 2008</h2>
-<p>Foi liberada a versão 0.4.1! É uma atualização de pouca importância, pois seu propósito principal é se manter atualizada com Lua,
-dessa forma, eLua está agora com a mais recente versão de Lua (5.1.4).
-Provavelmente você não precisa fazer a atualização para esta versão (já que a 5.1.4 corrige alguns poucos e exóticos problemas da 5.1.3), logo,
- estou disponibilizando somente os fontes, sem nenhum executável. Segue abaixo o log das alterações:</p>
+<p>Foi liberada a versão 0.4.1! É uma atualização de pouca importância, pois seu propósito principal é se manter atualizada com Lua,
+dessa forma, eLua está agora com a mais recente versão de Lua (5.1.4).
+Provavelmente você não precisa fazer a atualização para esta versão (já que a 5.1.4 corrige alguns poucos e exóticos problemas da 5.1.3), logo,
+ estou disponibilizando somente os fontes, sem nenhum executável. Segue abaixo o log das alterações:</p>
<ul>
-<li>Alterada a estrutura do sistema de arquivos; agora você pode gerar executáveis de ambas as versões de Lua (ponto flutuante e somente inteiro) a partir do mesmo diretório;</li>
-<li>Feita uma biblioteca matemática configurável usando-se o próprio mecanismo de bibliotecas já eistentes na plataforma;</li>
-<li>Os módulos "os" and "package" não são mais carregados por Lua, uma vêz que não podem mais ser utilizados. Devido a isso, o tamanho do código Lua ficou reduzido;</li>
-<li>A documentação do projeto foi atualizada.</li>
+<li>Alterada a estrutura do sistema de arquivos; agora você pode gerar executáveis de ambas as versões de Lua (ponto flutuante e somente inteiro) a partir do mesmo diretório;</li>
+<li>Feita uma biblioteca matemática configurável usando-se o próprio mecanismo de bibliotecas já eistentes na plataforma;</li>
+<li>Os módulos "os" and "package" não são mais carregados por Lua, uma vêz que não podem mais ser utilizados. Devido a isso, o tamanho do código Lua ficou reduzido;</li>
+<li>A documentação do projeto foi atualizada.</li>
</ul>
<h2>02 de Setembro de 2008</h2>
-<p>Foi liberada a versão 0.4! Segue abaixo o log das alterações:</p>
+<p>Foi liberada a versão 0.4! Segue abaixo o log das alterações:</p>
<ul>
<li>Criado suporte para LPC2888 (preliminarmente);</li>
-<li>Criado o módulo PWM;</li>
+<li>Criado o módulo PWM;</li>
<li>Novos exemplos: TV-B-Gone (desliga a sua TV), piano (toca piano a partir do teclado de seu PC),
- pwmled (apaga/acende led), todas baseadas no novo módulo PWM;</li>
-<li>Criado suporte para múltiplos espaços de memória (este recurso pode ser usado para obter vantagens tanto de memória RAM interna da CPU quanto de chips externos de memória RAM em placas com memória RAM);</li>
-<li>Autorun: Caso o arquivo "autorun.lua" exista no sistema de arquivos, este é executado antes do inicio do shell;</li>
-<li>Criado os módulos "pack" (compactação/descompactação de dados binários) e "bit" (operações binárias);</li>
-<li>Atualizado o compilador do sistema, que agora está mais fácil de utilizar e sabendo como lidar com "placas", como também CPUs;</li>
-<li>Foram modificados os módulos da plataforma existente para utilizar menos RAM e retornar uma mensagem de erro quando da tentativa de uso de um recurso não disponível no sistema;</li>
-<li>A documentação do projeto foi atualizada.</li>
+ pwmled (apaga/acende led), todas baseadas no novo módulo PWM;</li>
+<li>Criado suporte para múltiplos espaços de memória (este recurso pode ser usado para obter vantagens tanto de memória RAM interna da CPU quanto de chips externos de memória RAM em placas com memória RAM);</li>
+<li>Autorun: Caso o arquivo "autorun.lua" exista no sistema de arquivos, este é executado antes do inicio do shell;</li>
+<li>Criado os módulos "pack" (compactação/descompactação de dados binários) e "bit" (operações binárias);</li>
+<li>Atualizado o compilador do sistema, que agora está mais fácil de utilizar e sabendo como lidar com "placas", como também CPUs;</li>
+<li>Foram modificados os módulos da plataforma existente para utilizar menos RAM e retornar uma mensagem de erro quando da tentativa de uso de um recurso não disponÃvel no sistema;</li>
+<li>A documentação do projeto foi atualizada.</li>
</ul>
<h2>02 de Setembro de 2008</h2>
-<p>O site eLua foi atualizado antes da liberação da nova versão 0.4, a qual estará em breve disponível (muito breve por sinal). Existe agora uma <a href="http://www.eluaproject.net/?p=Faq">página FAQ</a>. Além disso, as páginas <a href="http://www.eluaproject.net/?p=Status">status e mapa do site</a>, <a href="http://www.eluaproject.net/?p=Building_eLua">compilando eLua</a>, <a href="http://www.eluaproject.net/?p=Example">exemplos de programas</a> e <a href="http://www.eluaproject.net/?p=Using_OpenOCD">usando OpenOCD</a> foram atualizadas. E existe ainda uma outra página chamada <a href="http://www.eluaproject.net/?p=eLua_on_LPC2888_CPUs">Como usar eLua com CPUs LPC2888</a>. Esperada ainda hoje a liberação da versão 0.4.</p>
+<p>O site eLua foi atualizado antes da liberação da nova versão 0.4, a qual estará em breve disponÃvel (muito breve por sinal). Existe agora uma <a href="faq.html">página FAQ</a>. Além disso, as páginas <a href="status.html">status e mapa do site</a>, <a href="building.html">compilando eLua</a>, <a href="examples.html">exemplos de programas</a> e <a href="tut_openocd.html">usando OpenOCD</a> foram atualizadas. E existe ainda uma outra página chamada <a href="installing_lpc2888.html">Como usar eLua com CPUs LPC2888</a>. Esperada ainda hoje a liberação da versão 0.4.</p>
<h2>09 de Agosto de 2008</h2>
-<p>OK, está levando mais tempo do que esperava :) Está disponível a página sobre como utilizar eLua com CPUs STR9 <a href="http://www.eluaproject.net/?p=eLua_on_STR9_CPUs">aqui</a>.</p>
+<p>OK, está levando mais tempo do que esperava :) Está disponÃvel a página sobre como utilizar eLua com CPUs STR9 <a href="installing_str9.html">aqui</a>.</p>
<h2>09 de Agosto de 2008</h2>
-<p>Foi liberada a versão 0.3! O página do projeto foi atualizada, e mais seções estarão disponíveis em breve, incluindo um tutorial sobre como utilizar eLua com CPUs STR9. Segue abaixo o log das alterações da versão 0.3:</p>
+<p>Foi liberada a versão 0.3! O página do projeto foi atualizada, e mais seções estarão disponÃveis em breve, incluindo um tutorial sobre como utilizar eLua com CPUs STR9. Segue abaixo o log das alterações da versão 0.3:</p>
<ul>
-<li>Agora você pode jogar hangman diretamente de eLua :), graças ao novo módulo "term" que é capaz de tratar sequências de "escape" ANSI;</li>
+<li>Agora você pode jogar hangman diretamente de eLua :), graças ao novo módulo "term" que é capaz de tratar sequências de "escape" ANSI;</li>
<li>Criado suporte para o ST STR912FW44</li>
<li>Criado suporte para o Cortex LM3S6965</li>
-<li>Sistema de compilação mais intuitivo e flexível (nova sintaxe, seleção de componentes em tempo de compilação)</li>
-<li>Examples de eLua esão agora fazendo parte do repositório</li>
-<li>A documentação do projeto foi atualizada.</li>
+<li>Sistema de compilação mais intuitivo e flexÃvel (nova sintaxe, seleção de componentes em tempo de compilação)</li>
+<li>Examples de eLua esão agora fazendo parte do repositório</li>
+<li>A documentação do projeto foi atualizada.</li>
</ul>
<h2>06 de Agosto de 2008</h2>
-<p>A página de web foi atualizada com o <a href="http://www.eluaproject.net/?p=Using_OpenOCD">tutorial OpenOCD</a>
-o qual continuará sendo revisado toda vêz que novas plataformas forem adicionadas. Esta atualização é também um anúncio informal da liberação em breve da versão 0.3, a qual (entre outras coisas) traz o suporte para o <a href="http://www.hitex.com/index.php?id=383">STR9-comStick</a>.</p>
+<p>A página de web foi atualizada com o <a href="tut_openocd.html">tutorial OpenOCD</a>
+o qual continuará sendo revisado toda vêz que novas plataformas forem adicionadas. Esta atualização é também um anúncio informal da liberação em breve da versão 0.3, a qual (entre outras coisas) traz o suporte para o <a href="http://www.hitex.com/index.php?id=383">STR9-comStick</a>.</p>
<h2>29 de Julho de 2008</h2>
-<p>eLua possui um novo repositório no BerliOS. Além do novo menu da página da web, a novidade é que o repositório de código está baseado no SVN (ao contrário do CVS utilizado até o momento).
-Caso você seja um desenvolvedor, provavelmente esta é uma boa notícia. Caso contrário, verifique a página de download para conhecer os novos locais para download.</p>
+<p>eLua possui um novo repositório no BerliOS. Além do novo menu da página da web, a novidade é que o repositório de código está baseado no SVN (ao contrário do CVS utilizado até o momento).
+Caso você seja um desenvolvedor, provavelmente esta é uma boa notÃcia. Caso contrário, verifique a página de download para conhecer os novos locais para download.</p>
<h2>28 de Julho de 2008</h2>
-<p>Recebi um relato sobre erros de linker após a execução de <a href="http://www.eluaproject.net/?p=Building_GCC_for_Cortex">minhas intruções</a> durante a compilação de um simples programa C++ para a CPU Cortex com compilador.
- Verifiquei e descobri que a biblioteca gcc's C++ (libstdc++) não estava gerando código corretamente para Cortex-M3. Minha culpa. Corrigi a página do tutorial. Foi necessário uma única alteração no passo 4,
-onde era preciso fornecer mais parametros para os comandos "make", e não somente o -CFLAGS. Obrigado pelo aviso.</p>
+<p>Recebi um relato sobre erros de linker após a execução de <a href="tc_cortex.html">minhas intruções</a> durante a compilação de um simples programa C++ para a CPU Cortex com compilador.
+ Verifiquei e descobri que a biblioteca gcc's C++ (libstdc++) não estava gerando código corretamente para Cortex-M3. Minha culpa. Corrigi a página do tutorial. Foi necessário uma única alteração no passo 4,
+onde era preciso fornecer mais parametros para os comandos "make", e não somente o -CFLAGS. Obrigado pelo aviso.</p>
<h2>27 de Julho de 2008</h2>
-<p>Foi liberada a versão 0.2! Além disso, como você já deve ter percebido, a página do projeto foi bastante modificada. Segue abaixo o log das alterações da versão 0.2:</p>
+<p>Foi liberada a versão 0.2! Além disso, como você já deve ter percebido, a página do projeto foi bastante modificada. Segue abaixo o log das alterações da versão 0.2:</p>
<ul>
<li>Criado suporte para o Cortex LM3S8962</li>
-<li>Módulos para novas plataformas (UART, SPI, Timer, platform data)</li>
-<li>Primeiro versão do eLua shell</li>
+<li>Módulos para novas plataformas (UART, SPI, Timer, platform data)</li>
+<li>Primeiro versão do eLua shell</li>
<li>Arquivos fontes de Lua podem agora serem enviados para processadores com XMODEM</li>
-<li>Pode-se baixar arquivos binários de imagem a partir de seções de "arquivos", logo, você não precisa recompilar eLua</li>
+<li>Pode-se baixar arquivos binários de imagem a partir de seções de "arquivos", logo, você não precisa recompilar eLua</li>
</ul>
<h2>25 de Julho de 2008</h2>
-<p>A página do projeto fo atualizada para refletir o atual <a href="http://www.eluaproject.net/?p=Status">status e roadmap</a> de eLua.
-Atualmente as páginas de status e de roadmap são separadas. Além disso, a versão 0.2 está sendo liberada em breve, com vários novos recursos, melhoramentos e
-suporte para novas plataformas. Novas documentações estão sendo preparadas.</p>
+<p>A página do projeto fo atualizada para refletir o atual <a href="status.html">status e roadmap</a> de eLua.
+Atualmente as páginas de status e de roadmap são separadas. Além disso, a versão 0.2 está sendo liberada em breve, com vários novos recursos, melhoramentos e
+suporte para novas plataformas. Novas documentações estão sendo preparadas.</p>
<h2>15 de Julho de 2008</h2>
-<p>Criado um <a href="http://www.eluaproject.net/?p=Booting_eLua_from_a_stick">tutorial</a> sobre como preparar um pendrive USB de boot com eLua! Acesse-o enquanto está quente! :)</p>
+<p>Criado um <a href="tut_bootstick.html">tutorial</a> sobre como preparar um pendrive USB de boot com eLua! Acesse-o enquanto está quente! :)</p>
<h2>11 July 2008</h2>
-<p>A versão 0.1 finalmente saiu! Certifique-se de verificar a <a href="http://www.eluaproject.net/?p=Downloads">página de download</a>,
-e também a página do projeto. A instruções de como fazer estão incluídas nos arquivos eLua. Além disso, novos tutoriais (construindo compiladores para o ARM e para o i386) foram criados, e a página <a href="http://www.eluaproject.net/?p=Booting_your_PC_in_eLua">boot em Lua</a> fo atualizada para refletir o fato de que agora você mesmo pode construir um arquivo ELF!</p>
+<p>A versão 0.1 finalmente saiu! Certifique-se de verificar a <a href="downloads.html">página de download</a>,
+e também a página do projeto. A instruções de como fazer estão incluÃdas nos arquivos eLua. Além disso, novos tutoriais (construindo compiladores para o ARM e para o i386) foram criados, e a página <a href="tut_bootpc.html">boot em Lua</a> fo atualizada para refletir o fato de que agora você mesmo pode construir um arquivo ELF!</p>
<h2>07 de Julho de 2008</h2>
-<p>Estou ainda "polindo" os códigos fontes e criando mais documentação antes de atualizar a promeira versão par o CVS. Enquanto isso, Preparei uma ótima surpresa para todos voces que se mostraram interessados em eLua (e par voces que não se interessaram também, pois desejo muito que a partir de agora voces fiquem curiosos:) ). Logo, se você sempre quis iniciar seu PC com Lua, dê uma olhada <a href="http://www.eluaproject.net/?p=Booting_your_PC_in_eLua">aqui</a>.
-É isso mesmo: sem OS, simplesmente o GRUB carrega um arquivo de boot tipo ELF!
-O arquivo tipo ELF é construido de acordo com a mesma estrutura em árvore que utilizei para montar dispositivos embarcados em eLua, precisei mudar somente a camada da plataforma
-(mais informações após a próxima atualização dos fontes e inclusão de novas documentações).
-Desejo que tenham gostado, da mesma maneira que eu. Enquanto isso é apenas uma prova de conceitos, não irei abandonar a idéia do "standalone Lua on PC", pois devem ter aplicações interesantes (pense em
-"BIOS scripting with Lua", <a href="http://en.wikipedia.org/wiki/Open_Firmware">Open Firmware</a> com Lua ao invés de Forth, aplicações educacionais e muias outras.)</p>
+<p>Estou ainda "polindo" os códigos fontes e criando mais documentação antes de atualizar a promeira versão par o CVS. Enquanto isso, Preparei uma ótima surpresa para todos voces que se mostraram interessados em eLua (e par voces que não se interessaram também, pois desejo muito que a partir de agora voces fiquem curiosos:) ). Logo, se você sempre quis iniciar seu PC com Lua, dê uma olhada <a href="tut_bootpc.html">aqui</a>.
+É isso mesmo: sem OS, simplesmente o GRUB carrega um arquivo de boot tipo ELF!
+O arquivo tipo ELF é construido de acordo com a mesma estrutura em árvore que utilizei para montar dispositivos embarcados em eLua, precisei mudar somente a camada da plataforma
+(mais informações após a próxima atualização dos fontes e inclusão de novas documentações).
+Desejo que tenham gostado, da mesma maneira que eu. Enquanto isso é apenas uma prova de conceitos, não irei abandonar a idéia do "standalone Lua on PC", pois devem ter aplicações interesantes (pense em
+"BIOS scripting with Lua", <a href="http://en.wikipedia.org/wiki/Open_Firmware">Open Firmware</a> com Lua ao invés de Forth, aplicações educacionais e muias outras.)</p>
<h2>05 de Julho de 2008</h2>
-<p>Inaugurada a página na web! Por enquanto você pode ler as <a href="http://www.eluaproject.net/?p=Overview">descrições dos projetos</a>. Além disso, está disponível um tutorial que explica como compilar um toolchain GCC para a arquitetura Cortex <a href="http://www.eluaproject.net/?p=Building_GCC_for_Cortex">aqui</a>.</p>
-</div>
-</body></html>
+<p>Inaugurada a página na web! Por enquanto você pode ler as <a href="overview.html">descrições dos projetos</a>. Além disso, está disponÃvel um tutorial que explica como compilar um toolchain GCC para a arquitetura Cortex <a href="tc_cortex.html">aqui</a>.</p>
+$$FOOTER$$
+
Modified: branches/eagle_mmc/doc/pt/overview.html
===================================================================
--- branches/eagle_mmc/doc/pt/overview.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/pt/overview.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,98 +1,139 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
+$$HEADER$$
+<a name="whatis" /><h3>O que é eLua ?</h3>
+<p><strong>eLua</strong>
+significa <strong>Embedded Lua</strong> e o projeto projeto visa trazer a
+funcionalidade completa da linguagem de programação <a href="http://www.lua.org">Lua</a> para o mundo
+do desenvolvimento de software embedded.</p>
+<p>A implementação busca oferecer isto de uma forma
+simples, para que não só desenvolvedores experientes mas também iniciantes no mundo embarcado e até
+mesmo usuários finais dos sistemas, possam desenvolver e alterar os
+programas dos seus produtos.</p>
-<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);">
-<a name="whatis"></a><h3>What is eLua ?</h3>
-<strong>eLua</strong>
-stands for <strong>Embedded Lua</strong> and the project
-aims to offer the full set of features of the <a href="www.lua.org">Lua Programming Language</a> to the embedded world. <span style="font-weight: bold;"><br>eLua</span>
-is not a striped down sub-sub-set of a language, much on the contrary.
-Besides offering different flavors of full Lua implementations
-(ie: integer or fp numbers, ...), <span style="font-weight: bold;">eLua</span>
-extends Lua with some neat types
-for the embedded world (ie: light tables, light functions, ...), to
-allow them to be romable and the aplications to exploit better the
-balance ROM/RAM of the current MCUs.<br><br>
-Lua is the perfect example of a
-minimal, yet fully
-functional language. Although generally advertised as a "scripting
-language" (and used accordingly especially in the game industry), it is
-also fully capable of running stand-alone programs. Its limited
-resource requirements make it suitable to a lot of microcontroller
-families. Lua's incredible portability (Lua code is ANSI C and runs virtually in every known platform) and <span style="font-weight: bold;">eLua</span>'s
-roadmap for supporting the most used MCUs on the market, opens to the
-embedded world a new degree of "portability". Write your program in Lua
-and run it, without or with very few modifications, on every <span style="font-weight: bold;">eLua</span> supported platform, even with different architectures!<br><br>The aim of the project is to have a fully functional Lua development
-environment <strong>on the microcontroller itself</strong>,
-without the need to install a specific development environment on the PC side.
-Initially, a PC will still be needed in order to edit the Lua programs
-for the microcontroller. But as the project evolves this requirement
-will be relaxed, as a basic editor (also residing on the
-microcontroller) will be usable with a variety of input/output devices.<br><br><span style="font-weight: bold;"></span><br>
-<br><br>
-<a name="audience"></a><br><h3>Audience</h3>
-<span style="font-weight: bold;">eLua</span> has a wide and varied audience, from highly skilled developers
-that want to extend their programs with the Lua library facilities and
-portable features, to the newcomer to the embedded world, who wants an
-easy and powerfull environment for prototyping, rapid application
-development, educational or final product quick production.<br><br><span style="font-weight: bold;">eLua</span>
-allows new embedded world programmers to use the simplicity and
-powerfullness of the Lua programming language, to hide low-level
-complexities and platform/architecture-dependent features. A whole new
-class of embedded programmers, with no deep knowledge of the peripheral
-details but with powerfull aplications in mind is now possible. Modern
-designers and multimedia artists are already an example of this "class".<br><br>On
-the other edge of the category, oldtime and skilled embedded developers
-can create complex and abstract modules, offering a degree of portability
-to the final user never dreamed before on the embedded world.<br><br>eLua audience would be among the following categories:<br><ul><li>Embedded developers that are looking for a fast, easy to use and powerful way of coding.</li><li>First-time
-embedded programmers (or simply first time programmers) that are
-looking for an easy way to "dive" into the embedded programming world.
-eLua is a great learning tool.</li><li>People that aren't really
-developers, but want to be able to prototype an embedded system
-fast and painless, without having to learn C for that.</li><li>Embedded
-developers that need powerfull meta-language mecanisms for complex code
-algorithms and data description, not offered by the languages available
-to the embedded development world.</li><li>Field
-engineers that can go their customer site and debug an eLua module on
-site, without any preparation at all, since the whole development
-environment resides on chip already.</li></ul><br><a name="authors"></a>
-<h3>Authors</h3>
-<p><strong>eLua</strong> is a joint project of <strong><a href="#contacts">Bogdan Marinescu</a></strong>,
-a software developer from Bucharest (Romania) and <strong><a href="#contacts">Dado Sutter</a></strong>,
-head of the Led Lab at <a href="http://www.puc-rio.br/">PUC-Rio
-University</a>, in Rio de Janeiro (Brazil). </p>
-<p>Its origins come from the <a href="http://www.circuitcellar.com/renesas2005m16c/winners/1685.htm">ReVaLuaTe</a>
-project also developed by Bogdan Marinescu (as a contest entry for the
-2005 Renesas M16CDesign Contest), and the Volta Project, managed by
-Dado Sutter at PUC-Rio from 2005 to 2007.</p>
-<p><strong>eLua</strong> is an Open Source and
-collaborative project and an always growing list of collaborators can
-be found in our <a href="#credits">Credits
-Page</a></p><p></p>
-<div style="text-align: center;"><span style="font-weight: bold;"></span><br><span style="font-weight: bold;"></span></div><table style="width: 578px; height: 256px; text-align: left; margin-left: auto; margin-right: auto;" border="1" cellpadding="2" cellspacing="2"><tbody><tr><td style="text-align: center; font-family: Verdana; font-weight: bold;" valign="undefined"><big>ReVaLuaTe Project</big></td><td style="text-align: center; font-family: Verdana; font-weight: bold;" valign="undefined"><big>Volta Project</big></td></tr><tr><td style="text-align: center;" valign="undefined"><img style="width: 278px; height: 188px;" alt="ReVaLuaTe project picture" src="../wb_img/terminalreneseas.jpg"></td><td style="text-align: center;" valign="undefined"><img style="width: 278px; height: 209px;" alt="Volta project picture" src="../wb_img/volta-small.jpg"></td></tr></tbody></table><div style="text-align: center;"><span style="font-weight: bold;"></span><br><span style="font-weight: bold;"!
></span><br><span style="font-weight: bold;"></span><br><span style="font-weight: bold;"></span></div><br><a name="contacts"></a>
-<h3>Contacts</h3>
-<p><strong>eLua</strong> authors can be contacted at:</p><p><strong>Bogdan Marinescu:</strong> bogdan dot marinescu at gmail dot com</p>
+<p><strong>eLua</strong> não é uma versão reduzida de Lua, muito pelo contrário, ela
+oferece os recursos completos da versão desktop de Lua, complementando-a
+ainda com caracterÃsticas especÃficas para o uso embedded.
+Oferece também a mesma possibilidade de escolha no uso de implementações diferentes
+de Lua (ex: Lua Inteiro x Lua Ponto-Flutuante). Muito trabalho foi e ainda será feito no sentido de tornar Lua mais "amigável" no mundo embedded,
+como as caracterÃsticas já adicionadas que permitem a redução dos requisitos de memória.</p>
+<p>Lua é o exemplo perfeito de uma linguagem mÃnima e, ainda assim, totalmente funcional. Embora geralmente anunciada como uma linguagem de "scripting" (e utilizada
+fortemente como tal na indústria de jogos e em tantas outras áreas), Lua é capaz de executar programas como qualquer outra linguagem
+tradicional.
+Grandes sistemas e aplicações (desktop ou web) hoje, são desenvolvidos utilizando
+seu poder e sua performance (ex: Adobe Lightroom, World of Warcraft, ...).
+Suas reduzidas necessidades de recursos de hardware, a tornam especialmente adequada para um grande número de famÃlias de microcontroladores.
+A alta portabilidade intrÃnseca do código Lua original (que é ANSI C e funciona praticamente em todas as plataformas
+que se conhece hoje), combinada com a arquitetura do software de <b>eLua</b>, altamente portátil,
+permite a migração fácil para uma grande variedade e arquiteturas de
+microcontroladores.
+As bibliotecas de acesso a periféricos disponibilizadas por <b>eLua</b> também são portáteis por
+definição, podendo-se assim executar um mesmo programa em Lua, sem ou com poucas
+modificações, em qualquer hardware que "rode" <span style="font-weight: bold;">eLua</span> (o <a href="status.html">status do projeto & roadmap</a>
+mostram uma lista sempre crescente de plataformas com suporte à <b>eLua</b>).
+<b>eLua</b> herdou o design minimalista e funcional de Lua, mantendo a filosofia bem conhecida do "<b>KISS</b>" - "<i>Keep It Small and Simple</i>", que significa "Mantenha seu código
+e sua arquitetura simples e sua complexidade reduzida".</p>
-<p><strong>Dado Sutter:</strong> dadosutter at gmail dot com</p> <br> You are also welcome to share your questions and suggestions on our <a href="comunity.html#lists">Mail Discussion List</a>
-<p></p><a name="license"></a>
-<h3>License</h3>
-<div class="content">
-<p><strong>eLua</strong> is Open Source and is freely
-distributed under the GPL (migrating to BSD soon) licence.</p>
-<p>The Lua code (with slight modifications) is included in the
-source
-tree and is, of course, licensed under the same MIT license that Lua
-uses.</p>
-<p>The terms of each of these licences can be viewed on their own
-pages at:</p>
-<p><a target="_top" href="http://en.wikipedia.org/wiki/GNU_General_Public_License">GPL
-Licence</a></p>
-<p><a target="_top" href="http://en.wikipedia.org/wiki/BSD_license#Terms">BSD
-Licence</a></p>
-<p><a target="_top" href="http://en.wikipedia.org/wiki/MIT_License">MIT
-Licence</a></p><p></p><p></p><p></p><p></p><p></p><p></p><p></p><p></p><p></p><p></p><p></p><p></p><p></p><p></p><p></p><p></p><p></p><p><a href="http://en.wikipedia.org/wiki/MIT_License"></a></p>
-</div>
-</body></html>
\ No newline at end of file
+<a name="features"></a><h3>Recursos</h3>
+<p><b>eLua</b> permite que você execute Lua diretamente no seu microcontrolador.
+Um grande conjunto de módulos complementares já existe para a programação de periféricos <strong>eLua</strong>
+e o desenvolvimento de novos tem um crescimento cada vez mais rápido.</p>
+<p>Relacionamos a seguir algumas funções que estão prontas ou sendo implementadas:</p>
+<ul>
+ <li>um sistema de configuração do build flexÃvel e um serviço de build
+ remoto via web</li>
+ <li>acesso ao interpretador Lua diretamente na sua MCU, através de uma variedade de
+ protocolos de transportes fÃsicos (RS-232, ethernet, ...)</li>
+ <li>uma biblioteca de periféricos independentes de plataforma (PIO, UART, PWM, SPI, TMR, ADC, NET,
+ I2C, CAN ...)</li>
+ <li>um File System (por enquanto apenas em ROM), fácil de ser portado para diferentes tipos de chips de memória e outros dispositivos de armazenamento</li>
+ <li>um pequeno Fyle System FAT R/W, para cartões MMC e SD</li>
+ <li>um shell próprio mÃnimo (para operações com arquivos, configuração do ambiente e outros recursos)</li>
+ <li>suporte a redes TCP/IP</li>
+ <li>um servidor http embedded escrito em Lua</li>
+ <li>terminal/console via serial ou Ethernet</li>
+ <li>depuração (diretamente no MCU ou remotamente com o PC)</li>
+ <li>execução distribuida de código (LuaRPC)</li>
+</ul>
+
+<p>Para obter mais informações sobre as funcionalidades (implementadas e previstas) em <strong>eLua</strong> veja a <a href="status.html">página de status</a>.</p>
+<p>O projeto foi concebido de forma que migrar <strong>eLua</strong> para uma outra plataforma
+ou mesmo arquitetura, seja algo fácil de ser realizado.
+Atualmente, esta migração está restrita às plataformas para as quais gcc + newlib
+ou toolchains completos (ex:CodeSourcery) estejam disponÃveis.
+Esta restrição irá desaparecer em um futuro próximo, já que <b>eLua</b> terá sua própria libc e portanto
+estará disponÃvel em um leque mais amplo de MCUs.</p>
+<p>Assim como para os ambientes Desktop, Lua em <strong>eLua</strong> está disponÃvel em duas implementações: "Lua padrão" (usando ponto flutuante) e "Lua inteiro" (usando inteiro).
+"Lua padrão" realiza operações de ponto flutuante (mais lentas devido a emulação via software no MCU),
+enquanto "Lua inteiro" realiza operações com números inteiros
+(suporte para ponto fixo e ponto flutuante podem ser adicionados em módulos separados) e assim será mais rápido.</p>
+
+<a name="audience"></a><h3>Público Alvo</h3>
+<p><span style="font-weight: bold;">eLua</span> tem uma audiência ampla e
+variada, desde recém-chegados ao mundo embedded que desejam um fácil e poderoso ambiente para prototipação,
+desenvolvimento e produção rápida de aplicações, como desenvolvedores altamente
+qualificados, que precisam expandir seus programas com recursos de
+bibliotecas de alto nÃvel com muita portabilidade.</p>
+<p><span style="font-weight: bold;">eLua</span> permite que programadores
+com pouca experiência no mundo embedded utilizem a simplicidade
+e o poder da linguagem de programação Lua, sem precisarem se preocupar com as complexidades e
+da arquitetura do hardware em uso.
+Utilizando <b>eLua</b>, o programador pode concentrar-se na implementação do seu programa,
+sem ter que se preocupar com detalhes de acessos à registros, configuração de periféricos e mesmo gerenciamento de memória.
+Com isso, aumentamos a produtividade e eliminamos tarefas muitas vezes frustrantes de lidar com drivers
+complexos de plataformas especÃficas. <stront>eLua</strong> absorve a
+complexidade das diversas arquiteturas, sem afastar demais o usuário do hardware.</p>
+<p>A lista abaixo resume o público-alvo de <b>eLua</b>:</p>
+<ul>
+ <li>Desenvolvedores de sistemas embarcados que estão procurando uma maneira rápida, fácil de usar e uma poderosa forma de codificação.</li>
+ <li>Novos programadores de sistemas embarcados (ou simplesmente programadores) que estão procurando uma maneira fácil de "mergulhar" no mundo da programação
+ embedded. <b>eLua</b> é uma grande ferramenta de aprendizagem.</li>
+ <li>Pessoas que não são realmente os desenvolvedores, mas ainda assim querem ser capazes de projetar
+ e prototipar sistemas embarcados de forma rápida e sem muita dor-de-cabeça, sem ter para isso que aprenderem a linguagem C.
+ (Designers, artistas, ...)</li>
+ <li>Desenvolvedores de sistemas embarcados que necessitam de mecanismos poderosos de meta-linguagem, para codificar algoritmos complexos e descrição de dados.</li>
+ <li>Engenheiros de campo que podem ir aos seus clientes realizar depuração de módulos de <b>eLua</b> no local
+ ou mesmo remotamente, sem para isso necessitar de preparação, já que todo o ambiente de desenvolvimento reside em um chip.</li>
+</ul>
+
+<a name="authors" /><h3>Autores</h3>
+<p><strong>eLua</strong> é um projeto conjunto de <strong><a href="#contacts">Bogdan Marinescu</a></strong>, um desenvolvedor de software de Bucarest,
+na Romênia e <strong><a href="#contacts">Dado Sutter</a></strong>, que
+dirige o Laboratório LED Lab na <a href="http://www.puc-rio.br/">PontifÃcia Universidade Católica, PUC-Rio</a>, no Rio de
+Janeiro, Brasil.</p>
+<p>Suas origens vêm dos projetos <a
+href="http://www.circuitcellar.com/renesas2005m16c/winners/1685.htm">ReVaLuaTe</a>,
+também desenvolvido pelo Bogdan Marinescu (como participante do concurso Renesas M16C Design de 2005) e do Projeto Volta,
+desenvolvido por Dado Sutter na PUC-Rio entre 2005 e 2007.</p>
+<p><strong>eLua</strong> é um projeto Open Source e uma lista crescente de colaboradores pode ser encontrada na nossa <a
+href="en_comunity.html#credits">página de créditos</a></p>
+<br />
+<table style="width: 578px; height: 256px; text-align: left; margin-left: auto; margin-right: auto;" border="1" cellpadding="2" cellspacing="2">
+<tbody>
+<tr>
+ <td style="text-align: center; font-family: Verdana; font-weight: bold;"><big>Projeto ReVaLuaTe</big></td>
+ <td style="text-align: center; font-family: Verdana; font-weight: bold;"><big>Projeto Volta</big></td>
+</tr>
+<tr>
+ <td style="text-align: center;"><img style="width: 278px; height: 188px;" alt="ReVaLuaTe project picture" src="images/terminalreneseas.jpg" /></td>
+ <td style="text-align: center;"><img style="width: 278px; height: 209px;" alt="Volta project picture" src="images/volta-small.jpg" /></td>
+</tr>
+</tbody>
+</table>
+<br />
+<br />
+<br />
+<a name="contacts" /><h3>Contatos</h3>
+<p>Os autores de <strong>eLua</strong> podem ser contactados em:</p><p><strong>Bogdan Marinescu:</strong> bogdan.marinescu -at- gmail.com</p>
+<p><strong>Dado Sutter:</strong> dadosutter -at- gmail.com</p>
+<p>Sejam bem-vindos e compartilhem suas dúvidas e sugestões em nossa <a href="comunity.html#lists">Lista de Discussão</a></p>
+<br />
+<br />
+<a name="license" /><h3>Licença</h3>
+<p><strong>eLua</strong> é Open Source e é distribuÃda gratuitamente sob a licença MIT.</p>
+<p>A licença MIT, diferentemente de outras licenças de código aberto (ex:
+GPL), permite que produtos de código proprietário sejam desenvolvidos
+utilizando <b>eLua</b>.</p>
+<p>O código Lua (com todas as mudanças especÃficas de <strong>eLua</strong>) está incluÃdo na árvore de origem e
+é, naturalmente, licenciado sob a mesma <a href="http://en.wikipedia.org/wiki/MIT_License">licença MIT de Lua.</a></p>
+<p>Há ainda outros (poucos) componentes com diferentes licenças hoje, em uso no código de <strong>eLua</strong>.
+Consulte o arquivo <strong>COPYING</strong> na distribuição fonte para maiores detalhes.</p>
+$$FOOTER$$
Modified: branches/eagle_mmc/doc/pt/platdependentmodules.html
===================================================================
--- branches/eagle_mmc/doc/pt/platdependentmodules.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/pt/platdependentmodules.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,9 +1,6 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
-
-<link rel="stylesheet" type="text/css" href="../style.css">
+<link rel="stylesheet" type="text/css" href="../style.css"></link>
</head>
<body style="background-color: rgb(255, 255, 255);">
<h3><a name="over"></a>Módulos Dependentes da Plataforma eLua</h3>
Modified: branches/eagle_mmc/doc/pt/platdepmodules.html
===================================================================
--- branches/eagle_mmc/doc/pt/platdepmodules.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/pt/platdepmodules.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,11 +1,6 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Produto</title>
-
-<link rel="stylesheet" type="text/css" href="../style.css">
</head>
-<body style="background-color: rgb(255, 255, 255);">
<h3><a name="over"></a>Módulos Dependentes da Plataforma eLua</h3>
<br>
<br>
Modified: branches/eagle_mmc/doc/pt/pwm_ref.html
===================================================================
--- branches/eagle_mmc/doc/pt/pwm_ref.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/pt/pwm_ref.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,42 +1,37 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Produto</title>
-
-<link rel="stylesheet" type="text/css" href="../style.css">
</head>
-<body style="background-color: rgb(255, 255, 255);">
<h3><a name="over"></a>pwm</h3>
<span style="font-weight: bold;"></span><br>
<p style="margin-bottom: 0in;"> <br>
</p>
<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">Permite que Lua use
-os blocos PWM para a CPU em questão.</font>
+os blocos PWM para a CPU em questão.</font>
</p>
<p style="margin-bottom: 0in;"> <br>
</p>
<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><strike><a name="setup"></a>[pwm.setup]</strike>(</font><font face="Bitstream Vera Sans Mono, sans-serif">pwm.setup( id,
-frequency, Active Cycle ) </font><font face="Bitstream Vera Sans Mono, sans-serif">
+frequency, Active Cycle ) </font><font face="Bitstream Vera Sans Mono, sans-serif">
Data = pwm.setup( id, frequency, duty ): configura o 'id' do bloco PWM para
-gerar a frequência especificada com o ciclo 'duty' especificado (duty é
-um número inteiro entre 0 e 100, indicando o percentual a ser
-utilizado). Ela retorna a frequência real configurada no bloco PWM.</font>
+gerar a frequência especificada com o ciclo 'duty' especificado (duty é
+um número inteiro entre 0 e 100, indicando o percentual a ser
+utilizado). Ela retorna a frequência real configurada no bloco PWM.</font>
</p>
<p style="margin-bottom: 0in;">
</p>
<p style="margin-bottom: 0in;"> <br>
</p>
<p style="margin-bottom: 0in;"> Aqui existe uma enorme
-mudança na proposta.
+mudança na proposta.
</p>
-<p style="margin-bottom: 0in;"> O Timer Clock e a frequência
-PWM "frame" seriam configurados na mesma função (.setup)
+<p style="margin-bottom: 0in;"> O Timer Clock e a frequência
+PWM "frame" seriam configurados na mesma função (.setup)
</p>
-<p style="margin-bottom: 0in;"> A função normal de
+<p style="margin-bottom: 0in;"> A função normal de
controle configuraria somente o ciclo ativo (.setcycle)
</p>
-<p style="margin-bottom: 0in;"> A função original .setup
-seria substituída por:
+<p style="margin-bottom: 0in;"> A função original .setup
+seria substituÃda por:
</p>
<p style="margin-bottom: 0in;"> <br>
</p>
@@ -45,12 +40,12 @@
</p>
<p style="margin-bottom: 0in;"> <a name="setcycle"></a>[pwm.setcycle(
id, active_cycle )]</p>
-<p style="margin-bottom: 0in;"><font face="Bitstream Vera Sans Mono, sans-serif"><a name="start"></a>[pwm.start()]
+<p style="margin-bottom: 0in;"><font face="Bitstream Vera Sans Mono, sans-serif"><a name="start"></a>[pwm.start()]
pwm.start( id ): inicia o 'id' do bloco PWM.</font>
</p>
<p style="margin-bottom: 0in;">
</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="stop"></a>[</font><font face="Bitstream Vera Sans Mono, sans-serif">pwm.stop()]
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="stop"></a>[</font><font face="Bitstream Vera Sans Mono, sans-serif">pwm.stop()]
</font><font face="Bitstream Vera Sans Mono, sans-serif">pwm.stop(
id ): finaliza o 'id' do bloco PWM.</font>
</p>
@@ -71,12 +66,12 @@
</p>
<p style="margin-bottom: 0in;"> <br>
</p>
-<p style="margin-bottom: 0in;"> Realmente é necessário
+<p style="margin-bottom: 0in;"> Realmente é necessário
existir
-.getclock ?? O clock é configurado pelo mesmo programa, é alterado repentinamente
-durante a operação, ..........
+.getclock ?? O clock é configurado pelo mesmo programa, é alterado repentinamente
+durante a operação, ..........
</p>
-<p style="margin-bottom: 0in;"> Caso fosse realmente necessário, poderia ser
+<p style="margin-bottom: 0in;"> Caso fosse realmente necessário, poderia ser
algo como pwm.gettimerclock(id) ou quem sabe (isso deve ser mais
discutido.....)
</p>
@@ -129,7 +124,7 @@
<br style="font-family: Helvetica,Arial,sans-serif;">
<br style="font-family: Helvetica,Arial,sans-serif;">
<span style="font-family: Helvetica,Arial,sans-serif;">
-
+
</span></big> <br>
<br style="font-family: Verdana;">
</body></html>
Modified: branches/eagle_mmc/doc/pt/refman.html
===================================================================
--- branches/eagle_mmc/doc/pt/refman.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/pt/refman.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,806 +1,18 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head><meta http-equiv="content-type" content="text/html; charset=ISO-8859-1"><meta http-equiv="Content-Language" content="en-us"><title>Product</title><link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);">
-<h3>eLua Modules Reference Manual
-</h3>
-<h2><a name="genericmodules"></a>eLua Generic
-Modules</h2>A Generic eLua Module is a module that can be used by a Lua program running on any of the <a href="status.html#platforms">supported eLua platforms</a>.<br>Write your code once and it is already automatically ported to the main platforms of the embedded world.<br><br><br><br><br><br><br><br><br><br><h3><a name="bitmodule"></a>bit</h3>
-Bitwise operations in eLua is implemented thru
-the BitLib library, from Reuben Thomas.<br>
-BitLib project is hosted at LuaForge on
-<a href="http://luaforge.net/projects/bitlib" target="_top">http://luaforge.net/projects/bitlib</a><br>
-<p class="MsoNormal" style="font-family: Verdana;"><a name="bit_bnot"></a>Res = bit.bnot( value )</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-unary negation
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-
-</p>
-<p class="MsoNormal" style="font-family: Verdana;"><a name="bit_band"></a> Res = bit.band( v1, v2, ... )</p>
-<p class="MsoNormal" style="font-family: Verdana;"><b>bitwise
-</b>"and"
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-
-</p>
-<p class="MsoNormal" style="font-family: Verdana;"><a name="bit_bor"></a> Res = bit.bor( v1, v2, ... )</p>
-<p class="MsoNormal" style="font-family: Verdana;"><span style="font-weight: bold;"> </span><b class="info" style="font-weight: bold;">bitwise</b><b class="info" style="font-weight: bold;">
-</b><span class="info" style="font-weight: bold;">"or"</span>
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-
-</p>
-<p class="MsoNormal" style="font-family: Verdana;"><a name="bit_bxor"></a> Res = bit.bxor( v1, v2, ... )</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-<b>bitwise</b><b> </b>"exclusive or"
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-
-</p>
-<p class="MsoNormal" style="font-family: Verdana;"><a name="bit_lshift"></a> Res = bit.lshift( value, pos )</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-shift "value" left "pos" positions.
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-
-</p>
-<p class="MsoNormal" style="font-family: Verdana;"><a name="bit_rshift"></a> Res = bit.rshift( value, pos )</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-shift "value" right "pos" positions. The sign is not propagated.
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-
-</p>
-<p class="MsoNormal" style="font-family: Verdana;"><a name="bit_arshift"></a> Res = bit.arshift( value, pos )</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-shift "value" right "pos" positions. The sign is propagated
-("arithmetic shift").
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-
-</p>
-<p class="MsoNormal" style="font-family: Verdana;"><a name="bit_bit"></a> Res = bit.bit( bitno )</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-a shortcut for bit.lshift( 1, bitno )
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-
-</p>
-<p class="MsoNormal" style="font-family: Verdana;"><a name="bit_set"></a> Res1, Res2, ... = bit.set( bitno, v1,
-v2, ... )</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-set the bit at position "bitno" in v1, v2, ... to 1.
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-
-</p>
-<p class="MsoNormal" style="font-family: Verdana;"><a name="bit_clear"></a> Res1, Res2, ... = bit.clear( bitno,
-v1, v2, ... )</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-set the bit at position "bitno"in v1, v2, ... to 0.
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-
-</p>
-<p class="MsoNormal" style="font-family: Verdana;"><a name="bit_isset"></a> Res = bit.isset( value, bitno )</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-returns true if bit at position "bitno" in "value" is 1, false
-otherwise.
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-
-</p>
-<p class="MsoNormal" style="font-family: Verdana;"><a name="bit_isclear"></a> Res = bit.isclear( value, bitno )</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-returns true if bit at position "bitno" in "value" is 0, false
-otherwise.
-</p>
-<br style="font-family: Verdana;">
-<br style="font-family: Verdana;">
-<br>
-<br>
-<br>
-<br>
-<br>
-<br>
-<br>
-<br>
-<h3><a name="cpumodule"></a>cpu</h3>
-<p class="MsoNormal" style="font-family: Verdana;"><br>
-</p>
-<p style="margin-bottom: 0in;"> </p>
-<font face="Bitstream Vera Sans Mono, sans-serif"><a name="cpu_write32"></a>write32( address, data ) : write
-the 32-bit data at the specified address</font>
-<p style="margin-bottom: 0in;"></p>
-<p style="margin-bottom: 0in;">
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="cpu_write16"></a>write16( address, data ) : write
-the 16-bit data at the specified address</font>
-</p>
-<p style="margin-bottom: 0in;">
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="cpu_write8"></a>write8( address, data ) : write the
-8-bit data at the specified address</font> <br>
-</p>
-<p style="margin-bottom: 0in;"><br>
-</p>
-<br>
-<font face="Bitstream Vera Sans Mono, sans-serif"><a name="cpu_read32"></a>Data = read32( address ) :
-reads 32-bit data from the specified address</font>
-<p style="margin-bottom: 0in;"></p>
-<p style="margin-bottom: 0in;">
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="cpu_read16"></a>Data = read16( address ) : reads
-16-bit data from the specified address</font>
-</p>
-<p style="margin-bottom: 0in;">
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="cpu_read8"></a>Data = read8( address ) : reads 8-bit
-data from the specified address</font></p>
-<p style="margin-bottom: 0in;"><br>
-</p>
-<br>
-<p style="margin-bottom: 0in;"><a name="cpu_disableinterrupts"></a>
-[cpu.disableinterrupts()] <font face="Bitstream Vera Sans Mono, sans-serif">cli(): disable
-CPU interrupts</font>
-</p>
-<p style="margin-bottom: 0in;"> <br>
-</p>
-<p style="margin-bottom: 0in;"> <br>
-</p>
-<p style="margin-bottom: 0in;"><a name="cpu_enableinterrupts"></a>
-[cpu.enableinterrupts()] <font face="Bitstream Vera Sans Mono, sans-serif">sei(): enable
-CPU interrupts</font>
-</p>
-<p style="margin-bottom: 0in;"> <br>
-</p>
-<p style="margin-bottom: 0in;">
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><br>
-</font></p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="cpu_clockfrequency"></a>[cpu.clockfrequency()]
-Clock = clock(): returns the CPU frequency</font>
-</p>
-<p style="margin-bottom: 0in;"> <br>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">Also, you can
-expose as many CPU constants (for example memory mapped registers)</font>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">as you want to
-this module. You might want to use this feature to access some </font>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">CPU memory areas
-(as defined in the CPU header files from the CPU support </font>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">package)
-directly from Lua. To do this, you'll need to define the </font>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">PLATFORM_CPU_CONSTANTS
-macro in the platform's platform_conf.h file </font>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">(src/platform/<platform
-name>/platform_conf.h). Include all your constants in a </font>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">_C(
-<constant name> ) definition, and then build your project.</font>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">For example,
-let's suppose that your CPU's interrupt controler has 3 memory</font>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">mapped
-registers: INT_REG_ENABLE, INT_REG_DISABLE and INT_REG_MASK. If you want</font>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">to access them
-from Lua, locate the header that defines the values of these</font>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">registers (I'll
-assume its name is "cpu.h") and add these lines to the</font>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">platform_conf.h:</font>
-</p>
-<p style="margin-bottom: 0in;"> <br>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">#include "cpu.h"</font>
-</p>
-<p style="margin-bottom: 0in;"> <br>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">#define
-PLATFORM_CPU_CONSTANTS\</font>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">_C(
-INT_REG_ENABLE ),\</font>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">_C(
-INT_REG_DISABLE ),\</font>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">_C( INT_REG_MASK
-)</font>
-</p>
-<p style="margin-bottom: 0in;"> <br>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">After this
-you'll be able to access the regs directly from Lua, like this:</font>
-</p>
-<p style="margin-bottom: 0in;"> <br>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">data = cpu.r32(
-cpu.INT_REG_ENABLE )</font>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">cpu.w32(
-cpu.INT_REG_ENABLE, data )</font>
-</p>
-<p style="margin-bottom: 0in;"> <br>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">For a
-"real-life" example, see the src/platform/lm3s/platform_conf.h file.</font>
-</p>
-<p style="margin-bottom: 0in;">
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">[uart.sendstring]
-uart.sendstr( id, str1, str2, ... ): this is similar to "uart.send",
-but its parameters are string. </font>
-</p>
-<p style="margin-bottom: 0in;"> <br>
-</p>
-<p style="margin-bottom: 0in;"> </p>
-<h3><a name="gpiomodule">pio</a></h3>
-<p class="MsoNormal" style="font-family: Verdana;">
-<b>pio</b></p><p class="MsoNormal" style="font-family: Verdana;">Programable Input Output Module</p><p class="MsoNormal" style="font-family: Verdana;">Some notes on PIO:</p><ul><li>pio: only
-some platform have internal pullups for the pio pins, while Cortex is
-the only platform that also provides pulldowns for its pios. However,
-in this case you're safe, as eLua will signal an error if you try to
-execute a pullup operatin on a platform that does not support it.</li></ul><p class="MsoNormal" style="font-family: Verdana;">
-</p>
-<br>
-<p class="MsoNormal" style="font-family: Verdana;"><a name="gpio_setpinvalue"></a> [pio.setpinvalue] pio.setpin(
-value, Pin1, Pin2 ... ): set the value to all the pins in the list
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
- to "value" (0 or 1).
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-
-</p>
-<p class="MsoNormal" style="font-family: Verdana;"><a name="gpio_setpinhigh"></a> [pio.setpinhigh] pio.set(
-Pin1, Pin2, ... ): set the value of all the pins in the list to 1.
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-
-</p>
-<p class="MsoNormal" style="font-family: Verdana;"><a name="gpio_getpinvalue"></a> [pio.getpinvalue] Val1, Val2,
-... = pio.get( Pin1, Pin2, ... ): reads one or more pins and returns
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
- their values (0 or 1).
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-
-</p>
-<p class="MsoNormal" style="font-family: Verdana;"><a name="gpio_setpinlow"></a> [pio.setpinlow] pio.clear(
-Pin1, Pin2, ... ): set the value of all the pins in the list to 0.
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-
-</p>
-<p class="MsoNormal" style="font-family: Verdana;"><a name="gpio_configpin"></a> [pio.configpin(pio.DIR, pio.DIR_INPUT)] pio.input( Pin1, Pin2, ... ): set the specified pin(s)
-as input(s).
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-[pio.configpin(pio.DIR, pio.DIR_OUTPUT)] pio.output( Pin1, Pin2, ...
-): set the specified pin(s) as output(s).
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-
-</p>
-<p class="MsoNormal" style="font-family: Verdana;"><a name="gpio_setportvalue"></a> [pio.setportvalue]
-pio.setport( value, Port1, Port2, ... ): set the value of all the ports
-in the
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
- list to "value".
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-
-</p>
-<p class="MsoNormal" style="font-family: Verdana;"><a name="gpio_getportvalue"></a> [pio.getportvalue] Val1,
-Val2, ... = pio.getport( Port1, Port2, ... ): reads one or more ports
-and
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
- returns their values.
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-
-</p>
-<p class="MsoNormal" style="font-family: Verdana;"><a name="gpio_getportname"></a> [pio.getportname]
-Port = pio.port( code ): return the physical port number associated
-with the given code. For example, "pio.port( pio.P0_20 )" will return
-0.
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-
-</p>
-<p class="MsoNormal" style="font-family: Verdana;"><a name="gpio_getpinnumber"></a> [pio.getpinnumber] Pin =
-pio.pin( code ): return the physical pin number associated with the
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-given code. For example, "pio.pin( pio.P0_20 )" will return 20.
-</p>
-<br>
-<a name="gpio_togglepin"></a>[pio.togglepin([Pin1],
-[Pin2], ...)]<br>
-<br>
-<a name="gpio_toogleport"></a>[pio.toggleport([Port1],
-[Port2], ...)]<br style="font-family: Verdana;">
-<br>
-Another idea (can be added to the above ?)<br>
-[pio.configport(pio.[FUNCTION], pio.MASK, [MASK])]<br>
-Ex:<br>
- pio.configpin(pio.DIR, pio.DIR_INPUT) (.DIR_OUTPUT)<br>
- pio.configpin(pio.PULL, pio.PULL_UP) (.PULL_DOWN,
-PULL_NO)<br style="font-family: Verdana;">
-<br>
-<p class="MsoNormal" style="font-family: Verdana;">
-[pio.configport(pio.DIR, pio.DIR_INPUT, [Port1], [Port2], ...)]
-pio.port_input( Port1, Port2, ... ): set the specified port(s) as
-input(s).
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-[pio.configport(pio.DIR, pio.DIR_OUTPUT, [Port1], [Port2], ...)]
-pio.port_output( Port1, Port2, ... ): set the specified port(s) as
-output(s).
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-[pio.configpin(pio.PULL, pio.PULL_UP, [Pin1], [Pin2], ...)]
-pio.pullup( Pin1, Pin2, ... ): enable internal pullups on the specified
-pins.Note that some CPUs might not provide this feature.
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-[pio.configpin(pio.PULL, pio.PULL_DOWN, [Pin1], [Pin2], ...)]
-pio.pulldown( Pin1, Pin2, ... ): enable internal pulldowns on the
-specified pins. Note that some CPUs might not provide this feature.
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-[pio.configpin(pio.PULL, pio.PULL_NO, [Pin1], [Pin2], ...)]
-pio.nopull( Pin1, Pin2, ... ): disable the pullups/pulldowns on the
-specifiedpins. Note that some CPUs might not provide this feature.
-</p>
-<br>
-<h3><a name="netmodule"></a>net</h3>
-<br>
-<h3><a name="pwmmodule"></a>pwm</h3>
-<span style="font-weight: bold;"></span><br>
-<p style="margin-bottom: 0in;"> <br>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">It allows Lua to
-use the PWM blocks on the target CPU.</font>
-</p>
-<p style="margin-bottom: 0in;"> <br>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><strike><a name="pwm_setup"></a>[pwm.setup]</strike>(</font><font face="Bitstream Vera Sans Mono, sans-serif">pwm.setup( id,
-frequency, Active Cycle ) </font><font face="Bitstream Vera Sans Mono, sans-serif">
-Data = pwm.setup( id, frequency, duty ): sets the PWM block 'id' to
-generate the specified frequency with the specified duty cycle (duty is
-an integer number from 0 to 100, specifying the duty cycle in
-percents). It returns the actual frequency set on the PWM block.</font>
-</p>
-<p style="margin-bottom: 0in;">
-</p>
-<p style="margin-bottom: 0in;"> <br>
-</p>
-<p style="margin-bottom: 0in;"> Here there is a bigger
-change on the proposal.
-</p>
-<p style="margin-bottom: 0in;"> The Timer Clock and the
-PWM "frame" frequency would be set up in the same function (.setup)
-</p>
-<p style="margin-bottom: 0in;"> The normal control
-function would only set the active cicle (.setcycle)
-</p>
-<p style="margin-bottom: 0in;"> The original .setup
-function would then be replaced by:
-</p>
-<p style="margin-bottom: 0in;"> <br>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">[pwm.setup( id,
-tmrclock, pwm_frequency )</font> ]<br>
-</p>
-<p style="margin-bottom: 0in;"> <a name="pwm_setcycle"></a>[pwm.setcycle(
-id, active_cycle )]</p>
-<p style="margin-bottom: 0in;"><font face="Bitstream Vera Sans Mono, sans-serif"><a name="pwm_start"></a>[pwm.start()]
-pwm.start( id ): start the PWM block 'id'.</font>
-</p>
-<p style="margin-bottom: 0in;">
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="pwm_stop"></a>[</font><font face="Bitstream Vera Sans Mono, sans-serif">pwm.stop()]
-</font><font face="Bitstream Vera Sans Mono, sans-serif">pwm.stop(
-id ): stop the PWM block 'id'.</font>
-</p>
-<br>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="pwm_setclock"></a>Data = pwm.setclock( id, clock ):
-set the base clock of the PWM block 'id' to</font>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">the given clock.
-In returns the actual clock set on the PWM block.</font>
-</p>
-<p style="margin-bottom: 0in;"> <br>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">[</font><font face="Bitstream Vera Sans Mono, sans-serif"><strike>pwm.getclock</strike>]
-</font><font face="Bitstream Vera Sans Mono, sans-serif">Data
-= pwm.getclock( id ): returns the base clock of the PWM block 'id'.</font>
-</p>
-<p style="margin-bottom: 0in;">
-</p>
-<p style="margin-bottom: 0in;"> <br>
-</p>
-<h3><a name="spimodule"></a>spi</h3>
-<span style="font-weight: bold;"></span><br>
-<big><span style="font-family: Helvetica,Arial,sans-serif;"></span><font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big><a name="spi_setup"></a>Actual_clock = spi.setup( id,
-spi.MASTER | spi.SLAVE, clock, cpol, cpha,</big></font><span style="font-family: Helvetica,Arial,sans-serif;">
-</span><br style="font-family: Helvetica,Arial,sans-serif;">
-<span style="font-family: Helvetica,Arial,sans-serif;">
- </span><font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>databits):
-set the SPI interface with the given parameters, returns the clock</big></font><span style="font-family: Helvetica,Arial,sans-serif;">
-</span><br style="font-family: Helvetica,Arial,sans-serif;">
-<span style="font-family: Helvetica,Arial,sans-serif;">
- </span><font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>that
-was set for the interface.</big></font><span style="font-family: Helvetica,Arial,sans-serif;">
-</span><br style="font-family: Helvetica,Arial,sans-serif;">
-<span style="font-family: Helvetica,Arial,sans-serif;">
-
-</span><br style="font-family: Helvetica,Arial,sans-serif;">
-<font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big><a name="spi_select"></a>spi.select(
-</big></font><font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>id</big></font><font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>
-): sets the selected spi as active (sets the SS line of the given
-interface).</big></font><span style="font-family: Helvetica,Arial,sans-serif;">
-</span><br style="font-family: Helvetica,Arial,sans-serif;">
-<font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big> </big></font><span style="font-family: Helvetica,Arial,sans-serif;">
-</span><br style="font-family: Helvetica,Arial,sans-serif;">
-<font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big><a name="spi_unselect"></a>spi.unselect(
-id ): clears the SS line of the given interface.</big></font><span style="font-family: Helvetica,Arial,sans-serif;">
-</span><br style="font-family: Helvetica,Arial,sans-serif;">
-<font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big> </big></font><span style="font-family: Helvetica,Arial,sans-serif;">
-</span><br style="font-family: Helvetica,Arial,sans-serif;">
-<font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big><a name="spi_send"></a>spi.send(
-id, Data1, Data2, ... ): sends all the data to the specified SPI</big></font><span style="font-family: Helvetica,Arial,sans-serif;">
-</span><br style="font-family: Helvetica,Arial,sans-serif;">
-<span style="font-family: Helvetica,Arial,sans-serif;">
- </span><font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>interface.</big></font><span style="font-family: Helvetica,Arial,sans-serif;">
-</span><br style="font-family: Helvetica,Arial,sans-serif;">
-<span style="font-family: Helvetica,Arial,sans-serif;">
-
-</span><br style="font-family: Helvetica,Arial,sans-serif;">
-<font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big><a name="spi_sendrecv"></a>[</big></font><font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>spi.sendrecv(</big></font><font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>id,
-Out1, Out2, ...</big></font><font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>)]
-</big></font><font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>In1,
-In2, ... = spi.send_recv( id, Out1, Out2, ... ): sends all the "out"
-bytes</big></font><span style="font-family: Helvetica,Arial,sans-serif;"> </span><font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>to
-the specified SPI interface and returts the data read after each sent
-byte.</big></font><span style="font-family: Helvetica,Arial,sans-serif;">
-</span><br style="font-family: Helvetica,Arial,sans-serif;">
-<br style="font-family: Helvetica,Arial,sans-serif;">
-<font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>Returning
-several values in this blocking way would not complicate some queued
-send implementations ? (ok, this could be another function :)</big></font><span style="font-family: Helvetica,Arial,sans-serif;">
-</span><br style="font-family: Helvetica,Arial,sans-serif;">
-<br style="font-family: Helvetica,Arial,sans-serif;">
-<font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>Sending multiple data/chars in a single
-call and not in
-a table argument does not allow the data to be built in run time
-(without some string massage, of course :)</big></font><br>
-<br>
-<br>
-<br>
-</big>
-<h3><a name="sysmodule"></a>sys</h3>
-<br>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="sys_platform"></a>[sys.platform()]
-pd.platform(): returns the platform name (f.e. LM3S)</font>
-</p>
-<p style="margin-bottom: 0in;">
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="sys_mcu"></a>[sys.mcu()]
-pd.cpu(): returns the CPU name (f.e. LM3S8962)</font>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="sys_cpu"></a>[sys.cpu()]
-would return ARM Cortex M3 in this case.....</font></p>
-<p style="margin-bottom: 0in;"><font face="Bitstream Vera Sans Mono, sans-serif"><br>
-</font></p>
-<font face="Bitstream Vera Sans Mono, sans-serif"> <a name="sys_board"></a>[sys.board()]</font><font face="Bitstream Vera Sans Mono, sans-serif">
-pd.board(): returns the CPU board (f.e. EK-LM3S8962)</font>
-<p style="margin-bottom: 0in;"> <br>
-</p>
-<h3><a name="term_termmodule">term</a></h3>
- Terminal support
-<p> <a name="term_clear"></a>[term.clear]
-term.clrscr(): clear the screen </p>
-<p> <br>
-<a name="term_cleareol"></a>[term.cleareol]
-term.clreol(): clear from the current cursor position to the end of the
-line </p>
-<p> </p>
-<p><a name="term_moveto"></a> [term.moveto]
-term.gotoxy( x, y ): position the cursor at the given coordinates<br>
-</p>
-<br>
-<p><a name="term_moveup"></a> [term.moveup]
-term.up( delta ): move the cursor up "delta" lines </p>
-<p> </p>
-<p><a name="term_movedown"></a> [term.movedown]
-term.down( delta ): move the cursor down "delta" lines </p>
-<p> </p>
-<p><a name="term_moveleft"></a> [term.moveleft]
-term.left( delta ): move the cursor left "delta" lines </p>
-<p> <br>
-<a name="term_moveright"></a>[term.moveright] term.right(
-delta ): move the cursor right "delta" lines </p>
-<p> </p>
-<p><a name="term_getlinecount"></a>
-[term.getlinecount] Lines = term.lines(): returns the number of lines </p>
-<p> </p>
-<p><a name="term_getcolcount"></a>
-[term.getcolcount] Cols = term.cols(): returns the number of columns </p>
-<p> </p>
-<br>
-<p><a name="term_printstr"></a> [term.printstr]
-term.putstr( s1, s2, ... ): writes the specified string(s) to the
-terminal<br>
-</p>
-<p> </p>
-<p> [term.printchar] term.put( c1, c2, ... ): writes the
-specified character(s) to the terminal </p>
-<p> </p>
-<p><a name="term_getx"></a> [term.getx] Cx =
-term.cursorx(): return the cursor X position </p>
-<p> </p>
-<p> <a name="term_gety"></a>[term.gety] Cy =
-term.cursory(): return the cursor Y position </p>
-<p> </p>
-<p> <font size="2"><a name="term_inputchar"></a>[term.inputchar]
-c = term.getch( term.WAIT | term.NOWAIT ): returns a char read from the
-</font> </p>
-<font size="2"> terminal.</font>
-<br style="font-family: Verdana;">
-<br>
-<br>
-<h3><a name="tmr_tmrmodule"></a>tmr</h3>
-<span style="font-weight: bold;"></span><big><br>
-</big>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">It allows Lua to
-execute timer specific operations (delay, read timer value,</font>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">start timer, get
-time difference).</font></p><p style="margin-bottom: 0in;"><font face="Bitstream Vera Sans Mono, sans-serif">Some notes on timers:</font></p><ul><li>timers: from all the platforms on which eLua runs, only
-the Luminary Cortex CPUs has rock solid 32-bit timers. You can do
-pretty much everything you need with them. All the other platforms have
-16-bit timers, which imposes some limits on the range of delays you can
-achieve with them. Make sure to use tmr.mindelay(id) and
-tmr.maxdelay(id) to check the actual resolution of your timers, and
-adapt your code accordingly. To 'compensate' for this, it's not
-possible to change the base timer frequency on the Cortex CPUs, but it
-is possible on most other platforms :) So be sure to also check the
-result of tmr.setclock(id)</li><li>also, when using timers,
-remember that if you're using XMODEM and/or the "term" module, TMR0 is
-used by both of them. So, if you change the TMR0 base clock in your
-code, be sure to restore the original setting before returning to the
-shell. You can change this static timer assignment by modifying
-src/main.c. It might also be possible to change it dynamically in the
-future, although I see little use for this.</li><li>PWM: the
-Cortex CPUs have 6 PWM channels, but channels 0/1, 2/3 and 4/5
-respectively share the same base clock setting. So, when you're
-changing the base clock for channel 1, you're also changing the base
-clock for channel 0; if channel 0 was already running, you won't like
-what will happen next. This time no eLua function can save you, you
-simply need you know your CPU architecture.</li></ul><p style="margin-bottom: 0in;">
-</p>
-<p style="margin-bottom: 0in;"> <br>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="tmr_delay"></a>tmr.delay( id, delay ): uses timer
-'id' to wait for 'delay' us.</font>
-</p>
-<p style="margin-bottom: 0in;"> <br>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><span style="font-style: italic;"><a name="tmr_read"></a></span>Data
-= tmr.read( id ): reads the value of timer 'id'. The returned value is </font>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">platform
-dependent.</font>
-</p>
-<p style="margin-bottom: 0in;">
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><span style="font-style: italic;"><a name="tmr_start"></a></span>Data
-= tmr.start( id ): start the timer 'id', and also returns its value at</font>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">the moment of
-start. The returned value is platform dependent.</font>
-</p>
-<p style="margin-bottom: 0in;">
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="tmr_diff"></a>diff
-= tmr.diff( id, end, start ): returns the time difference (in us)
-between</font>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">the timer values
-'end' and 'start' (obtained from calling tmr.start or</font>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">tmr.read). The
-order of end/start is irrelevant. </font>
-</p>
-<p style="margin-bottom: 0in;">
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="tmr_mindelay"></a>Data = tmr.mindelay( id ): returns
-the minimum delay (in us ) that can be </font>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">achieved by
-calling the tmr.delay function. If the return value is 0, the </font>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">platform layer
-is capable of executing sub-microsecond delays.</font>
-</p>
-<p style="margin-bottom: 0in;">
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="tmr_maxdelay"></a>Data = tmr.maxdelay( id ): returns
-the maximum delay (in us) that can be</font>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">achieved by
-calling the tmr.delay function.</font>
-</p>
-<p style="margin-bottom: 0in;">
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="tmr_setclock"></a>Data = tmr.setclock( id, clock ):
-sets the clock of the given timer. Returns the</font>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">actual clock set
-for the timer.</font>
-</p>
-<p style="margin-bottom: 0in;">
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="tmr_getclock"></a>Data = tmr.getclock( id ): return
-the clock of the given timer.</font>
-</p>
-<br>
-<br>
-<br>
-<br>
-<br>
-<h3><a name="uartmodule"></a>uart</h3>
-
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="uart_setup"></a><span style="font-weight: bold;">uart.setup(</span></font><font style="font-weight: bold;" face="Bitstream Vera Sans Mono, sans-serif"> id, baud,
-databits, </font>
-</p><p style="margin-bottom: 0in; font-weight: bold;"> <font face="Bitstream Vera Sans Mono, sans-serif">uart.PARITY_EVEN
-| uart.</font><font face="Bitstream Vera Sans Mono, sans-serif">PARITY</font><font face="Bitstream Vera Sans Mono, sans-serif">_ODD | uart.</font><font face="Bitstream Vera Sans Mono, sans-serif">PARITY</font><font face="Bitstream Vera Sans Mono, sans-serif">_NONE, </font>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><span style="font-weight: bold;">uart.STOPBITS_1
-| uart.STOPBITS_1_5 | uart.STOPBITS_2
-)</span></font></p>
-<p style="margin-bottom: 0in;"><font face="Bitstream Vera Sans Mono, sans-serif"><span style="font-weight: bold;"></span> Set the UART interface with the given
-parameters.</font></p><p style="margin-bottom: 0in;"><font face="Bitstream Vera Sans Mono, sans-serif"> Returns the actual baud rate that was set for the UART.</font>
-</p>
-
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><br>
-</font></p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="uart_send"></a></font><font face="Bitstream Vera Sans Mono, sans-serif"><span style="font-weight: bold;">uart.send( id,
-Data1, Data2, ... )</span></font></p><p style="margin-bottom: 0in;"><font face="Bitstream Vera Sans Mono, sans-serif"><span style="font-weight: bold;"></span> Send all the data to the specified UART interface.</font>
-</p>
-
-
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><br>
-</font></p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="uart_recv"></a></font><font face="Bitstream Vera Sans Mono, sans-serif">uart.recv(</font><font face="Bitstream Vera Sans Mono, sans-serif"> id,
-uart.TIMEOUT_NO | <strike>uart.TIMEOUT_INFINITE</strike> |
-timeout )</font><font face="Bitstream Vera Sans Mono, sans-serif">
- </font><font face="Bitstream Vera Sans Mono, sans-serif">Data =
-uart.recv( id, uart.NO_TIMEOUT | uart.INF_TIMEOUT | timeout )</font></p>
-<p style="margin-bottom: 0in;"><font face="Bitstream Vera Sans Mono, sans-serif"> Reads a byte from the
-specified UART interface.</font></p>
-<p style="margin-bottom: 0in;"></p>
-<p style="margin-bottom: 0in;">
-</p>
-<h2><a name="platdepmodules"></a>eLua Platform
-Dependent
-Modules</h2>A Platform Dependent eLua Module is a module that runs only on one or on a few <a href="status.html#platforms">supported eLua platforms</a>.<br>These
-modules make use of specifical devices and features offered by some
-kits and allow eLua aplications to make the best use of the external
-hardware on your platforms.<br><h3><a name="adcmodule"></a>adc - Analog to Digital Conversion Module</h3><span style="font-weight: bold;">Currently runs on:</span> LM3Sxxxx<br><br> The ADC module handles the Analog to Digital Conversion Peripherals.<br><br><br><a name="adc_sample"></a><span style="font-weight: bold;">adc.sample(channel_id)</span><br> Generate one processed sample.<br><br><br><a name="adc_getsamples"></a><span style="font-weight: bold;">adc.getsamples(channel_id,
-[count])</span><br> Request <span style="font-style: italic;">count</span> samples from the buffer.<br> if singular, an
-integer is returned. if multiple, a table of integers is returned. If
-<span style="font-style: italic;">count</span> is either zero or omitted, all available samples are returned.<br><br><br><a name="adc_maxval"></a><span style="font-weight: bold;">adc.maxval(channel_id)</span><br> Returns the largest integer one can expect fromr this channel on a given platform (based on bit depth).<br><br><br><a name="adc_samplesready"></a><span style="font-weight: bold;">adc.samplesready(channel_id)<br></span> Returns the number of samples waiting in the buffer.<br><br><br><a name="adc_dataready"></a><span style="font-weight: bold;">adc.dataready(channel_id)<br></span> If running in non-blocking mode, this will indicate if all of the
-samples requested from the last sample or <br>burst have been acquired and
-are waiting in the buffer.<br><br><br><a name="adc_setmode"></a><span style="font-weight: bold;">adc.setmode(channel_id,
-mode)<br></span> <span style="font-style: italic;">mode</span> 0 sets blocking mode. adc.getsamples will wait for
-requested samples to be captured before returning.<br> <span style="font-style: italic;">mode</span> 1 sets non-blocking mode<br><br><br><a name="adc_setsmoothing"></a><span style="font-weight: bold;">adc.setsmoothing(channel_id, length)<br></span> Set the length of the smoothing filter.<br> This must be a power of 2 (maximum = 128)<br><br><br><a name="adc_getsmoothing"></a><span style="font-weight: bold;">adc.getsmoothing(channel_id)<br></span> Get the current smoothing length in use.<br><br><br><a name="adc_burst"></a><span style="font-weight: bold;">adc.burst(
-channel_id, count, timer_id, frequency)<br></span> Request that <span style="font-style: italic;">count</span> samples be converted from <span style="font-style: italic;">channel_id</span>, using <span style="font-style: italic;">timer_id</span> at <span style="font-style: italic;">frequency.<br></span> <span style="font-style: italic;">count </span>must be greater than zero and a power of 2<br><br><br>
-<h3><a name="dispmodule"></a>disp</h3>
-<span style="font-weight: bold;">Currently runs on:</span> LM3Sxxxx<br><br> The disp module handles the RIT OLED display usage on Luminary Micro Cortex-M3 boards<br>
-<p class="MsoNormal"></p><p class="MsoNormal"><a name="disp_init"></a><span style="font-weight: bold;">
-disp.init( freq )</span></p><p class="MsoNormal">freq specifies the SSI Clock Frequency to be used.<br><br>This function initializes the SSI interface to the OLED display and configures the SSD1329 controller on the panel.<br></p><br><p class="MsoNormal"><a name="disp_enable"></a>
-<span style="font-weight: bold;">disp.enable()</span> </p>
-<p class="MsoNormal">Enable the SSI component of the OLED display driver.<br></p><p class="MsoNormal">freq specifies the SSI Clock Frequency to be used.<br>This function initializes the SSI interface to the OLED display.</p><p class="MsoNormal">
-</p>
-<p class="MsoNormal"><a name="disp_disable"></a>
-<span style="font-weight: bold;">disp.disable()</span> </p>
-<p class="MsoNormal"> <br>
-</p>
-<p class="MsoNormal"> <a name="disp_on"></a><span style="font-weight: bold;">disp.on()</span>
-</p>
-<p class="MsoNormal"> Turns on the OLED display.<br> This function will turn on the OLED display, causing it to display the contents of its internal frame buffer.<br><br>
-</p>
-<p class="MsoNormal"><a name="disp_off"></a>
-<span style="font-weight: bold;">disp.off</span>()</p><p class="MsoNormal">Turns off the OLED display<br>This
-function will turn off the OLED display. This will stop the
-scanning of the panel and turn off the on-chip DC-DC converter,
-preventing damage to the panel due to burn-in (it has similar
-characters to a CRT in this respect).<br><br></p>
-<p class="MsoNormal"><a name="disp_clear"></a>
-<span style="font-weight: bold;">disp.clear()</span></p><p class="MsoNormal">Clears the OLED display.<br>This function will clear the display RAM. All pixels in the display will be turned off.<br></p>
- <a name="disp_print"></a><span style="font-weight: bold;">disp.print( str, x, y, gray )</span><br><br>Displays a string on the OLED display.<br><br>Calling Arguments:<br>str is a string to be displayed.<br>x is the horizontal position to display the string, specified in columns from the left edge of the display.<br>y is the vertical position to display the string, specified in rows from the top edge of the display.<br>gray is the 4-bit gray scale (intensity) value to be used for displayed text. <br><br>This
-function will draw a string on the display. Only the ASCII
-characters between 32 (space) and 126 (tilde) are supported;
-other characters will result in random data being draw on the
-display (based on whatever appears before/after the font in
-memory). The font is mono-spaced, so characters such as ``i'' and
-``l'' have more white space around them than characters such as ``m''
-or ``w''.<br>If the drawing of the string reaches the right edge of the
-display, no more characters will be drawn. Therefore, special
-care is not required to avoid supplying a string that is ``too long''
-to display.<br><br>Because the OLED display packs 2 pixels of data in a single byte, the<br>parameter \e ulX must be an even column number (for example, 0, 2, 4, and<br>so on).<br><br>
-<br>
-<p class="MsoNormal"><a name="disp_draw"></a>
-<span style="font-weight: bold;">disp.draw( img, x, y, withd, height, gray )</span></p><p class="MsoNormal">Displays an image on the OLED display.<br><br>img a pointer to the string data representing a rit format image to display.<br>x is the horizontal position to display the string, specified in columns from the left edge of the display.<br>y is the vertical position to display the string, specified in rows from the top edge of the display.<br>width is the width of the image, specified in columns.<br>height is the height of the image, specified in rows.<br><br>This
-function will display a bitmap graphic on the display. Because of
-the format of the display RAM, the starting column x and the number of
-columns y must be an integer multiple of two.<br>The image data is
-organized with the first row of image data appearing left to
-right, followed immediately by the second row of image data. Each
-byte contains the data for two columns in the current row, with
-the leftmost column being contained in bits 7:4 and the rightmost
-column being contained in bits 3:0.<br>For example, an image six
-columns wide and seven scan lines tall would be arranged as
-follows (showing how the twenty one bytes of the image would appear on
-the display):<br><br>Because the OLED display packs 2 pixels of data in
-a single byte, the parameter x must be an even column number (for
-example, 0, 2, 4, and so on).<span style="font-weight: bold;"></span></p><p class="MsoNormal"><span style="font-family: Courier New;"> +-------------------+-------------------+-------------------+</span><br style="font-family: Courier New;"><span style="font-family: Courier New;">
-| Byte
-0 |
-Byte 1
-| Byte
-2 |</span><br style="font-family: Courier New;"><span style="font-family: Courier New;"> +---------+---------+---------+---------+---------+---------+</span><br style="font-family: Courier New;"><span style="font-family: Courier New;"> | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 |</span><br style="font-family: Courier New;"><span style="font-family: Courier New;"> +---------+---------+---------+---------+---------+---------+</span><br style="font-family: Courier New;"><span style="font-family: Courier New;">
-| Byte
-3 |
-Byte 4
-| Byte
-5 |</span><br style="font-family: Courier New;"><span style="font-family: Courier New;"> +---------+---------+---------+---------+---------+---------+</span><br style="font-family: Courier New;"><span style="font-family: Courier New;"> | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 |</span><br style="font-family: Courier New;"><span style="font-family: Courier New;"> +---------+---------+---------+---------+---------+---------+</span><br style="font-family: Courier New;"><span style="font-family: Courier New;">
-| Byte
-6 |
-Byte 7
-| Byte
-8 |</span><br style="font-family: Courier New;"><span style="font-family: Courier New;"> +---------+---------+---------+---------+---------+---------+</span><br style="font-family: Courier New;"><span style="font-family: Courier New;"> | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 |</span><br style="font-family: Courier New;"><span style="font-family: Courier New;"> +---------+---------+---------+---------+---------+---------+</span><br style="font-family: Courier New;"><span style="font-family: Courier New;">
-| Byte
-9 |
-Byte 10 |
-Byte 11 |</span><br style="font-family: Courier New;"><span style="font-family: Courier New;"> +---------+---------+---------+---------+---------+---------+</span><br style="font-family: Courier New;"><span style="font-family: Courier New;"> | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 |</span><br style="font-family: Courier New;"><span style="font-family: Courier New;"> +---------+---------+---------+---------+---------+---------+</span><br style="font-family: Courier New;"><span style="font-family: Courier New;">
-| Byte 12
-| Byte 13
-| Byte 14 |</span><br style="font-family: Courier New;"><span style="font-family: Courier New;"> +---------+---------+---------+---------+---------+---------+</span><br style="font-family: Courier New;"><span style="font-family: Courier New;"> | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 |</span><br style="font-family: Courier New;"><span style="font-family: Courier New;"> +---------+---------+---------+---------+---------+---------+</span><br style="font-family: Courier New;"><span style="font-family: Courier New;">
-| Byte 15
-| Byte 16
-| Byte 17 |</span><br style="font-family: Courier New;"><span style="font-family: Courier New;"> +---------+---------+---------+---------+---------+---------+</span><br style="font-family: Courier New;"><span style="font-family: Courier New;"> | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 |</span><br style="font-family: Courier New;"><span style="font-family: Courier New;"> +---------+---------+---------+---------+---------+---------+</span><br style="font-family: Courier New;"><span style="font-family: Courier New;">
-| Byte 18
-| Byte 19
-| Byte 20 |</span><br style="font-family: Courier New;"><span style="font-family: Courier New;"> +---------+---------+---------+---------+---------+---------+</span><br style="font-family: Courier New;"><span style="font-family: Courier New;"> | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 |</span><br style="font-family: Courier New;"><span style="font-family: Courier New;"> +---------+---------+---------+---------+---------+---------+</span><span style="font-weight: bold;"></span></p><p class="MsoNormal"><span style="font-weight: bold;"></span></p><p class="MsoNormal"><span style="font-weight: bold;"></span> </p>
-</body></html>
\ No newline at end of file
+<html><head>
+</head>
+<h3>The reference manual</h3>
+<p>The <b>eLua</b> reference manual presents in details all the modules that can be used from a Lua program running inside <b>eLua</b>. It doesn't cover the
+standard Lua libraries, as the <a target="_blank" href="http://www.lua.org/manual/5.1/">Lua reference manual</a> already does a very good job at this.
+Instead, it covers <b>eLua</b>-specific modules (most of which are linked with the <a href="arch_platform.html">platform interface</a>) and some generic
+"3rd party" modules that are included in <b>eLua</b> by default. There are two types of modules in <b>eLua</b>, both of which are presented
+in this section:
+<ul>
+ <li><b>generic modules</b>: they are available on all platforms and should behave the same on all platforms.</li>
+ <li><b>platform-depedent modules</b>: they can be found only on specific platforms. Using them sacrifices portability, but gives access to platform
+ internals that aren't covered by the generic modules (for example specific hardware features).</b>
+</ul></p>
+<p>Remember that in order to use a module (generic or not) in <b>eLua</b> you must first include it in your <b>eLua</b> binary image, check
+<a href="building.html#confmodules">here</a> for instructions on how to do this.</p>
+<p>
+</body></html>
Added: branches/eagle_mmc/doc/pt/refman_dep.html
===================================================================
--- branches/eagle_mmc/doc/pt/refman_dep.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/pt/refman_dep.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,6 @@
+$$HEADER$$
+<h3>Reference manual - platform dependent modules</h3>
+<p>This part of the reference manual presents the platform specifics in <b>eLua</b> (see <a href="arch_overview.html">here</a> for more information about platform
+specific modules).</p>
+$$FOOTER$$
+
Added: branches/eagle_mmc/doc/pt/refman_gen.html
===================================================================
--- branches/eagle_mmc/doc/pt/refman_gen.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/pt/refman_gen.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,6 @@
+$$HEADER$$
+<h3>Reference manual - generic modules</h3>
+<p>This part of the reference manual presents the generic modules in <b>eLua</b> (see <a href="arch_overview.html">here</a> for more information about generic
+modules).</p>
+$$FOOTER$$
+
Modified: branches/eagle_mmc/doc/pt/spi_ref.html
===================================================================
--- branches/eagle_mmc/doc/pt/spi_ref.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/pt/spi_ref.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,49 +1,44 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Produto</title>
-
-<link rel="stylesheet" type="text/css" href="../style.css">
</head>
-<body style="background-color: rgb(255, 255, 255);">
<h3><a name="over"></a>spi</h3>
<span style="font-weight: bold;"></span><br>
<big><span style="font-family: Helvetica,Arial,sans-serif;"></span><font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big><a name="setup"></a>Actual_clock = spi.setup( id,
spi.MASTER | spi.SLAVE, clock, cpol, cpha,</big></font><span style="font-family: Helvetica,Arial,sans-serif;">
</span><br style="font-family: Helvetica,Arial,sans-serif;">
<span style="font-family: Helvetica,Arial,sans-serif;">
- </span><font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>databits):
-configura a interface SPI com os parâmetros fornecidos, retorna o clock</big></font><span style="font-family: Helvetica,Arial,sans-serif;">
+ </span><font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>databits):
+configura a interface SPI com os parâmetros fornecidos, retorna o clock</big></font><span style="font-family: Helvetica,Arial,sans-serif;">
</span><br style="font-family: Helvetica,Arial,sans-serif;">
<span style="font-family: Helvetica,Arial,sans-serif;">
- </span><font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>que
+ </span><font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>que
foi configurado para a interface.</big></font><span style="font-family: Helvetica,Arial,sans-serif;">
</span><br style="font-family: Helvetica,Arial,sans-serif;">
<span style="font-family: Helvetica,Arial,sans-serif;">
-
+
</span><br style="font-family: Helvetica,Arial,sans-serif;">
<font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big><a name="select"></a>spi.select(
</big></font><font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>id</big></font><font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>
-): configura a SPI selecionada como ativa (configura a linha SS da interface em questão).</big></font><span style="font-family: Helvetica,Arial,sans-serif;">
+): configura a SPI selecionada como ativa (configura a linha SS da interface em questão).</big></font><span style="font-family: Helvetica,Arial,sans-serif;">
</span><br style="font-family: Helvetica,Arial,sans-serif;">
-<font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big> </big></font><span style="font-family: Helvetica,Arial,sans-serif;">
+<font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big> </big></font><span style="font-family: Helvetica,Arial,sans-serif;">
</span><br style="font-family: Helvetica,Arial,sans-serif;">
<font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big><a name="unselect"></a>spi.unselect(
-id ): inicializa a linha SS da interface em questão.</big></font><span style="font-family: Helvetica,Arial,sans-serif;">
+id ): inicializa a linha SS da interface em questão.</big></font><span style="font-family: Helvetica,Arial,sans-serif;">
</span><br style="font-family: Helvetica,Arial,sans-serif;">
-<font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big> </big></font><span style="font-family: Helvetica,Arial,sans-serif;">
+<font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big> </big></font><span style="font-family: Helvetica,Arial,sans-serif;">
</span><br style="font-family: Helvetica,Arial,sans-serif;">
<font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big><a name="send"></a>spi.send(
id, Data1, Data2, ... ): envia todos os dados para a interface SPI especificada.</big></font><span style="font-family: Helvetica,Arial,sans-serif;">
</span><br style="font-family: Helvetica,Arial,sans-serif;">
<span style="font-family: Helvetica,Arial,sans-serif;">
- </span><font style="font-family: Helvetica,Arial,sans-serif;" size="2"></font><span style="font-family: Helvetica,Arial,sans-serif;">
+ </span><font style="font-family: Helvetica,Arial,sans-serif;" size="2"></font><span style="font-family: Helvetica,Arial,sans-serif;">
</span><br style="font-family: Helvetica,Arial,sans-serif;">
<span style="font-family: Helvetica,Arial,sans-serif;">
-
+
</span><br style="font-family: Helvetica,Arial,sans-serif;">
<font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big><a name="sendrecv"></a>[</big></font><font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>spi.sendrecv(</big></font><font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>id,
-Out1, Out2, ...</big></font><font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>)]
+Out1, Out2, ...</big></font><font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>)]
</big></font><font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>In1,
In2, ... = spi.send_recv( id, Out1, Out2, ... ): envia todos os "out"
bytes</big></font><span style="font-family: Helvetica,Arial,sans-serif;"> </span><font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>para
@@ -51,12 +46,12 @@
</span><br style="font-family: Helvetica,Arial,sans-serif;">
<br style="font-family: Helvetica,Arial,sans-serif;">
<font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>Retornando
-diversos valôres dessa forma, facilitaria algumas futuras implementações ? (ok, isso poderia ser uma outra função :)</big></font><span style="font-family: Helvetica,Arial,sans-serif;">
+diversos valôres dessa forma, facilitaria algumas futuras implementações ? (ok, isso poderia ser uma outra função :)</big></font><span style="font-family: Helvetica,Arial,sans-serif;">
</span><br style="font-family: Helvetica,Arial,sans-serif;">
<br style="font-family: Helvetica,Arial,sans-serif;">
-<font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>Enviando múltiplos data/chars em uma única
-chamada e não usando
-uma tabela como argumento, evita que os dados sejam montados em tempo de execução
+<font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>Enviando múltiplos data/chars em uma única
+chamada e não usando
+uma tabela como argumento, evita que os dados sejam montados em tempo de execução
(claro que sem menhum string de mensagem :)</big></font><br>
<br>
<br>
@@ -91,7 +86,7 @@
<br style="font-family: Helvetica,Arial,sans-serif;">
<br style="font-family: Helvetica,Arial,sans-serif;">
<span style="font-family: Helvetica,Arial,sans-serif;">
-
+
</span></big> <br>
<br style="font-family: Verdana;">
</body></html>
Modified: branches/eagle_mmc/doc/pt/status.html
===================================================================
--- branches/eagle_mmc/doc/pt/status.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/pt/status.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,418 +1,542 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
-
-<link rel="stylesheet" type="text/css" href="../style.css">
-</head>
-<body style="background-color: rgb(255, 255, 255);">
-<h3>Current Status of Platforms and Modules Supported</h3>
-<p>As already stated, eLua allows you to run Lua completely on
-the
-microcontroller. A fast-growing set of complementary modules is also
-provided, for Lua programming eLua's generic (portable) peripherals. </p>
-<p>The following features are ready or being implemented:</p>
-<ul>
-<li>a (mostly) platform independent peripheral library (PIO,
-UART, PWM, SPI, TMR, ADC, NET, I2C...)</li>
-<li>a very low footprint embedded rom file system, easy to port
-to different types of memory chips and other storage devices</li>
-<li>a small FAT rw file system layer for SD cards.</li>
-<li>an embedded editor, to edit Lua programs directly via a
-serial connection or other input devices</li>
-<li>a minimal "shell" (for file operations, environment
-configuration and other facilities)</li>
-<li>network support</li>
-<li>an embedded http server</li>
-<li>Terminal / Console over Ethernet</li>
-</ul>
-<p>Porting eLua to another compatible platform should be as easy
-and
-painless as possible. Currently this is restricted to platforms for
-which the gcc+newlib combo is available. This might change in the
-future, but please not that this is not a priority of the project at
-this point.</p>
-<p>Also, the Lua "core" comes in two flavors: "regular Lua"
-(using
-floating point as the number type) and "integer Lua" (using integers).
-We'll add more about this in a future tutorial
-about Lua. For now, it's enough to say that "regular Lua" will be able
-to perform floating point operations (but will be slower because the
-floating point operations will be emulated in software on the MCU),
-while "integer Lua" will only be able to perform operations with
-integer numbers (but support for fixed and even floating point can be
-added with separate modules) and thus will be faster.</p>
-<p></p>
-<h3>Symbol Legends</h3>
-
-<table style="width: 325px; height: 169px;" class="table_center">
+$$HEADER$$
+<a name="platforms" /><h3>eLua platforms and modules status</h3>
+<p>O status atual de <b>eLua</b> pode ser representado pela relação de
+plataformas suportadas, pela lista de módulos disponÃveis para cada uma
+delas e ainda pelos módulos em desenvolvimento.<br />
+Estas informações estão apresentadas a seguir, organizadas em tabelas
+que usam a seguinte notação
+gráfica:</p>
+<table style="width: 325px;" class="table_center">
<tbody>
<tr>
-<th style="text-align: center;">Symbol</th>
-<th style="text-align: center;">Meaning</th>
+<th style="text-align: center;">SÃmbolo</th>
+<th style="text-align: center;">Significado</th>
</tr>
<tr>
-<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
-<td style="text-align: left;">Implemented and tested</td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: left;">Implementado e Testado</td>
</tr>
<tr>
-<td style="text-align: center;"><img src="../wb_img/yellowled.png"></td>
-<td style="text-align: left;">Implemented, not tested</td>
+<td style="text-align: center;"><img src="images/stat_not_tested.png" alt="Status: not tested" /></td>
+<td style="text-align: left;">Implementado, não testado</td>
</tr>
<tr>
-<td style="text-align: center;"><img src="../wb_img/ksame.png"></td>
-<td style="text-align: left;">Not yet implemented</td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: left;">Ainda não implementado</td>
</tr>
<tr>
-<td style="text-align: center;"><img src="../wb_img/agt_action_fail1.png"></td>
-<td style="text-align: left;">Not applicable</td>
+<td style="text-align: center;"><img src="images/stat_not_applicable.png" alt="Status: not applicable" /></td>
+<td style="text-align: left;">Não se aplica</td>
</tr>
</tbody>
-</table><br><br>
-<h3>Platforms x Modules Supported</h3>The following table shows the status of <span style="font-weight: bold;">eLua</span>'s modules implementation by
-platform.<br><br>
-<table style="text-align: left;">
+</table>
+
+<br /><br />
+<p>A lista de CPUs/Plataformas atualmente suportadas por <b>eLua</b> é
+apresentada a seguir:</p>
+<table style="text-align: left; width: 620px;" class="table_center">
<tbody>
<tr>
-<th>Module</th>
-<th rowspan="2">PIO</th>
-<th rowspan="2">SPI</th>
-<th rowspan="2">UART</th>
-<th rowspan="2">TMR</th>
-<th rowspan="2">PWM</th>
-<th rowspan="2">NET</th>
-<th rowspan="2">CPU</th>
-<th rowspan="2">ADC</th>
+ <th style="text-align: left;">CPU</th>
+ <th style="text-align: center;">Arquitetura</th>
+ <th style="text-align: center;">Plataforma</th>
+ <th style="text-align: center;">Placas Suportadas</th>
+ <th style="text-align: center;">Status</th>
</tr>
-<tr><td style="color: rgb(255, 102, 0);">MCU</td>
-</tr><tr>
-<td style="color: rgb(255, 102, 0);">LM3S8962</td>
-<td style="text-align: center;"><img style="width: 16px; height: 16px;" alt="Implemented" src="../wb_img/agt_action_success.png"></td>
-<td style="text-align: center;"><img style="width: 16px; height: 16px;" alt="Not Tested" src="../wb_img/yellowled.png"></td>
-<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
-<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
-<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
-<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
-<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
-<td style="text-align: center;"><img src="../wb_img/yellowled.png"> </td>
+<tr>
+ <td><a href="http://www.luminarymicro.com/products/LM3S8962.html">LM3S8962</a></td>
+ <td>Cortex-M3</td>
+ <td style="color: rgb(255, 102, 0);">lm3s</td>
+ <td><a href="http://www.luminarymicro.com/products/lm3s8962_can_ethernet_evaluation_kit.html">EKx-LM3S8962</a></td>
+ <td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
</tr>
<tr>
-<td style="color: rgb(255, 102, 0);">LM3S6965</td>
-<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
-<td style="text-align: center;"><img src="../wb_img/yellowled.png"></td>
-<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
-<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
-<td style="text-align: center;"><img src="../wb_img/yellowled.png"></td>
-<td style="text-align: center;"><img src="../wb_img/yellowled.png"></td>
-<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
-<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
+ <td><a href="http://www.luminarymicro.com/products/lm3s6965.html">LM3S6965</a></td>
+ <td>Cortex-M3</td>
+ <td style="color: rgb(255, 102, 0);">lm3s</td>
+ <td><a href="http://www.luminarymicro.com/products/lm3s6965_ethernet_evaluation_kit.html">EKx-LM3S6965</a></td>
+ <td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
</tr>
<tr>
-<td style="color: rgb(255, 102, 0);">i386</td>
-<td style="text-align: center;"><img src="../wb_img/agt_action_fail1.png"></td>
-<td style="text-align: center;"><img src="../wb_img/agt_action_fail1.png"></td>
-<td style="text-align: center;"><img src="../wb_img/agt_action_fail1.png"></td>
-<td style="text-align: center;"><img src="../wb_img/ksame.png"></td>
-<td style="text-align: center;"><img style="height: 16px; width: 16px;" alt="Not Implemented" src="../wb_img/agt_action_fail1.png"></td>
-<td style="text-align: center;"><img src="../wb_img/ksame.png"></td>
-<td style="text-align: center;"><img src="../wb_img/ksame.png"></td>
-<td style="text-align: center;"><img style="height: 16px; width: 16px;" alt="Not Implemented" src="../wb_img/agt_action_fail1.png"></td>
+ <td><a href="http://www.luminarymicro.com/products/lm3s6918.html">LM3S6918</a></td>
+ <td>Cortex-M3</td>
+ <td style="color: rgb(255, 102, 0);">lm3s</td>
+ <td><a href="http://www.micromint.com/index.php/SBC/eagle-100.html">Eagle 100</a></td>
+ <td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
</tr>
<tr>
-<td style="color: rgb(255, 102, 0);">AT91SAM7X256</td>
-<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
-<td style="text-align: center;"><img src="../wb_img/ksame.png"></td>
-<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
-<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
-<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
-<td style="text-align: center;"><img src="../wb_img/ksame.png"></td>
-<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
-<td style="text-align: center;"><img src="../wb_img/ksame.png"></td>
+ <td><a href="http://www.atmel.com/dyn/products/Product_card.asp?part_id=3755">AT91SAM7X256</a></td>
+ <td>ARM7TDMI</td>
+ <td style="color: rgb(255, 102, 0);">at91sam7x</td>
+ <td><a href="http://www.olimex.com/dev/sam7-ex256.html">SAM7-EX256</a></td>
+ <td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
</tr>
<tr>
-<td style="color: rgb(255, 102, 0);">AT91SAM7X512</td>
-<td style="text-align: center;"><img src="../wb_img/yellowled.png"></td>
-<td style="text-align: center;"><img src="../wb_img/ksame.png"></td>
-<td style="text-align: center;"><img src="../wb_img/yellowled.png"></td>
-<td style="text-align: center;"><img src="../wb_img/yellowled.png"></td>
-<td style="text-align: center;"><img src="../wb_img/yellowled.png"></td>
-<td style="text-align: center;"><img src="../wb_img/ksame.png"></td>
-<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
-<td style="text-align: center;" valign="undefined"><img src="../wb_img/ksame.png"></td>
+ <td><a href="http://www.atmel.com/dyn/products/Product_card.asp?part_id=4104">AT91SAM7X512</a></td>
+ <td>ARM7TDMI</td>
+ <td style="color: rgb(255, 102, 0);">at91sam7x</td>
+ <td>None</td>
+ <td style="text-align: center;"><img src="images/stat_not_tested.png" alt="Status: not tested" /></td>
</tr>
<tr>
-<td style="color: rgb(255, 102, 0);">STR912FW44</td>
-<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
-<td style="text-align: center;"><img src="../wb_img/ksame.png"></td>
-<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
-<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
-<td style="text-align: center;"><img src="../wb_img/ksame.png"></td>
-<td style="text-align: center;"><img src="../wb_img/ksame.png"></td>
-<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
-<td style="text-align: center;" valign="undefined"><img src="../wb_img/ksame.png"></td>
+ <td><a href="http://www.intel.com">i386 (generic)</a></td>
+ <td>x86</td>
+ <td style="color: rgb(255, 102, 0);">i386</td>
+ <td>PCs/emulators</td>
+ <td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
</tr>
<tr>
-<td style="color: rgb(255, 102, 0);">LPC2888</td>
-<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
-<td style="text-align: center;"><img src="../wb_img/ksame.png"></td>
-<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
-<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
-<td style="text-align: center;"><img src="../wb_img/agt_action_fail1.png"></td>
-<td style="text-align: center;"><img src="../wb_img/ksame.png"></td>
-<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
-<td style="text-align: center;" valign="undefined"><img src="../wb_img/ksame.png"></td>
+ <td><a href="http://www.st.com/mcu/devicedocs-STR912FAW44-101.html">STR912FAW44</a></td>
+ <td>ARM966E-S</td>
+ <td style="color: rgb(255, 102, 0);">str9</td>
+ <td><a href="http://www.hitex.com/index.php?id=383">STR9-comStick</a></td>
+ <td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
</tr>
<tr>
-<td style="color: rgb(255, 102, 0);">STR711FR2</td>
-<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
-<td style="text-align: center;"><img src="../wb_img/ksame.png"></td>
-<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"> </td>
-<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"> </td>
-<td style="text-align: center;"><img src="../wb_img/yellowled.png"></td>
-<td style="text-align: center;"> <img style="height: 16px; width: 16px;" alt="Not Implemented" src="../wb_img/agt_action_fail1.png"></td>
-<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"> </td>
-<td style="text-align: center;"><img src="../wb_img/ksame.png"></td>
+ <td><a href="http://www.standardics.nxp.com/microcontrollers/to/pip/LPC2880FET180.html">LPC2888</a></td>
+ <td>ARM7TDMI</td>
+ <td style="color: rgb(255, 102, 0);">lpc288x</td>
+ <td><a href="http://www.olimex.com/dev/lpc-h2888.html">LPC-H2888</a></td>
+ <td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
</tr>
<tr>
-<td style="color: rgb(255, 102, 0);">AVR32</td>
-<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
-<td style="text-align: center;"><br>
-</td>
-<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"> </td>
-<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"> </td>
-<td style="text-align: center;"><img src="../wb_img/yellowled.png"></td>
-<td style="text-align: center;"> <br>
-</td>
-<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"> </td>
-<td style="text-align: center;"><br>
-</td>
+ <td><a href="http://www.st.com/mcu/devicedocs-STR711FR2.html">STR711FR2</a></td>
+ <td>ARM7TDMI</td>
+ <td style="color: rgb(255, 102, 0);">str7</td>
+ <td><a href="http://www.sctec.com.br/content/view/101/30/">MOD711</a></td>
+ <td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
</tr>
<tr>
-<td style="color: rgb(255, 102, 0);">STM32</td>
-<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
-<td style="text-align: center;"><br>
-</td>
-<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"> </td>
-<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"> </td>
-<td style="text-align: center;"><img src="../wb_img/yellowled.png"></td>
-<td style="text-align: center;"></td>
-<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"> </td>
-<td style="text-align: center;"><img src="../wb_img/ksame.png"></td>
+ <td><a href="http://www.atmel.com/dyn/products/product_card.asp?part_id=4117">AT32UC3A0512</a></td>
+ <td>AVR32</td>
+ <td style="color: rgb(255, 102, 0);">avr32</td>
+ <td><a href="http://www.atmel.com/dyn/Products/tools_card.asp?tool_id=4114">ATEVK1100</a></td>
+ <td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
</tr>
+<tr>
+ <td><a href="http://www.st.com/mcu/devicedocs-STM32F103ZE-110.html">STM32F103ZE</a></td>
+ <td>Cortex-M3</td>
+ <td style="color: rgb(255, 102, 0);">stm32</td>
+ <td><a href="http://www.st.com/mcu/contentid-100-110-STM3210E_EVAL.html">STM3210E-EVAL</a></td>
+ <td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+</tr>
+<tr>
+ <td><a href="http://www.st.com/mcu/devicedocs-STM32F103RE-110.html">STM32F103RE</a></td>
+ <td>Cortex-M3</td>
+ <td style="color: rgb(255, 102, 0);">stm32</td>
+ <td><a href="http://www.futurlec.com/ET-STM32_Stamp.shtml">ET-STM32 Stamp</a></td>
+ <td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+</tr>
</tbody>
</table>
-<br>
-<br>
-<br>
-<br>
-<br>
-<h3><a name="roadmap"></a>Status of features
-& roadmap</h3>
-<p>The following table shows the status of some existent and
-planned eLua
-features. </p>
-<p><br>
-</p>
-<table style="text-align: left; width: 672px; height: 691px;" class="table_center">
+
+<br /><br />
+<p>A tabela a seguir apresenta uma lista de Módulos Genéricos para <b>eLua</b>
+e suas fases de desenvolvimento.</p>
+<table style="text-align: left; width: 620px;" class="table_center">
<tbody>
<tr>
-<th style="text-align: left;">eLua Features</th>
+<th style="text-align: left;">Nome</th>
+<th style="text-align: center;">Descrição</th>
<th style="text-align: center;">Status</th>
</tr>
<tr>
-<td style="text-align: left;">Full Lua interpreter
-running on targets</td>
-<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
+<td style="color: rgb(255, 102, 0);">pio</td>
+<td>Programmable Input/Output</td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
</tr>
<tr>
-<td>Various Lua scripts examples running properly</td>
-<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
+<td style="color: rgb(255, 102, 0);">tmr</td>
+<td>timers</td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
</tr>
<tr>
-<td style="text-align: left;">Choose floating point
-or integer Lua</td>
-<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
+<td style="color: rgb(255, 102, 0);">pwm</td>
+<td>Pulse Width Modulation</td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
</tr>
<tr>
-<td style="text-align: left;">XMODEM transfer over
-UART</td>
-<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
+<td style="color: rgb(255, 102, 0);">uart</td>
+<td>Universal Asynchronous Receiver Transmitter</td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
</tr>
<tr>
-<td style="text-align: left;">Embedded ROM (Flash)
-file
-system</td>
-<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
+<td style="color: rgb(255, 102, 0);">spi</td>
+<td>Serial Peripheral Interface</td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
</tr>
+<tr><td style="color: rgb(255, 102, 0);">net</td>
+<td>TCP/IP networking</td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+</tr>
<tr>
-<td style="text-align: left;">Terminal / Console
-over UART or Ethernet</td>
-<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
+<td style="color: rgb(255, 102, 0);">adc</td>
+<td>Analog to Digital Converter</td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
</tr>
<tr>
-<td style="text-align: left;">eLua command shell</td>
-<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
+<td style="color: rgb(255, 102, 0);">cpu</td>
+<td>low level system access</td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
</tr>
<tr>
-<td style="text-align: left;">eLua complete
-interrupt support</td>
-<td style="text-align: center;"><img src="../wb_img/ksame.png"></td>
+<td style="color: rgb(255, 102, 0);">pd</td>
+<td>platform data</td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
</tr>
<tr>
-<td style="text-align: left;">eLua "memory limiting"
-mode</td>
-<td style="text-align: center;"><img src="../wb_img/yellowled.png"></td>
+<td style="color: rgb(255, 102, 0);">term</td>
+<td>ANSI terminal access</td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
</tr>
<tr>
-<td style="text-align: left;">FAT File System layer
-for mmc/sd cards</td>
-<td style="text-align: center;"><img src="../wb_img/yellowled.png"></td>
+<td style="color: rgb(255, 102, 0);">bit</td>
+<td>bitwise operations</td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
</tr>
<tr>
-<td style="text-align: left;">Embedded R/W file
-system</td>
-<td style="text-align: center;">Partially
-implemented and tested</td>
+<td style="color: rgb(255, 102, 0);">pack</td>
+<td>pack/unpack binary data</td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
</tr>
<tr>
-<td style="text-align: left;">eLua FP module (for
-integer Lua)</td>
-<td style="color: rgb(255, 102, 0); text-align: center;"><img src="../wb_img/ksame.png">
-</td>
+<td style="color: rgb(255, 102, 0);">cmp</td>
+<td>analog comparator</td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
</tr>
<tr>
-<td style="text-align: left;">Embedded text editor</td>
-<td style="text-align: center;"><img src="../wb_img/ksame.png"></td>
+<td style="color: rgb(255, 102, 0);">i2c</td>
+<td>I2C bus access module</td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
</tr>
<tr>
-<td style="text-align: left;">Lua debugging on target</td>
-<td style="text-align: center;"><img src="../wb_img/ksame.png"></td>
+<td style="color: rgb(255, 102, 0);">cnt</td>
+<td>event counter</td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
</tr>
<tr>
-<td style="text-align: left;">GUI/IDE interface for
-eLua</td>
-<td style="text-align: center;"><img src="../wb_img/ksame.png"></td>
+<td style="color: rgb(255, 102, 0);">can</td>
+<td>Controller Area Network</td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
</tr>
-<tr>
-<td style="text-align: left;">GUI eLua build
-configuration tool<br>
-</td>
-<td style="text-align: center;"><img src="../wb_img/ksame.png">
-</td>
-</tr><tr><td align="undefined" valign="undefined">Embedded http web server</td><td style="text-align: center;" valign="undefined"><img src="../wb_img/agt_action_success.png"></td></tr>
</tbody>
</table>
-<br>
-<br>
-<br>
-<table style="text-align: left; width: 677px; height: 403px;" class="table_center">
+
+<br /><br />
+<p>A tabela a seguir apresenta a relação entre um modulo e sua implementação em cada
+plataforma.</p>
+<table style="text-align: left; width: 620px;" class="table_center">
<tbody>
<tr>
-<th style="text-align: left;">Generic Multi-Platform
-Peripheral Modules</th>
-<th style="text-align: center;">Status</th>
+<th>Módulo</th>
+<th rowspan="2">pio</th>
+<th rowspan="2">spi</th>
+<th rowspan="2">uart</th>
+<th rowspan="2">tmr</th>
+<th rowspan="2">pwm</th>
+<th rowspan="2">net</th>
+<th rowspan="2">cpu</th>
+<th rowspan="2">adc</th>
+<th rowspan="2">pd</th>
+<th rowspan="2">term</th>
+<th rowspan="2">bit</th>
+<th rowspan="2">pack</th>
</tr>
-<tr>
-<td style="text-align: left;">PIO - Programable
-Input / Output</td>
-<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
+<tr><td style="color: rgb(255, 102, 0);">MCU</td>
+</tr><tr>
+<td style="color: rgb(255, 102, 0);">LM3S8962</td>
+<td style="text-align: center;"><img style="width: 16px; height: 16px;" src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img style="width: 16px; height: 16px;" src="images/stat_not_tested.png" alt="Status: not tested" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_not_tested.png" alt="Status: not tested" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
</tr>
<tr>
-<td>TMR - Timers</td>
-<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
+<td style="color: rgb(255, 102, 0);">LM3S6965</td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_not_tested.png" alt="Status: not tested" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_not_tested.png" alt="Status: not tested" /></td>
+<td style="text-align: center;"><img src="images/stat_not_tested.png" alt="Status: not tested" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
</tr>
<tr>
-<td style="text-align: left;">PWM - Pulse Width
-Modulation</td>
-<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
+<td style="color: rgb(255, 102, 0);">LM3S6918</td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_not_tested.png" alt="Status: not tested" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_not_applicable.png" alt="Status: not applicable" /></td>
+<td style="text-align: center;"><img src="images/stat_not_tested.png" alt="Status: not tested" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_not_tested.png" alt="Status: not tested" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+
</tr>
<tr>
-<td style="text-align: left;">UART - Universal
-Assincronous Rx Tx</td>
-<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
+<td style="color: rgb(255, 102, 0);">i386</td>
+<td style="text-align: center;"><img src="images/stat_not_applicable.png" alt="Status: not applicable" /></td>
+<td style="text-align: center;"><img src="images/stat_not_applicable.png" alt="Status: not applicable" /></td>
+<td style="text-align: center;"><img src="images/stat_not_applicable.png" alt="Status: not applicable" /></td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img style="height: 16px; width: 16px;" src="images/stat_not_applicable.png" alt="Status: not applicable" /></td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img style="height: 16px; width: 16px;" src="images/stat_not_applicable.png" alt="Status: not applicable" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+
</tr>
<tr>
-<td style="text-align: left;">SPI - Serial
-Programable Interface</td>
-<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
+<td style="color: rgb(255, 102, 0);">AT91SAM7X256</td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+
</tr>
<tr>
-<td style="text-align: left;">CMP - Analog
-Comparator</td>
-<td style="text-align: center;"><img src="../wb_img/yellowled.png"></td>
+<td style="color: rgb(255, 102, 0);">AT91SAM7X512</td>
+<td style="text-align: center;"><img src="images/stat_not_tested.png" alt="Status: not tested" /></td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img src="images/stat_not_tested.png" alt="Status: not tested" /></td>
+<td style="text-align: center;"><img src="images/stat_not_tested.png" alt="Status: not tested" /></td>
+<td style="text-align: center;"><img src="images/stat_not_tested.png" alt="Status: not tested" /></td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;" ><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+
</tr>
<tr>
-<td style="text-align: left;">I2C </td>
-<td style="text-align: center;"><img src="../wb_img/ksame.png"></td>
+<td style="color: rgb(255, 102, 0);">STR912FAW44</td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;" ><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+
</tr>
<tr>
-<td style="text-align: left;">CNT - Event Counter
-</td>
-<td style="text-align: center;"><img src="../wb_img/yellowled.png"></td>
+<td style="color: rgb(255, 102, 0);">LPC2888</td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_not_applicable.png" alt="Status: not applicable" /></td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;" ><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+
</tr>
<tr>
-<td style="text-align: left;">CAN</td>
-<td style="text-align: center;"><img src="../wb_img/ksame.png"></td>
+<td style="color: rgb(255, 102, 0);">STR711FR2</td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /> </td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /> </td>
+<td style="text-align: center;"><img src="images/stat_not_tested.png" alt="Status: not tested" /></td>
+<td style="text-align: center;"><img src="images/stat_not_applicable.png" alt="Status: not applicable" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /> </td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+
</tr>
<tr>
-<td style="text-align: left;">NET -
-Ethernet module</td>
-<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
+<td style="color: rgb(255, 102, 0);">AT32UC3A0512</td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /> </td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /> </td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /> </td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+
</tr>
+<tr><td style="color: rgb(255, 102, 0);">STM32F103ZE</td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /> </td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /> </td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /> </td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+
+</tr>
+<tr><td style="color: rgb(255, 102, 0);">STM32F103RE</td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /> </td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /> </td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /> </td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+
+</tr>
+
</tbody>
</table>
-<br>
-<br>
-<br>
-<table style="width: 681px; height: 68px;" class="table_center">
+
+<br /><br />
+<p>Algumas plataformas possuem módulos especÃficos e suas implementações
+estão apresentadas na tabela a seguir. Pra compreender melhor a diferença
+entre módulos genéricos e módulos especÃficos para uma plataforma, por favor
+consulte a seção <a href="arch_overview.html">Arquitetura de eLua</a>.</p>
+<table style="width: 620px; margin-bottom: 10px;" class="table_center">
<tbody>
<tr>
-<th style="text-align: left;">Platform-Dependent
-Peripheral Modules</th>
-<th>Status</th>
+ <th style="text-align: left;">Nome</th>
+ <th style="text-align: center;">Descrição</th>
+ <th style="text-align: center;">Placas</th>
+ <th style="text-align: center;">Status</th>
</tr>
<tr>
-<td style="text-align: left;">DISP - RIT
-OLED Display Support for LM3Sxxxx</td>
-<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
+ <td style="color: rgb(255, 102, 0);">disp</td>
+ <td>OLED display support</td>
+ <td>EKx-LM3S8962<br>EKx-LM3S6965</td>
+ <td><img src="images/stat_ok.png" alt="Status: OK" /></td>
</tr>
-<tr>
-<td align="undefined" valign="undefined">LM3S
-- Luminary Micro kits onboard devices support (Leds, Buttons, ...)</td>
-<td style="text-align: center;" valign="undefined"><img src="../wb_img/agt_action_success.png"></td>
-</tr>
</tbody>
</table>
-<br>
-<br>
-<br>
-<table style="width: 680px; height: 389px;" class="table_center">
-<tbody>
+
+<br /><br />
+<a name="roadmap" /><h3>Status das funcionalidades e planejamento futuro</h3>
+<p>A tabela a seguir apresenta o status de algumas funcionalidades
+existentes e planejadas de<b>eLua</b>.</p>
+<table style="text-align: left; width: 620px;" class="table_center">
+<tbody><tr>
+<th style="text-align: left;">Funcionalidades</th>
+<th style="text-align: center;">Status</th>
+</tr>
<tr>
-<th style="text-align: left;">Functional Abstraction
-Auxiliary Modules</th>
-<th>Status</th>
+<td style="text-align: left;">Interpretador Lua completo rodando embarcado</td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
</tr>
<tr>
-<td style="text-align: left;">GPS - NMEA0183
-Sentences parsing and command handling</td>
-<td style="text-align: center;"><img src="../wb_img/yellowled.png"></td>
+<td>Diversos exemplos de código rodando sem erros</td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
</tr>
<tr>
-<td align="undefined" valign="undefined">PID
-- Proportional, Integrative & Derivative Control</td>
-<td style="text-align: center;" valign="undefined"><img src="../wb_img/ksame.png"></td>
+<td style="text-align: left;">Lua com Ponto Flutuante ou Inteiros</td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
</tr>
<tr>
-<td align="undefined" valign="undefined">LCD
-- Liquid Crystal Display support</td>
-<td style="text-align: center;" valign="undefined"><img src="../wb_img/ksame.png"></td>
+<td style="text-align: left;">Protocolo XMODEM via UART</td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
</tr>
<tr>
-<td align="undefined" valign="undefined">ROT
-- Rotary Switch & Encoder support</td>
-<td style="text-align: center;" valign="undefined"><img src="../wb_img/ksame.png"></td>
-</tr><tr><td align="undefined" valign="undefined">CHDK - Interfacing with Canon cameras also running Lua under <a href="http://chdk.wikia.com/" target="_top">CHKD</a></td><td style="text-align: center;" valign="undefined"><img src="../wb_img/yellowled.png"></td></tr><tr><td align="undefined" valign="undefined">DISP - External text & graphics displays</td><td style="text-align: center;" valign="undefined"><img src="../wb_img/ksame.png"></td></tr><tr><td align="undefined" valign="undefined">FUZZ - Fuzzy Logic Control</td><td style="text-align: center;" valign="undefined"><img src="../wb_img/ksame.png"></td></tr><tr><td align="undefined" valign="undefined">HUM - Humity Sensors over SPI, UART, I2C, PIO, ....</td><td style="text-align: center;" valign="undefined"><img src="../wb_img/ksame.png"></td></tr><tr><td align="undefined" valign="undefined">TMP - Temperature Sensors over SPI, UART, I2C, PIO, ....</td><td style="text-align: center;" valign="undefined"><img src="../wb_i!
mg/ksame.png"></td></tr><tr><td align="undefined" valign="undefined">BAR - Pressure Sensors over SPI, UART, I2C, PIO, ....</td><td style="text-align: center;" valign="undefined"><img src="../wb_img/ksame.png"></td></tr><tr><td align="undefined" valign="undefined">X10 - X10 Protocol support for X10 Devices Mapping & Control</td><td style="text-align: center;" valign="undefined"><img src="../wb_img/ksame.png"></td></tr><tr><td align="undefined" valign="undefined">MCP - Magnetic Compass abstraction</td><td style="text-align: center;" valign="undefined"><img src="../wb_img/ksame.png"></td></tr><tr><td align="undefined" valign="undefined">PS2 - Play Station 2 Joystick interfacing support</td><td style="text-align: center;" valign="undefined"><img src="../wb_img/ksame.png"></td></tr>
+<td style="text-align: left;">Embedded ROM (Flash) File System</td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+</tr>
+<tr>
+<td style="text-align: left;">Terminal / Console via UART e Ethernet</td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+</tr>
+<tr>
+<td style="text-align: left;">eLua Command Shell</td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+</tr>
+<tr>
+<td style="text-align: left;">Suporte completo à interrupções</td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+</tr>
+<tr>
+<td style="text-align: left;"><a href="arch_ltr.html">eLua LTR (Lua Tiny RAM) patch</a></td>
+<td style="text-align: center;"><img src="images/stat_ok.png" alt="Status: OK" /></td>
+</tr>
+<tr>
+<td style="text-align: left;">FAT File System para cartões MMC/SD</td>
+<td style="text-align: center;"><img src="images/stat_not_tested.png" alt="Status: not tested" /></td>
+</tr>
+<tr>
+<td style="text-align: left;">R/W File System</td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+</tr>
+<tr>
+<td style="text-align: left;">Módulo FP em eLua (para Lua com Inteiros)</td>
+<td style="color: rgb(255, 102, 0); text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" />
+</td>
+</tr>
+<tr>
+<td style="text-align: left;">Editor de texto embarcado</td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+</tr>
+<tr>
+<td style="text-align: left;">Lua debugging (remoto/local)</td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+</tr>
+<tr>
+<td style="text-align: left;">Interface GUI/IDE para eLua</td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+</tr>
+<tr>
+<td style="text-align: left;">Utilitário de configuração do build de eLua (web e local)<br></td>
+<td style="text-align: center;"><img src="images/stat_not_implemented.png" alt="Status: not implemented" /></td>
+</tr>
+<tr>
+<td style="text-align: left;" >Servidor HTTP embarcado</td>
+<td style="text-align: center;" ><img src="images/stat_ok.png" alt="Status: OK" /></td></tr>
</tbody>
-</table><br><br>If you need a module for a specific device support or logic & modeling abstraction, don't hesitate to suggest it in our <a href="https://lists.berlios.de/mailman/listinfo/elua-dev" target="_top">eLua User's and Developers List</a>. You may have one ready before you would imagine :)<br><br><br><br>
-</body></html>
\ No newline at end of file
+</table>
+
+<br /><br /><br /><br /><br /><br /><br />
+$$FOOTER$$
+
Modified: branches/eagle_mmc/doc/pt/sys_ref.html
===================================================================
--- branches/eagle_mmc/doc/pt/sys_ref.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/pt/sys_ref.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,11 +1,6 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Produto</title>
-
-<link rel="stylesheet" type="text/css" href="../style.css">
</head>
-<body style="background-color: rgb(255, 255, 255);">
<h3><a name="over"></a>sys</h3>
<br>
<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="platform"></a>[sys.platform()]
Modified: branches/eagle_mmc/doc/pt/tc_386.html
===================================================================
--- branches/eagle_mmc/doc/pt/tc_386.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/pt/tc_386.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,49 +1,28 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
+$$HEADER$$
+<p>Inicialmente, a idéia de um "i386" cross "compiler" em Linux parece estranha. Afinal, você já roda Linux numa plataforma compatível com i386. Porém, o compilador as vezes segue certos caminhos misteriosos junto com o sistema operacional onde este está rodando (veja por exemplo <a href="http://wiki.osdev.org/GCC_Cross-Compiler">esta página</a> para alguns sintomas possíveis). E ainda, você deseja usar uma NewLib, e não uma Libc, e ainda adaptar o máximo possível o seu ambiente às suas necessidades. Portanto, este tutorial irá mostrá-lo como fazer isso.</p>
+<p><strong>AVISO: Não sou um especialista no processo de construção de uma GCC/newlib/binutils. Tenho certeza de que existem melhores formas de realizar o que estou descrevendo aqui, no entanto, apresento apenas uma maneira rápida de construir um toolchain, não tenho nenhuma intenção de me aprofundar neste processo. Se você acha que, o que fiz aqui está errado, impreciso ou, simplesmente, escandalosamente feio, não hesite em <a href="overview.html#contacts">contactar-me</a> e farei as correções necessárias. E claro, este tutorial é fornecido sem qualquer tipo de garantia.</strong></p>
-<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);"><h3><a name="title" href="http://www.eluaproject.net/en/Building_GCC_for_i386" class="local">Building GCC for i386</a></h3>
-
- <div class="content">
+<h2>› Pré-requisitos</h2>
+<p>Para construir seu toolchain você precisará de:</p>
-<p>At first, the idea of an i386 "cross" compiler under Linux seems
-strange. After all, you're already running Linux on a i386 compatible
-architecture. But the compiler is sometimes tied in misterious ways
-with the operating system it's running on (see for example <a href="http://wiki.osdev.org/GCC_Cross-Compiler">this page</a>
-for some possible symptoms). And after all, you want to use Newlib, not
-libc, and to customize your development environment as much as
-possible. This tutorial will show you how to do that.</p>
+<ul>
-<p><strong>DISCLAIMER: I'm by no means a specialist in the
-GCC/newlib/binutils compilation process. I'm sure that there are better
-ways to accomplish what I'm describing here, however I just wanted a
-quick and dirty way to build a toolchain, I have no intention in
-becoming too intimate with the build process. If you think that what I
-did is wrong, innacurate, or simply outrageously ugly, feel free to <a href="http://www.giga.puc-rio.br/cgi-bin/elua.cgi?p=Contact">contact me</a> and I'll make the necessary corrections. And of course, this tutorial comes without any guarantees whatsoever.</strong></p>
+<li>um computador rodando Linux: Eu uso Ubuntu 8.04, mas qualquer Linux irá funcionar, desde que você saiba como encontrar o equivalente do "apt-get" para a sua distribuição. Não entrarei em detalhes sobre isso, pesquise no Google e você encontrará o que precisa. Assumimos também que o Linux já tem uma "base" nativa toolchain instalada (gcc/make e afins). Isto é verdadeiro para o Ubuntu depois de instalado. No entanto, você precisa verificar a sua distribuição específica.</li>
-<h2>› Prerequisites</h2>
-<p>To build your toolchain you'll need:</p>
-<ul><li>a computer running Linux: I use Ubuntu 8.04, but any Linux
-will do as long as you know how to find the equivalent of "apt-get" for
-your distribution. I won't be going into details about this, google it
-and you'll sure find what you need. It is also assumed that the Linux
-system already has a "basic" native toolchain installed (gcc/make and
-related). This is true for Ubuntu after installation. Again, you might
-need to check your specific distribution.</li><li>GNU binutils: get it from <a href="http://ftp.gnu.org/gnu/binutils/">here</a>.
-At the moment of writing this, the latest versions is 2.18, which for
-some weird reason refuses to compile on my system, so I'm using 2.17
-instead.</li><li>GCC: version 4.3.0 or newer is recommended. As
-I'm writing this, the latest GCC version is 4.3.1 which I'll be using
-for this tutorial. Download it from <a href="http://gcc.gnu.org/mirrors.html">here</a> after choosing a suitable mirror.</li><li>Newlib: as I'm writing this, the latest official Newlib version is 1.16.0. Download it from the <a href="ftp://sources.redhat.com/pub/newlib/index.html">Newlib FTP directory</a>.</li><li>Also,
-the tutorial assumes that you're using bash as your shell. If you use
-something else, you might need to adjust some shell-specific commands. </li></ul>
+<li>GNU binutils: faça o download clicando <a href="http://ftp.gnu.org/gnu/binutils/">aqui</a>. No momento em que estava fazendo este tutorial, as versões mais recentes eram 2.18, que por algum motivo desconhecido não compilava no meu sistema, por isso estou usando a versão 2,17.</li>
+<li>GCC: versão 4.3.0 ou superior é recomendada. No momento em que escrevia este tutorial, a versão mais recente era a 4.3.1, a qual usarei para este tutorial. Faça o download <a href="http://gcc.gnu.org/mirrors.html">aqui</a> logo após de ter escolhido o seu mirror.</li>
-<p>Also, you need some support programs/libraries in order to compile the toolchain. To install them:</p>
+<li>Newlib: enquanto preparava este tutorial, a versão mais recentes era a 1.16.0. Faça o download do diretório <a href="ftp://sources.redhat.com/pub/newlib/index.html">FTP Newlib</a>.</li>
+
+<li>Além disso, este tutorial assume que você esteja usando o bash como seu shell. Se você usar qualquer outra coisa, provavelmente você precisará ajustar alguns comandos do shell específico.</li>
+
+</ul>
+
+<p>Você ainda precisará de outros programas e bibliotecas a fim de construir o toolchain. Para instalá-los:</p>
+
<p><br></p>
<table class="table_cod">
@@ -53,10 +32,7 @@
</tbody></table>
-<p>Next, decide where you want to install your toolchain. They
-generally go in /usr/local/, so I'm going to assume
-/usr/local/cross-i686 for this tutorial. To save yourself some typing,
-set this path into a shell variable:</p>
+<p>Em seguida, decida onde pretende instalar o seu toolchain. Eles geralmente são instalados no diretório /usr/local/, logo, assumiremos o diretório /usr/local/cross-i386 para este tutorial. Para agilizarmos a digitação, defina este caminho como padrão na variável de ambiente:</p>
<p><br></p>
@@ -67,9 +43,9 @@
</tbody></table>
-<h2>› Step 1: binutils</h2>
+<h2>› Passo 1: binutils</h2>
-<p>This is the easiest step: unpack, configure, build.</p>
+<p>Este é o passo mais fácil: descompactar, configurar, compilar.</p>
<p><br></p>
@@ -103,16 +79,10 @@
-<p>Now you have your i386 "binutils" (assembler, linker, disassembler ...) in your PATH.</p>
-<h2>› Step 2: basic GCC</h2>
+<p>Agora você tem os "binutils" para a CPU i386(assembler, linker, disassembler ...) em seu PATH.</p>
+<h2>› Passo 2: GCC básico</h2>
-<p>In this step we build a "basic" GCC (that is, a GCC without any
-support libs, which we'll use in order to build all the libraries for
-our target). But first we need to make a slight modification in the
-configuration files. Out of the box, the GCC 4.3.1/newlib combo won't
-compile properly, giving a very weird "Link tests are not allowed after
-GCC_NO_EXECUTABLES" error. After a bit of googling, I found the
-solution for this:</p>
+<p>Nesta etapa iremos criar uma GCC "básica" (ou seja, uma GCC sem nenhuma bibliotecas de suporte, a qual utilizaremos a fim de criar todas as bibliotecas para o nosso objetivo). Mas primeiro, temos que fazer uma rápida modificação nos arquivos de configuração. Fora desse ambiente, o pacote GCC 4.3.1/newlib não compilará corretamente, emitindo o seguinte erro muito estranho "Link tests are not allowed after GCC_NO_EXECUTABLES". Após googlear um pouco, encontrei a seguinte solução:</p>
<p><br></p>
@@ -130,14 +100,11 @@
+<p>Estou usando o "joe", como meu editor de Linux favorito, no entanto, você pode usar qualquer outro editor de texto. Agora encontre a linha que tenha o string "AC_LIBTOOL_DLOPEN" e adicione um "#" no inicio da linha:</p>
-<p>I'm using "joe" here as it's my favourite Linux text mode editor,
-you can use any other text editor. Now find the line which says
-"AC_LIBTOOL_DLOPEN" and comment it out by adding a "#" before it: </p>
-
<pre><code> # AC_LIBTOOL_DLOPEN<br></code></pre>
-<p>Save the modified file and exit the text editor</p>
+<p>Salve o arquivo e saia do editor de texto.</p>
<p><br></p>
@@ -150,10 +117,8 @@
</tr>
</tbody></table>
+<p>Ótimo, agora sabemos que podemos compilar, então vamos em frente:</p>
-
-<p>Great, now we know it will compile, so let's do it:</p>
-
<p><br></p>
<table class="table_cod">
@@ -178,12 +143,8 @@
</tr>
</tbody></table>
+<p>No meu sistema, a última linha acima(sudo make install-gcc) termina com erros, devido a impossibilidade de encontrar a binutils recentemente compilada. Se isso acontece para qualquer tipo de comando "make install", aqui está uma maneira rápida de resolver isso:</p>
-<p>On my system, the last line above (sudo make install-gcc) terminated
-with errors, because it was unable to find our newly compiled binutils.
-If this happens for any kind of "make install" command, this is a quick
-way to solve it:</p>
-
<p><br></p>
<table class="table_cod">
@@ -196,13 +157,9 @@
<pre><code> # export PATH=/usr/local/cross-i686/bin:$PATH<br> # make install-gcc<br> # exit<br></code></pre>
-<h2>› Step 3: Newlib</h2>
+<h2>› Passo 3: Newlib</h2>
-<p>Once again, Newlib is as easy as unpack, configure, build. But I
-wanted my library to be as small as possible (as opposed to as fast as
-possible) and I only wanted to keep what's needed from it in the final
-executable, so I added the "-ffunction-sections -fdata-sections" flags
-to allow the linker to perform dead code stripping:</p>
+<p>Outra vez, esse passo 3 NewLib, é tão fácil quanto descompactar, configurar e compilar. Mas eu preciso que a minha biblioteca seja do menor tamanho possível (em contraposição, a tão rápida quanto possível) e só quero manter o necessário no executável, por isso, acrescentei os flags "-ffunction-sections -fdata-sections" para permitir que o linker execute dead code stripping:</p>
<p><br></p>
@@ -237,24 +194,24 @@
</tbody></table>
+<p>Algumas observações sobre os flags usados na sequência acima:</p>
-<p>Some notes about the flags used in the above sequence:</p>
+<ul>
+<li><code>--disable-newlib-supplied-syscalls:</code> isto merece uma página inteira, mas não dá para fazê-lo aqui. Para um melhor entendimento, veja <a href="http://openhardware.net/Embedded_ARM/NewLib_Stubs/">esta página</a>.</li>
-<ul><li><code>--disable-newlib-supplied-syscalls:</code> this deserves a page of its own, but I won't cover it here. For an explanation, see for example <a href="http://openhardware.net/Embedded_ARM/NewLib_Stubs/">this page</a>.</li><li><code>-D__PREFER_SIZE_OVER_SPEED -D__OPTIMIZE_SIZE__:</code> compile Newlib for size, not for speed (these are Newlib specific).</li><li><code>-Os -fomit-frame-pointer:</code> tell GCC to optimize for size, not for speed.</li><li><code>-D__BUFSIZ__=256:</code>
-again Newlib specific, this is the buffer size allocated by default for
-files opened via fopen(). The default is 1024, which I find too much
-for an eLua, so I'm using 256 here. Of course, you can change this
-value.</li></ul>
+<li><code>-D__PREFER_SIZE_OVER_SPEED -D__OPTIMIZE_SIZE__:</code> compila Newlib otimizando o tamanho, não a performance (estes são especÃficos da Newlib).</li>
+<li><code>-Os -fomit-frame-pointer:</code> indica para GCC otimizar o tamnho, não a velocidade.</li>
-<h2>› Step 4: full GCC</h2>
+<li><code>-D__BUFSIZ__=256:</code> novamente específico da Newlib, este é o tamanho default do buffer alocado para arquivos abertos via fopen(). O padrão é 1024, cujo tamanho considerei muito para eLua, logo estou usando 256 aqui. Certamente, você pode mudar este valor.</li>
-<p>Finally, in the last step of our tutorial, we complete the GCC
-build. In this stage, a number of compiler support libraries are built
-(most notably libgcc.a). Fortunately this is simpler that the Newlib
-compilation step:</p>
+</ul>
+<h2>› Passo 4: full GCC</h2>
+
+<p>Finalmente, no último passo deste tutorial, completamos a criaçã da GCC. Nesta etapa, várias bibliotecas de suporte do compilador são montadas (sendo a mais importante a libgcc.a). Felizmente isto é mais simples do que a compilacriação da NewLib:</p>
+
<p><br></p>
<table class="table_cod">
@@ -270,12 +227,8 @@
</tbody></table>
+<h2>› Passo 5: Tudo pronto!</h2>
-
-<h2>› Step 5: all done!</h2>
-
-<p>Now you can finally enjoy your i386 toolchain, and compile eLua with
-it :) After you do, you'll be able to boot eLua directly on your PC, as
-described <a href="http://www.giga.puc-rio.br/cgi-bin/elua.cgi?p=Booting_your_PC_in_eLua">here</a>, but you won't need to download the ELF file from the eLua project page, since you just generated it using your own toolchain!
-If you need further clarification, or if the above instructions didn't work for you, feel free to <a href="http://www.giga.puc-rio.br/cgi-bin/elua.cgi?p=Contact">contact me</a>.</p>
-</div></body></html>
\ No newline at end of file
+<p>Finalmente, você poderá usar o seu toolchain para i386, e compilar eLua com ele :) Após completar os passos acima, você será capaz de dar boot em eLua direto do seu PC, como descrito <a href="tut_bootpc.html">aqui</a>, e não precisará fazer o download do arquivo ELF da página do projeto eLua, já que você o gerou usando sua própria toolchain!
+Se você precisar de mais explicações ou se as instruções acima não funcionaram para você, sinta-se a vontade para <a href="overview.html#contacts">contactar-me</a>.</p>
+$$FOOTER$$
Modified: branches/eagle_mmc/doc/pt/tc_arm.html
===================================================================
--- branches/eagle_mmc/doc/pt/tc_arm.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/pt/tc_arm.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,48 +1,21 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
+$$HEADER$$
+<p> Esse tutorial explica como criar um toolchain com GCC+Newlib para ser usado na compilação de programas usando a arquitetura ARM, tornando assim possível a compilação de programas para um grande número de CPUs com arquitetura ARM. Você precisará desse recurso se pretende compilar eLua para as CPUs com arquitetura ARM. Esse tutorial é semelhante a muitos outros encontrados na Internet (particularmente o <a href="http://www.gnuarm.com/">gnuarm</a>, que serviu de base para esse tutorial), no entanto, este possui um maior detalhamento e mostra alguns "dicas" que você poderá utilizar quando estiver compilando a Newlib.</p>
-<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);"><h3><a name="title" href="http://www.eluaproject.net/en/Building_GCC_for_ARM" class="local">Building GCC for ARM</a></h3>
-
- <div class="content">
+<p><strong>AVISO: Eu não sou um especialista no processo de montagem de CGC/newlib/binutils. Tenho certeza de que existem melhores formas de realizar o que estou descrevendo aqui, no entanto, apresento apenas uma maneira rápida de construir um toolchain, não tenho nenhuma intenção de me aprofundar no processo de montagem. Se você encontrar algum erro, por favor entre em <a href="http://www.eluaproject.net/en/Contact">contato comigo</a> e farei as correções necessárias. Acrescento ainda, que esse tutorial não possui nenhum tipo de garantia.</strong></p>
-<p> This tutorial explains how you can create a GCC+Newlib toolchain
-that can be used to compile programs for the ARM architecture, thus
-making it possible to compile programs for the large number of ARM CPUs
-out there. You'll need such a toolchain if you want to compile eLua for
-ARM CPUs. This tutorial is similar to many others you'll find on the
-Internet (particulary the one from <a href="http://www.gnuarm.com/">gnuarm</a>, on which it's based), but it's a bit more detailed and shows some "tricks" you can use when compiling Newlib.</p>
+<h2>Pré-requisitos</h2>
+<p>Para construir seu toolchain você precisará de:</p>
-<p><strong>DISCLAIMER: I'm by no means a specialist in the
-GCC/newlib/binutils compilation process. I'm sure that there are better
-ways to accomplish what I'm describing here, however I just wanted a
-quick and dirty way to build a toolchain, I have no intention in
-becoming too intimate with the build process. If you think that what I
-did is wrong, innacurate, or simply outrageously ugly, feel free to <a href="http://www.eluaproject.net/en/Contact">contact me</a> and I'll make the necessary corrections. And of course, this tutorial comes without any guarantees whatsoever.</strong></p>
+<ul>
+<li>Um computador rodando Linux: Eu uso Ubuntu 8.04, mas qualquer Linux irá fazer, desde que você saiba como encontrar o equivalente do "apt-get" para a sua distribuição. Não entrarei em detalhes sobre isso, pesquise no Google e você encontrará o que precisa. Assumimos também que o Linux já tem uma "base" nativa toolchain instalada (gcc/make e afins). Isto é verdadeiro para o Ubuntu depois da instalação. No entanto, você precisa verificar a sua distribuição específica.</li>
+<li>GNU binutils: faça o download <a href="http://ftp.gnu.org/gnu/binutils/">aqui</a>. No momento em que elaborava este tutorial, as versões mais recentes eram 2.18, que por algum motivo desconhecido não compilava no meu sistema, por isso estou usando a versão 2,17.</li>
+<li>GCC: versão 4.3.0 ou superior é recomendada. No momento em que escrevia este tutorial, a versão mais recente era a 4.3.1, a qual usarei para este tutorial. Faça o download <a href="http://gcc.gnu.org/mirrors.html">aqui</a> depois de escolher um bom servidor de mirror.</li>
+<li>Newlib: enquanto preparava este tutorial, a versão mais recentes era a 1.16.0. Faça o download do <a href="ftp://sources.redhat.com/pub/newlib/index.html">diretório FTP Newlib</a>.</li>
+<li>Além disso, o tutorial assume que você esteja usando o bash como seu shell. Se você usar qualquer outra coisa, talvez você precise ajustar alguns comandos do shell específico.</li>
+</ul>
-<h2>Prerequisites</h2>
-<p>To build your toolchain you'll need:</p>
+<p>Você ainda precisará de outros programas e bibliotecas a fim de montar o toolchain. Para instalá-los:</p>
-<ul><li>a computer running Linux: I use Ubuntu 8.04, but any Linux
-will do as long as you know how to find the equivalent of "apt-get" for
-your distribution. I won't be going into details about this, google it
-and you'll sure find what you need. It is also assumed that the Linux
-system already has a "basic" native toolchain installed (gcc/make and
-related).This is true for Ubuntu after installation. Again, you might
-need to check your specific distribution.</li><li>GNU binutils: get it from <a href="http://ftp.gnu.org/gnu/binutils/">here</a>.
-At the moment of writing this, the latest versions is 2.18, which for
-some weird reason refuses to compile on my system, so I'm using 2.17
-instead.</li><li>GCC: version 4.3.0 or newer is recommended. As
-I'm writing this, the latest GCC version is 4.3.1 which I'll be using
-for this tutorial. Download it from <a href="http://gcc.gnu.org/mirrors.html">here</a> after choosing a suitable mirror.</li><li>Newlib: as I'm writing this, the latest official Newlib version is 1.16.0. Download it from the <a href="ftp://sources.redhat.com/pub/newlib/index.html">Newlib FTP directory</a>.</li><li>Also,
-the tutorial assumes that you're using bash as your shell. If you use
-something else, you might need to adjust some shell-specific commands. </li></ul>
-
-
-<p>Also, you need some support programs/libraries in order to compile the toolchain. To install them:</p>
-
<p><br></p>
<table class="table_cod">
@@ -52,10 +25,7 @@
</tbody></table>
-<p>Next, decide where you want to install your toolchain. They
-generally go in /usr/local/, so I'm going to assume
-/usr/local/cross-arm for this tutorial. To save yourself some typing,
-set this path into a shell variable:</p>
+<p>Em seguida, defina onde pretende instalar o seu toolchain. Eles geralmente são instalados no diretório /usr/local/, logo, assumiremos o diretório /usr/local/cross-arm para este tutorial. Para agilizar a digitação, defina este caminho como padrão na variável de ambiente:</p>
<p><br></p>
@@ -66,8 +36,8 @@
</tbody></table>
-<h2>› Step 1: binutils</h2>
-<p>This is the easiest step: unpack, configure, build.</p>
+<h2>› Passo 1: binutils</h2>
+<p>Este é o passo mais fácil: descompactar, configurar, compilar.</p>
<p><br></p>
@@ -127,17 +97,11 @@
</tbody></table>
-<p>Now you have your ARM "binutils" (assembler, linker, disassembler ...) in your PATH.</p>
+<p>Agora você tem os "binutils" da CPU ARM(assembler, linker, disassembler ...) em seu PATH.</p>
-<h2>Step 2: basic GCC</h2>
+<h2>Passo 2: basic GCC</h2>
-<p>In this step we build a "basic" GCC (that is, a GCC without any
-support libs, which we'll use in order to build all the libraries for
-our target). But first we need to make a slight modification in the
-configuration files. Out of the box, the GCC 4.3.1/newlib combo won't
-compile properly, giving a very weird "Link tests are not allowed after
-GCC_NO_EXECUTABLES" error. After a bit of googling, I found the
-solution for this:</p>
+<p>Nesta etapa vamos montar uma "base" GCC (ou seja, uma GCC sem nenhuma lib, a qual usaremos, a fim de criar todas as bibliotecas para o nosso objetivo). Mas primeiro temos que fazer uma rápida modificação nos arquivos de configuração. Fora desse ambiente, o pacote GCC 4.3.1/newlib não compilará corretamente, dando um erro muito estranho "Link tests are not allowed after GCCNOEXECUTABLES". Após uma procura no google, encontrei a solução para isso:</p>
<p><br></p>
@@ -154,13 +118,11 @@
</tbody></table>
-<p> I'm using "joe" here as it's my favourite Linux text mode editor,
-you can use any other text editor. Now find the line which says
-"AC_LIBTOOL_DLOPEN" and comment it out by adding a "#" before it:</p>
+<p> Estou usando "joe" aqui, como meu editor de texto Linux favorito, você pode usar qualquer outro editor de texto. Agora encontre a linha que tenha o string "AC_LIBTOOL_DLOPEN" e adicione um "#" no inicio da linha:</p>
<p><code># AC_LIBTOOL_DLOPEN</code></p>
-<p>Save the modified file and exit the text editor</p>
+<p>Salve o arquivo alterado e saia do editor. </p>
<p><br> </p>
@@ -175,7 +137,7 @@
-<p>Great, now we know it will compile, so let's do it:</p>
+<p>Ótimo, agora sabemos que podemos compilar, então vamos em frente:</p>
<p><br></p>
@@ -203,14 +165,10 @@
-<p>On my system, the last line above (sudo make install-gcc) terminated
-with errors, because it was unable to find our newly compiled binutils.
-If this happens for any kind of "make install" command, this is a quick
-way to solve it:</p>
+<p>No meu sistema, a última linha acima (sudo make install-gcc) termina com erros, devido a impossibilidade de encontrar a binutils recentemente compilada. Se isso acontece para qualquer tipo de comando "make install", aqui está uma maneira rápida de resolver isso:</p>
-<p style="text-align: left;"><br></p><div style="text-align: left;">
-
-</div><table class="table_cod">
+<p style="text-align: left;"><br></p><div style="text-align: left;"></div>
+<table class="table_cod">
<tbody><tr align="left">
<th>$ sudo -s -H</th>
</tr>
@@ -228,13 +186,9 @@
-<h2>Step 3: Newlib</h2>
+<h2>Passo 3: Newlib</h2>
-<p>Once again, Newlib is as easy as unpack, configure, build. But I
-wanted my library to be as small as possible (as opposed to as fast as
-possible) and I only wanted to keep what's needed from it in the final
-executable, so I added the "-ffunction-sections -fdata-sections" flags
-to allow the linker to perform dead code stripping:</p>
+<p>Mais uma vez, este etapa é tão fácil quanto descompactar, configurar, compilar. Mas eu preciso que a minha biblioteca seja do menor tamanho possível (em contraposição, tão rápida quanto possível) e eu só queria manter o que é necessário no executável, por isso, acrescentei os flags "-ffunction-sections -fdata-sections" para permitir que o linker execute "dead code stripping":</p>
<p><br></p>
@@ -270,21 +224,20 @@
-<p>Some notes about the flags used in the above sequence:</p>
+<p>Algumas observações sobre os flags usados na sequência acima:</p>
-<ul><li><code>--disable-newlib-supplied-syscalls</code>: this deserves a page of its own, but I won't cover it here. For an explanation, see for example <a href="http://openhardware.net/Embedded_ARM/NewLib_Stubs/">this page</a></li><li><code>-DPREFER_SIZE_OVER_SPEED -D__OPTIMIZE_SIZE__</code>: compile Newlib for size, not for speed (these are Newlib specific).</li><li><code>-Os -fomit-frame-pointer</code>: tell GCC to optimize for size, not for speed.</li><li><code>-D__BUFSIZ__=256</code>:
-again Newlib specific, this is the buffer size allocated by default for
-files opened via fopen(). The default is 1024, which I find too much
-for an eLua, so I'm using 256 here. Of course, you can change this
-value.</li></ul>
+<ul>
+<li><code>--disable-newlib-supplied-syscalls</code>: isto merece uma página própria, mas não vou fazê-lo aqui. Para uma explicação, por exemplo, ver <a href="http://openhardware.net/Embedded_ARM/NewLib_Stubs/">esta página</a></li>
+<li><code>-DPREFER_SIZE_OVER_SPEED -D__OPTIMIZE_SIZE__</code>: compila Newlib otimizando o tamanho, não a performance (estes são específicos da Newlib).</li>
+<li><code>-Os -fomit-frame-pointer</code>: indica para GCC otimizar o tamnho, não a velocidade.</li>
+<li><code>-D__BUFSIZ__=256</code>:
+novamente específico da Newlib, este é o tamanho default do buffer alocado para arquivos abertos via fopen(). O padrão é 1024, cujo tamanho considerei muito para eLua, logo estou usando 256 aqui. Certamente, você pode mudar este valor.</li>
+</ul>
-<h2>Step 4: full GCC</h2>
+<h2>Passo 4: full GCC</h2>
-<p>Finally, in the last step of our tutorial, we complete the GCC
-build. In this stage, a number of compiler support libraries are built
-(most notably libgcc.a). Fortunately this is simpler that the Newlib
-compilation step:</p>
+<p>Finalmente, no último passo deste tutorial, completamos a construção do GCC. Nesta etapa, várias bibliotecas de suporte do compilador são montadas (sendo a mais importante a libgcc.a). Felizmente este á o mais simples dos passos de compilação da NewLib:</p>
<p><br></p>
@@ -303,8 +256,8 @@
-<h2>Step 5: all done!</h2>
+<h2>Passo 5: Tudo pronto!</h2>
-<p>Now you can finally enjoy your ARM toolchain, and compile eLua with it :)
-If you need further clarification, or if the above instructions didn't work for you, feel free to <a href="http://www.eluaproject.net/en/Contact">contact me</a>.</p>
-</div></body></html>
\ No newline at end of file
+<p>
+Agora você pode finalmente desfrutar do seu toolchain para ARM, e compile eLua com ele :) Se você precisar de mais explicações, ou se as instruções acima não funcionaram para você, sinta-se a vontade para entrar em <a href="http://www.eluaproject.net/en/Contact">contato comigo.</a>.</p>
+$$FOOTER$$
\ No newline at end of file
Modified: branches/eagle_mmc/doc/pt/tc_cortex.html
===================================================================
--- branches/eagle_mmc/doc/pt/tc_cortex.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/pt/tc_cortex.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,59 +1,32 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
+$$HEADER$$
+<h3><a name="title" href="http://www.eluaproject.net/en/Building_GCC_for_Cortex" class="local">Construindo GCC para o Cortex</a></h3>
-<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);"><div class="content">
+<p>Este tutorial explica como criar um CCG+Newlib toolchain que poderá ser usado para compilar programas na arquitetura Cortex(Thumb2), tornando assim possível a compilação de programas para um grande número de CPUs Cortex(<a href="http://www.luminarymicro.com/">Luminary Micro</a>, <a href="http://www.st.com/mcu/inchtml-pages-stm32.html">ST</a>, com nova CPU Cortex sendo anunciada pela Atmel e outras companhias). Estou escrevendo este tutorial porque eu precisei trabalhar com uma CPU Cortex para o projeto eLua e não consegui encontrar em lugar nenhum, alguma ajuda para construir uma GCC para essa arquitetura. Você precisará de uma toolchain se quiser compilar eLua para CPUs Cortex-M3.</p>
-<h3><a name="title" href="http://www.eluaproject.net/en/Building_GCC_for_Cortex" class="local">Building GCC for Cortex</a></h3><p>This tutorial explains how you can create a GCC+Newlib toolchain
-that can be used to compile programs for the Cortex (Thumb2)
-architecture, thus making it possible to use GCC to compile programs
-for the increasingly number of Cortex CPUs out there (<a href="http://www.luminarymicro.com/">Luminary Micro</a>, <a href="http://www.st.com/mcu/inchtml-pages-stm32.html">ST</a>,
-with new Cortex CPUs being announced by Atmel and other companies). I
-am writing this tutorial because I needed to work on a Cortex CPU for
-the eLua project and I couldn't find anywhere a complete set of
-instructions for building GCC for this architecture. You'll need such a
-toolchain if you want to compile eLua for Cortex-M3 CPUs.</p>
+<p><strong>
+AVISO: Não sou um especialista no processo de compilação de CGC/newlib/binutils. Tenho certeza de que existem melhores formas de realizar o que estou descrevendo aqui, no entanto desejo apenas uma maneira rápida de construir um toolchain, não tenho nenhuma intenção de ficar muito íntimo do processo de construção. Se você acha que o que fiz aqui está errado, impreciso ou, simplesmente, escandalosamente feio, não hesite em <a href="http://www.eluaproject.net/en/Contact">contactar-me</a> e farei as correcções necessárias. E claro, este tutorial é fornecido sem qualquer garantia.</strong></p>
-<p><strong>DISCLAIMER: I'm by no means a specialist in the
-GCC/newlib/binutils compilation process. I'm sure that there are better
-ways to accomplish what I'm describing here, however I just wanted a
-quick and dirty way to build a toolchain, I have no intention in
-becoming too intimate with the build process. If you think that what I
-did is wrong, innacurate, or simply outrageously ugly, feel free to <a href="http://www.eluaproject.net/en/Contact">contact us</a> and I'll make the necessary corrections. And of course, this tutorial comes without any guarantees whatsoever.</strong></p>
+<h2>Pré-requisitos</h2>
+<p>Para construir seu toolchain você precisará de:</p>
-<h2>Prerequisites</h2>
-<p>To build your toolchain you'll need:</p>
+<ul>
-<ul><li>a computer running Linux: I use Ubuntu 8.04, but any Linux
-will do as long as you know how to find the equivalent of "apt-get" for
-your distribution. I won't be going into details about this, google it
-and you'll sure find what you need. It is also assumed that the Linux
-system already has a "basic" native toolchain installed (gcc/make and
-related). This is true for Ubuntu after installation. Again, you might
-need to check your specific distribution.</li><li>GNU binutils: get it from <a href="http://ftp.gnu.org/gnu/binutils/">here</a>.
-At the moment of writing this, the latest versions is 2.18, which for
-some weird reason refuses to compile on my system, so I'm using 2.17
-instead. <strong>UPDATE</strong>: you MUST use the new binutils 2.19
-distribution for the Cortex toolchain, since it fixes some assembler
-issues. You won't be able to compile eLua 0.5 or higher if you don't
-use binutils 2.19.</li><li>GCC: since support for Cortex (Thumb2)
-was only introduced staring with version 4.3.0, you'll need to download
-version 4.3.0 or newer. As I'm writing this, the latest GCC version is
-4.3.1, which I'll be using for this tutorial. Download it from <a href="http://gcc.gnu.org/mirrors.html">here</a> after choosing a suitable mirror.</li><li>Newlib:
-as I'm writing this, the latest official Newlib version is 1.16.0.
-However, the CVS version contains some fixes for the Thumb2
-architecture, some of them in very important functions (like
-setjmp/longjmp), so you'll need to fetch the sources from CVS (this
-will most likely change when a new official Newlib version is
-released). So go to <a href="http://sourceware.org/newlib/download.html">http://sourceware.org/newlib/download.html</a> and follow the instructions there in order to get the latest sources from CVS.</li><li>Also,
-the tutorial assumes that you're using bash as your shell. If you use
-something else, you might need to adjust some shell-specific commands. </li></ul>
+<li>Um computador rodando Linux: Eu uso Ubuntu 8.04, mas qualquer Linux irá fazer desde que você saiba como encontrar o equivalente do "apt-get" para a sua distribuição. Não entrarei em detalhes sobre isso, pesquise no Google e você encontrará o que você precisa. Assumimos também que o Linux já tem uma "base" nativa toolchain instalada (gcc/make e afins). Isto é verdadeiro para o Ubuntu após a sua instalação. Novamente, você precisa verificar a sua distribuição específica.</li>
-<p>Also, you need some support programs/libraries in order to compile the toolchain. To install them:</p>
+<li>GNU binutils: faça o download clicando <a href="http://ftp.gnu.org/gnu/binutils/">aqui</a>. No momento em que escrevia este tutorial, as versões mais recentes eram 2,18, que por algum motivo estranho recusou-se a compilar no meu sistema, por isso estou usando a versão 2,17. UPDATE: você deve usar a nova distribuição binutils 2.19 para o Cortex toolchain, desde que este corrigiu alguns problemas do compilador. Você não conseguirá compilar o eLua 0.5 ou maior se não utilizar binutils 2.19.</li>
+<li>GCC: A partir do suporte para Cortex (Thumb2) iniciado na versão 4.3.0, você deve fazer o download desta versão ou mais recente. Enquanto preparava esse tutorial, a versão mais recente era a 4.3.1, a qual foi utilizada para esse tutorial. Faça o download <a href="http://gcc.gnu.org/mirrors.html">aqui</a> depois de escolher um bom servidor mirror.</li>
+
+<li>Newlib: Enquanto escrevia este tutorial, a versão mais recentes era a 1.16.0. Entretanto, a versão CVS contêm algumas correções para a arquitetura Thumb2, algumas delas muito importantes (como setjmp/longjmp), logo você precisará obter os fontes do CVS(isto mudará bastante quando a nova versão oficial da NewLib for liberada). Então faça o download do diretório <a href="http://sourceware.org/newlib/download.html">http://sourceware.org/newlib/download.html</a> e siga as instruções para obter os fontes CVS mais recentes.</li>
+
+<li>Além disso, o tutorial assume que você está usando o bash como seu shell. Se você usar qualquer outra coisa, talvez seja necessário ajustar alguns comandos do shell específico.</li>
+
+</ul>
+
+
+<p>Você ainda precisará de outros programas e bibliotecas a fim de montar o toolchain. Para instalá-los execute o seguinte comando:</p>
+
<p><br></p>
<table class="table_cod">
@@ -63,12 +36,8 @@
</tbody></table>
+<p>Em seguida, decida onde pretende instalar o seu toolchain. Eles geralmente são instalados no diretório /usr/local/, logo, assumiremos o diretório /usr/local/cross-cortex para este tutorial. Para agilizar a digitação, defina este caminho como padrão na variável do ambiente:</p>
-<p>Next, decide where you want to install your toolchain. They
-generally go in /usr/local/, so I'm going to assume
-/usr/local/cross-cortex for this tutorial. To save yourself some
-typing, set this path into a shell variable:</p>
-
<p><br></p>
<table class="table_cod">
@@ -79,9 +48,9 @@
-<h2>Step 1: binutils</h2>
+<h2>Passo 1: binutils</h2>
-<p>This is the easiest step: unpack, configure, build.</p>
+<p>Este é o passo mais fácil: descompactar, configurar, montar.</p>
<p><br></p>
@@ -116,19 +85,12 @@
-<p>Now you have your ARM "binutils" (assembler, linker, disassembler ...) in your PATH. They are fully capable of handling Thumb2.</p>
+<p>Agora você tem os "binutils" da CPU Cortex(assembler, linker, disassembler ...) em seu PATH. Eles funcionam com a arquitetura Thumb2.</p>
-<h2>Step 2: basic GCC</h2>
+<h2>Passo 2: GCC básico</h2>
-<p>In this step we build a "basic" GCC (that is, a GCC without any
-support libs, which we'll use in order to build all the libraries for
-our target). But first we need to make a slight modification in the
-configuration files. Out of the box, the GCC 4.3.1/newlib combo won't
-compile properly, giving a very weird "Link tests are not allowed after
-GCC_NO_EXECUTABLES" error. After a bit of googling, I found the
-solution for this:</p>
+<p>Nesta etapa vamos construir um GCC "básico" (ou seja, uma GCC sem nenhuma lib, a qual usaremos, a fim de criar todas as bibliotecas para o nosso objetivo). Mas primeiro temos de fazer uma rápida modificação nos arquivos de configuração. Fora desse ambiente, o pacote GCC 4.3.1/newlib não compilará corretamente, dando um erro muito estranho "Link tests are not allowed after GCC_NO_EXECUTABLES". Após googlear um pouco, encontrei a solução para isso:</p>
-
<p><br></p>
<table class="table_cod">
@@ -144,14 +106,12 @@
</tbody></table>
-<p> I'm using "joe" here as it's my favourite Linux text mode editor,
-you can use any other text editor. Now find the line which says
-"AC_LIBTOOL_DLOPEN" and comment it out by adding a "#" before it: </p>
+<p>Estou usando "joe" aqui como meu editor de texto Linux favorito, você pode usar qualquer outro editor de texto. Agora encontre a linha que tem "AC_LIBTOOL_DLOPEN" e adicione um "#" no inicio da linha:</p>
<code># AC_LIBTOOL_DLOPEN<br></code>
-<p>Save the modified file and exit the text editor</p>
+<p>Salve o arquivo e saia do editor de texto.</p>
<p><br></p>
@@ -166,10 +126,9 @@
+<p>Ótimo, agora sabemos que podemos compilar, então vamos em frente:</p>
-<p>Great, now we know it will compile, so let's do it:</p>
-
<p><br></p>
<table class="table_cod">
@@ -195,10 +154,7 @@
-<p>On my system, the last line above (sudo make install-gcc) terminated
-with errors, because it was unable to find our newly compiled binutils.
-If this happens for any kind of "make install" command, this is a quick
-way to solve it:</p>
+<p>No meu sistema, a execução da última linha acima(sudo make install-gcc) gera um erro, devido a impossibilidade de encontrar o arquivo binutils. Se isso também acontece no seu sistema, aqui está uma maneira rápida de resolver:</p>
<p><br></p>
@@ -213,12 +169,9 @@
<code><br><br><br></code>
-<h2>Step 3: Newlib</h2>
+<h2>Passo 3: Newlib</h2>
-<p>Again, some modifications are in order before we start compiling.
-Because the CVS version of Newlib doesn't seem to have all the required
-support for Thumb2 yet, we need to tell Newlib to skip some of its
-libraries when compiling:</p>
+<p>Mais uma vez, algumas modificações s;ão necessárias antes de começarmos a compilação. Devido a versão CVS da NewLib parecer não permitir o suporte necessário para o Thumb2, precisamos fazer a NewLib saltar algumas de suas libraries durante a compilação:</p>
<p><br></p>
@@ -234,17 +187,12 @@
-<p> Find this fragment of code:</p>
+<p>Localize o código abaixo:</p>
-<pre><code> arm-*-elf* | strongarm-*-elf* | xscale-*-elf* | arm*-*-eabi* )<br> noconfigdirs="$noconfigdirs target-libffi target-qthreads"<br> libgloss_dir=arm<br> ;;<br><br> And add "target-libgloss" to the "noconfigdirs" variable:<br><br> arm-*-elf* | strongarm-*-elf* | xscale-*-elf* | arm*-*-eabi* )<br> noconfigdirs="$noconfigdirs target-libffi target-qthreads target-libgloss"<br> libgloss_dir=arm<br> ;;<br><br> Save the modified file and exit the text editor<br> $ autoconf<br></code></pre>
+<pre><code> arm-*-elf* | strongarm-*-elf* | xscale-*-elf* | arm*-*-eabi* )<br> noconfigdirs="$noconfigdirs target-libffi target-qthreads"<br> libgloss_dir=arm<br> ;;<br><br> And add "target-libgloss" to the "noconfigdirs" variable:<br><br> arm-*-elf* | strongarm-*-elf* | xscale-*-elf* | arm*-*-eabi* )<br> noconfigdirs="$noconfigdirs target-libffi target-qthreads target-libgloss"<br> libgloss_dir=arm<br> ;;<br><br> Salve o arquivo e saia do editor<br> $ autoconf<br></code></pre>
-<p>On one of the systems I ran the above sequence, it terminated with
-errors, complaining that autoconf 2.59 was not found. I don't know why
-that happens. 2.59 seems to be quite ancient, and the build ran equally
-well with 2.61 (the version of autoconf on the system that gave the
-error). If this happens to you, first execute autoconf --version to
-find the actual version of your autoconf, then do this:</p>
+<p>Em um dos sistemas onde executei a sequência acima, aconteceram erros, indicando que o arquivo autoconf 2.59 não tinha sido encontrado. Não entendi porque isto aconteceu. Como a vers;ão 2.59 já não é tão recente, e a compilação roda muito bem com a 2.61 (a vers;ão do autoconf no sistema que apresentou erro). Se isto acontece com você, execute inicialmente o autoconf --version para saber qual a versão corrente de seu autoconf, e então faça o seguinte:</p>
<p><br></p>
@@ -255,18 +203,10 @@
</tr>
</tbody></table>
-<pre><code>$ joe config/override.m4<br><br> Look for this line:<br><br> [m4_define([_GCC_AUTOCONF_VERSION], [2.59])])<br><br> And replace [2.59] with your actual version ([2.61] in my case).<br> $ autoconf<br></code></pre>
+<pre><code>$ joe config/override.m4<br><br> Localize esta linha:<br><br> [m4_define([_GCC_AUTOCONF_VERSION], [2.59])])<br><br> E substitua 2.59 pela sua versão atual (no meu caso 2.61).<br> $ autoconf<br></code></pre>
-<p>Once again, now we're ready to actually compile Newlib. But we need
-to tell it to compile for Thumb2. As already specified, I'm not a
-specialist when it comes to Newlib's build system, so I chosed the
-quick, dirty and not so elegant solution of providing the compilation
-flags directly from the command line. Also, as I wanted my library to
-be as small as possible (as opposed to as fast as possible) and I only
-wanted to keep what's needed from it in the final executable, I added
-the "-ffunction-sections -fdata-sections" flags to allow the linker to
-perform dead code stripping:</p>
+<p>Agora estamos prontos para compilar a Newlib. Mas é necessário informar que a compilação será feita para Thumb2. Como já foi dito antes, eu não sou um especialista, e quando se trata de montar uma Newlib, escolhi uma solução rápida, porém não tão elegante para passar os parametros de compilação diretamente na linha de comando. Além disso, como eu prefiro que a minha biblioteca tenha o menor tamanho possível (em contraposição a maior performance possível) e manter no programa executável somente o necessário, acrescentei o parametro "-ffunction-seções-fdata-sections" para permitir que o linker possa executar dead code stripping:</p>
<p><br></p>
@@ -298,24 +238,30 @@
-<p>Some notes about the flags used in the above sequence:</p>
+<p>Algumas observações sobre os parâmetros usados na sequência acima:</p>
-<ul><li><code>--disable-newlib-supplied-syscalls:</code> this deserves a page of its own, but I won't cover it here. For an explanation, see for example <a href="http://openhardware.net/Embedded_ARM/NewLib_Stubs/">this page</a>.</li><li><code>-DPREFER_SIZE_OVER_SPEED -D__OPTIMIZE_SIZE__:</code> compile Newlib for size, not for speed (these are Newlib specific).</li><li><code>-mcpu=cortex-m3 -mthumb:</code> this tells GCC that you want to compile for Cortex. Note that you need both flags.</li><li><code>-D__thumb2__:</code> again, this is Newlib specific, and seems to be required when compiling Newlib for Cortex.</li><li><code>-Os -fomit-frame-pointer:</code> tell GCC to optimize for size, not for speed.</li><li><code>-D__BUFSIZ__=256:</code>
-again Newlib specific, this is the buffer size allocated by default for
-files opened via fopen(). The default is 1024, which I find too much
-for an eLua, so I'm using 256 here. Of course, you can change this
-value.</li></ul>
+<ul>
+<li><code>--disable-newlib-supplied-syscalls:</code> isso merece um capÃtulo a parte, porém n&ão agora. Apenas como esclarecimento, veja os exemplos <a href="http://openhardware.net/Embedded_ARM/NewLib_Stubs/">nesta página</a>.</li>
+<li><code>-DPREFER_SIZE_OVER_SPEED -D__OPTIMIZE_SIZE__:</code> compile a Newlib otimizando o tamanho, e não a performance (utilizado para Newlib específica).</li>
-<h2>Step 4: full GCC</h2>
+<li><code>-mcpu=cortex-m3 -mthumb:</code> indica para a GCC que a compilação é para Cortex. É necessário utilizar os dois flags.</li>
-<p>Finally, in the last step of our tutorial, we complete the GCC
-build. In this stage, a number of compiler support libraries are built
-(most notably libgcc.a). Fortunately this is simpler that the Newlib
-compilation step, as long as you remember that we want to build our
-compiler support libraries for the Cortex architecture:</p>
+<li><code>-D__thumb2__:</code> É necessário quando compilando a Newlib para o Cortex.</li>
+<li><code>-Os -fomit-frame-pointer:</code> indica para a GCC para otimizar pelo tamanho, e não pela performance.</li>
+<li><code>-D__BUFSIZ__=256:</code>
+parâmetro específico navamente, este é o tamanho do buffer alocado por default para arquivos abertos via fopen(). O default é 1024, o qual acredito ser muito para eLua, logo utilizo aqui 256. Certamente, você poderá mudar este valor.</li>
+
+</ul>
+
+
+<h2>Passo 4: GCC completa</h2>
+
+<p>Finalmente, no último passo deste nosso tutorial, completamos a montagem do GCC. Nesta etapa, várias bibliotecas de suporte do compilador foram montadas (sendo a mais importante a libgcc.a). Felizmente este é o passo mais simples para a montagem da NewLib, e como você se lembra, ainda queremos montar nosso compilador para a arquitetura Cortex:</p>
+
+
<p><br></p>
<table class="table_cod">
@@ -333,11 +279,7 @@
-<h2>All Done!</h2>
-<p>Phew! That was quite a disturbing tutorial, with all that confusing
-flags lurking in every single shell line :) But at this point you
-should have a fully functional Cortex GCC toolchain, which seems to be
-something very rare, so enjoy it with pride.
-If you need further clarification, or if the above instructions didn't
-work for you, feel free to <a href="http://www.eluaproject.net/en/Contact">contact us</a>.</p><p></p><p></p>
-</div></body></html>
\ No newline at end of file
+<h2>Tudo pronto!</h2>
+<p>
+UFA! Esse tutorial foi um pouco confuso, com um monte de flags e linhas de comando muito longas :) No entanto, você possui agora um GCC toolchain para Cortex funcionando, o que parece ser uma coisa bastante rara hoje, então aproveite com orgulho. Se você precisar de mais explicações, ou se as instruções acima não funcionaram para você, sinta-se a vontade para <a href="http://www.eluaproject.net/en/Contact">contactar-me</a>.</p><p></p><p></p>
+$$FOOTER$$
Modified: branches/eagle_mmc/doc/pt/tchainbuild.html
===================================================================
--- branches/eagle_mmc/doc/pt/tchainbuild.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/pt/tchainbuild.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,9 +1,3 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
-
-<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);"><h3><a name="title" href="http://www.eluaproject.net/en/Building_GCC_for_i386" class="local">Toolchain Build</a></h3><a name="title" href="http://www.eluaproject.net/en/Building_GCC_for_i386" class="local"></a>eLua can be compiled and link edited with GCC Toolchains.<br><br>.....................<br><br>
-
- </body></html>
\ No newline at end of file
+$$HEADER$$
+<body style="background-color: rgb(255, 255, 255);"><h3><a name="title" href="http://www.eluaproject.net/en/Building_GCC_for_i386" class="local">Geração do Toolchain</a></h3><a name="title" href="http://www.eluaproject.net/en/Building_GCC_for_i386" class="local"></a>eLua pode ser gerado com o toolchain GCC.<br><br>.....................<br><br>
+$$FOOTER$$
Modified: branches/eagle_mmc/doc/pt/term_ref.html
===================================================================
--- branches/eagle_mmc/doc/pt/term_ref.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/pt/term_ref.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,11 +1,6 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Produto</title>
-
-<link rel="stylesheet" type="text/css" href="../style.css">
</head>
-<body style="background-color: rgb(255, 255, 255);">
<h3><a name="over">term</a></h3>
Suporte de Terminal
<p> <a name="clear"></a>[term.clear]
Modified: branches/eagle_mmc/doc/pt/tmr_ref.html
===================================================================
--- branches/eagle_mmc/doc/pt/tmr_ref.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/pt/tmr_ref.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,11 +1,6 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
-
-<link rel="stylesheet" type="text/css" href="../style.css">
</head>
-<body style="background-color: rgb(255, 255, 255);">
<h3><a name="over"></a>tmr</h3>
<span style="font-weight: bold;"></span><big><br>
</big>
Copied: branches/eagle_mmc/doc/pt/toolchains.html (from rev 525, branches/eagle_mmc/doc/en/toolchains.html)
===================================================================
--- branches/eagle_mmc/doc/en/toolchains.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/pt/toolchains.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,170 @@
+$$HEADER$$
+<h3>Toolchains for eLua</h3>
+<p>You need (at least) a toolchain if you decide to build <b>eLua</b> yourself. The toolchain must contain at least a compiler, an assembler, a linker and (most likely) a tool to extract binary
+ data from the compiled image (in order to build the actual firmware). Also, a program that reports the sizes of different sections in the compiled image is often used to give an idea about the
+ resource consumption of <b>eLua</b>. You can use as many toolchains as you want for a given target, as long as the build scripts know to handle them. This
+ section outlines the different toolchain choices available for compiling <b>eLua</b>. Use the links below to navigate directly to your target of interest.</p>
+<ul>
+ <li><a href="#armcortex">Toolchains for ARM and Cortex</a></li>
+ <li><a href="#avr32">Toolchains for AVR32</a></li>
+ <li><a href="#i386">Toolchains for i386</a></li>
+</ul>
+<p>If you have a different toolchain, reffer to the <a href="#configuration">toolchain configuration</a> paragraph in this document.</p>
+<a name="armcortex"><h2>Toolcains for ARM and Cortex</h2></a>
+<p>You have multiple options when building <b>eLua</b> for ARM and Cortex CPUs:</p>
+<ul>
+ <li>build your own toolchain. Even if you have a toolchain already available, you might want to do this for maximum flexibility and control (for example to control the libc build flags, or to
+ use specific version of the tools). Check <a href="tchainbuild.html">this link</a> for a step by step tutorial on building your own toolchain.</li>
+ <li>use a readily available toolchain. This saves you the hassle of building the toolchain yourself, which makes the process quicker and less error-prone.</li>
+</ul>
+<p>Because building a toolchain is already covered in another section of the documentation, we'll focus on installing a pre-compiled toolchain here. ARM is a very popular architecture, and because
+of this there are a lot of toolchains available for download free of charge. One of the most popular ones comes from <a href="http://www.codesourcery.com">CodeSourcery</a>, and we'll cover it here for a number of important reasons:</p>
+<ul>
+ <li>it has support for both "traditional" ARM targets and Cortex-M3 (Thumb2) targets</li>
+ <li>it comes with user-friendly installers for both Linux and Windows</li>
+ <li>it has fairlygood documentation</li>
+ <li><b>eLua</b> supports this toolchain for all its ARM and Cortex targets</li>
+</ul>
+<p>Obtaining and installing the toolchain is very easy:</p>
+<ol>
+ <li>go to <a href="http://www.codesourcery.com/sgpp/lite/arm/portal/subscription?@template=lite">the CodeSourcery download location</a> for the toolchain.</li>
+ <li>select from the table the current version in the "EABI" line (the link to the current version is just above the "All versions..." link).</li>
+ <li>download and run the installer.</li>
+</ol>
+<p>That's all! Make sure that the location of the toolchain is in your $PATH and build <b>eLua</b> with the <b>toolchain=codesourcery</b> option.</p>
+<a name="avr32"><h2>Toolchains for AVR32</h2></a>
+<p>Currently you have only one option for AVR32: download and install the toolchain from <a href="http://www.atmel.com">Atmel</a>. Unfortuntely they don't provide an installer, just a bunch of
+ Linux packages with some dependencies, so the installation process might be a bit tricky. These are the steps you should follow to install Atmel's AVR32 toolchain:</p>
+<ul>
+ <li>download the correct version for your Linux distribution (in this case Ubuntu) from <a href="http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4118">here</a>.</li>
+ <li>unzip the downloaded archive to a temporary directory, you'll get a bunch of .deb packages</li>
+ <li>install the packages from this command line (the package names are based on version 2.1.4 of the toolchain, change them as needed if you're using a different version):
+ <pre><code>$ sudo dpkg -i libavr32ocd1_3.0.9-1_i386.deb libavr32sim_0.2.1-1_i386.deb
+$ sudo dpkg -i libavrtools1_3.0.9-1_i386.deb libelfdwarfparser_2.0.7-1_i386.deb
+$ sudo dpkg -i avr32headers_1.9.11-1_all.deb
+$ sudo dpkg -i avr32parts_1.9.9-1_all.deb
+$ sudo dpkg -i avr32-binutils_2.17.atmel.1.2.6-2_i386
+$ sudo dpkg -i avr32-gcc-newlib_4.2.2-atmel.1.0.8-2_i386.deb
+$ sudo dpkg -i avr32program_3.0.4-1_i386.deb</code></pre>
+ If dpkg complains about missing dependencies, install them as required and resume the installation process.
+ </li>
+</ul>
+<p>That's it. Your toolchain is already be in $PATH (since it installs itself in /usr/bin) so you should be ready to build <b>eLua</b> for AVR32.</p>
+<a name="i386"><h2>Toolchains for i386</h2></a>
+<p>Currently the only tested procedure for building <b>eLua</b> for i386 is to <a href="tc_386.html">build an i386 toolchain</a>. Other toolchains might work equally well though, but none was tested so far.
+</p>
+<a name="configuration"><h3>Toolchain configuration in eLua <span style="color: red;">(WIP)</span></h3></a>
+<p>The <b>eLua</b> build system makes provisions for specifying an unlimited number of toolchains for a given target, selectable via the scons <b>toolchain=...</b> option. The default structure
+ of each of the toolchains supported by default is listed in the table below.</p>
+<table class="table_center">
+<tbody>
+<tr>
+ <th>Toolchain</th>
+ <th style="text-align:center;" rowspan="2">Name</th>
+ <th style="text-align:center;" rowspan="2">Compiler</th>
+ <th style="text-align:center;" rowspan="2">Linker</th>
+ <th style="text-align:center;" rowspan="2">Assembler</th>
+ <th style="text-align:center;" rowspan="2">Size tool</th>
+ <th style="text-align:center;" rowspan="2">Image copy tool</th>
+</tr>
+<tr>
+ <td>Platform</td>
+</tr>
+<tr>
+ <td style="color: rgb(255, 102, 0);">ARM (ELF)</td>
+ <td style="text-align:center;">arm-gcc</td>
+ <td style="text-align:center;">arm-elf-gcc</td>
+ <td style="text-align:center;">arm-elf-ld</td>
+ <td style="text-align:center;">arm-elf-as</td>
+ <td style="text-align:center;">arm-elf-size</td>
+ <td style="text-align:center;">arm-elf-objcopy</td>
+</tr>
+<tr>
+ <td style="color: rgb(255, 102, 0);">ARM (EABI)</td>
+ <td style="text-align:center;">codesourcery</td>
+ <td style="text-align:center;">arm-none-eabi-gcc</td>
+ <td style="text-align:center;">arm-none-eabi-ld</td>
+ <td style="text-align:center;">arm-none-eabi-as</td>
+ <td style="text-align:center;">arm-none-eabi-size</td>
+ <td style="text-align:center;">arm-none-eabi-objcopy</td>
+</tr>
+<tr>
+ <td style="color: rgb(255, 102, 0);">Cortex (ELF)</td>
+ <td style="text-align:center;">arm-gcc</td>
+ <td style="text-align:center;">arm-elf-gcc</td>
+ <td style="text-align:center;">arm-elf-ld</td>
+ <td style="text-align:center;">arm-elf-as</td>
+ <td style="text-align:center;">arm-elf-size</td>
+ <td style="text-align:center;">arm-elf-objcopy</td>
+</tr>
+<tr>
+ <td style="color: rgb(255, 102, 0);">Cortex (EABI)</td>
+ <td style="text-align:center;">codesourcery</td>
+ <td style="text-align:center;">arm-none-eabi-gcc</td>
+ <td style="text-align:center;">arm-none-eabi-ld</td>
+ <td style="text-align:center;">arm-none-eabi-as</td>
+ <td style="text-align:center;">arm-none-eabi-size</td>
+ <td style="text-align:center;">arm-none-eabi-objcopy</td>
+</tr>
+<tr>
+ <td style="color: rgb(255, 102, 0);">AVR32</td>
+ <td style="text-align:center;">avr32-gcc</td>
+ <td style="text-align:center;">avr32-gcc</td>
+ <td style="text-align:center;">avr32-ld</td>
+ <td style="text-align:center;">avr32-s</td>
+ <td style="text-align:center;">avr32-size</td>
+ <td style="text-align:center;">avr32-objcopy</td>
+</tr>
+<tr>
+ <td style="color: rgb(255, 102, 0);">i386</td>
+ <td style="text-align:center;">i686-gcc</td>
+ <td style="text-align:center;">i686-elf-gcc</td>
+ <td style="text-align:center;">i686-elf-ld</td>
+ <td style="text-align:center;">nasm</td>
+ <td style="text-align:center;">i686-elf-size</td>
+ <td style="text-align:center;">i686-elf-objcopy</td>
+</tr>
+</tbody>
+</table>
+
+<p>If you need to add a new toolchain or modify an existing one, take a look at the scons build script (SConstruct). A toolchain-related fragment of SConstruct is shown below:</p>
+<pre><code># List of toolchains
+toolchain_list = {
+ <b># This defines a toolchain with the name "arm-elf"</b>
+ 'arm-gcc' : {
+ 'compile' : 'arm-elf-gcc',
+ 'link' : 'arm-elf-ld',
+ 'asm' : 'arm-elf-as',
+ 'bin' : 'arm-elf-objcopy',
+ 'size' : 'arm-elf-size'
+ },
+ <b># Another toolchain, this time called "codesourcery"</b>
+ 'codesourcery' : {
+ 'compile' : 'arm-none-eabi-gcc',
+ 'link' : 'arm-none-eabi-ld',
+ 'asm' : 'arm-none-eabi-as',
+ 'bin' : 'arm-none-eabi-objcopy',
+ 'size' : 'arm-none-eabi-size'
+ },
+................
+}
+
+# List of platform/CPU/toolchains combinations
+# The first toolchain in the toolchains list is the default one
+# (the one that will be used if none is specified)
+platform_list = {
+ 'at91sam7x' : { 'cpus' : [ 'AT91SAM7X256', 'AT91SAM7X512' ], <b>'toolchains' : [ 'arm-gcc', 'codesourcery' ]</b> },
+ 'lm3s' : { 'cpus' : [ 'LM3S8962', 'LM3S6965', 'LM3S6918' ], <b>'toolchains' : [ 'arm-gcc', 'codesourcery' ]</b> },
+ ................
+}</code></pre>
+<p>From this fragment it's easy to undertand that there are at most two places in SConstruct that must be taken into account when dealing with toolchain:</p>
+<ul>
+ <li>the definition of <b>toolchain_list</b>. This is a list of all the supported toolchains with all their relevant components (compiler, linker, assembler, image copy tool and size tool).</li>
+ <li>each <b>eLua</b> platform has a list of permitted toolchains (only the toolchains specified in this list can be used to build an <b>eLua</b> image for that target). The first element of
+ this list will be automatically used if a <b>toolchain=...</b> option is not specified on the command line.</li>
+</ul>
+<p>Please note that in order to add a new toolchain to <b>eLua</b> it's generally not enough to edit just SConstruct. As different toolchains have different command line options, one should also
+ edit the platform's build configuration file (<i>src/platform/<platform name>/conf.py</i>) and make it aware of the new toolchain. The exact procedure for doing this is highly dependent on
+ the toolchain and it's well beyond the scope of this tutorial.</p>
+$$FOOTER$$
+
Modified: branches/eagle_mmc/doc/pt/tut_bootpc.html
===================================================================
--- branches/eagle_mmc/doc/pt/tut_bootpc.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/pt/tut_bootpc.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,93 +1,53 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
+$$HEADER$$
+<p>É isso mesmo o que você está pensando: depois de seguir esse tutorial, o seu PC irá fazer o <b>boot</b> diretamente de Lua! Não haverá Sistema Operacional lá (isso explica porque o processo de <b>boot</b> é tão rápido), somente você e Lua. Você será capaz de usar o interpretador Lua para escrever os seus programas e até mesmo usar o "dofile" para executar o código Lua.</p>
-<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);"><h3><a name="title" href="http://www.eluaproject.net/en/Booting_your_PC_in_eLua" class="local">Booting your PC in eLua</a></h3>
-
- <div class="content">
+<h2>Detalhes</h2>
-<p>That's right: after following this tutorial, your PC will boot
-directly into Lua! No OS there (this explains why the boot process is
-so fast), just you and Lua. You'll be able to use the regular Lua
-interpreter to write your programs and even use "dofile" to execute Lua
-code.</p>
+<p>
+Fazer o <b>boot</b> com Lua é necessário o uso do <a href="http://www.gnu.org/software/grub/">GRUB</a> para carregar o <a href="http://www.gnu.org/software/grub/manual/multiboot/">multiboot</a> que é um arquivo ELF contendo o nosso código <b>eLua</b>. Como o código <b>eLua</b> e as instruções de como fazer o <b>build</b> ainda não estão disponíveis, vou providenciar um <b>link</b> direto para o arquivo ELF. O código roda em modo protegido, dessa forma você terá acesso a toda memória. O código não possibilita acesso a qualquer dispositivo de armazenamento (HD, CDROM, floppy), ou seja, se você estiver preocupado que isso possa causar algum problema em seu sistema, pode relaxar agora :) Eu somente estou usando um teclado bem básico e "<b>drivers</b>" VGA, mas pode existir um risco de parada no sistema (embora isso seja pouco provável de acontecer).!
Se isso acontecer, tenha certeza de usar o <b>reset</b> por <b>hardware</b>, pois as teclas CTRL+ALT+DEL não são consideradas pelo código. Na dúvida, veja também a próxima seçõo.
+</p>
-<h2>Details</h2>
+<h2>Observação</h2>
-<p>Booting Lua involves using the well known <a href="http://www.gnu.org/software/grub/">GRUB</a> that will be used to load a <a href="http://www.gnu.org/software/grub/manual/multiboot/">multiboot</a>
-compliant ELF file that contains our eLua code. Since the eLua code and
-the build instructions are not available yet, I'll be providing a
-direct link to the ELF file. The code runs in protected mode, so you
-have access to your whole memory. The code does not access any kind of
-storage device (HDD, CDROM, floppy), so if you're worried that it might
-brick your system, you can relax now :) I'm only using some very basic
-keyboard and VGA "drivers", so all you're risking is a system freeze
-(even this is highly unlikely), nothing a good old RESET can't handle
-(be sure to use the hardware reset though, CTRL+ALT+DEL is not handled
-by the code). But just in case, see also the next section.</p>
+<p>
+<strong>Como já mencionado, o código não tentará acessar qualquer tipo de sistema de armazenamento tais como HD, CDROM e floppy, nem mesmo para leitura, dessa forma, você não precisará se preocupar com isso. Também não irá reprogramar os registradores da sua placa de vídeo, logo, esse código não causará qualquer dano a sua placa de vídeo ou ao seu monitor. Ele implementa somente um "driver de teclado em modo protegido", que dessa forma, não pode causar qualquer dano físico ao seu sistema. Em resumo, me esforcei ao máximo para fazer um código tão inofensivo quanto possível. Este código foi testado em 5 diferentes computadores e em 2 emuladores <a href="http://www.virtualbox.org/">VirtualBox</a> e nada de errado aconteceu. Como já foi dito antes, não existe garantia de qualquer espécie. É muito pou!
co provável que algo de errado possa acontecer ao seu sistema, no entanto, caso aconteça, não posso ser responsabilizado.
+</strong></p>
-<h2>Disclaimer</h2>
+<h2>Pré-Requisitos</h2>
-<p><strong>As already mentioned, the code won't try to access any kind
-of storage (HDD, CDROM, floppy), not even for reading, so you don't
-need to worry about that. Also it doesn't try to reprogram your video
-card registers, so it can't harm it or your monitor. It only implements
-a "protected mode keyboard driver" that can't physically damage
-anything in your system. In short, I made every effort to make the code
-as harmless as possible. I tested it on 5 different computers and in 2 <a href="http://www.virtualbox.org/">VirtualBox</a>
-emulators, and nothing bad happened. That said, there are no warranties
-of any kind. In the very unlikely event that something bad does happen
-to your system, you have my sincere sympathy, but I can't be held
-responsible for that.</strong></p>
+<p>Para fazer o <strong>boot</strong> do seu computador em Lua será necessário:</p>
-<h2>Prerequisites</h2>
+<ul>
+<li>um computador com no mínimo uma arquitetura 386 ou maior para rodar *Linux*. Eu testei isto somente em computadores *Pentium*, mas deveria rodar sem problemas em arquitetura 386.</li>
-<p>To boot your computer in Lua you'll need:</p>
+<li><a href="http://www.gnu.org/software/grub/">GRUB</a>. Desde que, você esteja rodando <strong>Linux</strong>, é muito provável que o GRUB já seja o seu <strong>bootloader</strong>. Se não, você deve instalá-lo. Não necessidade de instalar o GRUB no HD; um <strong>floppy</strong>, um pen drive USB ou até mesmo um CDROM irá trabalhar muito bem. Eu não vou tratar neste documento, do procedimento de instalação do GRUB, simplesmente procure no <strong>google</strong> por "install grub on floppy/usb/cdrom" e certamente você irá encontrar o que está procurando. Você pode procurar por exemplos, <a href="http://orgs.man.ac.uk/documentation/grub/grub_3.html">aqui<a>, <a href="http://www.freesoftwaremagazine.com/articles/grub_intro/">aqui</a> ou <a href="http://www.mayrhofer.eu.org/Default.aspx?pageindex=6&pageid=45">aqui</a>.</li>
-<ul><li>a 386 or better computer running Linux. I actually tested
-this only on Pentium class computers, but it should run on a 386
-without problems.</li><li><a href="http://www.gnu.org/software/grub/">GRUB</a>.
-Since you're running Linux, chances are you're already using GRUB as
-your bootloader. If not, you must install it. You don't need to install
-it on your HDD; a floppy, an USB stick or even a CDROM will work as
-well. I won't cover the GRUB installation procedure here, just google
-for "install grub on floppy/usb/cdrom" and you'll sure find what you're
-looking for. You can try for example <a href="http://orgs.man.ac.uk/documentation/grub/grub_3.html">here</a>, <a href="http://www.freesoftwaremagazine.com/articles/grub_intro/">here</a> or <a href="http://www.mayrhofer.eu.org/Default.aspx?pageindex=6&pageid=45">here</a>.</li><li>The eLua ELF file. Download it from <a href="http://elua.berlios.de/surprise">here</a>. OR <a href="http://www.eluaproject.net/en/Downloads">download eLua</a> and compile it for the i386 architecture using a toolchain that you can build by following <a href="http://www.eluaproject.net/en/Building_GCC_for_i386">this tutorial</a>.</li><li>a text editor to edit your GRUB configuration file.</li></ul>
+<li>O arquivo <strong>eLua</strong> ELF i386. Leia as instruções de como obter esse arquivo clicando <a href="http://elua.berlios.de/surprise">aqui</a>. Ou <a href="http://www.eluaproject.net/en/Downloads">baixe os fontes de eLua</a> e compile para a arquitetura i386 usando um toolchain que pode ser criado seguindo as instruções <a href="http://www.eluaproject.net/en/Building_GCC_for_i386">deste tutorial</a>.</li><li>Um editor de texto para alterar o seu arquivo de configuração do GRUB.</li>
+</ul>
+<p>O restante deste tutorial assume que você esteja usando o <strong>Linux</strong> com GRUB alocado em /boot/grub, esse caminho funciona na maioria das distribuições <strong>Linux</strong> (Eu estou usando Ubuntu 8.04).</p>
-<p>The rest of this tutorial assumes that you're using Linux with GRUB,
-and that GRUB is located in /boot/grub, which is true for many Linux
-distributions (I'm using Ubuntu 8.04).</p>
+<h2>Vamos começar</h2>
-<h2>Let's do this</h2>
-
-<p>First, copy the <a href="http://elua.berlios.de/surprise">eLua ELF file</a> to your "/boot" directory:</p>
+<p>
+Primeiro, copiar o <a href="http://elua.berlios.de/surprise">eLua ELF file</a> para o seu diretório "/boot":
+</p>
<pre><code>$ sudo cp surprise /boot<br></code></pre>
-<p>Next you need to add another entry to your GRUB menu file (/boot/grub/menu.lst). Edit it and add this entry:</p>
+<p>Em seguida, adicione outra entrada no menu de configuração do GRUB(/boot/grub/menu.lst). Edite-o e adicione esta entrada:</p>
<pre><code> title Surprise!<br> root (hd0,0)<br> kernel /boot/surprise<br> boot<br></code></pre>
+<p>É possível que seja necessário alterar a linha "root (hd0,0)" acima para se ajustar ao seu <strong>dispositivo de boot</strong>. O melhor caminho para fazer isso é procurar no arquivo menu.lst por uma entrada que faz o <strong>boot</strong> do kernel do seu <strong>Linux</strong>. Deve ficar algo a isto:
+</p>
-<p>You may need to modify the root (hd0,0) line above to match your
-boot device. The best way to do this is to look in the menu.lst file
-for the entry that boots your Linux kernel. It should look similar to
-this:</p>
-
<pre><code> title Ubuntu, kernel 2.6.20-16-generic<br> root (hd0,2)<br> kernel /boot/vmlinuz-2.6.20-16-generic<br> initrd /boot/initrd.img-2.6.20-16-generic<br> savedefault <br></code></pre>
+<p>
+Depois que encontrá-la, simplesmente copie a linha "root (hdx,y)" (root (hd0,2) no exemplo acima) e substitua pela sua nova entrada criada "root (hd0,0)". É isso aí! Agora pode rebootar o seu computador, e quando o menu do GRUB aparecer, escolha "Surprise!". Você pode até mesmo digitar dofile "/rom/bisect.lua" para executar o arquivo de teste "bisect.lua". Aproveite!</p>
-<p>After you find it, simply use the root (hdx,y) line from that entry
-(root (hd0,2) in the example above) in your newly created entry instead
-of root (hd0,0).
-That's it! Now reboot your computer, and when the GRUB boot menu
-appears, choose "Surprise!" from it. You can even type dofile
-"/rom/bisect.lua" to execute the "bisect.lua" test file. Enjoy!
-As usual, if you need more details, you can <a href="http://www.eluaproject.net/en/Contact">contact us</a>.
-Also, if you want to have you own USB stick that boots Lua, let me
-know. If enough people manifest their interest in this, I'll add
-another tutorial on how to do it (I already have an USB stick that
-boots Lua, of course :) ).</p>
-</div></body></html>
\ No newline at end of file
+<p>Se você precisar de mais detalhes, <a href="http://www.eluaproject.net/en/Contact">entre em contato conosco</a>.</p>
+
+<p>Além disso, se você quiser que o seu próprio PenDrive inicialize com Lua, vamos ver. Caso outras pessoas manisfestem o mesmo desejo, incluirei outro tutorial descrevendo como fazer isto (É claro que já tenho um PenDrive que da boot com Lua :) ).
+</p>
+$$FOOTER$$
Modified: branches/eagle_mmc/doc/pt/tut_bootstick.html
===================================================================
--- branches/eagle_mmc/doc/pt/tut_bootstick.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/pt/tut_bootstick.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,25 +1,17 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
-
-<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);"><h3><a name="title" href="http://www.eluaproject.net/en/Booting_eLua_from_a_stick" class="local">Booting eLua from a stick</a></h3>
-
- <div class="content">
-
-<p>This is follow up of <a href="http://www.eluaproject.net/en/Booting_your_PC_in_eLua">this tutorial</a>.
-After completing it you'll be able to boot eLua directly from your USB
+$$HEADER$$
+<h3>Booting eLua from an USB stick</h3>
+<p>This is follow up of <a href="tut_bootpc.html">this tutorial</a>.
+After completing it you'll be able to boot <b>eLua</b> directly from your USB
stick (provided, of course, that your computer can boot from an USB
stick, which is true for most computers nowadays). You might want to
-check the <a href="http://www.eluaproject.net/en/Booting_your_PC_in_eLua">boot your PC in eLua</a>
+check the <a href="tut_bootpc.html">boot your PC in eLua</a>
tutorial first for more details. If you have an old USB stick that you
don't use anymore, and/or the shear geekness of this idea makes you
feel curious, this tutorial is definitely for you :)</p>
-<h2>Disclaimer</h2>
+<h2 style="background-color: orangered;">Disclaimer</h2>
-<p><strong>As mentioned <a href="http://www.eluaproject.net/en/Booting_your_PC_in_eLua">here</a>,
+<p>As mentioned <a href="tut_bootpc.html">here</a>,
the code won't try to access any kind of storage (HDD, CDROM, floppy),
not even for reading, so you don't need to worry about that. Also it
doesn't try to reprogram your video card registers, so it can't harm it
@@ -33,25 +25,30 @@
responsible for that. Also, I can't be held responsible if you mess up
your HDD by failing the GRUB installation procedure (even though, once
again, this shouldn't be possible unless you really insist on messing
-it up). If you're new to computers, this tutorial might not be for you.
-Your call.</strong></p>
+it up). If you're new to computers or Linux, this tutorial might not be for you.
+Your call.</p>
<h2>Prerequisites</h2>
-<p>To have your own bootable eLua USB stick you'll need:</p>
+<p>To have your own bootable <b>eLua</b> USB stick you'll need:</p>
<ul><li>an USB stick. I tested this on an 128M USB stick, because
it's the smallest I could find. You should be OK with a 4M stick or
-even a 2M stick</li><li>a computer running Linux. I use Ubuntu, but any other distribution is fine.</li><li><a href="http://www.gnu.org/software/grub/">GRUB</a>.
+even a 2M stick</li>
+<li>a computer running Linux. I use Ubuntu, but any other distribution is fine.</li>
+<li><a href="http://www.gnu.org/software/grub/">GRUB</a>.
Since you're running Linux, chances are you're already using GRUB as
your bootloader. If not, you must install it on your HDD, or at least
know how to install it directly on the USB stick. I won't go into
details here, google it and you'll find lots of good articles about
-GRUB. This tutorial assumes that you're using GRUB as your bootloader.</li><li>The eLua ELF file. Download it from <a href="http://elua.berlios.de/surprise">here</a>. OR <a href="http://www.eluaproject.net/en/Downloads">download eLua</a> and compile it for the i386 architecture using a toolchain that you can build by following <a href="http://www.eluaproject.net/en/Building_GCC_for_i386">this tutorial</a>.</li><li>a text editor to edit your GRUB configuration file.</li></ul>
+GRUB. This tutorial assumes that you're using GRUB as your bootloader.</li>
+<li>The <b>eLua</b> i386 ELF file, see <a href="downloads.html">here</a> for instructions on how to obtain it. OR <a href="downloads.html">download the eLua source distribution</a> and compile it
+ for the i386 architecture using a toolchain that you can build by following <a href="tc_386.html">this tutorial</a>.</li>
+<li>a text editor to edit your GRUB configuration file.</li></ul>
<p>The rest of this tutorial assumes that you're using Linux with GRUB,
-and that GRUB is located in /boot/grub, which is true for many Linux
+and that GRUB is located in <i>/boot/grub</i>, which is true for many Linux
distributions.</p>
<h2>Backup your stick</h2>
@@ -65,39 +62,70 @@
chances are you'll need to re-partition and re-format your stick before
installing GRUB on it. The problem is that many sticks have a very
creative, non-standard partition table, and GRUB doesn't like that. I
-looked at the partition table on my eLua USB stick, and it scared me to
+looked at the original partition table of my <b>eLua</b> USB stick and it scared me to
death, so I had to follow this procedure. In short, you'll need to
delete all the partitions from your stick, create a new partition, and
-then format it. For a step by step tutorial check here.</p>
+then format it. For a step by step tutorial check <a href="http://www.4p8.com/eric.brasseur/suse9.1_usb_stick.html">here</a>.</p>
<h2>Install GRUB on your stick</h2>
-<p>First, mount your freshly formatted stick (I'm going to assume that the mount directory is /mnt):</p>
+<p>First, mount your freshly formatted stick (I'm going to assume that the mount directory is <i>/mnt</i>):</p>
-<pre><code> $ sudo mount /dev/sda1 /mnt<br></code></pre>
+<pre><code>$ sudo mount /dev/sda1 /mnt<br></code></pre>
-
-<p>(of course, you'll need to change /dev/sda1 to reflect the physical location of your USB stick).
+<p>(of course, you'll need to change <i>/dev/sda1</i> to reflect the physical location of your USB stick. You should know the physical location from the previous step).
Then copy the required GRUB files to your stick:</p>
-<pre><code> $ cd /mnt<br> $ mkdir boot<br> $ mkdir boot/grub<br> $ cd /boot/grub<br> $ cp stage1 fat_stage1_5 stage2 /mnt/boot/grub<br></code></pre>
+<pre><code>$ cd /mnt
+$ mkdir boot
+$ mkdir boot/grub
+$ cd /boot/grub
+$ cp stage1 fat_stage1_5 stage2 /mnt/boot/grub</code></pre>
+<p>Copy the <b>eLua</b> ELF file (<i>elua_lua_i386.elf</i> in this example, change the name if needed) to the GRUB directory as well:</p>
-<p>Copy the <a href="http://elua.berlios.de/surprise">eLua ELF file</a> to the GRUB directory as well:</p>
+<pre><code>$ cp elua_lua_i386.elf /mnt/boot/grub</code></pre>
-<pre><code> $ cp surprise /mnt/boot/grub<br></code></pre>
+<p>Create a <i>menu.lst</i> file for GRUB with you favorite text editori (I'm using vim):</p>
+<pre><code>$ cd /mnt/boot/grub
+$ vim menu.lst
+ title eLua
+ root (hd0,0)
+ kernel /boot/grub/elua_lua_i386.elf
+ boot</code></pre>
-<p>Create a menu.lst file for GRUB with you favorite text editor (I'm using joe):</p>
+<p>Now it's time to actually install GRUB on the stick.</p>
-<pre><code> $ cd /mnt/boot/grub<br> $ joe menu.lst<br> title Surprise!<br> root (hd0,0)<br> kernel /boot/grub/surprise<br> boot<br></code></pre>
+<pre><code>$ sudo -s -H
+# grub
-<p>Now it's time to actually install GRUB on the stick.</p>
+<b>Now we need to find the GRUB name of our USB stick. We'll use the "find" command from
+GRUB and our eLua ELF file to accomplish this:</b>
-<pre><code> $ sudo -s -H<br> # grub<br> Now we need to find the GRUB name of our USB stick. We'll use the "find" command from<br> GRUB and our "surprise" file to accomplish this:<br><br> grub> find /boot/grub/surprise<br> (hd2,0)<br><br> GRUB should respond with a single line (like (hd2,0) above). If it gives you more <br> than one line, something is wrong. Maybe you also installed eLua on your HDD? If so, <br> delete the /boot/grub/surprise file from your HDD and try again.<br> You might get a different (hdx,y) line. If so, just use it instead of (hd2,0) in the rest of <br> this tutorial.<br><br> grub> root (hd2,0)<br> grub> setup (hd2)<br> Checking if "/boot/grub/stage1" exists... yes<br> Checking if "/boot/grub/stage2" exists... yes<br> Checking if "/boot/grub/fat_stage1_5" exists... yes<br> Running "embed /boot/grub/fat_stage1_5 (hd2)"... 15 sectors are embedded.<br> succeeded<br> Running "install /boot/grub/stage1 (hd2) (hd2)1+15 p (h!
d2,0)/boot/grub/stage2<br> /boot/grub/menu.lst"... succeeded<br> Done. <br> grub> quit<br></code></pre>
+grub> find /boot/grub/elua_lua_i386.elf
+(hd2,0)
+<b>GRUB should respond with a single line (like (hd2,0) above). If it gives you more
+than one line, something is wrong. Maybe you also installed eLua on your HDD? If so,
+delete the /boot/grub/elua_lua_i386.elf file from your HDD and try again.
+You might get a different (hdx,y) line. If so, just use it instead of (hd2,0) in the
+rest of this tutorial</b>.
+grub> root (hd2,0)
+grub> setup (hd2)
+ Checking if "/boot/grub/stage1" exists... yes
+ Checking if "/boot/grub/stage2" exists... yes
+ Checking if "/boot/grub/fat_stage1_5" exists... yes
+ Running "embed /boot/grub/fat_stage1_5 (hd2)"... 15 sectors are embedded.
+ succeeded
+ Running "install /boot/grub/stage1 (hd2) (hd2)1+15 p (hd2,0)/boot/grub/stage2
+ /boot/grub/menu.lst"... succeeded
+ Done.
+grub> quit</code></pre>
+
<p>That's it! Now reboot your computer, make sure that your BIOS is set
-to boot from USB, and enjoy! You can even type dofile "/rom/bisect.lua"
-to execute the "bisect.lua" test file.
-As usual, if you need more details, you can <a href="http://www.eluaproject.net/en/Contact">contact us</a>.</p>
-</div></body></html>
\ No newline at end of file
+to boot from USB, and enjoy! See <a href="using.html">using eLua</a> for
+instructions on how to use your new toy :).</p>
+<p>As usual, if you need more details, you can <a href="overview.html#contacts">contact us</a>.</p>
+$$FOOTER$$
+
Modified: branches/eagle_mmc/doc/pt/tut_openocd.html
===================================================================
--- branches/eagle_mmc/doc/pt/tut_openocd.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/pt/tut_openocd.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,212 +1,114 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
+$$HEADER$$
+<h2>Downloads</h2>
-<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);"><h3><a name="title" href="http://www.eluaproject.net/en/Using_OpenOCD" class="local">Using OpenOCD</a></h3>
-
- <div class="content">
+<p>Se você preferir ignorar a longa e entediante introdução sobre o OpenOCD e ir direto para a área de download dos scripts do OpenOCD, clique nos links abaixo:</p>
-<h2>Quick downloads</h2>
+<ul><li><p><a href="http://www.eluaproject.net/en/Using_OpenOCD?p=Using_OpenOCD#str9files">Arquivos de configuração para STR9-comStick</a></p></li><li><p><a href="http://www.eluaproject.net/en/Using_OpenOCD?p=Using_OpenOCD#lpc2888files">Arquivos de configuração para LPC2888</a></p></li><li><p><a href="http://www.eluaproject.net/en/Using_OpenOCD?p=Using_OpenOCD#str7files">Arquivos de configuração para STR7</a></p></li></ul>
-<p>If you'd rather skip the long and boring OpenOCD introduction and
-skip directly to the OpenOCD script downloads, use the links below.</p>
+<h2>Sobre OpenOCD</h2>
+<p>
-<ul><li><p><a href="http://www.eluaproject.net/en/Using_OpenOCD?p=Using_OpenOCD#str9files">Configuration files for STR9-comStick</a></p></li><li><p><a href="http://www.eluaproject.net/en/Using_OpenOCD?p=Using_OpenOCD#lpc2888files">Configuration files for LPC2888</a></p></li><li><p><a href="http://www.eluaproject.net/en/Using_OpenOCD?p=Using_OpenOCD#str7files">Configuration files for STR7</a></p></li></ul>
+<a href="tut_openocd.html">OpenOCD</a> é uma ferramenta de código aberto que pode ser usada para conectar CPU's de interface <a href="http://en.wikipedia.org/wiki/JTAG">JTAG</a>. O uso do OpenOCD com uma conexão física JTAG permite a gravação da memória flash (on-chip) de sua CPU (ou carregar o código diretamente para a memória RAM), a leitura da memória interna da CPU (Flash / RAM) e o uso da <a href="http://sourceware.org/gdb/">gdb</a> para depurar o seu código. É desnecessário afirmar que esta é uma ferramenta muito útil (e especialmente quando a sua CPU for montada em volta de um núcleo ARM, uma vez que, neste caso, é quase certo existir uma interface JTAG que você; pode usar). Dito isto, se o seu único objetivo é gravar o seu firmware, sugiro se possível, que evite usar o OpenOCD. Não é fácil aprender a !
usá-la adequadamente, por ser uma ferramenta de linha de comando que utiliza configuração de arquivos com muitos parâmetros diferentes, e isso certamente leva tempo para acostumar. Pior, parece que não é muito bem documentada. Na wiki existem poucas informações sobre os parâmetros de configuração, no entanto, existem alguns bons tutoriais de OpenOCD na internet, mas nenhum deles consegue ser completo. E a sintaxe (e mesmo alguns comandos) parece mudar entre versões, o que torna as coisas ainda mais difíceis. É por isso que geralmente uso uma outra ferramenta para grava&cceidl;ão de firmware, quando disponível, e uso o OpenOCD apenas quando não encontro um bom gravador de firmware. Entretanto, se você precisa depurar o seu código, provavelmente você vai precisar usar o OpenOCD, uma vez que as alternativas não são baratas.
+Para resumir, você pode esquecer OpenOCD quando:</p>
-<h2>About OpenOCD</h2>
+<ul>
+<li><p> o fabricante de sua CPU fornece um programa para gravação em firmware. Certamente este é o caso, porém na maioria das vezes esses programas funcionam somente para Windows;</p></li>
+<li><p> precisa depurar o seu código, porém você já tem uma boa noção sobre onde pode estar o seu problema. Neste caso, simplesmente conecte um LED na porta PIO e ligue-o e desligue-o em vários pontos do seu código até localizar exatamente a origem do seu problema. Não me lembro qual foi a última vêz que usei gdb para depuração, pois "depuração com LED" foi da única coisa que precisei.</p></li>
+</ul>
-<p><a href="http://elua.berlios.de/tut_openocd.html">OpenOCD</a> is an open source tool that can be used to connect to a CPU's <a href="http://en.wikipedia.org/wiki/JTAG">JTAG</a>
-interface. Using OpenOCD and a physical JTAG connection allows you to
-burn the on-chip flash memory of your CPU (or to load your code
-directly to RAM), to read the internal CPU memory (Flash/RAM) and to
-use <a href="http://sourceware.org/gdb/">gdb</a> to debug your code.
-Needless to say, this is a very handy tool (and especially handy if
-your CPU happens to be built around an ARM core, since in this case you
-can be almost certain that it has a JTAG interface that you can use).
-That said, if your only goal is to burn your firmware, my personal
-suggestion is to avoid using OpenOCD if possible. It has quite a steep
-learning curve, because it is a command line tool that uses
-configuration files with lots of different parameters, and this takes a
-while to get used to. Worse, I feel that it is not very well
-docummented. The project's wiki does give a few good pointers about all
-the configuration parameters, and there are some good OpenOCD tutorials
-out there, but none of them tells the whole story. And the syntax (and
-even some commands) seems to change slightly between releases, which
-makes things even more confusing. This is why I generally choose to use
-a different firmware burning tool when available, and resort to OpenOCD
-only for targets that lack a proper firmware burning tool. If you need
-to debug your code, however, you probably want to use OpenOCD, since
-the alternatives aren't cheap.
-To summarize, you can forget about OpenOCD when:</p>
+<p>Por outro lado, você provavelmente usar´ OpenOCD quando:</p>
-<ul><li><p>your CPU manufacturer provides a special tool for
-firmware burning. This is quite often the case, but more often that not
-the forementioned tools work only in Windows.</p></li><li><p>you
-must debug your code, but you have a good intuition about where the
-problem is located. In this case, simply connecting a LED to a PIO port
-and turning it on and off from different parts of your code until you
-figure out exactly what's the problem can work wonders. I can't
-remember when was the last time I used gdb for debugging, since "LED
-debugging" was all I needed. </p></li></ul>
+<ul>
+<li><p>seu fabricante de sua CPU não fornecer uma programa para gravação em firmware (ou quando é fornecido, este não é o que você precisa);</p></li>
+<li><p>você está usando Linux, MacOS ou outro sistema operacional que não é suportado pelo programa fornecido pelo fabricante;</p></li>
+<li><p>você precisa realizar difíceis depurações a fim de tentar entender o que existe de errado com a sua aplicação.</p></li>
+</ul>
-<p>On the other hand, you should probably use OpenOCD when:</p>
+<p>Afinal, se você resolveu não utilzar o OpenOCD, agora é hora de abandonar esta página e se previnir de possíveis problemas. Caso você precise do OpenOCD, então continue lendo e tentarei tornar este tutorial o menos complicado possível. Entretanto, não espere que este tutorial esgote o assunto sobre OpenOCD, pois não é, minha intenção é dar a você informações suficientes para usar o OpenOCD para gravar eLua na sua placa. Portanto, não citarei aqui qualquer informação sobre depuração usando OpenOCD, somente gravação de firmware. E, antes de começarmos, por favor leia o aviso abaixo.</p>
-<ul><li><p>your CPU manufacturer doesn't provide a special tool for firmware burning (or it does, but it's not what you need).</p></li><li><p>you're using Linux, MacOS or another OS that is not supported by the firmware burning tool.</p></li><li><p>you need to do some serious debugging in order to understand what's wrong with your application.</p></li></ul>
+<p>AVISO: o uso inapropriado do OpenOCD pode causar um comportamento inesperado de sua CPU. Apesar da remota possibilidade de danificar fisicamente a sua CPU devido ao uso do OpenOCD, você pode acabar travando o seu chip, pode apagar uma área de memória que não poderia ser apagada, ou pode até desabilitar a interface JTAG (tornando-a inútil). Se você alterar os scripts fornecidos pelo tutorial, por favor, certifique-se do está fazendo. Além disso, não sou um especialista em OpenOCD, meus arquivos de configuração foram testados, no entanto podem conter erros. Resumindo, este tutorial não possui garantias de funcionamento.</p>
-<p>If you decided that you don't need OpenOCD after all, now it's a
-good time to navigate away from this page and save yourself from some
-possible symptoms of headache. If you need OpenOCD, read on, I'll try
-to make this as painless as possible. However, don't expect this to be
-a full tutorial on OpenOCD, because it's not; my intention is to give
-you just enough data to use OpenOCD for burning eLua on your board.
-Because of this, I won't be covering debugging with OpenOCD here, just
-firmware burning. And, before we begin, please read and understand the
-next paragraph.</p>
+<h2>Obtendo o OpenOCD</h2>
-<p>DISCLAIMER: using OpenOCD improperly may force your CPU to behave
-unexpectedly. While physically damaging your CPU as a result of using
-OpenOCD is very hard to accomplish, you might end up with a locked
-chip, or you might erase a memory area that was not supposed to be
-erased, you might even disable the JTAG interface on your chip (thus
-rendering it unusable). If you modify the configuration scripts that
-I'm going to provide, make sure that you know what you're doing. Also,
-I'm not at all an OpenOCD expert, so my configuration scripts might
-have errors, even though I tested them. In short, this tutorial comes
-without any guarantees whatsoever.</p>
-<h2>Getting OpenOCD</h2>
+<p>Caso você utilize Windows, o melhor site para baixar o OpenOCD compilado e pronto para usar é o <a href="http://www.yagarto.de/">Yagarto home page</a>. Este site fornece um instalador muito bom, e parece manter o mesmo padrão de evolução do OpenOCD (as versões do site Yagarto não são as mais recentes, mas estão quase sempre atualizadas). No entanto, se você usa Linux, poderá usar o apt-get ou o pacote gerenciador de sua distribuição:</p>
-<p>If you're on Windows, the best place to get OpenOCD already compiled and ready to run is to visit the <a href="http://www.yagarto.de/">Yagarto home page</a>.
-They provide a very nice OpenOCD installer, and they seem to keep up
-with OpenOCD progress (the versions on the Yagarto site are not
-"bleeding edge", but there are quite fresh nevertheless). If you're on
-Linux, you can always use apt-get or your distribution-specific package
-manager:</p>
-
<pre><code>$ sudo apt-get install openocd<br></code></pre>
+<p>Parece que a coisa não é bem assim: a versão do OpenOCD que baixei pelo apt-get é do dia 5/9/2007, enquanto a versão do site Yagarto é do dia 19/6/2008. Já que estou usando o OpenOCD para Windowns (devido ao Ubuntu 8.04 não detectar direito o meu adaptador USB-to-JTAG), minhas instruções são relevantes para a versão do Yagarto. Como foi dito na introdução, a função e os parâmetros de comandos diferentes podem variar entre uma versão e outra do OpenOCD, logo, se você deseja utilizar a versão do Yagarto em seu sistema não-Windows, terá que montá-la a partir dos fontes (veja abaixo). A principal fonte de pequisa sobre como montar o OpenOCD a partir dos programa fontes é o site <a href="http://openfacts.berlios.de/index-en.phtml?title=Building_OpenOCD">OpenOCD build page</a> encontrado na wiki OpenOCD. Al&eacut!
e;m desse site, existe um outro bom tutorial localizado em <a href="http://forum.sparkfun.com/viewtopic.php?t=11221">aqui</a>. Não irei fornecer as instruções para montagem, pois os dois links mencionados acima tratam muito bem do assunto, e além disso, o processo de montagem é relativamente simples. Entretanto, como os tutoriais explicam como montar baseados na última versão do OpenOCD, você precisará fazer uma pequena modificação para a versão do site Yagarto. A modificação se dá na etapa de verificação do SVN. Substitua este comando:</p>
-<p>There is a catch here though: the OpenOCD version that I get from
-apt-get is dated 2007-09-05, while the Yagarto OpenOCD version is from
-2008-06-19. Since I'm using OpenOCD from Windows (because Ubuntu 8.04
-doesn't seem to handle my USB-to-JTAG adapters very well), my
-instructions are relevant to the Yagarto version. As mentioned in the
-introduction, the meaning and parameters of different commands might
-change between OpenOCD version, so if you want to use the Yagarto
-version on your non Windows system, you'll have to build it from source
-(see below).
-The main resource on how to build OpenOCD from source is the <a href="http://openfacts.berlios.de/index-en.phtml?title=Building_OpenOCD">OpenOCD build page</a> from the OpenOCD wiki. Also, a very good tutorial can be found <a href="http://forum.sparkfun.com/viewtopic.php?t=11221">here</a>.
-I'm not going to provide step by step build instructions, since the two
-links that I mentioned cover this very well, and the build process is
-relatively straightforward. However, since both tutorials describe how
-to build the bleeding edge version of OpenOCD, you'll need a slight
-modification do build the Yagarto version instead. The modification is
-in the SVN checkout step. Replace this step:</p>
-
<pre><code>$ svn checkout svn://svn.berlios.de/openocd/trunk<br></code></pre>
+<p>Por este ('717' é uma revisão SVN do Yagarto OpenOCD):</p>
-<p>With this step ('717' is the SVN revision of the Yagarto OpenOCD build):</p>
-
<pre><code>$ svn checkout -r 717 svn://svn.berlios.de/openocd/trunk<br></code></pre>
+<p>Continue as instruções restantes, e ao final você terá o OpenOCD funcionando.</p>
-<p>Follow the rest of the build instructions, and in the end you should have a working OpenOCD.</p>
-<h2>Supported targets</h2>
+<h2>CPUs suportadas</h2>
-<p>I couldn't find a good page with a list of the targets that are
-supported by OpenOCD. So, if you want to check if your particular CPU
-is supported by OpenOCD, I recommend getting the latest sources (as
-described in the previous section) and listing the
-trunk/src/target/target directory:</p>
+<p>Não encontrei nenhum site que mostrasse alguma lista de dispositivos suportados pelo OpenOCD. Logo, se você deseja verificar se sua CPU funciona com o OpenOCD, recomendo baixar os fontes mais recentes (como descrito na seção anterior) e faça uma listagem do diretório trunk/src/target/target:</p>
<pre><code>$ ls trunk/src/target/target<br> at91eb40a.cfg<br> at91r40008.cfg<br> cfi.c<br> ....<br> str9comstick.cfg<br> ....<br></code></pre>
-<p>If this listing has something that looks like your CPU name, you're
-in luck. OpenOCD has support for LPC from NXP, AT91SAM cfrom Atmel,
-STR7/STR9 from ST, and many others.</p>
-<h2>Using OpenOCD</h2>
+<p>Caso esta listagem contenha algo que pareça com a sua CPU, você é um cara de sorte. OpenOCD funciona com o LPC da NXP, AT91SAM da Atmel, STR7/STR9 da ST, e muitos outros.</p>
-<p>To use OpenOCD, you'll need:</p>
+<h2>Usando o OpenOCD</h2>
-<ul><li>the OpenOCD executable, as described above</li><li>a board with a JTAG interface</li><li>a JTAG adapter</li></ul>
+<p>Para usar o OpenOCD, você precisará de:</p>
+<ul>
+<li>o executável do OpenOCD, como descrito acima</li>
+<li>uma placa com uma interface JTAG</li>
+<li>um adaptador JTAG</li>
+</ul>
-<p>In some cases, your CPU board might provide a built in JTAG adapter. For example, my <a href="http://www.luminarymicro.com/products/lm3s8962_can_ethernet_evaluation_kit.html">LM3S8962</a>
-board provides both an USB-to-JTAG and an USB-to-serial converter built
-on board, switching between them automatically. The same is true for my
-<a href="http://www.hitex.com/index.php?id=383">STR9-comStick</a>. On the other hand, my <a href="http://www.olimex.com/dev/sam7-ex256.html">SAM7-EX256</a> board has only a JTAG connector, I need a separate JTAG adapter to connect to it. I'm using <a href="http://www.olimex.com/dev/arm-usb-tiny.html">ARM-USB-TINY</a> from Olimex, but there are other affordable USB-to-JTAG adapters out there, like the Amontec <a href="http://www.amontec.com/jtagkey-tiny.shtml">JTAGKey-Tiny</a>. Not to mention that you can <a href="http://www.hs-augsburg.de/%7Ehhoegl/proj/usbjtag/usbjtag.html">build your ownt</a>.
-Although USB is my interface of choice, you'll find JTAG adapters for
-PC LPT ports too. The good news is that once you buy a JTAG adapter,
-chances are that it will work with many boards with different CPUs,
-since the JTAG connector layout is standardized and the JTAG adapters
-are generally able to work with different voltages.
-To actually use OpenOCD, you'll need a configuration file. The
-configuration file is the one that lets OpenOCD know about your setup,
-such as:</p>
+<p>Em alguns casos, a placa da sua CPU já vem com um adaptador embutido. Por exemplo, a minha <a href="http://www.luminarymicro.com/products/lm3s8962_can_ethernet_evaluation_kit.html">LM3S8962</a> já vem com os adaptadores USB-JTAG e USB-serial, alternando-se automaticamente. O mesmo acontece com a minha <a href="http://www.hitex.com/index.php?id=383">STR9-comStick</a>. Entretanto, no caso da minha <a href="http://www.olimex.com/dev/sam7-ex256.html">SAM7-EX256</a>, só existe um conector JTAG, logo, preciso de um adaptador JTAG separado para conectá-lo. Estou usando o <a href="http://www.olimex.com/dev/arm-usb-tiny.html">ARM-USB-TINY</a> da Olimex, porém existem adaptadores USB-JTAG de outros fabricantes disponíveis no mercado, como o Amontec <a href="http://www.amontec.com/jtagkey-tiny.shtml">JTAGKey-Tiny</a>. Além disso, você pode <a href="http://www.hs-augsburg.de/%7Ehhoegl/proj/usbjtag/usbjtag.html">constuir seu pr&o!
acute;prio adptador</a>. Apesar de preferir trabalhar com a interface USB, você encontrará também adaptadores para portas LPT. O interessante é que, quando você compra um adaptador JTAG, muito provavelmente, este funcionará com muitas placas usando diferentes CPUs, pois o layout do conector JTAG é padrão e a maioria dos adpatadores JTAG estão prontos para funcionar em diferentes voltagens.
+Na verdade, para usar o OpenOCD, você precisará de um arquivo de configuração. O arquivo de configuração serve para o OpenOCD conhecer a composição do seu hardware, tais como:</p>
<pre><code>* the kind of JTAG interface that you're using.<br>* the actual hardware platform you're using (ATM7TDMI, ARM966 and others).<br>* the memory configuration of your CPU (flash banks).<br>* the script used to program the flash memory.<br></code></pre>
-<p>Presenting a list of all the possible configuration options and
-their meaning is way beside the scope of this document, so I'm not
-going to do it, I'll give an example instead. For the example I'm going
-to use parts of my STR-comStick configuration file (comstick.cfg)
-adapted from the OpenOCD distribution and from other examples (don't
-worry, I'll provide full download links for this file later on). First
-we need to tell OpenOCD that we're using a the STR9-comStick
-USB-to-JTAG adapter:</p>
+<p>Apresentar uma lista com toda as opções de possíveis configurações e os seus respectivos significados, está muito além do escopo deste documento, logo não irei fazer isto, apresentarei exemplos. Para exemplificar, usarei trechos do meu arquivo de configuração da STR-comtick (comstick.cfg) adaptado da distribuição OpenOCD e de outros exemplos (não se preocupe, todos os links para os arquivos citados são fornecidos neste tutorial). Primeiramente, precisamos avisar ao OpenOCD que estamos usando um adaptador STR9-comstick USB-JTAG:</p>
<pre><code>interface ft2232<br>ft2232_device_desc "STR9-comStick A"<br>ft2232_layout comstick<br>ft2232_vid_pid 0x0640 0x002C<br>jtag_speed 4<br>jtag_nsrst_delay 100<br>jtag_ntrst_delay 100<br></code></pre>
+<p>Além disso, o OpenOCD precisa ser informado sobre qual a arquitetura que será usada e o layout de memória:</p>
-<p>Also, OpenOCD needs to know what's our target and its memory layout:</p>
-
<pre><code>target arm966e little run_and_init 1 arm966e<br>run_and_halt_time 0 50<br><br>working_area 0 0x50000000 32768 nobackup<br><br>flash bank str9x 0x00000000 0x00080000 0 0 0<br>flash bank str9x 0x00080000 0x00008000 0 0 0 <br></code></pre>
+<p>As instruções acima, dizem ao OpenOCD que a qrquitetura utilizada é a ARM966-E sendo executado no modo endian, com dois bancos de memória flash, o primeiro iniciando em 0x0 com 0x80000 bytes de tamanho e o outro iniciando em 0x80000 e com 0x80000 byte de tamanho. Finalmente, o OpenOCD deve saber qual o nome do arquivo de script (este é o arquivo usado para fisicamente programar a memória da CPU):
+</p>
-<p>This tells OpenOCD that our target is an ARM966-E running in little
-endian mode, with two flash memory banks, one that starts at 0x0 and
-it's 0x80000 bytes in size, and another one that starts at 0x80000 and
-it's 0x8000 bytes in size. Finally, OpenOCD must know what's the name
-of our script file (this is the file that is used to pysically program
-the CPU memory):</p>
-
<pre><code>#Script used for FLASH programming<br>target_script 0 reset str91x_flashprogram.script<br></code></pre>
-<p>The contents of the str91x_flashprogram.script is very target-dependent:</p>
+<p>O conteúdo do arquivo str91x_flashprogram.script é específico e depende diretamente da arquitetura utilizada:</p>
<pre><code>wait_halt<br>str9x flash_config 0 4 2 0 0x80000<br>flash protect 0 0 7 off<br>flash erase_sector 0 0 7<br>flash write_bank 0 main.bin 0<br>reset run<br>sleep 10<br>shutdown<br></code></pre>
+<p>Também não vou tentar explicar os comandos acima :) Basicamente, eles desprotegem a memória flash, apaga-a, gravam nela o conteúdo do arquivo "main.bin" e em seguida reinicia a CPU. Caso você precise gravar um arquivo com um nome diferente, modifique apenas o "main.bin" na linha de comando "flash write_bank". Para realizar tudo isso, é necessário avisar ao OpenOCD para utilizar o nosso arquivo de configuração:
+</p>
-<p>I'm not even going to attempt to explain this one :) Basically it
-unprotects the flash, erases it, writes the contents of "main.bin" to
-flash, and then resets the CPU. If you need to flash a file with a
-different name, the only thing you need to modify is the "main.bin" in
-the "flash write_bank" line.
-To use all this, you need to tell OpenOCD to use our configuration file:</p>
-
<pre><code>openocd-ftd2xx -f comstick.cfg<br></code></pre>
+<p>(nota: no Windows, o nome do arquivo executável do OpenOCD é "openocd-ftd2xx". No Linux é simplesmente "openocd". Substitua-o pelo no do seu executável.) Este é o fim do seu curso relâmpago de OpenOCD. É claro que existe muito mais para se aprender, portanto aqui vai uma lista de links com mais informações sobre esta matéria:</p>
-<p>(note: under Windows, the OpenOCD executable name is often
-"openocd-ftd2xx". Under Linux it's simply "openocd". Replace it with
-the actualy name with your executable.)
-That's it for your OpenOCD crash course. I realise that there's much
-more to learn, so here's a list of links with much better information
-on the subject:</p>
+<ul>
-<ul><li><a href="http://www.hs-augsburg.de/%7Ehhoegl/proj/openocd/oocd-quickref.pdf">OpenOCD quick reference</a> card. (slightly outdated)</li><li>A very good OpenOCD tutorial.</li><li><a href="http://openfacts.berlios.de/index-en.phtml?title=OpenOCD_scripts">OpenOCD configuration examples</a> from the official OpenOCD wiki.</li><li>An excellent page about using <a href="http://www.siwawi.arubi.uni-kl.de/avr_projects/arm_projects/openocd_intro/index.html">OpenOCD with ARM controllers</a>, with lots of real life examples.</li><li>An interesting <a href="http://forum.sparkfun.com/viewtopic.php?p=42079">topic on the SparkFun forum</a> about STR9 and OpenOCD.</li></ul>
+<li><a href="http://www.hs-augsburg.de/%7Ehhoegl/proj/openocd/oocd-quickref.pdf">Cartela para consulta rápida do OpenOCD</a>. (pouco desatualizado)</li>
+<li>Um tutorial muito bom.</li>
+<li><a href="http://openfacts.berlios.de/index-en.phtml?title=OpenOCD_scripts">Exemplos de configuração</a> da página oficial da wiki do OpenOCD.</li>
+<li>Uma página excelente sobre o uso do <a href="http://www.siwawi.arubi.uni-kl.de/avr_projects/arm_projects/openocd_intro/index.html">OpenOCD com controladores ARM</a>, contendo muitos exemplos práticos.</li>
+<li>Um interessante <a href="http://forum.sparkfun.com/viewtopic.php?p=42079">tópico no fórum do SparkFun</a> sobre STR9 e OpenOCD.</li>
+</ul>
<p><a name="str9files"></a></p>
-<h2>Configuration files for STR9-comStick</h2>
+<h2>Arquivos de configuração para o STR9-comStick</h2>
-<p>Download them below:</p>
+<p>Faça o download deles abaixo:</p>
<p><a href="http://elua.berlios.de/other/comstick.cfg">comstick.cfg</a></p>
@@ -216,48 +118,28 @@
<p><a href="http://elua.berlios.de/other/str91x_reset.script">str91x_reset.script</a></p>
-<p>The comstick.cfg configuration file is for prorgramming the
-STR9-comStick. comrst.cfg is for resetting it. The comStick has a very
-interesting habit: after you power it (via USB) it does not start
-executing the code from the internal flash, you need to execute OpenOCD
-with the comreset.cfg script to start it. This script does exactly what
-it says: executes a CPU reset (since the board doesn't have a RESET
-button). This is a very peculiar behaviour, and I'm not sure if it's
-generic or it's only relevant to my particular comStick. I suspect that
-the CPU RESET line isn't properly handled by the on-board USB-to-JTAG
-converter, and the only solution I have for this is to execute this
-script everytime you power the board and everytime you need to do a
-RESET.</p>
+<p>O arquivo de configuração comstick.cfg serve para programar o STR9-comStick. O comrst.cfg serve para resetá-lo. O comStick possui um hábito muito interessante: assim que você o liga (via USB) ele não inicia a execução do código da memória flash interna, para iniciá-lo é necessário executar o OpenOCD com o script comreset.cfg. Este script faz exatamente o que ele diz: executa um reset da CPU (já que a placa não possui um botão de RESET). Este é um comportamento bastante peculiar, e não tenho certeza se é algo genérico ou algum problema específico da minha comStick. Acredito que exista algum problema no tratamento do sinal de RESET da CPU pelo conversor USB-JTAG embutido na placa, e a única soluçõ foi executar este script toda vêz que você liga a placa ou precisa dar um RESET.</p>
<p><a name="lpc2888files"></a></p>
-<h2>Configuration files for LPC2888</h2>
+<h2>Arquivos de configuração para o LPC2888</h2>
-<p>LPC2888 is quite a different animal. I couldn't find any "official"
-LPC2888 configuration file for OpenOCD, so I had to learn how to write
-my own. It works, but I suspect it can be improved. This time, the
-configuration file applies to the latest (SVN) version of OpenOCD, so
-read this tutorial to understand how to get the latest OpenOCD sources
-and how to compile them (this section is based on version 922 of the
-OpenOCD repository). Then use the next file to burn your binary image
-to the chip:</p>
+<p>LPC2888 é algo bastante diferente. Não consegui encontrar um arquivo de configuração "oficial"
+do LPC2888 para o OpenOCD, logo tive que aprender como criar o meu próprio arquivo. Ele funciona, porém acredito que possa ser melhorado. No momento, o arquivo de configuração é compatível com o última versão (SVN) do OpenOCD, logo leia este tutorial para entender como obter os mais recentes arquivo fontes do OpenOCD e como compilá-los (esta seção é baseada na verão 922 do repositório do OpenOCD). Então utilize o arquivo abaixo para gravar no chip o arquivo de imagem binária:</p>
<p><a href="http://elua.berlios.de/other/lpc2888.cfg">lpc2888.cfg</a></p>
-<p>If your image name is not main.bin edit the file and change the
-corresponding line (flash write_bank 0 main.bin 0), then invoke openocd
-like this:</p>
+<p>Se o nome da sua imagem binária não é main.bin modifique o arquivo alterando a linha correspondente (flash write_bank 0 main.bin 0), e enão chame o OpenOCD da eguinte forma:</p>
<pre><code>openocd -f lpc2888.cfg<br></code></pre>
-<p>I'm using <a href="http://www.olimex.com/dev/arm-usb-tiny.html">ARM-USB-TINY</a>
-from Olimex, but it should be easy to use the script with any other
-JTAG adapter (don't forget to change the script to match your adapter).</p>
+<p>Estou usando <a href="http://www.olimex.com/dev/arm-usb-tiny.html">ARM-USB-TINY</a>
+da Olimex, no entanto, deve ser fácil usar este script com qualquer outro adaptador JTAG (nã esqueça de alterar o script para se ajustar ao seu adaptador).</p>
<p><a name="str7files"></a></p>
-<h2>Configuration files for STR711FR2 (STR7 from ST)</h2>
+<h2>Arquivos de configuração para o STR711FR2 (STR7 from ST)</h2>
-<p>Download them below:</p>
+<p>Faça o download deles abaixo:</p>
<p><a href="http://elua.berlios.de/other/str7prg.cfg">str7prg.cfg</a></p>
@@ -267,22 +149,10 @@
<p><a href="http://elua.berlios.de/other/str7_reset.script">str7_reset.scrip</a></p>
-<p>For STR7 I'm using the Yagarto OpenOCD build for Windows (repository
-version 717, as described at the beginning of this tutorial). The
-str7prg.cfg configuration file is for prorgramming the STR9-comStick.
-str7rst.cfg is for resetting it. I'm using a STR711FR2 heard board from
-<a href="http://www.sctec.com.br/content/view/101/30/">ScTec</a> to
-which I attached a few LEDs and a MAX3232 TTL to RS232 converter for
-the serial communication. The board comes with its own JTAG adadpter,
-but it uses a parallel interface, and since my computer doesn't have
-one, I used the <a href="http://www.olimex.com/dev/arm-usb-tiny.html">ARM-USB-TINY</a> from Olimex. To use them, invoke the OpenOCD executable like this:</p>
+<p>Para o STR7, estou usando o Yagarto OpenOCD feito para Windows (repositório versão 717, como está descrito no início deste tutorial). O arquivo de configuração str7prg.cfg serve para programar o STR9-comStick. str7rst.cfg serve para resetá-lo. Estou usando a placa STR711FR2 da <a href="http://www.sctec.com.br/content/view/101/30/">ScTec</a> na qual conectei alguns LEDs e um conversor MAX3232TTL-R232 para comunicação serial. A placa vem com seu próprio adaptador JTAG, mas ele é usado para uma interface paralela, e como o meu computador não tem uma entrada paralela, usei o <a href="http://www.olimex.com/dev/arm-usb-tiny.html">ARM-USB-TINY</a> da Olimex. Para usá-los, chamei o OpenOCD da seguinte forma:</p>
<pre><code>openocd-ftd2xx -f str7prg.cfg<br></code></pre>
-<p>(note: under Windows, the OpenOCD executable name is often
-"openocd-ftd2xx". Under Linux it's simply "openocd". Replace it with
-the actualy name with your executable.)
-Also, be sure to modify str7_flashprogram.script if your image name is
-not main.bin.</p><p></p><p></p><p></p><p> </p>
-</div></body></html>
\ No newline at end of file
+<p>(nota: no Windows, o nome do executável do OpenOCD chama-se normalmente "openocd-ftd2xx". No Linux chama-se simplesmente "openocd". Substitua-o com o nome do seu executá atual.) Além disso, certifique-e de alterar o arquivo str7_flashprogram.script caso o nome do seu arquivo imagem não seja main.bin.</p><p></p><p></p><p></p><p> </p>
+$$FOOTER$$
Modified: branches/eagle_mmc/doc/pt/tutorials.html
===================================================================
--- branches/eagle_mmc/doc/pt/tutorials.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/pt/tutorials.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,10 +1,4 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Tutoriais</title>
-
-<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);">
+$$HEADER$$
<h3>Tutoriais</h3>
<p>Esta sessão contêm informação sobre diferentes ferramentas e procedimentos relacionados com <b>eLua</b>:
<ul>
@@ -12,4 +6,4 @@
<li>rodando <b>eLua</b> (i386) na versão standalone utilizando diferentes cenários.</li>
<li>usando OpenOCD para programar em <b>eLua</b> em diferentes plataformas.</li>
</ul></p>
-</body></html>
+$$FOOTER$$
Modified: branches/eagle_mmc/doc/pt/uart_ref.html
===================================================================
--- branches/eagle_mmc/doc/pt/uart_ref.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/pt/uart_ref.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,11 +1,6 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Produto</title>
-
-<link rel="stylesheet" type="text/css" href="../style.css">
</head>
-<body style="background-color: rgb(255, 255, 255);">
<h3><a name="over"></a>uart</h3>
<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="setup"></a>[uart.setup(</font><font face="Bitstream Vera Sans Mono, sans-serif"> id, baud,
databits, </font>
Modified: branches/eagle_mmc/doc/pt/using.html
===================================================================
--- branches/eagle_mmc/doc/pt/using.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/pt/using.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,132 +1,178 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Usando eLua</title>
+$$HEADER$$
+<h3>Usando eLua</h3><p> Bem, você já <a href="building.html">compilou</a> e <a href="installing.html">instalou</a>
+<b>eLua</b>. Agora está (finalmente!) na hora da curtir os resultados :)
+ Você pode desenvolver em <b>eLua</b> utilizando tanto uma conexão serial (UART, de longe a mais comum) como uma conexão TCP/IP (neste caso, ainda em testes, mas funcionando muito bem), logo existem dois cenários para esta situação (veja também <a href="building.html">building eLua</a> para mais detalhes de como escolher entre console serial ou TCP/IP).</p>
+<a name="uart"><h3>Usando eLua com uma conexão serial</h3></a>
+<p>Tudo o que você precisa para usar <b>eLua</b> com uma conexão serial é de sua placa <b>eLua</b> conectada a um PC rodando um programa emulador de terminal.<br>Se
+você está usando o Windows, recomendamos o <a href="http://www.ayera.com/teraterm/">TeraTerm</a>.
+É gratuito, possui muitos recursos e é fácil de usar. O pré-instalado Hyper Terminal também pode ser usado, porém dê uma chance ao TeraTerm
+e compare as diferenças.<br>Se você usa Linux,
+irá provavelmente se deparar com o Minicom a qualque momento. Ele não é muito intuitivo e roda em modo texto, mas possui bastante recursos. Se você
+pesquisar no google por "minicom tutorial", poderá aprender rapidamente como instalá-lo e utilizá-lo. Você
+pode tentar outros emuladores, desde que configure-os
+adequadamente e que eles permitam que você faça transferência de arquivos
+via XMODEM, que no momento é o processo que <b>eLua</b> utiliza. Estes sáo os principais
+parâmetros a serem configurados:</p>
-<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);">
-<h3>Usando eLua</h3><p> Bem, você já <a href="building.html">construiu</a> e <a href="installing.html">instalou</a> <b>eLua</b>, e agora está na hora (finalmente) da curtir eLua :)
- Você pode compilar <b>eLua</b> utilizando tanto uma conexão serial (UART, longe de ser a mais comum) como uma conexão TCP/IP (neste caso, ainda em testes, mas funcionando muito bem), logo existem dois cenários para esta situação (veja também <a href="building.html">building eLua</a> para mais detalhes de como escolher entre console serial ou TCP/IP).</p>
-<a name="uart"><h3>Usando eLua com uma conexão serial</h3></a>
-<p>Tudo o que você precisa para usar <b>eLua</b> com uma conexão serial é de sua placa <b>eLua</b> conectada a um PC rodando um programa emulador de terminal.<br>Se
-você está usando o Windows, recomendo o <a target="_blank" href="http://www.ayera.com/teraterm/">TeraTerm</a>.
-É gratuito, possui muitos recursos e é fácil de usar. O pré-instalado Hyper Terminal também pode ser usado, porém dê uma chance ao TeraTerm, pois ele é muito melhor do que o HyperTerm IMO.<br>Se você usa o
-Linux,
-irá provavelmente se deparar com o minicom a qualque momento. Ele não é muito intuitivo e roda em modo texto, mas possui bastante recursos. Se você
-pesquisar no google por "minicom tutorial", poderá aprender rapidamente como instalá-lo e utilizá-lo. Você
-pode tentar outros emuladores, desde que configure-o
-adequadamente e que ele permite que você faça transferência de arquivos
-via XMODEM, que no momento é o processo que <b>eLua</b> utiliza. Estes sáo os principais
-parâmetros a serem configurados:</p>
+<ul>
+<li>configuraçáo da porta: 115200 baud (38400 para o <a href="installing_str7.html">STR7)</a>, 8N1(8 bits de dados, sem paridade, um stop bit).</li>
+<li>controle de fluxo do hardware: nenhum</li>
+<li>como interpretar uma nova linha: "CR" na recepção, "CR+LF" no envio (alguns emuladores não permitem essa opção). </li>
+</ul>
-<ul><li>configuraçáo da porta: 115200 baud (38400 para o <a href="installing_str7.html">STR7)</a>, 8N1(8 bits de dados, sem paridade, um stop bit). </li><li>controle de fluxo do hardware: nenhum</li><li>como interpretar uma nova linha: "CR" na recepção, "CR+LF" no envio (alguns emuladores não permitem essa opção). </li></ul>
+<p>
+Além disso, dependendo do seu kit, você irá precisar conectá-lo a uma porta serial do seu PC ou a uma porta USB, caso esteja usando um conversor USB/Serial. Por exemplo, como já foi explicado <a href="installing_lm3s.html">aqui</a>,
+a porta USB nas placas LM3Sxxxx possui duas conexões, portanto você pode usá-la como um conversor de USB para serial depois de atualizar o
+firmware, dispensando qualquer outro tipo de conexão. O mesmo acontece com a placa STR9-comStick. Entretanto, para a placa SAM7-EX256 você precisará conectar um cabo serial ao conector "RS232", desde que
+os jumpers já estejam configurados como explicado <a href="installing_at91sam7x.html">aqui</a>. Para a placa MOD711 você precisará acrescentar um chip conversor RS232.
+Não existe uma única regra, tudo depende do modêlo da sua placa.
+</p>
-
-<p>Além disso, dependendo do tipo da sua placa, você irá precisar conectá-la a uma porta serial do seu PC ou a uma porta USB, caso esteja usando um conversor USB/Serial. Por exemplo, como já foi explicado <a href="installing_lm3s.html">aqui</a>,
-a porta USB nas placas LM3Sxxxx possui duas conexões, portanto você pode usá-la como um conversor de USB para serial depois de atualizar o firmware, sendo assim, você não precisa de nenhum outro tipo de conexão. O mesmo acontece com a placa STR9-comStick. Entretanto, para a placa SAM7-EX256 você precisará conectar um cabo serial ao conector "RS232", desde que
-os jumpers já estejam configurados como explicado <a href="installing_at91sam7x.html">aqui</a> e para a placa MOD711 você precisará acrescentar um chip conversor RS232.
-Não existe uma única regra, tudo depende do modêlo da sua placa.
-</p>
-<a name="tcpip"><h3>Usando eLua com uma conexão TCP/IP</h3></a>
-<p>As coisas ficam bem mais fáceis se você decidir usar uma conexão TCP/IP:
+<a name="tcpip"><h3>Usando eLua com uma conexão TCP/IP</h3></a>
+<p>As coisas ficam bem mais fáceis se você decidir usar uma conexão TCP/IP:
<ul>
- <li>certifique-se que você conhece o endereço de sua placa. Se você habilitou IP estático (veja <a href="building.html">construindo</a>). lembre-se qual o IP escolhido; caso esteja usando DHCP, seu servidor DHCP deve ter incluído o endereço de sua placa <b>eLua</b> como seu DNS. O nome da placa sempre é "elua", logo caso você execute um "ping elua" a partir do shell poderá verificar se a placa está ativa.</li>
- <li>um telnet para o endereço da placa (ou simplesmente "telnet elua" com DHCP ativo), e você será recebido pelo shell prompt da placa (se o shell estiver ativo, leia o próximo parágrafo para mais detalhes).
- É importante salientar, que a placa <b>eLua</b> só poderá estar conectada a uma sessão telnet ativa a cada instante.</li>
+ <li>Certifique-se que você conhece o endereço IP de sua placa. Se você habilitou IP estático (veja <a href="building.html">construindo</a>)
+ e lembre-se qual o IP escolhido durante o build. Caso tenha optado pelo
+ modo DHCP (IP fornecido por um servidor na sua rede local), seu servidor DHCP deve ter
+ incluÃdo o endereço de sua placa <b>eLua</b> como seu DNS. O nome da placa sempre é "elua", logo caso você execute um "ping elua" a partir do
+ shell, poderá verificar se a placa está ativa.</li>
+ <li>Uma conexão Telnet para o endereço da placa (ou simplesmente "telnet elua" com DHCP ativo) e você será recebido pelo shell prompt da placa (se o shell estiver ativo, leia o próximo parágrafo para mais detalhes).
+ É importante salientar que uma placa <b>eLua</b> só poderá estar conectada a uma
+ única sessão Telnet ativa a cada instante.</li>
</ul>
+
</p>
-<p>Se você está rodando Windows, certifique-se que esteja utilizando um telnet adequado, o que significa na prática "tudo menos o telnet nativo".
- <a target="_blank" href="http://www.chiark.greenend.org.uk/~sgtatham/putty/">PuTTY</a> é muito popular e uma boa opção.</p>
+<p>Se você está desenvolvendo em Windows, certifique-se que esteja utilizando um
+cliente Telnet adequado, o que significa na prática "qualquer coisa menos o cliente Telnet nativo".
+<a href="http://www.chiark.greenend.org.uk/~sgtatham/putty/">PuTTY</a> é muito popular e uma boa opção.</p>
+
<a name="pc"><h3>Usando eLua "standalone" em seu PC</h3></a>
-<p>Se você construiu <b>eLua</b> para a plataforma i386, poderá dar boot direto pela placa <b>eLua</b>! Sem sistema operacional controlando o seu computador, somente <b>eLua</b> puro. Não haverá nenhum periférico para ter acesso, mas podemos usar o módulo term para executar o <i>hangman.lua</i> e o <i>life.lua</i>, bem como outros exemplos, o que o torna uma boa demonstração :) Siga <a href="installing_i386.html">
-este link</a> para obter informações específicas sobre a plataforma i386. </p>
+<p>Se fez um build de <b>eLua</b> para a plataforma i386, poderá dar boot direto
+em <b>eLua</b>(!!!), sem Sistema Operacional controlando o seu computador, somente <b>eLua</b>
+e mais nada. Não haverá nenhum periférico disponÃvel para acesso mas podemos usar o módulo term para executar
+jogos como o <i>hangman.lua</i> , o <i>life.lua</i>, assim como outros exemplos, o que o torna uma boa demonstração :)
+Siga <a href="installing_i386.html">este link</a> para obter informações especÃficas sobre a plataforma i386. </p>
<a name="shell"><h3><a name="shell"></a>O shell eLua</h3></a>
-<p>Não importa como você está conectado fisicamente (serial, TCP/IP ou pelo seu monitor de vídeo do PC após o boot com <b>eLua</b>), depois que você configurar a conexão PC-placa <b>elua</b> (se aplicável) e pressionar o botão "RESET" de sua placa ou simplesmente pressionar ENTER se você estiver usando uma conexão serial, você deve ver o shell prompt de <b>eLua</b> (se na construção de eLua, o shell prompt foi habilitado como descrito <a href="building.html">aqui</a>). O shell é um simples interpretador de comandos interativo que permite:
+<p>Não importa como você está conectado fisicamente (serial, TCP/IP ou pelo seu monitor de vÃdeo do PC após o boot com <b>eLua</b>),
+depois que você configurar a conexão PC-placa <b>elua</b> (se aplicável) e pressionar o botão "RESET" de sua placa ou simplesmente pressionar
+ENTER, você deve ver o shell prompt de <b>eLua</b> (o shell prompt deve ter
+sido habilitado no build, como descrito <a href="building.html">aqui</a>).
+O shell de <b>eLua</b> é um simples interpretador de comandos interativo que permite:
<ul>
- <li>fornece uma ajuda para o uso do interpretador com o comando help</li>
- <li>roda o interpretador Lua no modo interativo da mesma forma que fazemos em nosso computador</li>
- <li>roda programas Lua a partir do sistema de arquivo eLua</li>
- <li>transfere arquivo fonte via XMODEM e execute-o</li>
- <li>mostra a versão de eLua</li>
- <li>lista arquivos eLua</li>
+ <li>fornecer uma ajuda para o uso do interpretador com o comando help</li>
+ <li>rodar o interpretador Lua original, no modo interativo, da mesma forma que fazemos em
+ um desktop</li>
+ <li>rodar programas Lua que se encontream no File System de <b>eLua</b></li>
+ <li>transferir arquivos com programas fonte Lua via XMODEM e executa-los</li>
+ <li>mostrar a versão corrente de <b>eLua</b></li>
+ <li>listar arquivos do File System de <b>eLua</b></li>
</ul></p>
-<p>Segue abaixo uma descrição detalhada de todos os comandos.</p>
+<p>Segue abaixo uma descrição detalhada de todos os comandos.</p>
<h2>help</h2>
-<p>Mostra uma lista de todos os comandos disponíveis.</p>
+<p>Mostra uma lista de todos os comandos disponÃveis no shell de <b>eLua</b></p>
<h2>ver</h2>
-<p>Mostra a versão da imagem de <b>eLua</b> instalada na placa. Atualmente, a versão é somente incrementada por atualizações oficiais, logo se é liberada uma versão intermediária, esta não interfere no número da versão.</p>
+<p>Mostra a versão da imagem de <b>eLua</b> instalada na placa. Atualmente, a versão é somente incrementada por atualizações oficiais,
+logo se é liberada uma versão intermediária, esta não interfere no número da versão.</p>
<h2>recv</h2>
-<p>Permite que você receba um arquivo eLua (tanto arquivos fontes quanto compilados) via
-XMODEM e execute-o em sua placa. Para usar este comando, é necessário que a imagem do seu <b>eLua</b> tenha sido configurada para suportar XMODEM
-(veja <a href="building.html">construindo</a> para mais detalhes). Além disso, o seu programa emulador de terminal deve suportar o envio de arquivos via protocolo XMODEM. Ambos XMODEM com checksum e XMODEM com CRC são suportados, no entanto só é aceito o XMODEM com pacotes de 128
-bytes (XMODEM com pacotes de 1K não funciona).
-Para usar esse recurso, digite "recv" no prompt do shell. eLua responderá com
-"Waiting for file ...". Neste momento, você poderá enviar o arquivo para a placa eLua
-via XMODEM. eLua receberá e executará o arquivo. Não se preocupe quando ver o
-caracter 'C' aparecendo em seu terminal depois de entrar como esse comando,
-pois essa é a forma como o XMODEM é inicializado.<br>
-Como o XMODEM é um protocolo que se utiliza de comunicação serial, este comando não está disponível caso você esteja usando uma conexão TCP/IP.<br>
-Caso você esteja querendo enviar arquivos binários já compilados ao invés de código fonte para <b>eLua</b>, veja antes <a href="using.html#cross">essa sessão</a>.
+<p>Permite que você receba um arquivo eLua (tanto arquivos fontes quanto compilados) via protocolo
+XMODEM e execute-o em sua placa. Para usar este comando é necessário que sua imagem de <b>eLua</b> tenha sido configurada para suportar XMODEM
+(veja <a href="building.html">build de eLua</a> para mais detalhes). Além disso, o seu programa emulador de terminal deve suportar o envio de arquivos via protocolo XMODEM.
+Ambos XMODEM com checksum e XMODEM com CRC são suportados. No entanto só é aceito o XMODEM com pacotes de 128 bytes
+(não há suporte para XMODEM com pacotes de 1K).
+Para usar esse recurso, digite "recv" no prompt do shell. <b>eLua</b> responderá com
+"Waiting for file ...". Neste momento, você poderá enviar o arquivo para a placa eLua
+via XMODEM. <b>eLua</b> receberá e executará o arquivo. Não se preocupe quando ver o
+caracter 'C' aparecendo em seu terminal depois de entrar como esse comando, pois essa é a forma como o XMODEM é inicializado.<br>
+Como o XMODEM é um protocolo que se utiliza de comunicação serial, este comando não está disponÃvel caso você esteja usando uma conexão TCP/IP.<br>
+Caso você esteja querendo enviar arquivos binários já compilados ao invés de código fonte para <b>eLua</b>,
+veja antes <a href="using.html#cross">essa sessão</a>.
</p>
<h2>lua</h2>
-<p>Esse comando inicia a interpretador Lua, aceitando opcionalmente parâmetros na linha de comando, exatamente
-como se você estivesse em seu computador. O comando possui algumas restrições:</p>
+<p>Esse comando inicia a interpretador Lua, aceitando opcionalmente parâmetros na linha de comando, exatamente
+como se você estivesse em seu computador desktop. O comando possui algumas restrições:</p>
-<ul><li>No máximo 50 caracteres para o tamanho da linha de comando</li>
-<li>a sequência 'ESC` não foi implemantada. Por exemplo, o seguinte comando não funcionará
- devido a sequência 'ESC' com ' ('aspas simples') somente:
-
-<p><pre><code>eLua# lua -e 'print(\'Hello, World!\')' -i<br>
+<ul>
+<li>Máximo de 50 caracteres na linha de comando</li>
+<li>A sequência 'ESC` não foi implemantada. Por exemplo, o seguinte comando não funcionará
+ devido a sequência 'ESC' com ' ('aspas simples') somente:
+<p>
+<pre><code>eLua# lua -e 'print(\'Hello, World!\')' -i<br>
Press CTRL+Z to exit Lua<br>
-lua: (command line):1: unexpected symbol near ''</code></pre></p>
+lua: (command line):1: unexpected symbol near ''</code></pre>
+</p>
-<p>Entretanto, se você usar ambas ' ('aspas simples') e " ("aspas duplas"), então funcionará:</p>
+<p>Entretanto, se você usar ambas ' ('aspas simples') e " ("aspas duplas"), o comando então funcionará:</p>
<p><pre><code>eLua# lua -e 'print("Hello, World")' -i
Press CTRL+Z to exit Lua
Lua 5.1.4 Copyright (C) 1994-2008 Lua.org, PUC-Rio
-Hello,World</code></pre></p></li></ul>
-<p>Caso você queira executar um arquivo a partir do <a href="">##ROM file system</a>, não se esqueça de colocar antes do nome do arquivo o prefixo <i>/rom</i>. Por exemplo, para executar o arquivo <b>hello.lua</b>, digite o seguinte:</p>
-<p><pre><code>$ lua /rom/hello.lua</code></pre></p>
+Hello,World</code></pre></p></li>
+</ul>
+
+<p>Caso você queira executar um arquivo a partir do <a href="arch_romfs.html">ROM File System</a>, não se esqueça de colocar antes do nome do arquivo o prefixo
+<b>/rom</b>.
+Por exemplo, para executar o arquivo hello.lua, digite o seguinte:
+</p>
+<p>
+<pre><code>$ lua /rom/hello.lua</code></pre>
+</p>
+
<h2>ls or dir</h2>
-<p>Lista todos os arquivos do sistema de arquivos utilizado por <b>eLua</b> (atualmente armazenado em ROM), bem como o total ocupado e o espaço total do sistema de arquivos.</p>
+<p>Lista todos os arquivos do File System de <b>eLua</b> (atualmente armazenado em ROM), bem como o total ocupado
+por cada um e o espaço total do sistema de arquivos.
+</p>
+
<h2>exit</h2>
-<p>Sai do shell. Esse comando só faz sentido, caso você tenha compilado <b>eLua</b> para conexão sobre TCP/IP, já que a sessão telnet é encerrada com a placa <b>eLua</b>. Caso contrário o comando simplesmente encerra
- o shell e trava até você resetar sua placa.</p>
+<p>Sai do shell. Esse comando só faz sentido, caso você tenha compilado <b>eLua</b> para conexão sobre TCP/IP, já que a sessão telnet
+é encerrada com a placa <b>eLua</b>. Caso contrário o comando simplesmente encerra o shell e trava até você resetar sua placa.
+</p>
+
<a name="cross"><h3>Cross-compilation: compilando seus programas eLua para uma plataforma diferente</h3></a>
-<p><i>Cross-compilation</i> é o processo de compilação de um programa em uma platforma com obejtivo de ser
-utilzado em uma outra plataforma. Por exemplo, o processo de compilação para gerar uma imagem binária de <b>eLua</b> em
-seu PC para uso na sua placa <b>eLua</b> é o que chamamos de "cross-compiling". Lua pode ser compilada dessa forma também. Ao compilar Lua usando esse procedimento
- você tem algumas vantagens importantes:
+<p><i>Cross-compilation</i> é o processo de compilação de um programa em uma platforma com obejtivo de ser
+utilzado em uma outra plataforma. Por exemplo, o processo de compilação para gerar uma imagem binária de <b>eLua</b> em
+seu PC para uso na sua placa <b>eLua</b> é o que chamamos de "cross-compiling".
+Lua pode ser compilada dessa forma também. Ao compilar Lua usando esse procedimento você tem algumas vantagens importantes:
<ul>
-<li><b>volocidade</b>: o compilador Lua na placa <b>eLua</b> não precisa compilar o código fonte Lua
- , simplesmente executa o código binário.</li>
-<li><b>memória</b>: caso você esteja executando diretamente um código binário, nenhuma memória a mais
- é "gasta" em placa <b>eLua</b> para compilação do código Lua para bytecode.
- Muitas vezes isso é a "salvação". Caso você esteja tentando executar código Lua direto de sua placa e recebendo a mensagem de erro "not enough memory",
- pode mudar esse resultado compilando o programa Lua em seu PC e depois
- executando o arquivo gerado. Alé disso, compilar programas Lua muito grandes em sua placa
- <b>eLua</b> pode acarretar estouro de pilha, o que normalmente nos leva a erros difíceis de serem encontrados.</li>
-</ul></p>
-<p>Para usar "cross-compilation", as duas plataformas Lua (neste caso seu PC e sua placa <b>eLua</b>) devem ser compatíveis
-(devem ter os mesmos tipos de dados, com os mesmos tamanhos e a mesma representação de memória).
- Isto não é verdadeiro sempre. Por exemplo, alguns toolchains gcc para arquitetura ARM usam como padrão uma representação muito específica para números com dupla precisão (conhecida como formato FPA), tornando dessa forma, os arquivos bytecode gerados no PC com um compilador Lua inúteis para as placas ARM. Outros toolchains não possuem esse problema. Outras arquiteturas (como a AVR32) são "big endian", ao contrário da plataforma Intel para PCs que é "little endian".<br>
-Para resolver esses tipos de problemas, um patch para "Lua cross-compilation" foi enviado para a lista de e-mails de Lua
-a pouco tempo atrás, e foi bastante modificado como parte do projeto <b>eLua</b>
- para funcionar com a arquitetura ARM. Aqui está como usá-lo (as instruções abaixo foram testadas em Linux, não em Windows, mesmo assim, elas devem funcionar também no Windows com pouco ou quase nenhum esforço):
+<li><b>velocidade</b>: O compilador Lua na placa <b>eLua</b> não precisa compilar o código fonte
+Lua. Ele simplesmente executa o código binário (bytecodes Lua).</li>
+<li><b>memória</b>: caso você esteja executando diretamente um código binário, nenhuma memória
+adicional é usada na placa para compilação do código Lua para bytecode. Muitas vezes isso é a
+"salvação", quando você já está no limite de uso dos seus recursos de
+memória. Caso você esteja tentando executar código Lua direto de sua placa e recebendo a mensagem de erro "not enough memory",
+pode mudar esse resultado compilando o programa Lua em seu PC e depois executando o arquivo
+binário (bytecodes Lua) gerado. Além disso, compilar programas Lua muito grandes em sua placa
+<b>eLua</b> pode (raramente) acarretar estouro de pilha (stack overflow), o que normalmente nos leva a erros difÃceis de serem encontrados.</li>
+</ul>
+</p>
+
+<p>Para usar "cross-compilation", as duas plataformas Lua (neste caso seu PC e sua placa <b>eLua</b>) devem ser compatÃveis
+(mesmo tamanho de palavra, mesmo alinhamento etc...).
+Isto não é verdadeiro sempre. Por exemplo, alguns toolchains gcc para arquitetura ARM usam como padrão uma representação muito especÃfica
+para números com dupla precisão (conhecida como formato FPA), tornando dessa forma, os arquivos bytecode gerados no PC com um compilador Lua inúteis
+para as placas ARM. Outros toolchains não possuem esse problema. Outras arquiteturas (como a AVR32) são "big endian", ao contrário da plataforma
+Intel para PCs que é "little endian".<br>
+Para resolver esses tipos de problemas, um patch para "Lua cross-compilation" foi enviado para a lista de e-mails de Lua e foi bastante modificado
+como parte do projeto <b>eLua</b> para funcionar com a arquitetura ARM.
+Aqui está como usá-lo (as instruções abaixo foram testadas em Linux, não em Windows, mesmo assim, elas devem funcionar também no Windows com
+pouco ou quase nenhum esforço):
<ul>
-<li>primeiro, certifique-se que seu PC já esteja com todos os arquivos necessários para a construção de um <b>eLua</b> (gcc,
- binutils, libc, headers...). Você precisará também do scons. A boa notícia é que você já deve ter o scon instalado em seu sistema,
-já que, caso contrá você não seria capaz nem mesmo de construir <b>eLua</b> (veja <a href="building.html">construindo</a> para instruções mais detalhadas).</li>
-<li>a partir do diretório base de <b>eLua</b>, digite o seguinte comando:</li>
- <p><pre><code>$ scons -f cross-lua.py</code></pre></p></ul>
-<p>Esse comando gera um arquivo chamado <i>luac</i> no mesmo. É quase a mesma coisa que no compilador comum, mas possui alguns poucos argumentos para lidar com as diferenças entre as diversas arquiteturas (mostradas abaixo em negrito):</p>
+<li>Primeiro, certifique-se que seu PC já esteja com todos os arquivos necessários para o build de <b>eLua</b> (gcc, binutils, libc, headers...).
+Você precisará também do scons. A boa notÃcia é que você já deve ter o scons instalado em seu sistema,
+já que, caso contrário você não seria capaz nem mesmo de construir <b>eLua</b> (veja <a href="building.html">construindo</a> para
+instruções mais detalhadas).</li>
+<li>a partir do diretório base de <b>eLua</b>, digite o seguinte comando:</li>
+ <p><pre><code>$ scons -f cross-lua.py</code></pre></p>
+</ul>
+
+<p>Esse comando gera um arquivo chamado <i>luac</i> no mesmo.
+É quase a mesma coisa que no compilador comum, mas possui alguns poucos argumentos para lidar com as diferenças entre as diversas arquiteturas
+(mostradas abaixo em negrito):</p>
<p><pre><code>usage: ./luac [options] [filenames].
Available options are:
- process stdin
@@ -139,7 +185,7 @@
-ccn type bits cross-compile with given lua_Number type and size
-cce endian cross-compile with given endianness ('big' or 'little')</b>
-- stop handling options</code></pre></p>
-<p>Tudo que deve ser feito agora é usar a tabela abaixo para identificar qual os parâmetros certos para serem utilizados no cross-compiler:</p>
+<p>Tudo que deve ser feito agora é usar a tabela abaixo para identificar qual os parâmetros certos para serem utilizados no cross-compiler:</p>
</p><table style="text-align: left;" class="table_center">
<tbody>
<tr>
@@ -152,42 +198,45 @@
<td>Ponto Flutuante (lua)</td>
<td>ARM7TDMI<br>Cortex-M3<br>ARM966E-S</td>
<td><a href="toolchains.html">arm-gcc</a>
- <td><code>./luac -ccn float_arm 64 -cce little -o <script.luac> -s <script.lua></code></td>
+ <td><code>./luac -ccn float_arm 64 -cce little -o <script.luac> -s <script.lua></code></td>
</tr>
<tr>
<td>Ponto Flutuante (lua)</td>
<td>ARM7TDMI<br>Cortex-M3<br>ARM966E-S</td>
<td><a href="toolchains.html">codesourcery</a>
- <td><code>./luac -ccn float 64 -cce little -o <script.luac> -s <script.lua></code></td>
+ <td><code>./luac -ccn float 64 -cce little -o <script.luac> -s <script.lua></code></td>
</tr>
<tr>
<td>Inteiro (lualong)</td>
<td>ARM7TDMI<br>Cortex-M3<br>ARM966E-S</td>
<td><a href="toolchains.html">arm-gcc<br>codesourcery</a>
- <td><code>./luac -ccn int 32 -cce little -o <script.luac> -s <script.lua></code></td>
+ <td><code>./luac -ccn int 32 -cce little -o <script.luac> -s <script.lua></code></td>
</tr>
<tr>
<td>Ponto Flutuante (lua)</td>
<td>AVR32</td>
<td><a href="toolchains.html">avr32-gcc</a>
- <td><code>./luac -ccn float 64 -cce big -o <script.luac> -s <script.lua></code></td>
+ <td><code>./luac -ccn float 64 -cce big -o <script.luac> -s <script.lua></code></td>
</tr>
<tr>
<td>Inteiro (lualong)</td>
<td>AVR32</td>
<td><a href="toolchains.html">avr32-gcc</a>
- <td><code>./luac -ccn int 32 -cce big -o <script.luac> -s <script.lua></code></td>
+ <td><code>./luac -ccn int 32 -cce big -o <script.luac> -s <script.lua></code></td>
</tr>
</tbody>
</table>
-<p>(observe que se por alguma razão você precisa de um cross-compile <b>eLua</b> para x86, poderá usar o próprio compilador Lua).<br>
-Você pode omitir o parâmetro <i>-s</i> (de strip) da compilação, mas isso resultará em arquivos binários maiores (quando não se usa o parâmetro <i>-s</i>, a informação de debug não é removida do arquivo gerado).</p>
-<p>Você pode usar o arquivo gerado de duas formas:</p>
+<p>(observe que, se por alguma razão você precisar, de um cross-compile <b>eLua</b> para x86, poderá usar o próprio compilador Lua).<br>
+Você pode omitir o parâmetro <i>-s</i> (de strip) da compilação, mas isso resultará em arquivos binários maiores
+(quando não se usa o parâmetro <i>-s</i>, a informação de debug não é removida do arquivo gerado).</p>
+<p>Você pode usar o arquivo gerado de duas formas:</p>
<ul>
- <li>gravá-lo em uma <a href="arch_romfs.html">ROM do sistema de sua placa</a> e executá-lo a partir daí.</li>
- <li>usar o comando <i>recv</i> a partir <a href="using.html#shell">do shell</a> para enviá-lo para a placa usando uma conexão serial.</li>
+ <li>gravá-lo no <a href="arch_romfs.html">ROM File System</a> de sua placa
+ durante um build e executá-lo a partir daÃ.</li>
+ <li>usar o comando <i>recv</i> a partir <a href="using.html#shell">do
+ shell</a>, para enviá-lo para a placa usando uma conexão serial.</li>
</ul>
<p>
</p>
-</body></html>
+$$FOOTER$$
Modified: branches/eagle_mmc/doc/pt/versionhistory.html
===================================================================
--- branches/eagle_mmc/doc/pt/versionhistory.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/pt/versionhistory.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,9 +1,123 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Produto</title>
+$$HEADER$$
+<h3>Histórico das Versões de eLua</h3>
-<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);"><h3><a name="title" href="http://www.eluaproject.net/en/Using_OpenOCD" class="local"></a>Histórico das versões de eLua</h3>
-
- <div class="content"><span style="text-decoration: underline;"><span style="font-weight: bold;"></span></span><br></div></body></html>
+<p>A tabela abaixo apresenta a histórico de todas as versões oficiais de <b>eLua</b> (em ordem inversa, da mais recente à mais antiga)..</p>
+<table style="text-align: left" class="table_center">
+<tbody>
+<tr>
+<th style="text-align: left;">Versão</th>
+<th style="text-align: center;">Lançada em</th>
+<th style="text-align: center;">Descrição</th>
+</tr>
+<tr>
+ <td align="center" style="color: rgb(255, 102, 0);">##TODO</td>
+ <td align="center">##TODO.11.2009</td>
+ <td>
+ <ul>
+ <li>Adicionado suporte aos kits STR-E912</li>
+ <li>Exemplos alterados para suporte às STR-E912</li>
+ <li>Conteúdo da doc/site revisado e melhorado</li>
+ <li>Mais páginas em português</li>
+ <li>Novo m Módulo especÃfico PIO para suporte à novidades dos STR9</li>
+ <li>Adicionado EGC (Emergency Garbage Collection) patch à Lua</li>
+ <li>(Adicionado suporte inicial à Rotinas de Tratamento de Interrupção em Lua)</li>
+ <li>(Adicionado suporte aos NXP LPC24xx)</li>
+ <li>(##Adicionado um FAT File System para cartões SD/MMC {pode não sair no
+ próximo minor release ainda})</li>
+</ul>
+</td>
+<tr>
+ <td align="center" style="color: rgb(255, 102, 0);">0.6</td>
+ <td align="center">06.10.2009</td>
+ <td>
+ <ul>
+ <li>Licença alterada para MIT</li>
+ <li>Estrutura do site/doc completamente redesenhada</li>
+ <li>Documentação incluÃda nas distros, para acesso offline</li>
+ <li>Adicionado suporte à CPUs AVR32</li>
+ <li>Adicionado suporte à CPUs STM32</li>
+ <li>Novo módulo ADC com suporte a filtros de média móvel</li>
+ <li>Adiconado suporte à múltiplos toolchains</li>
+ <li>Comando ls (ou dir) adicionado ao shell</li>
+ <li>Novos exemplos de código: pong, tetrives, spaceship (jogos), logo (gráficos), adcpoll, adcscope (módulo ADC)</li>
+ <li>Adicionado LTR (Lua Tiny RAM) patch à Lua, com grande ganho de memória</li>
+ <li>O conteúdo do ROM File System agora pode ser especificado por placa/kit</li>
+ <li>Semântica das funções da API revisada (pode exigir pequenas alterações de código anterior)</li>
+</ul>
+</td>
+</tr>
+<tr>
+ <td align="center" style="color: rgb(255, 102, 0);">0.5</td>
+ <td align="center">01.11.2008</td>
+ <td><ul>
+ <li>Adicionado suporte para CPUs STR7 da ST</li>
+ <li>Adicionado Suporte TCP/IP usando a pilha uIP</li>
+ <li>Adicionado suporte para a console e o shell sobre TCP/IP, além da já existente conexão serial</li>
+ <li>Adicionado o módulo "net" (interface de eLua para funções TCP/IP)</li>
+ <li>Adicionado o módulo CPU " (interface de eLua para a CPU corrente)</li>
+ <li>Novos exemplos: morse.lua (codificador de código Morse), lhttpd.lua (servidor HTTP em Lua)</li>
+ <li>Adicionado suporte para cross-compilar de código Lua (compile no PC e execute na sua placa)</li>
+ <li>A partir de agora, o protocolo XMODEM pode receber bytecode Lua além de código fonte Lua</li>
+ <li>O buffer do XMODEM agora é dinâmico (cresce conforme necessário) em vez de ter um tamanho fixo</li>
+ <li>A documentação do projeto foi atualizada</li>
+</ul></td>
+</tr>
+<tr>
+ <td align="center" style="color: rgb(255, 102, 0);">0.4.1</td>
+ <td align="center">10.09.2008</td>
+ <td><ul>
+
+
+ <li>alterada a versão de Lua de 5.1.3 para 5.1.4</li>
+ <li>alterada a estrutura do sistema de arquivos, agora você pode gerar as duas versões de Lua (ponto flutuante e inteiro) a partir do mesmo diretório</li>
+ <li>biblioteca matemática configurável usando o mecanismo já existente das "bibliotecas da plataforma"</li>
+ <li>Os módulos "os" e "package" não são mais carregados por Lua, já que não podem ser mais utilizados. Devido a isso, o tamanho do código de eLua foi reduzido.</li>
+ <li>A documentação do projeto foi atualizada</li>
+</ul></td>
+</tr>
+<tr>
+ <td align="center" style="color: rgb(255, 102, 0);">0.4</td>
+ <td align="center">02.09.2008</td>
+ <td><ul>
+ <li>Adicionado suporte para LPC2888 (preliminar)</li>
+ <li>Adicionado módulo PWM</li>
+ <li>Novos exemplos: TV-B-Gone (desliga sua TV), piano (toque piano do teclado de seu computador), pwmled (fade in/out), todos baseados no novo módulo PWM</li>
+ <li>Adicionado suporte para múltiplos espaços de memória (isso pode ser usado para tirar proveito de CPUs com memória RAM interna e chips com memória RAM externa na placa)</li>
+ <li>Autorun: se "autorun.lua" existir no sistema de arquivos, é executado automaticamente antes de iniciar o shell</li>
+ <li>Adicionado os móulos "pack" (compactação/descompactação de dados binário) e "bit" (operações binárias)</li>
+ <li>sistema de geração de <b>eLua</b> atualizado, fácil de usar, agora ele sabe como lidar com "placas", bem como CPUs</li>
+ <li>Modificado os módulos das plataformas já existentes para ocupar menos memória RAM e emitir um aviso de erro quando um recurso indisponÃvel é solicitado</li>
+ <li>A documentação do projeto foi atualizada</li>
+</ul></td>
+</tr>
+<tr>
+ <td align="center" style="color: rgb(255, 102, 0);">0.3</td>
+ <td align="center">09.08.2008</td>
+ <td><ul>
+ <li>Agora você pode jogar "forca" diretamente de <b>eLua</b> :), graças ao novo módulo "term" que manipula seqüências de escape ANSI</li>
+ <li>Adicionado suporte para a ST STR912FAW44</li>
+ <li>Adicionado suporte para o Cortex LM3S6965</li>
+ <li>Sistema de geração de <b>eLua</b> mais intuitivo e flexÃvel (nova sintaxe ,seleção de componentes em tempo de compilação)</li>
+ <li>Exemplos de eLua são agora parte do repositório</li>
+ <li>A documentação do projeto foi atualizada</li>
+</ul></td>
+</tr>
+<tr>
+ <td align="center" style="color: rgb(255, 102, 0);">0.2</td>
+ <td align="center">27.08.2008</td>
+ <td><ul>
+ <li>Adicionado suporte para o Cortex LM3S8962</li>
+ <li>Novos módulos de plataforma (UART, SPI, Timer, dados da plataforma)</li>
+ <li>Primeiro lançamento do shell</li>
+ <li>Arquivos fonte de Lua podem ser enviados para a placa com XMODEM</li>
+ <li>Pode-se baixar arquivos de imagem binários a partir da seção "files", dessa forma, não é necessário compilar <b>eLua</b></li>
+</ul></td>
+</tr>
+<tr>
+ <td align="center" style="color: rgb(255, 102, 0);">0.1</td>
+ <td align="center">11.08.2008</td>
+ <td><ul><li>Versão inicial, com suporte para as plataformas i386 e AT91SAM7X</li></ul></td>
+</tr>
+</tbody>
+</table>
+$$FOOTER$$
Deleted: branches/eagle_mmc/doc/readme.txt
===================================================================
--- branches/eagle_mmc/doc/readme.txt 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/readme.txt 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,58 +0,0 @@
- This document describes the eLua documentation structure, formats and the
-tools used to maintain it.
-
- eLua documentation is created and maintained offline, in HTML format and
-integrated with the same version control system used for eLua Source Code.
-This allows the same content to be deployed both online, published on the
-site, and offline, included in our releases.
- All the content pages are created and edited offline, using any HTML
-editor. We're currently using KompoZer and opened to new sugestions :)
-
- The "doc site" structure is created by a help doc generator tool called
-WebBook, created at Tecgraf/PUC-Rio. WebBook is Open Source and Free
-Software, 100% written in Lua and it's usage is described in
-http://www.tecgraf.puc-rio.br/webbook
- WebBook takes the created pages and a configuration file, which is simply
-a Lua Table, and generates the main menu and overall site structure, in
-plain HTML and JavaScript, with regular support for CSS. There is no need
-for JavaScript programming or cgi-bin scripts to "run" the site. The result
-is pure HTML (and JavaScript) and any browser must be able to navigate the
- complete doc structure generated by WebBook.
-
- eLua documentation is kept on the development repository, on the /doc
-directory, under the trunk, branch and/or tag versions.
- Different doc language versions are kept under their own sub-directories (ie:
-/doc/en for english, /doc/pt for portuguese, /doc/ro for romanian etc...)
-
- Directory /doc/wb is used to run WebBook build script and to store
-configuration files. It does NOT need to be published or included in an
-offline version of the doc "site".
- File wb_usr.lua is the main configuration file. It defines the main titles,
-menu structure, utility fields/buttons and the startup options.
- File wb_build.lua is the main WebBook build script. Some facilities (bat files)
- are included for easy build under Windows but we haven't tested them.
- To create a WebBook Structure site, just edit wb_usr.lua and, from /wb dir, run
-
-$ lua5.1 wb_build.lua
-
- Directories that needed to be published and included in the distros are:
-
-/doc (## maybe not all files but tests are required here ##)
-/doc/en (english version doc pages and optional style sheets)
-/doc/pt (portuguese version doc pages and optional style sheets)
-/doc/img (images, logos and art files)
-
- eLua Doc can be viewed on any browser, simply opening the file
-index_en.html (or index_pt.html for the portuguese version), on the /doc
-directory.
-
-
-
-
-
-
-
-
-
-
-
Deleted: branches/eagle_mmc/doc/style.css
===================================================================
--- branches/eagle_mmc/doc/style.css 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/style.css 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,134 +0,0 @@
-/* Generated by KompoZer */
-body {
- margin-left: 1em;
- margin-right: 1em;
- font-family: tahoma,verdana,arial,helvetica,geneva,sans-serif;
- background-color: #ffffff;
-}
-p {
- margin-left: 1em;
- line-height: 130%;
-}
-h2 {
- border: 1px solid #808080;
- padding: 4px;
- background-color: #aaffcc;
- font-size: 99%;
- margin-left: 1em;
-}
-h3 {
- border: 1px solid #808080;
- padding: 6px;
- background-color: #cee7ff;
- color: #5c5c5c;
-}
-table {
- margin-left: 1em;
-}
-pre {
- border: 1px dashed #62a0ff;
- padding: 4px;
- background-color: #cee7ff;
- font-family: 'Monotype.com',"Courier New",Courier,monospace;
- font-size: 90%;
- line-height: 125%;
- margin-left: 1em;
- margin-right: 1em;
- overflow: auto;
-}
-p.info {
- margin-left: 3em;
-}
-ul {
- margin-left: 2em;
-}
-ol {
- margin-left: 2em;
-}
-h4 {
- margin-left: 2em;
-}
-h1 {
- text-align: center;
-}
-table {
- border-collapse: collapse;
-}
-td {
- border: 1px solid #808080;
- padding: 5px;
-}
-th {
- border: 2px solid #808080;
- padding: 5px;
- background-color: #c0c0c0;
-}
-.homeTitle {
- font-family: Arial,Helvetica,sans-serif;
- font-size: 36pt;
- font-weight: bold;
- color: #003399;
- text-align: center;
-}
-.homeDescription {
- font-family: Arial,Helvetica,sans-serif;
- font-size: 20pt;
- color: #003399;
- text-align: center;
-}
-.homeVersion {
- margin: 10px;
- font-family: Arial,Helvetica,sans-serif;
- font-size: 16pt;
- color: #003399;
- text-align: center;
-}
-.bg_winxp {
- text-align: center;
- background-color: #ece9d8;
-}
-.bg_vista {
- text-align: center;
- background-color: #f0f0f0;
-}
-.bg_gtk {
- text-align: center;
- background-color: #efebe7;
-}
-.bg_mot {
- text-align: center;
- background-color: #adb1c2;
-}
-.bg_win2k {
- text-align: center;
- background-color: #d4d0c8;
-}
-#navigation {
- position: fixed;
- top: 0;
- right: 0;
- background-color: #e1e1e1;
-}
-#navigation ul {
- margin: 0;
- padding: 0;
- list-style-type: none;
-}
-#navigation li {
- float: left;
-}
-#navigation a {
- border: 1px solid #808080;
- padding: 3px;
- color: #5c5c5c;
- text-decoration: none;
- display: block;
- background-color: #e1e1e1;
- font-size: small;
-}
-#navigation a:hover {
- border: 1px solid #808080;
- color: #e1e100;
- text-decoration: none;
- background-color: #5c5c5c;
-}
Added: branches/eagle_mmc/doc/style1.css
===================================================================
--- branches/eagle_mmc/doc/style1.css 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/style1.css 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,212 @@
+/*******************************************************************************
+ * Generic styling
+ ******************************************************************************/
+
+body {
+ padding: 0;
+ margin: 0;
+ font-family: tahoma,verdana,arial,helvetica,geneva,sans-serif;
+ background-color: #ffffff;
+}
+
+pre {
+ border: 1px dashed #ffbb22;
+ padding: 4px;
+ background-color: #ffddaa;
+ font-family: 'Monotype.com',"Courier New",Courier,monospace;
+ font-size: 90%;
+ line-height: 125%;
+ margin-left: 1em;
+ overflow: auto;
+}
+
+/*******************************************************************************
+ * Main layout
+ ******************************************************************************/
+
+/* Assume a logo size of 80x80 pixels! */
+#logo {
+ background-image: url(images/title_background.png);
+ background-repeat: no-repeat;
+ background-position:right;
+ color:#000;
+font: bold 150%/100% tahoma, Arial, sans-serif;
+ height: 90px;
+ margin: 0;
+ padding: 0;
+ width: 100%;
+ border-bottom: 0px solid #E7F1FA;
+}
+
+.logo_elua{
+margin-top:10px;
+margin-left:10px;
+}
+
+#nav, #menu {
+ float: left;
+ width: 170px;
+ margin-left: 8px;
+ padding-top: 5px;
+}
+
+#content {
+ padding-top: 10px;
+ margin: 0 8px 8px 181px;
+}
+
+/*******************************************************************************
+ * Logo styling
+ ******************************************************************************/
+
+#logo h6.selected {
+/* margin: 2px 4px 2px 4px;
+ padding: 2px;
+ background-color: #137096;
+ color: white;
+
+opacity:1.0;filter:alpha(opacity=100);
+*/
+}
+
+#logo h6 {
+ margin: 2px 4px 2px 4px;
+ padding: 2px;
+ #background-color: white;
+ color: #137096;
+}
+
+.header_title{
+ font-size:36px;
+ color:#0b0c79;
+ font-weight:bold;
+ padding-left:20px;
+}
+
+h6{
+ font-size:10px;
+}
+
+#logo a {
+ text-decoration: none;
+ padding: 2px 4px 2px 4px;
+}
+
+#logo a.lang img{
+border: 0px
+}
+
+#logo a.lang:hover {
+#border: 2px solid #ccc;
+# text-decoration: none;
+# background-color: blue;
+# color: white;
+}
+
+/*******************************************************************************
+ * Content styling
+ ******************************************************************************/
+
+#content p {
+ line-height: 120%;
+ padding-left: 1em;
+}
+
+#content h2 {
+ border: 1px solid #808080;
+ padding: 4px;
+ background-color: #a0ffa0;
+ font-size: 99%;
+ margin-left: 1em;
+}
+
+#content h3 {
+ border: 1px solid #808080;
+ padding: 5px;
+ background-color: #cee7ff;
+ color: #5c5c5c;
+ margin: 0;
+}
+
+#content table {
+ margin-left: 1em;
+}
+
+#content p.info {
+ margin-left: 3em;
+}
+
+#content p.doc {
+ margin-left: 2em;
+}
+
+#content ul {
+ padding-left: 1em;
+ margin-left: 40px;
+}
+
+#content ol {
+ margin-left: 2em;
+}
+
+#content h4 {
+ margin-left: 2em;
+}
+
+#content table {
+ border-collapse: collapse;
+}
+#content td {
+ border: 1px solid #808080;
+ padding: 5px;
+}
+#content th {
+ border: 2px solid #808080;
+ padding: 5px;
+ background-color: #c0c0c0;
+}
+
+/*******************************************************************************
+ * Table types
+ ******************************************************************************/
+
+table.invisible {
+ border: 0px solid black;
+ border-collapse: collapse;
+ margin-left: auto;
+ margin-right: auto;
+ margin-top: 4px;
+}
+
+table.invisible td {
+ text-align: center;
+ border: 0px solid black;
+}
+
+/*******************************************************************************
+ * Other styles
+ ******************************************************************************/
+
+.docdiv {
+ padding-left: 1em;
+}
+
+.docdiv pre {
+ margin-left: 0;
+}
+
+.code {
+ border: 0;
+ padding: 4px;
+ background-color: white;
+ font-family: "Courier New",Courier,monospace;
+ font-size: 90%;
+ padding-left: 1em;
+ overflow: auto;
+}
+
+.warning {
+ color: red;
+ font-weight: bold;
+}
+
Deleted: branches/eagle_mmc/doc/wb/js2lua.bat
===================================================================
--- branches/eagle_mmc/doc/wb/js2lua.bat 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/wb/js2lua.bat 2009-11-06 02:08:32 UTC (rev 526)
@@ -1 +0,0 @@
- at lua5.1 js2lua.lua %1 %2
Deleted: branches/eagle_mmc/doc/wb/js2lua.lua
===================================================================
--- branches/eagle_mmc/doc/wb/js2lua.lua 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/wb/js2lua.lua 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,28 +0,0 @@
--- Convert JavaScript into Lua
-
-if (not arg[1]) then
- error("Javascript filename must be passed as a parameter.")
-end
-if (not arg[2]) then
- error("Lua filename must be passed as a parameter.")
-end
-
-print("Converting...")
-
-local js_filename = arg[1]
-local file = io.open(js_filename)
-local wb_lua = file:read("*a")
-file:close()
-
-wb_lua = string.gsub(wb_lua, ":", "=")
-wb_lua = string.gsub(wb_lua, "http=", "http:")
-wb_lua = string.gsub(wb_lua, ";", " ")
-wb_lua = string.gsub(wb_lua, "%[", "{")
-wb_lua = string.gsub(wb_lua, "%]", "}")
-
-local lua_filename = arg[2]
-local file = io.open(lua_filename, "w")
-file:write(wb_lua)
-file:close()
-
-print("Done.")
Deleted: branches/eagle_mmc/doc/wb/make_hh.lua
===================================================================
--- branches/eagle_mmc/doc/wb/make_hh.lua 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/wb/make_hh.lua 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,274 +0,0 @@
----------------------------------------------------------------------
--- This program converts from Tecgraf's WebBook to HTML Help Project Files.
--- by Mark Stroetzel Glasberg and Antonio Scuri
--- 09 Dec, 2004
----------------------------------------------------------------------
-
-languages_description = {
- en = "0x0409 English - United States",
- es = "0x040A Spanish - Standard",
- fr = "0x040C French - Standard",
- de = "0x0407 German - Standard",
--- pt = "0x0816 Portuguese - Standard",
- pt = "0x0416 Portuguese - Brazil",
- it = "0x0410 Italian - Standard"
-}
-
--- INITIALIZATION ---------------------------------------------------
-
-function isinlist(lng, list)
- local i = 1
- local n = #list
- while i <= n do
- if list[i] == lng then
- return 1
- end
- i = i + 1;
- end
- return nil
-end
-
--- BASIC FUNCTIONS --------------------------------------------------
-
-function out(string)
- file:write(string)
-end
-
-function outln(string)
- local i = ident + 1
- while i>0 do
- file:write(" ")
- i = i - 1
- end
- file:write(string.."\n")
-end
-
--- HHP FILE FUNCTIONS ------------------------------------------------
-
-files = {}
-
-function add2files(v)
- if v then
- -- only up to "#"
- local j = string.find(v, "#")
- if j then
- f = string.sub(v, 0, j-1)
- else
- f = v
- end
-
- files[f] = f
- end
-end
-
-function writehhpheader()
- out("[OPTIONS]\n")
- outln("Binary Index=No")
- outln("Compatibility=1.0")
- outln("Compiled file=" .. wb_usr.file_title .. "_" .. lng .. ".chm")
- outln("Contents file=wb_tree" .. "_" .. lng .. ".hhc")
- outln("Default topic=" .. lng .. "/" .. wb_usr.tree.link)
- outln("Display compile notes=Yes")
- outln("Display compile progress=Yes")
- outln("Full-text search=Yes")
- outln("Language="..languages_description[lng])
- outln("Title="..wb_usr.messages[lng].title)
- out("\n")
- out("[FILES]\n")
- outln(lng .. "/" .. wb_usr.tree.link)
-end
-
-function writehhpfooter()
- local tmp = [[
-[INFOTYPES]
- ]]
- out(tmp)
-end
-
-function writehhpcenter()
- if (not files) then return end
-
- local v = next(files, nil)
- while v ~= nil do
- outln(dir..v)
- v = next(files, v)
- end
-end
-
-function writehhp()
- writehhpheader()
- writehhpcenter()
- writehhpfooter()
-end
-
-
--- HHC FILE FUNCTIONS ------------------------------------------------
-
-function writeheader()
- out("<!DOCTYPE HTML PUBLIC \"-//IETF//DTD HTML//EN\">\n")
- out("<!DOCTYPE HTML PUBLIC \"-//IETF//DTD HTML//EN\">\n")
- out("<HTML>\n")
- out("<HEAD>\n")
- out("<meta name=\"GENERATOR\" content=\"Microsoft® HTML Help Workshop 4.1\">\n")
- out("<!-- Sitemap 1.0 -->\n")
- out("<!-- Generated by WebBook -->\n")
- out("</HEAD><BODY>\n")
- out(" <UL>\n")
- out(" <LI> <OBJECT type=\"text/sitemap\">\n")
- out(" <param name=\"Name\" value=\""..wb_usr.messages[lng].title.."\">\n")
- out(" <param name=\"Local\" value=\""..lng .. "/" .. wb_usr.tree.link .. "\">\n")
- out(" </OBJECT>\n")
-end
-
-function type_string (o)
- return type(o) == "string"
-end
-
-function writeend()
- out(" </UL>\n")
- out("</BODY>\n")
- out("</HTML>\n")
-end
-
-function writesubitems(tree, mainlink)
- if (not tree) then
- return
- end
- local i = 1
- local n = #tree
- while i <= n do
- writetopic(tree[i], mainlink)
- i = i + 1
- end
- ident = ident - 1
-end
-
--- mainlink is the link of the father -> if no link is specified
--- this is the one that is used.
-function writetopic(t, mainlink)
- local link
- local topic_name
-
- add2files(mainlink)
-
- if t.name == nil then
- print("ERROR: Title is nil.")
- return
- end
-
- if (t.name[lng]) then
- topic_name = t.name[lng]
- else
- topic_name = t.name["nl"]
- end
-
- if topic_name == nil then
- print("ERROR: Title is nil in language [" .. lng .. "].")
- return
- end
-
- if t.link and t.link ~= "" then
- link = t.link
- else
- link = nil
- end
-
- add2files(link)
-
- if t.bookmark then
- if link == nil and mainlink == nil then
- print("Error saving bookmark!!!")
- return
- end
-
- if link then
- linkB = link .. "#" .. t.bookmark
- else
- linkB = mainlink .. "#" .. t.bookmark
- end
- else
- linkB = nil
- end
-
- outln("<LI> <OBJECT type=\"text/sitemap\">")
- outln("<param name=\"Name\" value=\""..topic_name.."\">")
- if linkB then
- outln("<param name=\"Local\" value=\""..dir..linkB.."\">")
- else
- if link then
- outln("<param name=\"Local\" value=\""..dir..link.."\">")
- end
- end
- if useimage == 1 then
- if t.folder then
- if ident == 0 then
- outln("<param name=\"ImageNumber\" value=\"1\">")
- else
- outln("<param name=\"ImageNumber\" value=\"6\">")
- end
- else
- outln("<param name=\"ImageNumber\" value=\"11\">")
- end
- end
- outln("</OBJECT>")
-
- -- Write folder --
- if t.folder then
- ident = ident + 1
- outln("<UL>")
- if link == nil then
- writesubitems(t.folder, mainlink)
- else
- writesubitems(t.folder, link)
- end
- outln("</UL>")
- end
-
-end
-
-function writetopics(tree)
- if (not tree) then return end
- local i = 1;
- local n = #tree
- while i <= n do
- outln("<UL>")
- writetopic(tree[i], nil)
- outln("</UL>")
- i = i + 1
- end
-end
-
--- MAIN -------------------------------------------------------------
-
--- lng -> from the command line
-
-dofile("wb_usr.lua")
-
-if (not arg[1]) then
- error("Missing language parameter.")
-end
-
-lng = arg[1]
-dir = lng.."/"
-ident = 0
-useimage = 1 -- Use images based on given information
-file = nil
-
-print("Writing \"wb_tree" .. "_" .. lng .. ".hhc\" file.")
-file = io.open("wb_tree" .. "_" .. lng .. ".hhc", "w")
-writeheader()
-writetopics(wb_usr.tree.folder)
-writeend()
-file:close()
-
-if ident ~= 0 then
- print("Ident not correct!")
-end
-
-print("Writing \"wb" .. "_" .. lng .. ".hhp\" file.")
-file = io.open("wb" .. "_" .. lng .. ".hhp", "w")
-writehhp()
-file:close()
-
-print("done.")
-
Deleted: branches/eagle_mmc/doc/wb/template_index.html
===================================================================
--- branches/eagle_mmc/doc/wb/template_index.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/wb/template_index.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,28 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html>
-
-<head>
-<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
-<title>WB_TITLE</title>
-</head>
-
-<frameset rows="TITLE_BAR_HEIGHT,*" frameborder="0" framespacing="0" bordercolor="#0B6DCE">
- <frame name="wb_title" scrolling="no" noresize="noresize" src="wb_titleWB_LNG.html"
- frameborder="0" marginheight="0" marginwidth="0" target="wb_cont">
- <frameset cols="WB_START_SIZE,*" frameborder="1" framespacing="4" bordercolor="#0B6DCE" border="4">
- <frameset rows="27,*" frameborder="0" framespacing="0" bordercolor="#0B6DCE">
- <frame name="wb_bar" scrolling="no" src="wb_barWB_LNG.html" frameborder="0" target="wb_cont">
- <frame name="wb_tree" src="wb_treeWB_LNG.html" frameborder="1" target="wb_cont">
- </frameset>
- <frame name="wb_cont" src="WB_START_PAGE" frameborder="0">
- </frameset>
- <noframes>
- <body>
-
- <p>This page uses frames, but your browser doesn't support them.</p>
-
- </body>
- </noframes>
-</frameset>
-
-</html>
Deleted: branches/eagle_mmc/doc/wb/template_ssSearch.html
===================================================================
--- branches/eagle_mmc/doc/wb/template_ssSearch.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/wb/template_ssSearch.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,25 +0,0 @@
-<html>
-<head>
-<title>ssSearch</title>
-<link rel="stylesheet" type="text/css" href="style.css">
-</head>
-<body>
-<h3>WB_SEARCH</h3>
-<blockquote>
-<center>
- <applet code="ssSearch.class" width="640" height="480">
- <param name="BGCOLOR" value="0B6DCE">
- <param name="LISTAREACOLOR" value="ffffff">
- <!-- Use "_self", "_blank", "_parent", "_top" or any other user-defined name -->
- <param name="TARGETFRAME" value="_self">
- <param name="DATAFILE" value="wb_searchWB_LNG.txt">
- <!-- The APPLETHOME param is just an acknowledgement -->
- <!-- Do not edit the value of APPLETHOME param -->
- <param name="APPLETHOME" value="http://www.geocities.com/SiliconValley/Lakes/5365/index.html">
- </applet>
-</center>
-</blockquote>
-<p>Powered by <a href="http://us.geocities.com/nsenthil/ssSearch.html">ssSearch</a>
-from Nalla
-Senthilnathan.</p>
-</body></html>
Deleted: branches/eagle_mmc/doc/wb/template_wb_bar.html
===================================================================
--- branches/eagle_mmc/doc/wb/template_wb_bar.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/wb/template_wb_bar.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,29 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html>
-<head>
-<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
- <title>Bar</title>
- <base target="wb_cont">
- <style type="text/css">
- .navigation{
- padding: 0;
- margin: 0;
- white-space: nowrap;
- border: 1px solid #7F93C7;
- background-color: #FFFFFF;
- line-height: 19px;
- }
- .navigation p { margin: 1px; white-space: nowrap; }
- .navigation img { vertical-align: middle; }
- </style>
-</head>
-
-<body style="margin: 2px; background-color: #F1F1F1">
- <div class="navigation">
- <p><a target="_blank" href="http://www.eluaproject.net"><img src="wb_img/logo.png" style="border-width: 0px"></a>
- <img src="wb_img/barlineleft.png"><img alt="WB_EXPALL_ALT" src="wb_img/showall.png" onclick="parent.wb_tree.showAllFolders()" onmouseover="this.src='wb_img/showall_over.png'" onmouseout="this.src='wb_img/showall.png'"><img alt="WB_CONTALL_ALT" src="wb_img/hideall.png" onclick="parent.wb_tree.hideAllFolders()" onmouseover="this.src='wb_img/hideall_over.png'" onmouseout="this.src='wb_img/hideall.png'"><img alt="WB_SYNC_ALT" src="wb_img/sync.png" onclick="parent.wb_tree.syncContents()" onmouseover="this.src='wb_img/sync_over.png'" onmouseout="this.src='wb_img/sync.png'"><img alt="WB_NEXT_ALT" src="wb_img/next.png" onclick="parent.wb_tree.nextContents()" onmouseover="this.src='wb_img/next_over.png'" onmouseout="this.src='wb_img/next.png'"><img alt="WB_PREV_ALT" src="wb_img/previous.png" onclick="parent.wb_tree.prevContents()" onmouseover="this.src='wb_img/previous_over.png'" onmouseout="this.src='wb_img/previous.png'">WB_LNG_BUTTON
-
- </p>
- </div>
-</body>
-</html>
Deleted: branches/eagle_mmc/doc/wb/template_wb_search.html
===================================================================
--- branches/eagle_mmc/doc/wb/template_wb_search.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/wb/template_wb_search.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,11 +0,0 @@
-
- <FORM method=GET action="http://www.google.com/search" style="margin-bottom: 0; margin: 0; text-align: center;font-size:12px;font-family:verdana;">
- <input type="hidden" name="ie" value="UTF-8" />
- <input type="hidden" name=oe value="UTF-8" />
- WB_SEARCH_LABEL
- <INPUT TYPE="text" name="q" size="21" maxlength="255" value="" />
- <INPUT type="submit" name="btnG" VALUE="Search" style="height: 21px; vertical-align: top; font-size: x-small;" />
- <input type="hidden" name="domains" value="WB_SEARCH_LINK" />
- <input type="hidden" name="sitesearch" value="WB_SEARCH_LINK" />
- </FORM>
-
Deleted: branches/eagle_mmc/doc/wb/template_wb_title.html
===================================================================
--- branches/eagle_mmc/doc/wb/template_wb_title.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/wb/template_wb_title.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,58 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<head>
-<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
-
-<title>Title</title>
-<base target="wb_cont">
-<style type="text/css">
-td.title {
- font-family: Arial, Helvetica, sans-serif;
- font-size: 16pt;
- font-weight: bold;
- color: #FFFFFF;
- text-align: left;
- vertical-align: middle;
-}
-td.contact {
- text-align: center;
- vertical-align: middle;
- /*width: 11em;*/
-}
-a.contact {
- font-family: Arial, Helvetica, sans-serif;
- color: #0962BB;
- font-size: 9pt;
- text-decoration: none;
- font-weight: bold;
-}
-a.contact:hover {
- text-decoration: underline;
-}
-</style>
-</head>
-
-<body style="background-color: WB_TITLE_BGCOLOR; margin-left: 3px; margin-right: 3px; margin-top: 2px; margin-bottom: 0; background-image: url('wb_img/title_background.png');">
-
-<table border="0" style="width: 100%;" cellspacing="0" cellpadding="0">
- <tr>
- <td valign="center" style="width: 30px;padding:0px 10px 0px 0px;">
- WB_LOGO
- </td>
- <td valign="center" class="title">WB_BAR_TITLE</td>
- <!--td style="width: 3.5em">
- <a class="contact" href="ssSearchWB_LNG.html">SimpleSearch</a>
- </td-->
- <td style="width: 280px" >
- WB_SEARCH_FORM
- </td>
- <td class="contact">
- WB_COPYRIGHT
- <br>
- WB_CONTACT
- </td>
- </tr>
-</table>
-
-</body>
-
-</html>
Deleted: branches/eagle_mmc/doc/wb/template_wb_tree.html
===================================================================
--- branches/eagle_mmc/doc/wb/template_wb_tree.html 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/wb/template_wb_tree.html 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,220 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html>
-<head>
-<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
- <title>Tree</title>
- <base target="wb_cont">
- <style type="text/css">
- .tree { font-family: helvetica, sans-serif; font-size: 10pt; }
- .tree h3 {
- margin: 5px 0px 0px 0px;
- font-size: 12pt;
- }
- .tree p { margin: 0px; white-space: nowrap; }
- .tree p.sep { margin: 0px; white-space: nowrap; line-height: 8px; font-size: 5px; }
- .tree div { display: none; margin: 0px; }
- .tree img { vertical-align: middle; }
- .tree a.el { text-decoration: none; margin-left: 4px; color: #003366; }
- .tree a:hover { text-decoration: none; background-color: #e0e0ff }
- </style>
- <script type="text/javascript">
- lastLink = null;
-
- function hideFolder(folder, id)
- {
- var imageNode = document.images["img" + id];
- if (imageNode != null)
- {
- var len = imageNode.src.length;
- if (imageNode.src.substring(len-8,len-4) == "last")
- imageNode.src = "wb_img/plusnodelast.png";
- else if (imageNode.src.substring(len-8,len-4) == "node")
- imageNode.src = "wb_img/plusnode.png";
- }
- folder.style.display = "none";
- }
-
- function showFolder(folder, id)
- {
- var imageNode = document.images["img" + id];
- if (imageNode != null)
- {
- var len = imageNode.src.length;
- if (imageNode.src.substring(len-8,len-4) == "last")
- imageNode.src = "wb_img/minusnodelast.png";
- else if (imageNode.src.substring(len-8,len-4) == "node")
- imageNode.src = "wb_img/minusnode.png";
- }
- folder.style.display = "block";
- }
-
- function toggleFolder(id)
- {
- var folder = document.getElementById(id);
- if (folder.style.display == "block")
- hideFolder(folder, id);
- else
- showFolder(folder, id);
- }
-
- function setFoldersAtLevel(level, show)
- {
- var i = 1;
- do
- {
- var folder_id = level + "." + i;
- var id = "folder" + folder_id;
- var folder = document.getElementById(id);
- if (folder != null)
- {
- setFoldersAtLevel(folder_id, show);
-
- if (show)
- showFolder(folder, id);
- else
- hideFolder(folder, id);
- }
- i++;
- } while(folder != null);
- }
-
- function showAllFolders()
- {
- setFoldersAtLevel("", true);
- }
-
- function hideAllFolders()
- {
- setFoldersAtLevel("", false);
- }
-
- function getFolderId(name)
- {
- return name.substring(name.indexOf("folder"), name.length);
- }
-
- function showFolderRec(id)
- {
- var folder = document.getElementById(id);
- if (folder != null)
- {
- showFolder(folder, id);
-
- var parent_id = id.substring(0, id.lastIndexOf("."))
- if (parent_id != null && parent_id != "folder")
- {
- showFolderRec(parent_id)
- }
- }
- }
-
- function clearLastLink()
- {
- if (lastLink != null)
- {
- lastLink.style.color = ""
- lastLink = null;
- }
- }
-
- function goToLink(link)
- {
- var id = getFolderId(link.name);
- showFolderRec(id);
- location.hash = "#" + link.name;
- link.style.color = "#ff0000";
-
- clearLastLink();
- lastLink = link;
- }
-
- function syncContents()
- {
- var cur_topic = parent.wb_cont.location.href
-
- for (var i = 0; i < document.links.length; i++)
- {
- var link = document.links[i];
- if (cur_topic == link.href)
- {
- goToLink(link)
- return
- }
- }
- }
-
- function nextContents()
- {
- var cur_topic = parent.wb_cont.location.href
-
- for (var i = 0; i < document.links.length; i++)
- {
- var link = document.links[i];
- if (cur_topic == link.href)
- {
- if (i == document.links.length-1)
- link = document.links[0];
- else
- link = document.links[i+1];
-
- goToLink(link)
- parent.wb_cont.location.href = link.href;
- return
- }
- }
- }
-
- function prevContents()
- {
- var cur_topic = parent.wb_cont.location.href
- var prev_link = document.links[document.links.length-1]
-
- for (var i = 0; i < document.links.length; i++)
- {
- var link = document.links[i];
- if (cur_topic == link.href)
- {
- if (i == 0)
- link = document.links[document.links.length-1];
- else
- link = document.links[i-1];
-
- goToLink(link)
- parent.wb_cont.location.href = link.href;
- return
- }
- }
- }
-
- function showStartPage()
- {
- var full_url = parent.document.URL;
- if (full_url == null)
- return;
-
- var param = full_url.substring(full_url.indexOf("?") + 1, full_url.length);
- if (param == null)
- return;
-
- var param_url = param.substring(param.indexOf("url=") + 4, param.length);
- if (param_url == null)
- return;
-
- var param_len = param_url.length;
- for (var i = 0; i < document.links.length; i++)
- {
- var link = document.links[i];
- var link_url = link.href.substring(link.href.length-param_len, link.href.length)
- if (link_url == param_url)
- {
- goToLink(link)
- parent.wb_cont.location.href = link.href;
- return
- }
- }
- }
- </script>
-</head>
-
-<body style="margin: 2px; background-color: #F1F1F1" onload="showStartPage()">
- <div class="tree" onmouseout="clearLastLink()">
Deleted: branches/eagle_mmc/doc/wb/wb2hh.bat
===================================================================
--- branches/eagle_mmc/doc/wb/wb2hh.bat 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/wb/wb2hh.bat 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,29 +0,0 @@
- at echo off
-
-Echo Building...
-lua5.1 make_hh.lua %1
-Echo .
-pause
-
-Echo Preparing...
-move wb_%1.hhp ..
-move wb_tree_%1.hhc ..
-cd ..
-move download download.old
-Echo .
-pause
-
-Echo Compiling...
-hhc wb_%1.hhp
-Echo .
-pause
-
-Echo Finishing...
-move wb_%1.hhp wb
-move wb_tree_%1.hhc wb
-move download.old download
-move /y *.chm download
-cd wb
-Echo .
-
-Echo Done.
Deleted: branches/eagle_mmc/doc/wb/wb_build.bat
===================================================================
--- branches/eagle_mmc/doc/wb/wb_build.bat 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/wb/wb_build.bat 2009-11-06 02:08:32 UTC (rev 526)
@@ -1 +0,0 @@
- at lua5.1 wb_build.lua
Deleted: branches/eagle_mmc/doc/wb/wb_build.lua
===================================================================
--- branches/eagle_mmc/doc/wb/wb_build.lua 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/wb/wb_build.lua 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,395 +0,0 @@
-
-dofile("wb_usr.lua")
-
-lngCount = nil
-lngSuffix = nil
-lngIndex = nil
-lngNext = nil
-linkCount = 1
-
-function readFile(filename)
- local file = io.open(filename)
- local text = file:read("*a")
- file:close()
- return text
-end
-
-function writeFile(filename, text)
- local file = io.open(filename, "w")
- file:write(text)
- file:close()
-end
-
--- #####################################################################
-
-htmlFiles = {}
-
-function addHtmlFile(v)
- if v then
- -- only up to "#"
- local j = string.find(v, "#")
- if j then
- f = string.sub(v, 0, j-1)
- else
- f = v
- end
-
- htmlFiles[f] = f
- end
-end
-
--- #####################################################################
-function loadSearch()
- local searchHTML = readFile("template_wb_search.html")
-
- if(wb_usr.enable_search == true)then
- searchHTML = string.gsub(searchHTML, "WB_SEARCH_LABEL", wb_usr.search_label or "")
- searchHTML = string.gsub(searchHTML, "WB_SEARCH_LINK", wb_usr.search_link)
- else
- searchHTML = ""
- end
- return searchHTML
-end
-
-function writeIndexFile()
- print("Writing \"../index"..lngSuffix..".html\".")
-
- local wb_index = readFile("template_index.html")
-
- wb_index = string.gsub(wb_index, "WB_TITLE", wb_usr.messages[lngIndex].title)
- wb_index = string.gsub(wb_index, "TITLE_BAR_HEIGHT", wb_usr.title_bar_height or 51)
- wb_index = string.gsub(wb_index, "WB_START_SIZE", wb_usr.start_size)
- wb_index = string.gsub(wb_index, "WB_START_PAGE", lngIndex.."/"..wb_usr.tree.link)
- if (lngCount > 1) then
- wb_index = string.gsub(wb_index, "WB_LNG", lngSuffix)
- else
- wb_index = string.gsub(wb_index, "WB_LNG", "")
- end
-
- writeFile("../index"..lngSuffix..".html", wb_index)
-end
-
--- #####################################################################
-
-function writeTitleFile()
- print("Writing \"../wb_title"..lngSuffix..".html\".")
-
- local wb_title = readFile("template_wb_title.html")
- if(wb_usr.logo_image_file ~= nil and wb_usr.logo_image_file ~= "")then
- wb_title = string.gsub(wb_title, "WB_LOGO", [[<A href="]]..wb_usr.logo_onclick_link..[[" target="blank"><img src="wb_img/]]..wb_usr.logo_image_file..[[" border="0"></A>]])
- else
- wb_title = string.gsub(wb_title, "WB_LOGO","")
- end
-
- wb_title = string.gsub(wb_title, "WB_BAR_TITLE", wb_usr.messages[lngIndex].bar_title)
- wb_title = string.gsub(wb_title, "WB_TITLE_BGCOLOR", wb_usr.title_bgcolor)
- wb_title = string.gsub(wb_title, "WB_SEARCH_FORM",loadSearch())
-
- local copyrightHTML = ""
- if (wb_usr.copyright_link ~= nil and wb_usr.copyright_name ~= nil and wb_usr.copyright_link ~= "" and wb_usr.copyright_name ~= "")then
- copyrightHTML = [[<a class="contact" target="_blank" href="WB_COPYRIGHT_LINK">© WB_COPYRIGHT_NAME</a>]]
- copyrightHTML = string.gsub(copyrightHTML, "WB_COPYRIGHT_LINK", wb_usr.copyright_link)
- copyrightHTML = string.gsub(copyrightHTML, "WB_COPYRIGHT_NAME", wb_usr.copyright_name)
- end
- wb_title = string.gsub(wb_title, "WB_COPYRIGHT", copyrightHTML)
-
- local contactHTML = ""
- if wb_usr.contact ~= nil and wb_usr.contact ~= "" then
- contactHTML = string.gsub([[<a class="contact" href="mailto:WB_CONTACT">(WB_CONTACT)</a>]], "WB_CONTACT", wb_usr.contact)
- end
- wb_title = string.gsub(wb_title, "WB_CONTACT", contactHTML)
-
- if (lngCount > 1) then
- wb_title = string.gsub(wb_title, "WB_LNG", lngSuffix)
- else
- wb_title = string.gsub(wb_title, "WB_LNG", "")
- end
-
- writeFile("../wb_title"..lngSuffix..".html", wb_title)
-end
-
--- #####################################################################
-
-function writeIndent(file, level)
- -- base identation
- file:write(" ")
-
- for i = 1, level*2, 1 do
- file:write(" ")
- end
-end
-
-function getNodeName(node)
- local name = nil
- if (node.name[lngIndex]) then
- name = node.name[lngIndex]
- else
- name = node.name["nl"]
- end
-
- if not name then
- error("Name not found.")
- end
-
- return name
-end
-
-function writeNode(file, node, opened, level, folder_index, folder_suffix, node_suffix, child_prefix)
- if (node.folder) then -- folder
- -- box image
- writeIndent(file, level)
- file:write("<p>")
-
- folder_suffix = folder_suffix .. "." .. folder_index
-
- file:write(child_prefix.."<img name=\"imgfolder"..folder_suffix.."\" ")
-
- if (opened) then
- file:write("src=\"wb_img/minusnode"..node_suffix..".png\" ")
- else
- file:write("src=\"wb_img/plusnode"..node_suffix..".png\" ")
- end
-
- file:write("onclick=\"toggleFolder('folder"..folder_suffix.."')\">")
-
- if (node.link) then
- file:write("<a name=\"link"..linkCount.."folder"..folder_suffix.."\" class=\"el\" href=\""..lngIndex.."/"..node.link.."\">"..getNodeName(node).."</a>")
- addHtmlFile(node.link)
- linkCount = linkCount + 1
- else
- file:write(" "..getNodeName(node))
- end
-
- file:write("</p>\n")
-
- -- folder div
- writeIndent(file, level)
- if (opened) then
- file:write("<div id=\"folder"..folder_suffix.."\" style=\"display:block\">\n")
- else
- file:write("<div id=\"folder"..folder_suffix.."\">\n")
- end
-
- local n = #(node.folder)
- local next_folder_index = 0
- local next_node_suffix = ""
- local next_child_prefix = "<img src=\"wb_img/vertline.png\">"
- if (node_suffix == "last") then
- next_child_prefix = "<img src=\"wb_img/blank.png\">"
- end
- for i = 1, n, 1 do
- if (i == n) then
- next_node_suffix = "last"
- end
- if (node.folder[i].folder) then
- next_folder_index = next_folder_index + 1
- end
- writeNode(file, node.folder[i], false, level+1, next_folder_index, folder_suffix, next_node_suffix, child_prefix..next_child_prefix)
- end
-
- writeIndent(file, level)
- file:write("</div>\n")
- else -- leaf
- if (node.link and node.link ~= "") then -- normal leaf
- writeIndent(file, level)
- file:write("<p>"..child_prefix.."<img src=\"wb_img/node"..node_suffix..".png\"><a class=\"el\" name=\"link"..linkCount.."folder"..folder_suffix.."\" href=\""..lngIndex.."/"..node.link.."\">"..getNodeName(node).."</a></p>\n")
- addHtmlFile(node.link)
- linkCount = linkCount + 1
- else -- separator leaf
- writeIndent(file, level)
- file:write("<p class=\"sep\">")
-
- local sep_child_prefix = string.gsub(child_prefix, "/vertline", "/sepvertline")
- sep_child_prefix = string.gsub(sep_child_prefix, "/blank", "/sepblank")
-
- file:write(sep_child_prefix.."<img src=\"wb_img/sepnode.png\"></p>\n")
- end
- end
-end
-
-function writeTree(file)
- -- root node
- file:write(" <h3><a name=\"link0folder.0\" class=\"el\" href=\""..lngIndex.."/"..wb_usr.tree.link.."\">"..getNodeName(wb_usr.tree).."</a></h3>\n")
- addHtmlFile(wb_usr.tree.link)
-
- local folder = wb_usr.tree.folder
- local n = #folder
- local node_suffix = ""
- local folder_index = 0
- for i = 1, n, 1 do
- if (i == n) then
- node_suffix = "last"
- end
- if (folder[i].folder) then
- folder_index = folder_index + 1
- end
- if (i == 1 and wb_usr.start_open) then
- writeNode(file, folder[i], true, 1, folder_index, "", node_suffix, "")
- else
- writeNode(file, folder[i], false, 1, folder_index, "", node_suffix, "")
- end
- end
-end
-
-function writeTreeFile()
- print("Writing \"../wb_tree"..lngSuffix..".html\".")
-
- local file = io.open("../wb_tree"..lngSuffix..".html", "w")
-
- -- Write Header
- local wb_tree = readFile("template_wb_tree.html")
- file:write(wb_tree)
-
- -- Write Tree Nodes and Leafs
- writeTree(file)
-
- -- Write Footer
- file:write(" </div>\n")
- if wb_usr.tree.footer then
- file:write(wb_usr.tree.footer)
- end
- file:write("</body>\n")
- file:write("</html>\n")
-
- file:close()
-end
-
--- #####################################################################
-
-lngMessages =
-{
- search= {
- en= "Simple Search",
- pt= "Busca Simples",
- es= "Busca Simples",
- },
- exp_all= {
- en= "Expand All Nodes",
- pt= "Expande Todos os Nós",
- es= "Ensanchar Todos Nodos",
- },
- cont_all= {
- en= "Contract All Nodes",
- pt= "Contrai Todos os Nós",
- es= "Contrato Todos Nodos",
- },
- sync= {
- en= "Sync Tree with Contents",
- pt= "Sincroniza Ãrvore com Conteúdo",
- es= "Sincroniza Ãrbol con el Contenido",
- },
- lang= {
- en= "Switch Language",
- pt= "Troca Idioma",
- es= "Cambie Idioma",
- },
- next= {
- en= "Next Link",
- pt= "Próximo Link",
- es= "Próximo Link",
- },
- prev= {
- en= "Previous Link",
- pt= "Link Anterior",
- es= "Link Anterior",
- },
-}
-
-function writeBarFile()
- print("Writing \"../wb_bar"..lngSuffix..".html\".")
-
- local file = io.open("../wb_bar"..lngSuffix..".html", "w")
-
- local wb_bar = readFile("template_wb_bar.html")
-
- wb_bar = string.gsub(wb_bar, "WB_EXPALL_ALT", lngMessages.exp_all[lngIndex])
- wb_bar = string.gsub(wb_bar, "WB_CONTALL_ALT", lngMessages.cont_all[lngIndex])
- wb_bar = string.gsub(wb_bar, "WB_SYNC_ALT", lngMessages.sync[lngIndex])
- wb_bar = string.gsub(wb_bar, "WB_NEXT_ALT", lngMessages.next[lngIndex])
- wb_bar = string.gsub(wb_bar, "WB_PREV_ALT", lngMessages.prev[lngIndex])
-
- if (lngCount > 1) then
- local lng_button = "<img src=\"wb_img/barlineright.png\">"
- lng_button = lng_button .. "<a target=\"_top\" href=\"index_"..lngNext..".html\"><img alt=\""..lngMessages.lang[lngIndex].."\" src=\"wb_img/lng"..lngSuffix..".png\" onmouseover=\"this.src='wb_img/lng"..lngSuffix.."_over.png'\" onmouseout=\"this.src='wb_img/lng"..lngSuffix..".png'\" style=\"border-width: 0px\"></a>"
- wb_bar = string.gsub(wb_bar, "WB_LNG_BUTTON", lng_button)
- else
- wb_bar = string.gsub(wb_bar, "WB_LNG_BUTTON", "")
- end
-
- file:write(wb_bar)
- file:close()
-end
-
--- #####################################################################
-
-function writeSearchFile()
- print("Writing \"../ssSearch"..lngSuffix..".html\".")
-
- local file = io.open("../ssSearch"..lngSuffix..".html", "w")
-
- local wb_search = readFile("template_ssSearch.html")
-
- wb_search = string.gsub(wb_search, "WB_SEARCH", lngMessages.search[lngIndex])
-
- if (lngCount > 1) then
- wb_search = string.gsub(wb_search, "WB_LNG", lngSuffix)
- else
- wb_search = string.gsub(wb_search, "WB_LNG", "")
- end
-
- file:write(wb_search)
- file:close()
-end
-
-function writeSearchIndexFile()
- print("Writing \"../wb_search"..lngSuffix..".txt\".")
-
- local file = io.open("../wb_search"..lngSuffix..".txt", "w")
-
- local v = next(htmlFiles, nil)
- while v ~= nil do
- file:write(lngIndex.."/"..v.."\n")
- v = next(htmlFiles, v)
- end
-
- file:close()
-end
-
--- #####################################################################
-
-lngCount = 0
-local first_name = nil
-local prev_elem = nil
-for name, elem in pairs(wb_usr.messages) do
- if (lngCount == 0) then
- first_name = name
- end
- lngCount = lngCount + 1
- if (prev_elem) then
- prev_elem.next = name
- end
- prev_elem = elem
-end
-prev_elem.next = first_name
-
-print("Building...")
-
-for name, elem in pairs(wb_usr.messages) do
- lngIndex = name
- lngNext = elem.next
-
- if (lngCount > 1) then
- lngSuffix = "_"..lngIndex
- else
- lngSuffix = ""
- end
-
- writeIndexFile()
- writeTitleFile()
- writeBarFile()
- writeTreeFile()
- writeSearchFile()
- writeSearchIndexFile()
-end
-
-print("Done.")
Modified: branches/eagle_mmc/doc/wb/wb_usr_template.lua
===================================================================
--- branches/eagle_mmc/doc/wb/wb_usr_template.lua 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/wb/wb_usr_template.lua 2009-11-06 02:08:32 UTC (rev 526)
@@ -111,9 +111,13 @@
{
name = { en = "Developers", pt = "Desenvolvedores" },
link = "downloads.html#svndev"
- },
+ },
},
},
+ {
+ name = { en = "eLua Logos", pt = "Logotipos eLua" },
+ link = "downloads.html#elualogos",
+ },
{
name = { en = "Old Versions", pt = "Versões Anteriores" },
link = "dl_old.html",
Deleted: branches/eagle_mmc/doc/wb_img/barlineleft.png
===================================================================
(Binary files differ)
Deleted: branches/eagle_mmc/doc/wb_img/barlineright.png
===================================================================
(Binary files differ)
Deleted: branches/eagle_mmc/doc/wb_img/blank.png
===================================================================
(Binary files differ)
Deleted: branches/eagle_mmc/doc/wb_img/eLuaLogo.png
===================================================================
--- branches/eagle_mmc/doc/wb_img/eLuaLogo.png 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/wb_img/eLuaLogo.png 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,37 +0,0 @@
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Deleted: branches/eagle_mmc/doc/wb_img/elua_arch.png
===================================================================
--- branches/eagle_mmc/doc/wb_img/elua_arch.png 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/wb_img/elua_arch.png 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,297 +0,0 @@
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-K|g×ÔË c°ªŸ6œ¼ûî»?ýÏúž@±‡â…:!‚Q4k”Ê¿jŠ Ï”óíœù=èöÑøš¦7¶Ïy¨ P
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-}ü½ºÂ •¯Æ{Õ•Æñ~u¥m|P]é k?¬rªÖºÇÇUkícÝñ*×ø¤j{|ZµÎ>ÖV1NT·Ï«Öë㋪õÆñeÕzã8YµÞ6þQµÞ96|uÄ5¾>²Á1|l~(‘8y¨¤ 77— §MÐ_—WŸGÇÖáÄ
-•:œ‰R‡#Qêpâ J NŒPI'OoZˆ„.ÄÂÏœàßѾ}ûÛïîí ŠAŽøŽ/ï[uêÄ(SêÔ‰M£Ô©È”:u"¦N¤ NÐ`¸I“&Ç ™Y§Yпfý÷eOžg„J Nlþ®:g—ÍåUçì
-¼^uÎ.’,uê$sêUˆ—À·$tÉ¡NÖvïÞ
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\ No newline at end of file
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Deleted: branches/eagle_mmc/doc/wb_img/stat_not_applicable.png
===================================================================
--- branches/eagle_mmc/doc/wb_img/stat_not_applicable.png 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/wb_img/stat_not_applicable.png 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,4 +0,0 @@
-‰PNG
-
-
-Ÿ÷ZÉ]϶·¦¬
\ No newline at end of file
Deleted: branches/eagle_mmc/doc/wb_img/stat_not_implemented.png
===================================================================
--- branches/eagle_mmc/doc/wb_img/stat_not_implemented.png 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/wb_img/stat_not_implemented.png 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,6 +0,0 @@
-‰PNG
-
-
-@„Ñ€íÄ¿ŒKPÐmÈ·!ß‚Þ#˜w(_a±Ž¹3Ò|% â
-? ^‡âTë Kz³ô&x Ñ|žm÷ȘŸ¾ƒÊª;UªX³nšBÉ! 7J!N€Ž…Y»àšY8l}ó-‘ñ $ÂýA7Ú®ÕV(Û>üÚ„§.À3`Zå¢Ü Ûÿ‡PØ5T®Êr¯Û óï°H×áÄÁpø"G=+Òj† µ#ê‡×75òc°pQ6úSïæ«ol°Þ(SNZˆ; VU˜¨eNOB~98Äý´Mn d$ûé'º‚¹} îOmeéÊ%^Y¿J¹’` Dœ ·8{2ÀË™xÕ‹?0Qpä3_p¬u¼¿îo÷%ÿå`jwæs‹Ò
-$‰eð z¿Ì싇ÇÃZ)0Y•ŠFÉA§;~¯êû;.—gŒºæ@ŠÖ=qqüpØ ,.™ OÑ)_£$uIäeÄi-»ß7Û»·òá~8ãÃõ%”A½p@ž°ì.ɹ#ƒê
\ No newline at end of file
Deleted: branches/eagle_mmc/doc/wb_img/stat_not_tested.png
===================================================================
--- branches/eagle_mmc/doc/wb_img/stat_not_tested.png 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/wb_img/stat_not_tested.png 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,16 +0,0 @@
-‰PNG
-
-
-OiCCPPhotoshop ICC profile
-Øä!¢Žƒ£ˆŠÊûá{£kÖ¼÷æÍþµ×>ç¬ó³ÏÀ –H3Q5€ ©B àƒÇÄÆáä.@
-$p
-d€ r`)¬‚B(†Í° *`/Ô@ 4ÀQh†“p.ÂU¸=púažÁ(¼ AÈa!ÚˆbŠX#Ž™…ø!ÁH‹$ ɈQ"K‘5H1RŠT UH ò=r9‡\Fº‘;È
-b at q¤øSâ(RÊjJåå4åe˜2AU£šRݨ¡T5ZB¡¶R¯Q‡¨4uš9̓IK¥¢•Óhh÷i¯ètºÝ• N—ÐWÒËéGè—èôw
†ƒÇˆg(›gw¯˜L¦Ó‹ÇT071ë˜ç™™oUX*¶*|‘Ê
-•J•&•*/T©ª¦ªÞª UóUËT©^S}®FU3Sã© Ô–«UªPëSSg©;¨‡ªg¨oT?¤~Yý‰YÃLÃOC¤Q ±_ã¼Æ c³x,!k
«†u5Ä&±ÍÙ|v*»˜ý »‹=ª©¡9C3J3W³Ró”f?ã˜qøœtN ç(§—ó~ŠÞï)â)¦4L¹1e\kª–—–X«H«Q«Gë½6®í§¦½E»YûAÇJ'\'GgÎçSÙSݧ
-§M=:õ®.ªk¥¡»Dw¿n§î˜ž¾^€žLo§Þy½çú }/ýTýmú§õG X³ $Û Î<Å5qo< /ÇÛñQC]Ã@C¥a•a—á„‘¹Ñ<£ÕFFŒiÆ\ã$ãmÆmÆ£&&!&KMêMîšRM¹¦)¦;L;LÇÍÌÍ¢ÍÖ™5›=1×2ç›ç›×›ß·`ZxZ,¶¨¶¸eI²äZ¦Yn…Z9Y¥XUZ]³F%Ö»»§§¹N“N«žÖgðñ¶É¶©·°åØÛ®¶m¶}agbg·Å®Ã“}º}ý=
‡Ù« Z ~s´r:V:ޚΜî?}Åô–é/gXÏÏØ3ã¶Ë)ÄiS›ÓGgg¹sƒóˆ‹‰K‚Ë.—>.›ÆÝȽäJtõq]ázÒõ›³›Âí¨Û¯î6îiî‡ÜŸÌ4Ÿ)žY3sÐÃÈCàQåÑ? Ÿ•0k߬~OCOgµç#/c/‘W×°·¥wª÷aï>ö>rŸã>ã<7Þ2ÞY_Ì7À·È·ËOÃož_…ßC#ÿdÿzÿÑ
-y Âg"/Ñ6шØC\* NòH*Mz’쑼5y$Å3¥,幄'©¼L
LÝ›:žšv m2=:½1ƒ’‘qBª!M“¶gêgæfvˬe…²þÅn‹·/ •Ék³¬Y-
-¶B¦èTZ(×*²geWf¿Í‰Ê9–«ž+Íí̳ÊÛ7œïŸÿíÂá’¶¥†KW- X潬j9²<qyÛ
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-å…}ëÜ×í]OX/Yßµaú†>‰Š®Û—Ø(Üxå‡oÊ¿™Ü”´©«Ä¹dÏfÒféæÞ-ž[–ª—æ—n
ÙÚ´
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6
UœÆâ#pDyäé÷ ß÷
:ÚvŒ{¬áÓ v g /jBšòšF›Sšû[b[ºOÌ>ÑÖêÞzüGÛ œ4<YyJóTÉiÚé‚Ó“gòÏŒ•}~.ùÜ`Û¢¶{çcÎßjoïºtáÒEÿ‹ç;¼;Î\ò¸tò²ÛåW¸Wš¯:_mêtê<þ“ÓOÇ»œ»š®¹\k¹îz½µ{f÷éž7ÎÝô½yñÿÖÕž9=ݽózo÷Å÷õßÝ~r'ýÎË»Ùw'î¼O¼_ô@íAÙC݇Õ?[þÜØïÜjÀw óÑÜG÷…ƒÏþ‘õC™Ë†
†ëž8>99â?rýéü§CÏdÏ&žþ¢þË®/~øÕë×Îјѡ—ò—“¿m|¥ýêÀë¯ÛÆÂÆ ¾Éx31^ôVûíÁwÜw ï£ßOä| (ÿhù±õSЧû“““ÿ˜óüc3-Û
-B@…[:J$”!‹"²+?—ipÒ7Ie)O
-B!M‹À‚ïÀµjLÑIjg—&šÂ/$@°qlB º=Wç˜ÜŽ®
\ No newline at end of file
Deleted: branches/eagle_mmc/doc/wb_img/stat_ok.png
===================================================================
--- branches/eagle_mmc/doc/wb_img/stat_ok.png 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/doc/wb_img/stat_ok.png 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,4 +0,0 @@
-‰PNG
-
-
-?ï‰,Q—Oû¼åѪs•gÍ/ã=po Lô;A.K±ÆïÌÁ
\ No newline at end of file
Deleted: branches/eagle_mmc/doc/wb_img/sync.png
===================================================================
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Modified: branches/eagle_mmc/inc/luarpc_rpc.h
===================================================================
--- branches/eagle_mmc/inc/luarpc_rpc.h 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/inc/luarpc_rpc.h 2009-11-06 02:08:32 UTC (rev 526)
@@ -52,7 +52,6 @@
#define DOGCC(x) /* */
#endif
-
/* assertions */
#ifndef NDEBUG
@@ -76,14 +75,13 @@
*/
enum {
- ERR_EOF = MAXINT - 100, /* reached end of file on transport */
- ERR_CLOSED = MAXINT - 101, /* attempted operation on closed transport */
- ERR_PROTOCOL = MAXINT - 102, /* some error in the received protocol */
- ERR_NODATA = MAXINT - 103,
- ERR_BADFNAME = MAXINT - 104,
- ERR_DATALINK = MAXINT - 105,
- ERR_COMMAND = MAXINT - 106,
- ERR_HEADER = MAXINT - 107
+ ERR_EOF = MAXINT - 100, /* reached end of file on transport */
+ ERR_CLOSED = MAXINT - 101, /* attempted operation on closed transport */
+ ERR_PROTOCOL = MAXINT - 102, /* some error in the received protocol */
+ ERR_NODATA = MAXINT - 103,
+ ERR_COMMAND = MAXINT - 106,
+ ERR_HEADER = MAXINT - 107,
+ ERR_LONGFNAME = MAXINT - 108
};
enum exception_type { done, nonfatal, fatal };
@@ -147,10 +145,6 @@
#define INVALID_TRANSPORT (-1)
-#define HEAD_BYTE (0x7e)
-
-#define TAIL_BYTE (0x7f)
-
#define TRANSPORT_VERIFY_OPEN \
if (tpt->fd == INVALID_TRANSPORT) \
{ \
@@ -191,4 +185,4 @@
int transport_is_open (Transport *tpt);
/* Shut down connection */
-void transport_close (Transport *tpt);
\ No newline at end of file
+void transport_close (Transport *tpt);
Modified: branches/eagle_mmc/inc/romfs.h
===================================================================
--- branches/eagle_mmc/inc/romfs.h 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/inc/romfs.h 2009-11-06 02:08:32 UTC (rev 526)
@@ -6,7 +6,7 @@
#include "type.h"
#include "devman.h"
// Maximum length of a filename in the filesystem
-#define MAX_FNAME_LENGTH 14
+#define MAX_FNAME_LENGTH 30
/*******************************************************************************
The Read-Only "filesystem" resides in a contiguous zone of memory, with the
@@ -26,19 +26,20 @@
// This is the function used to read a byte at the given address from the file
// system
-typedef u8 ( *p_read_fs_byte )( u16 );
+typedef u8 ( *p_read_fs_byte )( u32 );
// A small "FILE" structure
typedef struct
{
- u16 baseaddr;
- u16 offset;
+ u32 baseaddr;
+ u32 offset;
u16 size;
p_read_fs_byte p_read_func;
} FS;
// FS functions
DM_DEVICE* romfs_init();
-u16 romfs_get_dir_entry(u16 offset, char *fname, int *fsize);
+u32 romfs_get_dir_entry( u32 offset, char *fname, u16 *fsize );
#endif
+
Modified: branches/eagle_mmc/inc/version.h
===================================================================
--- branches/eagle_mmc/inc/version.h 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/inc/version.h 2009-11-06 02:08:32 UTC (rev 526)
@@ -3,7 +3,7 @@
#ifndef __VERSION_H__
#define __VERSION_H__
-#define ELUA_VERSION 0.5
-#define ELUA_STR_VERSION "0.5"
+#define ELUA_VERSION 0.6
+#define ELUA_STR_VERSION "0.6"
#endif
Modified: branches/eagle_mmc/mkfs.py
===================================================================
--- branches/eagle_mmc/mkfs.py 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/mkfs.py 2009-11-06 02:08:32 UTC (rev 526)
@@ -7,6 +7,8 @@
_numdata = 0
_bytecnt = 0
+maxlen = 30
+
# Line output function
def _add_data( data, outfile, moredata = True ):
global _crtline, _numdata, _bytecnt
@@ -46,8 +48,8 @@
# Process all files
for fname in flist:
- if len( fname ) > 14:
- print "Skipping %s (name longer than 14 chars)" % realname
+ if len( fname ) > maxlen:
+ print "Skipping %s (name longer than %d chars)" % ( fname, maxlen )
continue
# Get actual file name
Added: branches/eagle_mmc/romfs/EK-LM3S6965.lua
===================================================================
--- branches/eagle_mmc/romfs/EK-LM3S6965.lua 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/romfs/EK-LM3S6965.lua 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,34 @@
+-- This auxiliar platform dependent module defines some hardware devices
+-- available in the specific development kit.
+-- It will be automatically require()d when eLua detects it is running on the
+-- respective platform, exposing auxiliar constants and functions to facilitate
+-- and keep portable the access to the underlying hardware.
+-- The code configures the MCU to interface with the platform devices and
+-- exposes the following objects, constants and fuctions:
+-- Onboard Buttons:
+-- BTN_UP, BTN_DOWN, BTN_LEFT, BTN_RIGHT, BTN_SELECT
+-- Onboard LED:
+-- Auxiliar Function:
+-- btn_pressed( button )
+-- returns true if the arg button is pressed, false otherwise
+
+local pio = pio
+
+module(...)
+
+BTN_UP = pio.PE_0
+BTN_DOWN = pio.PE_1
+BTN_LEFT = pio.PE_2
+BTN_RIGHT = pio.PE_3
+BTN_SELECT = pio.PF_1
+
+btn_pressed = function( button )
+ return pio.pin.getval( button ) == 0
+end
+
+LED_1 = pio.PF_0
+
+pio.pin.setdir( pio.INPUT, BTN_UP, BTN_DOWN, BTN_LEFT, BTN_RIGHT, BTN_SELECT )
+pio.pin.setpull( pio.PULLUP, BTN_UP, BTN_DOWN, BTN_LEFT, BTN_RIGHT, BTN_SELECT )
+pio.pin.setdir( pio.OUTPUT, LED_1 )
+
Added: branches/eagle_mmc/romfs/EK-LM3S8962.lua
===================================================================
--- branches/eagle_mmc/romfs/EK-LM3S8962.lua 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/romfs/EK-LM3S8962.lua 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,34 @@
+-- This auxiliar platform dependent module defines some hardware devices
+-- available in the specific development kit.
+-- It will be automatically require()d when eLua detects it is running on the
+-- respective platform, exposing auxiliar constants and functions to facilitate
+-- and keep portable the access to the underlying hardware.
+-- The code configures the MCU to interface with the platform devices and
+-- exposes the following objects, constants and fuctions:
+-- Onboard Buttons:
+-- BTN_UP, BTN_DOWN, BTN_LEFT, BTN_RIGHT, BTN_SELECT
+-- Onboard LED:
+-- Auxiliar Function:
+-- btn_pressed( button )
+-- returns true if the arg button is pressed, false otherwise
+
+local pio = pio
+
+module(...)
+
+BTN_UP = pio.PE_0
+BTN_DOWN = pio.PE_1
+BTN_LEFT = pio.PE_2
+BTN_RIGHT = pio.PE_3
+BTN_SELECT = pio.PF_1
+
+btn_pressed = function( button )
+ return pio.pin.getval( button ) == 0
+end
+
+LED_1 = pio.PF_0
+
+pio.pin.setdir( pio.INPUT, BTN_UP, BTN_DOWN, BTN_LEFT, BTN_RIGHT, BTN_SELECT )
+pio.pin.setpull( pio.PULLUP, BTN_UP, BTN_DOWN, BTN_LEFT, BTN_RIGHT, BTN_SELECT )
+pio.pin.setdir( pio.OUTPUT, LED_1 )
+
Deleted: branches/eagle_mmc/romfs/LM3S.lua
===================================================================
--- branches/eagle_mmc/romfs/LM3S.lua 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/romfs/LM3S.lua 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,20 +0,0 @@
-local pio = pio
-
-module(...)
-
-BTN_UP = pio.PE_0
-BTN_DOWN = pio.PE_1
-BTN_LEFT = pio.PE_2
-BTN_RIGHT = pio.PE_3
-BTN_SELECT = pio.PF_1
-
-btnpressed = function( button )
- return pio.pin.getval( button ) == 0
-end
-
-LED_1 = pio.PF_0
-
-pio.pin.setdir( pio.INPUT, pio.PE_0, pio.PE_1, pio.PE_2, pio.PE_3, pio.PF_1 )
-pio.pin.setpull( pio.PULLUP, pio.PE_0, pio.PE_1, pio.PE_2, pio.PE_3, pio.PF_1 )
-pio.pin.setdir( pio.OUTPUT, pio.PF_0 )
-
Modified: branches/eagle_mmc/romfs/adcscope.lua
===================================================================
--- branches/eagle_mmc/romfs/adcscope.lua 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/romfs/adcscope.lua 2009-11-06 02:08:32 UTC (rev 526)
@@ -41,7 +41,7 @@
end
end
etime = tread(0) -- get cycle end time
- dtime = tmr.diff(0,etime,stime)/numiter -- compute average acquisition time per cycle
+ dtime = tmr.gettimediff(0,etime,stime)/numiter -- compute average acquisition time per cycle
-- draw last acquired samples on the console
term.moveto(1,4)
Modified: branches/eagle_mmc/romfs/led.lua
===================================================================
--- branches/eagle_mmc/romfs/led.lua 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/romfs/led.lua 2009-11-06 02:08:32 UTC (rev 526)
@@ -17,20 +17,32 @@
elseif pd.board() == "ATEVK1100" then
ledpin = pio.PB_27
invert = true
+elseif pd.board() == "STR-E912" then
+ ledpin = pio.P6_4
+elseif pd.board() == "ELUA-PUC" then
+ ledpin = pio.P1_20
else
print( "\nError: Unknown board " .. pd.board() .. " !" )
return
end
function cycle()
- if not invert then pio.pin.sethigh( ledpin ) else pio.pin.setlow( ledpin ) end
+ if not invert then
+ pio.pin.sethigh( ledpin )
+ else
+ pio.pin.setlow( ledpin )
+ end
tmr.delay( 0, 500000 )
- if not invert then pio.pin.setlow( ledpin ) else pio.pin.sethigh( ledpin ) end
+ if not invert then
+ pio.pin.setlow( ledpin )
+ else
+ pio.pin.sethigh( ledpin )
+ end
tmr.delay( 0, 500000 )
end
pio.pin.setdir( pio.OUTPUT, ledpin )
-print( "Hello from eLua on " .. pd.cpu() )
+print( "Hello from eLua on " .. pd.board() )
print "Watch your LED blinking :)"
print "Press any key to end this demo.\n"
Modified: branches/eagle_mmc/romfs/lhttpd.lua
===================================================================
--- branches/eagle_mmc/romfs/lhttpd.lua 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/romfs/lhttpd.lua 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,5 +1,5 @@
-- Check platform
-if pd.board() ~= 'EK-LM3S8962' and pd.board() ~= 'EK-LM3S6965' and pd.board() ~= 'EAGLE-100' then
+if pd.board() ~= 'EK-LM3S8962' and pd.board() ~= 'EK-LM3S6965' and pd.board() ~= 'EAGLE-100' and pd.board() ~= 'EK-LM3S9B92' then
print( pd.board() .. " not supported by this example" )
return
end
Added: branches/eagle_mmc/romfs/logo.bin
===================================================================
--- branches/eagle_mmc/romfs/logo.bin 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/romfs/logo.bin 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1 @@
+
\ No newline at end of file
Added: branches/eagle_mmc/romfs/logo.lua
===================================================================
--- branches/eagle_mmc/romfs/logo.lua 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/romfs/logo.lua 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,81 @@
+local disp = lm3s.disp
+
+disp.init( 1000000 )
+disp.clear()
+
+local math = math
+local floor = math.floor
+local pi = math.pi
+
+local img = io.open( "/rom/logo.bin", "rb")
+if img == nil then
+ print "Unable to load image"
+ return 0
+end
+local imgdata = img:read( "*a" )
+img:close()
+
+local maxx , maxy = 64, 64
+local xf, yf = maxx / 2 - 1, maxy / 2 - 1
+local ct = yf * maxx + xf + 1
+
+local function rotate( imgdata, angle )
+ local c = math.cos( angle )
+ local s = math.sin( angle )
+ local newdata = bitarray.new( maxx * maxy, 4 )
+ local xc, ys = -xf * c, -yf * s
+ local xs, yc = -xf * s, -yf * c
+ local p1, p2 = xc - ys, xs + yc
+ local p3, p4 = -xc - ys, -xs + yc
+ local xx1, yy1, xx2, yy2
+ local widx1, widx2 = 1, 2*xf + 1
+ local widx3, widx4 = 2 * yf * maxx + 1, 2 * yf * maxx + 2 * xf + 1
+ local w1, w2, w3, w4
+ for y = -yf, 0 do
+ xx1, yy1, xx2, yy2 = p1, p2, p3, p4
+ w1, w2, w3, w4 = widx1, widx2, widx3, widx4
+ for x = -xf, 0 do
+ if ( xx1 >= -xf ) and ( xx1 <= xf ) and ( yy1 >= -yf ) and ( yy1 <= yf ) then
+ newdata[ w1 ] = imgdata[ floor( yy1 ) * maxx + floor( xx1 ) + ct ]
+ end
+ if ( xx2 >= -xf ) and ( xx2 <= xf ) and ( yy2 >= -yf ) and ( yy2 <= yf ) then
+ newdata[ w2 ] = imgdata[ floor( yy2 ) * maxx + floor( xx2 ) + ct ]
+ end
+ if ( -xx2 >= -xf ) and ( -xx2 <= xf ) and ( -yy2 >= -yf ) and ( -yy2 <= yf ) then
+ newdata[ w3 ] = imgdata[ floor( -yy2 ) * maxx + floor( -xx2 ) + ct ]
+ end
+ if ( -xx1 >= -xf ) and ( -xx1 <= xf ) and ( -yy1 >= -yf ) and ( -yy1 <= yf ) then
+ newdata[ w4 ] = imgdata[ floor( -yy1 ) * maxx + floor( -xx1 ) + ct ]
+ end
+ xx1 = xx1 + c ; yy1 = yy1 + s ; xx2 = xx2 - c ; yy2 = yy2 - s
+ w1 = w1 + 1 ; w2 = w2 - 1 ; w3 = w3 + 1 ; w4 = w4 - 1
+ end
+ p1 = p1 - s ; p2 = p2 + c ; p3 = p3 - s ; p4 = p4 + c
+ widx1 = widx1 + maxx ; widx2 = widx2 + maxx ; widx3 = widx3 - maxx ; widx4 = widx4 - maxx
+ end
+ return bitarray.tostring( newdata, "raw" )
+end
+
+local origx = ( 128 - maxx ) / 2
+local origy = ( 96 - maxy ) / 2
+disp.draw( imgdata, origx, origy, maxx, maxy )
+local imgd = bitarray.new( imgdata, 4 )
+imgdata = nil
+collectgarbage()
+
+local delta = pi / 8
+local angles = { 0, delta, pi / 4, 3 * delta, pi / 2, 5 * delta, 3 * pi / 4, 7 * delta, pi,
+ 9 * delta, 5 * pi / 4, 11 * delta, 3 * pi / 2, 13 * delta, 7 * pi / 4, 15 * delta }
+local index = 2
+
+while uart.getchar( 0, uart.NO_TIMEOUT ) == "" do
+ local newimg = rotate( imgd, angles[ index ] )
+ disp.draw( newimg, origx, origy, maxx, maxy )
+ newimg = nil
+ collectgarbage()
+ index = index + 1
+ index = index > #angles and 1 or index
+end
+
+disp.clear()
+
Modified: branches/eagle_mmc/romfs/morse.lua
===================================================================
--- branches/eagle_mmc/romfs/morse.lua 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/romfs/morse.lua 2009-11-06 02:08:32 UTC (rev 526)
@@ -99,7 +99,7 @@
while true do
term.clrscr()
term.moveto(1, 1)
- print("Welcome to eLua Morse Playing on " .. pd.cpu())
+ print("Welcome to eLua Morse Playing on " .. pd.board())
io.write("Enter phrase (empty phrase to exit): ")
local msg, enabled = io.read(), true
if #msg == 0 then break end
Modified: branches/eagle_mmc/romfs/piano.lua
===================================================================
--- branches/eagle_mmc/romfs/piano.lua 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/romfs/piano.lua 2009-11-06 02:08:32 UTC (rev 526)
@@ -12,6 +12,10 @@
elseif pd.board() == "SAM7-EX256" then
pwmid, tmrid = 0, 1
tmr.setclock( 1, 1000000 )
+elseif pd.board() == "STR-E912" then
+ local g = str9.pio
+ g.setpin( pio.P4_6, g.OUTPUT, g.OUTPUT_PUSHPULL, false, g.ALT_OUTPUT2 )
+ pwmid, tmrid = 3, 1
else
print( pd.board() .. " not supported with this example" )
return
Modified: branches/eagle_mmc/romfs/pong.lua
===================================================================
--- branches/eagle_mmc/romfs/pong.lua 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/romfs/pong.lua 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,124 +1,329 @@
-require("LM3S")
+-------------------------------------------------------------------------------
+--
+-- eLua Pong Game
+--
+-- LED Lab @ PUC-Rio - 2009
+-- Dado Sutter
+-- Ives Negreiros
+-- Ricardo Rosa
+-- Pedro Bittencourt
+-- Teo Benjamin
+--
-function drawPaddle( y, color )
- disp.print("|", 0, y, color)
- disp.print("|", 0, y+4, color)
- disp.print("|", 0, y+8, color)
+-- Initial Version by Dado Sutter, Fev 2009
+-- This had only the ball bouncing on walls, paddle and paddle movement
+--
+-- Greatly enhanced by Teo Benjamin in Aug/Sep 2009, adding:
+-- Score, resizeable paddles, levels/speeds, items
+--
+--
+-------------------------------------------------------------------------------
+
+local canvas = {}
+-- canvas.x -- Horizontal display size
+-- canvas.y -- Vertical display size
+
+local paddle = {}
+-- paddle.size -- Actual Paddle size = ( 6 * ( paddle.size + 1 ) ) + 2
+-- paddle.max_size -- Max paddle.size value -> Constant
+-- paddle.min_size -- Min paddle.size value -> Constant
+-- paddle.y -- Paddle's Y position ( X position not needed, always 0 )
+
+local ball = {}
+-- ball.x -- Ball's X position
+-- ball.y -- Ball's Y position -> starts at a random position
+-- ball.dx -- Ball's X movement ( 1 = moving right; -1 = moving left )
+-- ball.dy -- Ball's Y movement ( 1 = moving down; -1 = moving up )
+-- ball.char -- The char that is printed for the ball -> Constant
+
+local item = {}
+-- item.x -- Item's X position
+-- item.y -- Item's Y position ( fix for each item )
+-- item.char -- This is the char that represents the item ( if false, there is no item )
+-- item.all_chars -- A table that contains all the possibles item chars. Initialized by upload_items() function
+
+-- Define all constants
+local tmr_id = 1
+paddle.max_size = 4
+paddle.min_size = 0
+ball.char = "*"
+local delay_incr = 2000
+
+-- Define all "global" variables as program local ones.
+-- The values are initialized at the main loop.
+
+local score -- Player's score
+local dscore -- How many points for each paddle hit
+local delay_time -- This value is used for the main delay, to make the game speed faster or slower
+local paddle_hits -- Counts the number of hits on paddle
+local highscore -- Current Highscore
+
+item.all_chars = {}
+local pressed = {} -- pressed[ button ] is true if the corresponding button was pressed, or nil if not
+
+local kit = require( pd.board() ) -- This variable is used as a pin assignments for the specific board
+
+local itemFunction = {
+["L"] = function ()
+ draw_paddle( paddle.y, 0, 0 )
+ if paddle.size < paddle.max_size then
+ paddle.size = paddle.size + 1
+ end
+ draw_paddle( paddle.y, 11, 0 )
+ end,
+
+["S"] = function ()
+ draw_paddle( paddle.y, 0, 0 )
+ if paddle.size > paddle.min_size then
+ paddle.size = paddle.size - 1
+ end
+ draw_paddle( paddle.y, 11, 0 )
+ end,
+
+["?"] = function ()
+ item.char = item.all_chars[ math.random( #item.all_chars ) ]
+ use_item()
+ end,
+
+["*"] = function ()
+ end,
+
+["P"] = function ()
+ score = score + dscore
+ end,
+
+["D"] = function ()
+ score = score * 2
+ end,
+
+["Z"] = function ()
+ lm3s.disp.print( tostring( score ), 111, 89, 0 )
+ score = 0
+ end,
+
+["T"] = function ()
+ lm3s.disp.print( ball.char, ball.x, ball.y, 0 )
+ ball.y = math.random( 82 )
+ lm3s.disp.print( ball.char, ball.x, ball.y, 15 )
+ end,
+
+["F"] = function()
+ if delay_time >= 1000 then
+ delay_time = delay_time - 1000
+ end
+ end,
+}
+
+-- Updates Y paddle position and draw it using the draw_paddle( ... ) function
+function update_paddle_pos()
+ if kit.btn_pressed( kit.BTN_UP ) then
+ if ( paddle.y > 0 ) then
+ paddle.y = paddle.y - 1
+ draw_paddle( paddle.y, 11, -1 )
+ else
+ tmr.delay( 1, 1700 )
+ end
+ elseif kit.btn_pressed( kit.BTN_DOWN ) then
+ if ( paddle.y + ( paddle.size*6 ) + 1 < 90 ) then
+ paddle.y = paddle.y + 1
+ draw_paddle( paddle.y, 11, 1 )
+ else
+ tmr.delay( 1, 1600 )
+ end
+ else
+ draw_paddle( paddle.y, 11, 0 )
+ tmr.delay( 1, 300 ) -- Maintain function processing time aprox the same
+ end
end
-function updateBallPos()
- if( bx >= 121 or bx <= 4) then
- dx = -dx;
+-- Draw the paddle in the display. This function is used by update_paddle_pos() function
+function draw_paddle( y, color, movement )
+ if ( movement == 0 ) then
+ for i = 0, paddle.size, 1 do
+ lm3s.disp.print( "|", 0, y + ( i * 6 ), color )
+ end
+ elseif ( movement > 0 ) then -- Paddle moving Down
+ if y < 8 then
+ lm3s.disp.print( "|", 0, 0, 0 )
+ else
+ lm3s.disp.print( "|", 0, y - 8 , 0 )
+ end
+ for i = 0, paddle.size, 1 do
+ lm3s.disp.print( "|", 0, y + ( i * 6 ), color )
+ end
+ elseif ( movement < 0 ) then -- Paddle moving Up
+ lm3s.disp.print( "|", 0, y + ( ( paddle.size + 1 ) * 6 ) + 2 , 0 )
+ for i = 0, paddle.size, 1 do
+ lm3s.disp.print( "|", 0, y + ( i * 6 ), color )
+ end
end
+end
- if(( by >= 89 ) or ( by <= 0 )) then
- dy = -dy;
+-- Updates the ( X, Y ) ball position and prints the corresponding char
+function update_ball_pos()
+ if( ( ball.x + 5 >= canvas.x ) or ( ball.x <= 4 ) ) then
+ ball.dx = -ball.dx;
+ if ball.dx == -1 and item.char == false then
+ createItem()
+ end
end
- disp.print( ball, bx, by, 0 )
- bx, by = ( bx + dx ), ( by + dy );
- disp.print( ball, bx, by, 15 )
+ if( ( ball.y >= 90 - ball.dy ) or ( ball.y <= 1 - ball.dy ) ) then
+ ball.dy = -ball.dy;
+ end
+ lm3s.disp.print( ball.char, ball.x, ball.y, 0 )
+ ball.x, ball.y = ( ball.x + ball.dx ), ( ball.y + ball.dy );
+ lm3s.disp.print( ball.char, ball.x, ball.y, 15 )
end
-function updatePaddlePos()
- if LM3S.btnpressed( LM3S.BTN_UP ) then
- if ( py > 0 ) then
- drawPaddle( py, 0 )
- py = py - 1
- drawPaddle( py, 11 )
+-- Draw the top wall and erase the last one. Used to move it
+function draw_wall( x )
+ for i = 0, canvas.y, 7 do -- Erase the wall
+ lm3s.disp.print( "|", canvas.x + 1, i, 0 )
+ end
+ canvas.x = x
+ for i = 0, canvas.y, 7 do -- Draw a new wall
+ lm3s.disp.print( "|", canvas.x + 1, i, 6 )
+ end
+end
+
+-- Item Functions
+function createItem()
+ item.char = item.all_chars[ math.random( #item.all_chars ) ]
+ item.x = canvas.x - 10
+ item.y = ball.y
+end
+
+-- Upload the itens from table itemFunction into the table item.all_chars
+-- Must be used to initialize the items
+function upload_items()
+ for k,v in pairs( itemFunction ) do
+ table.insert( item.all_chars, k )
+ end
+end
+
+-- Updates the item X position
+function update_item_pos()
+ if item.char then
+ if ( item.x <= 4 ) then
+ if ( ( item.y + 8 < paddle.y ) or ( item.y > paddle.y + ( paddle.size * 6 ) + 8 ) ) == false then
+ use_item()
+ end
+ lm3s.disp.print( item.char, item.x, item.y, 0 )
+ item.char = false
+ return
end
- elseif LM3S.btnpressed( LM3S.BTN_DOWN ) then
- if ( py < 80 ) then
- drawPaddle( py, 0 )
- py = py + 1
- drawPaddle( py, 11 )
+ lm3s.disp.print( item.char, item.x, item.y, 0 )
+ item.x = item.x - 2
+ lm3s.disp.print( item.char, item.x, item.y, 10 )
+ end
+end
+
+-- Uses the item's function
+function use_item()
+ itemFunction[ item.char ]()
+end
+
+-- Checks if a button was clicked ( pressed and released )
+-- Returns true or false
+function button_clicked( button )
+ if kit.btn_pressed( button ) then
+ pressed[ button ] = true
+ else
+ if pressed[ button ] then
+ pressed[ button ] = nil
+ return true
end
- else
- tmr.delay( 0, 400 ) -- Maintain function processing time aprox the same
+ pressed[ button ] = nil
end
+ return false
end
------------ MAIN ------------
-disp.init(1000000)
+upload_items()
+lm3s.disp.init( 1000000 )
-term.clrscr()
-term.moveto( 5, 1 )
-print( "Welcome to eLua Pong on a RIT display" )
-disp.print( "eLua Pong", 30, 40, 11 )
-tmr.delay ( 0, 2000000 )
+tmr.start( tmr_id )
+--menu()
+math.randomseed( tmr.read( tmr_id ) ) -- If you use the menu function, the time will be used as a seed to the random function
+--tmr.stop( tmr_id )
-highscore = 0
+collectgarbage( "collect" )
-while (true) do
- play = false
-
- bx, by = 5, 48
- dx, dy = 1, 1
- py = 48
-
+-- GAME START
+repeat
+ canvas.x = 124
+ canvas.y = 97
+ ball.x = 5
+ ball.y = math.random( ( canvas.y - 8 ) / 2 ) + ( canvas.y / 4 )
+ ball.dx = 1
+ ball.dy = 1
+ paddle.y = ball.y - 4
+ item.x = 0
+ item.y = 0
score = 0
dscore = 1
- ball = "*"
- time = 10000
-
- change = 0
-
- disp.clear()
- drawPaddle( py, 11 )
+ item.char = false
+ paddle.size = 2
+ delay_time = 10000
+ paddle_hits = 0
+ lm3s.disp.clear()
+
+ draw_wall( canvas.x )
+ draw_paddle( paddle.y, 11, 0 )
+
while ( true ) do
for i = 0, 1 do
- updatePaddlePos()
- tmr.delay ( 0, time )
+ update_paddle_pos()
end
- updateBallPos()
- if ( bx == 4 ) then
- if (( by+8 < py ) or ( by > py+16 )) then
+ tmr.delay ( 0, delay_time )
+ update_ball_pos()
+ update_item_pos()
+ if ( ball.x <= 4 ) then
+ if ( ( ball.y + 8 < paddle.y ) or ( ball.y > paddle.y + ( paddle.size * 6 ) + 8 ) ) then -- If this is true, you lose
break
- else
+ else -- Else, you score
score = score + dscore
+ paddle_hits = paddle_hits + 1
end
end
-
- if change == 0 then
- if LM3S.btnpressed( LM3S.BTN_RIGHT ) and time > 0 then
- change = 1
- elseif LM3S.btnpressed( LM3S.BTN_LEFT ) and dscore > 1 then
- change = -1
- end
+
+ if button_clicked( kit.BTN_RIGHT ) and delay_time > 0 then -- If the right button is clicked, increase the level
+ delay_time = delay_time - delay_incr
+ dscore = dscore + 1
end
-
- if ( LM3S.btnpressed( LM3S.BTN_RIGHT ) ) == false and ( LM3S.btnpressed( LM3S.BTN_LEFT ) ) == false then
- if change == 1 then
- time = time - 2000
- dscore = dscore + 1
- elseif change == -1 then
- time = time + 2000
- dscore = dscore - 1
- end
- change = 0
+ if button_clicked( kit.BTN_LEFT ) and dscore > 0 then -- If the left button is clicked, decrease the level
+ delay_time = delay_time + delay_incr
+ dscore = dscore - 1
end
-
- disp.print( tostring( dscore ), 118, 0, 6 )
-
+
+ if ( paddle_hits == 5 ) and canvas.x > 80 then -- After 5 hits in a row, move the wall until canvas.x = 80
+ paddle_hits = 0
+ draw_wall( canvas.x - 5 )
+ end
+ lm3s.disp.print( tostring( dscore ), 118, 0, 6 )
+ lm3s.disp.print( tostring( score ), 111, 89, 6 )
+ collectgarbage( "collect" )
end
-
- if score > highscore then
+-------------------------------------------
+-- Game Over
+-------------------------------------------
+ if score >= ( highscore or 0 ) then
highscore = score
end
-
- disp.clear()
- disp.print( "Game Over :(", 30, 20, 11 )
- disp.print( "Your score was " .. tostring( score ), 15, 40, 11 )
- disp.print( "High score: " .. tostring( highscore ), 15, 50, 11 )
- disp.print( "SELECT to restart", 6, 70, 11 )
- for i=0, 500000 do
- if LM3S.btnpressed( LM3S.BTN_SELECT ) then
- play = true
+ lm3s.disp.clear()
+ lm3s.disp.print( "Game Over :(", 30, 20, 11 )
+ lm3s.disp.print( "Your score was "..tostring( score ), 15, 40, 11 )
+ lm3s.disp.print( "Highscore: "..tostring( highscore ), 15, 50, 11 )
+ lm3s.disp.print( "SELECT to restart", 6, 70, 11 )
+ enough = true
+ for i=1, 100000 do
+ if kit.btn_pressed( kit.BTN_SELECT ) then
+ enough = false
break
end
end
- if play == false then
- disp.off()
- break
- end
-end
+until ( enough )
+
+lm3s.disp.off()
+lm3s.disp.init( 1000000 )
Modified: branches/eagle_mmc/romfs/pwmled.lua
===================================================================
--- branches/eagle_mmc/romfs/pwmled.lua 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/romfs/pwmled.lua 2009-11-06 02:08:32 UTC (rev 526)
@@ -4,6 +4,11 @@
if pd.board() == 'EK-LM3S8962' or pd.board() == 'EK-LM3S6965' or pd.board() == 'ET-STM32' or pd.board() == 'EAGLE-100' then
pwmid, tmrid = 0, 1
pwm.setclock( pwmid, 25000000 )
+elseif pd.board() == 'ELUA-PUC' then
+ pwmid, tmrid = 7, 0
+ local psel = cpu.r32( cpu.IO_PINSEL3 )
+ psel = bit.bor( bit.band( psel, 0xFFFFFCFF ), 0x00000200 )
+ cpu.w32( cpu.IO_PINSEL3, psel )
else
print( pd.board() .. " not supported by this example" )
return
Added: branches/eagle_mmc/romfs/spaceship.lua
===================================================================
--- branches/eagle_mmc/romfs/spaceship.lua 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/romfs/spaceship.lua 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,274 @@
+-------------------------------------------------------------------------------
+--
+-- eLua SpaceShip Game
+--
+-- LED Lab @ PUC-Rio - 2009
+-- Dado Sutter
+-- Ives Negreiros
+-- Ricardo Rosa
+-- Pedro Bittencourt
+-- Teo Benjamin
+--
+--
+-- Initial Version by Téo Benjamin, Aug 2009
+--
+-------------------------------------------------------------------------------
+
+local xcanvas = 124 -- Real screen X size
+local xcanvas = xcanvas - 12 -- Canvas size with wall
+local ycanvas = 96 -- Screen Y size
+local pressed = {} -- This table is used to help the buttonClicked function. If the btn if pressed,
+ -- pressed[ btn ] = true, when it is released, pressed[ btn ] = nil
+local ShipChar = ">" -- This is the char that is printed to represent the SpaceShip
+local shotChar = "-" -- This char is printed to represent the shots
+local enemyChar = "@" -- This char is used to represent the enemies
+local sy = 16 -- Ship's Y position
+local sx = 0 -- Ship's X position
+local bullets = 50 -- Number of bullets left
+local score = 0 -- Player's score
+local numOfEnemies = 5 -- Number of simultaneous enemies
+local won = false -- If the player won the game, this value is true. If not, it's false.
+-- Initialization
+local kit = require( pd.board() )
+
+
+local canvasMap = {} -- canvasMap[ line ][ #shot ]
+-- canvasMap[ i ][ j ]: i represents the y position and j is a numeric index for each shot in that line. The value is the x position.
+-- canvasMap[ i ].e represents the x position of the enemy in that line, if any.
+-- Enemies can only appear in lines 5, 15, 25, 35, ..., 75 and 85
+for i = 1, ycanvas, 1 do
+ canvasMap[ i ] = {}
+end
+for i = 5, 85, 10 do
+ canvasMap[ i ].e = false
+end
+
+function drawWall( x, y )
+ for i = 0, y, 7 do
+ lm3s.disp.print( "|", xcanvas + 1, i, 0 )
+ end
+ xcanvas = x
+ for i = 0, y, 7 do
+ lm3s.disp.print( "|", xcanvas + 1, i, 6 )
+ end
+
+end
+
+function drawShip( x, y, color, movement )
+
+ if ( movement == 0 ) then
+ lm3s.disp.print( ShipChar, x, y, color )
+ elseif ( movement > 0 ) then -- Moving Down
+ if y < 8 then
+ lm3s.disp.print( ShipChar, x, 0, 0 )
+ else
+ lm3s.disp.print( ShipChar, x, y - 8 , 0 )
+ end
+ lm3s.disp.print( ShipChar, x, y, color )
+ elseif ( movement < 0 ) then -- Moving Up
+ lm3s.disp.print( ShipChar, x, y + 8, 0 )
+ lm3s.disp.print( ShipChar, x, y, color )
+ end
+end
+
+
+function updateShipPos()
+ if kit.btn_pressed( kit.BTN_UP ) then
+ if ( sy > 1 ) then
+ sy = sy - 1
+ drawShip( sx, sy, 11, -1 )
+ else
+ tmr.delay( 1, 1700 )
+ end
+ elseif kit.btn_pressed( kit.BTN_DOWN ) then
+ if ( sy + 7 < ycanvas ) then
+ sy = sy + 1
+ drawShip( sx, sy, 11, 1 )
+ else
+ tmr.delay( 1, 1600 )
+ end
+ else
+ drawShip( sx, sy, 11, 0 )
+ tmr.delay( 1, 300 ) -- Maintain function processing time aprox the same
+ end
+end
+
+
+
+function updateShots()
+ for i in ipairs( canvasMap ) do
+ for j in ipairs( canvasMap[ i ] ) do
+ if canvasMap[ i ][ j ] then
+ lm3s.disp.print( shotChar, canvasMap[ i ][ j ], i, 0 )
+ canvasMap[ i ][ j ] = canvasMap[ i ][ j ] + 2
+ lm3s.disp.print( shotChar, canvasMap[ i ][ j ], i, 13 )
+ if canvasMap[ i ][ j ] + 4 >= xcanvas then
+ lm3s.disp.print( shotChar, canvasMap[ i ][ j ], i, 0 )
+ table.remove( canvasMap[ i ], j )
+ break
+ end
+ local en = math.floor( i / 10 ) * 10 + 5
+ if canvasMap[ en ].e then
+ if ( canvasMap[ i ][ j ] <= canvasMap[ en ].e ) and ( canvasMap[ i ][ j ] + 4 >= canvasMap[ en ].e ) then
+ destroyEnemy( i, j, en )
+ createEnemy()
+ end
+ end
+ else
+ tmr.delay( 1, 1200 )
+ end
+ end
+ end
+end
+
+function shot()
+ if bullets > 0 then
+ table.insert( canvasMap[ sy ], sx + 6 )
+ bullets = bullets - 1
+ end
+ sound()
+end
+
+function buttonClicked( button )
+ if kit.btn_pressed( button ) then
+ pressed[ button ] = true
+ else
+ if pressed[ button ] then
+ pressed[ button ] = false
+ return true
+ end
+ pressed[ button ] = false
+ end
+ return false
+end
+
+function printBulletsNum()
+ lm3s.disp.print( string.format( "%2d", bullets ), xcanvas + 4, 2, 6 )
+end
+
+function printScore()
+ lm3s.disp.print( string.format( "%2d", score ), xcanvas + 4, ycanvas - 10, 6 )
+end
+
+function sound()
+ pwm.start( 1 )
+ tmr.delay( 0, 20000 )
+ pwm.stop( 1 )
+end
+
+
+function updateEnemiesPos()
+ for i = 5, 85, 10 do
+ if canvasMap[ i ].e then
+ lm3s.disp.print( enemyChar, canvasMap[ i ].e, i, 0 )
+ canvasMap[ i ].e = canvasMap[ i ].e - 1
+ lm3s.disp.print( enemyChar, canvasMap[ i ].e, i, 11 )
+ if canvasMap[ i ].e <= 0 then
+ lm3s.disp.print( enemyChar, canvasMap[ i ].e, i, 0 )
+ canvasMap[ i ].e = nil
+ createEnemy()
+ end
+ end
+ end
+end
+
+function createEnemy()
+ while true do
+ local en = ( math.random( 0, 8 ) )*10 + 5
+ if not canvasMap[ en ].e then
+ canvasMap[ en ].e = xcanvas - 5
+ break
+ end
+ end
+end
+
+function addEnemy()
+ if numOfEnemies < 9 then
+ numOfEnemies = numOfEnemies + 1
+ createEnemy()
+ end
+end
+function destroyEnemy( i, j, en )
+ lm3s.disp.print( shotChar, canvasMap[ i ][ j ], i, 0 )
+ table.remove( canvasMap[ i ], j )
+ lm3s.disp.print( enemyChar, canvasMap[ en ].e, en, 0 )
+ canvasMap[ en ].e = nil
+ score = score + 1
+end
+
+function destroyAll()
+ for i in ipairs( canvasMap ) do
+ for j in ipairs( canvasMap[ i ] ) do
+ lm3s.disp.print( shotChar, canvasMap[ i ][ j ], i, 0 )
+ table.remove( canvasMap[ i ], j )
+ end
+ local en = math.floor( i / 10 ) * 10 + 5
+ if canvasMap[ en ].e then
+ lm3s.disp.print( enemyChar, canvasMap[ en ].e, en, 0 )
+ canvasMap[ en ].e = nil
+ end
+ end
+
+end
+
+for i = 1, numOfEnemies, 1 do
+ createEnemy()
+end
+
+
+lm3s.disp.init( 1000000 )
+
+-- Initial information
+lm3s.disp.print( "eLua SpaceShip", 10, 40, 11 )
+lm3s.disp.print( "Press SELECT", 10, 70, 11 )
+local seed = 0
+while not buttonClicked( kit.BTN_SELECT ) do
+ seed = seed + 1
+end
+math.randomseed( seed )
+lm3s.disp.clear()
+
+-------------------------------------------------------------------------------
+--
+-- MAIN LOOP
+--
+-------------------------------------------------------------------------------
+pwm.setclock( 1, 25000000 )
+pwm.setup( 1, 1000, 70 )
+
+drawWall( xcanvas, ycanvas )
+
+while true do
+ updateEnemiesPos()
+ for i = 1, 3, 1 do
+ updateShipPos()
+ updateShots()
+ end
+ printBulletsNum()
+ printScore()
+ if buttonClicked( kit.BTN_SELECT ) then shot() end
+ if buttonClicked( kit.BTN_RIGHT ) then
+ destroyAll()
+ for i = 1, numOfEnemies, 1 do
+ createEnemy()
+ end
+ end
+ if score >= 50 then
+ won = true
+ break
+ end
+ if bullets <= 0 then
+ won = false
+ break
+ end
+ tmr.delay(1, 12000)
+ collectgarbage("collect")
+end
+if won then
+ lm3s.disp.clear()
+ lm3s.disp.print( "You won!", 50, 30, 11 )
+ lm3s.disp.print( "Congratulations!", 70, 20, 11 )
+else
+ lm3s.disp.clear()
+ lm3s.disp.print( "Game Over! :(", 60, 20, 11 )
+end
Added: branches/eagle_mmc/romfs/tetrives.lua
===================================================================
--- branches/eagle_mmc/romfs/tetrives.lua 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/romfs/tetrives.lua 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,385 @@
+-------------------------------------------------------------------------------
+--
+-- eLua Tetris Game
+--
+-- LED Lab @ PUC-Rio - 2009
+-- Dado Sutter
+-- Ives Negreiros
+-- Ricardo Rosa
+-- Pedro Bittencourt
+-- Rafael Barmak
+-- Teo Benjamin
+--
+-- Initial Version by Ives Negreiros, August 2009
+--
+---------------------------------------------------------------------------------
+local Vmax = 22 -- Number of pieces in vertical +1
+local Hmax = 12 -- Number of pieces horizontally + 2
+local score = 0 -- Player's score
+local highscore = 0 -- Player's highscore
+local next_piece = 0 -- Code for the next piece
+local PieceV = 0 -- Vertical position of the piece
+local PieceH = 0 -- Horizontal position of the piece
+local level = 1 -- Level
+local rotate_type = 0 -- Type of rotation for each piece
+local total_lines = 0 -- Total number of lines made by player
+local seed = 0 -- Variable used to make math.random return a diferent value each time
+local game_map = {} -- Table for the game map
+for i = 1, Vmax, 1 do
+ game_map[ i ] = {}
+end
+
+-- Initial information
+local platform = require( pd.board() )
+lm3s.disp.init( 1000000 )
+
+lm3s.disp.print( "Tetrives", 30, 30, 11 )
+lm3s.disp.print( "Press SELECT", 30, 60, 11 )
+while platform.btn_pressed( platform.BTN_SELECT ) == false do
+ seed = seed + 1
+end
+
+math.randomseed( seed )
+lm3s.disp.clear()
+
+function scan_piece( next_piece ) -- This function selec the next piece based on return of math.random function
+ if( next_piece == 1 ) then
+ next_piece_map = { { 1, 1 }, { 1, 1 } }
+ next_rotate_type = 0
+
+ elseif( next_piece == 2 ) then
+ next_piece_map = { { 1, 1, 0 }, { 0, 1, 1 }, { 0, 0, 0 } }
+ next_rotate_type = 1
+
+ elseif( next_piece == 3 ) then
+ next_piece_map = { { 0, 1, 1 }, { 1, 1, 0 }, { 0, 0, 0 } }
+ next_rotate_type = 1
+
+ elseif( next_piece == 4 ) then
+ next_piece_map = { { 0, 0, 1 }, { 1, 1, 1 }, { 0, 0, 0 } }
+ next_rotate_type = 2
+
+ elseif( next_piece == 5 ) then
+ next_piece_map = { { 1, 0, 0 }, { 1, 1, 1 }, { 0, 0, 0 } }
+ next_rotate_type = 2
+
+ elseif( next_piece == 6 ) then
+ next_piece_map = { { 0, 1, 0 }, { 1, 1, 1 }, { 0, 0, 0 } }
+ next_rotate_type = 2
+
+ elseif( next_piece == 7 ) then
+ next_piece_map = { {0, 0, 0, 0 }, { 1, 1, 1, 1 }, { 0, 0, 0, 0 }, { 0, 0, 0, 0 } }
+ next_rotate_type = 4
+ end
+end
+
+function draw_walls() -- This function draws the walls and the base of game piece screen
+ for i = 6, 63, 3 do
+ lm3s.disp.print( "|", 3, i, 11 )
+ end
+ for i = 3, 118, 4 do
+ lm3s.disp.print( "-", i, 2, 11 )
+ lm3s.disp.print( "-", i, 65, 11 )
+ end
+end
+
+function sound() -- This function beeps
+ pwm.start( 1 )
+ tmr.delay( 0, 20000 )
+ pwm.stop( 1 )
+end
+
+function print_data() -- This function writes the score and level on screen
+ lm3s.disp.print( "Score:"..tostring( score ), 0, 88, 8 )
+ lm3s.disp.print( "Level:"..tostring( level ), 0, 80, 8 )
+end
+
+function draw_piece() -- This function draws the piece on the screen
+ for i in ipairs( piece_map ) do
+ for j in ipairs( piece_map[ i ] ) do
+ if( piece_map[ i ][ j ] == 1 ) then
+ lm3s.disp.print( "*", ( PieceV + i - 1 ) * 6, ( PieceH + j - 1 ) * 6, 11 )
+ end
+ end
+ end
+end
+
+function erase_piece() -- This function erases the piece on the screen
+ for i in ipairs( piece_map ) do
+ for j in ipairs( piece_map[ i ] ) do
+ if( piece_map[ i ][ j ] == 1 ) then
+ lm3s.disp.print( "*", ( PieceV + i - 1 ) * 6, ( PieceH + j - 1 ) * 6, 0 )
+ end
+ end
+ end
+end
+
+function move_down() -- This function moves the piece down if there is no obstacle in the way, else create new piece
+ free = 0 -- It also test the lines (see function test_line for further explanation)
+ for i in ipairs( piece_map ) do
+ for j in ipairs( piece_map[ i ] ) do
+ if( piece_map[ i ][ j ] == 1 ) then
+ if( game_map[ PieceV + i - 1 ][ PieceH + j ] == 0 ) then
+ free = free + 1
+ end
+ end
+ end
+ end
+ if ( free == 4 ) then
+ erase_piece()
+ PieceV = PieceV - 1
+ draw_piece()
+ else
+ for i in ipairs( piece_map ) do
+ for j in ipairs( piece_map[ i ] ) do
+ if( piece_map[ i ][ j ] == 1 ) then
+ game_map[ PieceV + i ][ PieceH + j ] = 1
+ end
+ end
+ end
+ test_line()
+ create_new_piece()
+ end
+end
+
+function move_left() -- This function moves the piece left if there is no obstacle in the way
+ free = 0
+ for i in ipairs( piece_map ) do
+ for j in ipairs( piece_map[ i ] ) do
+ if( piece_map[ i ][ j ] == 1 ) then
+ if( game_map[ PieceV + i ][ PieceH + j - 1 ] == 0 ) then
+ free = free + 1
+ end
+ end
+ end
+ end
+ if ( free == 4 ) then
+ erase_piece()
+ PieceH = PieceH - 1
+ draw_piece()
+ end
+end
+
+function move_right() -- This function moves the piece right if there is no obstacle in the way
+ free = 0
+ for i in ipairs( piece_map ) do
+ for j in ipairs( piece_map[ i ] ) do
+ if( piece_map[ i ][ j ] == 1 ) then
+ if( game_map[ PieceV + i ][ PieceH + j + 1 ] == 0 ) then
+ free = free + 1
+ end
+ end
+ end
+ end
+ if ( free == 4 ) then
+ erase_piece()
+ PieceH = PieceH + 1
+ draw_piece()
+ end
+end
+
+function rotate() -- This function rotate the pieces
+ piecerot = {}
+ for i = 1, 4, 1 do
+ piecerot[ i ] = {}
+ end
+ free = 0
+ erase_piece()
+ if ( rotate_type == 1 or rotate_type == 2 ) then
+ for i in ipairs( piece_map ) do -- this loop test if each part of piece can rotate
+ for j in ipairs( piece_map[ i ] ) do
+ if( piece_map[ i ][ j ] == 1 ) then
+ if( game_map[ PieceV + j ][ 4 - i + PieceH ] == 0 ) then
+ free = free + 1
+ end
+ end
+ end
+ end
+ if( free == 4 ) then -- If all the parts of piece can rotate, then 'free' will be equals to four
+ if( rotate_type == 2 ) then
+ rotate_type = 1
+ end
+ for i in ipairs( piece_map ) do -- This loop rotates the piece
+ for j in ipairs( piece_map[ i ] ) do
+ piecerot[ i ][ j ] = piece_map[ j ][ 4 - i ] -- This is the equation of the rotation function for this type of rotation
+ end
+ end
+ piece_map = piecerot
+ end
+
+ elseif ( rotate_type == 3 ) then -- This part works like the upper part, but for another type of rotation
+ for i in ipairs( piece_map ) do
+ for j in ipairs( piece_map[ i ] ) do
+ if( piece_map[ i ][ j ] == 1 ) then
+ if( game_map[ 4 - j + PieceV ][ PieceH + i ] == 0 ) then
+ free = free + 1
+ end
+ end
+ end
+ end
+ if( free == 4 ) then
+ rotate_type = 2
+ for i in ipairs( piece_map ) do
+ for j in ipairs( piece_map[ i ] ) do
+ piecerot[ i ][ j ] = piece_map[ 4 - j ][ i ]
+ end
+ end
+ piece_map = piecerot
+ end
+
+ elseif ( rotate_type == 4 ) then -- This part works like the upper part, but for another type of rotation
+ for i in ipairs( piece_map ) do
+ for j in ipairs( piece_map[ i ] ) do
+ if( piece_map[ i ][ j ] == 1 ) then
+ if( game_map[ PieceV + j ][ PieceH + i ] == 0 ) then
+ free = free + 1
+ end
+ end
+ end
+ end
+ if(free == 4 ) then
+ for i in ipairs( piece_map ) do
+ for j in ipairs( piece_map [ i ] ) do
+ piecerot[ i ][ j ] = piece_map[ j ][ i ]
+ end
+ end
+ piece_map = piecerot
+ end
+ end
+ draw_piece()
+ sound()
+end
+
+function remove_line( line )
+ for i = line, Vmax - 2, 1 do
+ for j = 2, Hmax - 1, 1 do
+ lm3s.disp.print( "*", ( i - 1 ) * 6, ( j - 1 ) * 6, 0 )
+ game_map[ i ][ j ] = game_map[ i + 1 ][ j ]
+ if( game_map[ i ][ j ] == 1 ) then
+ lm3s.disp.print( "*", ( i - 1 ) * 6, ( j - 1 ) * 6, 11 )
+ end
+ end
+ end
+end
+
+function test_line() -- This function tests the lines, if there is a full line, then this
+ lines = 0 -- function removes this line and move down everything that is upper to it
+ i = 2
+ while ( i<Vmax ) do
+ j = 2
+ while ( j<Hmax ) do
+ if( game_map[i][j] == 0 ) then
+ break
+ elseif( j == Hmax - 1 ) then
+ remove_line( i )
+ lines = lines + 1
+ i = i - 1
+ break
+ end
+ j = j + 1
+ end
+ i = i + 1
+ end
+ total_lines = total_lines + lines
+ score = score + 100 * level * lines * lines -- This is the euqation for the score value
+ if( total_lines >= 8 and level < 4 ) then
+ level = level + 1
+ total_lines = 0
+ end
+end
+
+function create_new_piece() -- This Function creates a new piece
+ piece_map = next_piece_map
+ rotate_type = next_rotate_type
+ PieceV = 18
+ PieceH = 4
+ next_piece = math.random( 7 )
+ scan_piece ( next_piece )
+ for i = 1, 2, 1 do
+ for j = 1, 4, 1 do
+ lm3s.disp.print( "*", 94 + ( j * 6 ), 78 + ( i * 6 ), 0 )
+ end
+ end
+ for i in ipairs( next_piece_map ) do
+ if( i == 3 ) then
+ break
+ end
+ for j in ipairs( next_piece_map[ i ] ) do
+ if( next_piece_map[ i ][ j ] == 1 ) then
+ lm3s.disp.print( "*", 94 + ( j * 6 ), 78 + ( ( 3 - i ) * 6 ), 11 )
+ end
+ end
+ end
+ draw_piece()
+end
+
+---------------------------------------------------------------------------------
+-- --
+-- MAIN LOOP --
+-- --
+---------------------------------------------------------------------------------
+repeat
+
+ for i in ipairs( game_map ) do -- This loop create the border of game's map
+ for j = 1, Hmax, 1 do
+ if( j == 1 or j == Hmax or i == 1 or i == Vmax ) then
+ game_map[ i ][ j ] = 1
+ else
+ game_map[ i ][ j ] = 0
+ end
+ end
+ end
+ level = 1 -- This statements sets the level and score from the beginning
+ score = 0
+ pwm.setclock( 1, 25000000 ) -- This statements sets the PWM for the sound function
+ pwm.setup( 1, 1000, 70 )
+ draw_walls()
+ next_piece = math.random(7)
+ scan_piece ( next_piece )
+ create_new_piece()
+ collectgarbage( "collect" )
+ while true do -- This loop refreshes the data and responds the player's input
+ print_data ()
+ Tmax = 11 - 2 * level -- This statement raises the speed based on the level
+ for i = 1, Tmax, 1 do
+ if platform.btn_pressed( platform.BTN_UP ) then
+ move_left()
+ end
+ if platform.btn_pressed( platform.BTN_DOWN ) then
+ move_right()
+ end
+ if platform.btn_pressed( platform.BTN_RIGHT ) then
+ rotate()
+ end
+ if platform.btn_pressed( platform.BTN_LEFT ) then -- If the player presses "down", the piece drops instantly and a point is added to score
+ score = score + 1
+ tmr.delay( 1, 30000 )
+ break
+ end
+ tmr.delay( 1, 70000 )
+ end
+ move_down()
+ if( game_map[ PieceV + 2 ][ PieceH + 2 ] == 1 ) then -- If this condition is true then game over
+ break
+ end
+ collectgarbage( "collect" )
+ end
+
+ if score > highscore then
+ highscore = score
+ end
+ lm3s.disp.clear() -- This statements displays the game over screen
+ lm3s.disp.print( "Game Over :(", 30, 20, 11 )
+ lm3s.disp.print( "Your score was "..tostring( score ), 0, 40, 11 )
+ lm3s.disp.print( "Highscore: "..tostring( highscore ), 15, 50, 11 )
+ lm3s.disp.print( "SELECT to restart", 6, 70, 11 )
+ enough = true -- If the player presses select before the time reach 1000000ms, then restart the game
+ for i=1, 1000000 do
+ if platform.btn_pressed( platform.BTN_SELECT ) then
+ enough = false
+ break
+ end
+ end
+ lm3s.disp.clear()
+until ( enough )
+lm3s.disp.off()
Modified: branches/eagle_mmc/src/lua/lapi.c
===================================================================
--- branches/eagle_mmc/src/lua/lapi.c 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/lua/lapi.c 2009-11-06 02:08:32 UTC (rev 526)
@@ -687,14 +687,14 @@
LUA_API void lua_setfield (lua_State *L, int idx, const char *k) {
StkId t;
- TValue key;
lua_lock(L);
api_checknelems(L, 1);
t = index2adr(L, idx);
api_checkvalidindex(L, t);
- setsvalue(L, &key, luaS_new(L, k));
- luaV_settable(L, t, &key, L->top - 1);
- L->top--; /* pop value */
+ setsvalue2s(L, L->top, luaS_new(L, k));
+ api_incr_top(L);
+ luaV_settable(L, t, L->top - 1, L->top - 2);
+ L->top -= 2; /* pop key and value */
lua_unlock(L);
}
@@ -940,11 +940,11 @@
g = G(L);
switch (what) {
case LUA_GCSTOP: {
- g->GCthreshold = MAX_LUMEM;
+ set_block_gc(L);
break;
}
case LUA_GCRESTART: {
- g->GCthreshold = g->totalbytes;
+ unset_block_gc(L);
break;
}
case LUA_GCCOLLECT: {
@@ -961,6 +961,10 @@
break;
}
case LUA_GCSTEP: {
+ if(is_block_gc(L)) {
+ res = 1; /* gc is block so we need to pretend that the collection cycle finished. */
+ break;
+ }
lu_mem a = (cast(lu_mem, data) << 10);
if (a <= g->totalbytes)
g->GCthreshold = g->totalbytes - a;
@@ -985,6 +989,24 @@
g->gcstepmul = data;
break;
}
+ case LUA_GCSETMEMLIMIT: {
+ /* GC values are expressed in Kbytes: #bytes/2^10 */
+ lu_mem new_memlimit = (cast(lu_mem, data) << 10);
+ if(new_memlimit > 0 && new_memlimit < g->totalbytes) {
+ /* run a full GC to make totalbytes < the new limit. */
+ luaC_fullgc(L);
+ if(new_memlimit < g->totalbytes)
+ new_memlimit = (g->totalbytes + 1024) & ~(1024-1); /* round up to next multiple of 1024 */
+ }
+ g->memlimit = new_memlimit;
+ /* new memlimit might be > then requested memlimit. */
+ res = cast_int(new_memlimit >> 10);
+ break;
+ }
+ case LUA_GCGETMEMLIMIT: {
+ res = cast_int(g->memlimit >> 10);
+ break;
+ }
default: res = -1; /* invalid option */
}
lua_unlock(L);
Modified: branches/eagle_mmc/src/lua/lauxlib.c
===================================================================
--- branches/eagle_mmc/src/lua/lauxlib.c 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/lua/lauxlib.c 2009-11-06 02:08:32 UTC (rev 526)
@@ -25,6 +25,10 @@
#include "lrotable.h"
#include "lauxlib.h"
+#include "lgc.h"
+#include "ldo.h"
+#include "lobject.h"
+#include "lstate.h"
#define FREELIST_REF 0 /* free list of references */
@@ -674,15 +678,39 @@
/* }====================================================== */
+static int l_check_memlimit(lua_State *L, size_t needbytes) {
+ global_State *g = G(L);
+ int cycle_count = 0;
+ lu_mem limit = g->memlimit - needbytes;
+ /* make sure the GC is not disabled. */
+ if (!is_block_gc(L)) {
+ while (g->totalbytes >= limit) {
+ /* only allow the GC to finished atleast 1 full cycle. */
+ if (g->gcstate == GCSpause && ++cycle_count > 1) break;
+ luaC_step(L);
+ }
+ }
+ return (g->totalbytes >= limit) ? 1 : 0;
+}
+
+
static void *l_alloc (void *ud, void *ptr, size_t osize, size_t nsize) {
- (void)ud;
- (void)osize;
+ lua_State *L = (lua_State *)ud;
+ void *nptr;
if (nsize == 0) {
free(ptr);
return NULL;
}
- else
- return realloc(ptr, nsize);
+ if(nsize > osize && L != NULL) {
+ if(G(L)->memlimit > 0 && l_check_memlimit(L, nsize - osize))
+ return NULL;
+ }
+ nptr = realloc(ptr, nsize);
+ if (nptr == NULL && L != NULL) {
+ luaC_fullgc(L); /* emergency full collection. */
+ nptr = realloc(ptr, nsize); /* try allocation again */
+ }
+ return nptr;
}
@@ -696,6 +724,7 @@
LUALIB_API lua_State *luaL_newstate (void) {
lua_State *L = lua_newstate(l_alloc, NULL);
+ lua_setallocf(L, l_alloc, L); /* allocator need lua_State. */
if (L) lua_atpanic(L, &panic);
return L;
}
Modified: branches/eagle_mmc/src/lua/lbaselib.c
===================================================================
--- branches/eagle_mmc/src/lua/lbaselib.c 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/lua/lbaselib.c 2009-11-06 02:08:32 UTC (rev 526)
@@ -193,9 +193,10 @@
static int luaB_collectgarbage (lua_State *L) {
static const char *const opts[] = {"stop", "restart", "collect",
- "count", "step", "setpause", "setstepmul", NULL};
+ "count", "step", "setpause", "setstepmul","setmemlimit","getmemlimit", NULL};
static const int optsnum[] = {LUA_GCSTOP, LUA_GCRESTART, LUA_GCCOLLECT,
- LUA_GCCOUNT, LUA_GCSTEP, LUA_GCSETPAUSE, LUA_GCSETSTEPMUL};
+ LUA_GCCOUNT, LUA_GCSTEP, LUA_GCSETPAUSE, LUA_GCSETSTEPMUL,
+ LUA_GCSETMEMLIMIT,LUA_GCGETMEMLIMIT};
int o = luaL_checkoption(L, 1, "collect", opts);
int ex = luaL_optint(L, 2, 0);
int res = lua_gc(L, optsnum[o], ex);
Modified: branches/eagle_mmc/src/lua/ldo.c
===================================================================
--- branches/eagle_mmc/src/lua/ldo.c 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/lua/ldo.c 2009-11-06 02:08:32 UTC (rev 526)
@@ -208,7 +208,9 @@
static StkId adjust_varargs (lua_State *L, Proto *p, int actual) {
int i;
int nfixargs = p->numparams;
+#if defined(LUA_COMPAT_VARARG)
Table *htab = NULL;
+#endif
StkId base, fixed;
for (; actual < nfixargs; ++actual)
setnilvalue(L->top++);
@@ -218,10 +220,13 @@
lua_assert(p->is_vararg & VARARG_HASARG);
luaC_checkGC(L);
htab = luaH_new(L, nvar, 1); /* create `arg' table */
+ sethvalue2s(L, L->top, htab); /* put table on stack */
+ incr_top(L);
for (i=0; i<nvar; i++) /* put extra arguments into `arg' table */
- setobj2n(L, luaH_setnum(L, htab, i+1), L->top - nvar + i);
+ setobj2n(L, luaH_setnum(L, htab, i+1), L->top - 1 - nvar + i);
/* store counter in field `n' */
setnvalue(luaH_setstr(L, htab, luaS_newliteral(L, "n")), cast_num(nvar));
+ L->top--; /* remove table from stack */
}
#endif
/* move fixed parameters to final position */
@@ -231,11 +236,13 @@
setobjs2s(L, L->top++, fixed+i);
setnilvalue(fixed+i);
}
+#if defined(LUA_COMPAT_VARARG)
/* add `arg' parameter */
if (htab) {
sethvalue(L, L->top++, htab);
lua_assert(iswhite(obj2gco(htab)));
}
+#endif
return base;
}
@@ -498,6 +505,7 @@
struct SParser *p = cast(struct SParser *, ud);
int c = luaZ_lookahead(p->z);
luaC_checkGC(L);
+ set_block_gc(L); /* stop collector during parsing */
tf = ((c == LUA_SIGNATURE[0]) ? luaU_undump : luaY_parser)(L, p->z,
&p->buff, p->name);
cl = luaF_newLclosure(L, tf->nups, hvalue(gt(L)));
@@ -506,6 +514,7 @@
cl->l.upvals[i] = luaF_newupval(L);
setclvalue(L, L->top, cl);
incr_top(L);
+ unset_block_gc(L);
}
Modified: branches/eagle_mmc/src/lua/lfunc.c
===================================================================
--- branches/eagle_mmc/src/lua/lfunc.c 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/lua/lfunc.c 2009-11-06 02:08:32 UTC (rev 526)
@@ -66,7 +66,6 @@
}
uv = luaM_new(L, UpVal); /* not found: create a new one */
uv->tt = LUA_TUPVAL;
- uv->marked = luaC_white(g);
uv->v = level; /* current value lives in the stack */
uv->next = *pp; /* chain it in the proper position */
*pp = obj2gco(uv);
@@ -74,6 +73,7 @@
uv->u.l.next = g->uvhead.u.l.next;
uv->u.l.next->u.l.prev = uv;
g->uvhead.u.l.next = uv;
+ luaC_marknew(L, obj2gco(uv));
lua_assert(uv->u.l.next->u.l.prev == uv && uv->u.l.prev->u.l.next == uv);
return uv;
}
Modified: branches/eagle_mmc/src/lua/lgc.c
===================================================================
--- branches/eagle_mmc/src/lua/lgc.c 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/lua/lgc.c 2009-11-06 02:08:32 UTC (rev 526)
@@ -232,8 +232,10 @@
int i;
lua_assert(cl->l.nupvalues == cl->l.p->nups);
markobject(g, cl->l.p);
- for (i=0; i<cl->l.nupvalues; i++) /* mark its upvalues */
- markobject(g, cl->l.upvals[i]);
+ for (i=0; i<cl->l.nupvalues; i++) { /* mark its upvalues */
+ if(cl->l.upvals[i])
+ markobject(g, cl->l.upvals[i]);
+ }
}
}
@@ -258,6 +260,7 @@
CallInfo *ci;
markvalue(g, gt(l));
lim = l->top;
+ if(l->stack == NULL) return; /* no stack to traverse */
for (ci = l->base_ci; ci <= l->ci; ci++) {
lua_assert(ci->top <= l->stack_last);
if (lim < ci->top) lim = ci->top;
@@ -419,8 +422,6 @@
else { /* must erase `curr' */
lua_assert(isdead(g, curr) || deadmask == bitmask(SFIXEDBIT));
*p = curr->gch.next;
- if (curr == g->rootgc) /* is the first element of the list? */
- g->rootgc = curr->gch.next; /* adjust first */
freeobj(L, curr);
}
}
@@ -437,7 +438,10 @@
/* check size of buffer */
if (luaZ_sizebuffer(&g->buff) > LUA_MINBUFFER*2) { /* buffer too big? */
size_t newsize = luaZ_sizebuffer(&g->buff) / 2;
- luaZ_resizebuffer(L, &g->buff, newsize);
+ /* make sure newsize is larger then the buffer's in use size. */
+ newsize = (luaZ_bufflen(&g->buff) > newsize) ? luaZ_bufflen(&g->buff) : newsize;
+ if(newsize < luaZ_sizebuffer(&g->buff))
+ luaZ_resizebuffer(L, &g->buff, newsize);
}
}
@@ -609,10 +613,14 @@
void luaC_step (lua_State *L) {
global_State *g = G(L);
+ if(is_block_gc(L)) return;
+ set_block_gc(L);
l_mem lim = (GCSTEPSIZE/100) * g->gcstepmul;
if (lim == 0)
lim = (MAX_LUMEM-1)/2; /* no limit */
g->gcdept += g->totalbytes - g->GCthreshold;
+ if (g->estimate > g->totalbytes)
+ g->estimate = g->totalbytes;
do {
lim -= singlestep(L);
if (g->gcstate == GCSpause)
@@ -630,11 +638,14 @@
lua_assert(g->totalbytes >= g->estimate);
setthreshold(g);
}
+ unset_block_gc(L);
}
void luaC_fullgc (lua_State *L) {
global_State *g = G(L);
+ if(is_block_gc(L)) return;
+ set_block_gc(L);
if (g->gcstate <= GCSpropagate) {
/* reset sweep marks to sweep all elements (returning them to white) */
g->sweepstrgc = 0;
@@ -656,6 +667,7 @@
singlestep(L);
}
setthreshold(g);
+ unset_block_gc(L);
}
@@ -683,6 +695,14 @@
}
+void luaC_marknew (lua_State *L, GCObject *o) {
+ global_State *g = G(L);
+ o->gch.marked = luaC_white(g);
+ if (g->gcstate == GCSpropagate)
+ reallymarkobject(g, o); /* mark new objects as gray during propagate state. */
+}
+
+
void luaC_link (lua_State *L, GCObject *o, lu_byte tt) {
global_State *g = G(L);
o->gch.next = g->rootgc;
Modified: branches/eagle_mmc/src/lua/lgc.h
===================================================================
--- branches/eagle_mmc/src/lua/lgc.h 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/lua/lgc.h 2009-11-06 02:08:32 UTC (rev 526)
@@ -37,7 +37,23 @@
#define test2bits(x,b1,b2) testbits(x, (bit2mask(b1, b2)))
+/*
+** Possible Garbage Collector flags.
+** Layout for bit use in 'gsflags' field in global_State structure.
+** bit 0 - Protect GC from recursive calls.
+*/
+#define GCFlagsNone 0
+#define GCBlockGCBit 0
+#define GCResizingStringsBit 1
+
+#define is_block_gc(L) testbit(G(L)->gcflags, GCBlockGCBit)
+#define set_block_gc(L) l_setbit(G(L)->gcflags, GCBlockGCBit)
+#define unset_block_gc(L) resetbit(G(L)->gcflags, GCBlockGCBit)
+#define is_resizing_strings_gc(L) testbit(G(L)->gcflags, GCResizingStringsBit)
+#define set_resizing_strings_gc(L) l_setbit(G(L)->gcflags, GCResizingStringsBit)
+#define unset_resizing_strings_gc(L) resetbit(G(L)->gcflags, GCResizingStringsBit)
+
/*
** Layout for bit use in `marked' field:
** bit 0 - object is white (type 0)
@@ -101,6 +117,7 @@
LUAI_FUNC void luaC_freeall (lua_State *L);
LUAI_FUNC void luaC_step (lua_State *L);
LUAI_FUNC void luaC_fullgc (lua_State *L);
+LUAI_FUNC void luaC_marknew (lua_State *L, GCObject *o);
LUAI_FUNC void luaC_link (lua_State *L, GCObject *o, lu_byte tt);
LUAI_FUNC void luaC_linkupval (lua_State *L, UpVal *uv);
LUAI_FUNC void luaC_barrierf (lua_State *L, GCObject *o, GCObject *v);
Modified: branches/eagle_mmc/src/lua/linit.c
===================================================================
--- branches/eagle_mmc/src/lua/linit.c 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/lua/linit.c 2009-11-06 02:08:32 UTC (rev 526)
@@ -19,6 +19,8 @@
#include "platform_conf.h"
#endif
+extern int luaopen_platform( lua_State *L );
+
#ifdef LUA_REMOTE
#include "auxmods.h"
#define LUA_PLATFORM_LIBS_ROM \
@@ -38,7 +40,7 @@
#ifdef LUA_PLATFORM_LIBS_REG
LUA_PLATFORM_LIBS_REG,
#endif
-#if defined(LUA_PLATFORM_LIBS_ROM) && LUA_OPTIMIZE_MEMORY != 2
+#if defined(LUA_PLATFORM_LIBS_ROM)
#define _ROM( name, openf, table ) { name, openf },
LUA_PLATFORM_LIBS_ROM
#endif
@@ -65,7 +67,7 @@
#if defined(LUA_PLATFORM_LIBS_ROM) && LUA_OPTIMIZE_MEMORY == 2
#undef _ROM
#define _ROM( name, openf, table ) { name, table },
-LUA_PLATFORM_LIBS_ROM
+ LUA_PLATFORM_LIBS_ROM
#endif
#endif
{NULL, NULL}
@@ -79,3 +81,4 @@
lua_call(L, 1, 0);
}
}
+
Modified: branches/eagle_mmc/src/lua/lrotable.c
===================================================================
--- branches/eagle_mmc/src/lua/lrotable.c 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/lua/lrotable.c 2009-11-06 02:08:32 UTC (rev 526)
@@ -36,8 +36,8 @@
if (pentry == NULL)
return NULL;
while(pentry->key.type != LUA_TNIL) {
- if ((strkey && (pentry->key.type == LUA_TSTRING) && (!strcmp(pentry->key.strkey, strkey))) ||
- (!strkey && (pentry->key.type == LUA_TNUMBER) && ((luaR_numkey)pentry->key.numkey == numkey))) {
+ if ((strkey && (pentry->key.type == LUA_TSTRING) && (!strcmp(pentry->key.id.strkey, strkey))) ||
+ (!strkey && (pentry->key.type == LUA_TNUMBER) && ((luaR_numkey)pentry->key.id.numkey == numkey))) {
res = &pentry->value;
break;
}
@@ -84,9 +84,9 @@
if (pentries[pos].key.type != LUA_TNIL) {
/* Found an entry */
if (pentries[pos].key.type == LUA_TSTRING)
- setsvalue(L, key, luaS_new(L, pentries[pos].key.strkey))
+ setsvalue(L, key, luaS_new(L, pentries[pos].key.id.strkey))
else
- setnvalue(key, (lua_Number)pentries[pos].key.numkey)
+ setnvalue(key, (lua_Number)pentries[pos].key.id.numkey)
setobj2s(L, val, &pentries[pos].value);
}
}
Modified: branches/eagle_mmc/src/lua/lrotable.h
===================================================================
--- branches/eagle_mmc/src/lua/lrotable.h 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/lua/lrotable.h 2009-11-06 02:08:32 UTC (rev 526)
@@ -32,7 +32,7 @@
{
const char* strkey;
luaR_numkey numkey;
- };
+ } id;
} luaR_key;
/* An entry in the read only table */
Modified: branches/eagle_mmc/src/lua/lstate.c
===================================================================
--- branches/eagle_mmc/src/lua/lstate.c 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/lua/lstate.c 2009-11-06 02:08:32 UTC (rev 526)
@@ -119,6 +119,8 @@
lua_State *luaE_newthread (lua_State *L) {
lua_State *L1 = tostate(luaM_malloc(L, state_size(lua_State)));
luaC_link(L, obj2gco(L1), LUA_TTHREAD);
+ setthvalue(L, L->top, L1); /* put thread on stack */
+ incr_top(L);
preinit_state(L1, G(L));
stack_init(L1, L); /* init stack */
setobj2n(L, gt(L1), gt(L)); /* share table of globals */
@@ -126,7 +128,8 @@
L1->basehookcount = L->basehookcount;
L1->hook = L->hook;
resethookcount(L1);
- lua_assert(iswhite(obj2gco(L1)));
+ lua_assert(!isdead(G(L), obj2gco(L1)));
+ L->top--; /* remove thread from stack */
return L1;
}
@@ -160,6 +163,7 @@
g->uvhead.u.l.prev = &g->uvhead;
g->uvhead.u.l.next = &g->uvhead;
g->GCthreshold = 0; /* mark it as unfinished state */
+ g->estimate = 0;
g->strt.size = 0;
g->strt.nuse = 0;
g->strt.hash = NULL;
@@ -167,6 +171,7 @@
luaZ_initbuffer(L, &g->buff);
g->panic = NULL;
g->gcstate = GCSpause;
+ g->gcflags = GCFlagsNone;
g->rootgc = obj2gco(L);
g->sweepstrgc = 0;
g->sweepgc = &g->rootgc;
@@ -175,6 +180,7 @@
g->weak = NULL;
g->tmudata = NULL;
g->totalbytes = sizeof(LG);
+ g->memlimit = 0;
g->gcpause = LUAI_GCPAUSE;
g->gcstepmul = LUAI_GCMUL;
g->gcdept = 0;
Modified: branches/eagle_mmc/src/lua/lstate.h
===================================================================
--- branches/eagle_mmc/src/lua/lstate.h 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/lua/lstate.h 2009-11-06 02:08:32 UTC (rev 526)
@@ -71,6 +71,7 @@
void *ud; /* auxiliary data to `frealloc' */
lu_byte currentwhite;
lu_byte gcstate; /* state of garbage collector */
+ lu_byte gcflags; /* flags for the garbage collector */
int sweepstrgc; /* position of sweep in `strt' */
GCObject *rootgc; /* list of all collectable objects */
GCObject **sweepgc; /* position of sweep in `rootgc' */
@@ -81,6 +82,7 @@
Mbuffer buff; /* temporary buffer for string concatentation */
lu_mem GCthreshold;
lu_mem totalbytes; /* number of bytes currently allocated */
+ lu_mem memlimit; /* maximum number of bytes that can be allocated, 0 = no limit. */
lu_mem estimate; /* an estimate of number of bytes actually in use */
lu_mem gcdept; /* how much GC is `behind schedule' */
int gcpause; /* size of pause between successive GCs */
Modified: branches/eagle_mmc/src/lua/lstring.c
===================================================================
--- branches/eagle_mmc/src/lua/lstring.c 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/lua/lstring.c 2009-11-06 02:08:32 UTC (rev 526)
@@ -20,30 +20,34 @@
void luaS_resize (lua_State *L, int newsize) {
- GCObject **newhash;
stringtable *tb;
int i;
- if (G(L)->gcstate == GCSsweepstring)
- return; /* cannot resize during GC traverse */
- newhash = luaM_newvector(L, newsize, GCObject *);
tb = &G(L)->strt;
- for (i=0; i<newsize; i++) newhash[i] = NULL;
+ if (G(L)->gcstate == GCSsweepstring || newsize == tb->size || is_resizing_strings_gc(L))
+ return; /* cannot resize during GC traverse or doesn't need to be resized */
+ set_resizing_strings_gc(L);
+ if (newsize > tb->size) {
+ luaM_reallocvector(L, tb->hash, tb->size, newsize, GCObject *);
+ for (i=tb->size; i<newsize; i++) tb->hash[i] = NULL;
+ }
/* rehash */
for (i=0; i<tb->size; i++) {
GCObject *p = tb->hash[i];
+ tb->hash[i] = NULL;
while (p) { /* for each node in the list */
GCObject *next = p->gch.next; /* save next */
unsigned int h = gco2ts(p)->hash;
int h1 = lmod(h, newsize); /* new position */
lua_assert(cast_int(h%newsize) == lmod(h, newsize));
- p->gch.next = newhash[h1]; /* chain it */
- newhash[h1] = p;
+ p->gch.next = tb->hash[h1]; /* chain it */
+ tb->hash[h1] = p;
p = next;
}
}
- luaM_freearray(L, tb->hash, tb->size, TString *);
+ if (newsize < tb->size)
+ luaM_reallocvector(L, tb->hash, tb->size, newsize, GCObject *);
tb->size = newsize;
- tb->hash = newhash;
+ unset_resizing_strings_gc(L);
}
@@ -53,6 +57,9 @@
stringtable *tb;
if (l+1 > (MAX_SIZET - sizeof(TString))/sizeof(char))
luaM_toobig(L);
+ tb = &G(L)->strt;
+ if ((tb->nuse + 1) > cast(lu_int32, tb->size) && tb->size <= MAX_INT/2)
+ luaS_resize(L, tb->size*2); /* too crowded */
ts = cast(TString *, luaM_malloc(L, (l+1)*sizeof(char)+sizeof(TString)));
ts->tsv.len = l;
ts->tsv.hash = h;
@@ -61,13 +68,10 @@
ts->tsv.reserved = 0;
memcpy(ts+1, str, l*sizeof(char));
((char *)(ts+1))[l] = '\0'; /* ending 0 */
- tb = &G(L)->strt;
h = lmod(h, tb->size);
ts->tsv.next = tb->hash[h]; /* chain new entry */
tb->hash[h] = obj2gco(ts);
tb->nuse++;
- if (tb->nuse > cast(lu_int32, tb->size) && tb->size <= MAX_INT/2)
- luaS_resize(L, tb->size*2); /* too crowded */
return ts;
}
Modified: branches/eagle_mmc/src/lua/ltable.c
===================================================================
--- branches/eagle_mmc/src/lua/ltable.c 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/lua/ltable.c 2009-11-06 02:08:32 UTC (rev 526)
@@ -277,20 +277,35 @@
}
-static void setnodevector (lua_State *L, Table *t, int size) {
+static Node *getfreepos (Table *t) {
+ while (t->lastfree-- > t->node) {
+ if (ttisnil(gkey(t->lastfree)))
+ return t->lastfree;
+ }
+ return NULL; /* could not find a free place */
+}
+
+
+static void resizenodevector (lua_State *L, Table *t, int oldsize, int newsize) {
int lsize;
- if (size == 0) { /* no elements to hash part? */
+ if (newsize == 0) { /* no elements to hash part? */
t->node = cast(Node *, dummynode); /* use common `dummynode' */
lsize = 0;
}
else {
+ Node *node = t->node;
int i;
- lsize = ceillog2(size);
+ lsize = ceillog2(newsize);
if (lsize > MAXBITS)
luaG_runerror(L, "table overflow");
- size = twoto(lsize);
- t->node = luaM_newvector(L, size, Node);
- for (i=0; i<size; i++) {
+ newsize = twoto(lsize);
+ if (node == dummynode) {
+ oldsize = 0;
+ node = NULL; /* don't try to realloc `dummynode' pointer. */
+ }
+ luaM_reallocvector(L, node, oldsize, newsize, Node);
+ t->node = node;
+ for (i=oldsize; i<newsize; i++) {
Node *n = gnode(t, i);
gnext(n) = NULL;
setnilvalue(gkey(n));
@@ -298,19 +313,138 @@
}
}
t->lsizenode = cast_byte(lsize);
- t->lastfree = gnode(t, size); /* all positions are free */
+ t->lastfree = gnode(t, newsize); /* reset lastfree to end of table. */
}
+static Node *find_prev_node(Node *mp, Node *next) {
+ Node *prev = mp;
+ while (prev != NULL && gnext(prev) != next) prev = gnext(prev);
+ return prev;
+}
+
+
+/*
+** move a node from it's old position to it's new position during a rehash;
+** first, check whether the moving node's main position is free. If not, check whether
+** colliding node is in its main position or not: if it is not, move colliding
+** node to an empty place and put moving node in its main position; otherwise
+** (colliding node is in its main position), moving node goes to an empty position.
+*/
+static int move_node (lua_State *L, Table *t, Node *node) {
+ Node *mp = mainposition(t, key2tval(node));
+ /* if node is in it's main position, don't need to move node. */
+ if (mp == node) return 1;
+ /* if node is in it's main position's chain, don't need to move node. */
+ if (find_prev_node(mp, node) != NULL) return 1;
+ /* is main position is free? */
+ if (!ttisnil(gval(mp)) || mp == dummynode) {
+ /* no; move main position node if it is out of its main position */
+ Node *othermp;
+ othermp = mainposition(t, key2tval(mp));
+ if (othermp != mp) { /* is colliding node out of its main position? */
+ /* yes; swap colliding node with the node that is being moved. */
+ Node *prev;
+ Node tmp;
+ tmp = *node;
+ prev = find_prev_node(othermp, mp); /* find previous */
+ if (prev != NULL) gnext(prev) = node; /* redo the chain with `n' in place of `mp' */
+ *node = *mp; /* copy colliding node into free pos. (mp->next also goes) */
+ *mp = tmp;
+ return (prev != NULL) ? 1 : 0; /* is colliding node part of its main position chain? */
+ }
+ else { /* colliding node is in its own main position */
+ /* add node to main position's chain. */
+ gnext(node) = gnext(mp); /* chain new position */
+ gnext(mp) = node;
+ }
+ }
+ else { /* main position is free, move node */
+ *mp = *node;
+ gnext(node) = NULL;
+ setnilvalue(gkey(node));
+ setnilvalue(gval(node));
+ }
+ return 1;
+}
+
+
+static int move_number (lua_State *L, Table *t, Node *node) {
+ int key;
+ lua_Number n = nvalue(key2tval(node));
+ lua_number2int(key, n);
+ if (luai_numeq(cast_num(key), nvalue(key2tval(node)))) {/* index is int? */
+ /* (1 <= key && key <= t->sizearray) */
+ if (cast(unsigned int, key-1) < cast(unsigned int, t->sizearray)) {
+ setobjt2t(L, &t->array[key-1], gval(node));
+ setnilvalue(gkey(node));
+ setnilvalue(gval(node));
+ return 1;
+ }
+ }
+ return 0;
+}
+
+
+static void resize_hashpart (lua_State *L, Table *t, int nhsize) {
+ int i;
+ int lsize=0;
+ int oldhsize = (t->node != dummynode) ? twoto(t->lsizenode) : 0;
+ if (nhsize > 0) { /* round new hashpart size up to next power of two. */
+ lsize=ceillog2(nhsize);
+ if (lsize > MAXBITS)
+ luaG_runerror(L, "table overflow");
+ }
+ nhsize = twoto(lsize);
+ /* grow hash part to new size. */
+ if (oldhsize < nhsize)
+ resizenodevector(L, t, oldhsize, nhsize);
+ else { /* hash part might be shrinking */
+ if (nhsize > 0) {
+ t->lsizenode = cast_byte(lsize);
+ t->lastfree = gnode(t, nhsize); /* reset lastfree back to end of table. */
+ }
+ else { /* new hashpart size is zero. */
+ resizenodevector(L, t, oldhsize, nhsize);
+ return;
+ }
+ }
+ /* break old chains, try moving int keys to array part and compact keys into new hashpart */
+ for (i = 0; i < oldhsize; i++) {
+ Node *old = gnode(t, i);
+ gnext(old) = NULL;
+ if (ttisnil(gval(old))) { /* clear nodes with nil values. */
+ setnilvalue(gkey(old));
+ continue;
+ }
+ if (ttisnumber(key2tval(old))) { /* try moving the int keys into array part. */
+ if(move_number(L, t, old))
+ continue;
+ }
+ if (i >= nhsize) { /* move all valid keys to indices < nhsize. */
+ Node *n = getfreepos(t); /* get a free place */
+ lua_assert(n != dummynode && n != NULL);
+ *n = *old;
+ }
+ }
+ /* shrink hash part */
+ if (oldhsize > nhsize)
+ resizenodevector(L, t, oldhsize, nhsize);
+ /* move nodes to their new mainposition and re-create node chains */
+ for (i = 0; i < nhsize; i++) {
+ Node *curr = gnode(t, i);
+ if (!ttisnil(gval(curr)))
+ while (move_node(L, t, curr) == 0);
+ }
+}
+
+
static void resize (lua_State *L, Table *t, int nasize, int nhsize) {
int i;
int oldasize = t->sizearray;
- int oldhsize = t->lsizenode;
- Node *nold = t->node; /* save old hash ... */
if (nasize > oldasize) /* array part must grow? */
setarrayvector(L, t, nasize);
- /* create new hash part with appropriate size */
- setnodevector(L, t, nhsize);
+ resize_hashpart(L, t, nhsize);
if (nasize < oldasize) { /* array part must shrink? */
t->sizearray = nasize;
/* re-insert elements from vanishing slice */
@@ -321,14 +455,6 @@
/* shrink array */
luaM_reallocvector(L, t->array, oldasize, nasize, TValue);
}
- /* re-insert elements from hash part */
- for (i = twoto(oldhsize) - 1; i >= 0; i--) {
- Node *old = nold+i;
- if (!ttisnil(gval(old)))
- setobjt2t(L, luaH_set(L, t, key2tval(old)), gval(old));
- }
- if (nold != dummynode)
- luaM_freearray(L, nold, twoto(oldhsize), Node); /* free old array */
}
@@ -366,6 +492,8 @@
Table *luaH_new (lua_State *L, int narray, int nhash) {
Table *t = luaM_new(L, Table);
luaC_link(L, obj2gco(t), LUA_TTABLE);
+ sethvalue2s(L, L->top, t); /* put table on stack */
+ incr_top(L);
t->metatable = NULL;
t->flags = cast_byte(~0);
/* temporary values (kept only if some malloc fails) */
@@ -374,7 +502,8 @@
t->lsizenode = 0;
t->node = cast(Node *, dummynode);
setarrayvector(L, t, narray);
- setnodevector(L, t, nhash);
+ resizenodevector(L, t, 0, nhash);
+ L->top--; /* remove table from stack */
return t;
}
@@ -387,16 +516,7 @@
}
-static Node *getfreepos (Table *t) {
- while (t->lastfree-- > t->node) {
- if (ttisnil(gkey(t->lastfree)))
- return t->lastfree;
- }
- return NULL; /* could not find a free place */
-}
-
-
/*
** inserts a new key into a hash table; first, check whether key's main
** position is free. If not, check whether colliding node is in its main
Modified: branches/eagle_mmc/src/lua/lua.c
===================================================================
--- branches/eagle_mmc/src/lua/lua.c 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/lua/lua.c 2009-11-06 02:08:32 UTC (rev 526)
@@ -47,6 +47,7 @@
"Available options are:\n"
" -e stat execute string " LUA_QL("stat") "\n"
" -l name require library " LUA_QL("name") "\n"
+ " -m limit set memory limit. (units are in Kbytes)\n"
" -i enter interactive mode after executing " LUA_QL("script") "\n"
" -v show version information\n"
" -- stop handling options\n"
@@ -280,6 +281,7 @@
break;
case 'e':
*pe = 1; /* go through */
+ case 'm': /* go through */
case 'l':
if (argv[i][2] == '\0') {
i++;
@@ -307,6 +309,15 @@
return 1;
break;
}
+ case 'm': {
+ const char *limit = argv[i] + 2;
+ int memlimit=0;
+ if (*limit == '\0') limit = argv[++i];
+ lua_assert(limit != NULL);
+ memlimit = atoi(limit);
+ lua_gc(L, LUA_GCSETMEMLIMIT, memlimit);
+ break;
+ }
case 'l': {
const char *filename = argv[i] + 2;
if (*filename == '\0') filename = argv[++i];
Modified: branches/eagle_mmc/src/lua/lua.h
===================================================================
--- branches/eagle_mmc/src/lua/lua.h 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/lua/lua.h 2009-11-06 02:08:32 UTC (rev 526)
@@ -228,6 +228,8 @@
#define LUA_GCSTEP 5
#define LUA_GCSETPAUSE 6
#define LUA_GCSETSTEPMUL 7
+#define LUA_GCSETMEMLIMIT 8
+#define LUA_GCGETMEMLIMIT 9
LUA_API int (lua_gc) (lua_State *L, int what, int data);
Modified: branches/eagle_mmc/src/lua/luaconf.h
===================================================================
--- branches/eagle_mmc/src/lua/luaconf.h 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/lua/luaconf.h 2009-11-06 02:08:32 UTC (rev 526)
@@ -490,7 +490,7 @@
@@ LUAI_MAXVARS is the maximum number of local variables per function
@* (must be smaller than 250).
*/
-#define LUAI_MAXVARS 25
+#define LUAI_MAXVARS 50
/*
@@ -827,7 +827,7 @@
** without modifying the main part of the file.
*/
-#ifndef LUA_CROSS_COMPILER
+#if !defined(LUA_CROSS_COMPILER) || defined(_WIN32)
typedef short int16_t;
typedef long int32_t;
#endif
@@ -835,7 +835,7 @@
/* If you define the next macro you'll get the ability to set rotables as
metatables for tables/userdata/types (but the VM might run slower)
*/
-#ifndef LUA_CROSS_COMPILER
+#if (LUA_OPTIMIZE_MEMORY == 2) && !defined(LUA_CROSS_COMPILER)
#define LUA_META_ROTABLES
#endif
Modified: branches/eagle_mmc/src/lua/lvm.c
===================================================================
--- branches/eagle_mmc/src/lua/lvm.c 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/lua/lvm.c 2009-11-06 02:08:32 UTC (rev 526)
@@ -319,6 +319,7 @@
if (l >= MAX_SIZET - tl) luaG_runerror(L, "string length overflow");
tl += l;
}
+ G(L)->buff.n = tl;
buffer = luaZ_openspace(L, &G(L)->buff, tl);
tl = 0;
for (i=n; i>0; i--) { /* concat all strings */
@@ -327,6 +328,7 @@
tl += l;
}
setsvalue2s(L, top-n, luaS_newlstr(L, buffer, tl));
+ luaZ_resetbuffer(&G(L)->buff);
}
total -= n-1; /* got `n' strings to create 1 new */
last -= n-1;
@@ -481,7 +483,9 @@
case OP_NEWTABLE: {
int b = GETARG_B(i);
int c = GETARG_C(i);
- sethvalue(L, ra, luaH_new(L, luaO_fb2int(b), luaO_fb2int(c)));
+ Table *h;
+ Protect(h = luaH_new(L, luaO_fb2int(b), luaO_fb2int(c)));
+ sethvalue(L, RA(i), h);
Protect(luaC_checkGC(L));
continue;
}
@@ -748,6 +752,7 @@
p = cl->p->p[GETARG_Bx(i)];
nup = p->nups;
ncl = luaF_newLclosure(L, nup, cl->env);
+ setclvalue(L, ra, ncl);
ncl->l.p = p;
for (j=0; j<nup; j++, pc++) {
if (GET_OPCODE(*pc) == OP_GETUPVAL)
@@ -757,7 +762,6 @@
ncl->l.upvals[j] = luaF_findupval(L, base + GETARG_B(*pc));
}
}
- setclvalue(L, ra, ncl);
Protect(luaC_checkGC(L));
continue;
}
Modified: branches/eagle_mmc/src/luarpc_posix_serial.c
===================================================================
--- branches/eagle_mmc/src/luarpc_posix_serial.c 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/luarpc_posix_serial.c 2009-11-06 02:08:32 UTC (rev 526)
@@ -20,6 +20,9 @@
#include "luarpc_rpc.h"
+void transport_open( Transport *tpt, const char *path );
+
+
#ifdef LUARPC_ENABLE_SERIAL
/* Setup Transport */
Modified: branches/eagle_mmc/src/main.c
===================================================================
--- branches/eagle_mmc/src/main.c 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/main.c 2009-11-06 02:08:32 UTC (rev 526)
@@ -8,6 +8,8 @@
#include "xmodem.h"
#include "shell.h"
#include "lua.h"
+#include "lauxlib.h"
+#include "lualib.h"
#include "term.h"
#include "platform_conf.h"
#ifdef ELUA_SIMULATOR
@@ -28,6 +30,16 @@
extern char etext[];
+
+void boot_remote( void )
+{
+ lua_State *L = lua_open();
+ luaL_openlibs(L); /* open libraries */
+ lua_getglobal( L, "rpc" );
+ lua_getfield( L, -1, "server" );
+ lua_pcall( L, 0, 0, 0 );
+}
+
// ****************************************************************************
// Program entry point
@@ -51,7 +63,6 @@
// Register the ROM filesystem
dm_register( romfs_init() );
-#ifdef FS_AUTORUN
// Autorun: if "autorun.lua" is found in the file system, run it first
if( ( fp = fopen( FS_AUTORUN, "r" ) ) != NULL )
{
@@ -59,8 +70,11 @@
char* lua_argv[] = { "lua", FS_AUTORUN, NULL };
lua_main( 2, lua_argv );
}
-#endif
-
+
+#ifdef ELUA_BOOT_REMOTE
+ boot_remote();
+#else
+
// Run the shell
if( shell_init() == 0 )
{
@@ -71,6 +85,7 @@
}
else
shell_start();
+#endif // #ifdef ELUA_BOOT_REMOTE
#ifdef ELUA_SIMULATOR
hostif_exit(0);
@@ -79,4 +94,3 @@
while( 1 );
#endif
}
-
Modified: branches/eagle_mmc/src/modules/adc.c
===================================================================
--- branches/eagle_mmc/src/modules/adc.c 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/modules/adc.c 2009-11-06 02:08:32 UTC (rev 526)
@@ -193,7 +193,7 @@
static int adc_insertsamples( lua_State* L )
{
unsigned id, i, startidx;
- u16 bcnt, count, zcount;
+ u16 bcnt, count;
id = luaL_checkinteger( L, 1 );
MOD_CHECK_ID( adc, id );
Modified: branches/eagle_mmc/src/modules/auxmods.h
===================================================================
--- branches/eagle_mmc/src/modules/auxmods.h 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/modules/auxmods.h 2009-11-06 02:08:32 UTC (rev 526)
@@ -48,6 +48,9 @@
#define AUXLIB_LUARPC "rpc"
LUALIB_API int ( luaopen_luarpc )( lua_State *L );
+#define AUXLIB_BITARRAY "bitarray"
+LUALIB_API int ( luaopen_bitarray )( lua_State *L );
+
// Helper macros
#define MOD_CHECK_ID( mod, id )\
Added: branches/eagle_mmc/src/modules/bitarray.c
===================================================================
--- branches/eagle_mmc/src/modules/bitarray.c 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/modules/bitarray.c 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,333 @@
+ // Module that implements a fixed size bit array
+
+#include "lua.h"
+#include "lualib.h"
+#include "lauxlib.h"
+#include "platform.h"
+#include "auxmods.h"
+#include "lrotable.h"
+#include <string.h>
+
+#define META_NAME "eLua.bitarray"
+#define bitarray_check( L ) ( bitarray_t* )luaL_checkudata( L, 1, META_NAME )
+#define ROUND_SIZE(s) ( ( ( s ) >> 3 ) + ( ( s ) & 7 ? 1 : 0 ) )
+
+// Unpack modes
+enum
+{
+ BITARRAY_UNPACK_RAW = 0,
+ BITARRAY_UNPACK_SEQ
+};
+
+// Structure that describes our array
+typedef struct
+{
+ u32 capacity;
+ u8 elsize;
+ u8 values[ 1 ];
+} bitarray_t;
+
+// Index shift values/masks
+static const u8 bitarray_index_shift[] = { 0, 3, 2, 0, 1 };
+static const u8 bitarray_index_mask[] = { 0, 0x01, 0x03, 0, 0x0F };
+
+// Lua: array = bitarray.new( capacity, [element_size_bits], [fill] ), or
+// array = bitarray.new( "string", [element_size_bits] ), or
+// array = bitarray.new( lua_array, [element_size_bits] )
+static int bitarray_new( lua_State *L )
+{
+ u32 total, capacity;
+ u8 elsize, fill = 0, fromarray = 0;
+ const char *buf = NULL;
+ bitarray_t *pa;
+ size_t temp;
+
+ if( lua_isnumber( L, 1 ) )
+ {
+ // capacity, [element_size_bits], [fill]
+ capacity = luaL_checkinteger( L, 1 );
+ if( lua_isnumber( L, 2 ) )
+ elsize = luaL_checkinteger( L, 2 );
+ else
+ elsize = 8;
+ if( lua_isnumber( L, 3 ) )
+ fill = luaL_checkinteger( L, 3 );
+ }
+ else if( lua_isstring( L, 1 ) || lua_istable( L, 1 ) || lua_isrotable( L, 1 ) )
+ {
+ // string, [element_size_bits] OR (ro)table, [element_size_bits]
+ if( lua_isstring( L, 1 ) )
+ buf = lua_tolstring( L, 1, &temp );
+ else
+ {
+ temp = lua_objlen( L, 1 );
+ fromarray = 1;
+ }
+ if( lua_isnumber( L, 2 ) )
+ elsize = luaL_checkinteger( L, 2 );
+ else
+ elsize = 8;
+ if( ( temp << 3 ) % elsize )
+ return luaL_error( L, "length is not a multiple of element size." );
+ capacity = ( temp << 3 ) / elsize;
+ }
+ else
+ return luaL_error( L, "invalid arguments." );
+
+ if( elsize <= 0 || ( elsize > 32 ) || ( elsize & ( elsize - 1 ) ) )
+ return luaL_error( L, "invalid element size." );
+ total = ROUND_SIZE( capacity * elsize );
+ if( total <= 0 )
+ return luaL_error( L, "invalid arguments.");
+ pa = ( bitarray_t* )lua_newuserdata( L, sizeof( bitarray_t ) + total - 1 );
+ pa->capacity = capacity;
+ pa->elsize = elsize;
+
+ if( buf )
+ memcpy( pa->values, buf, temp );
+ else if( fromarray )
+ {
+ for( total = 1; total <= temp; total ++ )
+ {
+ lua_rawgeti( L, 1, total );
+ pa->values[ total - 1 ] = lua_tointeger( L, -1 );
+ lua_pop( L, 1 );
+ }
+ }
+ else
+ memset( pa->values, fill, total );
+ luaL_getmetatable( L, META_NAME );
+ lua_setmetatable( L, -2 );
+ return 1;
+}
+
+// Helper: get the value at the given index
+static u32 bitarray_getval( bitarray_t *pa, u32 idx )
+{
+ u32 shift, val = 0;
+ u8 rest, mask;
+
+ idx --;
+ if( pa->elsize < 8 ) // sub-byte elements
+ {
+ shift = idx >> bitarray_index_shift[ pa->elsize ];
+ mask = 1 << bitarray_index_shift[ pa->elsize ];
+ rest = idx & ( mask - 1 );
+ val = pa->values[ shift ];
+ val = ( val >> ( ( mask - 1 - rest ) * pa->elsize ) ) & bitarray_index_mask[ pa->elsize ];
+ }
+ else // one byte or more elements
+ switch( pa->elsize )
+ {
+ case 8:
+ val = pa->values[ idx ];
+ break;
+
+ case 16:
+ val = *( ( u16* )pa->values + idx );
+ break;
+
+ case 32:
+ val = *( ( u32* )pa->values + idx );
+ break;
+ }
+ return val;
+}
+
+// Lua: value = array[ idx ]
+static int bitarray_get( lua_State *L )
+{
+ bitarray_t *pa;
+ u32 idx;
+
+ pa = bitarray_check( L );
+ idx = luaL_checkinteger( L, 2 );
+ if( ( idx <= 0 ) || ( idx > pa->capacity ) )
+ return luaL_error( L, "invalid index." );
+ lua_pushinteger( L, bitarray_getval( pa, idx ) );
+ return 1;
+}
+
+// Lua: array[ key ] = value
+static int bitarray_set( lua_State *L )
+{
+ bitarray_t *pa;
+ u32 idx, shift, newval, val = 0;
+ u8 rest, mask;
+
+ pa = bitarray_check( L );
+ idx = luaL_checkinteger( L, 2 );
+ newval = luaL_checkinteger( L, 3 );
+ if( ( idx <= 0 ) || ( idx > pa->capacity ) )
+ return luaL_error( L, "invalid index." );
+ idx --;
+ if( pa->elsize < 8 ) // sub-byte elements
+ {
+ shift = idx >> bitarray_index_shift[ pa->elsize ];
+ mask = 1 << bitarray_index_shift[ pa->elsize ];
+ rest = idx & ( mask - 1 );
+ val = pa->values[ shift ];
+ val &= ~( bitarray_index_mask[ pa->elsize ] << ( ( mask - 1 - rest ) * pa->elsize ) );
+ val |= newval << ( ( mask - 1 - rest ) * pa->elsize );
+ pa->values[ shift ] = val;
+ }
+ else // one byte or more elements
+ switch( pa->elsize )
+ {
+ case 8:
+ pa->values[ idx ] = val;;
+ break;
+
+ case 16:
+ *( ( u16* )pa->values + idx ) = val;
+ break;
+
+ case 32:
+ *( ( u32* )pa->values + idx ) = val;
+ break;
+ }
+ return 0;
+}
+
+// Lua : size = #array
+static int bitarray_len( lua_State *L )
+{
+ bitarray_t *pa;
+
+ pa = bitarray_check( L );
+ lua_pushinteger( L, pa->capacity );
+ return 1;
+}
+
+// Lua iterator
+static int bitarray_iter( lua_State *L )
+{
+ bitarray_t *pa;
+ u32 idx;
+
+ pa = bitarray_check( L );
+ idx = luaL_checkinteger( L, 2 ) + 1;
+ if( idx <= pa->capacity )
+ {
+ lua_pushinteger( L, idx );
+ lua_pushinteger( L, bitarray_getval( pa, idx ) );
+ return 2;
+ }
+ else
+ return 0;
+}
+
+// Lua iterator "factory"
+static int bitarray_pairs( lua_State *L )
+{
+#if LUA_OPTIMIZE_MEMORY > 0
+ lua_pushlightfunction( L, bitarray_iter );
+#else
+ lua_pushcclosure( L, bitarray_iter, 0 );
+#endif
+ lua_pushvalue( L, 1 );
+ lua_pushinteger ( L, 0 );
+ return 3;
+}
+
+// Lua: string = bitarray.tostring( array, ["raw"|"seq"] )
+static int bitarray_tostring( lua_State *L )
+{
+ luaL_Buffer b;
+ bitarray_t *pa;
+ u32 idx;
+ u8 mode = BITARRAY_UNPACK_SEQ;
+ const char *ptextmode;
+
+ pa = bitarray_check( L );
+ if( lua_isstring( L, 2 ) )
+ {
+ ptextmode = lua_tostring( L, 2 );
+ if( !strcmp( ptextmode, "raw" ) )
+ mode = BITARRAY_UNPACK_RAW;
+ else if( !strcmp( ptextmode, "seq" ) )
+ mode = BITARRAY_UNPACK_SEQ;
+ else
+ return luaL_error( L, "invalid mode string." );
+ }
+ if( ( mode == BITARRAY_UNPACK_SEQ ) && ( pa->elsize > 8 ) )
+ return luaL_error( L, "element size too large." );
+ luaL_buffinit( L, &b );
+ if( mode == BITARRAY_UNPACK_SEQ )
+ for( idx = 1; idx <= pa->capacity; idx ++ )
+ luaL_addchar( &b, bitarray_getval( pa, idx ) );
+ else
+ luaL_addlstring( &b, ( char* )pa->values, ROUND_SIZE( pa->capacity * pa->elsize ) );
+ luaL_pushresult( &b );
+ return 1;
+}
+
+// Lua: table = bitarray.totable( array, ["raw"|"seq"] )
+static int bitarray_totable( lua_State *L )
+{
+ bitarray_t *pa;
+ u32 idx;
+ u8 mode = BITARRAY_UNPACK_SEQ;
+ const char *ptextmode;
+
+ pa = bitarray_check( L );
+ if( lua_isstring( L, 2 ) )
+ {
+ ptextmode = lua_tostring( L, 2 );
+ if( !strcmp( ptextmode, "raw" ) )
+ mode = BITARRAY_UNPACK_RAW;
+ else if( !strcmp( ptextmode, "seq" ) )
+ mode = BITARRAY_UNPACK_SEQ;
+ else
+ return luaL_error( L, "invalid mode string." );
+ }
+ if( ( mode == BITARRAY_UNPACK_SEQ ) && ( pa->elsize > 8 ) )
+ return luaL_error( L, "element size too large." );
+ lua_newtable( L );
+ if( mode == BITARRAY_UNPACK_SEQ )
+ for( idx = 1; idx <= pa->capacity; idx ++ )
+ {
+ lua_pushinteger( L, bitarray_getval( pa, idx ) );
+ lua_rawseti( L, -2, idx );
+ }
+ else
+ for( idx = 0; idx < ROUND_SIZE( pa->capacity * pa->elsize ); idx ++ )
+ {
+ lua_pushinteger( L, pa->values[ idx ] );
+ lua_rawseti( L, -2, idx + 1 );
+ }
+ return 1;
+}
+
+// Module function map
+#define MIN_OPT_LEVEL 2
+#include "lrodefs.h"
+const LUA_REG_TYPE bitarray_map[] =
+{
+ { LSTRKEY( "new" ), LFUNCVAL( bitarray_new ) },
+ { LSTRKEY( "pairs" ), LFUNCVAL( bitarray_pairs ) },
+ { LSTRKEY( "tostring" ), LFUNCVAL( bitarray_tostring ) },
+ { LSTRKEY( "totable" ), LFUNCVAL( bitarray_totable ) },
+ { LNILKEY, LNILVAL }
+};
+
+static const LUA_REG_TYPE bitarray_mt_map[] =
+{
+ { LSTRKEY( "__index" ), LFUNCVAL( bitarray_get ) },
+ { LSTRKEY( "__newindex" ), LFUNCVAL( bitarray_set ) },
+ { LSTRKEY( "__len" ), LFUNCVAL( bitarray_len ) },
+ { LNILKEY, LNILVAL }
+};
+
+LUALIB_API int luaopen_bitarray( lua_State* L )
+{
+#if LUA_OPTIMIZE_MEMORY > 0
+ luaL_rometatable( L, META_NAME, ( void* )bitarray_mt_map );
+ return 0;
+#else // #if LUA_OPTIMIZE_MEMORY > 0
+ luaL_newmetatable( L, META_NAME );
+ luaL_register( L, NULL, bitarray_mt_map );
+ luaL_register( L, AUXLIB_BITARRAY, bitarray_map );
+ return 1;
+#endif // #if LUA_OPTIMIZE_MEMORY > 0
+}
Modified: branches/eagle_mmc/src/modules/luarpc.c
===================================================================
--- branches/eagle_mmc/src/modules/luarpc.c 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/modules/luarpc.c 2009-11-06 02:08:32 UTC (rev 526)
@@ -5,6 +5,14 @@
* see the file LICENSE that comes with this distribution. *
*****************************************************************************/
+// Modifications by James Snyder - jbsnyder at fanplastic.org
+// - more generic backend interface to accomodate different link types
+// - integration with eLua (including support for rotables)
+// - extensions of remote global table as local table metaphor
+// - methods to allow remote assignment, getting remote values
+// - accessing and calling types nested multiple levels deep on tables now works
+// - port from Lua 4.x to 5.x
+
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
@@ -18,7 +26,10 @@
#include "platform.h"
#include "platform_conf.h"
#endif
+
+#ifdef LUA_OPTIMIZE_MEMORY
#include "lrotable.h"
+#endif
#include "luarpc_rpc.h"
@@ -27,25 +38,29 @@
/* Support for Compiling with rotables */
#ifdef LUA_OPTIMIZE_MEMORY
-#define LUA_ISCALLABLE(state, idx) ( lua_isfunction( state, idx ) || lua_islightfunction( state, idx ) )
+#define LUA_ISCALLABLE( state, idx ) ( lua_isfunction( state, idx ) || lua_islightfunction( state, idx ) )
#else
-#define LUA_ISCALLABLE(state, idx) lua_isfunction( state, idx )
+#define LUA_ISCALLABLE( state, idx ) lua_isfunction( state, idx )
#endif
+/* Prototypes for Local Functions */
+LUALIB_API int luaopen_luarpc( lua_State *L );
+Handle *handle_create( lua_State *L );
+
+
struct exception_context the_exception_context[ 1 ];
-static void errorMessage (const char *msg, va_list ap)
+static void errorMessage( const char *msg, va_list ap )
{
- fflush (stdout);
- fflush (stderr);
- fprintf (stderr,"\nError: ");
- vfprintf (stderr,msg,ap);
- fprintf (stderr,"\n\n");
- fflush (stderr);
+ fflush( stdout );
+ fflush( stderr );
+ fprintf( stderr,"\nError: " );
+ vfprintf( stderr,msg,ap );
+ fprintf( stderr,"\n\n" );
+ fflush( stderr );
}
-
-DOGCC(static void panic (const char *msg, ...)
+DOGCC(static void panic( const char *msg, ... )
__attribute__ ((noreturn,unused));)
static void panic (const char *msg, ...)
{
@@ -56,7 +71,7 @@
}
-DOGCC(static void rpcdebug (const char *msg, ...)
+DOGCC(static void rpcdebug( const char *msg, ... )
__attribute__ ((noreturn,unused));)
static void rpcdebug (const char *msg, ...)
{
@@ -99,19 +114,17 @@
/* return a string representation of an error number */
-static const char * errorString (int n)
+static const char * errorString( int n )
{
switch (n) {
- case ERR_EOF: return "connection closed unexpectedly (\"end of file\")";
- case ERR_CLOSED: return "operation requested on a closed transport";
- case ERR_PROTOCOL: return "error in the received LuaRPC protocol";
- case ERR_COMMAND: return "undefined RPC command";
- case ERR_DATALINK: return "transmission error at data link level";
- case ERR_NODATA: return "no data received when attempting to read";
- case ERR_BADFNAME: return "function name is too long";
- case RPC_UNSUPPORTED_CMD: return "an unsupported action was requested";
- case ERR_HEADER: return "header exchanged failed";
- default: return transport_strerror (n);
+ case ERR_EOF: return "connection closed unexpectedly";
+ case ERR_CLOSED: return "operation requested on closed transport";
+ case ERR_PROTOCOL: return "error in the received protocol";
+ case ERR_COMMAND: return "undefined command";
+ case ERR_NODATA: return "no data received when attempting to read";
+ case ERR_HEADER: return "header exchanged failed";
+ case ERR_LONGFNAME: return "function name too long";
+ default: return transport_strerror( n );
}
}
@@ -156,14 +169,14 @@
transport_write_buffer( tpt, &x, 1 );
}
-static void swap_bytes( char *number, size_t numbersize )
+static void swap_bytes( uint8_t *number, size_t numbersize )
{
int i;
- for (i=0; i<numbersize/2; i++)
+ for ( i = 0 ; i < numbersize / 2 ; i ++ )
{
- char temp = number[i];
- number[i] = number[numbersize-1-i];
- number[numbersize-1-i] = temp;
+ uint8_t temp = number[ i ];
+ number[ i ] = number[ numbersize - 1 - i ];
+ number[ numbersize - 1 - i ] = temp;
}
}
@@ -180,7 +193,7 @@
TRANSPORT_VERIFY_OPEN;
transport_read_buffer ( tpt, ub.b, 4 );
if( tpt->net_little != tpt->loc_little )
- swap_bytes( (char *)ub.b, 4 );
+ swap_bytes( ( uint8_t * )ub.b, 4 );
return ub.i;
}
@@ -193,7 +206,7 @@
TRANSPORT_VERIFY_OPEN;
ub.i = ( uint32_t )x;
if( tpt->net_little != tpt->loc_little )
- swap_bytes( ( char * )ub.b, 4 );
+ swap_bytes( ( uint8_t * )ub.b, 4 );
transport_write_buffer( tpt, ub.b, 4 );
}
@@ -208,7 +221,7 @@
transport_read_buffer ( tpt, b, tpt->lnum_bytes );
if( tpt->net_little != tpt->loc_little )
- swap_bytes( ( char * )b, tpt->lnum_bytes );
+ swap_bytes( ( uint8_t * )b, tpt->lnum_bytes );
if( tpt->net_intnum != tpt->loc_intnum )
{
@@ -230,7 +243,7 @@
int64_t y = *( int64_t * )b;
x = ( lua_Number )y;
} break;
- default: lua_assert(0);
+ default: lua_assert( 0 );
}
}
else
@@ -241,7 +254,7 @@
/* write a lua number to the transport */
-static void transport_write_number (Transport *tpt, lua_Number x)
+static void transport_write_number( Transport *tpt, lua_Number x )
{
struct exception e;
TRANSPORT_VERIFY_OPEN;
@@ -252,25 +265,25 @@
{
case 1: {
int8_t y = ( int8_t )x;
- transport_write_buffer( tpt, ( char * )&y, 1 );
+ transport_write_buffer( tpt, ( u8 * )&y, 1 );
} break;
case 2: {
int16_t y = ( int16_t )x;
if( tpt->net_little != tpt->loc_little )
- swap_bytes( ( char * )&y, 2 );
- transport_write_buffer( tpt, ( char * )&y, 2 );
+ swap_bytes( ( uint8_t * )&y, 2 );
+ transport_write_buffer( tpt, ( u8 * )&y, 2 );
} break;
case 4: {
int32_t y = ( int32_t )x;
if( tpt->net_little != tpt->loc_little )
- swap_bytes( ( char * )&y, 4 );
- transport_write_buffer( tpt, (char *)&y, 4 );
+ swap_bytes( ( uint8_t * )&y, 4 );
+ transport_write_buffer( tpt,( u8 * )&y, 4 );
} break;
case 8: {
int64_t y = ( int64_t )x;
if( tpt->net_little != tpt->loc_little )
- swap_bytes( ( char * )&y, 8 );
- transport_write_buffer( tpt, (char *)&y, 8 );
+ swap_bytes( ( uint8_t * )&y, 8 );
+ transport_write_buffer( tpt, ( u8 * )&y, 8 );
} break;
default: lua_assert(0);
}
@@ -278,8 +291,8 @@
else
{
if( tpt->net_little != tpt->loc_little )
- swap_bytes( ( char * )&x, 8 );
- transport_write_buffer( tpt, ( char * )&x, 8 );
+ swap_bytes( ( uint8_t * )&x, 8 );
+ transport_write_buffer( tpt, ( u8 * )&x, 8 );
}
}
@@ -303,8 +316,8 @@
int n = lua_gettop( L ); /* number of arguments on stack */
if ( n != desired_n )
{
- char s[ 100 ]; /* @@@ can we cut this down? */
- sprintf( s, "must have %d argument%c", desired_n,
+ char s[ 30 ];
+ snprintf( s, 30, "must have %d arg%c", desired_n,
( desired_n == 1 ) ? '\0' : 's' );
my_lua_error( L, s );
}
@@ -439,15 +452,15 @@
break;
case LUA_TUSERDATA:
- my_lua_error( L, "can't pass user data to a remote function" );
+ my_lua_error( L, "userdata transmission unsupported" );
break;
case LUA_TTHREAD:
- my_lua_error( L, "can't pass threads to a remote function" );
+ my_lua_error( L, "thread transmission unsupported" );
break;
case LUA_TLIGHTUSERDATA:
- my_lua_error( L, "can't pass light user data to a remote function" );
+ my_lua_error( L, "light userdata transmission unsupported" );
break;
}
MYASSERT( lua_gettop( L ) == stack_at_start );
@@ -691,7 +704,6 @@
static int handle_index (lua_State *L)
{
const char *s;
- Helper *h;
MYASSERT( lua_gettop( L ) == 2 );
MYASSERT( lua_isuserdata( L, 1 ) && ismetatable_type( L, 1, "rpc.handle" ) );
@@ -700,9 +712,9 @@
my_lua_error( L, "can't index a handle with a non-string" );
s = lua_tostring( L, 2 );
if ( strlen( s ) > NUM_FUNCNAME_CHARS - 1 )
- my_lua_error( L, "function name is too long" );
+ my_lua_error( L, errorString( ERR_LONGFNAME ) );
- h = helper_create( L, ( Handle * )lua_touserdata( L, 1 ), s );
+ helper_create( L, ( Handle * )lua_touserdata( L, 1 ), s );
/* return the helper object */
return 1;
@@ -714,18 +726,17 @@
static int handle_newindex( lua_State *L )
{
const char *s;
- Helper *h;
MYASSERT( lua_gettop( L ) == 3 );
MYASSERT( lua_isuserdata( L, 1 ) && ismetatable_type( L, 1, "rpc.handle" ) );
if( lua_type( L, 2 ) != LUA_TSTRING )
- my_lua_error( L, "can't index a handle with a non-string" );
+ my_lua_error( L, "can't index handle with a non-string" );
s = lua_tostring( L, 2 );
if ( strlen( s ) > NUM_FUNCNAME_CHARS - 1 )
- my_lua_error( L, "function name is too long" );
+ my_lua_error( L, errorString( ERR_LONGFNAME ) );
- h = helper_create( L, ( Handle * )lua_touserdata( L, 1 ), "" );
+ helper_create( L, ( Handle * )lua_touserdata( L, 1 ), "" );
lua_replace(L, 1);
helper_newindex( L );
@@ -742,7 +753,7 @@
/* get length of name & make stack of helpers */
len = strlen( helper->funcname );
- if( helper->nparents > 0 )
+ if( helper->nparents > 0 ) // If helper has parents, build string to remote index
{
hstack = ( Helper ** )alloca( sizeof( Helper * ) * helper->nparents );
hstack[ helper->nparents - 1 ] = helper->parent;
@@ -753,18 +764,19 @@
hstack[ i - 1 ] = hstack[ i ]->parent;
len += strlen( hstack[ i ]->funcname ) + 1;
}
- }
-
- transport_write_u32( tpt, len );
- /* replay helper key names */
- if( helper->nparents > 0)
- {
+
+ transport_write_u32( tpt, len );
+
+ /* replay helper key names */
for( i = 0 ; i < helper->nparents ; i ++ )
{
transport_write_string( tpt, hstack[ i ]->funcname, strlen( hstack[ i ]->funcname ) );
transport_write_string( tpt, ".", 1 );
}
}
+ else // If helper has no parents, just use length of global
+ transport_write_u32( tpt, len );
+
transport_write_string( tpt, helper->funcname, strlen( helper->funcname ) );
}
@@ -792,10 +804,6 @@
Try
{
- int len;
- u8 cmdresp;
- /* write function name */
- len = strlen( helper->funcname );
helper_wait_ready( tpt, RPC_CMD_GET );
helper_remote_index( helper );
@@ -807,21 +815,15 @@
{
switch( e.type )
{
- case fatal:
- if ( e.errnum == ERR_CLOSED )
- my_lua_error( L, "can't refer to a remote function after the handle has been closed" );
deal_with_error( L, helper->handle, errorString( e.errnum ) );
- transport_close( tpt );
- break;
case nonfatal:
- deal_with_error( L, helper->handle, errorString( e.errnum ) );
lua_pushnil( L );
return 1;
break;
- default:
- deal_with_error( L, helper->handle, errorString( e.errnum ) );
+ case fatal:
transport_close( tpt );
break;
+ default: lua_assert( 0 );
}
}
return freturn;
@@ -884,7 +886,6 @@
{
int i,n;
u32 nret,ret_code;
- u8 cmdresp;
/* write function name */
helper_wait_ready( tpt, RPC_CMD_CALL );
@@ -899,16 +900,16 @@
write_variable( tpt, L, i );
/* if we're in async mode, we're done */
- if ( h->handle->async )
+ /*if ( h->handle->async )
{
h->handle->read_reply_count++;
freturn = 0;
- }
+ }*/
/* read return code */
ret_code = transport_read_u8( tpt );
- if ( ret_code== 0 )
+ if ( ret_code == 0 )
{
/* read return arguments */
nret = transport_read_u32( tpt );
@@ -921,7 +922,7 @@
else
{
/* read error and handle it */
- u32 code = transport_read_u32( tpt );
+ transport_read_u32( tpt ); // read code (not being used here)
u32 len = transport_read_u32( tpt );
char *err_string = ( char * )alloca( len + 1 );
transport_read_string( tpt, err_string, len );
@@ -935,21 +936,15 @@
{
switch( e.type )
{
- case fatal:
- if ( e.errnum == ERR_CLOSED )
- my_lua_error( L, "can't refer to a remote function after the handle has been closed" );
deal_with_error( L, h->handle, errorString( e.errnum ) );
- transport_close( tpt );
- break;
case nonfatal:
- deal_with_error( L, h->handle, errorString( e.errnum ) );
lua_pushnil( L );
return 1;
break;
- default:
- deal_with_error( L, h->handle, errorString( e.errnum ) );
+ case fatal:
transport_close( tpt );
break;
+ default: lua_assert( 0 );
}
}
}
@@ -971,12 +966,8 @@
tpt = &h->handle->tpt;
Try
- {
- int len;
- u8 cmdresp;
-
+ {
/* write function name */
- len = strlen( h->funcname );
helper_wait_ready( tpt, RPC_CMD_NEWINDEX );
helper_remote_index( h );
@@ -987,7 +978,7 @@
if( ret_code != 0 )
{
/* read error and handle it */
- u32 code = transport_read_u32( tpt );
+ transport_read_u32( tpt ); // Read code (not using here)
u32 len = transport_read_u32( tpt );
char *err_string = ( char * )alloca( len + 1 );
transport_read_string( tpt, err_string, len );
@@ -1002,21 +993,15 @@
{
switch( e.type )
{
- case fatal:
- if ( e.errnum == ERR_CLOSED )
- my_lua_error( L, "can't refer to a remote function after the handle has been closed" );
deal_with_error( L, h->handle, errorString( e.errnum ) );
- transport_close( tpt );
- break;
case nonfatal:
- deal_with_error( L, h->handle, errorString( e.errnum ) );
lua_pushnil( L );
return 1;
break;
- default:
- deal_with_error( L, h->handle, errorString( e.errnum ) );
+ case fatal:
transport_close( tpt );
break;
+ default: lua_assert( 0 );
}
}
return freturn;
@@ -1039,18 +1024,17 @@
static int helper_index (lua_State *L)
{
const char *s;
- Helper *h;
MYASSERT( lua_gettop( L ) == 2 );
MYASSERT( lua_isuserdata( L, 1 ) && ismetatable_type( L, 1, "rpc.helper" ) );
if( lua_type( L, 2 ) != LUA_TSTRING )
- my_lua_error( L, "can't index a handle with a non-string" );
+ my_lua_error( L, "can't index handle with non-string" );
s = lua_tostring( L, 2 );
if ( strlen( s ) > NUM_FUNCNAME_CHARS - 1 )
- my_lua_error( L, "function name is too long" );
+ my_lua_error( L, errorString( ERR_LONGFNAME ) );
- h = helper_append( L, ( Helper * )lua_touserdata( L, 1 ), s );
+ helper_append( L, ( Helper * )lua_touserdata( L, 1 ), s );
return 1;
}
@@ -1139,7 +1123,7 @@
}
}
- my_lua_error(L,"argument must be an RPC handle");
+ my_lua_error(L,"arg must be handle");
return 0;
}
@@ -1155,7 +1139,7 @@
check_num_args( L, 2 );
if ( !lua_isuserdata( L, 1 ) || !ismetatable_type( L, 1, "rpc.handle" ) )
- my_lua_error( L, "first argument must be an RPC client handle" );
+ my_lua_error( L, "first arg must be client handle" );
handle = ( Handle * )lua_touserdata( L, 1 );
@@ -1266,7 +1250,7 @@
/* get function */
/* @@@ perhaps handle more like variables instead of using a long string? */
- /* @@@ also strtok is not thread safe */
+ /* @@@ also strtok is not reentrant, strtok_r would be, if needed */
token = strtok( funcname, "." );
lua_getglobal( L, token );
token = strtok( NULL, "." );
@@ -1370,7 +1354,7 @@
handle = rpc_listen_helper( L );
if ( handle == 0 )
- printf( "Bad Handle!" );
+ printf( "bad Handle" );
return 1;
}
@@ -1383,7 +1367,7 @@
check_num_args( L, 1 );
if ( !( lua_isuserdata( L, 1 ) && ismetatable_type( L, 1, "rpc.server_handle" ) ) )
- my_lua_error( L, "argument must be an RPC server handle" );
+ my_lua_error( L, "arg must be server handle" );
handle = ( ServerHandle * )lua_touserdata( L, 1 );
@@ -1522,7 +1506,7 @@
check_num_args( L, 1 );
if ( ! ( lua_isuserdata( L, 1 ) && ismetatable_type( L, 1, "rpc.server_handle" ) ) )
- my_lua_error( L, "argument must be an RPC server handle" );
+ my_lua_error( L, "arg must be server handle" );
handle = ( ServerHandle * )lua_touserdata( L, 1 );
@@ -1572,7 +1556,7 @@
else if ( lua_isnil( L, 1 ) )
{ ;; }
else
- my_lua_error( L, "bad arguments" );
+ my_lua_error( L, "bad args" );
/* @@@ add option for handle */
/* Handle *h = (Handle*) lua_touserdata (L,1); */
@@ -1584,8 +1568,6 @@
/****************************************************************************/
/* register RPC functions */
-
-
#ifndef LUARPC_STANDALONE
#define MIN_OPT_LEVEL 2
Modified: branches/eagle_mmc/src/modules/net.c
===================================================================
--- branches/eagle_mmc/src/modules/net.c 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/modules/net.c 2009-11-06 02:08:32 UTC (rev 526)
@@ -201,6 +201,11 @@
#if LUA_OPTIMIZE_MEMORY > 0
{ LSTRKEY( "SOCK_STREAM" ), LNUMVAL( ELUA_NET_SOCK_STREAM ) },
{ LSTRKEY( "SOCK_DGRAM" ), LNUMVAL( ELUA_NET_SOCK_DGRAM ) },
+ { LSTRKEY( "ERR_OK" ), LNUMVAL( ELUA_NET_ERR_OK ) },
+ { LSTRKEY( "ERR_TIMEOUT" ), LNUMVAL( ELUA_NET_ERR_TIMEDOUT ) },
+ { LSTRKEY( "ERR_CLOSED" ), LNUMVAL( ELUA_NET_ERR_CLOSED ) },
+ { LSTRKEY( "ERR_ABORTED" ), LNUMVAL( ELUA_NET_ERR_ABORTED ) },
+ { LSTRKEY( "ERR_OVERFLOW" ), LNUMVAL( ELUA_NET_ERR_OVERFLOW ) },
#endif
{ LNILKEY, LNILVAL }
};
@@ -213,10 +218,13 @@
luaL_register( L, AUXLIB_NET, net_map );
// Module constants
- lua_pushnumber( L, ELUA_NET_SOCK_STREAM );
- lua_setfield( L, -2, "SOCK_STREAM" );
- lua_pushnumber( L, ELUA_NET_SOCK_DGRAM );
- lua_setfield( L, -2, "SOCK_DGRAM" );
+ MOD_REG_NUMBER( L, "SOCK_STREAM", ELUA_NET_SOCK_STREAM );
+ MOD_REG_NUMBER( L, "SOCK_DGRAM", ELUA_NET_SOCK_DGRAM );
+ MOD_REG_NUMBER( L, "ERR_OK", ELUA_NET_ERR_OK );
+ MOD_REG_NUMBER( L, "ERR_TIMEDOUT", ELUA_NET_ERR_TIMEDOUT );
+ MOD_REG_NUMBER( L, "ERR_CLOSED", ELUA_NET_ERR_CLOSED );
+ MOD_REG_NUMBER( L, "ERR_ABORTED", ELUA_NET_ERR_ABORTED );
+ MOD_REG_NUMBER( L, "ERR_OVERFLOW", ELUA_NET_ERR_OVERFLOW );
return 1;
#endif // #if LUA_OPTIMIZE_MEMORY > 0
@@ -230,3 +238,4 @@
}
#endif // #ifdef BUILD_UIP
+
Modified: branches/eagle_mmc/src/modules/spi.c
===================================================================
--- branches/eagle_mmc/src/modules/spi.c 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/modules/spi.c 2009-11-06 02:08:32 UTC (rev 526)
@@ -7,8 +7,8 @@
#include "auxmods.h"
#include "lrotable.h"
-// Lua: select( id )
-static int spi_select( lua_State* L )
+// Lua: sson( id )
+static int spi_sson( lua_State* L )
{
unsigned id;
@@ -18,8 +18,8 @@
return 0;
}
-// Lua: unselect( id )
-static int spi_unselect( lua_State* L )
+// Lua: ssoff( id )
+static int spi_ssoff( lua_State* L )
{
unsigned id;
@@ -29,7 +29,7 @@
return 0;
}
-// Lua: setup( id, MASTER/SLAVE, clock, cpol, cpha, databits )
+// Lua: clock = setup( id, MASTER/SLAVE, clock, cpol, cpha, databits )
static int spi_setup( lua_State* L )
{
unsigned id, cpol, cpha, is_master, databits;
@@ -37,59 +37,84 @@
id = luaL_checkinteger( L, 1 );
MOD_CHECK_ID( spi, id );
- is_master = luaL_checkinteger( L, 2 );
+ is_master = luaL_checkinteger( L, 2 ) == PLATFORM_SPI_MASTER;
+ if( !is_master )
+ return luaL_error( L, "invalid type (only spi.MASTER is supported)" );
clock = luaL_checkinteger( L, 3 );
cpol = luaL_checkinteger( L, 4 );
+ if( ( cpol != 0 ) && ( cpol != 1 ) )
+ return luaL_error( L, "invalid clock polarity." );
cpha = luaL_checkinteger( L, 5 );
+ if( ( cpha != 0 ) && ( cpha != 1 ) )
+ return luaL_error( L, "invalid clock phase." );
databits = luaL_checkinteger( L, 6 );
res = platform_spi_setup( id, is_master, clock, cpol, cpha, databits );
lua_pushinteger( L, res );
return 1;
}
-// Lua: send( id, out1, out2, ... )
-static int spi_send( lua_State* L )
+// Helper function: generic write/readwrite
+static int spi_rw_helper( lua_State *L, int withread )
{
spi_data_type value;
+ const char *sval;
int total = lua_gettop( L ), i, id;
+ size_t len, residx = 1;
id = luaL_checkinteger( L, 1 );
MOD_CHECK_ID( spi, id );
+ if( withread )
+ lua_newtable( L );
for( i = 2; i <= total; i ++ )
{
- value = luaL_checkinteger( L, i );
- platform_spi_send_recv( id, value );
+ if( lua_isnumber( L, i ) )
+ {
+ value = platform_spi_send_recv( id, lua_tointeger( L, i ) );
+ if( withread )
+ {
+ lua_pushnumber( L, value );
+ lua_rawseti( L, -2, residx ++ );
+ }
+ }
+ else if( lua_isstring( L, i ) )
+ {
+ sval = lua_tolstring( L, i, &len );
+ for( i = 0; i < len; i ++ )
+ {
+ value = platform_spi_send_recv( id, sval[ i ] );
+ if( withread )
+ {
+ lua_pushnumber( L, value );
+ lua_rawseti( L, -2, residx ++ );
+ }
+ }
+ }
}
- return 0;
+ return withread ? 1 : 0;
}
-// Lua: in1, in2, ... = send_recv( id, out1, out2, ... )
-static int spi_send_recv( lua_State* L )
+// Lua: write( id, out1, out2, ... )
+static int spi_write( lua_State* L )
{
- spi_data_type value;
- int total = lua_gettop( L ), i, id;
-
- id = luaL_checkinteger( L, 1 );
- MOD_CHECK_ID( spi, id );
- for( i = 2; i <= total; i ++ )
- {
- value = luaL_checkinteger( L, i );
- value = platform_spi_send_recv( id, value );
- lua_pushinteger( L, value );
- }
- return total - 1;
+ return spi_rw_helper( L, 0 );
}
+// Lua: restable = readwrite( id, out1, out2, ... )
+static int spi_readwrite( lua_State* L )
+{
+ return spi_rw_helper( L, 1 );
+}
+
// Module function map
#define MIN_OPT_LEVEL 2
#include "lrodefs.h"
const LUA_REG_TYPE spi_map[] =
{
{ LSTRKEY( "setup" ), LFUNCVAL( spi_setup ) },
- { LSTRKEY( "select" ), LFUNCVAL( spi_select ) },
- { LSTRKEY( "unselect" ), LFUNCVAL( spi_unselect ) },
- { LSTRKEY( "send" ), LFUNCVAL( spi_send ) },
- { LSTRKEY( "send_recv" ), LFUNCVAL( spi_send_recv ) },
+ { LSTRKEY( "sson" ), LFUNCVAL( spi_sson ) },
+ { LSTRKEY( "ssoff" ), LFUNCVAL( spi_ssoff ) },
+ { LSTRKEY( "write" ), LFUNCVAL( spi_write ) },
+ { LSTRKEY( "readwrite" ), LFUNCVAL( spi_readwrite ) },
#if LUA_OPTIMIZE_MEMORY > 0
{ LSTRKEY( "MASTER" ), LNUMVAL( PLATFORM_SPI_MASTER ) } ,
{ LSTRKEY( "SLAVE" ), LNUMVAL( PLATFORM_SPI_SLAVE ) },
@@ -105,10 +130,8 @@
luaL_register( L, AUXLIB_SPI, spi_map );
// Add the MASTER and SLAVE constants (for spi.setup)
- lua_pushnumber( L, PLATFORM_SPI_MASTER );
- lua_setfield( L, -2, "MASTER" );
- lua_pushnumber( L, PLATFORM_SPI_SLAVE );
- lua_setfield( L, -2, "SLAVE" );
+ MOD_REG_NUMBER( L, "MASTER", PLATFORM_SPI_MASTER );
+ MOD_REG_NUMBER( L, "SLAVE", PLATFORM_SPI_SLAVE );
return 1;
#endif // #if LUA_OPTIMIZE_MEMORY > 0
Modified: branches/eagle_mmc/src/modules/tmr.c
===================================================================
--- branches/eagle_mmc/src/modules/tmr.c 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/modules/tmr.c 2009-11-06 02:08:32 UTC (rev 526)
@@ -51,8 +51,8 @@
return tmrh_timer_op( L, PLATFORM_TIMER_OP_START );
}
-// Lua: time_us = diff( id, end, start )
-static int tmr_diff( lua_State* L )
+// Lua: time_us = gettimediff( id, end, start )
+static int tmr_gettimediff( lua_State* L )
{
timer_data_type end, start;
u32 res;
@@ -60,15 +60,15 @@
id = luaL_checkinteger( L, 1 );
MOD_CHECK_ID( timer, id );
- end = luaL_checkinteger( L, 2 );
- start = luaL_checkinteger( L, 3 );
+ end = ( timer_data_type )luaL_checkinteger( L, 2 );
+ start = ( timer_data_type )luaL_checkinteger( L, 3 );
res = platform_timer_get_diff_us( id, end, start );
lua_pushinteger( L, res );
return 1;
}
-// Lua: res = mindelay( id )
-static int tmr_mindelay( lua_State* L )
+// Lua: res = getmindelay( id )
+static int tmr_getmindelay( lua_State* L )
{
u32 res;
unsigned id;
@@ -80,8 +80,8 @@
return 1;
}
-// Lua: res = maxdelay( id )
-static int tmr_maxdelay( lua_State* L )
+// Lua: res = getmaxdelay( id )
+static int tmr_getmaxdelay( lua_State* L )
{
u32 res;
unsigned id;
@@ -101,7 +101,7 @@
id = luaL_checkinteger( L, 1 );
MOD_CHECK_ID( timer, id );
- clock = luaL_checkinteger( L, 2 );
+ clock = ( u32 )luaL_checkinteger( L, 2 );
clock = platform_timer_op( id, PLATFORM_TIMER_OP_SET_CLOCK, clock );
lua_pushinteger( L, clock );
return 1;
@@ -151,9 +151,9 @@
{ LSTRKEY( "delay" ), LFUNCVAL( tmr_delay ) },
{ LSTRKEY( "read" ), LFUNCVAL( tmr_read ) },
{ LSTRKEY( "start" ), LFUNCVAL( tmr_start ) },
- { LSTRKEY( "diff" ), LFUNCVAL( tmr_diff ) },
- { LSTRKEY( "mindelay" ), LFUNCVAL( tmr_mindelay ) },
- { LSTRKEY( "maxdelay" ), LFUNCVAL( tmr_maxdelay ) },
+ { LSTRKEY( "gettimediff" ), LFUNCVAL( tmr_gettimediff ) },
+ { LSTRKEY( "getmindelay" ), LFUNCVAL( tmr_getmindelay ) },
+ { LSTRKEY( "getmaxdelay" ), LFUNCVAL( tmr_getmaxdelay ) },
{ LSTRKEY( "setclock" ), LFUNCVAL( tmr_setclock ) },
{ LSTRKEY( "getclock" ), LFUNCVAL( tmr_getclock ) },
#if LUA_OPTIMIZE_MEMORY > 0 && VTMR_NUM_TIMERS > 0
Modified: branches/eagle_mmc/src/modules/uart.c
===================================================================
--- branches/eagle_mmc/src/modules/uart.c 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/modules/uart.c 2009-11-06 02:08:32 UTC (rev 526)
@@ -35,7 +35,7 @@
return 1;
}
-// Lua: write( id, string1, string2, ... )
+// Lua: write( id, string1, [string2], ..., [stringn] )
static int uart_write( lua_State* L )
{
int id;
@@ -47,10 +47,20 @@
MOD_CHECK_ID( uart, id );
for( s = 2; s <= total; s ++ )
{
- luaL_checktype( L, s, LUA_TSTRING );
- buf = lua_tolstring( L, s, &len );
- for( i = 0; i < len; i ++ )
- platform_uart_send( id, buf[ i ] );
+ if( lua_isnumber( L, s ) )
+ {
+ len = lua_tointeger( L, s );
+ if( ( len < 0 ) || ( len > 255 ) )
+ return luaL_error( L, "invalid number" );
+ platform_uart_send( id, ( u8 )len );
+ }
+ else
+ {
+ luaL_checktype( L, s, LUA_TSTRING );
+ buf = lua_tolstring( L, s, &len );
+ for( i = 0; i < len; i ++ )
+ platform_uart_send( id, buf[ i ] );
+ }
}
return 0;
}
Modified: branches/eagle_mmc/src/platform/lm3s/adc.c
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/adc.c 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lm3s/adc.c 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,979 +1,1317 @@
-//*****************************************************************************
-//
-// adc.c - Driver for the ADC.
-//
-// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
-// Software License Agreement
-//
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
-//
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws. All rights are reserved. You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program. Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
-//
-// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-//
-// This is part of revision 3740 of the Stellaris Peripheral Driver Library.
-//
-//*****************************************************************************
-
-//*****************************************************************************
-//
-//! \addtogroup adc_api
-//! @{
-//
-//*****************************************************************************
-
-#include "hw_adc.h"
-#include "hw_ints.h"
-#include "hw_memmap.h"
-#include "hw_types.h"
-#include "adc.h"
-#include "debug.h"
-#include "interrupt.h"
-
-//*****************************************************************************
-//
-// These defines are used by the ADC driver to simplify access to the ADC
-// sequencer's registers.
-//
-//*****************************************************************************
-#define ADC_SEQ (ADC_O_SSMUX0)
-#define ADC_SEQ_STEP (ADC_O_SSMUX1 - ADC_O_SSMUX0)
-#define ADC_SSMUX (ADC_O_SSMUX0 - ADC_O_SSMUX0)
-#define ADC_SSCTL (ADC_O_SSCTL0 - ADC_O_SSMUX0)
-#define ADC_SSFIFO (ADC_O_SSFIFO0 - ADC_O_SSMUX0)
-#define ADC_SSFSTAT (ADC_O_SSFSTAT0 - ADC_O_SSMUX0)
-
-//*****************************************************************************
-//
-// The currently configured software oversampling factor for each of the ADC
-// sequencers.
-//
-//*****************************************************************************
-static unsigned char g_pucOversampleFactor[3];
-
-//*****************************************************************************
-//
-//! Registers an interrupt handler for an ADC interrupt.
-//!
-//! \param ulBase is the base address of the ADC module.
-//! \param ulSequenceNum is the sample sequence number.
-//! \param pfnHandler is a pointer to the function to be called when the
-//! ADC sample sequence interrupt occurs.
-//!
-//! This function sets the handler to be called when a sample sequence
-//! interrupt occurs. This will enable the global interrupt in the interrupt
-//! controller; the sequence interrupt must be enabled with ADCIntEnable(). It
-//! is the interrupt handler's responsibility to clear the interrupt source via
-//! ADCIntClear().
-//!
-//! \sa IntRegister() for important information about registering interrupt
-//! handlers.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum,
- void (*pfnHandler)(void))
-{
- unsigned long ulInt;
-
- //
- // Check the arguments.
- //
- ASSERT(ulBase == ADC_BASE);
- ASSERT(ulSequenceNum < 4);
-
- //
- // Determine the interrupt to register based on the sequence number.
- //
- ulInt = INT_ADC0 + ulSequenceNum;
-
- //
- // Register the interrupt handler.
- //
- IntRegister(ulInt, pfnHandler);
-
- //
- // Enable the timer interrupt.
- //
- IntEnable(ulInt);
-}
-
-//*****************************************************************************
-//
-//! Unregisters the interrupt handler for an ADC interrupt.
-//!
-//! \param ulBase is the base address of the ADC module.
-//! \param ulSequenceNum is the sample sequence number.
-//!
-//! This function unregisters the interrupt handler. This will disable the
-//! global interrupt in the interrupt controller; the sequence interrupt must
-//! be disabled via ADCIntDisable().
-//!
-//! \sa IntRegister() for important information about registering interrupt
-//! handlers.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-ADCIntUnregister(unsigned long ulBase, unsigned long ulSequenceNum)
-{
- unsigned long ulInt;
-
- //
- // Check the arguments.
- //
- ASSERT(ulBase == ADC_BASE);
- ASSERT(ulSequenceNum < 4);
-
- //
- // Determine the interrupt to unregister based on the sequence number.
- //
- ulInt = INT_ADC0 + ulSequenceNum;
-
- //
- // Disable the interrupt.
- //
- IntDisable(ulInt);
-
- //
- // Unregister the interrupt handler.
- //
- IntUnregister(ulInt);
-}
-
-//*****************************************************************************
-//
-//! Disables a sample sequence interrupt.
-//!
-//! \param ulBase is the base address of the ADC module.
-//! \param ulSequenceNum is the sample sequence number.
-//!
-//! This function disables the requested sample sequence interrupt.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum)
-{
- //
- // Check the arguments.
- //
- ASSERT(ulBase == ADC_BASE);
- ASSERT(ulSequenceNum < 4);
-
- //
- // Disable this sample sequence interrupt.
- //
- HWREG(ulBase + ADC_O_IM) &= ~(1 << ulSequenceNum);
-}
-
-//*****************************************************************************
-//
-//! Enables a sample sequence interrupt.
-//!
-//! \param ulBase is the base address of the ADC module.
-//! \param ulSequenceNum is the sample sequence number.
-//!
-//! This function enables the requested sample sequence interrupt. Any
-//! outstanding interrupts are cleared before enabling the sample sequence
-//! interrupt.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum)
-{
- //
- // Check the arguments.
- //
- ASSERT(ulBase == ADC_BASE);
- ASSERT(ulSequenceNum < 4);
-
- //
- // Clear any outstanding interrupts on this sample sequence.
- //
- HWREG(ulBase + ADC_O_ISC) = 1 << ulSequenceNum;
-
- //
- // Enable this sample sequence interrupt.
- //
- HWREG(ulBase + ADC_O_IM) |= 1 << ulSequenceNum;
-}
-
-//*****************************************************************************
-//
-//! Gets the current interrupt status.
-//!
-//! \param ulBase is the base address of the ADC module.
-//! \param ulSequenceNum is the sample sequence number.
-//! \param bMasked is false if the raw interrupt status is required and true if
-//! the masked interrupt status is required.
-//!
-//! This returns the interrupt status for the specified sample sequence.
-//! Either the raw interrupt status or the status of interrupts that are
-//! allowed to reflect to the processor can be returned.
-//!
-//! \return The current raw or masked interrupt status.
-//
-//*****************************************************************************
-unsigned long
-ADCIntStatus(unsigned long ulBase, unsigned long ulSequenceNum,
- tBoolean bMasked)
-{
- //
- // Check the arguments.
- //
- ASSERT(ulBase == ADC_BASE);
- ASSERT(ulSequenceNum < 4);
-
- //
- // Return either the interrupt status or the raw interrupt status as
- // requested.
- //
- if(bMasked)
- {
- return(HWREG(ulBase + ADC_O_ISC) & (1 << ulSequenceNum));
- }
- else
- {
- return(HWREG(ulBase + ADC_O_RIS) & (1 << ulSequenceNum));
- }
-}
-
-//*****************************************************************************
-//
-//! Clears sample sequence interrupt source.
-//!
-//! \param ulBase is the base address of the ADC module.
-//! \param ulSequenceNum is the sample sequence number.
-//!
-//! The specified sample sequence interrupt is cleared, so that it no longer
-//! asserts. This must be done in the interrupt handler to keep it from being
-//! called again immediately upon exit.
-//!
-//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
-//! several clock cycles before the interrupt source is actually cleared.
-//! Therefore, it is recommended that the interrupt source be cleared early in
-//! the interrupt handler (as opposed to the very last action) to avoid
-//! returning from the interrupt handler before the interrupt source is
-//! actually cleared. Failure to do so may result in the interrupt handler
-//! being immediately reentered (since NVIC still sees the interrupt source
-//! asserted).
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum)
-{
- //
- // Check the arugments.
- //
- ASSERT(ulBase == ADC_BASE);
- ASSERT(ulSequenceNum < 4);
-
- //
- // Clear the interrupt.
- //
- HWREG(ulBase + ADC_O_ISC) = 1 << ulSequenceNum;
-}
-
-//*****************************************************************************
-//
-//! Enables a sample sequence.
-//!
-//! \param ulBase is the base address of the ADC module.
-//! \param ulSequenceNum is the sample sequence number.
-//!
-//! Allows the specified sample sequence to be captured when its trigger is
-//! detected. A sample sequence must be configured before it is enabled.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-ADCSequenceEnable(unsigned long ulBase, unsigned long ulSequenceNum)
-{
- //
- // Check the arugments.
- //
- ASSERT(ulBase == ADC_BASE);
- ASSERT(ulSequenceNum < 4);
-
- //
- // Enable the specified sequence.
- //
- HWREG(ulBase + ADC_O_ACTSS) |= 1 << ulSequenceNum;
-}
-
-//*****************************************************************************
-//
-//! Disables a sample sequence.
-//!
-//! \param ulBase is the base address of the ADC module.
-//! \param ulSequenceNum is the sample sequence number.
-//!
-//! Prevents the specified sample sequence from being captured when its trigger
-//! is detected. A sample sequence should be disabled before it is configured.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-ADCSequenceDisable(unsigned long ulBase, unsigned long ulSequenceNum)
-{
- //
- // Check the arugments.
- //
- ASSERT(ulBase == ADC_BASE);
- ASSERT(ulSequenceNum < 4);
-
- //
- // Disable the specified sequences.
- //
- HWREG(ulBase + ADC_O_ACTSS) &= ~(1 << ulSequenceNum);
-}
-
-//*****************************************************************************
-//
-//! Configures the trigger source and priority of a sample sequence.
-//!
-//! \param ulBase is the base address of the ADC module.
-//! \param ulSequenceNum is the sample sequence number.
-//! \param ulTrigger is the trigger source that initiates the sample sequence;
-//! must be one of the \b ADC_TRIGGER_* values.
-//! \param ulPriority is the relative priority of the sample sequence with
-//! respect to the other sample sequences.
-//!
-//! This function configures the initiation criteria for a sample sequence.
-//! Valid sample sequences range from zero to three; sequence zero will capture
-//! up to eight samples, sequences one and two will capture up to four samples,
-//! and sequence three will capture a single sample. The trigger condition and
-//! priority (with respect to other sample sequence execution) is set.
-//!
-//! The \e ulTrigger parameter can take on the following values:
-//!
-//! - \b ADC_TRIGGER_PROCESSOR - A trigger generated by the processor, via the
-//! ADCProcessorTrigger() function.
-//! - \b ADC_TRIGGER_COMP0 - A trigger generated by the first analog
-//! comparator; configured with ComparatorConfigure().
-//! - \b ADC_TRIGGER_COMP1 - A trigger generated by the second analog
-//! comparator; configured with ComparatorConfigure().
-//! - \b ADC_TRIGGER_COMP2 - A trigger generated by the third analog
-//! comparator; configured with ComparatorConfigure().
-//! - \b ADC_TRIGGER_EXTERNAL - A trigger generated by an input from the Port
-//! B4 pin.
-//! - \b ADC_TRIGGER_TIMER - A trigger generated by a timer; configured with
-//! TimerControlTrigger().
-//! - \b ADC_TRIGGER_PWM0 - A trigger generated by the first PWM generator;
-//! configured with PWMGenIntTrigEnable().
-//! - \b ADC_TRIGGER_PWM1 - A trigger generated by the second PWM generator;
-//! configured with PWMGenIntTrigEnable().
-//! - \b ADC_TRIGGER_PWM2 - A trigger generated by the third PWM generator;
-//! configured with PWMGenIntTrigEnable().
-//! - \b ADC_TRIGGER_ALWAYS - A trigger that is always asserted, causing the
-//! sample sequence to capture repeatedly (so long as
-//! there is not a higher priority source active).
-//!
-//! Note that not all trigger sources are available on all Stellaris family
-//! members; consult the data sheet for the device in question to determine the
-//! availability of triggers.
-//!
-//! The \e ulPriority parameter is a value between 0 and 3, where 0 represents
-//! the highest priority and 3 the lowest. Note that when programming the
-//! priority among a set of sample sequences, each must have unique priority;
-//! it is up to the caller to guarantee the uniqueness of the priorities.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-ADCSequenceConfigure(unsigned long ulBase, unsigned long ulSequenceNum,
- unsigned long ulTrigger, unsigned long ulPriority)
-{
- //
- // Check the arugments.
- //
- ASSERT(ulBase == ADC_BASE);
- ASSERT(ulSequenceNum < 4);
- ASSERT((ulTrigger == ADC_TRIGGER_PROCESSOR) ||
- (ulTrigger == ADC_TRIGGER_COMP0) ||
- (ulTrigger == ADC_TRIGGER_COMP1) ||
- (ulTrigger == ADC_TRIGGER_COMP2) ||
- (ulTrigger == ADC_TRIGGER_EXTERNAL) ||
- (ulTrigger == ADC_TRIGGER_TIMER) ||
- (ulTrigger == ADC_TRIGGER_PWM0) ||
- (ulTrigger == ADC_TRIGGER_PWM1) ||
- (ulTrigger == ADC_TRIGGER_PWM2) ||
- (ulTrigger == ADC_TRIGGER_ALWAYS));
- ASSERT(ulPriority < 4);
-
- //
- // Compute the shift for the bits that control this sample sequence.
- //
- ulSequenceNum *= 4;
-
- //
- // Set the trigger event for this sample sequence.
- //
- HWREG(ulBase + ADC_O_EMUX) = ((HWREG(ulBase + ADC_O_EMUX) &
- ~(0xf << ulSequenceNum)) |
- ((ulTrigger & 0xf) << ulSequenceNum));
-
- //
- // Set the priority for this sample sequence.
- //
- HWREG(ulBase + ADC_O_SSPRI) = ((HWREG(ulBase + ADC_O_SSPRI) &
- ~(0xf << ulSequenceNum)) |
- ((ulPriority & 0x3) << ulSequenceNum));
-}
-
-//*****************************************************************************
-//
-//! Configure a step of the sample sequencer.
-//!
-//! \param ulBase is the base address of the ADC module.
-//! \param ulSequenceNum is the sample sequence number.
-//! \param ulStep is the step to be configured.
-//! \param ulConfig is the configuration of this step; must be a logical OR of
-//! \b ADC_CTL_TS, \b ADC_CTL_IE, \b ADC_CTL_END, \b ADC_CTL_D, and one of the
-//! input channel selects (\b ADC_CTL_CH0 through \b ADC_CTL_CH7).
-//!
-//! This function will set the configuration of the ADC for one step of a
-//! sample sequence. The ADC can be configured for single-ended or
-//! differential operation (the \b ADC_CTL_D bit selects differential
-//! operation when set), the channel to be sampled can be chosen (the
-//! \b ADC_CTL_CH0 through \b ADC_CTL_CH7 values), and the internal temperature
-//! sensor can be selected (the \b ADC_CTL_TS bit). Additionally, this step
-//! can be defined as the last in the sequence (the \b ADC_CTL_END bit) and it
-//! can be configured to cause an interrupt when the step is complete (the
-//! \b ADC_CTL_IE bit). The configuration is used by the ADC at the
-//! appropriate time when the trigger for this sequence occurs.
-//!
-//! The \e ulStep parameter determines the order in which the samples are
-//! captured by the ADC when the trigger occurs. It can range from zero to
-//! seven for the first sample sequence, from zero to three for the second and
-//! third sample sequence, and can only be zero for the fourth sample sequence.
-//!
-//! Differential mode only works with adjacent channel pairs (for example, 0
-//! and 1). The channel select must be the number of the channel pair to
-//! sample (for example, \b ADC_CTL_CH0 for 0 and 1, or \b ADC_CTL_CH1 for 2
-//! and 3) or undefined results will be returned by the ADC. Additionally, if
-//! differential mode is selected when the temperature sensor is being sampled,
-//! undefined results will be returned by the ADC.
-//!
-//! It is the responsibility of the caller to ensure that a valid configuration
-//! is specified; this function does not check the validity of the specified
-//! configuration.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-ADCSequenceStepConfigure(unsigned long ulBase, unsigned long ulSequenceNum,
- unsigned long ulStep, unsigned long ulConfig)
-{
- //
- // Check the arugments.
- //
- ASSERT(ulBase == ADC_BASE);
- ASSERT(ulSequenceNum < 4);
- ASSERT(((ulSequenceNum == 0) && (ulStep < 8)) ||
- ((ulSequenceNum == 1) && (ulStep < 4)) ||
- ((ulSequenceNum == 2) && (ulStep < 4)) ||
- ((ulSequenceNum == 3) && (ulStep < 1)));
-
- //
- // Get the offset of the sequence to be configured.
- //
- ulBase += ADC_SEQ + (ADC_SEQ_STEP * ulSequenceNum);
-
- //
- // Compute the shift for the bits that control this step.
- //
- ulStep *= 4;
-
- //
- // Set the analog mux value for this step.
- //
- HWREG(ulBase + ADC_SSMUX) = ((HWREG(ulBase + ADC_SSMUX) &
- ~(0x0000000f << ulStep)) |
- ((ulConfig & 0x0f) << ulStep));
-
- //
- // Set the control value for this step.
- //
- HWREG(ulBase + ADC_SSCTL) = ((HWREG(ulBase + ADC_SSCTL) &
- ~(0x0000000f << ulStep)) |
- (((ulConfig & 0xf0) >> 4) << ulStep));
-}
-
-//*****************************************************************************
-//
-//! Determines if a sample sequence overflow occurred.
-//!
-//! \param ulBase is the base address of the ADC module.
-//! \param ulSequenceNum is the sample sequence number.
-//!
-//! This determines if a sample sequence overflow has occurred. This will
-//! happen if the captured samples are not read from the FIFO before the next
-//! trigger occurs.
-//!
-//! \return Returns zero if there was not an overflow, and non-zero if there
-//! was.
-//
-//*****************************************************************************
-long
-ADCSequenceOverflow(unsigned long ulBase, unsigned long ulSequenceNum)
-{
- //
- // Check the arguments.
- //
- ASSERT(ulBase == ADC_BASE);
- ASSERT(ulSequenceNum < 4);
-
- //
- // Determine if there was an overflow on this sequence.
- //
- return(HWREG(ulBase + ADC_O_OSTAT) & (1 << ulSequenceNum));
-}
-
-//*****************************************************************************
-//
-//! Clears the overflow condition on a sample sequence.
-//!
-//! \param ulBase is the base address of the ADC module.
-//! \param ulSequenceNum is the sample sequence number.
-//!
-//! This will clear an overflow condition on one of the sample sequences. The
-//! overflow condition must be cleared in order to detect a subsequent overflow
-//! condition (it otherwise causes no harm).
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-ADCSequenceOverflowClear(unsigned long ulBase, unsigned long ulSequenceNum)
-{
- //
- // Check the arguments.
- //
- ASSERT(ulBase == ADC_BASE);
- ASSERT(ulSequenceNum < 4);
-
- //
- // Clear the overflow condition for this sequence.
- //
- HWREG(ulBase + ADC_O_OSTAT) = 1 << ulSequenceNum;
-}
-
-//*****************************************************************************
-//
-//! Determines if a sample sequence underflow occurred.
-//!
-//! \param ulBase is the base address of the ADC module.
-//! \param ulSequenceNum is the sample sequence number.
-//!
-//! This determines if a sample sequence underflow has occurred. This will
-//! happen if too many samples are read from the FIFO.
-//!
-//! \return Returns zero if there was not an underflow, and non-zero if there
-//! was.
-//
-//*****************************************************************************
-long
-ADCSequenceUnderflow(unsigned long ulBase, unsigned long ulSequenceNum)
-{
- //
- // Check the arguments.
- //
- ASSERT(ulBase == ADC_BASE);
- ASSERT(ulSequenceNum < 4);
-
- //
- // Determine if there was an underflow on this sequence.
- //
- return(HWREG(ulBase + ADC_O_USTAT) & (1 << ulSequenceNum));
-}
-
-//*****************************************************************************
-//
-//! Clears the underflow condition on a sample sequence.
-//!
-//! \param ulBase is the base address of the ADC module.
-//! \param ulSequenceNum is the sample sequence number.
-//!
-//! This will clear an underflow condition on one of the sample sequences. The
-//! underflow condition must be cleared in order to detect a subsequent
-//! underflow condition (it otherwise causes no harm).
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-ADCSequenceUnderflowClear(unsigned long ulBase, unsigned long ulSequenceNum)
-{
- //
- // Check the arguments.
- //
- ASSERT(ulBase == ADC_BASE);
- ASSERT(ulSequenceNum < 4);
-
- //
- // Clear the underflow condition for this sequence.
- //
- HWREG(ulBase + ADC_O_USTAT) = 1 << ulSequenceNum;
-}
-
-//*****************************************************************************
-//
-//! Gets the captured data for a sample sequence.
-//!
-//! \param ulBase is the base address of the ADC module.
-//! \param ulSequenceNum is the sample sequence number.
-//! \param pulBuffer is the address where the data is stored.
-//!
-//! This function copies data from the specified sample sequence output FIFO to
-//! a memory resident buffer. The number of samples available in the hardware
-//! FIFO are copied into the buffer, which is assumed to be large enough to
-//! hold that many samples. This will only return the samples that are
-//! presently available, which may not be the entire sample sequence if it is
-//! in the process of being executed.
-//!
-//! \return Returns the number of samples copied to the buffer.
-//
-//*****************************************************************************
-long
-ADCSequenceDataGet(unsigned long ulBase, unsigned long ulSequenceNum,
- unsigned long *pulBuffer)
-{
- unsigned long ulCount;
-
- //
- // Check the arguments.
- //
- ASSERT(ulBase == ADC_BASE);
- ASSERT(ulSequenceNum < 4);
-
- //
- // Get the offset of the sequence to be read.
- //
- ulBase += ADC_SEQ + (ADC_SEQ_STEP * ulSequenceNum);
-
- //
- // Read samples from the FIFO until it is empty.
- //
- ulCount = 0;
- while(!(HWREG(ulBase + ADC_SSFSTAT) & ADC_SSFSTAT0_EMPTY) && (ulCount < 8))
- {
- //
- // Read the FIFO and copy it to the destination.
- //
- *pulBuffer++ = HWREG(ulBase + ADC_SSFIFO);
-
- //
- // Increment the count of samples read.
- //
- ulCount++;
- }
-
- //
- // Return the number of samples read.
- //
- return(ulCount);
-}
-
-//*****************************************************************************
-//
-//! Causes a processor trigger for a sample sequence.
-//!
-//! \param ulBase is the base address of the ADC module.
-//! \param ulSequenceNum is the sample sequence number.
-//!
-//! This function triggers a processor-initiated sample sequence if the sample
-//! sequence trigger is configured to \b ADC_TRIGGER_PROCESSOR.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-ADCProcessorTrigger(unsigned long ulBase, unsigned long ulSequenceNum)
-{
- //
- // Check the arguments.
- //
- ASSERT(ulBase == ADC_BASE);
- ASSERT(ulSequenceNum < 4);
-
- //
- // Generate a processor trigger for this sample sequence.
- //
- HWREG(ulBase + ADC_O_PSSI) = 1 << ulSequenceNum;
-}
-
-//*****************************************************************************
-//
-//! Configures the software oversampling factor of the ADC.
-//!
-//! \param ulBase is the base address of the ADC module.
-//! \param ulSequenceNum is the sample sequence number.
-//! \param ulFactor is the number of samples to be averaged.
-//!
-//! This function configures the software oversampling for the ADC, which can
-//! be used to provide better resolution on the sampled data. Oversampling is
-//! accomplished by averaging multiple samples from the same analog input.
-//! Three different oversampling rates are supported; 2x, 4x, and 8x.
-//!
-//! Oversampling is only supported on the sample sequencers that are more than
-//! one sample in depth (that is, the fourth sample sequencer is not
-//! supported). Oversampling by 2x (for example) divides the depth of the
-//! sample sequencer by two; so 2x oversampling on the first sample sequencer
-//! can only provide four samples per trigger. This also means that 8x
-//! oversampling is only available on the first sample sequencer.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-ADCSoftwareOversampleConfigure(unsigned long ulBase,
- unsigned long ulSequenceNum,
- unsigned long ulFactor)
-{
- unsigned long ulValue;
-
- //
- // Check the arguments.
- //
- ASSERT(ulBase == ADC_BASE);
- ASSERT(ulSequenceNum < 3);
- ASSERT(((ulFactor == 2) || (ulFactor == 4) || (ulFactor == 8)) &&
- ((ulSequenceNum == 0) || (ulFactor != 8)));
-
- //
- // Convert the oversampling factor to a shift factor.
- //
- for(ulValue = 0, ulFactor >>= 1; ulFactor; ulValue++, ulFactor >>= 1)
- {
- }
-
- //
- // Save the sfiht factor.
- //
- g_pucOversampleFactor[ulSequenceNum] = ulValue;
-}
-
-//*****************************************************************************
-//
-//! Configures a step of the software oversampled sequencer.
-//!
-//! \param ulBase is the base address of the ADC module.
-//! \param ulSequenceNum is the sample sequence number.
-//! \param ulStep is the step to be configured.
-//! \param ulConfig is the configuration of this step.
-//!
-//! This function configures a step of the sample sequencer when using the
-//! software oversampling feature. The number of steps available depends on
-//! the oversampling factor set by ADCSoftwareOversampleConfigure(). The value
-//! of \e ulConfig is the same as defined for ADCSequenceStepConfigure().
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-ADCSoftwareOversampleStepConfigure(unsigned long ulBase,
- unsigned long ulSequenceNum,
- unsigned long ulStep,
- unsigned long ulConfig)
-{
- //
- // Check the arguments.
- //
- ASSERT(ulBase == ADC_BASE);
- ASSERT(ulSequenceNum < 3);
- ASSERT(((ulSequenceNum == 0) &&
- (ulStep < (8 >> g_pucOversampleFactor[ulSequenceNum]))) ||
- (ulStep < (4 >> g_pucOversampleFactor[ulSequenceNum])));
-
- //
- // Get the offset of the sequence to be configured.
- //
- ulBase += ADC_SEQ + (ADC_SEQ_STEP * ulSequenceNum);
-
- //
- // Compute the shift for the bits that control this step.
- //
- ulStep *= 4 << g_pucOversampleFactor[ulSequenceNum];
-
- //
- // Loop through the hardware steps that make up this step of the software
- // oversampled sequence.
- //
- for(ulSequenceNum = 1 << g_pucOversampleFactor[ulSequenceNum];
- ulSequenceNum; ulSequenceNum--)
- {
- //
- // Set the analog mux value for this step.
- //
- HWREG(ulBase + ADC_SSMUX) = ((HWREG(ulBase + ADC_SSMUX) &
- ~(0x0000000f << ulStep)) |
- ((ulConfig & 0x0f) << ulStep));
-
- //
- // Set the control value for this step.
- //
- HWREG(ulBase + ADC_SSCTL) = ((HWREG(ulBase + ADC_SSCTL) &
- ~(0x0000000f << ulStep)) |
- (((ulConfig & 0xf0) >> 4) << ulStep));
- if(ulSequenceNum != 1)
- {
- HWREG(ulBase + ADC_SSCTL) &= ~((ADC_SSCTL0_IE0 |
- ADC_SSCTL0_END0) << ulStep);
- }
-
- //
- // Go to the next hardware step.
- //
- ulStep += 4;
- }
-}
-
-//*****************************************************************************
-//
-//! Gets the captured data for a sample sequence using software oversampling.
-//!
-//! \param ulBase is the base address of the ADC module.
-//! \param ulSequenceNum is the sample sequence number.
-//! \param pulBuffer is the address where the data is stored.
-//! \param ulCount is the number of samples to be read.
-//!
-//! This function copies data from the specified sample sequence output FIFO to
-//! a memory resident buffer with software oversampling applied. The requested
-//! number of samples are copied into the data buffer; if there are not enough
-//! samples in the hardware FIFO to satisfy this many oversampled data items
-//! then incorrect results will be returned. It is the caller's responsibility
-//! to read only the samples that are available and wait until enough data is
-//! available, for example as a result of receiving an interrupt.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-ADCSoftwareOversampleDataGet(unsigned long ulBase, unsigned long ulSequenceNum,
- unsigned long *pulBuffer, unsigned long ulCount)
-{
- unsigned long ulIdx, ulAccum;
-
- //
- // Check the arguments.
- //
- ASSERT(ulBase == ADC_BASE);
- ASSERT(ulSequenceNum < 3);
- ASSERT(((ulSequenceNum == 0) &&
- (ulCount < (8 >> g_pucOversampleFactor[ulSequenceNum]))) ||
- (ulCount < (4 >> g_pucOversampleFactor[ulSequenceNum])));
-
- //
- // Get the offset of the sequence to be read.
- //
- ulBase += ADC_SEQ + (ADC_SEQ_STEP * ulSequenceNum);
-
- //
- // Read the samples from the FIFO until it is empty.
- //
- while(ulCount--)
- {
- //
- // Compute the sum of the samples.
- //
- ulAccum = 0;
- for(ulIdx = 1 << g_pucOversampleFactor[ulSequenceNum]; ulIdx; ulIdx--)
- {
- //
- // Read the FIFO and add it to the accumulator.
- //
- ulAccum += HWREG(ulBase + ADC_SSFIFO);
- }
-
- //
- // Write the averaged sample to the output buffer.
- //
- *pulBuffer++ = ulAccum >> g_pucOversampleFactor[ulSequenceNum];
- }
-}
-
-//*****************************************************************************
-//
-//! Configures the hardware oversampling factor of the ADC.
-//!
-//! \param ulBase is the base address of the ADC module.
-//! \param ulFactor is the number of samples to be averaged.
-//!
-//! This function configures the hardware oversampling for the ADC, which can
-//! be used to provide better resolution on the sampled data. Oversampling is
-//! accomplished by averaging multiple samples from the same analog input. Six
-//! different oversampling rates are supported; 2x, 4x, 8x, 16x, 32x, and 64x.
-//! Specifying an oversampling factor of zero will disable hardware
-//! oversampling.
-//!
-//! Hardware oversampling applies uniformly to all sample sequencers. It does
-//! not reduce the depth of the sample sequencers like the software
-//! oversampling APIs; each sample written into the sample sequence FIFO is a
-//! fully oversampled analog input reading.
-//!
-//! Enabling hardware averaging increases the precision of the ADC at the cost
-//! of throughput. For example, enabling 4x oversampling reduces the
-//! throughput of a 250 Ksps ADC to 62.5 Ksps.
-//!
-//! \note Hardware oversampling is available beginning with Rev C0 of the
-//! Stellaris microcontroller.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-ADCHardwareOversampleConfigure(unsigned long ulBase, unsigned long ulFactor)
-{
- unsigned long ulValue;
-
- //
- // Check the arguments.
- //
- ASSERT(ulBase == ADC_BASE);
- ASSERT(((ulFactor == 0) || (ulFactor == 2) || (ulFactor == 4) ||
- (ulFactor == 8) || (ulFactor == 16) || (ulFactor == 32) ||
- (ulFactor == 64)));
-
- //
- // Convert the oversampling factor to a shift factor.
- //
- for(ulValue = 0, ulFactor >>= 1; ulFactor; ulValue++, ulFactor >>= 1)
- {
- }
-
- //
- // Write the shift factor to the ADC to configure the hardware oversampler.
- //
- HWREG(ulBase + ADC_O_SAC) = ulValue;
-}
-
-//*****************************************************************************
-//
-// Close the Doxygen group.
-//! @}
-//
-//*****************************************************************************
+//*****************************************************************************
+//
+// adc.c - Driver for the ADC.
+//
+// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup adc_api
+//! @{
+//
+//*****************************************************************************
+
+#include "hw_adc.h"
+#include "hw_ints.h"
+#include "hw_memmap.h"
+#include "hw_types.h"
+#include "adc.h"
+#include "debug.h"
+#include "interrupt.h"
+
+//*****************************************************************************
+//
+// These defines are used by the ADC driver to simplify access to the ADC
+// sequencer's registers.
+//
+//*****************************************************************************
+#define ADC_SEQ (ADC_O_SSMUX0)
+#define ADC_SEQ_STEP (ADC_O_SSMUX1 - ADC_O_SSMUX0)
+#define ADC_SSMUX (ADC_O_SSMUX0 - ADC_O_SSMUX0)
+#define ADC_SSCTL (ADC_O_SSCTL0 - ADC_O_SSMUX0)
+#define ADC_SSFIFO (ADC_O_SSFIFO0 - ADC_O_SSMUX0)
+#define ADC_SSFSTAT (ADC_O_SSFSTAT0 - ADC_O_SSMUX0)
+#define ADC_SSOP (ADC_O_SSOP0 - ADC_O_SSMUX0)
+#define ADC_SSDC (ADC_O_SSDC0 - ADC_O_SSMUX0)
+
+//*****************************************************************************
+//
+// The currently configured software oversampling factor for each of the ADC
+// sequencers.
+//
+//*****************************************************************************
+static unsigned char g_pucOversampleFactor[3];
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for an ADC interrupt.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulSequenceNum is the sample sequence number.
+//! \param pfnHandler is a pointer to the function to be called when the
+//! ADC sample sequence interrupt occurs.
+//!
+//! This function sets the handler to be called when a sample sequence
+//! interrupt occurs. This will enable the global interrupt in the interrupt
+//! controller; the sequence interrupt must be enabled with ADCIntEnable(). It
+//! is the interrupt handler's responsibility to clear the interrupt source via
+//! ADCIntClear().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum,
+ void (*pfnHandler)(void))
+{
+ unsigned long ulInt;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulSequenceNum < 4);
+
+ //
+ // Determine the interrupt to register based on the sequence number.
+ //
+ ulInt = INT_ADC0 + ulSequenceNum;
+
+ //
+ // Register the interrupt handler.
+ //
+ IntRegister(ulInt, pfnHandler);
+
+ //
+ // Enable the timer interrupt.
+ //
+ IntEnable(ulInt);
+}
+
+//*****************************************************************************
+//
+//! Unregisters the interrupt handler for an ADC interrupt.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulSequenceNum is the sample sequence number.
+//!
+//! This function unregisters the interrupt handler. This will disable the
+//! global interrupt in the interrupt controller; the sequence interrupt must
+//! be disabled via ADCIntDisable().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCIntUnregister(unsigned long ulBase, unsigned long ulSequenceNum)
+{
+ unsigned long ulInt;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulSequenceNum < 4);
+
+ //
+ // Determine the interrupt to unregister based on the sequence number.
+ //
+ ulInt = INT_ADC0 + ulSequenceNum;
+
+ //
+ // Disable the interrupt.
+ //
+ IntDisable(ulInt);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(ulInt);
+}
+
+//*****************************************************************************
+//
+//! Disables a sample sequence interrupt.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulSequenceNum is the sample sequence number.
+//!
+//! This function disables the requested sample sequence interrupt.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulSequenceNum < 4);
+
+ //
+ // Disable this sample sequence interrupt.
+ //
+ HWREG(ulBase + ADC_O_IM) &= ~(1 << ulSequenceNum);
+}
+
+//*****************************************************************************
+//
+//! Enables a sample sequence interrupt.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulSequenceNum is the sample sequence number.
+//!
+//! This function enables the requested sample sequence interrupt. Any
+//! outstanding interrupts are cleared before enabling the sample sequence
+//! interrupt.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulSequenceNum < 4);
+
+ //
+ // Clear any outstanding interrupts on this sample sequence.
+ //
+ HWREG(ulBase + ADC_O_ISC) = 1 << ulSequenceNum;
+
+ //
+ // Enable this sample sequence interrupt.
+ //
+ HWREG(ulBase + ADC_O_IM) |= 1 << ulSequenceNum;
+}
+
+//*****************************************************************************
+//
+//! Gets the current interrupt status.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulSequenceNum is the sample sequence number.
+//! \param bMasked is false if the raw interrupt status is required and true if
+//! the masked interrupt status is required.
+//!
+//! This returns the interrupt status for the specified sample sequence.
+//! Either the raw interrupt status or the status of interrupts that are
+//! allowed to reflect to the processor can be returned.
+//!
+//! \return The current raw or masked interrupt status.
+//
+//*****************************************************************************
+unsigned long
+ADCIntStatus(unsigned long ulBase, unsigned long ulSequenceNum,
+ tBoolean bMasked)
+{
+ unsigned long ulTemp;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulSequenceNum < 4);
+
+ //
+ // Return either the interrupt status or the raw interrupt status as
+ // requested.
+ //
+ if(bMasked)
+ {
+ ulTemp = HWREG(ulBase + ADC_O_ISC) & (0x10001 << ulSequenceNum);
+ }
+ else
+ {
+ ulTemp = HWREG(ulBase + ADC_O_RIS) & (0x10000 | (1 << ulSequenceNum));
+
+ //
+ // If the Digital Comparator status bit is set, reflect it to the
+ // appropriate sequence bit.
+ //
+ if(ulTemp & 0x10000)
+ {
+ ulTemp |= 0xF0000;
+ ulTemp &= ~(0x10000 << ulSequenceNum);
+ }
+ }
+
+ //
+ // Return the interrupt status
+ //
+ return(ulTemp);
+}
+
+//*****************************************************************************
+//
+//! Clears sample sequence interrupt source.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulSequenceNum is the sample sequence number.
+//!
+//! The specified sample sequence interrupt is cleared, so that it no longer
+//! asserts. This must be done in the interrupt handler to keep it from being
+//! called again immediately upon exit.
+//!
+//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
+//! several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared. Failure to do so may result in the interrupt handler
+//! being immediately reentered (since NVIC still sees the interrupt source
+//! asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum)
+{
+ //
+ // Check the arugments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulSequenceNum < 4);
+
+ //
+ // Clear the interrupt.
+ //
+ HWREG(ulBase + ADC_O_ISC) = 1 << ulSequenceNum;
+}
+
+//*****************************************************************************
+//
+//! Enables a sample sequence.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulSequenceNum is the sample sequence number.
+//!
+//! Allows the specified sample sequence to be captured when its trigger is
+//! detected. A sample sequence must be configured before it is enabled.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCSequenceEnable(unsigned long ulBase, unsigned long ulSequenceNum)
+{
+ //
+ // Check the arugments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulSequenceNum < 4);
+
+ //
+ // Enable the specified sequence.
+ //
+ HWREG(ulBase + ADC_O_ACTSS) |= 1 << ulSequenceNum;
+}
+
+//*****************************************************************************
+//
+//! Disables a sample sequence.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulSequenceNum is the sample sequence number.
+//!
+//! Prevents the specified sample sequence from being captured when its trigger
+//! is detected. A sample sequence should be disabled before it is configured.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCSequenceDisable(unsigned long ulBase, unsigned long ulSequenceNum)
+{
+ //
+ // Check the arugments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulSequenceNum < 4);
+
+ //
+ // Disable the specified sequences.
+ //
+ HWREG(ulBase + ADC_O_ACTSS) &= ~(1 << ulSequenceNum);
+}
+
+//*****************************************************************************
+//
+//! Configures the trigger source and priority of a sample sequence.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulSequenceNum is the sample sequence number.
+//! \param ulTrigger is the trigger source that initiates the sample sequence;
+//! must be one of the \b ADC_TRIGGER_* values.
+//! \param ulPriority is the relative priority of the sample sequence with
+//! respect to the other sample sequences.
+//!
+//! This function configures the initiation criteria for a sample sequence.
+//! Valid sample sequences range from zero to three; sequence zero will capture
+//! up to eight samples, sequences one and two will capture up to four samples,
+//! and sequence three will capture a single sample. The trigger condition and
+//! priority (with respect to other sample sequence execution) is set.
+//!
+//! The \e ulTrigger parameter can take on the following values:
+//!
+//! - \b ADC_TRIGGER_PROCESSOR - A trigger generated by the processor, via the
+//! ADCProcessorTrigger() function.
+//! - \b ADC_TRIGGER_COMP0 - A trigger generated by the first analog
+//! comparator; configured with ComparatorConfigure().
+//! - \b ADC_TRIGGER_COMP1 - A trigger generated by the second analog
+//! comparator; configured with ComparatorConfigure().
+//! - \b ADC_TRIGGER_COMP2 - A trigger generated by the third analog
+//! comparator; configured with ComparatorConfigure().
+//! - \b ADC_TRIGGER_EXTERNAL - A trigger generated by an input from the Port
+//! B4 pin.
+//! - \b ADC_TRIGGER_TIMER - A trigger generated by a timer; configured with
+//! TimerControlTrigger().
+//! - \b ADC_TRIGGER_PWM0 - A trigger generated by the first PWM generator;
+//! configured with PWMGenIntTrigEnable().
+//! - \b ADC_TRIGGER_PWM1 - A trigger generated by the second PWM generator;
+//! configured with PWMGenIntTrigEnable().
+//! - \b ADC_TRIGGER_PWM2 - A trigger generated by the third PWM generator;
+//! configured with PWMGenIntTrigEnable().
+//! - \b ADC_TRIGGER_ALWAYS - A trigger that is always asserted, causing the
+//! sample sequence to capture repeatedly (so long as
+//! there is not a higher priority source active).
+//!
+//! Note that not all trigger sources are available on all Stellaris family
+//! members; consult the data sheet for the device in question to determine the
+//! availability of triggers.
+//!
+//! The \e ulPriority parameter is a value between 0 and 3, where 0 represents
+//! the highest priority and 3 the lowest. Note that when programming the
+//! priority among a set of sample sequences, each must have unique priority;
+//! it is up to the caller to guarantee the uniqueness of the priorities.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCSequenceConfigure(unsigned long ulBase, unsigned long ulSequenceNum,
+ unsigned long ulTrigger, unsigned long ulPriority)
+{
+ //
+ // Check the arugments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulSequenceNum < 4);
+ ASSERT((ulTrigger == ADC_TRIGGER_PROCESSOR) ||
+ (ulTrigger == ADC_TRIGGER_COMP0) ||
+ (ulTrigger == ADC_TRIGGER_COMP1) ||
+ (ulTrigger == ADC_TRIGGER_COMP2) ||
+ (ulTrigger == ADC_TRIGGER_EXTERNAL) ||
+ (ulTrigger == ADC_TRIGGER_TIMER) ||
+ (ulTrigger == ADC_TRIGGER_PWM0) ||
+ (ulTrigger == ADC_TRIGGER_PWM1) ||
+ (ulTrigger == ADC_TRIGGER_PWM2) ||
+ (ulTrigger == ADC_TRIGGER_ALWAYS));
+ ASSERT(ulPriority < 4);
+
+ //
+ // Compute the shift for the bits that control this sample sequence.
+ //
+ ulSequenceNum *= 4;
+
+ //
+ // Set the trigger event for this sample sequence.
+ //
+ HWREG(ulBase + ADC_O_EMUX) = ((HWREG(ulBase + ADC_O_EMUX) &
+ ~(0xf << ulSequenceNum)) |
+ ((ulTrigger & 0xf) << ulSequenceNum));
+
+ //
+ // Set the priority for this sample sequence.
+ //
+ HWREG(ulBase + ADC_O_SSPRI) = ((HWREG(ulBase + ADC_O_SSPRI) &
+ ~(0xf << ulSequenceNum)) |
+ ((ulPriority & 0x3) << ulSequenceNum));
+}
+
+//*****************************************************************************
+//
+//! Configure a step of the sample sequencer.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulSequenceNum is the sample sequence number.
+//! \param ulStep is the step to be configured.
+//! \param ulConfig is the configuration of this step; must be a logical OR of
+//! \b ADC_CTL_TS, \b ADC_CTL_IE, \b ADC_CTL_END, \b ADC_CTL_D, and one of the
+//! input channel selects (\b ADC_CTL_CH0 through \b ADC_CTL_CH15). For parts
+//! with the Digital Comparator feature, the follow values may also be OR'd
+//! into the \e ulConfig value to enable the Digital Comparater feature:
+//! \b ADC_CTL_CE and one of the comparater selects (\b ADC_CTL_CMP0 through
+//! \b ADC_CTL_CMP7).
+//!
+//! This function will set the configuration of the ADC for one step of a
+//! sample sequence. The ADC can be configured for single-ended or
+//! differential operation (the \b ADC_CTL_D bit selects differential
+//! operation when set), the channel to be sampled can be chosen (the
+//! \b ADC_CTL_CH0 through \b ADC_CTL_CH15 values), and the internal
+//! temperature sensor can be selected (the \b ADC_CTL_TS bit). Additionally,
+//! this step can be defined as the last in the sequence (the \b ADC_CTL_END
+//! bit) and it can be configured to cause an interrupt when the step is
+//! complete (the \b ADC_CTL_IE bit). If the Digital Comparators are present
+//! on the device, this step may also be configured send the ADC sample to
+//! the selected comparator (the \b ADC_CTL_CMP0 through \b ADC_CTL_CMP7
+//! values) by using the \b ADC_CTL_CE bit. The configuration is used by the
+//! ADC at the appropriate time when the trigger for this sequence occurs.
+//!
+//! \note If the Digitial Comparator is present and enabled using the
+//! \b ADC_CTL_CE bit, the ADC sample will NOT be written into the ADC
+//! sequence data FIFO.
+//!
+//! The \e ulStep parameter determines the order in which the samples are
+//! captured by the ADC when the trigger occurs. It can range from zero to
+//! seven for the first sample sequence, from zero to three for the second and
+//! third sample sequence, and can only be zero for the fourth sample sequence.
+//!
+//! Differential mode only works with adjacent channel pairs (for example, 0
+//! and 1). The channel select must be the number of the channel pair to
+//! sample (for example, \b ADC_CTL_CH0 for 0 and 1, or \b ADC_CTL_CH1 for 2
+//! and 3) or undefined results will be returned by the ADC. Additionally, if
+//! differential mode is selected when the temperature sensor is being sampled,
+//! undefined results will be returned by the ADC.
+//!
+//! It is the responsibility of the caller to ensure that a valid configuration
+//! is specified; this function does not check the validity of the specified
+//! configuration.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCSequenceStepConfigure(unsigned long ulBase, unsigned long ulSequenceNum,
+ unsigned long ulStep, unsigned long ulConfig)
+{
+ unsigned long ulTemp;
+
+ //
+ // Check the arugments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulSequenceNum < 4);
+ ASSERT(((ulSequenceNum == 0) && (ulStep < 8)) ||
+ ((ulSequenceNum == 1) && (ulStep < 4)) ||
+ ((ulSequenceNum == 2) && (ulStep < 4)) ||
+ ((ulSequenceNum == 3) && (ulStep < 1)));
+
+ //
+ // Get the offset of the sequence to be configured.
+ //
+ ulBase += ADC_SEQ + (ADC_SEQ_STEP * ulSequenceNum);
+
+ //
+ // Compute the shift for the bits that control this step.
+ //
+ ulStep *= 4;
+
+ //
+ // Set the analog mux value for this step.
+ //
+ HWREG(ulBase + ADC_SSMUX) = ((HWREG(ulBase + ADC_SSMUX) &
+ ~(0x0000000f << ulStep)) |
+ ((ulConfig & 0x0f) << ulStep));
+
+ //
+ // Set the control value for this step.
+ //
+ HWREG(ulBase + ADC_SSCTL) = ((HWREG(ulBase + ADC_SSCTL) &
+ ~(0x0000000f << ulStep)) |
+ (((ulConfig & 0xf0) >> 4) << ulStep));
+
+ //
+ // Enable Digital Comparator if specified in the ulConfig bit-fields.
+ //
+ if(ulConfig & 0x000F0000)
+ {
+ //
+ // Program the comparator for the specified step.
+ //
+ ulTemp = HWREG(ulBase + ADC_SSDC);
+ ulTemp &= ~(0xF << ulStep);
+ ulTemp |= (((ulConfig & 0x00070000) >> 16) << ulStep);
+ HWREG(ulBase + ADC_SSDC) = ulTemp;
+
+ //
+ // Enable the comparator.
+ //
+ ulTemp = HWREG(ulBase + ADC_SSOP);
+ ulTemp |= (1 << ulStep);
+ HWREG(ulBase + ADC_SSOP) = ulTemp;
+ }
+
+ //
+ // Disable Digital Comparator if not specified.
+ //
+ else
+ {
+ ulTemp = HWREG(ulBase + ADC_SSOP);
+ ulTemp &= ~(1 << ulStep);
+ HWREG(ulBase + ADC_SSOP) = ulTemp;
+ }
+}
+
+//*****************************************************************************
+//
+//! Determines if a sample sequence overflow occurred.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulSequenceNum is the sample sequence number.
+//!
+//! This determines if a sample sequence overflow has occurred. This will
+//! happen if the captured samples are not read from the FIFO before the next
+//! trigger occurs.
+//!
+//! \return Returns zero if there was not an overflow, and non-zero if there
+//! was.
+//
+//*****************************************************************************
+long
+ADCSequenceOverflow(unsigned long ulBase, unsigned long ulSequenceNum)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulSequenceNum < 4);
+
+ //
+ // Determine if there was an overflow on this sequence.
+ //
+ return(HWREG(ulBase + ADC_O_OSTAT) & (1 << ulSequenceNum));
+}
+
+//*****************************************************************************
+//
+//! Clears the overflow condition on a sample sequence.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulSequenceNum is the sample sequence number.
+//!
+//! This will clear an overflow condition on one of the sample sequences. The
+//! overflow condition must be cleared in order to detect a subsequent overflow
+//! condition (it otherwise causes no harm).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCSequenceOverflowClear(unsigned long ulBase, unsigned long ulSequenceNum)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulSequenceNum < 4);
+
+ //
+ // Clear the overflow condition for this sequence.
+ //
+ HWREG(ulBase + ADC_O_OSTAT) = 1 << ulSequenceNum;
+}
+
+//*****************************************************************************
+//
+//! Determines if a sample sequence underflow occurred.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulSequenceNum is the sample sequence number.
+//!
+//! This determines if a sample sequence underflow has occurred. This will
+//! happen if too many samples are read from the FIFO.
+//!
+//! \return Returns zero if there was not an underflow, and non-zero if there
+//! was.
+//
+//*****************************************************************************
+long
+ADCSequenceUnderflow(unsigned long ulBase, unsigned long ulSequenceNum)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulSequenceNum < 4);
+
+ //
+ // Determine if there was an underflow on this sequence.
+ //
+ return(HWREG(ulBase + ADC_O_USTAT) & (1 << ulSequenceNum));
+}
+
+//*****************************************************************************
+//
+//! Clears the underflow condition on a sample sequence.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulSequenceNum is the sample sequence number.
+//!
+//! This will clear an underflow condition on one of the sample sequences. The
+//! underflow condition must be cleared in order to detect a subsequent
+//! underflow condition (it otherwise causes no harm).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCSequenceUnderflowClear(unsigned long ulBase, unsigned long ulSequenceNum)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulSequenceNum < 4);
+
+ //
+ // Clear the underflow condition for this sequence.
+ //
+ HWREG(ulBase + ADC_O_USTAT) = 1 << ulSequenceNum;
+}
+
+//*****************************************************************************
+//
+//! Gets the captured data for a sample sequence.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulSequenceNum is the sample sequence number.
+//! \param pulBuffer is the address where the data is stored.
+//!
+//! This function copies data from the specified sample sequence output FIFO to
+//! a memory resident buffer. The number of samples available in the hardware
+//! FIFO are copied into the buffer, which is assumed to be large enough to
+//! hold that many samples. This will only return the samples that are
+//! presently available, which may not be the entire sample sequence if it is
+//! in the process of being executed.
+//!
+//! \return Returns the number of samples copied to the buffer.
+//
+//*****************************************************************************
+long
+ADCSequenceDataGet(unsigned long ulBase, unsigned long ulSequenceNum,
+ unsigned long *pulBuffer)
+{
+ unsigned long ulCount;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulSequenceNum < 4);
+
+ //
+ // Get the offset of the sequence to be read.
+ //
+ ulBase += ADC_SEQ + (ADC_SEQ_STEP * ulSequenceNum);
+
+ //
+ // Read samples from the FIFO until it is empty.
+ //
+ ulCount = 0;
+ while(!(HWREG(ulBase + ADC_SSFSTAT) & ADC_SSFSTAT0_EMPTY) && (ulCount < 8))
+ {
+ //
+ // Read the FIFO and copy it to the destination.
+ //
+ *pulBuffer++ = HWREG(ulBase + ADC_SSFIFO);
+
+ //
+ // Increment the count of samples read.
+ //
+ ulCount++;
+ }
+
+ //
+ // Return the number of samples read.
+ //
+ return(ulCount);
+}
+
+//*****************************************************************************
+//
+//! Causes a processor trigger for a sample sequence.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulSequenceNum is the sample sequence number.
+//!
+//! This function triggers a processor-initiated sample sequence if the sample
+//! sequence trigger is configured to \b ADC_TRIGGER_PROCESSOR.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCProcessorTrigger(unsigned long ulBase, unsigned long ulSequenceNum)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulSequenceNum < 4);
+
+ //
+ // Generate a processor trigger for this sample sequence.
+ //
+ HWREG(ulBase + ADC_O_PSSI) = 1 << ulSequenceNum;
+}
+
+//*****************************************************************************
+//
+//! Configures the software oversampling factor of the ADC.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulSequenceNum is the sample sequence number.
+//! \param ulFactor is the number of samples to be averaged.
+//!
+//! This function configures the software oversampling for the ADC, which can
+//! be used to provide better resolution on the sampled data. Oversampling is
+//! accomplished by averaging multiple samples from the same analog input.
+//! Three different oversampling rates are supported; 2x, 4x, and 8x.
+//!
+//! Oversampling is only supported on the sample sequencers that are more than
+//! one sample in depth (that is, the fourth sample sequencer is not
+//! supported). Oversampling by 2x (for example) divides the depth of the
+//! sample sequencer by two; so 2x oversampling on the first sample sequencer
+//! can only provide four samples per trigger. This also means that 8x
+//! oversampling is only available on the first sample sequencer.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCSoftwareOversampleConfigure(unsigned long ulBase,
+ unsigned long ulSequenceNum,
+ unsigned long ulFactor)
+{
+ unsigned long ulValue;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulSequenceNum < 3);
+ ASSERT(((ulFactor == 2) || (ulFactor == 4) || (ulFactor == 8)) &&
+ ((ulSequenceNum == 0) || (ulFactor != 8)));
+
+ //
+ // Convert the oversampling factor to a shift factor.
+ //
+ for(ulValue = 0, ulFactor >>= 1; ulFactor; ulValue++, ulFactor >>= 1)
+ {
+ }
+
+ //
+ // Save the sfiht factor.
+ //
+ g_pucOversampleFactor[ulSequenceNum] = ulValue;
+}
+
+//*****************************************************************************
+//
+//! Configures a step of the software oversampled sequencer.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulSequenceNum is the sample sequence number.
+//! \param ulStep is the step to be configured.
+//! \param ulConfig is the configuration of this step.
+//!
+//! This function configures a step of the sample sequencer when using the
+//! software oversampling feature. The number of steps available depends on
+//! the oversampling factor set by ADCSoftwareOversampleConfigure(). The value
+//! of \e ulConfig is the same as defined for ADCSequenceStepConfigure().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCSoftwareOversampleStepConfigure(unsigned long ulBase,
+ unsigned long ulSequenceNum,
+ unsigned long ulStep,
+ unsigned long ulConfig)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulSequenceNum < 3);
+ ASSERT(((ulSequenceNum == 0) &&
+ (ulStep < (8 >> g_pucOversampleFactor[ulSequenceNum]))) ||
+ (ulStep < (4 >> g_pucOversampleFactor[ulSequenceNum])));
+
+ //
+ // Get the offset of the sequence to be configured.
+ //
+ ulBase += ADC_SEQ + (ADC_SEQ_STEP * ulSequenceNum);
+
+ //
+ // Compute the shift for the bits that control this step.
+ //
+ ulStep *= 4 << g_pucOversampleFactor[ulSequenceNum];
+
+ //
+ // Loop through the hardware steps that make up this step of the software
+ // oversampled sequence.
+ //
+ for(ulSequenceNum = 1 << g_pucOversampleFactor[ulSequenceNum];
+ ulSequenceNum; ulSequenceNum--)
+ {
+ //
+ // Set the analog mux value for this step.
+ //
+ HWREG(ulBase + ADC_SSMUX) = ((HWREG(ulBase + ADC_SSMUX) &
+ ~(0x0000000f << ulStep)) |
+ ((ulConfig & 0x0f) << ulStep));
+
+ //
+ // Set the control value for this step.
+ //
+ HWREG(ulBase + ADC_SSCTL) = ((HWREG(ulBase + ADC_SSCTL) &
+ ~(0x0000000f << ulStep)) |
+ (((ulConfig & 0xf0) >> 4) << ulStep));
+ if(ulSequenceNum != 1)
+ {
+ HWREG(ulBase + ADC_SSCTL) &= ~((ADC_SSCTL0_IE0 |
+ ADC_SSCTL0_END0) << ulStep);
+ }
+
+ //
+ // Go to the next hardware step.
+ //
+ ulStep += 4;
+ }
+}
+
+//*****************************************************************************
+//
+//! Gets the captured data for a sample sequence using software oversampling.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulSequenceNum is the sample sequence number.
+//! \param pulBuffer is the address where the data is stored.
+//! \param ulCount is the number of samples to be read.
+//!
+//! This function copies data from the specified sample sequence output FIFO to
+//! a memory resident buffer with software oversampling applied. The requested
+//! number of samples are copied into the data buffer; if there are not enough
+//! samples in the hardware FIFO to satisfy this many oversampled data items
+//! then incorrect results will be returned. It is the caller's responsibility
+//! to read only the samples that are available and wait until enough data is
+//! available, for example as a result of receiving an interrupt.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCSoftwareOversampleDataGet(unsigned long ulBase, unsigned long ulSequenceNum,
+ unsigned long *pulBuffer, unsigned long ulCount)
+{
+ unsigned long ulIdx, ulAccum;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulSequenceNum < 3);
+ ASSERT(((ulSequenceNum == 0) &&
+ (ulCount < (8 >> g_pucOversampleFactor[ulSequenceNum]))) ||
+ (ulCount < (4 >> g_pucOversampleFactor[ulSequenceNum])));
+
+ //
+ // Get the offset of the sequence to be read.
+ //
+ ulBase += ADC_SEQ + (ADC_SEQ_STEP * ulSequenceNum);
+
+ //
+ // Read the samples from the FIFO until it is empty.
+ //
+ while(ulCount--)
+ {
+ //
+ // Compute the sum of the samples.
+ //
+ ulAccum = 0;
+ for(ulIdx = 1 << g_pucOversampleFactor[ulSequenceNum]; ulIdx; ulIdx--)
+ {
+ //
+ // Read the FIFO and add it to the accumulator.
+ //
+ ulAccum += HWREG(ulBase + ADC_SSFIFO);
+ }
+
+ //
+ // Write the averaged sample to the output buffer.
+ //
+ *pulBuffer++ = ulAccum >> g_pucOversampleFactor[ulSequenceNum];
+ }
+}
+
+//*****************************************************************************
+//
+//! Configures the hardware oversampling factor of the ADC.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulFactor is the number of samples to be averaged.
+//!
+//! This function configures the hardware oversampling for the ADC, which can
+//! be used to provide better resolution on the sampled data. Oversampling is
+//! accomplished by averaging multiple samples from the same analog input. Six
+//! different oversampling rates are supported; 2x, 4x, 8x, 16x, 32x, and 64x.
+//! Specifying an oversampling factor of zero will disable hardware
+//! oversampling.
+//!
+//! Hardware oversampling applies uniformly to all sample sequencers. It does
+//! not reduce the depth of the sample sequencers like the software
+//! oversampling APIs; each sample written into the sample sequence FIFO is a
+//! fully oversampled analog input reading.
+//!
+//! Enabling hardware averaging increases the precision of the ADC at the cost
+//! of throughput. For example, enabling 4x oversampling reduces the
+//! throughput of a 250 Ksps ADC to 62.5 Ksps.
+//!
+//! \note Hardware oversampling is available beginning with Rev C0 of the
+//! Stellaris microcontroller.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCHardwareOversampleConfigure(unsigned long ulBase, unsigned long ulFactor)
+{
+ unsigned long ulValue;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(((ulFactor == 0) || (ulFactor == 2) || (ulFactor == 4) ||
+ (ulFactor == 8) || (ulFactor == 16) || (ulFactor == 32) ||
+ (ulFactor == 64)));
+
+ //
+ // Convert the oversampling factor to a shift factor.
+ //
+ for(ulValue = 0, ulFactor >>= 1; ulFactor; ulValue++, ulFactor >>= 1)
+ {
+ }
+
+ //
+ // Write the shift factor to the ADC to configure the hardware oversampler.
+ //
+ HWREG(ulBase + ADC_O_SAC) = ulValue;
+}
+
+//*****************************************************************************
+//
+//! Configures an ADC Digital Comparator.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulComp is the index of the comparator to configure.
+//! \param ulConfig is the configuration of the comparator.
+//!
+//! This function will configure a comparator. The \e ulConfig parameter is
+//! the result of a logical OR operation between the \b ADC_COMP_TRIG_xxx, and
+//! \b ADC_COMP_INT_xxx values.
+//!
+//! The \b ADC_COMP_TRIG_xxx term can take on the following values:
+//!
+//! - \b ADC_COMP_TRIG_NONE to never trigger PWM fault condition.
+//! - \b ADC_COMP_TRIG_LOW_ALWAYS to always trigger PWM fault condition when
+//! ADC output is in the low-band.
+//! - \b ADC_COMP_TRIG_LOW_ONCE to trigger PWM fault condition once when ADC
+//! output transitions into the low-band.
+//! - \b ADC_COMP_TRIG_LOW_HALWAYS to always trigger PWM fault condition when
+//! ADC output is in the low-band only if ADC output has been in the high-band
+//! since the last trigger output.
+//! - \b ADC_COMP_TRIG_LOW_HONCE to trigger PWM fault condition once when ADC
+//! output transitions into low-band only if ADC output has been in the
+//! high-band since the last trigger output.
+//! - \b ADC_COMP_TRIG_MID_ALWAYS to always trigger PWM fault condition when
+//! ADC output is in the mid-band.
+//! - \b ADC_COMP_TRIG_MID_ONCE to trigger PWM fault condition once when ADC
+//! output transitions into the mid-band.
+//! - \b ADC_COMP_TRIG_HIGH_ALWAYS to always trigger PWM fault condition when
+//! ADC output is in the high-band.
+//! - \b ADC_COMP_TRIG_HIGH_ONCE to trigger PWM fault condition once when ADC
+//! output transitions into the high-band.
+//! - \b ADC_COMP_TRIG_HIGH_HALWAYS to always trigger PWM fault condition when
+//! ADC output is in the high-band only if ADC output has been in the low-band
+//! since the last trigger output.
+//! - \b ADC_COMP_TRIG_HIGH_HONCE to trigger PWM fault condition once when ADC
+//! output transitions into high-band only if ADC output has been in the
+//! low-band since the last trigger output.
+//!
+//! The \b ADC_COMP_INT_xxx term can take on the following values:
+//!
+//! - \b ADC_COMP_INT_NONE to never generate ADC interrupt.
+//! - \b ADC_COMP_INT_LOW_ALWAYS to always generate ADC interrupt when ADC
+//! output is in the low-band.
+//! - \b ADC_COMP_INT_LOW_ONCE to generate ADC interrupt once when ADC output
+//! transitions into the low-band.
+//! - \b ADC_COMP__INT_LOW_HALWAYS to always generate ADC interrupt when ADC
+//! output is in the low-band only if ADC output has been in the high-band
+//! since the last trigger output.
+//! - \b ADC_COMP_INT_LOW_HONCE to generate ADC interrupt once when ADC output
+//! transitions into low-band only if ADC output has been in the high-band
+//! since the last trigger output.
+//! - \b ADC_COMP_INT_MID_ALWAYS to always generate ADC interrupt when ADC
+//! output is in the mid-band.
+//! - \b ADC_COMP_INT_MID_ONCE to generate ADC interrupt once when ADC output
+//! transitions into the mid-band.
+//! - \b ADC_COMP_INT_HIGH_ALWAYS to always generate ADC interrupt when ADC
+//! output is in the high-band.
+//! - \b ADC_COMP_INT_HIGH_ONCE to generate ADC interrupt once when ADC output
+//! transitions into the high-band.
+//! - \b ADC_COMP_INT_HIGH_HALWAYS to always generate ADC interrupt when ADC
+//! output is in the high-band only if ADC output has been in the low-band
+//! since the last trigger output.
+//! - \b ADC_COMP_INT_HIGH_HONCE to generate ADC interrupt once when ADC output
+//! transitions into high-band only if ADC output has been in the low-band
+//! since the last trigger output.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCComparatorConfigure(unsigned long ulBase, unsigned long ulComp,
+ unsigned long ulConfig)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulComp < 8);
+
+ //
+ // Save the new setting.
+ //
+ HWREG(ulBase + ADC_O_DCCTL0 + (ulComp * 4)) = ulConfig;
+}
+
+//*****************************************************************************
+//
+//! Define the ADC Digital Comparator Regions.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulComp is the index of the comparator to configure.
+//! \param ulLowRef is the reference point for the low/mid band threshold.
+//! \param ulHighRef is the reference point for the mid/high band threshold.
+//!
+//! The ADC Digital Comparator operation is based on three ADC value regions:
+//! - \b low-band is defined as any ADC value less than or equal to the
+//! \e ulLowRef value.
+//! - \b mid-band is defined as any ADC value greater than the \e ulLowRef
+//! value but less than or equal to the \e ulHighRef value.
+//! - \b high-band is defined as any ADC value greater than the \e ulHighRef
+//! value.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCComparatorRegionSet(unsigned long ulBase, unsigned long ulComp,
+ unsigned long ulLowRef, unsigned long ulHighRef)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulComp < 8);
+ ASSERT((ulLowRef < 1024) && (ulLowRef <= ulHighRef));
+ ASSERT(ulHighRef < 1024);
+
+ //
+ // Save the new region settings.
+ //
+ HWREG(ulBase + ADC_O_DCCMP0 + (ulComp * 4)) = (ulHighRef << 16) | ulLowRef;
+}
+
+//*****************************************************************************
+//
+//! Resets the current ADC Digital Comparator conditions.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulComp is the index of the comparator.
+//! \param bTrigger is the flag to indicate reset of Trigger conditions.
+//! \param bInterrupt is the flag to indicate reset of Interrupt conditions.
+//!
+//! Because the Digital Comparator uses current and previous ADC values, this
+//! function is provide to allow the comparator to be reset to its initial
+//! value to prevent stale data from being used when a sequence is enabled.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCComparatorReset(unsigned long ulBase, unsigned long ulComp,
+ tBoolean bTrigger, tBoolean bInterrupt)
+{
+ unsigned long ulTemp = 0;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulComp < 8);
+
+ //
+ // Set the appropriate bits to reset the trigger and/or interrupt
+ // comparator conditions.
+ //
+ if(bTrigger)
+ {
+ ulTemp |= (1 << (16 + ulComp));
+ }
+ if(bInterrupt)
+ {
+ ulTemp |= (1 << ulComp);
+ }
+
+ HWREG(ulBase + ADC_O_DCRIC) = ulTemp;
+}
+
+//*****************************************************************************
+//
+//! Disables a sample sequence comparator interrupt.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulSequenceNum is the sample sequence number.
+//!
+//! This function disables the requested sample sequence comparator interrupt.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCComparatorIntDisable(unsigned long ulBase, unsigned long ulSequenceNum)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulSequenceNum < 4);
+
+ //
+ // Disable this sample sequence comparator interrupt.
+ //
+ HWREG(ulBase + ADC_O_IM) &= ~(0x10000 << ulSequenceNum);
+}
+
+//*****************************************************************************
+//
+//! Enables a sample sequence comparator interrupt.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulSequenceNum is the sample sequence number.
+//!
+//! This function enables the requested sample sequence comparator interrupt.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCComparatorIntEnable(unsigned long ulBase, unsigned long ulSequenceNum)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulSequenceNum < 4);
+
+ //
+ // Enable this sample sequence interrupt.
+ //
+ HWREG(ulBase + ADC_O_IM) |= 0x10000 << ulSequenceNum;
+}
+
+//*****************************************************************************
+//
+//! Gets the current comparator interrupt status.
+//!
+//! \param ulBase is the base address of the ADC module.
+//!
+//! This returns the Digitial Comparator interrupt status bits. This status
+//! is sequence agnostic.
+//!
+//! \return The current comparator interrupt status.
+//
+//*****************************************************************************
+unsigned long
+ADCComparatorIntStatus(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+
+ //
+ // Return the digitial comparator interrupt status.
+ //
+ return(HWREG(ulBase + ADC_O_DCISC));
+}
+
+//*****************************************************************************
+//
+//! Clears sample sequence comparator interrupt source.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulStatus is the bit-mapped interrupts status to clear.
+//!
+//! The specified interrupt status is cleared.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCComparatorIntClear(unsigned long ulBase, unsigned long ulStatus)
+{
+ //
+ // Check the arugments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+
+ //
+ // Clear the interrupt.
+ //
+ HWREG(ulBase + ADC_O_DCISC) = ulStatus;
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
Property changes on: branches/eagle_mmc/src/platform/lm3s/adc.c
___________________________________________________________________
Name: svn:executable
+ *
Modified: branches/eagle_mmc/src/platform/lm3s/adc.h
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/adc.h 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lm3s/adc.h 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,141 +1,216 @@
-//*****************************************************************************
-//
-// adc.h - ADC headers for using the ADC driver functions.
-//
-// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
-// Software License Agreement
-//
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
-//
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws. All rights are reserved. You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program. Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
-//
-// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-//
-// This is part of revision 3740 of the Stellaris Peripheral Driver Library.
-//
-//*****************************************************************************
-
-#ifndef __ADC_H__
-#define __ADC_H__
-
-//*****************************************************************************
-//
-// If building with a C++ compiler, make all of the definitions in this header
-// have a C binding.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-//*****************************************************************************
-//
-// Values that can be passed to ADCSequenceConfigure as the ulTrigger
-// parameter.
-//
-//*****************************************************************************
-#define ADC_TRIGGER_PROCESSOR 0x00000000 // Processor event
-#define ADC_TRIGGER_COMP0 0x00000001 // Analog comparator 0 event
-#define ADC_TRIGGER_COMP1 0x00000002 // Analog comparator 1 event
-#define ADC_TRIGGER_COMP2 0x00000003 // Analog comparator 2 event
-#define ADC_TRIGGER_EXTERNAL 0x00000004 // External event
-#define ADC_TRIGGER_TIMER 0x00000005 // Timer event
-#define ADC_TRIGGER_PWM0 0x00000006 // PWM0 event
-#define ADC_TRIGGER_PWM1 0x00000007 // PWM1 event
-#define ADC_TRIGGER_PWM2 0x00000008 // PWM2 event
-#define ADC_TRIGGER_ALWAYS 0x0000000F // Always event
-
-//*****************************************************************************
-//
-// Values that can be passed to ADCSequenceStepConfigure as the ulConfig
-// parameter.
-//
-//*****************************************************************************
-#define ADC_CTL_TS 0x00000080 // Temperature sensor select
-#define ADC_CTL_IE 0x00000040 // Interrupt enable
-#define ADC_CTL_END 0x00000020 // Sequence end select
-#define ADC_CTL_D 0x00000010 // Differential select
-#define ADC_CTL_CH0 0x00000000 // Input channel 0
-#define ADC_CTL_CH1 0x00000001 // Input channel 1
-#define ADC_CTL_CH2 0x00000002 // Input channel 2
-#define ADC_CTL_CH3 0x00000003 // Input channel 3
-#define ADC_CTL_CH4 0x00000004 // Input channel 4
-#define ADC_CTL_CH5 0x00000005 // Input channel 5
-#define ADC_CTL_CH6 0x00000006 // Input channel 6
-#define ADC_CTL_CH7 0x00000007 // Input channel 7
-
-//*****************************************************************************
-//
-// Prototypes for the APIs.
-//
-//*****************************************************************************
-extern void ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum,
- void (*pfnHandler)(void));
-extern void ADCIntUnregister(unsigned long ulBase,
- unsigned long ulSequenceNum);
-extern void ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum);
-extern void ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum);
-extern unsigned long ADCIntStatus(unsigned long ulBase,
- unsigned long ulSequenceNum,
- tBoolean bMasked);
-extern void ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum);
-extern void ADCSequenceEnable(unsigned long ulBase,
- unsigned long ulSequenceNum);
-extern void ADCSequenceDisable(unsigned long ulBase,
- unsigned long ulSequenceNum);
-extern void ADCSequenceConfigure(unsigned long ulBase,
- unsigned long ulSequenceNum,
- unsigned long ulTrigger,
- unsigned long ulPriority);
-extern void ADCSequenceStepConfigure(unsigned long ulBase,
- unsigned long ulSequenceNum,
- unsigned long ulStep,
- unsigned long ulConfig);
-extern long ADCSequenceOverflow(unsigned long ulBase,
- unsigned long ulSequenceNum);
-extern void ADCSequenceOverflowClear(unsigned long ulBase,
- unsigned long ulSequenceNum);
-extern long ADCSequenceUnderflow(unsigned long ulBase,
- unsigned long ulSequenceNum);
-extern void ADCSequenceUnderflowClear(unsigned long ulBase,
- unsigned long ulSequenceNum);
-extern long ADCSequenceDataGet(unsigned long ulBase,
- unsigned long ulSequenceNum,
- unsigned long *pulBuffer);
-extern void ADCProcessorTrigger(unsigned long ulBase,
- unsigned long ulSequenceNum);
-extern void ADCSoftwareOversampleConfigure(unsigned long ulBase,
- unsigned long ulSequenceNum,
- unsigned long ulFactor);
-extern void ADCSoftwareOversampleStepConfigure(unsigned long ulBase,
- unsigned long ulSequenceNum,
- unsigned long ulStep,
- unsigned long ulConfig);
-extern void ADCSoftwareOversampleDataGet(unsigned long ulBase,
- unsigned long ulSequenceNum,
- unsigned long *pulBuffer,
- unsigned long ulCount);
-extern void ADCHardwareOversampleConfigure(unsigned long ulBase,
- unsigned long ulFactor);
-
-//*****************************************************************************
-//
-// Mark the end of the C bindings section for C++ compilers.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-}
-#endif
-
-#endif // __ADC_H__
+//*****************************************************************************
+//
+// adc.h - ADC headers for using the ADC driver functions.
+//
+// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __ADC_H__
+#define __ADC_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to ADCSequenceConfigure as the ulTrigger
+// parameter.
+//
+//*****************************************************************************
+#define ADC_TRIGGER_PROCESSOR 0x00000000 // Processor event
+#define ADC_TRIGGER_COMP0 0x00000001 // Analog comparator 0 event
+#define ADC_TRIGGER_COMP1 0x00000002 // Analog comparator 1 event
+#define ADC_TRIGGER_COMP2 0x00000003 // Analog comparator 2 event
+#define ADC_TRIGGER_EXTERNAL 0x00000004 // External event
+#define ADC_TRIGGER_TIMER 0x00000005 // Timer event
+#define ADC_TRIGGER_PWM0 0x00000006 // PWM0 event
+#define ADC_TRIGGER_PWM1 0x00000007 // PWM1 event
+#define ADC_TRIGGER_PWM2 0x00000008 // PWM2 event
+#define ADC_TRIGGER_ALWAYS 0x0000000F // Always event
+
+//*****************************************************************************
+//
+// Values that can be passed to ADCSequenceStepConfigure as the ulConfig
+// parameter.
+//
+//*****************************************************************************
+#define ADC_CTL_TS 0x00000080 // Temperature sensor select
+#define ADC_CTL_IE 0x00000040 // Interrupt enable
+#define ADC_CTL_END 0x00000020 // Sequence end select
+#define ADC_CTL_D 0x00000010 // Differential select
+#define ADC_CTL_CH0 0x00000000 // Input channel 0
+#define ADC_CTL_CH1 0x00000001 // Input channel 1
+#define ADC_CTL_CH2 0x00000002 // Input channel 2
+#define ADC_CTL_CH3 0x00000003 // Input channel 3
+#define ADC_CTL_CH4 0x00000004 // Input channel 4
+#define ADC_CTL_CH5 0x00000005 // Input channel 5
+#define ADC_CTL_CH6 0x00000006 // Input channel 6
+#define ADC_CTL_CH7 0x00000007 // Input channel 7
+#define ADC_CTL_CH8 0x00000008 // Input channel 8
+#define ADC_CTL_CH9 0x00000009 // Input channel 9
+#define ADC_CTL_CH10 0x0000000A // Input channel 10
+#define ADC_CTL_CH11 0x0000000B // Input channel 11
+#define ADC_CTL_CH12 0x0000000C // Input channel 12
+#define ADC_CTL_CH13 0x0000000D // Input channel 13
+#define ADC_CTL_CH14 0x0000000E // Input channel 14
+#define ADC_CTL_CH15 0x0000000F // Input channel 15
+#define ADC_CTL_CMP0 0x00080000 // Select Comparator 0
+#define ADC_CTL_CMP1 0x00090000 // Select Comparator 1
+#define ADC_CTL_CMP2 0x000A0000 // Select Comparator 2
+#define ADC_CTL_CMP3 0x000B0000 // Select Comparator 3
+#define ADC_CTL_CMP4 0x000C0000 // Select Comparator 4
+#define ADC_CTL_CMP5 0x000D0000 // Select Comparator 5
+#define ADC_CTL_CMP6 0x000E0000 // Select Comparator 6
+#define ADC_CTL_CMP7 0x000F0000 // Select Comparator 7
+
+//*****************************************************************************
+//
+// Values that can be passed to ADCComparatorConfigure as part of the
+// ulConfig parameter.
+//
+//*****************************************************************************
+#define ADC_COMP_TRIG_NONE 0x00000000 // Trigger Disabled
+#define ADC_COMP_TRIG_LOW_ALWAYS \
+ 0x00001000 // Trigger Low Always
+#define ADC_COMP_TRIG_LOW_ONCE 0x00001100 // Trigger Low Once
+#define ADC_COMP_TRIG_LOW_HALWAYS \
+ 0x00001200 // Trigger Low Always (Hysteresis)
+#define ADC_COMP_TRIG_LOW_HONCE 0x00001300 // Trigger Low Once (Hysteresis)
+#define ADC_COMP_TRIG_MID_ALWAYS \
+ 0x00001400 // Trigger Mid Always
+#define ADC_COMP_TRIG_MID_ONCE 0x00001500 // Trigger Mid Once
+#define ADC_COMP_TRIG_HIGH_ALWAYS \
+ 0x00001C00 // Trigger High Always
+#define ADC_COMP_TRIG_HIGH_ONCE 0x00001D00 // Trigger High Once
+#define ADC_COMP_TRIG_HIGH_HALWAYS \
+ 0x00001E00 // Trigger High Always (Hysteresis)
+#define ADC_COMP_TRIG_HIGH_HONCE \
+ 0x00001F00 // Trigger High Once (Hysteresis)
+
+#define ADC_COMP_INT_NONE 0x00000000 // Interrupt Disabled
+#define ADC_COMP_INT_LOW_ALWAYS \
+ 0x00000010 // Interrupt Low Always
+#define ADC_COMP_INT_LOW_ONCE 0x00000011 // Interrupt Low Once
+#define ADC_COMP_INT_LOW_HALWAYS \
+ 0x00000012 // Interrupt Low Always
+ // (Hysteresis)
+#define ADC_COMP_INT_LOW_HONCE 0x00000013 // Interrupt Low Once (Hysteresis)
+#define ADC_COMP_INT_MID_ALWAYS \
+ 0x00000014 // Interrupt Mid Always
+#define ADC_COMP_INT_MID_ONCE 0x00000015 // Interrupt Mid Once
+#define ADC_COMP_INT_HIGH_ALWAYS \
+ 0x0000001C // Interrupt High Always
+#define ADC_COMP_INT_HIGH_ONCE 0x0000001D // Interrupt High Once
+#define ADC_COMP_INT_HIGH_HALWAYS \
+ 0x0000001E // Interrupt High Always
+ // (Hysteresis)
+#define ADC_COMP_INT_HIGH_HONCE \
+ 0x0000001F // Interrupt High Once (Hysteresis)
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern void ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum,
+ void (*pfnHandler)(void));
+extern void ADCIntUnregister(unsigned long ulBase,
+ unsigned long ulSequenceNum);
+extern void ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum);
+extern void ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum);
+extern unsigned long ADCIntStatus(unsigned long ulBase,
+ unsigned long ulSequenceNum,
+ tBoolean bMasked);
+extern void ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum);
+extern void ADCSequenceEnable(unsigned long ulBase,
+ unsigned long ulSequenceNum);
+extern void ADCSequenceDisable(unsigned long ulBase,
+ unsigned long ulSequenceNum);
+extern void ADCSequenceConfigure(unsigned long ulBase,
+ unsigned long ulSequenceNum,
+ unsigned long ulTrigger,
+ unsigned long ulPriority);
+extern void ADCSequenceStepConfigure(unsigned long ulBase,
+ unsigned long ulSequenceNum,
+ unsigned long ulStep,
+ unsigned long ulConfig);
+extern long ADCSequenceOverflow(unsigned long ulBase,
+ unsigned long ulSequenceNum);
+extern void ADCSequenceOverflowClear(unsigned long ulBase,
+ unsigned long ulSequenceNum);
+extern long ADCSequenceUnderflow(unsigned long ulBase,
+ unsigned long ulSequenceNum);
+extern void ADCSequenceUnderflowClear(unsigned long ulBase,
+ unsigned long ulSequenceNum);
+extern long ADCSequenceDataGet(unsigned long ulBase,
+ unsigned long ulSequenceNum,
+ unsigned long *pulBuffer);
+extern void ADCProcessorTrigger(unsigned long ulBase,
+ unsigned long ulSequenceNum);
+extern void ADCSoftwareOversampleConfigure(unsigned long ulBase,
+ unsigned long ulSequenceNum,
+ unsigned long ulFactor);
+extern void ADCSoftwareOversampleStepConfigure(unsigned long ulBase,
+ unsigned long ulSequenceNum,
+ unsigned long ulStep,
+ unsigned long ulConfig);
+extern void ADCSoftwareOversampleDataGet(unsigned long ulBase,
+ unsigned long ulSequenceNum,
+ unsigned long *pulBuffer,
+ unsigned long ulCount);
+extern void ADCHardwareOversampleConfigure(unsigned long ulBase,
+ unsigned long ulFactor);
+extern void ADCComparatorConfigure(unsigned long ulBase, unsigned long ulComp,
+ unsigned long ulConfig);
+extern void ADCComparatorRegionSet(unsigned long ulBase, unsigned long ulComp,
+ unsigned long ulLowRef,
+ unsigned long ulHighRef);
+extern void ADCComparatorReset(unsigned long ulBase, unsigned long ulComp,
+ tBoolean bTrigger, tBoolean bInterrupt);
+extern void ADCComparatorIntDisable(unsigned long ulBase,
+ unsigned long ulSequenceNum);
+extern void ADCComparatorIntEnable(unsigned long ulBase,
+ unsigned long ulSequenceNum);
+extern unsigned long ADCComparatorIntStatus(unsigned long ulBase);
+extern void ADCComparatorIntClear(unsigned long ulBase,
+ unsigned long ulStatus);
+
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __ADC_H__
Property changes on: branches/eagle_mmc/src/platform/lm3s/adc.h
___________________________________________________________________
Name: svn:executable
+ *
Added: branches/eagle_mmc/src/platform/lm3s/can.c
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/can.c 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lm3s/can.c 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,2203 @@
+//*****************************************************************************
+//
+// can.c - Driver for the CAN module.
+//
+// Copyright (c) 2006-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup can_api
+//! @{
+//
+//*****************************************************************************
+
+#include "hw_can.h"
+#include "hw_ints.h"
+#include "hw_nvic.h"
+#include "hw_memmap.h"
+#include "hw_types.h"
+#include "can.h"
+#include "debug.h"
+#include "interrupt.h"
+
+//*****************************************************************************
+//
+// This is the maximum number that can be stored as an 11bit Message
+// identifier.
+//
+//*****************************************************************************
+#define CAN_MAX_11BIT_MSG_ID (0x7ff)
+
+//*****************************************************************************
+//
+// This is used as the loop delay for accessing the CAN controller registers.
+//
+//*****************************************************************************
+#define CAN_RW_DELAY (5)
+
+//
+// The maximum CAN bit timing divisor is 13.
+//
+#define CAN_MAX_BIT_DIVISOR (13)
+
+//
+// The minimum CAN bit timing divisor is 5.
+//
+#define CAN_MIN_BIT_DIVISOR (5)
+
+//
+// The maximum CAN pre-divisor is 1024.
+//
+#define CAN_MAX_PRE_DIVISOR (1024)
+
+//
+// The minimum CAN pre-divisor is 1024.
+//
+#define CAN_MIN_PRE_DIVISOR (1024)
+
+//*****************************************************************************
+//
+// This table is used by the CANBitRateSet() API as the register defaults for
+// the bit timing values.
+//
+//*****************************************************************************
+static const unsigned short g_usCANBitValues[] =
+{
+ 0x1100, // TSEG2 2, TSEG1 2, SJW 1, Divide 5
+ 0x1200, // TSEG2 2, TSEG1 3, SJW 1, Divide 6
+ 0x2240, // TSEG2 3, TSEG1 3, SJW 2, Divide 7
+ 0x2340, // TSEG2 3, TSEG1 4, SJW 2, Divide 8
+ 0x3340, // TSEG2 4, TSEG1 4, SJW 2, Divide 9
+ 0x3440, // TSEG2 4, TSEG1 5, SJW 2, Divide 10
+ 0x3540, // TSEG2 4, TSEG1 6, SJW 2, Divide 11
+ 0x3640, // TSEG2 4, TSEG1 7, SJW 2, Divide 12
+ 0x3740 // TSEG2 4, TSEG1 8, SJW 2, Divide 13
+};
+
+//*****************************************************************************
+//
+//! \internal
+//! Checks a CAN base address.
+//!
+//! \param ulBase is the base address of the CAN controller.
+//!
+//! This function determines if a CAN controller base address is valid.
+//!
+//! \return Returns \b true if the base address is valid and \b false
+//! otherwise.
+//
+//*****************************************************************************
+#ifdef DEBUG
+static tBoolean
+CANBaseValid(unsigned long ulBase)
+{
+ return((ulBase == CAN0_BASE) || (ulBase == CAN1_BASE) ||
+ (ulBase == CAN2_BASE));
+}
+#endif
+
+//*****************************************************************************
+//
+//! \internal
+//!
+//! Returns the CAN controller interrupt number.
+//!
+//! \param ulBase is the base address of the selected CAN controller
+//!
+//! Given a CAN controller base address, returns the corresponding interrupt
+//! number.
+//!
+//! This function replaces the original CANGetIntNumber() API and performs the
+//! same actions. A macro is provided in <tt>can.h</tt> to map the original
+//! API to this API.
+//!
+//! \return Returns a CAN interrupt number, or -1 if \e ulPort is invalid.
+//
+//*****************************************************************************
+static long
+CANIntNumberGet(unsigned long ulBase)
+{
+ long lIntNumber;
+
+ //
+ // Return the interrupt number for the given CAN controller.
+ //
+ switch(ulBase)
+ {
+ //
+ // Return the interrupt number for CAN 0
+ //
+ case CAN0_BASE:
+ {
+ lIntNumber = INT_CAN0;
+ break;
+ }
+
+ //
+ // Return the interrupt number for CAN 1
+ //
+ case CAN1_BASE:
+ {
+ lIntNumber = INT_CAN1;
+ break;
+ }
+
+ //
+ // Return the interrupt number for CAN 2
+ //
+ case CAN2_BASE:
+ {
+ lIntNumber = INT_CAN2;
+ break;
+ }
+
+ //
+ // Return -1 to indicate a bad address was passed in.
+ //
+ default:
+ {
+ lIntNumber = -1;
+ }
+ }
+ return(lIntNumber);
+}
+
+//*****************************************************************************
+//
+//! \internal
+//!
+//! Reads a CAN controller register.
+//!
+//! \param ulRegAddress is the full address of the CAN register to be read.
+//!
+//! This function performs the necessary synchronization to read from a CAN
+//! controller register.
+//!
+//! This function replaces the original CANReadReg() API and performs the same
+//! actions. A macro is provided in <tt>can.h</tt> to map the original API to
+//! this API.
+//!
+//! \note This function provides the delay required to access CAN registers.
+//! This delay is required when accessing CAN registers directly.
+//!
+//! \return Returns the value read from the register.
+//
+//*****************************************************************************
+static unsigned long
+CANRegRead(unsigned long ulRegAddress)
+{
+ volatile int iDelay;
+ unsigned long ulRetVal;
+ unsigned long ulIntNumber;
+ unsigned long ulReenableInts;
+
+ //
+ // Get the CAN interrupt number from the register base address.
+ //
+ ulIntNumber = CANIntNumberGet(ulRegAddress & 0xfffff000);
+
+ //
+ // Make sure that the CAN base address was valid.
+ //
+ ASSERT(ulIntNumber != (unsigned long)-1);
+
+ //
+ // Remember current state so that CAN interrupts are only re-enabled if
+ // they were already enabled.
+ //
+ ulReenableInts = HWREG(NVIC_EN1) & (1 << (ulIntNumber - 48));
+
+ //
+ // If the CAN interrupt was enabled then disable it.
+ //
+ if(ulReenableInts)
+ {
+ IntDisable(ulIntNumber);
+ }
+
+ //
+ // Trigger the inital read to the CAN controller. The value returned at
+ // this point is not valid.
+ //
+ HWREG(ulRegAddress);
+
+ //
+ // This delay is necessary for the CAN have the correct data on the bus.
+ //
+ for(iDelay = 0; iDelay < CAN_RW_DELAY; iDelay++)
+ {
+ }
+
+ //
+ // Do the final read that has the valid value of the register.
+ //
+ ulRetVal = HWREG(ulRegAddress);
+
+ //
+ // Reenable CAN interrupts if they were enabled before this call.
+ //
+ if(ulReenableInts)
+ {
+ IntEnable(ulIntNumber);
+ }
+
+ return(ulRetVal);
+}
+
+//*****************************************************************************
+//
+//! \internal
+//!
+//! Writes a CAN controller register.
+//!
+//! \param ulRegAddress is the full address of the CAN register to be written.
+//! \param ulRegValue is the value to write into the register specified by
+//! \e ulRegAddress.
+//!
+//! This function takes care of the synchronization necessary to write to a
+//! CAN controller register.
+//!
+//! This function replaces the original CANWriteReg() API and performs the same
+//! actions. A macro is provided in <tt>can.h</tt> to map the original API to
+//! this API.
+//!
+//! \note The delays in this function are required when accessing CAN registers
+//! directly.
+//!
+//! \return None.
+//
+//*****************************************************************************
+static void
+CANRegWrite(unsigned long ulRegAddress, unsigned long ulRegValue)
+{
+ volatile int iDelay;
+
+ //
+ // Trigger the inital write to the CAN controller. The value will not make
+ // it out to the CAN controller for CAN_RW_DELAY cycles.
+ //
+ HWREG(ulRegAddress) = ulRegValue;
+
+ //
+ // Delay to allow the CAN controller to receive the new data.
+ //
+ for(iDelay = 0; iDelay < CAN_RW_DELAY; iDelay++)
+ {
+ }
+}
+
+//*****************************************************************************
+//
+//! \internal
+//!
+//! Copies data from a buffer to the CAN Data registers.
+//!
+//! \param pucData is a pointer to the data to be written out to the CAN
+//! controller's data registers.
+//! \param pulRegister is an unsigned long pointer to the first register of the
+//! CAN controller's data registers. For example, in order to use the IF1
+//! register set on CAN controller 0, the value would be: \b CAN0_BASE \b +
+//! \b CAN_O_IF1DA1.
+//! \param iSize is the number of bytes to copy into the CAN controller.
+//!
+//! This function takes the steps necessary to copy data from a contiguous
+//! buffer in memory into the non-contiguous data registers used by the CAN
+//! controller. This function is rarely used outside of the CANMessageSet()
+//! function.
+//!
+//! This function replaces the original CANWriteDataReg() API and performs the
+//! same actions. A macro is provided in <tt>can.h</tt> to map the original
+//! API to this API.
+//!
+//! \return None.
+//
+//*****************************************************************************
+static void
+CANDataRegWrite(unsigned char *pucData, unsigned long *pulRegister, int iSize)
+{
+ int iIdx;
+ unsigned long ulValue;
+
+ //
+ // Loop always copies 1 or 2 bytes per iteration.
+ //
+ for(iIdx = 0; iIdx < iSize; )
+ {
+
+ //
+ // Write out the data 16 bits at a time since this is how the registers
+ // are aligned in memory.
+ //
+ ulValue = pucData[iIdx++];
+
+ //
+ // Only write the second byte if needed otherwise it will be zero.
+ //
+ if(iIdx < iSize)
+ {
+ ulValue |= (pucData[iIdx++] << 8);
+ }
+ CANRegWrite((unsigned long)(pulRegister++), ulValue);
+ }
+}
+
+//*****************************************************************************
+//
+//! \internal
+//!
+//! Copies data from a buffer to the CAN Data registers.
+//!
+//! \param pucData is a pointer to the location to store the data read from the
+//! CAN controller's data registers.
+//! \param pulRegister is an unsigned long pointer to the first register of the
+//! CAN controller's data registers. For example, in order to use the IF1
+//! register set on CAN controller 1, the value would be: \b CAN0_BASE \b +
+//! \b CAN_O_IF1DA1.
+//! \param iSize is the number of bytes to copy from the CAN controller.
+//!
+//! This function takes the steps necessary to copy data to a contiguous buffer
+//! in memory from the non-contiguous data registers used by the CAN
+//! controller. This function is rarely used outside of the CANMessageGet()
+//! function.
+//!
+//! This function replaces the original CANReadDataReg() API and performs the
+//! same actions. A macro is provided in <tt>can.h</tt> to map the original
+//! API to this API.
+//!
+//! \return None.
+//
+//*****************************************************************************
+static void
+CANDataRegRead(unsigned char *pucData, unsigned long *pulRegister, int iSize)
+{
+ int iIdx;
+ unsigned long ulValue;
+
+ //
+ // Loop always copies 1 or 2 bytes per iteration.
+ //
+ for(iIdx = 0; iIdx < iSize; )
+ {
+ //
+ // Read out the data 16 bits at a time since this is how the registers
+ // are aligned in memory.
+ //
+ ulValue = CANRegRead((unsigned long)(pulRegister++));
+
+ //
+ // Store the first byte.
+ //
+ pucData[iIdx++] = (unsigned char)ulValue;
+
+ //
+ // Only read the second byte if needed.
+ //
+ if(iIdx < iSize)
+ {
+ pucData[iIdx++] = (unsigned char)(ulValue >> 8);
+ }
+ }
+}
+
+//*****************************************************************************
+//
+//! Initializes the CAN controller after reset.
+//!
+//! \param ulBase is the base address of the CAN controller.
+//!
+//! After reset, the CAN controller is left in the disabled state. However,
+//! the memory used for message objects contains undefined values and must be
+//! cleared prior to enabling the CAN controller the first time. This prevents
+//! unwanted transmission or reception of data before the message objects are
+//! configured. This function must be called before enabling the controller
+//! the first time.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+CANInit(unsigned long ulBase)
+{
+ int iMsg;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(CANBaseValid(ulBase));
+
+ //
+ // Place CAN controller in init state, regardless of previous state. This
+ // will put controller in idle, and allow the message object RAM to be
+ // programmed.
+ //
+ CANRegWrite(ulBase + CAN_O_CTL, CAN_CTL_INIT);
+
+ //
+ // Wait for busy bit to clear
+ //
+ while(CANRegRead(ulBase + CAN_O_IF1CRQ) & CAN_IF1CRQ_BUSY)
+ {
+ }
+
+ //
+ // Clear the message value bit in the arbitration register. This indicates
+ // the message is not valid and is a "safe" condition to leave the message
+ // object. The same arb reg is used to program all the message objects.
+ //
+ CANRegWrite(ulBase + CAN_O_IF1CMSK, CAN_IF1CMSK_WRNRD | CAN_IF1CMSK_ARB |
+ CAN_IF1CMSK_CONTROL);
+ CANRegWrite(ulBase + CAN_O_IF1ARB2, 0);
+ CANRegWrite(ulBase + CAN_O_IF1MCTL, 0);
+
+ //
+ // Loop through to program all 32 message objects
+ //
+ for(iMsg = 1; iMsg <= 32; iMsg++)
+ {
+ //
+ // Wait for busy bit to clear
+ //
+ while(CANRegRead(ulBase + CAN_O_IF1CRQ) & CAN_IF1CRQ_BUSY)
+ {
+ }
+
+ //
+ // Initiate programming the message object
+ //
+ CANRegWrite(ulBase + CAN_O_IF1CRQ, iMsg);
+ }
+
+ //
+ // Make sure that the interrupt and new data flags are updated for the
+ // message objects.
+ //
+ CANRegWrite(ulBase + CAN_O_IF1CMSK, CAN_IF1CMSK_NEWDAT |
+ CAN_IF1CMSK_CLRINTPND);
+
+ //
+ // Loop through to program all 32 message objects
+ //
+ for(iMsg = 1; iMsg <= 32; iMsg++)
+ {
+ //
+ // Wait for busy bit to clear.
+ //
+ while(CANRegRead(ulBase + CAN_O_IF1CRQ) & CAN_IF1CRQ_BUSY)
+ {
+ }
+
+ //
+ // Initiate programming the message object
+ //
+ CANRegWrite(ulBase + CAN_O_IF1CRQ, iMsg);
+ }
+
+ //
+ // Acknowledge any pending status interrupts.
+ //
+ CANRegRead(ulBase + CAN_O_STS);
+}
+
+//*****************************************************************************
+//
+//! Enables the CAN controller.
+//!
+//! \param ulBase is the base address of the CAN controller to enable.
+//!
+//! Enables the CAN controller for message processing. Once enabled, the
+//! controller will automatically transmit any pending frames, and process any
+//! received frames. The controller can be stopped by calling CANDisable().
+//! Prior to calling CANEnable(), CANInit() should have been called to
+//! initialize the controller and the CAN bus clock should be configured by
+//! calling CANBitTimingSet().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+CANEnable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(CANBaseValid(ulBase));
+
+ //
+ // Clear the init bit in the control register.
+ //
+ CANRegWrite(ulBase + CAN_O_CTL,
+ CANRegRead(ulBase + CAN_O_CTL) & ~CAN_CTL_INIT);
+}
+
+//*****************************************************************************
+//
+//! Disables the CAN controller.
+//!
+//! \param ulBase is the base address of the CAN controller to disable.
+//!
+//! Disables the CAN controller for message processing. When disabled, the
+//! controller will no longer automatically process data on the CAN bus. The
+//! controller can be restarted by calling CANEnable(). The state of the CAN
+//! controller and the message objects in the controller are left as they were
+//! before this call was made.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+CANDisable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(CANBaseValid(ulBase));
+
+ //
+ // Set the init bit in the control register.
+ //
+ CANRegWrite(ulBase + CAN_O_CTL,
+ CANRegRead(ulBase + CAN_O_CTL) | CAN_CTL_INIT);
+}
+
+//*****************************************************************************
+//
+//! Reads the current settings for the CAN controller bit timing.
+//!
+//! \param ulBase is the base address of the CAN controller.
+//! \param pClkParms is a pointer to a structure to hold the timing parameters.
+//!
+//! This function reads the current configuration of the CAN controller bit
+//! clock timing, and stores the resulting information in the structure
+//! supplied by the caller. Refer to CANBitTimingSet() for the meaning of the
+//! values that are returned in the structure pointed to by \e pClkParms.
+//!
+//! This function replaces the original CANGetBitTiming() API and performs the
+//! same actions. A macro is provided in <tt>can.h</tt> to map the original
+//! API to this API.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+CANBitTimingGet(unsigned long ulBase, tCANBitClkParms *pClkParms)
+{
+ unsigned int uBitReg;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(CANBaseValid(ulBase));
+ ASSERT(pClkParms != 0);
+
+ //
+ // Read out all the bit timing values from the CAN controller registers.
+ //
+ uBitReg = CANRegRead(ulBase + CAN_O_BIT);
+
+ //
+ // Set the phase 2 segment.
+ //
+ pClkParms->uPhase2Seg = ((uBitReg & CAN_BIT_TSEG2_M) >> 12) + 1;
+
+ //
+ // Set the phase 1 segment.
+ //
+ pClkParms->uSyncPropPhase1Seg = ((uBitReg & CAN_BIT_TSEG1_M) >> 8) + 1;
+
+ //
+ // Set the sychronous jump width.
+ //
+ pClkParms->uSJW = ((uBitReg & CAN_BIT_SJW_M) >> 6) + 1;
+
+ //
+ // Set the pre-divider for the CAN bus bit clock.
+ //
+ pClkParms->uQuantumPrescaler =
+ ((uBitReg & CAN_BIT_BRP_M) |
+ ((CANRegRead(ulBase + CAN_O_BRPE) & CAN_BRPE_BRPE_M) << 6)) + 1;
+}
+
+//*****************************************************************************
+//
+//! This function is used to set the CAN bit timing values to a nominal setting
+//! based on a desired bit rate.
+//!
+//! \param ulBase is the base address of the CAN controller.
+//! \param ulSourceClock is the system clock for the device in Hz.
+//! \param ulBitRate is the desired bit rate.
+//!
+//! This function will set the CAN bit timing for the bit rate passed in the
+//! \e ulBitRate parameter based on the \e ulSourceClock parameter. Since the
+//! CAN clock is based off of the system clock the calling function should pass
+//! in the source clock rate either by retrieving it from SysCtlClockGet() or
+//! using a specific value in Hz. The CAN bit clock is calculated to be an
+//! average timing value that should work for most systems. If tighter timing
+//! requirements are needed, then the CANBitTimingSet() function is available
+//! for full customization of all of the CAN bit timing values. Since not all
+//! bit rates can be matched exactly, the bit rate is set to the value closest
+//! to the desired bit rate without being higher than the \e ulBitRate value.
+//!
+//! \note On some devices the source clock is fixed at 8MHz so the
+//! \e ulSourceClock should be set to 8000000.
+//!
+//! \return This function returns the bit rate that the CAN controller was
+//! configured to use or it returns 0 to indicate that the bit rate was not
+//! changed because the requested bit rate was not valid.
+//!
+//*****************************************************************************
+unsigned long
+CANBitRateSet(unsigned long ulBase, unsigned long ulSourceClock,
+ unsigned long ulBitRate)
+{
+ unsigned long ulDesiredRatio;
+ unsigned long ulCANBits;
+ unsigned long ulPreDivide;
+ unsigned long ulRegValue;
+ unsigned short usCANCTL;
+
+ ASSERT(ulBitRate != 0);
+
+ //
+ // Caclulate the desired clock rate.
+ //
+ ulDesiredRatio = ulSourceClock / ulBitRate;
+
+ //
+ // If the ratio of CAN bit rate to processor clock is too small or too
+ // large then return 0 indicating that no bit rate was set.
+ //
+ if((ulDesiredRatio > (CAN_MIN_PRE_DIVISOR * CAN_MIN_BIT_DIVISOR)) ||
+ (ulDesiredRatio < CAN_MIN_BIT_DIVISOR))
+ {
+ return(0);
+ }
+
+ //
+ // Make sure that the Desired Ratio is not too large. This enforces the
+ // requirement that the bit rate is larger than requested.
+ //
+ if((ulSourceClock / ulDesiredRatio) > ulBitRate)
+ {
+ ulDesiredRatio += 1;
+ }
+
+ //
+ // Check all possible values to find a matching value.
+ //
+ while(ulDesiredRatio <= CAN_MAX_PRE_DIVISOR * CAN_MAX_BIT_DIVISOR)
+ {
+ //
+ // Loop through all possible CAN bit divisors.
+ //
+ for(ulCANBits = CAN_MAX_BIT_DIVISOR; ulCANBits >= CAN_MIN_BIT_DIVISOR;
+ ulCANBits--)
+ {
+ //
+ // For a given CAN bit divisor save the pre divisor.
+ //
+ ulPreDivide = ulDesiredRatio / ulCANBits;
+
+ //
+ // If the caculated divisors match the desired clock ratio then
+ // return these bit rate and set the CAN bit timing.
+ //
+ if((ulPreDivide * ulCANBits) == ulDesiredRatio)
+ {
+ //
+ // Start building the bit timing value by adding the bit timing
+ // in time quanta.
+ //
+ ulRegValue = g_usCANBitValues[ulCANBits - CAN_MIN_BIT_DIVISOR];
+
+ //
+ // To set the bit timing register, the controller must be placed
+ // in init mode (if not already), and also configuration change
+ // bit enabled. The stat of the register should be saved
+ // so it can be restored.
+ //
+ usCANCTL = CANRegRead(ulBase + CAN_O_CTL);
+ CANRegWrite(ulBase + CAN_O_CTL, usCANCTL | CAN_CTL_INIT |
+ CAN_CTL_CCE);
+
+ //
+ // Now add in the pre-scalar on the bit rate.
+ //
+ ulRegValue |= ((ulPreDivide - 1)& CAN_BIT_BRP_M);
+
+ //
+ // Set the clock bits in the and the lower bits of the
+ // pre-scalar.
+ //
+ CANRegWrite(ulBase + CAN_O_BIT, ulRegValue);
+
+ //
+ // Set the divider upper bits in the extension register.
+ //
+ CANRegWrite(ulBase + CAN_O_BRPE,
+ ((ulPreDivide - 1) >> 6) & CAN_BRPE_BRPE_M);
+
+ //
+ // Restore the saved CAN Control register.
+ //
+ CANRegWrite(ulBase + CAN_O_CTL, usCANCTL);
+
+ //
+ // Return the computed bit rate.
+ //
+ return(ulSourceClock / ( ulPreDivide * ulCANBits));
+ }
+ }
+
+ //
+ // Move the divisor up one and look again. Only in rare cases are
+ // more than 2 loops required to find the value.
+ //
+ ulDesiredRatio++;
+ }
+ return(0);
+}
+
+//*****************************************************************************
+//
+//! Configures the CAN controller bit timing.
+//!
+//! \param ulBase is the base address of the CAN controller.
+//! \param pClkParms points to the structure with the clock parameters.
+//!
+//! Configures the various timing parameters for the CAN bus bit timing:
+//! Propagation segment, Phase Buffer 1 segment, Phase Buffer 2 segment, and
+//! the Synchronization Jump Width. The values for Propagation and Phase
+//! Buffer 1 segments are derived from the combination
+//! \e pClkParms->uSyncPropPhase1Seg parameter. Phase Buffer 2 is determined
+//! from the \e pClkParms->uPhase2Seg parameter. These two parameters, along
+//! with \e pClkParms->uSJW are based in units of bit time quanta. The actual
+//! quantum time is determined by the \e pClkParms->uQuantumPrescaler value,
+//! which specifies the divisor for the CAN module clock.
+//!
+//! The total bit time, in quanta, will be the sum of the two Seg parameters,
+//! as follows:
+//!
+//! bit_time_q = uSyncPropPhase1Seg + uPhase2Seg + 1
+//!
+//! Note that the Sync_Seg is always one quantum in duration, and will be added
+//! to derive the correct duration of Prop_Seg and Phase1_Seg.
+//!
+//! The equation to determine the actual bit rate is as follows:
+//!
+//! CAN Clock /
+//! ((\e uSyncPropPhase1Seg + \e uPhase2Seg + 1) * (\e uQuantumPrescaler))
+//!
+//! This means that with \e uSyncPropPhase1Seg = 4, \e uPhase2Seg = 1,
+//! \e uQuantumPrescaler = 2 and an 8 MHz CAN clock, that the bit rate will be
+//! (8 MHz) / ((5 + 2 + 1) * 2) or 500 Kbit/sec.
+//!
+//! This function replaces the original CANSetBitTiming() API and performs the
+//! same actions. A macro is provided in <tt>can.h</tt> to map the original
+//! API to this API.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+CANBitTimingSet(unsigned long ulBase, tCANBitClkParms *pClkParms)
+{
+ unsigned int uBitReg;
+ unsigned int uSavedInit;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(CANBaseValid(ulBase));
+ ASSERT(pClkParms != 0);
+
+ //
+ // The phase 1 segment must be in the range from 2 to 16.
+ //
+ ASSERT((pClkParms->uSyncPropPhase1Seg >= 2) &&
+ (pClkParms->uSyncPropPhase1Seg <= 16));
+
+ //
+ // The phase 2 segment must be in the range from 1 to 8.
+ //
+ ASSERT((pClkParms->uPhase2Seg >= 1) && (pClkParms->uPhase2Seg <= 8));
+
+ //
+ // The synchronous jump windows must be in the range from 1 to 4.
+ //
+ ASSERT((pClkParms->uSJW >= 1) && (pClkParms->uSJW <= 4));
+
+ //
+ // The CAN clock pre-divider must be in the range from 1 to 1024.
+ //
+ ASSERT((pClkParms->uQuantumPrescaler <= 1024) &&
+ (pClkParms->uQuantumPrescaler >= 1));
+
+ //
+ // To set the bit timing register, the controller must be placed in init
+ // mode (if not already), and also configuration change bit enabled. State
+ // of the init bit should be saved so it can be restored at the end.
+ //
+ uSavedInit = CANRegRead(ulBase + CAN_O_CTL);
+ CANRegWrite(ulBase + CAN_O_CTL, uSavedInit | CAN_CTL_INIT | CAN_CTL_CCE);
+
+ //
+ // Set the bit fields of the bit timing register according to the parms.
+ //
+ uBitReg = ((pClkParms->uPhase2Seg - 1) << 12) & CAN_BIT_TSEG2_M;
+ uBitReg |= ((pClkParms->uSyncPropPhase1Seg - 1) << 8) & CAN_BIT_TSEG1_M;
+ uBitReg |= ((pClkParms->uSJW - 1) << 6) & CAN_BIT_SJW_M;
+ uBitReg |= (pClkParms->uQuantumPrescaler - 1) & CAN_BIT_BRP_M;
+ CANRegWrite(ulBase + CAN_O_BIT, uBitReg);
+
+ //
+ // Set the divider upper bits in the extension register.
+ //
+ CANRegWrite(ulBase + CAN_O_BRPE,
+ ((pClkParms->uQuantumPrescaler - 1) >> 6) & CAN_BRPE_BRPE_M);
+ //
+ // Clear the config change bit, and restore the init bit.
+ //
+ uSavedInit &= ~CAN_CTL_CCE;
+
+ //
+ // If Init was not set before, then clear it.
+ //
+ if(uSavedInit & CAN_CTL_INIT)
+ {
+ uSavedInit &= ~CAN_CTL_INIT;
+ }
+ CANRegWrite(ulBase + CAN_O_CTL, uSavedInit);
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the CAN controller.
+//!
+//! \param ulBase is the base address of the CAN controller.
+//! \param pfnHandler is a pointer to the function to be called when the
+//! enabled CAN interrupts occur.
+//!
+//! This function registers the interrupt handler in the interrupt vector
+//! table, and enables CAN interrupts on the interrupt controller; specific CAN
+//! interrupt sources must be enabled using CANIntEnable(). The interrupt
+//! handler being registered must clear the source of the interrupt using
+//! CANIntClear().
+//!
+//! If the application is using a static interrupt vector table stored in
+//! flash, then it is not necessary to register the interrupt handler this way.
+//! Instead, IntEnable() should be used to enable CAN interrupts on the
+//! interrupt controller.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+CANIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
+{
+ unsigned long ulIntNumber;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(CANBaseValid(ulBase));
+
+ //
+ // Get the actual interrupt number for this CAN controller.
+ //
+ ulIntNumber = CANIntNumberGet(ulBase);
+
+ //
+ // Register the interrupt handler.
+ //
+ IntRegister(ulIntNumber, pfnHandler);
+
+ //
+ // Enable the Ethernet interrupt.
+ //
+ IntEnable(ulIntNumber);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for the CAN controller.
+//!
+//! \param ulBase is the base address of the controller.
+//!
+//! This function unregisters the previously registered interrupt handler and
+//! disables the interrupt on the interrupt controller.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+CANIntUnregister(unsigned long ulBase)
+{
+ unsigned long ulIntNumber;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(CANBaseValid(ulBase));
+
+ //
+ // Get the actual interrupt number for this CAN controller.
+ //
+ ulIntNumber = CANIntNumberGet(ulBase);
+
+ //
+ // Register the interrupt handler.
+ //
+ IntUnregister(ulIntNumber);
+
+ //
+ // Disable the CAN interrupt.
+ //
+ IntDisable(ulIntNumber);
+}
+
+//*****************************************************************************
+//
+//! Enables individual CAN controller interrupt sources.
+//!
+//! \param ulBase is the base address of the CAN controller.
+//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.
+//!
+//! Enables specific interrupt sources of the CAN controller. Only enabled
+//! sources will cause a processor interrupt.
+//!
+//! The \e ulIntFlags parameter is the logical OR of any of the following:
+//!
+//! - \b CAN_INT_ERROR - a controller error condition has occurred
+//! - \b CAN_INT_STATUS - a message transfer has completed, or a bus error has
+//! been detected
+//! - \b CAN_INT_MASTER - allow CAN controller to generate interrupts
+//!
+//! In order to generate any interrupts, \b CAN_INT_MASTER must be enabled.
+//! Further, for any particular transaction from a message object to generate
+//! an interrupt, that message object must have interrupts enabled (see
+//! CANMessageSet()). \b CAN_INT_ERROR will generate an interrupt if the
+//! controller enters the ``bus off'' condition, or if the error counters reach
+//! a limit. \b CAN_INT_STATUS will generate an interrupt under quite a few
+//! status conditions and may provide more interrupts than the application
+//! needs to handle. When an interrupt occurs, use CANIntStatus() to determine
+//! the cause.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+CANIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(CANBaseValid(ulBase));
+ ASSERT((ulIntFlags & ~(CAN_CTL_EIE | CAN_CTL_SIE | CAN_CTL_IE)) == 0);
+
+ //
+ // Enable the specified interrupts.
+ //
+ CANRegWrite(ulBase + CAN_O_CTL,
+ CANRegRead(ulBase + CAN_O_CTL) | ulIntFlags);
+}
+
+//*****************************************************************************
+//
+//! Disables individual CAN controller interrupt sources.
+//!
+//! \param ulBase is the base address of the CAN controller.
+//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled.
+//!
+//! Disables the specified CAN controller interrupt sources. Only enabled
+//! interrupt sources can cause a processor interrupt.
+//!
+//! The \e ulIntFlags parameter has the same definition as in the
+//! CANIntEnable() function.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+CANIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(CANBaseValid(ulBase));
+ ASSERT((ulIntFlags & ~(CAN_CTL_EIE | CAN_CTL_SIE | CAN_CTL_IE)) == 0);
+
+ //
+ // Disable the specified interrupts.
+ //
+ CANRegWrite(ulBase + CAN_O_CTL,
+ CANRegRead(ulBase + CAN_O_CTL) & ~(ulIntFlags));
+}
+
+//*****************************************************************************
+//
+//! Returns the current CAN controller interrupt status.
+//!
+//! \param ulBase is the base address of the CAN controller.
+//! \param eIntStsReg indicates which interrupt status register to read
+//!
+//! Returns the value of one of two interrupt status registers. The interrupt
+//! status register read is determined by the \e eIntStsReg parameter, which
+//! can have one of the following values:
+//!
+//! - \b CAN_INT_STS_CAUSE - indicates the cause of the interrupt
+//! - \b CAN_INT_STS_OBJECT - indicates pending interrupts of all message
+//! objects
+//!
+//! \b CAN_INT_STS_CAUSE returns the value of the controller interrupt register
+//! and indicates the cause of the interrupt. It will be a value of
+//! \b CAN_INT_INTID_STATUS if the cause is a status interrupt. In this case,
+//! the status register should be read with the CANStatusGet() function.
+//! Calling this function to read the status will also clear the status
+//! interrupt. If the value of the interrupt register is in the range 1-32,
+//! then this indicates the number of the highest priority message object that
+//! has an interrupt pending. The message object interrupt can be cleared by
+//! using the CANIntClear() function, or by reading the message using
+//! CANMessageGet() in the case of a received message. The interrupt handler
+//! can read the interrupt status again to make sure all pending interrupts are
+//! cleared before returning from the interrupt.
+//!
+//! \b CAN_INT_STS_OBJECT returns a bit mask indicating which message objects
+//! have pending interrupts. This can be used to discover all of the pending
+//! interrupts at once, as opposed to repeatedly reading the interrupt register
+//! by using \b CAN_INT_STS_CAUSE.
+//!
+//! \return Returns the value of one of the interrupt status registers.
+//
+//*****************************************************************************
+unsigned long
+CANIntStatus(unsigned long ulBase, tCANIntStsReg eIntStsReg)
+{
+ unsigned long ulStatus;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(CANBaseValid(ulBase));
+
+ //
+ // See which status the caller is looking for.
+ //
+ switch(eIntStsReg)
+ {
+ //
+ // The caller wants the global interrupt status for the CAN controller
+ // specified by ulBase.
+ //
+ case CAN_INT_STS_CAUSE:
+ {
+ ulStatus = CANRegRead(ulBase + CAN_O_INT);
+ break;
+ }
+
+ //
+ // The caller wants the current message status interrupt for all
+ // messages.
+ //
+ case CAN_INT_STS_OBJECT:
+ {
+ //
+ // Read and combine both 16 bit values into one 32bit status.
+ //
+ ulStatus = (CANRegRead(ulBase + CAN_O_MSG1INT) &
+ CAN_MSG1INT_INTPND_M);
+ ulStatus |= (CANRegRead(ulBase + CAN_O_MSG2INT) << 16);
+ break;
+ }
+
+ //
+ // Request was for unknown status so just return 0.
+ //
+ default:
+ {
+ ulStatus = 0;
+ break;
+ }
+ }
+ //
+ // Return the interrupt status value
+ //
+ return(ulStatus);
+}
+
+//*****************************************************************************
+//
+//! Clears a CAN interrupt source.
+//!
+//! \param ulBase is the base address of the CAN controller.
+//! \param ulIntClr is a value indicating which interrupt source to clear.
+//!
+//! This function can be used to clear a specific interrupt source. The
+//! \e ulIntClr parameter should be one of the following values:
+//!
+//! - \b CAN_INT_INTID_STATUS - Clears a status interrupt.
+//! - 1-32 - Clears the specified message object interrupt
+//!
+//! It is not necessary to use this function to clear an interrupt. This
+//! should only be used if the application wants to clear an interrupt source
+//! without taking the normal interrupt action.
+//!
+//! Normally, the status interrupt is cleared by reading the controller status
+//! using CANStatusGet(). A specific message object interrupt is normally
+//! cleared by reading the message object using CANMessageGet().
+//!
+//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
+//! several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared. Failure to do so may result in the interrupt handler
+//! being immediately reentered (since NVIC still sees the interrupt source
+//! asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+CANIntClear(unsigned long ulBase, unsigned long ulIntClr)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(CANBaseValid(ulBase));
+ ASSERT((ulIntClr == CAN_INT_INTID_STATUS) ||
+ ((ulIntClr>=1) && (ulIntClr <=32)));
+
+ if(ulIntClr == CAN_INT_INTID_STATUS)
+ {
+ //
+ // Simply read and discard the status to clear the interrupt.
+ //
+ CANRegRead(ulBase + CAN_O_STS);
+ }
+ else
+ {
+ //
+ // Wait to be sure that this interface is not busy.
+ //
+ while(CANRegRead(ulBase + CAN_O_IF1CRQ) & CAN_IF1CRQ_BUSY)
+ {
+ }
+
+ //
+ // Only change the interrupt pending state by setting only the
+ // CAN_IF1CMSK_CLRINTPND bit.
+ //
+ CANRegWrite(ulBase + CAN_O_IF1CMSK, CAN_IF1CMSK_CLRINTPND);
+
+ //
+ // Send the clear pending interrupt command to the CAN controller.
+ //
+ CANRegWrite(ulBase + CAN_O_IF1CRQ, ulIntClr & CAN_IF1CRQ_MNUM_M);
+
+ //
+ // Wait to be sure that this interface is not busy.
+ //
+ while(CANRegRead(ulBase + CAN_O_IF1CRQ) & CAN_IF1CRQ_BUSY)
+ {
+ }
+ }
+}
+
+//*****************************************************************************
+//
+//! Sets the CAN controller automatic retransmission behavior.
+//!
+//! \param ulBase is the base address of the CAN controller.
+//! \param bAutoRetry enables automatic retransmission.
+//!
+//! Enables or disables automatic retransmission of messages with detected
+//! errors. If \e bAutoRetry is \b true, then automatic retransmission is
+//! enabled, otherwise it is disabled.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+CANRetrySet(unsigned long ulBase, tBoolean bAutoRetry)
+{
+ unsigned long ulCtlReg;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(CANBaseValid(ulBase));
+
+ ulCtlReg = CANRegRead(ulBase + CAN_O_CTL);
+
+ //
+ // Conditionally set the DAR bit to enable/disable auto-retry.
+ //
+ if(bAutoRetry)
+ {
+ //
+ // Clearing the DAR bit tells the controller to not disable the
+ // auto-retry of messages which were not transmitted or received
+ // correctly.
+ //
+ ulCtlReg &= ~CAN_CTL_DAR;
+ }
+ else
+ {
+ //
+ // Setting the DAR bit tells the controller to disable the auto-retry
+ // of messages which were not transmitted or received correctly.
+ //
+ ulCtlReg |= CAN_CTL_DAR;
+ }
+
+ CANRegWrite(ulBase + CAN_O_CTL, ulCtlReg);
+}
+
+//*****************************************************************************
+//
+//! Returns the current setting for automatic retransmission.
+//!
+//! \param ulBase is the base address of the CAN controller.
+//!
+//! Reads the current setting for the automatic retransmission in the CAN
+//! controller and returns it to the caller.
+//!
+//! \return Returns \b true if automatic retransmission is enabled, \b false
+//! otherwise.
+//
+//*****************************************************************************
+tBoolean
+CANRetryGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(CANBaseValid(ulBase));
+
+ //
+ // Read the disable automatic retry setting from the CAN controller.
+ //
+ if(CANRegRead(ulBase + CAN_O_CTL) & CAN_CTL_DAR)
+ {
+ //
+ // Automatic data retransmission is not enabled.
+ //
+ return(false);
+ }
+
+ //
+ // Automatic data retransmission is enabled.
+ //
+ return(true);
+}
+
+//*****************************************************************************
+//
+//! Reads one of the controller status registers.
+//!
+//! \param ulBase is the base address of the CAN controller.
+//! \param eStatusReg is the status register to read.
+//!
+//! Reads a status register of the CAN controller and returns it to the caller.
+//! The different status registers are:
+//!
+//! - \b CAN_STS_CONTROL - the main controller status
+//! - \b CAN_STS_TXREQUEST - bit mask of objects pending transmission
+//! - \b CAN_STS_NEWDAT - bit mask of objects with new data
+//! - \b CAN_STS_MSGVAL - bit mask of objects with valid configuration
+//!
+//! When reading the main controller status register, a pending status
+//! interrupt will be cleared. This should be used in the interrupt handler
+//! for the CAN controller if the cause is a status interrupt. The controller
+//! status register fields are as follows:
+//!
+//! - \b CAN_STATUS_BUS_OFF - controller is in bus-off condition
+//! - \b CAN_STATUS_EWARN - an error counter has reached a limit of at least 96
+//! - \b CAN_STATUS_EPASS - CAN controller is in the error passive state
+//! - \b CAN_STATUS_RXOK - a message was received successfully (independent of
+//! any message filtering).
+//! - \b CAN_STATUS_TXOK - a message was successfully transmitted
+//! - \b CAN_STATUS_LEC_MSK - mask of last error code bits (3 bits)
+//! - \b CAN_STATUS_LEC_NONE - no error
+//! - \b CAN_STATUS_LEC_STUFF - stuffing error detected
+//! - \b CAN_STATUS_LEC_FORM - a format error occurred in the fixed format part
+//! of a message
+//! - \b CAN_STATUS_LEC_ACK - a transmitted message was not acknowledged
+//! - \b CAN_STATUS_LEC_BIT1 - dominant level detected when trying to send in
+//! recessive mode
+//! - \b CAN_STATUS_LEC_BIT0 - recessive level detected when trying to send in
+//! dominant mode
+//! - \b CAN_STATUS_LEC_CRC - CRC error in received message
+//!
+//! The remaining status registers are 32-bit bit maps to the message objects.
+//! They can be used to quickly obtain information about the status of all the
+//! message objects without needing to query each one. They contain the
+//! following information:
+//!
+//! - \b CAN_STS_TXREQUEST - if a message object's TxRequest bit is set, that
+//! means that a transmission is pending on that object. The application can
+//! use this to determine which objects are still waiting to send a message.
+//! - \b CAN_STS_NEWDAT - if a message object's NewDat bit is set, that means
+//! that a new message has been received in that object, and has not yet been
+//! picked up by the host application
+//! - \b CAN_STS_MSGVAL - if a message object's MsgVal bit is set, that means
+//! it has a valid configuration programmed. The host application can use this
+//! to determine which message objects are empty/unused.
+//!
+//! \return Returns the value of the status register.
+//
+//*****************************************************************************
+unsigned long
+CANStatusGet(unsigned long ulBase, tCANStsReg eStatusReg)
+{
+ unsigned long ulStatus;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(CANBaseValid(ulBase));
+
+ switch(eStatusReg)
+ {
+ //
+ // Just return the global CAN status register since that is what was
+ // requested.
+ //
+ case CAN_STS_CONTROL:
+ {
+ ulStatus = CANRegRead(ulBase + CAN_O_STS);
+ CANRegWrite(ulBase + CAN_O_STS,
+ ~(CAN_STS_RXOK | CAN_STS_TXOK | CAN_STS_LEC_M));
+ break;
+ }
+
+ //
+ // Combine the Transmit status bits into one 32bit value.
+ //
+ case CAN_STS_TXREQUEST:
+ {
+ ulStatus = CANRegRead(ulBase + CAN_O_TXRQ1);
+ ulStatus |= CANRegRead(ulBase + CAN_O_TXRQ2) << 16;
+ break;
+ }
+
+ //
+ // Combine the New Data status bits into one 32bit value.
+ //
+ case CAN_STS_NEWDAT:
+ {
+ ulStatus = CANRegRead(ulBase + CAN_O_NWDA1);
+ ulStatus |= CANRegRead(ulBase + CAN_O_NWDA2) << 16;
+ break;
+ }
+
+ //
+ // Combine the Message valid status bits into one 32bit value.
+ //
+ case CAN_STS_MSGVAL:
+ {
+ ulStatus = CANRegRead(ulBase + CAN_O_MSG1VAL);
+ ulStatus |= CANRegRead(ulBase + CAN_O_MSG2VAL) << 16;
+ break;
+ }
+
+ //
+ // Unknown CAN status requested so return 0.
+ //
+ default:
+ {
+ ulStatus = 0;
+ break;
+ }
+ }
+ return(ulStatus);
+}
+
+//*****************************************************************************
+//
+//! Reads the CAN controller error counter register.
+//!
+//! \param ulBase is the base address of the CAN controller.
+//! \param pulRxCount is a pointer to storage for the receive error counter.
+//! \param pulTxCount is a pointer to storage for the transmit error counter.
+//!
+//! Reads the error counter register and returns the transmit and receive error
+//! counts to the caller along with a flag indicating if the controller receive
+//! counter has reached the error passive limit. The values of the receive and
+//! transmit error counters are returned through the pointers provided as
+//! parameters.
+//!
+//! After this call, \e *pulRxCount will hold the current receive error count
+//! and \e *pulTxCount will hold the current transmit error count.
+//!
+//! \return Returns \b true if the receive error count has reached the error
+//! passive limit, and \b false if the error count is below the error passive
+//! limit.
+//
+//*****************************************************************************
+tBoolean
+CANErrCntrGet(unsigned long ulBase, unsigned long *pulRxCount,
+ unsigned long *pulTxCount)
+{
+ unsigned long ulCANError;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(CANBaseValid(ulBase));
+
+ //
+ // Read the current count of transmit/receive errors.
+ //
+ ulCANError = CANRegRead(ulBase + CAN_O_ERR);
+
+ //
+ // Extract the error numbers from the register value.
+ //
+ *pulRxCount = (ulCANError & CAN_ERR_REC_M) >> CAN_ERR_REC_S;
+ *pulTxCount = (ulCANError & CAN_ERR_TEC_M) >> CAN_ERR_TEC_S;
+
+ if(ulCANError & CAN_ERR_RP)
+ {
+ return(true);
+ }
+ return(false);
+}
+
+//*****************************************************************************
+//
+//! Configures a message object in the CAN controller.
+//!
+//! \param ulBase is the base address of the CAN controller.
+//! \param ulObjID is the object number to configure (1-32).
+//! \param pMsgObject is a pointer to a structure containing message object
+//! settings.
+//! \param eMsgType indicates the type of message for this object.
+//!
+//! This function is used to configure any one of the 32 message objects in the
+//! CAN controller. A message object can be configured as any type of CAN
+//! message object as well as several options for automatic transmission and
+//! reception. This call also allows the message object to be configured to
+//! generate interrupts on completion of message receipt or transmission. The
+//! message object can also be configured with a filter/mask so that actions
+//! are only taken when a message that meets certain parameters is seen on the
+//! CAN bus.
+//!
+//! The \e eMsgType parameter must be one of the following values:
+//!
+//! - \b MSG_OBJ_TYPE_TX - CAN transmit message object.
+//! - \b MSG_OBJ_TYPE_TX_REMOTE - CAN transmit remote request message object.
+//! - \b MSG_OBJ_TYPE_RX - CAN receive message object.
+//! - \b MSG_OBJ_TYPE_RX_REMOTE - CAN receive remote request message object.
+//! - \b MSG_OBJ_TYPE_RXTX_REMOTE - CAN remote frame receive remote, then
+//! transmit message object.
+//!
+//! The message object pointed to by \e pMsgObject must be populated by the
+//! caller, as follows:
+//!
+//! - \e ulMsgID - contains the message ID, either 11 or 29 bits.
+//! - \e ulMsgIDMask - mask of bits from \e ulMsgID that must match if
+//! identifier filtering is enabled.
+//! - \e ulFlags
+//! - Set \b MSG_OBJ_TX_INT_ENABLE flag to enable interrupt on transmission.
+//! - Set \b MSG_OBJ_RX_INT_ENABLE flag to enable interrupt on receipt.
+//! - Set \b MSG_OBJ_USE_ID_FILTER flag to enable filtering based on the
+//! identifier mask specified by \e ulMsgIDMask.
+//! - \e ulMsgLen - the number of bytes in the message data. This should be
+//! non-zero even for a remote frame; it should match the expected bytes of the
+//! data responding data frame.
+//! - \e pucMsgData - points to a buffer containing up to 8 bytes of data for a
+//! data frame.
+//!
+//! \b Example: To send a data frame or remote frame(in response to a remote
+//! request), take the following steps:
+//!
+//! -# Set \e eMsgType to \b MSG_OBJ_TYPE_TX.
+//! -# Set \e pMsgObject->ulMsgID to the message ID.
+//! -# Set \e pMsgObject->ulFlags. Make sure to set \b MSG_OBJ_TX_INT_ENABLE to
+//! allow an interrupt to be generated when the message is sent.
+//! -# Set \e pMsgObject->ulMsgLen to the number of bytes in the data frame.
+//! -# Set \e pMsgObject->pucMsgData to point to an array containing the bytes
+//! to send in the message.
+//! -# Call this function with \e ulObjID set to one of the 32 object buffers.
+//!
+//! \b Example: To receive a specific data frame, take the following steps:
+//!
+//! -# Set \e eMsgObjType to \b MSG_OBJ_TYPE_RX.
+//! -# Set \e pMsgObject->ulMsgID to the full message ID, or a partial mask to
+//! use partial ID matching.
+//! -# Set \e pMsgObject->ulMsgIDMask bits that should be used for masking
+//! during comparison.
+//! -# Set \e pMsgObject->ulFlags as follows:
+//! - Set \b MSG_OBJ_TX_INT_ENABLE flag to be interrupted when the data frame
+//! is received.
+//! - Set \b MSG_OBJ_USE_ID_FILTER flag to enable identifier based filtering.
+//! -# Set \e pMsgObject->ulMsgLen to the number of bytes in the expected data
+//! frame.
+//! -# The buffer pointed to by \e pMsgObject->pucMsgData and
+//! \e pMsgObject->ulMsgLen are not used by this call as no data is present at
+//! the time of the call.
+//! -# Call this function with \e ulObjID set to one of the 32 object buffers.
+//!
+//! If you specify a message object buffer that already contains a message
+//! definition, it will be overwritten.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+CANMessageSet(unsigned long ulBase, unsigned long ulObjID,
+ tCANMsgObject *pMsgObject, tMsgObjType eMsgType)
+{
+ unsigned short usCmdMaskReg;
+ unsigned short usMaskReg[2];
+ unsigned short usArbReg[2];
+ unsigned short usMsgCtrl;
+ tBoolean bTransferData;
+ tBoolean bUseExtendedID;
+
+ bTransferData = 0;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(CANBaseValid(ulBase));
+ ASSERT((ulObjID <= 32) && (ulObjID != 0));
+ ASSERT((eMsgType == MSG_OBJ_TYPE_TX) ||
+ (eMsgType == MSG_OBJ_TYPE_TX_REMOTE) ||
+ (eMsgType == MSG_OBJ_TYPE_RX) ||
+ (eMsgType == MSG_OBJ_TYPE_RX_REMOTE) ||
+ (eMsgType == MSG_OBJ_TYPE_TX_REMOTE) ||
+ (eMsgType == MSG_OBJ_TYPE_RXTX_REMOTE));
+
+ //
+ // Wait for busy bit to clear
+ //
+ while(CANRegRead(ulBase + CAN_O_IF1CRQ) & CAN_IF1CRQ_BUSY)
+ {
+ }
+
+ //
+ // See if we need to use an extended identifier or not.
+ //
+ if((pMsgObject->ulMsgID > CAN_MAX_11BIT_MSG_ID) ||
+ (pMsgObject->ulFlags & MSG_OBJ_EXTENDED_ID))
+ {
+ bUseExtendedID = 1;
+ }
+ else
+ {
+ bUseExtendedID = 0;
+ }
+
+ //
+ // This is always a write to the Message object as this call is setting a
+ // message object. This call will also always set all size bits so it sets
+ // both data bits. The call will use the CONTROL register to set control
+ // bits so this bit needs to be set as well.
+ //
+ usCmdMaskReg = (CAN_IF1CMSK_WRNRD | CAN_IF1CMSK_DATAA | CAN_IF1CMSK_DATAB |
+ CAN_IF1CMSK_CONTROL);
+
+ //
+ // Initialize the values to a known state before filling them in based on
+ // the type of message object that is being configured.
+ //
+ usArbReg[0] = 0;
+ usMsgCtrl = 0;
+ usMaskReg[0] = 0;
+ usMaskReg[1] = 0;
+
+ switch(eMsgType)
+ {
+ //
+ // Transmit message object.
+ //
+ case MSG_OBJ_TYPE_TX:
+ {
+ //
+ // Set the TXRQST bit and the reset the rest of the register.
+ //
+ usMsgCtrl |= CAN_IF1MCTL_TXRQST;
+ usArbReg[1] = CAN_IF1ARB2_DIR;
+ bTransferData = 1;
+ break;
+ }
+
+ //
+ // Transmit remote request message object
+ //
+ case MSG_OBJ_TYPE_TX_REMOTE:
+ {
+ //
+ // Set the TXRQST bit and the reset the rest of the register.
+ //
+ usMsgCtrl |= CAN_IF1MCTL_TXRQST;
+ usArbReg[1] = 0;
+ break;
+ }
+
+ //
+ // Receive message object.
+ //
+ case MSG_OBJ_TYPE_RX:
+ {
+ //
+ // This clears the DIR bit along with everthing else. The TXRQST
+ // bit was cleard by defaulting usMsgCtrl to 0.
+ //
+ usArbReg[1] = 0;
+ break;
+ }
+
+ //
+ // Receive remote request message object.
+ //
+ case MSG_OBJ_TYPE_RX_REMOTE:
+ {
+ //
+ // The DIR bit is set to one for remote receivers. The TXRQST bit
+ // was cleard by defaulting usMsgCtrl to 0.
+ //
+ usArbReg[1] = CAN_IF1ARB2_DIR;
+
+ //
+ // Set this object so that it only indicates that a remote frame
+ // was received and allow for software to handle it by sending back
+ // a data frame.
+ //
+ usMsgCtrl = CAN_IF1MCTL_UMASK;
+
+ //
+ // Use the full Identifier by default.
+ //
+ usMaskReg[0] = 0xffff;
+ usMaskReg[1] = 0x1fff;
+
+ //
+ // Make sure to send the mask to the message object.
+ //
+ usCmdMaskReg |= CAN_IF1CMSK_MASK;
+ break;
+ }
+
+ //
+ // Remote frame receive remote, with auto-transmit message object.
+ //
+ case MSG_OBJ_TYPE_RXTX_REMOTE:
+ {
+ //
+ // Oddly the DIR bit is set to one for remote receivers.
+ //
+ usArbReg[1] = CAN_IF1ARB2_DIR;
+
+ //
+ // Set this object to auto answer if a matching identifier is seen.
+ //
+ usMsgCtrl = CAN_IF1MCTL_RMTEN | CAN_IF1MCTL_UMASK;
+
+ //
+ // The data to be returned needs to be filled in.
+ //
+ bTransferData = 1;
+ break;
+ }
+
+ //
+ // This case should never happen due to the ASSERT statement at the
+ // beginning of this function.
+ //
+ default:
+ {
+ return;
+ }
+ }
+
+ //
+ // Configure the Mask Registers.
+ //
+ if(pMsgObject->ulFlags & MSG_OBJ_USE_ID_FILTER)
+ {
+ if(bUseExtendedID)
+ {
+ //
+ // Set the 29 bits of Identifier mask that were requested.
+ //
+ usMaskReg[0] = pMsgObject->ulMsgIDMask & CAN_IF1MSK1_IDMSK_M;
+ usMaskReg[1] = ((pMsgObject->ulMsgIDMask >> 16) &
+ CAN_IF1MSK2_IDMSK_M);
+ }
+ else
+ {
+ //
+ // Lower 16 bit are unused so set them to zero.
+ //
+ usMaskReg[0] = 0;
+
+ //
+ // Put the 11 bit Mask Identifier into the upper bits of the field
+ // in the register.
+ //
+ usMaskReg[1] = ((pMsgObject->ulMsgIDMask << 2) &
+ CAN_IF1MSK2_IDMSK_M);
+ }
+ }
+
+ //
+ // If the caller wants to filter on the extended ID bit then set it.
+ //
+ if((pMsgObject->ulFlags & MSG_OBJ_USE_EXT_FILTER) ==
+ MSG_OBJ_USE_EXT_FILTER)
+ {
+ usMaskReg[1] |= CAN_IF1MSK2_MXTD;
+ }
+
+ //
+ // The caller wants to filter on the message direction field.
+ //
+ if((pMsgObject->ulFlags & MSG_OBJ_USE_DIR_FILTER) ==
+ MSG_OBJ_USE_DIR_FILTER)
+ {
+ usMaskReg[1] |= CAN_IF1MSK2_MDIR;
+ }
+
+ if(pMsgObject->ulFlags & (MSG_OBJ_USE_ID_FILTER | MSG_OBJ_USE_DIR_FILTER |
+ MSG_OBJ_USE_EXT_FILTER))
+ {
+ //
+ // Set the UMASK bit to enable using the mask register.
+ //
+ usMsgCtrl |= CAN_IF1MCTL_UMASK;
+
+ //
+ // Set the MASK bit so that this gets trasferred to the Message Object.
+ //
+ usCmdMaskReg |= CAN_IF1CMSK_MASK;
+ }
+
+ //
+ // Set the Arb bit so that this gets transferred to the Message object.
+ //
+ usCmdMaskReg |= CAN_IF1CMSK_ARB;
+
+ //
+ // Configure the Arbitration registers.
+ //
+ if(bUseExtendedID)
+ {
+ //
+ // Set the 29 bit version of the Identifier for this message object.
+ //
+ usArbReg[0] |= pMsgObject->ulMsgID & CAN_IF1ARB1_ID_M;
+ usArbReg[1] |= (pMsgObject->ulMsgID >> 16) & CAN_IF1ARB2_ID_M;
+
+ //
+ // Mark the message as valid and set the extended ID bit.
+ //
+ usArbReg[1] |= CAN_IF1ARB2_MSGVAL | CAN_IF1ARB2_XTD;
+ }
+ else
+ {
+ //
+ // Set the 11 bit version of the Identifier for this message object.
+ // The lower 18 bits are set to zero.
+ //
+ usArbReg[1] |= (pMsgObject->ulMsgID << 2) & CAN_IF1ARB2_ID_M;
+
+ //
+ // Mark the message as valid.
+ //
+ usArbReg[1] |= CAN_IF1ARB2_MSGVAL;
+ }
+
+ //
+ // Set the data length since this is set for all transfers. This is also a
+ // single transfer and not a FIFO transfer so set EOB bit.
+ //
+ usMsgCtrl |= (pMsgObject->ulMsgLen & CAN_IF1MCTL_DLC_M) | CAN_IF1MCTL_EOB;
+
+ //
+ // Enable transmit interrupts if they should be enabled.
+ //
+ if(pMsgObject->ulFlags & MSG_OBJ_TX_INT_ENABLE)
+ {
+ usMsgCtrl |= CAN_IF1MCTL_TXIE;
+ }
+
+ //
+ // Enable receive interrupts if they should be enabled.
+ //
+ if(pMsgObject->ulFlags & MSG_OBJ_RX_INT_ENABLE)
+ {
+ usMsgCtrl |= CAN_IF1MCTL_RXIE;
+ }
+
+ //
+ // Write the data out to the CAN Data registers if needed.
+ //
+ if(bTransferData)
+ {
+ CANDataRegWrite(pMsgObject->pucMsgData,
+ (unsigned long *)(ulBase + CAN_O_IF1DA1),
+ pMsgObject->ulMsgLen);
+ }
+
+ //
+ // Write out the registers to program the message object.
+ //
+ CANRegWrite(ulBase + CAN_O_IF1CMSK, usCmdMaskReg);
+ CANRegWrite(ulBase + CAN_O_IF1MSK1, usMaskReg[0]);
+ CANRegWrite(ulBase + CAN_O_IF1MSK2, usMaskReg[1]);
+ CANRegWrite(ulBase + CAN_O_IF1ARB1, usArbReg[0]);
+ CANRegWrite(ulBase + CAN_O_IF1ARB2, usArbReg[1]);
+ CANRegWrite(ulBase + CAN_O_IF1MCTL, usMsgCtrl);
+
+ //
+ // Transfer the message object to the message object specifiec by ulObjID.
+ //
+ CANRegWrite(ulBase + CAN_O_IF1CRQ, ulObjID & CAN_IF1CRQ_MNUM_M);
+
+ return;
+}
+
+//*****************************************************************************
+//
+//! Reads a CAN message from one of the message object buffers.
+//!
+//! \param ulBase is the base address of the CAN controller.
+//! \param ulObjID is the object number to read (1-32).
+//! \param pMsgObject points to a structure containing message object fields.
+//! \param bClrPendingInt indicates whether an associated interrupt should be
+//! cleared.
+//!
+//! This function is used to read the contents of one of the 32 message objects
+//! in the CAN controller, and return it to the caller. The data returned is
+//! stored in the fields of the caller-supplied structure pointed to by
+//! \e pMsgObject. The data consists of all of the parts of a CAN message,
+//! plus some control and status information.
+//!
+//! Normally this is used to read a message object that has received and stored
+//! a CAN message with a certain identifier. However, this could also be used
+//! to read the contents of a message object in order to load the fields of the
+//! structure in case only part of the structure needs to be changed from a
+//! previous setting.
+//!
+//! When using CANMessageGet, all of the same fields of the structure are
+//! populated in the same way as when the CANMessageSet() function is used,
+//! with the following exceptions:
+//!
+//! \e pMsgObject->ulFlags:
+//!
+//! - \b MSG_OBJ_NEW_DATA indicates if this is new data since the last time it
+//! was read
+//! - \b MSG_OBJ_DATA_LOST indicates that at least one message was received on
+//! this message object, and not read by the host before being overwritten.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+CANMessageGet(unsigned long ulBase, unsigned long ulObjID,
+ tCANMsgObject *pMsgObject, tBoolean bClrPendingInt)
+{
+ unsigned short usCmdMaskReg;
+ unsigned short usMaskReg[2];
+ unsigned short usArbReg[2];
+ unsigned short usMsgCtrl;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(CANBaseValid(ulBase));
+ ASSERT((ulObjID <= 32) && (ulObjID != 0));
+
+ //
+ // This is always a read to the Message object as this call is setting a
+ // message object.
+ //
+ usCmdMaskReg = (CAN_IF1CMSK_DATAA | CAN_IF1CMSK_DATAB |
+ CAN_IF1CMSK_CONTROL | CAN_IF1CMSK_MASK | CAN_IF1CMSK_ARB);
+
+ //
+ // Clear a pending interrupt and new data in a message object.
+ //
+ if(bClrPendingInt)
+ {
+ usCmdMaskReg |= CAN_IF1CMSK_CLRINTPND;
+ }
+
+ //
+ // Set up the request for data from the message object.
+ //
+ CANRegWrite(ulBase + CAN_O_IF2CMSK, usCmdMaskReg);
+
+ //
+ // Transfer the message object to the message object specifiec by ulObjID.
+ //
+ CANRegWrite(ulBase + CAN_O_IF2CRQ, ulObjID & CAN_IF1CRQ_MNUM_M);
+
+ //
+ // Wait for busy bit to clear
+ //
+ while(CANRegRead(ulBase + CAN_O_IF2CRQ) & CAN_IF1CRQ_BUSY)
+ {
+ }
+
+ //
+ // Read out the IF Registers.
+ //
+ usMaskReg[0] = CANRegRead(ulBase + CAN_O_IF2MSK1);
+ usMaskReg[1] = CANRegRead(ulBase + CAN_O_IF2MSK2);
+ usArbReg[0] = CANRegRead(ulBase + CAN_O_IF2ARB1);
+ usArbReg[1] = CANRegRead(ulBase + CAN_O_IF2ARB2);
+ usMsgCtrl = CANRegRead(ulBase + CAN_O_IF2MCTL);
+
+ pMsgObject->ulFlags = MSG_OBJ_NO_FLAGS;
+
+ //
+ // Determine if this is a remote frame by checking the TXRQST and DIR bits.
+ //
+ if((!(usMsgCtrl & CAN_IF1MCTL_TXRQST) &&
+ (usArbReg[1] & CAN_IF1ARB2_DIR)) ||
+ ((usMsgCtrl & CAN_IF1MCTL_TXRQST) &&
+ (!(usArbReg[1] & CAN_IF1ARB2_DIR))))
+ {
+ pMsgObject->ulFlags |= MSG_OBJ_REMOTE_FRAME;
+ }
+
+ //
+ // Get the identifier out of the register, the format depends on size of
+ // the mask.
+ //
+ if(usArbReg[1] & CAN_IF1ARB2_XTD)
+ {
+ //
+ // Set the 29 bit version of the Identifier for this message object.
+ //
+ pMsgObject->ulMsgID = ((usArbReg[1] & CAN_IF1ARB2_ID_M) << 16) |
+ usArbReg[0];
+
+ pMsgObject->ulFlags |= MSG_OBJ_EXTENDED_ID;
+ }
+ else
+ {
+ //
+ // The Identifier is an 11 bit value.
+ //
+ pMsgObject->ulMsgID = (usArbReg[1] & CAN_IF1ARB2_ID_M) >> 2;
+ }
+
+ //
+ // Indicate that we lost some data.
+ //
+ if(usMsgCtrl & CAN_IF1MCTL_MSGLST)
+ {
+ pMsgObject->ulFlags |= MSG_OBJ_DATA_LOST;
+ }
+
+ //
+ // Set the flag to indicate if ID masking was used.
+ //
+ if(usMsgCtrl & CAN_IF1MCTL_UMASK)
+ {
+ if(usArbReg[1] & CAN_IF1ARB2_XTD)
+ {
+ //
+ // The Identifier Mask is assumed to also be a 29 bit value.
+ //
+ pMsgObject->ulMsgIDMask =
+ ((usMaskReg[1] & CAN_IF1MSK2_IDMSK_M) << 16) | usMaskReg[0];
+ //
+ // If this is a fully specified Mask and a remote frame then don't
+ // set the MSG_OBJ_USE_ID_FILTER because the ID was not really
+ // filtered.
+ //
+ if((pMsgObject->ulMsgIDMask != 0x1fffffff) ||
+ ((pMsgObject->ulFlags & MSG_OBJ_REMOTE_FRAME) == 0))
+ {
+ pMsgObject->ulFlags |= MSG_OBJ_USE_ID_FILTER;
+ }
+ }
+ else
+ {
+ //
+ // The Identifier Mask is assumed to also be an 11 bit value.
+ //
+ pMsgObject->ulMsgIDMask = ((usMaskReg[1] & CAN_IF1MSK2_IDMSK_M) >>
+ 2);
+
+ //
+ // If this is a fully specified Mask and a remote frame then don't
+ // set the MSG_OBJ_USE_ID_FILTER because the ID was not really
+ // filtered.
+ //
+ if((pMsgObject->ulMsgIDMask != 0x7ff) ||
+ ((pMsgObject->ulFlags & MSG_OBJ_REMOTE_FRAME) == 0))
+ {
+ pMsgObject->ulFlags |= MSG_OBJ_USE_ID_FILTER;
+ }
+ }
+
+ //
+ // Indicate if the extended bit was used in filtering.
+ //
+ if(usMaskReg[1] & CAN_IF1MSK2_MXTD)
+ {
+ pMsgObject->ulFlags |= MSG_OBJ_USE_EXT_FILTER;
+ }
+
+ //
+ // Indicate if direction filtering was enabled.
+ //
+ if(usMaskReg[1] & CAN_IF1MSK2_MDIR)
+ {
+ pMsgObject->ulFlags |= MSG_OBJ_USE_DIR_FILTER;
+ }
+ }
+
+ //
+ // Set the interupt flags.
+ //
+ if(usMsgCtrl & CAN_IF1MCTL_TXIE)
+ {
+ pMsgObject->ulFlags |= MSG_OBJ_TX_INT_ENABLE;
+ }
+ if(usMsgCtrl & CAN_IF1MCTL_RXIE)
+ {
+ pMsgObject->ulFlags |= MSG_OBJ_RX_INT_ENABLE;
+ }
+
+ //
+ // See if there is new data available.
+ //
+ if(usMsgCtrl & CAN_IF1MCTL_NEWDAT)
+ {
+ //
+ // Get the amount of data needed to be read.
+ //
+ pMsgObject->ulMsgLen = (usMsgCtrl & CAN_IF1MCTL_DLC_M);
+
+ //
+ // Don't read any data for a remote frame, there is nothing valid in
+ // that buffer anyway.
+ //
+ if((pMsgObject->ulFlags & MSG_OBJ_REMOTE_FRAME) == 0)
+ {
+ //
+ // Read out the data from the CAN registers.
+ //
+ CANDataRegRead(pMsgObject->pucMsgData,
+ (unsigned long *)(ulBase + CAN_O_IF2DA1),
+ pMsgObject->ulMsgLen);
+ }
+
+ //
+ // Now clear out the new data flag.
+ //
+ CANRegWrite(ulBase + CAN_O_IF2CMSK, CAN_IF1CMSK_NEWDAT);
+
+ //
+ // Transfer the message object to the message object specifiec by
+ // ulObjID.
+ //
+ CANRegWrite(ulBase + CAN_O_IF2CRQ, ulObjID & CAN_IF1CRQ_MNUM_M);
+
+ //
+ // Wait for busy bit to clear
+ //
+ while(CANRegRead(ulBase + CAN_O_IF2CRQ) & CAN_IF1CRQ_BUSY)
+ {
+ }
+
+ //
+ // Indicate that there is new data in this message.
+ //
+ pMsgObject->ulFlags |= MSG_OBJ_NEW_DATA;
+ }
+ else
+ {
+ //
+ // Along with the MSG_OBJ_NEW_DATA not being set the amount of data
+ // needs to be set to zero if none was available.
+ //
+ pMsgObject->ulMsgLen = 0;
+ }
+}
+
+//*****************************************************************************
+//
+//! Clears a message object so that it is no longer used.
+//!
+//! \param ulBase is the base address of the CAN controller.
+//! \param ulObjID is the message object number to disable (1-32).
+//!
+//! This function frees the specified message object from use. Once a message
+//! object has been ``cleared,'' it will no longer automatically send or
+//! receive messages, or generate interrupts.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+CANMessageClear(unsigned long ulBase, unsigned long ulObjID)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(CANBaseValid(ulBase));
+ ASSERT((ulObjID >= 1) && (ulObjID <= 32));
+
+ //
+ // Wait for busy bit to clear
+ //
+ while(CANRegRead(ulBase + CAN_O_IF1CRQ) & CAN_IF1CRQ_BUSY)
+ {
+ }
+
+ //
+ // Clear the message value bit in the arbitration register. This indicates
+ // the message is not valid.
+ //
+ CANRegWrite(ulBase + CAN_O_IF1CMSK, CAN_IF1CMSK_WRNRD | CAN_IF1CMSK_ARB);
+ CANRegWrite(ulBase + CAN_O_IF1ARB1, 0);
+ CANRegWrite(ulBase + CAN_O_IF1ARB2, 0);
+
+ //
+ // Initiate programming the message object
+ //
+ CANRegWrite(ulBase + CAN_O_IF1CRQ, ulObjID & CAN_IF1CRQ_MNUM_M);
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
Property changes on: branches/eagle_mmc/src/platform/lm3s/can.c
___________________________________________________________________
Name: svn:executable
+ *
Added: branches/eagle_mmc/src/platform/lm3s/can.h
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/can.h 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lm3s/can.h 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,458 @@
+//*****************************************************************************
+//
+// can.h - Defines and Macros for the CAN controller.
+//
+// Copyright (c) 2006-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __CAN_H__
+#define __CAN_H__
+
+//*****************************************************************************
+//
+//! \addtogroup can_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Miscellaneous defines for Message ID Types
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! These are the flags used by the tCANMsgObject variable when calling the
+//! CANMessageSet() and CANMessageGet() functions.
+//
+//*****************************************************************************
+typedef enum
+{
+ //
+ //! This indicates that transmit interrupts should be enabled, or are
+ //! enabled.
+ //
+ MSG_OBJ_TX_INT_ENABLE = 0x00000001,
+
+ //
+ //! This indicates that receive interrupts should be enabled, or are
+ //! enabled.
+ //
+ MSG_OBJ_RX_INT_ENABLE = 0x00000002,
+
+ //
+ //! This indicates that a message object will use or is using an extended
+ //! identifier.
+ //
+ MSG_OBJ_EXTENDED_ID = 0x00000004,
+
+ //
+ //! This indicates that a message object will use or is using filtering
+ //! based on the object's message identifier.
+ //
+ MSG_OBJ_USE_ID_FILTER = 0x00000008,
+
+ //
+ //! This indicates that new data was available in the message object.
+ //
+ MSG_OBJ_NEW_DATA = 0x00000080,
+
+ //
+ //! This indicates that data was lost since this message object was last
+ //! read.
+ //
+ MSG_OBJ_DATA_LOST = 0x00000100,
+
+ //
+ //! This indicates that a message object will use or is using filtering
+ //! based on the direction of the transfer. If the direction filtering is
+ //! used, then ID filtering must also be enabled.
+ //
+ MSG_OBJ_USE_DIR_FILTER = (0x00000010 | MSG_OBJ_USE_ID_FILTER),
+
+ //
+ //! This indicates that a message object will use or is using message
+ //! identifier filtering based on the extended identifier. If the extended
+ //! identifier filtering is used, then ID filtering must also be enabled.
+ //
+ MSG_OBJ_USE_EXT_FILTER = (0x00000020 | MSG_OBJ_USE_ID_FILTER),
+
+ //
+ //! This indicates that a message object is a remote frame.
+ //
+ MSG_OBJ_REMOTE_FRAME = 0x00000040,
+
+ //
+ //! This indicates that a message object has no flags set.
+ //
+ MSG_OBJ_NO_FLAGS = 0x00000000
+}
+tCANObjFlags;
+
+//*****************************************************************************
+//
+//! This define is used with the #tCANObjFlags enumerated values to allow
+//! checking only status flags and not configuration flags.
+//
+//*****************************************************************************
+#define MSG_OBJ_STATUS_MASK (MSG_OBJ_NEW_DATA | MSG_OBJ_DATA_LOST)
+
+//*****************************************************************************
+//
+//! The structure used for encapsulating all the items associated with a CAN
+//! message object in the CAN controller.
+//
+//*****************************************************************************
+typedef struct
+{
+ //
+ //! The CAN message identifier used for 11 or 29 bit identifiers.
+ //
+ unsigned long ulMsgID;
+
+ //
+ //! The message identifier mask used when identifier filtering is enabled.
+ //
+ unsigned long ulMsgIDMask;
+
+ //
+ //! This value holds various status flags and settings specified by
+ //! tCANObjFlags.
+ //
+ unsigned long ulFlags;
+
+ //
+ //! This value is the number of bytes of data in the message object.
+ //
+ unsigned long ulMsgLen;
+
+ //
+ //! This is a pointer to the message object's data.
+ //
+ unsigned char *pucMsgData;
+}
+tCANMsgObject;
+
+//*****************************************************************************
+//
+//! This structure is used for encapsulating the values associated with setting
+//! up the bit timing for a CAN controller. The structure is used when calling
+//! the CANGetBitTiming and CANSetBitTiming functions.
+//
+//*****************************************************************************
+typedef struct
+{
+ //
+ //! This value holds the sum of the Synchronization, Propagation, and Phase
+ //! Buffer 1 segments, measured in time quanta. The valid values for this
+ //! setting range from 2 to 16.
+ //
+ unsigned int uSyncPropPhase1Seg;
+
+ //
+ //! This value holds the Phase Buffer 2 segment in time quanta. The valid
+ //! values for this setting range from 1 to 8.
+ //
+ unsigned int uPhase2Seg;
+
+ //
+ //! This value holds the Resynchronization Jump Width in time quanta. The
+ //! valid values for this setting range from 1 to 4.
+ //
+ unsigned int uSJW;
+
+ //
+ //! This value holds the CAN_CLK divider used to determine time quanta.
+ //! The valid values for this setting range from 1 to 1023.
+ //
+ unsigned int uQuantumPrescaler;
+}
+tCANBitClkParms;
+
+//*****************************************************************************
+//
+//! This data type is used to identify the interrupt status register. This is
+//! used when calling the CANIntStatus() function.
+//
+//*****************************************************************************
+typedef enum
+{
+ //
+ //! Read the CAN interrupt status information.
+ //
+ CAN_INT_STS_CAUSE,
+
+ //
+ //! Read a message object's interrupt status.
+ //
+ CAN_INT_STS_OBJECT
+}
+tCANIntStsReg;
+
+//*****************************************************************************
+//
+//! This data type is used to identify which of several status registers to
+//! read when calling the CANStatusGet() function.
+//
+//*****************************************************************************
+typedef enum
+{
+ //
+ //! Read the full CAN controller status.
+ //
+ CAN_STS_CONTROL,
+
+ //
+ //! Read the full 32-bit mask of message objects with a transmit request
+ //! set.
+ //
+ CAN_STS_TXREQUEST,
+
+ //
+ //! Read the full 32-bit mask of message objects with new data available.
+ //
+ CAN_STS_NEWDAT,
+
+ //
+ //! Read the full 32-bit mask of message objects that are enabled.
+ //
+ CAN_STS_MSGVAL
+}
+tCANStsReg;
+
+//*****************************************************************************
+//
+//! These definitions are used to specify interrupt sources to CANIntEnable()
+//! and CANIntDisable().
+//
+//*****************************************************************************
+typedef enum
+{
+ //
+ //! This flag is used to allow a CAN controller to generate error
+ //! interrupts.
+ //
+ CAN_INT_ERROR = 0x00000008,
+
+ //
+ //! This flag is used to allow a CAN controller to generate status
+ //! interrupts.
+ //
+ CAN_INT_STATUS = 0x00000004,
+
+ //
+ //! This flag is used to allow a CAN controller to generate any CAN
+ //! interrupts. If this is not set, then no interrupts will be generated
+ //! by the CAN controller.
+ //
+ CAN_INT_MASTER = 0x00000002
+}
+tCANIntFlags;
+
+//*****************************************************************************
+//
+//! This definition is used to determine the type of message object that will
+//! be set up via a call to the CANMessageSet() API.
+//
+//*****************************************************************************
+typedef enum
+{
+ //
+ //! Transmit message object.
+ //
+ MSG_OBJ_TYPE_TX,
+
+ //
+ //! Transmit remote request message object
+ //
+ MSG_OBJ_TYPE_TX_REMOTE,
+
+ //
+ //! Receive message object.
+ //
+ MSG_OBJ_TYPE_RX,
+
+ //
+ //! Receive remote request message object.
+ //
+ MSG_OBJ_TYPE_RX_REMOTE,
+
+ //
+ //! Remote frame receive remote, with auto-transmit message object.
+ //
+ MSG_OBJ_TYPE_RXTX_REMOTE
+}
+tMsgObjType;
+
+//*****************************************************************************
+//
+//! The following enumeration contains all error or status indicators that can
+//! be returned when calling the CANStatusGet() function.
+//
+//*****************************************************************************
+typedef enum
+{
+ //
+ //! CAN controller has entered a Bus Off state.
+ //
+ CAN_STATUS_BUS_OFF = 0x00000080,
+
+ //
+ //! CAN controller error level has reached warning level.
+ //
+ CAN_STATUS_EWARN = 0x00000040,
+
+ //
+ //! CAN controller error level has reached error passive level.
+ //
+ CAN_STATUS_EPASS = 0x00000020,
+
+ //
+ //! A message was received successfully since the last read of this status.
+ //
+ CAN_STATUS_RXOK = 0x00000010,
+
+ //
+ //! A message was transmitted successfully since the last read of this
+ //! status.
+ //
+ CAN_STATUS_TXOK = 0x00000008,
+
+ //
+ //! This is the mask for the last error code field.
+ //
+ CAN_STATUS_LEC_MSK = 0x00000007,
+
+ //
+ //! There was no error.
+ //
+ CAN_STATUS_LEC_NONE = 0x00000000,
+
+ //
+ //! A bit stuffing error has occurred.
+ //
+ CAN_STATUS_LEC_STUFF = 0x00000001,
+
+ //
+ //! A formatting error has occurred.
+ //
+ CAN_STATUS_LEC_FORM = 0x00000002,
+
+ //
+ //! An acknowledge error has occurred.
+ //
+ CAN_STATUS_LEC_ACK = 0x00000003,
+
+ //
+ //! The bus remained a bit level of 1 for longer than is allowed.
+ //
+ CAN_STATUS_LEC_BIT1 = 0x00000004,
+
+ //
+ //! The bus remained a bit level of 0 for longer than is allowed.
+ //
+ CAN_STATUS_LEC_BIT0 = 0x00000005,
+
+ //
+ //! A CRC error has occurred.
+ //
+ CAN_STATUS_LEC_CRC = 0x00000006,
+
+ //
+ //! This is the mask for the CAN Last Error Code (LEC).
+ //
+ CAN_STATUS_LEC_MASK = 0x00000007
+}
+tCANStatusCtrl;
+
+//*****************************************************************************
+//
+// API Function prototypes
+//
+//*****************************************************************************
+extern void CANBitTimingGet(unsigned long ulBase, tCANBitClkParms *pClkParms);
+extern void CANBitTimingSet(unsigned long ulBase, tCANBitClkParms *pClkParms);
+extern unsigned long CANBitRateSet(unsigned long ulBase,
+ unsigned long ulSourceClock,
+ unsigned long ulBitRate);
+extern void CANDisable(unsigned long ulBase);
+extern void CANEnable(unsigned long ulBase);
+extern tBoolean CANErrCntrGet(unsigned long ulBase, unsigned long *pulRxCount,
+ unsigned long *pulTxCount);
+extern void CANInit(unsigned long ulBase);
+extern void CANIntClear(unsigned long ulBase, unsigned long ulIntClr);
+extern void CANIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
+extern void CANIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
+extern void CANIntRegister(unsigned long ulBase, void (*pfnHandler)(void));
+extern unsigned long CANIntStatus(unsigned long ulBase,
+ tCANIntStsReg eIntStsReg);
+extern void CANIntUnregister(unsigned long ulBase);
+extern void CANMessageClear(unsigned long ulBase, unsigned long ulObjID);
+extern void CANMessageGet(unsigned long ulBase, unsigned long ulObjID,
+ tCANMsgObject *pMsgObject, tBoolean bClrPendingInt);
+extern void CANMessageSet(unsigned long ulBase, unsigned long ulObjID,
+ tCANMsgObject *pMsgObject, tMsgObjType eMsgType);
+extern tBoolean CANRetryGet(unsigned long ulBase);
+extern void CANRetrySet(unsigned long ulBase, tBoolean bAutoRetry);
+extern unsigned long CANStatusGet(unsigned long ulBase, tCANStsReg eStatusReg);
+
+//*****************************************************************************
+//
+// Several CAN APIs have been renamed, with the original function name being
+// deprecated. These defines provide backward compatibility.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+#define CANSetBitTiming(a, b) CANBitTimingSet(a, b)
+#define CANGetBitTiming(a, b) CANBitTimingGet(a, b)
+#endif
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+#endif // __CAN_H__
Property changes on: branches/eagle_mmc/src/platform/lm3s/can.h
___________________________________________________________________
Name: svn:executable
+ *
Modified: branches/eagle_mmc/src/platform/lm3s/conf.py
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/conf.py 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lm3s/conf.py 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,5 +1,5 @@
# Configuration file for the LM3S microcontroller
-specific_files = "startup_gcc.c platform.c usart.c sysctl.c gpio.c ssi.c timer.c pwm.c ethernet.c systick.c flash.c interrupt.c cpu.c adc.c"
+specific_files = "startup_gcc.c platform.c uart.c sysctl.c gpio.c ssi.c timer.c pwm.c ethernet.c systick.c flash.c interrupt.c cpu.c adc.c"
if boardname == 'EK-LM3S6965' or boardname == 'EK-LM3S8962':
specific_files = specific_files + " rit128x96x4.c disp.c"
@@ -12,7 +12,10 @@
else:
linkopts = ""
-ldscript = "lm3s.ld"
+if boardname == 'EK-LM3S9B92':
+ ldscript = "lm3s-9b92.ld"
+else:
+ ldscript = "lm3s.ld"
# Prepend with path
specific_files = " ".join( [ "src/platform/%s/%s" % ( platform, f ) for f in specific_files.split() ] )
Modified: branches/eagle_mmc/src/platform/lm3s/cpu.c
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/cpu.c 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lm3s/cpu.c 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,189 +1,189 @@
-//*****************************************************************************
-//
-// cpu.c - Instruction wrappers for special CPU instructions needed by the
-// drivers.
-//
-// Copyright (c) 2006-2008 Luminary Micro, Inc. All rights reserved.
-// Software License Agreement
-//
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
-//
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws. All rights are reserved. You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program. Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
-//
-// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-//
-// This is part of revision 3740 of the Stellaris Peripheral Driver Library.
-//
-//*****************************************************************************
-
-#include "cpu.h"
-
-//*****************************************************************************
-//
-// Wrapper function for the CPSID instruction. Returns the state of PRIMASK
-// on entry.
-//
-//*****************************************************************************
-#if defined(codered) || defined(gcc) || defined(sourcerygxx)
-unsigned long __attribute__((naked))
-CPUcpsid(void)
-{
- unsigned long ulRet;
-
- //
- // Read PRIMASK and disable interrupts.
- //
- __asm(" mrs %0, PRIMASK\n"
- " cpsid i\n"
- " bx lr\n"
- : "=r" (ulRet));
-
- //
- // The return is handled in the inline assembly, but the compiler will
- // still complain if there is not an explicit return here (despite the fact
- // that this does not result in any code being produced because of the
- // naked attribute).
- //
- return(ulRet);
-}
-#endif
-#if defined(ewarm)
-unsigned long
-CPUcpsid(void)
-{
- //
- // Read PRIMASK and disable interrupts.
- //
- __asm(" mrs r0, PRIMASK\n"
- " cpsid i\n");
-
- //
- // "Warning[Pe940]: missing return statement at end of non-void function"
- // is suppressed here to avoid putting a "bx lr" in the inline assembly
- // above and a superfluous return statement here.
- //
-#pragma diag_suppress=Pe940
-}
-#pragma diag_default=Pe940
-#endif
-#if defined(rvmdk) || defined(__ARMCC_VERSION)
-__asm unsigned long
-CPUcpsid(void)
-{
- //
- // Read PRIMASK and disable interrupts.
- //
- mrs r0, PRIMASK;
- cpsid i;
- bx lr
-}
-#endif
-
-//*****************************************************************************
-//
-// Wrapper function for the CPSIE instruction. Returns the state of PRIMASK
-// on entry.
-//
-//*****************************************************************************
-#if defined(codered) || defined(gcc) || defined(sourcerygxx)
-unsigned long __attribute__((naked))
-CPUcpsie(void)
-{
- unsigned long ulRet;
-
- //
- // Read PRIMASK and enable interrupts.
- //
- __asm(" mrs %0, PRIMASK\n"
- " cpsie i\n"
- " bx lr\n"
- : "=r" (ulRet));
-
- //
- // The return is handled in the inline assembly, but the compiler will
- // still complain if there is not an explicit return here (despite the fact
- // that this does not result in any code being produced because of the
- // naked attribute).
- //
- return(ulRet);
-}
-#endif
-#if defined(ewarm)
-unsigned long
-CPUcpsie(void)
-{
- //
- // Read PRIMASK and enable interrupts.
- //
- __asm(" mrs r0, PRIMASK\n"
- " cpsie i\n");
-
- //
- // "Warning[Pe940]: missing return statement at end of non-void function"
- // is suppressed here to avoid putting a "bx lr" in the inline assembly
- // above and a superfluous return statement here.
- //
-#pragma diag_suppress=Pe940
-}
-#pragma diag_default=Pe940
-#endif
-#if defined(rvmdk) || defined(__ARMCC_VERSION)
-__asm unsigned long
-CPUcpsie(void)
-{
- //
- // Read PRIMASK and enable interrupts.
- //
- mrs r0, PRIMASK;
- cpsie i;
- bx lr
-}
-#endif
-
-//*****************************************************************************
-//
-// Wrapper function for the WFI instruction.
-//
-//*****************************************************************************
-#if defined(codered) || defined(gcc) || defined(sourcerygxx)
-void __attribute__((naked))
-CPUwfi(void)
-{
- //
- // Wait for the next interrupt.
- //
- __asm(" wfi\n"
- " bx lr\n");
-}
-#endif
-#if defined(ewarm)
-void
-CPUwfi(void)
-{
- //
- // Wait for the next interrupt.
- //
- __asm(" wfi\n");
-}
-#endif
-#if defined(rvmdk) || defined(__ARMCC_VERSION)
-__asm void
-CPUwfi(void)
-{
- //
- // Wait for the next interrupt.
- //
- wfi;
- bx lr
-}
-#endif
+//*****************************************************************************
+//
+// cpu.c - Instruction wrappers for special CPU instructions needed by the
+// drivers.
+//
+// Copyright (c) 2006-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#include "cpu.h"
+
+//*****************************************************************************
+//
+// Wrapper function for the CPSID instruction. Returns the state of PRIMASK
+// on entry.
+//
+//*****************************************************************************
+#if defined(codered) || defined(gcc) || defined(sourcerygxx)
+unsigned long __attribute__((naked))
+CPUcpsid(void)
+{
+ unsigned long ulRet;
+
+ //
+ // Read PRIMASK and disable interrupts.
+ //
+ __asm(" mrs %0, PRIMASK\n"
+ " cpsid i\n"
+ " bx lr\n"
+ : "=r" (ulRet));
+
+ //
+ // The return is handled in the inline assembly, but the compiler will
+ // still complain if there is not an explicit return here (despite the fact
+ // that this does not result in any code being produced because of the
+ // naked attribute).
+ //
+ return(ulRet);
+}
+#endif
+#if defined(ewarm)
+unsigned long
+CPUcpsid(void)
+{
+ //
+ // Read PRIMASK and disable interrupts.
+ //
+ __asm(" mrs r0, PRIMASK\n"
+ " cpsid i\n");
+
+ //
+ // "Warning[Pe940]: missing return statement at end of non-void function"
+ // is suppressed here to avoid putting a "bx lr" in the inline assembly
+ // above and a superfluous return statement here.
+ //
+#pragma diag_suppress=Pe940
+}
+#pragma diag_default=Pe940
+#endif
+#if defined(rvmdk) || defined(__ARMCC_VERSION)
+__asm unsigned long
+CPUcpsid(void)
+{
+ //
+ // Read PRIMASK and disable interrupts.
+ //
+ mrs r0, PRIMASK;
+ cpsid i;
+ bx lr
+}
+#endif
+
+//*****************************************************************************
+//
+// Wrapper function for the CPSIE instruction. Returns the state of PRIMASK
+// on entry.
+//
+//*****************************************************************************
+#if defined(codered) || defined(gcc) || defined(sourcerygxx)
+unsigned long __attribute__((naked))
+CPUcpsie(void)
+{
+ unsigned long ulRet;
+
+ //
+ // Read PRIMASK and enable interrupts.
+ //
+ __asm(" mrs %0, PRIMASK\n"
+ " cpsie i\n"
+ " bx lr\n"
+ : "=r" (ulRet));
+
+ //
+ // The return is handled in the inline assembly, but the compiler will
+ // still complain if there is not an explicit return here (despite the fact
+ // that this does not result in any code being produced because of the
+ // naked attribute).
+ //
+ return(ulRet);
+}
+#endif
+#if defined(ewarm)
+unsigned long
+CPUcpsie(void)
+{
+ //
+ // Read PRIMASK and enable interrupts.
+ //
+ __asm(" mrs r0, PRIMASK\n"
+ " cpsie i\n");
+
+ //
+ // "Warning[Pe940]: missing return statement at end of non-void function"
+ // is suppressed here to avoid putting a "bx lr" in the inline assembly
+ // above and a superfluous return statement here.
+ //
+#pragma diag_suppress=Pe940
+}
+#pragma diag_default=Pe940
+#endif
+#if defined(rvmdk) || defined(__ARMCC_VERSION)
+__asm unsigned long
+CPUcpsie(void)
+{
+ //
+ // Read PRIMASK and enable interrupts.
+ //
+ mrs r0, PRIMASK;
+ cpsie i;
+ bx lr
+}
+#endif
+
+//*****************************************************************************
+//
+// Wrapper function for the WFI instruction.
+//
+//*****************************************************************************
+#if defined(codered) || defined(gcc) || defined(sourcerygxx)
+void __attribute__((naked))
+CPUwfi(void)
+{
+ //
+ // Wait for the next interrupt.
+ //
+ __asm(" wfi\n"
+ " bx lr\n");
+}
+#endif
+#if defined(ewarm)
+void
+CPUwfi(void)
+{
+ //
+ // Wait for the next interrupt.
+ //
+ __asm(" wfi\n");
+}
+#endif
+#if defined(rvmdk) || defined(__ARMCC_VERSION)
+__asm void
+CPUwfi(void)
+{
+ //
+ // Wait for the next interrupt.
+ //
+ wfi;
+ bx lr
+}
+#endif
Property changes on: branches/eagle_mmc/src/platform/lm3s/cpu.c
___________________________________________________________________
Name: svn:executable
+ *
Modified: branches/eagle_mmc/src/platform/lm3s/cpu.h
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/cpu.h 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lm3s/cpu.h 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,60 +1,60 @@
-//*****************************************************************************
-//
-// cpu.h - Prototypes for the CPU instruction wrapper functions.
-//
-// Copyright (c) 2006-2008 Luminary Micro, Inc. All rights reserved.
-// Software License Agreement
-//
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
-//
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws. All rights are reserved. You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program. Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
-//
-// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-//
-// This is part of revision 3740 of the Stellaris Peripheral Driver Library.
-//
-//*****************************************************************************
-
-#ifndef __CPU_H__
-#define __CPU_H__
-
-//*****************************************************************************
-//
-// If building with a C++ compiler, make all of the definitions in this header
-// have a C binding.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-//*****************************************************************************
-//
-// Prototypes.
-//
-//*****************************************************************************
-extern unsigned long CPUcpsid(void);
-extern unsigned long CPUcpsie(void);
-extern void CPUwfi(void);
-
-//*****************************************************************************
-//
-// Mark the end of the C bindings section for C++ compilers.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-}
-#endif
-
-#endif // __CPU_H__
+//*****************************************************************************
+//
+// cpu.h - Prototypes for the CPU instruction wrapper functions.
+//
+// Copyright (c) 2006-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __CPU_H__
+#define __CPU_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Prototypes.
+//
+//*****************************************************************************
+extern unsigned long CPUcpsid(void);
+extern unsigned long CPUcpsie(void);
+extern void CPUwfi(void);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __CPU_H__
Property changes on: branches/eagle_mmc/src/platform/lm3s/cpu.h
___________________________________________________________________
Name: svn:executable
+ *
Modified: branches/eagle_mmc/src/platform/lm3s/debug.h
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/debug.h 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lm3s/debug.h 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,56 +1,56 @@
-//*****************************************************************************
-//
-// debug.h - Macros for assisting debug of the driver library.
-//
-// Copyright (c) 2006-2008 Luminary Micro, Inc. All rights reserved.
-// Software License Agreement
-//
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
-//
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws. All rights are reserved. You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program. Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
-//
-// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-//
-// This is part of revision 3740 of the Stellaris Peripheral Driver Library.
-//
-//*****************************************************************************
-
-#ifndef __DEBUG_H__
-#define __DEBUG_H__
-
-//*****************************************************************************
-//
-// Prototype for the function that is called when an invalid argument is passed
-// to an API. This is only used when doing a DEBUG build.
-//
-//*****************************************************************************
-extern void __error__(char *pcFilename, unsigned long ulLine);
-
-//*****************************************************************************
-//
-// The ASSERT macro, which does the actual assertion checking. Typically, this
-// will be for procedure arguments.
-//
-//*****************************************************************************
-#ifdef DEBUG
-#define ASSERT(expr) { \
- if(!(expr)) \
- { \
- __error__(__FILE__, __LINE__); \
- } \
- }
-#else
-#define ASSERT(expr)
-#endif
-
-#endif // __DEBUG_H__
+//*****************************************************************************
+//
+// debug.h - Macros for assisting debug of the driver library.
+//
+// Copyright (c) 2006-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DEBUG_H__
+#define __DEBUG_H__
+
+//*****************************************************************************
+//
+// Prototype for the function that is called when an invalid argument is passed
+// to an API. This is only used when doing a DEBUG build.
+//
+//*****************************************************************************
+extern void __error__(char *pcFilename, unsigned long ulLine);
+
+//*****************************************************************************
+//
+// The ASSERT macro, which does the actual assertion checking. Typically, this
+// will be for procedure arguments.
+//
+//*****************************************************************************
+#ifdef DEBUG
+#define ASSERT(expr) { \
+ if(!(expr)) \
+ { \
+ __error__(__FILE__, __LINE__); \
+ } \
+ }
+#else
+#define ASSERT(expr)
+#endif
+
+#endif // __DEBUG_H__
Property changes on: branches/eagle_mmc/src/platform/lm3s/debug.h
___________________________________________________________________
Name: svn:executable
+ *
Modified: branches/eagle_mmc/src/platform/lm3s/ethernet.c
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/ethernet.c 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lm3s/ethernet.c 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,1281 +1,1280 @@
-//*****************************************************************************
-//
-// ethernet.c - Driver for the Integrated Ethernet Controller
-//
-// Copyright (c) 2006-2008 Luminary Micro, Inc. All rights reserved.
-// Software License Agreement
-//
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
-//
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws. All rights are reserved. You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program. Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
-//
-// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-//
-// This is part of revision 3740 of the Stellaris Peripheral Driver Library.
-//
-//*****************************************************************************
-
-//*****************************************************************************
-//
-//! \addtogroup ethernet_api
-//! @{
-//
-//*****************************************************************************
-
-#include "hw_ints.h"
-#include "hw_memmap.h"
-#include "hw_types.h"
-#include "hw_ethernet.h"
-#include "debug.h"
-#include "interrupt.h"
-#include "sysctl.h"
-#include "ethernet.h"
-
-//*****************************************************************************
-//
-//! Initializes the Ethernet controller for operation.
-//!
-//! \param ulBase is the base address of the controller.
-//! \param ulEthClk is the rate of the clock supplied to the Ethernet module.
-//!
-//! This function will prepare the Ethernet controller for first time use in
-//! a given hardware/software configuration. This function should be called
-//! before any other Ethernet API functions are called.
-//!
-//! The peripheral clock will be the same as the processor clock. This will be
-//! the value returned by SysCtlClockGet(), or it can be explicitly hard-coded
-//! if it is constant and known (to save the code/execution overhead of a call
-//! to SysCtlClockGet()).
-//!
-//! This function replaces the original EthernetInit() API and performs the
-//! same actions. A macro is provided in <tt>ethernet.h</tt> to map the
-//! original API to this API.
-//!
-//! \note If the device configuration is changed (for example, the system clock
-//! is reprogrammed to a different speed), then the Ethernet controller must be
-//! disabled by calling the EthernetDisable() function and the controller must
-//! be reinitialized by calling the EthernetInitExpClk() function again. After
-//! the controller has been reinitialized, the controller should be
-//! reconfigured using the appropriate Ethernet API calls.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-EthernetInitExpClk(unsigned long ulBase, unsigned long ulEthClk)
-{
- unsigned long ulDiv;
-
- //
- // Check the arguments.
- //
- ASSERT(ulBase == ETH_BASE);
-
- //
- // Set the Management Clock Divider register for access to the PHY
- // register set (via EthernetPHYRead/Write).
- //
- // The MDC clock divided down from the system clock using the following
- // formula. A maximum of 2.5MHz is allowed for F(mdc).
- //
- // F(mdc) = F(sys) / (2 * (div + 1))
- // div = (F(sys) / (2 * F(mdc))) - 1
- // div = (F(sys) / 2 / F(mdc)) - 1
- //
- // Note: Because we should round up, to ensure we don't violate the
- // maximum clock speed, we can simplify this as follows:
- //
- // div = F(sys) / 2 / F(mdc)
- //
- // For example, given a system clock of 6.0MHz, and a div value of 1,
- // the mdc clock would be programmed as 1.5 MHz.
- //
- ulDiv = (ulEthClk / 2) / 2500000;
- HWREG(ulBase + MAC_O_MDV) = (ulDiv & MAC_MDV_DIV_M);
-}
-
-//*****************************************************************************
-//
-//! Sets the configuration of the Ethernet controller.
-//!
-//! \param ulBase is the base address of the controller.
-//! \param ulConfig is the configuration for the controller.
-//!
-//! After the EthernetInitExpClk() function has been called, this API function
-//! can be used to configure the various features of the Ethernet controller.
-//!
-//! The Ethernet controller provides three control registers that are used
-//! to configure the controller's operation. The transmit control register
-//! provides settings to enable full duplex operation, to auto-generate the
-//! frame check sequence, and to pad the transmit packets to the minimum
-//! length as required by the IEEE standard. The receive control register
-//! provides settings to enable reception of packets with bad frame check
-//! sequence values and to enable multi-cast or promiscuous modes. The
-//! timestamp control register provides settings that enable support logic in
-//! the controller that allow the use of the General Purpose Timer 3 to capture
-//! timestamps for the transmitted and received packets.
-//!
-//! The \e ulConfig parameter is the logical OR of the following values:
-//!
-//! - \b ETH_CFG_TS_TSEN - Enable TX and RX interrupt status as CCP timer
-//! inputs
-//! - \b ETH_CFG_RX_BADCRCDIS - Disable reception of packets with a bad CRC
-//! - \b ETH_CFG_RX_PRMSEN - Enable promiscuous mode reception (all packets)
-//! - \b ETH_CFG_RX_AMULEN - Enable reception of multicast packets
-//! - \b ETH_CFG_TX_DPLXEN - Enable full duplex transmit mode
-//! - \b ETH_CFG_TX_CRCEN - Enable transmit with auto CRC generation
-//! - \b ETH_CFG_TX_PADEN - Enable padding of transmit data to minimum size
-//!
-//! These bit-mapped values are programmed into the transmit, receive, and/or
-//! timestamp control register.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-EthernetConfigSet(unsigned long ulBase, unsigned long ulConfig)
-{
- unsigned long ulTemp;
-
- //
- // Check the arguments.
- //
- ASSERT(ulBase == ETH_BASE);
- ASSERT((ulConfig & ~(ETH_CFG_TX_DPLXEN | ETH_CFG_TX_CRCEN |
- ETH_CFG_TX_PADEN | ETH_CFG_RX_BADCRCDIS |
- ETH_CFG_RX_PRMSEN | ETH_CFG_RX_AMULEN |
- ETH_CFG_TS_TSEN)) == 0);
-
- //
- // Setup the Transmit Control Register.
- //
- ulTemp = HWREG(ulBase + MAC_O_TCTL);
- ulTemp &= ~(MAC_TCTL_DUPLEX | MAC_TCTL_CRC | MAC_TCTL_PADEN);
- ulTemp |= ulConfig & 0x0FF;
- HWREG(ulBase + MAC_O_TCTL) = ulTemp;
-
- //
- // Setup the Receive Control Register.
- //
- ulTemp = HWREG(ulBase + MAC_O_RCTL);
- ulTemp &= ~(MAC_RCTL_BADCRC | MAC_RCTL_PRMS | MAC_RCTL_AMUL);
- ulTemp |= (ulConfig >> 8) & 0x0FF;
- HWREG(ulBase + MAC_O_RCTL) = ulTemp;
-
- //
- // Setup the Time Stamp Configuration register.
- //
- ulTemp = HWREG(ulBase + MAC_O_TS);
- ulTemp &= ~(MAC_TS_TSEN);
- ulTemp |= (ulConfig >> 16) & 0x0FF;
- HWREG(ulBase + MAC_O_TS) = ulTemp;
-}
-
-//*****************************************************************************
-//
-//! Gets the current configuration of the Ethernet controller.
-//!
-//! \param ulBase is the base address of the controller.
-//!
-//! This function will query the control registers of the Ethernet controller
-//! and return a bit-mapped configuration value.
-//!
-//! \sa The description of the EthernetConfigSet() function provides detailed
-//! information for the bit-mapped configuration values that will be returned.
-//!
-//! \return Returns the bit-mapped Ethernet controller configuration value.
-//
-//*****************************************************************************
-unsigned long
-EthernetConfigGet(unsigned long ulBase)
-{
- unsigned long ulConfig;
-
- //
- // Check the arguments.
- //
- ASSERT(ulBase == ETH_BASE);
-
- //
- // Read and return the Ethernet controller configuration parameters,
- // properly shifted into the appropriate bit field positions.
- //
- ulConfig = HWREG(ulBase + MAC_O_TS) << 16;
- ulConfig |= (HWREG(ulBase + MAC_O_RCTL) & ~(MAC_RCTL_RXEN)) << 8;
- ulConfig |= HWREG(ulBase + MAC_O_TCTL) & ~(MAC_TCTL_TXEN);
- return(ulConfig);
-}
-
-//*****************************************************************************
-//
-//! Sets the MAC address of the Ethernet controller.
-//!
-//! \param ulBase is the base address of the controller.
-//! \param pucMACAddr is the pointer to the array of MAC-48 address octets.
-//!
-//! This function will program the IEEE-defined MAC-48 address specified in
-//! \e pucMACAddr into the Ethernet controller. This address is used by the
-//! Ethernet controller for hardware-level filtering of incoming Ethernet
-//! packets (when promiscuous mode is not enabled).
-//!
-//! The MAC-48 address is defined as 6 octets, illustrated by the following
-//! example address. The numbers are shown in hexadecimal format.
-//!
-//! AC-DE-48-00-00-80
-//!
-//! In this representation, the first three octets (AC-DE-48) are the
-//! Organizationally Unique Identifier (OUI). This is a number assigned by
-//! the IEEE to an organization that requests a block of MAC addresses. The
-//! last three octets (00-00-80) are a 24-bit number managed by the OUI owner
-//! to uniquely identify a piece of hardware within that organization that is
-//! to be connected to the Ethernet.
-//!
-//! In this representation, the octets are transmitted from left to right,
-//! with the ``AC'' octet being transmitted first and the ``80'' octet being
-//! transmitted last. Within an octet, the bits are transmitted LSB to MSB.
-//! For this address, the first bit to be transmitted would be ``0'', the LSB
-//! of ``AC'', and the last bit to be transmitted would be ``1'', the MSB of
-//! ``80''.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-EthernetMACAddrSet(unsigned long ulBase, unsigned char *pucMACAddr)
-{
- unsigned long ulTemp;
- unsigned char *pucTemp = (unsigned char *)&ulTemp;
-
- //
- // Check the arguments.
- //
- ASSERT(ulBase == ETH_BASE);
- ASSERT(pucMACAddr != 0);
-
- //
- // Program the MAC Address into the device. The first four bytes of the
- // MAC Address are placed into the IA0 register. The remaining two bytes
- // of the MAC address are placed into the IA1 register.
- //
- pucTemp[0] = pucMACAddr[0];
- pucTemp[1] = pucMACAddr[1];
- pucTemp[2] = pucMACAddr[2];
- pucTemp[3] = pucMACAddr[3];
- HWREG(ulBase + MAC_O_IA0) = ulTemp;
- ulTemp = 0;
- pucTemp[0] = pucMACAddr[4];
- pucTemp[1] = pucMACAddr[5];
- HWREG(ulBase + MAC_O_IA1) = ulTemp;
-}
-
-//*****************************************************************************
-//
-//! Gets the MAC address of the Ethernet controller.
-//!
-//! \param ulBase is the base address of the controller.
-//! \param pucMACAddr is the pointer to the location in which to store the
-//! array of MAC-48 address octets.
-//!
-//! This function will read the currently programmed MAC address into the
-//! \e pucMACAddr buffer.
-//!
-//! \sa Refer to EthernetMACAddrSet() API description for more details about
-//! the MAC address format.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-EthernetMACAddrGet(unsigned long ulBase, unsigned char *pucMACAddr)
-{
- unsigned long ulTemp;
- unsigned char *pucTemp = (unsigned char *)&ulTemp;
-
- //
- // Check the arguments.
- //
- ASSERT(ulBase == ETH_BASE);
- ASSERT(pucMACAddr != 0);
-
- //
- // Read the MAC address from the device. The first four bytes of the
- // MAC address are read from the IA0 register. The remaining two bytes
- // of the MAC addres
- //
- ulTemp = HWREG(ulBase + MAC_O_IA0);
- pucMACAddr[0] = pucTemp[0];
- pucMACAddr[1] = pucTemp[1];
- pucMACAddr[2] = pucTemp[2];
- pucMACAddr[3] = pucTemp[3];
- ulTemp = HWREG(ulBase + MAC_O_IA1);
- pucMACAddr[4] = pucTemp[0];
- pucMACAddr[5] = pucTemp[1];
-}
-
-//*****************************************************************************
-//
-//! Enables the Ethernet controller for normal operation.
-//!
-//! \param ulBase is the base address of the controller.
-//!
-//! Once the Ethernet controller has been configured using the
-//! EthernetConfigSet() function and the MAC address has been programmed using
-//! the EthernetMACAddrSet() function, this API function can be called to
-//! enable the controller for normal operation.
-//!
-//! This function will enable the controller's transmitter and receiver, and
-//! will reset the receive FIFO.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-EthernetEnable(unsigned long ulBase)
-{
- //
- // Check the arguments.
- //
- ASSERT(ulBase == ETH_BASE);
-
- //
- // Reset the receive FIFO.
- //
- HWREG(ulBase + MAC_O_RCTL) |= MAC_RCTL_RSTFIFO;
-
- //
- // Enable the Ethernet receiver.
- //
- HWREG(ulBase + MAC_O_RCTL) |= MAC_RCTL_RXEN;
-
- //
- // Enable Ethernet transmitter.
- //
- HWREG(ulBase + MAC_O_TCTL) |= MAC_TCTL_TXEN;
-
- //
- // Reset the receive FIFO again, after the receiver has been enabled.
- //
- HWREG(ulBase + MAC_O_RCTL) |= MAC_RCTL_RSTFIFO;
-}
-
-//*****************************************************************************
-//
-//! Disables the Ethernet controller.
-//!
-//! \param ulBase is the base address of the controller.
-//!
-//! When terminating operations on the Ethernet interface, this function should
-//! be called. This function will disable the transmitter and receiver, and
-//! will clear out the receive FIFO.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-EthernetDisable(unsigned long ulBase)
-{
- //
- // Check the arguments.
- //
- ASSERT(ulBase == ETH_BASE);
-
- //
- // Reset the receive FIFO.
- //
- HWREG(ulBase + MAC_O_RCTL) |= MAC_RCTL_RSTFIFO;
-
- //
- // Disable the Ethernet transmitter.
- //
- HWREG(ulBase + MAC_O_TCTL) &= ~(MAC_TCTL_TXEN);
-
- //
- // Disable the Ethernet receiver.
- //
- HWREG(ulBase + MAC_O_RCTL) &= ~(MAC_RCTL_RXEN);
-
- //
- // Reset the receive FIFO again, after the receiver has been disabled.
- //
- HWREG(ulBase + MAC_O_RCTL) |= MAC_RCTL_RSTFIFO;
-}
-
-//*****************************************************************************
-//
-//! Check for packet available from the Ethernet controller.
-//!
-//! \param ulBase is the base address of the controller.
-//!
-//! The Ethernet controller provides a register that contains the number of
-//! packets available in the receive FIFO. When the last bytes of a packet are
-//! successfully received (that is, the frame check sequence bytes), the packet
-//! count is incremented. Once the packet has been fully read (including the
-//! frame check sequence bytes) from the FIFO, the packet count will be
-//! decremented.
-//!
-//! \return Returns \b true if there are one or more packets available in the
-//! receive FIFO, including the current packet being read, and \b false
-//! otherwise.
-//
-//*****************************************************************************
-tBoolean
-EthernetPacketAvail(unsigned long ulBase)
-{
- //
- // Check the arguments.
- //
- ASSERT(ulBase == ETH_BASE);
-
- //
- // Return the availability of packets.
- //
- return((HWREG(ulBase + MAC_O_NP) & MAC_NP_NPR_M) ? true : false);
-}
-
-//*****************************************************************************
-//
-//! Checks for packet space available in the Ethernet controller.
-//!
-//! \param ulBase is the base address of the controller.
-//!
-//! The Ethernet controller's transmit FIFO is designed to support a single
-//! packet at a time. After the packet has been written into the FIFO, the
-//! transmit request bit must be set to enable the transmission of the packet.
-//! Only after the packet has been transmitted can a new packet be written
-//! into the FIFO. This function will simply check to see if a packet is
-//! in progress. If so, there is no space available in the transmit FIFO.
-//!
-//! \return Returns \b true if a space is available in the transmit FIFO, and
-//! \b false otherwise.
-//
-//*****************************************************************************
-tBoolean
-EthernetSpaceAvail(unsigned long ulBase)
-{
- //
- // Check the arguments.
- //
- ASSERT(ulBase == ETH_BASE);
-
- //
- // Return the availability of space.
- //
- return((HWREG(ulBase + MAC_O_TR) & MAC_TR_NEWTX) ? false : true);
-}
-
-//*****************************************************************************
-//
-//! \internal
-//!
-//! Internal function for reading a packet from the Ethernet controller.
-//!
-//! \param ulBase is the base address of the controller.
-//! \param pucBuf is the pointer to the packet buffer.
-//! \param lBufLen is the maximum number of bytes to be read into the buffer.
-//!
-//! Based on the following table of how the receive frame is stored in the
-//! receive FIFO, this function will extract a packet from the FIFO and store
-//! it in the packet buffer that was passed in.
-//!
-//! Format of the data in the RX FIFO is as follows:
-//!
-//! \verbatim
-//! +---------+----------+----------+----------+----------+
-//! | | 31:24 | 23:16 | 15:8 | 7:0 |
-//! +---------+----------+----------+----------+----------+
-//! | Word 0 | DA 2 | DA 1 | FL MSB | FL LSB |
-//! +---------+----------+----------+----------+----------+
-//! | Word 1 | DA 6 | DA 5 | DA 4 | DA 3 |
-//! +---------+----------+----------+----------+----------+
-//! | Word 2 | SA 4 | SA 3 | SA 2 | SA 1 |
-//! +---------+----------+----------+----------+----------+
-//! | Word 3 | FT LSB | FT MSB | SA 6 | SA 5 |
-//! +---------+----------+----------+----------+----------+
-//! | Word 4 | DATA 4 | DATA 3 | DATA 2 | DATA 1 |
-//! +---------+----------+----------+----------+----------+
-//! | Word 5 | DATA 8 | DATA 7 | DATA 6 | DATA 5 |
-//! +---------+----------+----------+----------+----------+
-//! | Word 6 | DATA 12 | DATA 11 | DATA 10 | DATA 9 |
-//! +---------+----------+----------+----------+----------+
-//! | ... | | | | |
-//! +---------+----------+----------+----------+----------+
-//! | Word X | DATA n | DATA n-1 | DATA n-2 | DATA n-3 |
-//! +---------+----------+----------+----------+----------+
-//! | Word Y | FCS 4 | FCS 3 | FCS 2 | FCS 1 |
-//! +---------+----------+----------+----------+----------+
-//! \endverbatim
-//!
-//! Where FL is Frame Length, (FL + DA + SA + FT + DATA + FCS) Bytes.
-//! Where DA is Destination (MAC) Address.
-//! Where SA is Source (MAC) Address.
-//! Where FT is Frame Type (or Frame Length for Ethernet).
-//! Where DATA is Payload Data for the Ethernet Frame.
-//! Where FCS is the Frame Check Sequence.
-//!
-//! \return Returns the negated packet length \b -n if the packet is too large
-//! for \e pucBuf, and returns the packet length \b n otherwise.
-//
-//*****************************************************************************
-static long
-EthernetPacketGetInternal(unsigned long ulBase, unsigned char *pucBuf,
- long lBufLen)
-{
- unsigned long ulTemp;
- long lFrameLen, lTempLen;
- long i = 0;
-
- //
- // Read WORD 0 (see format above) from the FIFO, set the receive
- // Frame Length and store the first two bytes of the destination
- // address in the receive buffer.
- //
- ulTemp = HWREG(ulBase + MAC_O_DATA);
- lFrameLen = (long)(ulTemp & 0xFFFF);
- pucBuf[i++] = (unsigned char) ((ulTemp >> 16) & 0xff);
- pucBuf[i++] = (unsigned char) ((ulTemp >> 24) & 0xff);
-
- //
- // Read all but the last WORD into the receive buffer.
- //
- lTempLen = (lBufLen < (lFrameLen - 6)) ? lBufLen : (lFrameLen - 6);
- while(i <= (lTempLen - 4))
- {
- *(unsigned long *)&pucBuf[i] = HWREG(ulBase + MAC_O_DATA);
- i += 4;
- }
-
- //
- // Read the last 1, 2, or 3 BYTES into the buffer
- //
- if(i < lTempLen)
- {
- ulTemp = HWREG(ulBase + MAC_O_DATA);
- if(i == lTempLen - 3)
- {
- pucBuf[i++] = ((ulTemp >> 0) & 0xff);
- pucBuf[i++] = ((ulTemp >> 8) & 0xff);
- pucBuf[i++] = ((ulTemp >> 16) & 0xff);
- i += 1;
- }
- else if(i == lTempLen - 2)
- {
- pucBuf[i++] = ((ulTemp >> 0) & 0xff);
- pucBuf[i++] = ((ulTemp >> 8) & 0xff);
- i += 2;
- }
- else if(i == lTempLen - 1)
- {
- pucBuf[i++] = ((ulTemp >> 0) & 0xff);
- i += 3;
- }
- }
-
- //
- // Read any remaining WORDS (that did not fit into the buffer).
- //
- while(i < (lFrameLen - 2))
- {
- ulTemp = HWREG(ulBase + MAC_O_DATA);
- i += 4;
- }
-
- //
- // If frame was larger than the buffer, return the "negative" frame length
- //
- lFrameLen -= 6;
- if(lFrameLen > lBufLen)
- {
- return(-lFrameLen);
- }
-
- //
- // Return the Frame Length
- //
- return(lFrameLen);
-}
-
-//*****************************************************************************
-//
-//! Receives a packet from the Ethernet controller.
-//!
-//! \param ulBase is the base address of the controller.
-//! \param pucBuf is the pointer to the packet buffer.
-//! \param lBufLen is the maximum number of bytes to be read into the buffer.
-//!
-//! This function reads a packet from the receive FIFO of the controller and
-//! places it into \e pucBuf. If no packet is available the function will
-//! return immediately. Otherwise, the function will read the entire packet
-//! from the receive FIFO. If there are more bytes in the packet than will fit
-//! into \e pucBuf (as specified by \e lBufLen), the function will return the
-//! negated length of the packet and the buffer will contain \e lBufLen bytes
-//! of the packet. Otherwise, the function will return the length of the
-//! packet that was read and \e pucBuf will contain the entire packet
-//! (excluding the frame check sequence bytes).
-//!
-//! This function replaces the original EthernetPacketNonBlockingGet() API and
-//! performs the same actions. A macro is provided in <tt>ethernet.h</tt> to
-//! map the original API to this API.
-//!
-//! \note This function will return immediately if no packet is available.
-//!
-//! \return Returns \b 0 if no packet is available, the negated packet length
-//! \b -n if the packet is too large for \e pucBuf, and the packet length \b n
-//! otherwise.
-//
-//*****************************************************************************
-long
-EthernetPacketGetNonBlocking(unsigned long ulBase, unsigned char *pucBuf,
- long lBufLen)
-{
- //
- // Check the arguments.
- //
- ASSERT(ulBase == ETH_BASE);
- ASSERT(pucBuf != 0);
- ASSERT(lBufLen > 0);
-
- //
- // Check to see if any packets are available.
- //
- if((HWREG(ulBase + MAC_O_NP) & MAC_NP_NPR_M) == 0)
- {
- return(0);
- }
-
- //
- // Read the packet, and return.
- //
- return(EthernetPacketGetInternal(ulBase, pucBuf, lBufLen));
-}
-
-//*****************************************************************************
-//
-//! Waits for a packet from the Ethernet controller.
-//!
-//! \param ulBase is the base address of the controller.
-//! \param pucBuf is the pointer to the packet buffer.
-//! \param lBufLen is the maximum number of bytes to be read into the buffer.
-//!
-//! This function reads a packet from the receive FIFO of the controller and
-//! places it into \e pucBuf. The function will wait until a packet is
-//! available in the FIFO. Then the function will read the entire packet
-//! from the receive FIFO. If there are more bytes in the packet than will
-//! fit into \e pucBuf (as specified by \e lBufLen), the function will return
-//! the negated length of the packet and the buffer will contain \e lBufLen
-//! bytes of the packet. Otherwise, the function will return the length of
-//! the packet that was read and \e pucBuf will contain the entire packet
-//! (excluding the frame check sequence bytes).
-//!
-//! \note This function is blocking and will not return until a packet arrives.
-//!
-//! \return Returns the negated packet length \b -n if the packet is too large
-//! for \e pucBuf, and returns the packet length \b n otherwise.
-//
-//*****************************************************************************
-long
-EthernetPacketGet(unsigned long ulBase, unsigned char *pucBuf,
- long lBufLen)
-{
- //
- // Check the arguments.
- //
- ASSERT(ulBase == ETH_BASE);
- ASSERT(pucBuf != 0);
- ASSERT(lBufLen > 0);
-
- //
- // Wait for a packet to become available
- //
- while((HWREG(ulBase + MAC_O_NP) & MAC_NP_NPR_M) == 0)
- {
- }
-
- //
- // Read the packet
- //
- return(EthernetPacketGetInternal(ulBase, pucBuf, lBufLen));
-}
-
-//*****************************************************************************
-//
-//! \internal
-//!
-//! Internal function for sending a packet to the Ethernet controller.
-//!
-//! \param ulBase is the base address of the controller.
-//! \param pucBuf is the pointer to the packet buffer.
-//! \param lBufLen is number of bytes in the packet to be transmitted.
-//!
-//! Puts a packet into the transmit FIFO of the controller.
-//!
-//! Format of the data in the TX FIFO is as follows:
-//!
-//! \verbatim
-//! +---------+----------+----------+----------+----------+
-//! | | 31:24 | 23:16 | 15:8 | 7:0 |
-//! +---------+----------+----------+----------+----------+
-//! | Word 0 | DA 2 | DA 1 | PL MSB | PL LSB |
-//! +---------+----------+----------+----------+----------+
-//! | Word 1 | DA 6 | DA 5 | DA 4 | DA 3 |
-//! +---------+----------+----------+----------+----------+
-//! | Word 2 | SA 4 | SA 3 | SA 2 | SA 1 |
-//! +---------+----------+----------+----------+----------+
-//! | Word 3 | FT LSB | FT MSB | SA 6 | SA 5 |
-//! +---------+----------+----------+----------+----------+
-//! | Word 4 | DATA 4 | DATA 3 | DATA 2 | DATA 1 |
-//! +---------+----------+----------+----------+----------+
-//! | Word 5 | DATA 8 | DATA 7 | DATA 6 | DATA 5 |
-//! +---------+----------+----------+----------+----------+
-//! | Word 6 | DATA 12 | DATA 11 | DATA 10 | DATA 9 |
-//! +---------+----------+----------+----------+----------+
-//! | ... | | | | |
-//! +---------+----------+----------+----------+----------+
-//! | Word X | DATA n | DATA n-1 | DATA n-2 | DATA n-3 |
-//! +---------+----------+----------+----------+----------+
-//! \endverbatim
-//!
-//! Where PL is Payload Length, (DATA) only
-//! Where DA is Destination (MAC) Address
-//! Where SA is Source (MAC) Address
-//! Where FT is Frame Type (or Frame Length for Ethernet)
-//! Where DATA is Payload Data for the Ethernet Frame
-//!
-//! \return Returns the negated packet length \b -lBufLen if the packet is too
-//! large for FIFO, and the packet length \b lBufLen otherwise.
-//
-//*****************************************************************************
-static long
-EthernetPacketPutInternal(unsigned long ulBase, unsigned char *pucBuf,
- long lBufLen)
-{
- unsigned long ulTemp;
- long i = 0;
-
- //
- // If the packet is too large, return the negative packet length as
- // an error code.
- //
- if(lBufLen > (2048 - 2))
- {
- return(-lBufLen);
- }
-
- //
- // Build and write WORD 0 (see format above) to the transmit FIFO.
- //
- ulTemp = (unsigned long)(lBufLen - 14);
- ulTemp |= (pucBuf[i++] << 16);
- ulTemp |= (pucBuf[i++] << 24);
- HWREG(ulBase + MAC_O_DATA) = ulTemp;
-
- //
- // Write each subsequent WORD n to the transmit FIFO, except for the last
- // WORD (if the word does not contain 4 bytes).
- //
- while(i <= (lBufLen - 4))
- {
- HWREG(ulBase + MAC_O_DATA) = *(unsigned long *)&pucBuf[i];
- i += 4;
- }
-
- //
- // Build the last word of the remaining 1, 2, or 3 bytes, and store
- // the WORD into the transmit FIFO.
- //
- if(i != lBufLen)
- {
- if(i == (lBufLen - 3))
- {
- ulTemp = (pucBuf[i++] << 0);
- ulTemp |= (pucBuf[i++] << 8);
- ulTemp |= (pucBuf[i++] << 16);
- HWREG(ulBase + MAC_O_DATA) = ulTemp;
- }
- else if(i == (lBufLen - 2))
- {
- ulTemp = (pucBuf[i++] << 0);
- ulTemp |= (pucBuf[i++] << 8);
- HWREG(ulBase + MAC_O_DATA) = ulTemp;
- }
- else if(i == (lBufLen - 1))
- {
- ulTemp = (pucBuf[i++] << 0);
- HWREG(ulBase + MAC_O_DATA) = ulTemp;
- }
- }
-
- //
- // Activate the transmitter
- //
- HWREG(ulBase + MAC_O_TR) = MAC_TR_NEWTX;
-
- //
- // Return the Buffer Length transmitted.
- //
- return(lBufLen);
-}
-
-//*****************************************************************************
-//
-//! Sends a packet to the Ethernet controller.
-//!
-//! \param ulBase is the base address of the controller.
-//! \param pucBuf is the pointer to the packet buffer.
-//! \param lBufLen is number of bytes in the packet to be transmitted.
-//!
-//! This function writes \e lBufLen bytes of the packet contained in \e pucBuf
-//! into the transmit FIFO of the controller and then activates the
-//! transmitter for this packet. If no space is available in the FIFO, the
-//! function will return immediately. If space is available, the
-//! function will return once \e lBufLen bytes of the packet have been placed
-//! into the FIFO and the transmitter has been started. The function will not
-//! wait for the transmission to complete. The function will return the
-//! negated \e lBufLen if the length is larger than the space available in
-//! the transmit FIFO.
-//!
-//! This function replaces the original EthernetPacketNonBlockingPut() API and
-//! performs the same actions. A macro is provided in <tt>ethernet.h</tt> to
-//! map the original API to this API.
-//!
-//! \note This function does not block and will return immediately if no space
-//! is available for the transmit packet.
-//!
-//! \return Returns \b 0 if no space is available in the transmit FIFO, the
-//! negated packet length \b -lBufLen if the packet is too large for FIFO, and
-//! the packet length \b lBufLen otherwise.
-//
-//*****************************************************************************
-long
-EthernetPacketPutNonBlocking(unsigned long ulBase, unsigned char *pucBuf,
- long lBufLen)
-{
- //
- // Check the arguments.
- //
- ASSERT(ulBase == ETH_BASE);
- ASSERT(pucBuf != 0);
- ASSERT(lBufLen > 0);
-
- //
- // Check if the transmit FIFO is in use and return the appropriate code.
- //
- if(HWREG(ulBase + MAC_O_TR) & MAC_TR_NEWTX)
- {
- return(0);
- }
-
- //
- // Send the packet and return.
- //
- return(EthernetPacketPutInternal(ulBase, pucBuf, lBufLen));
-}
-
-//*****************************************************************************
-//
-//! Waits to send a packet from the Ethernet controller.
-//!
-//! \param ulBase is the base address of the controller.
-//! \param pucBuf is the pointer to the packet buffer.
-//! \param lBufLen is number of bytes in the packet to be transmitted.
-//!
-//! This function writes \e lBufLen bytes of the packet contained in \e pucBuf
-//! into the transmit FIFO of the controller and then activates the transmitter
-//! for this packet. This function will wait until the transmit FIFO is empty.
-//! Once space is available, the function will return once \e lBufLen bytes of
-//! the packet have been placed into the FIFO and the transmitter has been
-//! started. The function will not wait for the transmission to complete. The
-//! function will return the negated \e lBufLen if the length is larger than
-//! the space available in the transmit FIFO.
-//!
-//! \note This function blocks and will wait until space is available for the
-//! transmit packet before returning.
-//!
-//! \return Returns the negated packet length \b -lBufLen if the packet is too
-//! large for FIFO, and the packet length \b lBufLen otherwise.
-//
-//*****************************************************************************
-long
-EthernetPacketPut(unsigned long ulBase, unsigned char *pucBuf,
- long lBufLen)
-{
- //
- // Check the arguments.
- //
- ASSERT(ulBase == ETH_BASE);
- ASSERT(pucBuf != 0);
- ASSERT(lBufLen > 0);
-
- //
- // Wait for current packet (if any) to complete.
- //
- while(HWREG(ulBase + MAC_O_TR) & MAC_TR_NEWTX)
- {
- }
-
- //
- // Send the packet and return.
- //
- return(EthernetPacketPutInternal(ulBase, pucBuf, lBufLen));
-}
-
-//*****************************************************************************
-//
-//! Registers an interrupt handler for an Ethernet interrupt.
-//!
-//! \param ulBase is the base address of the controller.
-//! \param pfnHandler is a pointer to the function to be called when the
-//! enabled Ethernet interrupts occur.
-//!
-//! This function sets the handler to be called when the Ethernet interrupt
-//! occurs. This will enable the global interrupt in the interrupt controller;
-//! specific Ethernet interrupts must be enabled via EthernetIntEnable(). It
-//! is the interrupt handler's responsibility to clear the interrupt source.
-//!
-//! \sa IntRegister() for important information about registering interrupt
-//! handlers.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-EthernetIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
-{
- //
- // Check the arguments.
- //
- ASSERT(ulBase == ETH_BASE);
- ASSERT(pfnHandler != 0);
-
- //
- // Register the interrupt handler.
- //
- IntRegister(INT_ETH, pfnHandler);
-
- //
- // Enable the Ethernet interrupt.
- //
- IntEnable(INT_ETH);
-}
-
-//*****************************************************************************
-//
-//! Unregisters an interrupt handler for an Ethernet interrupt.
-//!
-//! \param ulBase is the base address of the controller.
-//!
-//! This function unregisters the interrupt handler. This will disable the
-//! global interrupt in the interrupt controller so that the interrupt handler
-//! no longer is called.
-//!
-//! \sa IntRegister() for important information about registering interrupt
-//! handlers.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-EthernetIntUnregister(unsigned long ulBase)
-{
- //
- // Check the arguments.
- //
- ASSERT(ulBase == ETH_BASE);
-
- //
- // Disable the interrupt.
- //
- IntDisable(INT_ETH);
-
- //
- // Unregister the interrupt handler.
- //
- IntUnregister(INT_ETH);
-}
-
-//*****************************************************************************
-//
-//! Enables individual Ethernet interrupt sources.
-//!
-//! \param ulBase is the base address of the controller.
-//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.
-//!
-//! Enables the indicated Ethernet interrupt sources. Only the sources that
-//! are enabled can be reflected to the processor interrupt; disabled sources
-//! have no effect on the processor.
-//!
-//! The \e ulIntFlags parameter is the logical OR of any of the following:
-//!
-//! - \b ETH_INT_PHY - An interrupt from the PHY has occurred. The integrated
-//! PHY supports a number of interrupt conditions. The PHY register, PHY_MR17,
-//! must be read to determine which PHY interrupt has occurred. This register
-//! can be read using the EthernetPHYRead() API function.
-//! - \b ETH_INT_MDIO - This interrupt indicates that a transaction on the
-//! management interface has completed successfully.
-//! - \b ETH_INT_RXER - This interrupt indicates that an error has occurred
-//! during reception of a frame. This error can indicate a length mismatch, a
-//! CRC failure, or an error indication from the PHY.
-//! - \b ETH_INT_RXOF - This interrupt indicates that a frame has been received
-//! that exceeds the available space in the RX FIFO.
-//! - \b ETH_INT_TX - This interrupt indicates that the packet stored in the TX
-//! FIFO has been successfully transmitted.
-//! - \b ETH_INT_TXER - This interrupt indicates that an error has occurred
-//! during the transmission of a packet. This error can be either a retry
-//! failure during the back-off process, or an invalid length stored in the TX
-//! FIFO.
-//! - \b ETH_INT_RX - This interrupt indicates that one (or more) packets are
-//! available in the RX FIFO for processing.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-EthernetIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
-{
- //
- // Check the arguments.
- //
- ASSERT(ulBase == ETH_BASE);
- ASSERT(!(ulIntFlags & ~(ETH_INT_PHY | ETH_INT_MDIO | ETH_INT_RXER |
- ETH_INT_RXOF | ETH_INT_TX | ETH_INT_TXER |
- ETH_INT_RX)));
-
- //
- // Enable the specified interrupts.
- //
- HWREG(ulBase + MAC_O_IM) |= ulIntFlags;
-}
-
-//*****************************************************************************
-//
-//! Disables individual Ethernet interrupt sources.
-//!
-//! \param ulBase is the base address of the controller.
-//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled.
-//!
-//! Disables the indicated Ethernet interrupt sources. Only the sources that
-//! are enabled can be reflected to the processor interrupt; disabled sources
-//! have no effect on the processor.
-//!
-//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
-//! parameter to EthernetIntEnable().
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-EthernetIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
-{
- //
- // Check the arguments.
- //
- ASSERT(ulBase == ETH_BASE);
- ASSERT(!(ulIntFlags & ~(ETH_INT_PHY | ETH_INT_MDIO | ETH_INT_RXER |
- ETH_INT_RXOF | ETH_INT_TX | ETH_INT_TXER |
- ETH_INT_RX)));
-
- //
- // Disable the specified interrupts.
- //
- HWREG(ulBase + MAC_O_IM) &= ~ulIntFlags;
-}
-
-//*****************************************************************************
-//
-//! Gets the current Ethernet interrupt status.
-//!
-//! \param ulBase is the base address of the controller.
-//! \param bMasked is false if the raw interrupt status is required and true
-//! if the masked interrupt status is required.
-//!
-//! This returns the interrupt status for the Ethernet controller. Either the
-//! raw interrupt status or the status of interrupts that are allowed to
-//! reflect to the processor can be returned.
-//!
-//! \return Returns the current interrupt status, enumerated as a bit field of
-//! values described in EthernetIntEnable().
-//
-//*****************************************************************************
-unsigned long
-EthernetIntStatus(unsigned long ulBase, tBoolean bMasked)
-{
- unsigned long ulStatus;
-
- //
- // Check the arguments.
- //
- ASSERT(ulBase == ETH_BASE);
-
- //
- // Read the unmasked status.
- //
- ulStatus = HWREG(ulBase + MAC_O_RIS);
-
- //
- // If masked status is requested, mask it off.
- //
- if(bMasked)
- {
- ulStatus &= HWREG(ulBase + MAC_O_IM);
- }
-
- //
- // Return the interrupt status value.
- //
- return(ulStatus);
-}
-
-//*****************************************************************************
-//
-//! Clears Ethernet interrupt sources.
-//!
-//! \param ulBase is the base address of the controller.
-//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
-//!
-//! The specified Ethernet interrupt sources are cleared so that they no longer
-//! assert. This must be done in the interrupt handler to keep it from being
-//! called again immediately upon exit.
-//!
-//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
-//! parameter to EthernetIntEnable().
-//!
-//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
-//! several clock cycles before the interrupt source is actually cleared.
-//! Therefore, it is recommended that the interrupt source be cleared early in
-//! the interrupt handler (as opposed to the very last action) to avoid
-//! returning from the interrupt handler before the interrupt source is
-//! actually cleared. Failure to do so may result in the interrupt handler
-//! being immediately reentered (since NVIC still sees the interrupt source
-//! asserted).
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-EthernetIntClear(unsigned long ulBase, unsigned long ulIntFlags)
-{
- //
- // Check the arguments.
- //
- ASSERT(ulBase == ETH_BASE);
- ASSERT(!(ulIntFlags & ~(ETH_INT_PHY | ETH_INT_MDIO | ETH_INT_RXER |
- ETH_INT_RXOF | ETH_INT_TX | ETH_INT_TXER |
- ETH_INT_RX)));
-
- //
- // Clear the requested interrupt sources.
- //
- HWREG(ulBase + MAC_O_IACK) = ulIntFlags;
-}
-
-//*****************************************************************************
-//
-//! Writes to the PHY register.
-//!
-//! \param ulBase is the base address of the controller.
-//! \param ucRegAddr is the address of the PHY register to be accessed.
-//! \param ulData is the data to be written to the PHY register.
-//!
-//! This function will write the \e ulData to the PHY register specified by
-//! \e ucRegAddr.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-EthernetPHYWrite(unsigned long ulBase, unsigned char ucRegAddr,
- unsigned long ulData)
-{
- //
- // Check the arguments.
- //
- ASSERT(ulBase == ETH_BASE);
-
- //
- // Wait for any pending transaction to complete.
- //
- while(HWREG(ulBase + MAC_O_MCTL) & MAC_MCTL_START)
- {
- }
-
- //
- // Program the DATA to be written.
- //
- HWREG(ulBase + MAC_O_MTXD) = ulData & MAC_MTXD_MDTX_M;
-
- //
- // Program the PHY register address and initiate the transaction.
- //
- HWREG(ulBase + MAC_O_MCTL) = (((ucRegAddr << 3) & MAC_MCTL_REGADR_M) |
- MAC_MCTL_WRITE | MAC_MCTL_START);
-
- //
- // Wait for the write transaction to complete.
- //
- while(HWREG(ulBase + MAC_O_MCTL) & MAC_MCTL_START)
- {
- }
-}
-
-//*****************************************************************************
-//
-//! Reads from a PHY register.
-//!
-//! \param ulBase is the base address of the controller.
-//! \param ucRegAddr is the address of the PHY register to be accessed.
-//!
-//! This function will return the contents of the PHY register specified by
-//! \e ucRegAddr.
-//!
-//! \return Returns the 16-bit value read from the PHY.
-//
-//*****************************************************************************
-unsigned long
-EthernetPHYRead(unsigned long ulBase, unsigned char ucRegAddr)
-{
- //
- // Check the arguments.
- //
- ASSERT(ulBase == ETH_BASE);
-
- //
- // Wait for any pending transaction to complete.
- //
- while(HWREG(ulBase + MAC_O_MCTL) & MAC_MCTL_START)
- {
- }
-
- //
- // Program the PHY register address and initiate the transaction.
- //
- HWREG(ulBase + MAC_O_MCTL) = (((ucRegAddr << 3) & MAC_MCTL_REGADR_M) |
- MAC_MCTL_START);
-
- //
- // Wait for the transaction to complete.
- //
- while(HWREG(ulBase + MAC_O_MCTL) & MAC_MCTL_START)
- {
- }
-
- //
- // Return the PHY data that was read.
- //
- return(HWREG(ulBase + MAC_O_MRXD) & MAC_MRXD_MDRX_M);
-}
-
-//*****************************************************************************
-//
-// Close the Doxygen group.
-//! @}
-//
-//*****************************************************************************
+//*****************************************************************************
+//
+// ethernet.c - Driver for the Integrated Ethernet Controller
+//
+// Copyright (c) 2006-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup ethernet_api
+//! @{
+//
+//*****************************************************************************
+
+#include "hw_ethernet.h"
+#include "hw_ints.h"
+#include "hw_memmap.h"
+#include "hw_types.h"
+#include "debug.h"
+#include "ethernet.h"
+#include "interrupt.h"
+
+//*****************************************************************************
+//
+//! Initializes the Ethernet controller for operation.
+//!
+//! \param ulBase is the base address of the controller.
+//! \param ulEthClk is the rate of the clock supplied to the Ethernet module.
+//!
+//! This function will prepare the Ethernet controller for first time use in
+//! a given hardware/software configuration. This function should be called
+//! before any other Ethernet API functions are called.
+//!
+//! The peripheral clock will be the same as the processor clock. This will be
+//! the value returned by SysCtlClockGet(), or it can be explicitly hard-coded
+//! if it is constant and known (to save the code/execution overhead of a call
+//! to SysCtlClockGet()).
+//!
+//! This function replaces the original EthernetInit() API and performs the
+//! same actions. A macro is provided in <tt>ethernet.h</tt> to map the
+//! original API to this API.
+//!
+//! \note If the device configuration is changed (for example, the system clock
+//! is reprogrammed to a different speed), then the Ethernet controller must be
+//! disabled by calling the EthernetDisable() function and the controller must
+//! be reinitialized by calling the EthernetInitExpClk() function again. After
+//! the controller has been reinitialized, the controller should be
+//! reconfigured using the appropriate Ethernet API calls.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EthernetInitExpClk(unsigned long ulBase, unsigned long ulEthClk)
+{
+ unsigned long ulDiv;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == ETH_BASE);
+
+ //
+ // Set the Management Clock Divider register for access to the PHY
+ // register set (via EthernetPHYRead/Write).
+ //
+ // The MDC clock divided down from the system clock using the following
+ // formula. A maximum of 2.5MHz is allowed for F(mdc).
+ //
+ // F(mdc) = F(sys) / (2 * (div + 1))
+ // div = (F(sys) / (2 * F(mdc))) - 1
+ // div = (F(sys) / 2 / F(mdc)) - 1
+ //
+ // Note: Because we should round up, to ensure we don't violate the
+ // maximum clock speed, we can simplify this as follows:
+ //
+ // div = F(sys) / 2 / F(mdc)
+ //
+ // For example, given a system clock of 6.0MHz, and a div value of 1,
+ // the mdc clock would be programmed as 1.5 MHz.
+ //
+ ulDiv = (ulEthClk / 2) / 2500000;
+ HWREG(ulBase + MAC_O_MDV) = (ulDiv & MAC_MDV_DIV_M);
+}
+
+//*****************************************************************************
+//
+//! Sets the configuration of the Ethernet controller.
+//!
+//! \param ulBase is the base address of the controller.
+//! \param ulConfig is the configuration for the controller.
+//!
+//! After the EthernetInitExpClk() function has been called, this API function
+//! can be used to configure the various features of the Ethernet controller.
+//!
+//! The Ethernet controller provides three control registers that are used
+//! to configure the controller's operation. The transmit control register
+//! provides settings to enable full duplex operation, to auto-generate the
+//! frame check sequence, and to pad the transmit packets to the minimum
+//! length as required by the IEEE standard. The receive control register
+//! provides settings to enable reception of packets with bad frame check
+//! sequence values and to enable multi-cast or promiscuous modes. The
+//! timestamp control register provides settings that enable support logic in
+//! the controller that allow the use of the General Purpose Timer 3 to capture
+//! timestamps for the transmitted and received packets.
+//!
+//! The \e ulConfig parameter is the logical OR of the following values:
+//!
+//! - \b ETH_CFG_TS_TSEN - Enable TX and RX interrupt status as CCP timer
+//! inputs
+//! - \b ETH_CFG_RX_BADCRCDIS - Disable reception of packets with a bad CRC
+//! - \b ETH_CFG_RX_PRMSEN - Enable promiscuous mode reception (all packets)
+//! - \b ETH_CFG_RX_AMULEN - Enable reception of multicast packets
+//! - \b ETH_CFG_TX_DPLXEN - Enable full duplex transmit mode
+//! - \b ETH_CFG_TX_CRCEN - Enable transmit with auto CRC generation
+//! - \b ETH_CFG_TX_PADEN - Enable padding of transmit data to minimum size
+//!
+//! These bit-mapped values are programmed into the transmit, receive, and/or
+//! timestamp control register.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EthernetConfigSet(unsigned long ulBase, unsigned long ulConfig)
+{
+ unsigned long ulTemp;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == ETH_BASE);
+ ASSERT((ulConfig & ~(ETH_CFG_TX_DPLXEN | ETH_CFG_TX_CRCEN |
+ ETH_CFG_TX_PADEN | ETH_CFG_RX_BADCRCDIS |
+ ETH_CFG_RX_PRMSEN | ETH_CFG_RX_AMULEN |
+ ETH_CFG_TS_TSEN)) == 0);
+
+ //
+ // Setup the Transmit Control Register.
+ //
+ ulTemp = HWREG(ulBase + MAC_O_TCTL);
+ ulTemp &= ~(MAC_TCTL_DUPLEX | MAC_TCTL_CRC | MAC_TCTL_PADEN);
+ ulTemp |= ulConfig & 0x0FF;
+ HWREG(ulBase + MAC_O_TCTL) = ulTemp;
+
+ //
+ // Setup the Receive Control Register.
+ //
+ ulTemp = HWREG(ulBase + MAC_O_RCTL);
+ ulTemp &= ~(MAC_RCTL_BADCRC | MAC_RCTL_PRMS | MAC_RCTL_AMUL);
+ ulTemp |= (ulConfig >> 8) & 0x0FF;
+ HWREG(ulBase + MAC_O_RCTL) = ulTemp;
+
+ //
+ // Setup the Time Stamp Configuration register.
+ //
+ ulTemp = HWREG(ulBase + MAC_O_TS);
+ ulTemp &= ~(MAC_TS_TSEN);
+ ulTemp |= (ulConfig >> 16) & 0x0FF;
+ HWREG(ulBase + MAC_O_TS) = ulTemp;
+}
+
+//*****************************************************************************
+//
+//! Gets the current configuration of the Ethernet controller.
+//!
+//! \param ulBase is the base address of the controller.
+//!
+//! This function will query the control registers of the Ethernet controller
+//! and return a bit-mapped configuration value.
+//!
+//! \sa The description of the EthernetConfigSet() function provides detailed
+//! information for the bit-mapped configuration values that will be returned.
+//!
+//! \return Returns the bit-mapped Ethernet controller configuration value.
+//
+//*****************************************************************************
+unsigned long
+EthernetConfigGet(unsigned long ulBase)
+{
+ unsigned long ulConfig;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == ETH_BASE);
+
+ //
+ // Read and return the Ethernet controller configuration parameters,
+ // properly shifted into the appropriate bit field positions.
+ //
+ ulConfig = HWREG(ulBase + MAC_O_TS) << 16;
+ ulConfig |= (HWREG(ulBase + MAC_O_RCTL) & ~(MAC_RCTL_RXEN)) << 8;
+ ulConfig |= HWREG(ulBase + MAC_O_TCTL) & ~(MAC_TCTL_TXEN);
+ return(ulConfig);
+}
+
+//*****************************************************************************
+//
+//! Sets the MAC address of the Ethernet controller.
+//!
+//! \param ulBase is the base address of the controller.
+//! \param pucMACAddr is the pointer to the array of MAC-48 address octets.
+//!
+//! This function will program the IEEE-defined MAC-48 address specified in
+//! \e pucMACAddr into the Ethernet controller. This address is used by the
+//! Ethernet controller for hardware-level filtering of incoming Ethernet
+//! packets (when promiscuous mode is not enabled).
+//!
+//! The MAC-48 address is defined as 6 octets, illustrated by the following
+//! example address. The numbers are shown in hexadecimal format.
+//!
+//! AC-DE-48-00-00-80
+//!
+//! In this representation, the first three octets (AC-DE-48) are the
+//! Organizationally Unique Identifier (OUI). This is a number assigned by
+//! the IEEE to an organization that requests a block of MAC addresses. The
+//! last three octets (00-00-80) are a 24-bit number managed by the OUI owner
+//! to uniquely identify a piece of hardware within that organization that is
+//! to be connected to the Ethernet.
+//!
+//! In this representation, the octets are transmitted from left to right,
+//! with the ``AC'' octet being transmitted first and the ``80'' octet being
+//! transmitted last. Within an octet, the bits are transmitted LSB to MSB.
+//! For this address, the first bit to be transmitted would be ``0'', the LSB
+//! of ``AC'', and the last bit to be transmitted would be ``1'', the MSB of
+//! ``80''.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EthernetMACAddrSet(unsigned long ulBase, unsigned char *pucMACAddr)
+{
+ unsigned long ulTemp;
+ unsigned char *pucTemp = (unsigned char *)&ulTemp;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == ETH_BASE);
+ ASSERT(pucMACAddr != 0);
+
+ //
+ // Program the MAC Address into the device. The first four bytes of the
+ // MAC Address are placed into the IA0 register. The remaining two bytes
+ // of the MAC address are placed into the IA1 register.
+ //
+ pucTemp[0] = pucMACAddr[0];
+ pucTemp[1] = pucMACAddr[1];
+ pucTemp[2] = pucMACAddr[2];
+ pucTemp[3] = pucMACAddr[3];
+ HWREG(ulBase + MAC_O_IA0) = ulTemp;
+ ulTemp = 0;
+ pucTemp[0] = pucMACAddr[4];
+ pucTemp[1] = pucMACAddr[5];
+ HWREG(ulBase + MAC_O_IA1) = ulTemp;
+}
+
+//*****************************************************************************
+//
+//! Gets the MAC address of the Ethernet controller.
+//!
+//! \param ulBase is the base address of the controller.
+//! \param pucMACAddr is the pointer to the location in which to store the
+//! array of MAC-48 address octets.
+//!
+//! This function will read the currently programmed MAC address into the
+//! \e pucMACAddr buffer.
+//!
+//! \sa Refer to EthernetMACAddrSet() API description for more details about
+//! the MAC address format.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EthernetMACAddrGet(unsigned long ulBase, unsigned char *pucMACAddr)
+{
+ unsigned long ulTemp;
+ unsigned char *pucTemp = (unsigned char *)&ulTemp;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == ETH_BASE);
+ ASSERT(pucMACAddr != 0);
+
+ //
+ // Read the MAC address from the device. The first four bytes of the
+ // MAC address are read from the IA0 register. The remaining two bytes
+ // of the MAC addres
+ //
+ ulTemp = HWREG(ulBase + MAC_O_IA0);
+ pucMACAddr[0] = pucTemp[0];
+ pucMACAddr[1] = pucTemp[1];
+ pucMACAddr[2] = pucTemp[2];
+ pucMACAddr[3] = pucTemp[3];
+ ulTemp = HWREG(ulBase + MAC_O_IA1);
+ pucMACAddr[4] = pucTemp[0];
+ pucMACAddr[5] = pucTemp[1];
+}
+
+//*****************************************************************************
+//
+//! Enables the Ethernet controller for normal operation.
+//!
+//! \param ulBase is the base address of the controller.
+//!
+//! Once the Ethernet controller has been configured using the
+//! EthernetConfigSet() function and the MAC address has been programmed using
+//! the EthernetMACAddrSet() function, this API function can be called to
+//! enable the controller for normal operation.
+//!
+//! This function will enable the controller's transmitter and receiver, and
+//! will reset the receive FIFO.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EthernetEnable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == ETH_BASE);
+
+ //
+ // Reset the receive FIFO.
+ //
+ HWREG(ulBase + MAC_O_RCTL) |= MAC_RCTL_RSTFIFO;
+
+ //
+ // Enable the Ethernet receiver.
+ //
+ HWREG(ulBase + MAC_O_RCTL) |= MAC_RCTL_RXEN;
+
+ //
+ // Enable Ethernet transmitter.
+ //
+ HWREG(ulBase + MAC_O_TCTL) |= MAC_TCTL_TXEN;
+
+ //
+ // Reset the receive FIFO again, after the receiver has been enabled.
+ //
+ HWREG(ulBase + MAC_O_RCTL) |= MAC_RCTL_RSTFIFO;
+}
+
+//*****************************************************************************
+//
+//! Disables the Ethernet controller.
+//!
+//! \param ulBase is the base address of the controller.
+//!
+//! When terminating operations on the Ethernet interface, this function should
+//! be called. This function will disable the transmitter and receiver, and
+//! will clear out the receive FIFO.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EthernetDisable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == ETH_BASE);
+
+ //
+ // Reset the receive FIFO.
+ //
+ HWREG(ulBase + MAC_O_RCTL) |= MAC_RCTL_RSTFIFO;
+
+ //
+ // Disable the Ethernet transmitter.
+ //
+ HWREG(ulBase + MAC_O_TCTL) &= ~(MAC_TCTL_TXEN);
+
+ //
+ // Disable the Ethernet receiver.
+ //
+ HWREG(ulBase + MAC_O_RCTL) &= ~(MAC_RCTL_RXEN);
+
+ //
+ // Reset the receive FIFO again, after the receiver has been disabled.
+ //
+ HWREG(ulBase + MAC_O_RCTL) |= MAC_RCTL_RSTFIFO;
+}
+
+//*****************************************************************************
+//
+//! Check for packet available from the Ethernet controller.
+//!
+//! \param ulBase is the base address of the controller.
+//!
+//! The Ethernet controller provides a register that contains the number of
+//! packets available in the receive FIFO. When the last bytes of a packet are
+//! successfully received (that is, the frame check sequence bytes), the packet
+//! count is incremented. Once the packet has been fully read (including the
+//! frame check sequence bytes) from the FIFO, the packet count will be
+//! decremented.
+//!
+//! \return Returns \b true if there are one or more packets available in the
+//! receive FIFO, including the current packet being read, and \b false
+//! otherwise.
+//
+//*****************************************************************************
+tBoolean
+EthernetPacketAvail(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == ETH_BASE);
+
+ //
+ // Return the availability of packets.
+ //
+ return((HWREG(ulBase + MAC_O_NP) & MAC_NP_NPR_M) ? true : false);
+}
+
+//*****************************************************************************
+//
+//! Checks for packet space available in the Ethernet controller.
+//!
+//! \param ulBase is the base address of the controller.
+//!
+//! The Ethernet controller's transmit FIFO is designed to support a single
+//! packet at a time. After the packet has been written into the FIFO, the
+//! transmit request bit must be set to enable the transmission of the packet.
+//! Only after the packet has been transmitted can a new packet be written
+//! into the FIFO. This function will simply check to see if a packet is
+//! in progress. If so, there is no space available in the transmit FIFO.
+//!
+//! \return Returns \b true if a space is available in the transmit FIFO, and
+//! \b false otherwise.
+//
+//*****************************************************************************
+tBoolean
+EthernetSpaceAvail(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == ETH_BASE);
+
+ //
+ // Return the availability of space.
+ //
+ return((HWREG(ulBase + MAC_O_TR) & MAC_TR_NEWTX) ? false : true);
+}
+
+//*****************************************************************************
+//
+//! \internal
+//!
+//! Internal function for reading a packet from the Ethernet controller.
+//!
+//! \param ulBase is the base address of the controller.
+//! \param pucBuf is the pointer to the packet buffer.
+//! \param lBufLen is the maximum number of bytes to be read into the buffer.
+//!
+//! Based on the following table of how the receive frame is stored in the
+//! receive FIFO, this function will extract a packet from the FIFO and store
+//! it in the packet buffer that was passed in.
+//!
+//! Format of the data in the RX FIFO is as follows:
+//!
+//! \verbatim
+//! +---------+----------+----------+----------+----------+
+//! | | 31:24 | 23:16 | 15:8 | 7:0 |
+//! +---------+----------+----------+----------+----------+
+//! | Word 0 | DA 2 | DA 1 | FL MSB | FL LSB |
+//! +---------+----------+----------+----------+----------+
+//! | Word 1 | DA 6 | DA 5 | DA 4 | DA 3 |
+//! +---------+----------+----------+----------+----------+
+//! | Word 2 | SA 4 | SA 3 | SA 2 | SA 1 |
+//! +---------+----------+----------+----------+----------+
+//! | Word 3 | FT LSB | FT MSB | SA 6 | SA 5 |
+//! +---------+----------+----------+----------+----------+
+//! | Word 4 | DATA 4 | DATA 3 | DATA 2 | DATA 1 |
+//! +---------+----------+----------+----------+----------+
+//! | Word 5 | DATA 8 | DATA 7 | DATA 6 | DATA 5 |
+//! +---------+----------+----------+----------+----------+
+//! | Word 6 | DATA 12 | DATA 11 | DATA 10 | DATA 9 |
+//! +---------+----------+----------+----------+----------+
+//! | ... | | | | |
+//! +---------+----------+----------+----------+----------+
+//! | Word X | DATA n | DATA n-1 | DATA n-2 | DATA n-3 |
+//! +---------+----------+----------+----------+----------+
+//! | Word Y | FCS 4 | FCS 3 | FCS 2 | FCS 1 |
+//! +---------+----------+----------+----------+----------+
+//! \endverbatim
+//!
+//! Where FL is Frame Length, (FL + DA + SA + FT + DATA + FCS) Bytes.
+//! Where DA is Destination (MAC) Address.
+//! Where SA is Source (MAC) Address.
+//! Where FT is Frame Type (or Frame Length for Ethernet).
+//! Where DATA is Payload Data for the Ethernet Frame.
+//! Where FCS is the Frame Check Sequence.
+//!
+//! \return Returns the negated packet length \b -n if the packet is too large
+//! for \e pucBuf, and returns the packet length \b n otherwise.
+//
+//*****************************************************************************
+static long
+EthernetPacketGetInternal(unsigned long ulBase, unsigned char *pucBuf,
+ long lBufLen)
+{
+ unsigned long ulTemp;
+ long lFrameLen, lTempLen;
+ long i = 0;
+
+ //
+ // Read WORD 0 (see format above) from the FIFO, set the receive
+ // Frame Length and store the first two bytes of the destination
+ // address in the receive buffer.
+ //
+ ulTemp = HWREG(ulBase + MAC_O_DATA);
+ lFrameLen = (long)(ulTemp & 0xFFFF);
+ pucBuf[i++] = (unsigned char) ((ulTemp >> 16) & 0xff);
+ pucBuf[i++] = (unsigned char) ((ulTemp >> 24) & 0xff);
+
+ //
+ // Read all but the last WORD into the receive buffer.
+ //
+ lTempLen = (lBufLen < (lFrameLen - 6)) ? lBufLen : (lFrameLen - 6);
+ while(i <= (lTempLen - 4))
+ {
+ *(unsigned long *)&pucBuf[i] = HWREG(ulBase + MAC_O_DATA);
+ i += 4;
+ }
+
+ //
+ // Read the last 1, 2, or 3 BYTES into the buffer
+ //
+ if(i < lTempLen)
+ {
+ ulTemp = HWREG(ulBase + MAC_O_DATA);
+ if(i == lTempLen - 3)
+ {
+ pucBuf[i++] = ((ulTemp >> 0) & 0xff);
+ pucBuf[i++] = ((ulTemp >> 8) & 0xff);
+ pucBuf[i++] = ((ulTemp >> 16) & 0xff);
+ i += 1;
+ }
+ else if(i == lTempLen - 2)
+ {
+ pucBuf[i++] = ((ulTemp >> 0) & 0xff);
+ pucBuf[i++] = ((ulTemp >> 8) & 0xff);
+ i += 2;
+ }
+ else if(i == lTempLen - 1)
+ {
+ pucBuf[i++] = ((ulTemp >> 0) & 0xff);
+ i += 3;
+ }
+ }
+
+ //
+ // Read any remaining WORDS (that did not fit into the buffer).
+ //
+ while(i < (lFrameLen - 2))
+ {
+ ulTemp = HWREG(ulBase + MAC_O_DATA);
+ i += 4;
+ }
+
+ //
+ // If frame was larger than the buffer, return the "negative" frame length
+ //
+ lFrameLen -= 6;
+ if(lFrameLen > lBufLen)
+ {
+ return(-lFrameLen);
+ }
+
+ //
+ // Return the Frame Length
+ //
+ return(lFrameLen);
+}
+
+//*****************************************************************************
+//
+//! Receives a packet from the Ethernet controller.
+//!
+//! \param ulBase is the base address of the controller.
+//! \param pucBuf is the pointer to the packet buffer.
+//! \param lBufLen is the maximum number of bytes to be read into the buffer.
+//!
+//! This function reads a packet from the receive FIFO of the controller and
+//! places it into \e pucBuf. If no packet is available the function will
+//! return immediately. Otherwise, the function will read the entire packet
+//! from the receive FIFO. If there are more bytes in the packet than will fit
+//! into \e pucBuf (as specified by \e lBufLen), the function will return the
+//! negated length of the packet and the buffer will contain \e lBufLen bytes
+//! of the packet. Otherwise, the function will return the length of the
+//! packet that was read and \e pucBuf will contain the entire packet
+//! (excluding the frame check sequence bytes).
+//!
+//! This function replaces the original EthernetPacketNonBlockingGet() API and
+//! performs the same actions. A macro is provided in <tt>ethernet.h</tt> to
+//! map the original API to this API.
+//!
+//! \note This function will return immediately if no packet is available.
+//!
+//! \return Returns \b 0 if no packet is available, the negated packet length
+//! \b -n if the packet is too large for \e pucBuf, and the packet length \b n
+//! otherwise.
+//
+//*****************************************************************************
+long
+EthernetPacketGetNonBlocking(unsigned long ulBase, unsigned char *pucBuf,
+ long lBufLen)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == ETH_BASE);
+ ASSERT(pucBuf != 0);
+ ASSERT(lBufLen > 0);
+
+ //
+ // Check to see if any packets are available.
+ //
+ if((HWREG(ulBase + MAC_O_NP) & MAC_NP_NPR_M) == 0)
+ {
+ return(0);
+ }
+
+ //
+ // Read the packet, and return.
+ //
+ return(EthernetPacketGetInternal(ulBase, pucBuf, lBufLen));
+}
+
+//*****************************************************************************
+//
+//! Waits for a packet from the Ethernet controller.
+//!
+//! \param ulBase is the base address of the controller.
+//! \param pucBuf is the pointer to the packet buffer.
+//! \param lBufLen is the maximum number of bytes to be read into the buffer.
+//!
+//! This function reads a packet from the receive FIFO of the controller and
+//! places it into \e pucBuf. The function will wait until a packet is
+//! available in the FIFO. Then the function will read the entire packet
+//! from the receive FIFO. If there are more bytes in the packet than will
+//! fit into \e pucBuf (as specified by \e lBufLen), the function will return
+//! the negated length of the packet and the buffer will contain \e lBufLen
+//! bytes of the packet. Otherwise, the function will return the length of
+//! the packet that was read and \e pucBuf will contain the entire packet
+//! (excluding the frame check sequence bytes).
+//!
+//! \note This function is blocking and will not return until a packet arrives.
+//!
+//! \return Returns the negated packet length \b -n if the packet is too large
+//! for \e pucBuf, and returns the packet length \b n otherwise.
+//
+//*****************************************************************************
+long
+EthernetPacketGet(unsigned long ulBase, unsigned char *pucBuf,
+ long lBufLen)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == ETH_BASE);
+ ASSERT(pucBuf != 0);
+ ASSERT(lBufLen > 0);
+
+ //
+ // Wait for a packet to become available
+ //
+ while((HWREG(ulBase + MAC_O_NP) & MAC_NP_NPR_M) == 0)
+ {
+ }
+
+ //
+ // Read the packet
+ //
+ return(EthernetPacketGetInternal(ulBase, pucBuf, lBufLen));
+}
+
+//*****************************************************************************
+//
+//! \internal
+//!
+//! Internal function for sending a packet to the Ethernet controller.
+//!
+//! \param ulBase is the base address of the controller.
+//! \param pucBuf is the pointer to the packet buffer.
+//! \param lBufLen is number of bytes in the packet to be transmitted.
+//!
+//! Puts a packet into the transmit FIFO of the controller.
+//!
+//! Format of the data in the TX FIFO is as follows:
+//!
+//! \verbatim
+//! +---------+----------+----------+----------+----------+
+//! | | 31:24 | 23:16 | 15:8 | 7:0 |
+//! +---------+----------+----------+----------+----------+
+//! | Word 0 | DA 2 | DA 1 | PL MSB | PL LSB |
+//! +---------+----------+----------+----------+----------+
+//! | Word 1 | DA 6 | DA 5 | DA 4 | DA 3 |
+//! +---------+----------+----------+----------+----------+
+//! | Word 2 | SA 4 | SA 3 | SA 2 | SA 1 |
+//! +---------+----------+----------+----------+----------+
+//! | Word 3 | FT LSB | FT MSB | SA 6 | SA 5 |
+//! +---------+----------+----------+----------+----------+
+//! | Word 4 | DATA 4 | DATA 3 | DATA 2 | DATA 1 |
+//! +---------+----------+----------+----------+----------+
+//! | Word 5 | DATA 8 | DATA 7 | DATA 6 | DATA 5 |
+//! +---------+----------+----------+----------+----------+
+//! | Word 6 | DATA 12 | DATA 11 | DATA 10 | DATA 9 |
+//! +---------+----------+----------+----------+----------+
+//! | ... | | | | |
+//! +---------+----------+----------+----------+----------+
+//! | Word X | DATA n | DATA n-1 | DATA n-2 | DATA n-3 |
+//! +---------+----------+----------+----------+----------+
+//! \endverbatim
+//!
+//! Where PL is Payload Length, (DATA) only
+//! Where DA is Destination (MAC) Address
+//! Where SA is Source (MAC) Address
+//! Where FT is Frame Type (or Frame Length for Ethernet)
+//! Where DATA is Payload Data for the Ethernet Frame
+//!
+//! \return Returns the negated packet length \b -lBufLen if the packet is too
+//! large for FIFO, and the packet length \b lBufLen otherwise.
+//
+//*****************************************************************************
+static long
+EthernetPacketPutInternal(unsigned long ulBase, unsigned char *pucBuf,
+ long lBufLen)
+{
+ unsigned long ulTemp;
+ long i = 0;
+
+ //
+ // If the packet is too large, return the negative packet length as
+ // an error code.
+ //
+ if(lBufLen > (2048 - 2))
+ {
+ return(-lBufLen);
+ }
+
+ //
+ // Build and write WORD 0 (see format above) to the transmit FIFO.
+ //
+ ulTemp = (unsigned long)(lBufLen - 14);
+ ulTemp |= (pucBuf[i++] << 16);
+ ulTemp |= (pucBuf[i++] << 24);
+ HWREG(ulBase + MAC_O_DATA) = ulTemp;
+
+ //
+ // Write each subsequent WORD n to the transmit FIFO, except for the last
+ // WORD (if the word does not contain 4 bytes).
+ //
+ while(i <= (lBufLen - 4))
+ {
+ HWREG(ulBase + MAC_O_DATA) = *(unsigned long *)&pucBuf[i];
+ i += 4;
+ }
+
+ //
+ // Build the last word of the remaining 1, 2, or 3 bytes, and store
+ // the WORD into the transmit FIFO.
+ //
+ if(i != lBufLen)
+ {
+ if(i == (lBufLen - 3))
+ {
+ ulTemp = (pucBuf[i++] << 0);
+ ulTemp |= (pucBuf[i++] << 8);
+ ulTemp |= (pucBuf[i++] << 16);
+ HWREG(ulBase + MAC_O_DATA) = ulTemp;
+ }
+ else if(i == (lBufLen - 2))
+ {
+ ulTemp = (pucBuf[i++] << 0);
+ ulTemp |= (pucBuf[i++] << 8);
+ HWREG(ulBase + MAC_O_DATA) = ulTemp;
+ }
+ else if(i == (lBufLen - 1))
+ {
+ ulTemp = (pucBuf[i++] << 0);
+ HWREG(ulBase + MAC_O_DATA) = ulTemp;
+ }
+ }
+
+ //
+ // Activate the transmitter
+ //
+ HWREG(ulBase + MAC_O_TR) = MAC_TR_NEWTX;
+
+ //
+ // Return the Buffer Length transmitted.
+ //
+ return(lBufLen);
+}
+
+//*****************************************************************************
+//
+//! Sends a packet to the Ethernet controller.
+//!
+//! \param ulBase is the base address of the controller.
+//! \param pucBuf is the pointer to the packet buffer.
+//! \param lBufLen is number of bytes in the packet to be transmitted.
+//!
+//! This function writes \e lBufLen bytes of the packet contained in \e pucBuf
+//! into the transmit FIFO of the controller and then activates the
+//! transmitter for this packet. If no space is available in the FIFO, the
+//! function will return immediately. If space is available, the
+//! function will return once \e lBufLen bytes of the packet have been placed
+//! into the FIFO and the transmitter has been started. The function will not
+//! wait for the transmission to complete. The function will return the
+//! negated \e lBufLen if the length is larger than the space available in
+//! the transmit FIFO.
+//!
+//! This function replaces the original EthernetPacketNonBlockingPut() API and
+//! performs the same actions. A macro is provided in <tt>ethernet.h</tt> to
+//! map the original API to this API.
+//!
+//! \note This function does not block and will return immediately if no space
+//! is available for the transmit packet.
+//!
+//! \return Returns \b 0 if no space is available in the transmit FIFO, the
+//! negated packet length \b -lBufLen if the packet is too large for FIFO, and
+//! the packet length \b lBufLen otherwise.
+//
+//*****************************************************************************
+long
+EthernetPacketPutNonBlocking(unsigned long ulBase, unsigned char *pucBuf,
+ long lBufLen)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == ETH_BASE);
+ ASSERT(pucBuf != 0);
+ ASSERT(lBufLen > 0);
+
+ //
+ // Check if the transmit FIFO is in use and return the appropriate code.
+ //
+ if(HWREG(ulBase + MAC_O_TR) & MAC_TR_NEWTX)
+ {
+ return(0);
+ }
+
+ //
+ // Send the packet and return.
+ //
+ return(EthernetPacketPutInternal(ulBase, pucBuf, lBufLen));
+}
+
+//*****************************************************************************
+//
+//! Waits to send a packet from the Ethernet controller.
+//!
+//! \param ulBase is the base address of the controller.
+//! \param pucBuf is the pointer to the packet buffer.
+//! \param lBufLen is number of bytes in the packet to be transmitted.
+//!
+//! This function writes \e lBufLen bytes of the packet contained in \e pucBuf
+//! into the transmit FIFO of the controller and then activates the transmitter
+//! for this packet. This function will wait until the transmit FIFO is empty.
+//! Once space is available, the function will return once \e lBufLen bytes of
+//! the packet have been placed into the FIFO and the transmitter has been
+//! started. The function will not wait for the transmission to complete. The
+//! function will return the negated \e lBufLen if the length is larger than
+//! the space available in the transmit FIFO.
+//!
+//! \note This function blocks and will wait until space is available for the
+//! transmit packet before returning.
+//!
+//! \return Returns the negated packet length \b -lBufLen if the packet is too
+//! large for FIFO, and the packet length \b lBufLen otherwise.
+//
+//*****************************************************************************
+long
+EthernetPacketPut(unsigned long ulBase, unsigned char *pucBuf,
+ long lBufLen)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == ETH_BASE);
+ ASSERT(pucBuf != 0);
+ ASSERT(lBufLen > 0);
+
+ //
+ // Wait for current packet (if any) to complete.
+ //
+ while(HWREG(ulBase + MAC_O_TR) & MAC_TR_NEWTX)
+ {
+ }
+
+ //
+ // Send the packet and return.
+ //
+ return(EthernetPacketPutInternal(ulBase, pucBuf, lBufLen));
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for an Ethernet interrupt.
+//!
+//! \param ulBase is the base address of the controller.
+//! \param pfnHandler is a pointer to the function to be called when the
+//! enabled Ethernet interrupts occur.
+//!
+//! This function sets the handler to be called when the Ethernet interrupt
+//! occurs. This will enable the global interrupt in the interrupt controller;
+//! specific Ethernet interrupts must be enabled via EthernetIntEnable(). It
+//! is the interrupt handler's responsibility to clear the interrupt source.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EthernetIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == ETH_BASE);
+ ASSERT(pfnHandler != 0);
+
+ //
+ // Register the interrupt handler.
+ //
+ IntRegister(INT_ETH, pfnHandler);
+
+ //
+ // Enable the Ethernet interrupt.
+ //
+ IntEnable(INT_ETH);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for an Ethernet interrupt.
+//!
+//! \param ulBase is the base address of the controller.
+//!
+//! This function unregisters the interrupt handler. This will disable the
+//! global interrupt in the interrupt controller so that the interrupt handler
+//! no longer is called.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EthernetIntUnregister(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == ETH_BASE);
+
+ //
+ // Disable the interrupt.
+ //
+ IntDisable(INT_ETH);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(INT_ETH);
+}
+
+//*****************************************************************************
+//
+//! Enables individual Ethernet interrupt sources.
+//!
+//! \param ulBase is the base address of the controller.
+//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.
+//!
+//! Enables the indicated Ethernet interrupt sources. Only the sources that
+//! are enabled can be reflected to the processor interrupt; disabled sources
+//! have no effect on the processor.
+//!
+//! The \e ulIntFlags parameter is the logical OR of any of the following:
+//!
+//! - \b ETH_INT_PHY - An interrupt from the PHY has occurred. The integrated
+//! PHY supports a number of interrupt conditions. The PHY register, PHY_MR17,
+//! must be read to determine which PHY interrupt has occurred. This register
+//! can be read using the EthernetPHYRead() API function.
+//! - \b ETH_INT_MDIO - This interrupt indicates that a transaction on the
+//! management interface has completed successfully.
+//! - \b ETH_INT_RXER - This interrupt indicates that an error has occurred
+//! during reception of a frame. This error can indicate a length mismatch, a
+//! CRC failure, or an error indication from the PHY.
+//! - \b ETH_INT_RXOF - This interrupt indicates that a frame has been received
+//! that exceeds the available space in the RX FIFO.
+//! - \b ETH_INT_TX - This interrupt indicates that the packet stored in the TX
+//! FIFO has been successfully transmitted.
+//! - \b ETH_INT_TXER - This interrupt indicates that an error has occurred
+//! during the transmission of a packet. This error can be either a retry
+//! failure during the back-off process, or an invalid length stored in the TX
+//! FIFO.
+//! - \b ETH_INT_RX - This interrupt indicates that one (or more) packets are
+//! available in the RX FIFO for processing.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EthernetIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == ETH_BASE);
+ ASSERT(!(ulIntFlags & ~(ETH_INT_PHY | ETH_INT_MDIO | ETH_INT_RXER |
+ ETH_INT_RXOF | ETH_INT_TX | ETH_INT_TXER |
+ ETH_INT_RX)));
+
+ //
+ // Enable the specified interrupts.
+ //
+ HWREG(ulBase + MAC_O_IM) |= ulIntFlags;
+}
+
+//*****************************************************************************
+//
+//! Disables individual Ethernet interrupt sources.
+//!
+//! \param ulBase is the base address of the controller.
+//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled.
+//!
+//! Disables the indicated Ethernet interrupt sources. Only the sources that
+//! are enabled can be reflected to the processor interrupt; disabled sources
+//! have no effect on the processor.
+//!
+//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
+//! parameter to EthernetIntEnable().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EthernetIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == ETH_BASE);
+ ASSERT(!(ulIntFlags & ~(ETH_INT_PHY | ETH_INT_MDIO | ETH_INT_RXER |
+ ETH_INT_RXOF | ETH_INT_TX | ETH_INT_TXER |
+ ETH_INT_RX)));
+
+ //
+ // Disable the specified interrupts.
+ //
+ HWREG(ulBase + MAC_O_IM) &= ~ulIntFlags;
+}
+
+//*****************************************************************************
+//
+//! Gets the current Ethernet interrupt status.
+//!
+//! \param ulBase is the base address of the controller.
+//! \param bMasked is false if the raw interrupt status is required and true
+//! if the masked interrupt status is required.
+//!
+//! This returns the interrupt status for the Ethernet controller. Either the
+//! raw interrupt status or the status of interrupts that are allowed to
+//! reflect to the processor can be returned.
+//!
+//! \return Returns the current interrupt status, enumerated as a bit field of
+//! values described in EthernetIntEnable().
+//
+//*****************************************************************************
+unsigned long
+EthernetIntStatus(unsigned long ulBase, tBoolean bMasked)
+{
+ unsigned long ulStatus;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == ETH_BASE);
+
+ //
+ // Read the unmasked status.
+ //
+ ulStatus = HWREG(ulBase + MAC_O_RIS);
+
+ //
+ // If masked status is requested, mask it off.
+ //
+ if(bMasked)
+ {
+ ulStatus &= HWREG(ulBase + MAC_O_IM);
+ }
+
+ //
+ // Return the interrupt status value.
+ //
+ return(ulStatus);
+}
+
+//*****************************************************************************
+//
+//! Clears Ethernet interrupt sources.
+//!
+//! \param ulBase is the base address of the controller.
+//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
+//!
+//! The specified Ethernet interrupt sources are cleared so that they no longer
+//! assert. This must be done in the interrupt handler to keep it from being
+//! called again immediately upon exit.
+//!
+//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
+//! parameter to EthernetIntEnable().
+//!
+//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
+//! several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared. Failure to do so may result in the interrupt handler
+//! being immediately reentered (since NVIC still sees the interrupt source
+//! asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EthernetIntClear(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == ETH_BASE);
+ ASSERT(!(ulIntFlags & ~(ETH_INT_PHY | ETH_INT_MDIO | ETH_INT_RXER |
+ ETH_INT_RXOF | ETH_INT_TX | ETH_INT_TXER |
+ ETH_INT_RX)));
+
+ //
+ // Clear the requested interrupt sources.
+ //
+ HWREG(ulBase + MAC_O_IACK) = ulIntFlags;
+}
+
+//*****************************************************************************
+//
+//! Writes to the PHY register.
+//!
+//! \param ulBase is the base address of the controller.
+//! \param ucRegAddr is the address of the PHY register to be accessed.
+//! \param ulData is the data to be written to the PHY register.
+//!
+//! This function will write the \e ulData to the PHY register specified by
+//! \e ucRegAddr.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EthernetPHYWrite(unsigned long ulBase, unsigned char ucRegAddr,
+ unsigned long ulData)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == ETH_BASE);
+
+ //
+ // Wait for any pending transaction to complete.
+ //
+ while(HWREG(ulBase + MAC_O_MCTL) & MAC_MCTL_START)
+ {
+ }
+
+ //
+ // Program the DATA to be written.
+ //
+ HWREG(ulBase + MAC_O_MTXD) = ulData & MAC_MTXD_MDTX_M;
+
+ //
+ // Program the PHY register address and initiate the transaction.
+ //
+ HWREG(ulBase + MAC_O_MCTL) = (((ucRegAddr << 3) & MAC_MCTL_REGADR_M) |
+ MAC_MCTL_WRITE | MAC_MCTL_START);
+
+ //
+ // Wait for the write transaction to complete.
+ //
+ while(HWREG(ulBase + MAC_O_MCTL) & MAC_MCTL_START)
+ {
+ }
+}
+
+//*****************************************************************************
+//
+//! Reads from a PHY register.
+//!
+//! \param ulBase is the base address of the controller.
+//! \param ucRegAddr is the address of the PHY register to be accessed.
+//!
+//! This function will return the contents of the PHY register specified by
+//! \e ucRegAddr.
+//!
+//! \return Returns the 16-bit value read from the PHY.
+//
+//*****************************************************************************
+unsigned long
+EthernetPHYRead(unsigned long ulBase, unsigned char ucRegAddr)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == ETH_BASE);
+
+ //
+ // Wait for any pending transaction to complete.
+ //
+ while(HWREG(ulBase + MAC_O_MCTL) & MAC_MCTL_START)
+ {
+ }
+
+ //
+ // Program the PHY register address and initiate the transaction.
+ //
+ HWREG(ulBase + MAC_O_MCTL) = (((ucRegAddr << 3) & MAC_MCTL_REGADR_M) |
+ MAC_MCTL_START);
+
+ //
+ // Wait for the transaction to complete.
+ //
+ while(HWREG(ulBase + MAC_O_MCTL) & MAC_MCTL_START)
+ {
+ }
+
+ //
+ // Return the PHY data that was read.
+ //
+ return(HWREG(ulBase + MAC_O_MRXD) & MAC_MRXD_MDRX_M);
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
Property changes on: branches/eagle_mmc/src/platform/lm3s/ethernet.c
___________________________________________________________________
Name: svn:executable
+ *
Modified: branches/eagle_mmc/src/platform/lm3s/ethernet.h
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/ethernet.h 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lm3s/ethernet.h 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,172 +1,172 @@
-//*****************************************************************************
-//
-// ethernet.h - Defines and Macros for the ethernet module.
-//
-// Copyright (c) 2006-2008 Luminary Micro, Inc. All rights reserved.
-// Software License Agreement
-//
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
-//
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws. All rights are reserved. You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program. Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
-//
-// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-//
-// This is part of revision 3740 of the Stellaris Peripheral Driver Library.
-//
-//*****************************************************************************
-
-#ifndef __ETHERNET_H__
-#define __ETHERNET_H__
-
-//*****************************************************************************
-//
-// If building with a C++ compiler, make all of the definitions in this header
-// have a C binding.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-//*****************************************************************************
-//
-// Values that can be passed to EthernetConfigSet as the ulConfig value, and
-// returned from EthernetConfigGet.
-//
-//*****************************************************************************
-#define ETH_CFG_TS_TSEN 0x010000 // Enable Timestamp (CCP)
-#define ETH_CFG_RX_BADCRCDIS 0x000800 // Disable RX BAD CRC Packets
-#define ETH_CFG_RX_PRMSEN 0x000400 // Enable RX Promiscuous
-#define ETH_CFG_RX_AMULEN 0x000200 // Enable RX Multicast
-#define ETH_CFG_TX_DPLXEN 0x000010 // Enable TX Duplex Mode
-#define ETH_CFG_TX_CRCEN 0x000004 // Enable TX CRC Generation
-#define ETH_CFG_TX_PADEN 0x000002 // Enable TX Padding
-
-//*****************************************************************************
-//
-// Values that can be passed to EthernetIntEnable, EthernetIntDisable, and
-// EthernetIntClear as the ulIntFlags parameter, and returned from
-// EthernetIntStatus.
-//
-//*****************************************************************************
-#define ETH_INT_PHY 0x040 // PHY Event/Interrupt
-#define ETH_INT_MDIO 0x020 // Management Transaction
-#define ETH_INT_RXER 0x010 // RX Error
-#define ETH_INT_RXOF 0x008 // RX FIFO Overrun
-#define ETH_INT_TX 0x004 // TX Complete
-#define ETH_INT_TXER 0x002 // TX Error
-#define ETH_INT_RX 0x001 // RX Complete
-
-//*****************************************************************************
-//
-// Helper Macros for Ethernet Processing
-//
-//*****************************************************************************
-//
-// htonl/ntohl - big endian/little endian byte swapping macros for
-// 32-bit (long) values
-//
-//*****************************************************************************
-#ifndef htonl
- #define htonl(a) \
- ((((a) >> 24) & 0x000000ff) | \
- (((a) >> 8) & 0x0000ff00) | \
- (((a) << 8) & 0x00ff0000) | \
- (((a) << 24) & 0xff000000))
-#endif
-
-#ifndef ntohl
- #define ntohl(a) htonl((a))
-#endif
-
-//*****************************************************************************
-//
-// htons/ntohs - big endian/little endian byte swapping macros for
-// 16-bit (short) values
-//
-//*****************************************************************************
-#ifndef htons
- #define htons(a) \
- ((((a) >> 8) & 0x00ff) | \
- (((a) << 8) & 0xff00))
-#endif
-
-#ifndef ntohs
- #define ntohs(a) htons((a))
-#endif
-
-//*****************************************************************************
-//
-// API Function prototypes
-//
-//*****************************************************************************
-extern void EthernetInitExpClk(unsigned long ulBase, unsigned long ulEthClk);
-extern void EthernetConfigSet(unsigned long ulBase, unsigned long ulConfig);
-extern unsigned long EthernetConfigGet(unsigned long ulBase);
-extern void EthernetMACAddrSet(unsigned long ulBase,
- unsigned char *pucMACAddr);
-extern void EthernetMACAddrGet(unsigned long ulBase,
- unsigned char *pucMACAddr);
-extern void EthernetEnable(unsigned long ulBase);
-extern void EthernetDisable(unsigned long ulBase);
-extern tBoolean EthernetPacketAvail(unsigned long ulBase);
-extern tBoolean EthernetSpaceAvail(unsigned long ulBase);
-extern long EthernetPacketGetNonBlocking(unsigned long ulBase,
- unsigned char *pucBuf,
- long lBufLen);
-extern long EthernetPacketGet(unsigned long ulBase, unsigned char *pucBuf,
- long lBufLen);
-extern long EthernetPacketPutNonBlocking(unsigned long ulBase,
- unsigned char *pucBuf,
- long lBufLen);
-extern long EthernetPacketPut(unsigned long ulBase, unsigned char *pucBuf,
- long lBufLen);
-extern void EthernetIntRegister(unsigned long ulBase,
- void (*pfnHandler)(void));
-extern void EthernetIntUnregister(unsigned long ulBase);
-extern void EthernetIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
-extern void EthernetIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
-extern unsigned long EthernetIntStatus(unsigned long ulBase, tBoolean bMasked);
-extern void EthernetIntClear(unsigned long ulBase, unsigned long ulIntFlags);
-extern void EthernetPHYWrite(unsigned long ulBase, unsigned char ucRegAddr,
- unsigned long ulData);
-extern unsigned long EthernetPHYRead(unsigned long ulBase,
- unsigned char ucRegAddr);
-
-//*****************************************************************************
-//
-// Several Ethernet APIs have been renamed, with the original function name
-// being deprecated. These defines provide backward compatibility.
-//
-//*****************************************************************************
-#ifndef DEPRECATED
-#include "sysctl.h"
-#define EthernetInit(a) \
- EthernetInitExpClk(a, SysCtlClockGet())
-#define EthernetPacketNonBlockingGet(a, b, c) \
- EthernetPacketGetNonBlocking(a, b, c)
-#define EthernetPacketNonBlockingPut(a, b, c) \
- EthernetPacketPutNonBlocking(a, b, c)
-#endif
-
-//*****************************************************************************
-//
-// Mark the end of the C bindings section for C++ compilers.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-}
-#endif
-
-#endif // __ETHERNET_H__
+//*****************************************************************************
+//
+// ethernet.h - Defines and Macros for the ethernet module.
+//
+// Copyright (c) 2006-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __ETHERNET_H__
+#define __ETHERNET_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to EthernetConfigSet as the ulConfig value, and
+// returned from EthernetConfigGet.
+//
+//*****************************************************************************
+#define ETH_CFG_TS_TSEN 0x010000 // Enable Timestamp (CCP)
+#define ETH_CFG_RX_BADCRCDIS 0x000800 // Disable RX BAD CRC Packets
+#define ETH_CFG_RX_PRMSEN 0x000400 // Enable RX Promiscuous
+#define ETH_CFG_RX_AMULEN 0x000200 // Enable RX Multicast
+#define ETH_CFG_TX_DPLXEN 0x000010 // Enable TX Duplex Mode
+#define ETH_CFG_TX_CRCEN 0x000004 // Enable TX CRC Generation
+#define ETH_CFG_TX_PADEN 0x000002 // Enable TX Padding
+
+//*****************************************************************************
+//
+// Values that can be passed to EthernetIntEnable, EthernetIntDisable, and
+// EthernetIntClear as the ulIntFlags parameter, and returned from
+// EthernetIntStatus.
+//
+//*****************************************************************************
+#define ETH_INT_PHY 0x040 // PHY Event/Interrupt
+#define ETH_INT_MDIO 0x020 // Management Transaction
+#define ETH_INT_RXER 0x010 // RX Error
+#define ETH_INT_RXOF 0x008 // RX FIFO Overrun
+#define ETH_INT_TX 0x004 // TX Complete
+#define ETH_INT_TXER 0x002 // TX Error
+#define ETH_INT_RX 0x001 // RX Complete
+
+//*****************************************************************************
+//
+// Helper Macros for Ethernet Processing
+//
+//*****************************************************************************
+//
+// htonl/ntohl - big endian/little endian byte swapping macros for
+// 32-bit (long) values
+//
+//*****************************************************************************
+#ifndef htonl
+ #define htonl(a) \
+ ((((a) >> 24) & 0x000000ff) | \
+ (((a) >> 8) & 0x0000ff00) | \
+ (((a) << 8) & 0x00ff0000) | \
+ (((a) << 24) & 0xff000000))
+#endif
+
+#ifndef ntohl
+ #define ntohl(a) htonl((a))
+#endif
+
+//*****************************************************************************
+//
+// htons/ntohs - big endian/little endian byte swapping macros for
+// 16-bit (short) values
+//
+//*****************************************************************************
+#ifndef htons
+ #define htons(a) \
+ ((((a) >> 8) & 0x00ff) | \
+ (((a) << 8) & 0xff00))
+#endif
+
+#ifndef ntohs
+ #define ntohs(a) htons((a))
+#endif
+
+//*****************************************************************************
+//
+// API Function prototypes
+//
+//*****************************************************************************
+extern void EthernetInitExpClk(unsigned long ulBase, unsigned long ulEthClk);
+extern void EthernetConfigSet(unsigned long ulBase, unsigned long ulConfig);
+extern unsigned long EthernetConfigGet(unsigned long ulBase);
+extern void EthernetMACAddrSet(unsigned long ulBase,
+ unsigned char *pucMACAddr);
+extern void EthernetMACAddrGet(unsigned long ulBase,
+ unsigned char *pucMACAddr);
+extern void EthernetEnable(unsigned long ulBase);
+extern void EthernetDisable(unsigned long ulBase);
+extern tBoolean EthernetPacketAvail(unsigned long ulBase);
+extern tBoolean EthernetSpaceAvail(unsigned long ulBase);
+extern long EthernetPacketGetNonBlocking(unsigned long ulBase,
+ unsigned char *pucBuf,
+ long lBufLen);
+extern long EthernetPacketGet(unsigned long ulBase, unsigned char *pucBuf,
+ long lBufLen);
+extern long EthernetPacketPutNonBlocking(unsigned long ulBase,
+ unsigned char *pucBuf,
+ long lBufLen);
+extern long EthernetPacketPut(unsigned long ulBase, unsigned char *pucBuf,
+ long lBufLen);
+extern void EthernetIntRegister(unsigned long ulBase,
+ void (*pfnHandler)(void));
+extern void EthernetIntUnregister(unsigned long ulBase);
+extern void EthernetIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
+extern void EthernetIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
+extern unsigned long EthernetIntStatus(unsigned long ulBase, tBoolean bMasked);
+extern void EthernetIntClear(unsigned long ulBase, unsigned long ulIntFlags);
+extern void EthernetPHYWrite(unsigned long ulBase, unsigned char ucRegAddr,
+ unsigned long ulData);
+extern unsigned long EthernetPHYRead(unsigned long ulBase,
+ unsigned char ucRegAddr);
+
+//*****************************************************************************
+//
+// Several Ethernet APIs have been renamed, with the original function name
+// being deprecated. These defines provide backward compatibility.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+#include "sysctl.h"
+#define EthernetInit(a) \
+ EthernetInitExpClk(a, SysCtlClockGet())
+#define EthernetPacketNonBlockingGet(a, b, c) \
+ EthernetPacketGetNonBlocking(a, b, c)
+#define EthernetPacketNonBlockingPut(a, b, c) \
+ EthernetPacketPutNonBlocking(a, b, c)
+#endif
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __ETHERNET_H__
Property changes on: branches/eagle_mmc/src/platform/lm3s/ethernet.h
___________________________________________________________________
Name: svn:executable
+ *
Modified: branches/eagle_mmc/src/platform/lm3s/flash.c
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/flash.c 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lm3s/flash.c 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,871 +1,915 @@
-//*****************************************************************************
-//
-// flash.c - Driver for programming the on-chip flash.
-//
-// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
-// Software License Agreement
-//
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
-//
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws. All rights are reserved. You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program. Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
-//
-// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-//
-// This is part of revision 3740 of the Stellaris Peripheral Driver Library.
-//
-//*****************************************************************************
-
-//*****************************************************************************
-//
-//! \addtogroup flash_api
-//! @{
-//
-//*****************************************************************************
-
-#include "hw_flash.h"
-#include "hw_ints.h"
-#include "hw_memmap.h"
-#include "hw_sysctl.h"
-#include "hw_types.h"
-#include "debug.h"
-#include "flash.h"
-#include "interrupt.h"
-
-//*****************************************************************************
-//
-// An array that maps the specified memory bank to the appropriate Flash
-// Memory Protection Program Enable (FMPPE) register.
-//
-//*****************************************************************************
-static const unsigned long g_pulFMPPERegs[] =
-{
- FLASH_FMPPE,
- FLASH_FMPPE1,
- FLASH_FMPPE2,
- FLASH_FMPPE3
-};
-
-//*****************************************************************************
-//
-// An array that maps the specified memory bank to the appropriate Flash
-// Memory Protection Read Enable (FMPRE) register.
-//
-//*****************************************************************************
-static const unsigned long g_pulFMPRERegs[] =
-{
- FLASH_FMPRE,
- FLASH_FMPRE1,
- FLASH_FMPRE2,
- FLASH_FMPRE3
-};
-
-//*****************************************************************************
-//
-//! Gets the number of processor clocks per micro-second.
-//!
-//! This function returns the number of clocks per micro-second, as presently
-//! known by the flash controller.
-//!
-//! \return Returns the number of processor clocks per micro-second.
-//
-//*****************************************************************************
-unsigned long
-FlashUsecGet(void)
-{
- //
- // Return the number of clocks per micro-second.
- //
- return(HWREG(FLASH_USECRL) + 1);
-}
-
-//*****************************************************************************
-//
-//! Sets the number of processor clocks per micro-second.
-//!
-//! \param ulClocks is the number of processor clocks per micro-second.
-//!
-//! This function is used to tell the flash controller the number of processor
-//! clocks per micro-second. This value must be programmed correctly or the
-//! flash most likely will not program correctly; it has no affect on reading
-//! flash.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-FlashUsecSet(unsigned long ulClocks)
-{
- //
- // Set the number of clocks per micro-second.
- //
- HWREG(FLASH_USECRL) = ulClocks - 1;
-}
-
-//*****************************************************************************
-//
-//! Erases a block of flash.
-//!
-//! \param ulAddress is the start address of the flash block to be erased.
-//!
-//! This function will erase a 1 kB block of the on-chip flash. After erasing,
-//! the block will be filled with 0xFF bytes. Read-only and execute-only
-//! blocks cannot be erased.
-//!
-//! This function will not return until the block has been erased.
-//!
-//! \return Returns 0 on success, or -1 if an invalid block address was
-//! specified or the block is write-protected.
-//
-//*****************************************************************************
-long
-FlashErase(unsigned long ulAddress)
-{
- //
- // Check the arguments.
- //
- ASSERT(!(ulAddress & (FLASH_ERASE_SIZE - 1)));
-
- //
- // Clear the flash access interrupt.
- //
- HWREG(FLASH_FCMISC) = FLASH_FCMISC_AMISC;
-
- //
- // Erase the block.
- //
- HWREG(FLASH_FMA) = ulAddress;
- HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_ERASE;
-
- //
- // Wait until the block has been erased.
- //
- while(HWREG(FLASH_FMC) & FLASH_FMC_ERASE)
- {
- }
-
- //
- // Return an error if an access violation occurred.
- //
- if(HWREG(FLASH_FCRIS) & FLASH_FCRIS_ARIS)
- {
- return(-1);
- }
-
- //
- // Success.
- //
- return(0);
-}
-
-//*****************************************************************************
-//
-//! Programs flash.
-//!
-//! \param pulData is a pointer to the data to be programmed.
-//! \param ulAddress is the starting address in flash to be programmed. Must
-//! be a multiple of four.
-//! \param ulCount is the number of bytes to be programmed. Must be a multiple
-//! of four.
-//!
-//! This function will program a sequence of words into the on-chip flash.
-//! Programming each location consists of the result of an AND operation
-//! of the new data and the existing data; in other words bits that contain
-//! 1 can remain 1 or be changed to 0, but bits that are 0 cannot be changed
-//! to 1. Therefore, a word can be programmed multiple times as long as these
-//! rules are followed; if a program operation attempts to change a 0 bit to
-//! a 1 bit, that bit will not have its value changed.
-//!
-//! Since the flash is programmed one word at a time, the starting address and
-//! byte count must both be multiples of four. It is up to the caller to
-//! verify the programmed contents, if such verification is required.
-//!
-//! This function will not return until the data has been programmed.
-//!
-//! \return Returns 0 on success, or -1 if a programming error is encountered.
-//
-//*****************************************************************************
-long
-FlashProgram(unsigned long *pulData, unsigned long ulAddress,
- unsigned long ulCount)
-{
- //
- // Check the arguments.
- //
- ASSERT(!(ulAddress & 3));
- ASSERT(!(ulCount & 3));
-
- //
- // Clear the flash access interrupt.
- //
- HWREG(FLASH_FCMISC) = FLASH_FCMISC_AMISC;
-
- //
- // Loop over the words to be programmed.
- //
- while(ulCount)
- {
- //
- // Program the next word.
- //
- HWREG(FLASH_FMA) = ulAddress;
- HWREG(FLASH_FMD) = *pulData;
- HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_WRITE;
-
- //
- // Wait until the word has been programmed.
- //
- while(HWREG(FLASH_FMC) & FLASH_FMC_WRITE)
- {
- }
-
- //
- // Increment to the next word.
- //
- pulData++;
- ulAddress += 4;
- ulCount -= 4;
- }
-
- //
- // Return an error if an access violation occurred.
- //
- if(HWREG(FLASH_FCRIS) & FLASH_FCRIS_ARIS)
- {
- return(-1);
- }
-
- //
- // Success.
- //
- return(0);
-}
-
-//*****************************************************************************
-//
-//! Gets the protection setting for a block of flash.
-//!
-//! \param ulAddress is the start address of the flash block to be queried.
-//!
-//! This function will get the current protection for the specified 2 kB block
-//! of flash. Each block can be read/write, read-only, or execute-only.
-//! Read/write blocks can be read, executed, erased, and programmed. Read-only
-//! blocks can be read and executed. Execute-only blocks can only be executed;
-//! processor and debugger data reads are not allowed.
-//!
-//! \return Returns the protection setting for this block. See
-//! FlashProtectSet() for possible values.
-//
-//*****************************************************************************
-tFlashProtection
-FlashProtectGet(unsigned long ulAddress)
-{
- unsigned long ulFMPRE, ulFMPPE;
- unsigned long ulBank;
-
- //
- // Check the argument.
- //
- ASSERT(!(ulAddress & (FLASH_PROTECT_SIZE - 1)));
-
- //
- // Calculate the Flash Bank from Base Address, and mask off the Bank
- // from ulAddress for subsequent reference.
- //
- ulBank = (((ulAddress / FLASH_PROTECT_SIZE) / 32) % 4);
- ulAddress &= ((FLASH_PROTECT_SIZE * 32) - 1);
-
- //
- // Read the appropriate flash protection registers for the specified
- // flash bank.
- //
- ulFMPRE = HWREG(g_pulFMPRERegs[ulBank]);
- ulFMPPE = HWREG(g_pulFMPPERegs[ulBank]);
-
- //
- // For Stellaris Sandstorm-class devices, revision C1 and C2, the upper
- // bits of the FMPPE register are used for JTAG protect options, and are
- // not available for the FLASH protection scheme. When Querying Block
- // Protection, assume these bits are 1.
- //
- if(CLASS_IS_SANDSTORM && (REVISION_IS_C1 || REVISION_IS_C2))
- {
- ulFMPRE |= (FLASH_FMP_BLOCK_31 | FLASH_FMP_BLOCK_30);
- }
-
- //
- // Check the appropriate protection bits for the block of memory that
- // is specified by the address.
- //
- switch((((ulFMPRE >> (ulAddress / FLASH_PROTECT_SIZE)) &
- FLASH_FMP_BLOCK_0) << 1) |
- ((ulFMPPE >> (ulAddress / FLASH_PROTECT_SIZE)) & FLASH_FMP_BLOCK_0))
- {
- //
- // This block is marked as execute only (that is, it can not be erased
- // or programmed, and the only reads allowed are via the instruction
- // fecth interface).
- //
- case 0:
- case 1:
- {
- return(FlashExecuteOnly);
- }
-
- //
- // This block is marked as read only (that is, it can not be erased or
- // programmed).
- //
- case 2:
- {
- return(FlashReadOnly);
- }
-
- //
- // This block is read/write; it can be read, erased, and programmed.
- //
- case 3:
- default:
- {
- return(FlashReadWrite);
- }
- }
-}
-
-//*****************************************************************************
-//
-//! Sets the protection setting for a block of flash.
-//!
-//! \param ulAddress is the start address of the flash block to be protected.
-//! \param eProtect is the protection to be applied to the block. Can be one
-//! of \b FlashReadWrite, \b FlashReadOnly, or \b FlashExecuteOnly.
-//!
-//! This function will set the protection for the specified 2 kB block of
-//! flash. Blocks which are read/write can be made read-only or execute-only.
-//! Blocks which are read-only can be made execute-only. Blocks which are
-//! execute-only cannot have their protection modified. Attempts to make the
-//! block protection less stringent (that is, read-only to read/write) will
-//! result in a failure (and be prevented by the hardware).
-//!
-//! Changes to the flash protection are maintained only until the next reset.
-//! This allows the application to be executed in the desired flash protection
-//! environment to check for inappropriate flash access (via the flash
-//! interrupt). To make the flash protection permanent, use the
-//! FlashProtectSave() function.
-//!
-//! \return Returns 0 on success, or -1 if an invalid address or an invalid
-//! protection was specified.
-//
-//*****************************************************************************
-long
-FlashProtectSet(unsigned long ulAddress, tFlashProtection eProtect)
-{
- unsigned long ulProtectRE, ulProtectPE;
- unsigned long ulBank;
-
- //
- // Check the argument.
- //
- ASSERT(!(ulAddress & (FLASH_PROTECT_SIZE - 1)));
- ASSERT((eProtect == FlashReadWrite) || (eProtect == FlashReadOnly) ||
- (eProtect == FlashExecuteOnly));
-
- //
- // Convert the address into a block number.
- //
- ulAddress /= FLASH_PROTECT_SIZE;
-
- //
- // ulAddress contains a "raw" block number. Derive the Flash Bank from
- // the "raw" block number, and convert ulAddress to a "relative"
- // block number.
- //
- ulBank = ((ulAddress / 32) % 4);
- ulAddress %= 32;
-
- //
- // Get the current protection for the specified flash bank.
- //
- ulProtectRE = HWREG(g_pulFMPRERegs[ulBank]);
- ulProtectPE = HWREG(g_pulFMPPERegs[ulBank]);
-
- //
- // For Stellaris Sandstorm-class devices, revision C1 and C2, the upper
- // bits of the FMPPE register are used for JTAG protect options, and are
- // not available for the FLASH protection scheme. When setting protection,
- // check to see if block 30 or 31 and protection is FlashExecuteOnly. If
- // so, return an error condition.
- //
- if(CLASS_IS_SANDSTORM && (REVISION_IS_C1 || REVISION_IS_C2))
- {
- if((ulAddress >= 30) && (eProtect == FlashExecuteOnly))
- {
- return(-1);
- }
- }
-
- //
- // Set the protection based on the requested proection.
- //
- switch(eProtect)
- {
- //
- // Make this block execute only.
- //
- case FlashExecuteOnly:
- {
- //
- // Turn off the read and program bits for this block.
- //
- ulProtectRE &= ~(FLASH_FMP_BLOCK_0 << ulAddress);
- ulProtectPE &= ~(FLASH_FMP_BLOCK_0 << ulAddress);
-
- //
- // We're done handling this protection.
- //
- break;
- }
-
- //
- // Make this block read only.
- //
- case FlashReadOnly:
- {
- //
- // The block can not be made read only if it is execute only.
- //
- if(((ulProtectRE >> ulAddress) & FLASH_FMP_BLOCK_0) !=
- FLASH_FMP_BLOCK_0)
- {
- return(-1);
- }
-
- //
- // Make this block read only.
- //
- ulProtectPE &= ~(FLASH_FMP_BLOCK_0 << ulAddress);
-
- //
- // We're done handling this protection.
- //
- break;
- }
-
- //
- // Make this block read/write.
- //
- case FlashReadWrite:
- default:
- {
- //
- // The block can not be made read/write if it is not already
- // read/write.
- //
- if((((ulProtectRE >> ulAddress) & FLASH_FMP_BLOCK_0) !=
- FLASH_FMP_BLOCK_0) ||
- (((ulProtectPE >> ulAddress) & FLASH_FMP_BLOCK_0) !=
- FLASH_FMP_BLOCK_0))
- {
- return(-1);
- }
-
- //
- // The block is already read/write, so there is nothing to do.
- //
- return(0);
- }
- }
-
- //
- // For Stellaris Sandstorm-class devices, revision C1 and C2, the upper
- // bits of the FMPPE register are used for JTAG options, and are not
- // available for the FLASH protection scheme. When setting block
- // protection, ensure that these bits are not altered.
- //
- if(CLASS_IS_SANDSTORM && (REVISION_IS_C1 || REVISION_IS_C2))
- {
- ulProtectRE &= ~(FLASH_FMP_BLOCK_31 | FLASH_FMP_BLOCK_30);
- ulProtectRE |= (HWREG(g_pulFMPRERegs[ulBank]) &
- (FLASH_FMP_BLOCK_31 | FLASH_FMP_BLOCK_30));
- }
-
- //
- // Set the new protection for the specified flash bank.
- //
- HWREG(g_pulFMPRERegs[ulBank]) = ulProtectRE;
- HWREG(g_pulFMPPERegs[ulBank]) = ulProtectPE;
-
- //
- // Success.
- //
- return(0);
-}
-
-//*****************************************************************************
-//
-//! Saves the flash protection settings.
-//!
-//! This function will make the currently programmed flash protection settings
-//! permanent. This is a non-reversible operation; a chip reset or power cycle
-//! will not change the flash protection.
-//!
-//! This function will not return until the protection has been saved.
-//!
-//! \return Returns 0 on success, or -1 if a hardware error is encountered.
-//
-//*****************************************************************************
-long
-FlashProtectSave(void)
-{
- int ulTemp, ulLimit;
-
- //
- // If running on a Sandstorm-class device, only trigger a save of the first
- // two protection registers (FMPRE and FMPPE). Otherwise, save the
- // entire bank of flash protection registers.
- //
- ulLimit = CLASS_IS_SANDSTORM ? 2 : 8;
- for(ulTemp = 0; ulTemp < ulLimit; ulTemp++)
- {
- //
- // Tell the flash controller to write the flash protection register.
- //
- HWREG(FLASH_FMA) = ulTemp;
- HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_COMT;
-
- //
- // Wait until the write has completed.
- //
- while(HWREG(FLASH_FMC) & FLASH_FMC_COMT)
- {
- }
- }
-
- //
- // Success.
- //
- return(0);
-}
-
-//*****************************************************************************
-//
-//! Gets the user registers.
-//!
-//! \param pulUser0 is a pointer to the location to store USER Register 0.
-//! \param pulUser1 is a pointer to the location to store USER Register 1.
-//!
-//! This function will read the contents of user registers (0 and 1), and
-//! store them in the specified locations.
-//!
-//! \return Returns 0 on success, or -1 if a hardware error is encountered.
-//
-//*****************************************************************************
-long
-FlashUserGet(unsigned long *pulUser0, unsigned long *pulUser1)
-{
- //
- // Verify that the pointers are valid.
- //
- ASSERT(pulUser0 != 0);
- ASSERT(pulUser1 != 0);
-
- //
- // Verify that hardware supports user registers.
- //
- if(CLASS_IS_SANDSTORM)
- {
- return(-1);
- }
-
- //
- // Get and store the current value of the user registers.
- //
- *pulUser0 = HWREG(FLASH_USERREG0);
- *pulUser1 = HWREG(FLASH_USERREG1);
-
- //
- // Success.
- //
- return(0);
-}
-
-//*****************************************************************************
-//
-//! Sets the user registers.
-//!
-//! \param ulUser0 is the value to store in USER Register 0.
-//! \param ulUser1 is the value to store in USER Register 1.
-//!
-//! This function will set the contents of the user registers (0 and 1) to
-//! the specified values.
-//!
-//! \return Returns 0 on success, or -1 if a hardware error is encountered.
-//
-//*****************************************************************************
-long
-FlashUserSet(unsigned long ulUser0, unsigned long ulUser1)
-{
- //
- // Verify that hardware supports user registers.
- //
- if(CLASS_IS_SANDSTORM)
- {
- return(-1);
- }
-
- //
- // Save the new values into the user registers.
- //
- HWREG(FLASH_USERREG0) = ulUser0;
- HWREG(FLASH_USERREG1) = ulUser1;
-
- //
- // Success.
- //
- return(0);
-}
-
-//*****************************************************************************
-//
-//! Saves the user registers.
-//!
-//! This function will make the currently programmed user register settings
-//! permanent. This is a non-reversible operation; a chip reset or power cycle
-//! will not change this setting.
-//!
-//! This function will not return until the protection has been saved.
-//!
-//! \return Returns 0 on success, or -1 if a hardware error is encountered.
-//
-//*****************************************************************************
-long
-FlashUserSave(void)
-{
- //
- // Verify that hardware supports user registers.
- //
- if(CLASS_IS_SANDSTORM)
- {
- return(-1);
- }
-
- //
- // Setting the MSB of FMA will trigger a permanent save of a USER
- // register. Bit 0 will indicate User 0 (0) or User 1 (1).
- //
- HWREG(FLASH_FMA) = 0x80000000;
- HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_COMT;
-
- //
- // Wait until the write has completed.
- //
- while(HWREG(FLASH_FMC) & FLASH_FMC_COMT)
- {
- }
-
- //
- // Tell the flash controller to write the USER1 Register.
- //
- HWREG(FLASH_FMA) = 0x80000001;
- HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_COMT;
-
- //
- // Wait until the write has completed.
- //
- while(HWREG(FLASH_FMC) & FLASH_FMC_COMT)
- {
- }
-
- //
- // Success.
- //
- return(0);
-}
-
-//*****************************************************************************
-//
-//! Registers an interrupt handler for the flash interrupt.
-//!
-//! \param pfnHandler is a pointer to the function to be called when the flash
-//! interrupt occurs.
-//!
-//! This sets the handler to be called when the flash interrupt occurs. The
-//! flash controller can generate an interrupt when an invalid flash access
-//! occurs, such as trying to program or erase a read-only block, or trying to
-//! read from an execute-only block. It can also generate an interrupt when a
-//! program or erase operation has completed. The interrupt will be
-//! automatically enabled when the handler is registered.
-//!
-//! \sa IntRegister() for important information about registering interrupt
-//! handlers.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-FlashIntRegister(void (*pfnHandler)(void))
-{
- //
- // Register the interrupt handler, returning an error if an error occurs.
- //
- IntRegister(INT_FLASH, pfnHandler);
-
- //
- // Enable the flash interrupt.
- //
- IntEnable(INT_FLASH);
-}
-
-//*****************************************************************************
-//
-//! Unregisters the interrupt handler for the flash interrupt.
-//!
-//! This function will clear the handler to be called when the flash interrupt
-//! occurs. This will also mask off the interrupt in the interrupt controller
-//! so that the interrupt handler is no longer called.
-//!
-//! \sa IntRegister() for important information about registering interrupt
-//! handlers.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-FlashIntUnregister(void)
-{
- //
- // Disable the interrupt.
- //
- IntDisable(INT_FLASH);
-
- //
- // Unregister the interrupt handler.
- //
- IntUnregister(INT_FLASH);
-}
-
-//*****************************************************************************
-//
-//! Enables individual flash controller interrupt sources.
-//!
-//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled.
-//! Can be any of the \b FLASH_FCIM_PROGRAM or \b FLASH_FCIM_ACCESS values.
-//!
-//! Enables the indicated flash controller interrupt sources. Only the sources
-//! that are enabled can be reflected to the processor interrupt; disabled
-//! sources have no effect on the processor.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-FlashIntEnable(unsigned long ulIntFlags)
-{
- //
- // Enable the specified interrupts.
- //
- HWREG(FLASH_FCIM) |= ulIntFlags;
-}
-
-//*****************************************************************************
-//
-//! Disables individual flash controller interrupt sources.
-//!
-//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled.
-//! Can be any of the \b FLASH_FCIM_PROGRAM or \b FLASH_FCIM_ACCESS values.
-//!
-//! Disables the indicated flash controller interrupt sources. Only the
-//! sources that are enabled can be reflected to the processor interrupt;
-//! disabled sources have no effect on the processor.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-FlashIntDisable(unsigned long ulIntFlags)
-{
- //
- // Disable the specified interrupts.
- //
- HWREG(FLASH_FCIM) &= ~(ulIntFlags);
-}
-
-//*****************************************************************************
-//
-//! Gets the current interrupt status.
-//!
-//! \param bMasked is false if the raw interrupt status is required and true if
-//! the masked interrupt status is required.
-//!
-//! This returns the interrupt status for the flash controller. Either the raw
-//! interrupt status or the status of interrupts that are allowed to reflect to
-//! the processor can be returned.
-//!
-//! \return The current interrupt status, enumerated as a bit field of
-//! \b FLASH_FCMISC_PROGRAM and \b FLASH_FCMISC_AMISC.
-//
-//*****************************************************************************
-unsigned long
-FlashIntGetStatus(tBoolean bMasked)
-{
- //
- // Return either the interrupt status or the raw interrupt status as
- // requested.
- //
- if(bMasked)
- {
- return(HWREG(FLASH_FCMISC));
- }
- else
- {
- return(HWREG(FLASH_FCRIS));
- }
-}
-
-//*****************************************************************************
-//
-//! Clears flash controller interrupt sources.
-//!
-//! \param ulIntFlags is the bit mask of the interrupt sources to be cleared.
-//! Can be any of the \b FLASH_FCMISC_PROGRAM or \b FLASH_FCMISC_AMISC values.
-//!
-//! The specified flash controller interrupt sources are cleared, so that they
-//! no longer assert. This must be done in the interrupt handler to keep it
-//! from being called again immediately upon exit.
-//!
-//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
-//! several clock cycles before the interrupt source is actually cleared.
-//! Therefore, it is recommended that the interrupt source be cleared early in
-//! the interrupt handler (as opposed to the very last action) to avoid
-//! returning from the interrupt handler before the interrupt source is
-//! actually cleared. Failure to do so may result in the interrupt handler
-//! being immediately reentered (since NVIC still sees the interrupt source
-//! asserted).
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-FlashIntClear(unsigned long ulIntFlags)
-{
- //
- // Clear the flash interrupt.
- //
- HWREG(FLASH_FCMISC) = ulIntFlags;
-}
-
-//*****************************************************************************
-//
-// Close the Doxygen group.
-//! @}
-//
-//*****************************************************************************
+//*****************************************************************************
+//
+// flash.c - Driver for programming the on-chip flash.
+//
+// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup flash_api
+//! @{
+//
+//*****************************************************************************
+
+#include "hw_flash.h"
+#include "hw_ints.h"
+#include "hw_sysctl.h"
+#include "hw_types.h"
+#include "debug.h"
+#include "flash.h"
+#include "interrupt.h"
+
+//*****************************************************************************
+//
+// An array that maps the specified memory bank to the appropriate Flash
+// Memory Protection Program Enable (FMPPE) register.
+//
+//*****************************************************************************
+static const unsigned long g_pulFMPPERegs[] =
+{
+ FLASH_FMPPE,
+ FLASH_FMPPE1,
+ FLASH_FMPPE2,
+ FLASH_FMPPE3
+};
+
+//*****************************************************************************
+//
+// An array that maps the specified memory bank to the appropriate Flash
+// Memory Protection Read Enable (FMPRE) register.
+//
+//*****************************************************************************
+static const unsigned long g_pulFMPRERegs[] =
+{
+ FLASH_FMPRE,
+ FLASH_FMPRE1,
+ FLASH_FMPRE2,
+ FLASH_FMPRE3
+};
+
+//*****************************************************************************
+//
+//! Gets the number of processor clocks per micro-second.
+//!
+//! This function returns the number of clocks per micro-second, as presently
+//! known by the flash controller.
+//!
+//! \return Returns the number of processor clocks per micro-second.
+//
+//*****************************************************************************
+unsigned long
+FlashUsecGet(void)
+{
+ //
+ // Return the number of clocks per micro-second.
+ //
+ return(HWREG(FLASH_USECRL) + 1);
+}
+
+//*****************************************************************************
+//
+//! Sets the number of processor clocks per micro-second.
+//!
+//! \param ulClocks is the number of processor clocks per micro-second.
+//!
+//! This function is used to tell the flash controller the number of processor
+//! clocks per micro-second. This value must be programmed correctly or the
+//! flash most likely will not program correctly; it has no affect on reading
+//! flash.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+FlashUsecSet(unsigned long ulClocks)
+{
+ //
+ // Set the number of clocks per micro-second.
+ //
+ HWREG(FLASH_USECRL) = ulClocks - 1;
+}
+
+//*****************************************************************************
+//
+//! Erases a block of flash.
+//!
+//! \param ulAddress is the start address of the flash block to be erased.
+//!
+//! This function will erase a 1 kB block of the on-chip flash. After erasing,
+//! the block will be filled with 0xFF bytes. Read-only and execute-only
+//! blocks cannot be erased.
+//!
+//! This function will not return until the block has been erased.
+//!
+//! \return Returns 0 on success, or -1 if an invalid block address was
+//! specified or the block is write-protected.
+//
+//*****************************************************************************
+long
+FlashErase(unsigned long ulAddress)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(!(ulAddress & (FLASH_ERASE_SIZE - 1)));
+
+ //
+ // Clear the flash access interrupt.
+ //
+ HWREG(FLASH_FCMISC) = FLASH_FCMISC_AMISC;
+
+ //
+ // Erase the block.
+ //
+ HWREG(FLASH_FMA) = ulAddress;
+ HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_ERASE;
+
+ //
+ // Wait until the block has been erased.
+ //
+ while(HWREG(FLASH_FMC) & FLASH_FMC_ERASE)
+ {
+ }
+
+ //
+ // Return an error if an access violation occurred.
+ //
+ if(HWREG(FLASH_FCRIS) & FLASH_FCRIS_ARIS)
+ {
+ return(-1);
+ }
+
+ //
+ // Success.
+ //
+ return(0);
+}
+
+//*****************************************************************************
+//
+//! Programs flash.
+//!
+//! \param pulData is a pointer to the data to be programmed.
+//! \param ulAddress is the starting address in flash to be programmed. Must
+//! be a multiple of four.
+//! \param ulCount is the number of bytes to be programmed. Must be a multiple
+//! of four.
+//!
+//! This function will program a sequence of words into the on-chip flash.
+//! Programming each location consists of the result of an AND operation
+//! of the new data and the existing data; in other words bits that contain
+//! 1 can remain 1 or be changed to 0, but bits that are 0 cannot be changed
+//! to 1. Therefore, a word can be programmed multiple times as long as these
+//! rules are followed; if a program operation attempts to change a 0 bit to
+//! a 1 bit, that bit will not have its value changed.
+//!
+//! Since the flash is programmed one word at a time, the starting address and
+//! byte count must both be multiples of four. It is up to the caller to
+//! verify the programmed contents, if such verification is required.
+//!
+//! This function will not return until the data has been programmed.
+//!
+//! \return Returns 0 on success, or -1 if a programming error is encountered.
+//
+//*****************************************************************************
+long
+FlashProgram(unsigned long *pulData, unsigned long ulAddress,
+ unsigned long ulCount)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(!(ulAddress & 3));
+ ASSERT(!(ulCount & 3));
+
+ //
+ // Clear the flash access interrupt.
+ //
+ HWREG(FLASH_FCMISC) = FLASH_FCMISC_AMISC;
+
+ //
+ // See if this device has a write buffer.
+ //
+ if(HWREG(SYSCTL_NVMSTAT) & SYSCTL_NVMSTAT_FWB)
+ {
+ //
+ // Loop over the words to be programmed.
+ //
+ while(ulCount)
+ {
+ //
+ // Set the address of this block of words.
+ //
+ HWREG(FLASH_FMA) = ulAddress & ~(0x7f);
+
+ //
+ // Loop over the words in this 32-word block.
+ //
+ while(((ulAddress & 0x7c) || (HWREG(FLASH_FWBVAL) == 0)) &&
+ (ulCount != 0))
+ {
+ //
+ // Write this word into the write buffer.
+ //
+ HWREG(FLASH_FWBN + (ulAddress & 0x7c)) = *pulData++;
+ ulAddress += 4;
+ ulCount -= 4;
+ }
+
+ //
+ // Program the contents of the write buffer into flash.
+ //
+ HWREG(FLASH_FMC2) = FLASH_FMC2_WRKEY | FLASH_FMC2_WRBUF;
+
+ //
+ // Wait until the write buffer has been programmed.
+ //
+ while(HWREG(FLASH_FMC2) & FLASH_FMC2_WRBUF)
+ {
+ }
+ }
+ }
+ else
+ {
+ //
+ // Loop over the words to be programmed.
+ //
+ while(ulCount)
+ {
+ //
+ // Program the next word.
+ //
+ HWREG(FLASH_FMA) = ulAddress;
+ HWREG(FLASH_FMD) = *pulData;
+ HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_WRITE;
+
+ //
+ // Wait until the word has been programmed.
+ //
+ while(HWREG(FLASH_FMC) & FLASH_FMC_WRITE)
+ {
+ }
+
+ //
+ // Increment to the next word.
+ //
+ pulData++;
+ ulAddress += 4;
+ ulCount -= 4;
+ }
+ }
+
+ //
+ // Return an error if an access violation occurred.
+ //
+ if(HWREG(FLASH_FCRIS) & FLASH_FCRIS_ARIS)
+ {
+ return(-1);
+ }
+
+ //
+ // Success.
+ //
+ return(0);
+}
+
+//*****************************************************************************
+//
+//! Gets the protection setting for a block of flash.
+//!
+//! \param ulAddress is the start address of the flash block to be queried.
+//!
+//! This function will get the current protection for the specified 2 kB block
+//! of flash. Each block can be read/write, read-only, or execute-only.
+//! Read/write blocks can be read, executed, erased, and programmed. Read-only
+//! blocks can be read and executed. Execute-only blocks can only be executed;
+//! processor and debugger data reads are not allowed.
+//!
+//! \return Returns the protection setting for this block. See
+//! FlashProtectSet() for possible values.
+//
+//*****************************************************************************
+tFlashProtection
+FlashProtectGet(unsigned long ulAddress)
+{
+ unsigned long ulFMPRE, ulFMPPE;
+ unsigned long ulBank;
+
+ //
+ // Check the argument.
+ //
+ ASSERT(!(ulAddress & (FLASH_PROTECT_SIZE - 1)));
+
+ //
+ // Calculate the Flash Bank from Base Address, and mask off the Bank
+ // from ulAddress for subsequent reference.
+ //
+ ulBank = (((ulAddress / FLASH_PROTECT_SIZE) / 32) % 4);
+ ulAddress &= ((FLASH_PROTECT_SIZE * 32) - 1);
+
+ //
+ // Read the appropriate flash protection registers for the specified
+ // flash bank.
+ //
+ ulFMPRE = HWREG(g_pulFMPRERegs[ulBank]);
+ ulFMPPE = HWREG(g_pulFMPPERegs[ulBank]);
+
+ //
+ // For Stellaris Sandstorm-class devices, revision C1 and C2, the upper
+ // bits of the FMPPE register are used for JTAG protect options, and are
+ // not available for the FLASH protection scheme. When Querying Block
+ // Protection, assume these bits are 1.
+ //
+ if(CLASS_IS_SANDSTORM && (REVISION_IS_C1 || REVISION_IS_C2))
+ {
+ ulFMPRE |= (FLASH_FMP_BLOCK_31 | FLASH_FMP_BLOCK_30);
+ }
+
+ //
+ // Check the appropriate protection bits for the block of memory that
+ // is specified by the address.
+ //
+ switch((((ulFMPRE >> (ulAddress / FLASH_PROTECT_SIZE)) &
+ FLASH_FMP_BLOCK_0) << 1) |
+ ((ulFMPPE >> (ulAddress / FLASH_PROTECT_SIZE)) & FLASH_FMP_BLOCK_0))
+ {
+ //
+ // This block is marked as execute only (that is, it can not be erased
+ // or programmed, and the only reads allowed are via the instruction
+ // fetch interface).
+ //
+ case 0:
+ case 1:
+ {
+ return(FlashExecuteOnly);
+ }
+
+ //
+ // This block is marked as read only (that is, it can not be erased or
+ // programmed).
+ //
+ case 2:
+ {
+ return(FlashReadOnly);
+ }
+
+ //
+ // This block is read/write; it can be read, erased, and programmed.
+ //
+ case 3:
+ default:
+ {
+ return(FlashReadWrite);
+ }
+ }
+}
+
+//*****************************************************************************
+//
+//! Sets the protection setting for a block of flash.
+//!
+//! \param ulAddress is the start address of the flash block to be protected.
+//! \param eProtect is the protection to be applied to the block. Can be one
+//! of \b FlashReadWrite, \b FlashReadOnly, or \b FlashExecuteOnly.
+//!
+//! This function will set the protection for the specified 2 kB block of
+//! flash. Blocks which are read/write can be made read-only or execute-only.
+//! Blocks which are read-only can be made execute-only. Blocks which are
+//! execute-only cannot have their protection modified. Attempts to make the
+//! block protection less stringent (that is, read-only to read/write) will
+//! result in a failure (and be prevented by the hardware).
+//!
+//! Changes to the flash protection are maintained only until the next reset.
+//! This allows the application to be executed in the desired flash protection
+//! environment to check for inappropriate flash access (via the flash
+//! interrupt). To make the flash protection permanent, use the
+//! FlashProtectSave() function.
+//!
+//! \return Returns 0 on success, or -1 if an invalid address or an invalid
+//! protection was specified.
+//
+//*****************************************************************************
+long
+FlashProtectSet(unsigned long ulAddress, tFlashProtection eProtect)
+{
+ unsigned long ulProtectRE, ulProtectPE;
+ unsigned long ulBank;
+
+ //
+ // Check the argument.
+ //
+ ASSERT(!(ulAddress & (FLASH_PROTECT_SIZE - 1)));
+ ASSERT((eProtect == FlashReadWrite) || (eProtect == FlashReadOnly) ||
+ (eProtect == FlashExecuteOnly));
+
+ //
+ // Convert the address into a block number.
+ //
+ ulAddress /= FLASH_PROTECT_SIZE;
+
+ //
+ // ulAddress contains a "raw" block number. Derive the Flash Bank from
+ // the "raw" block number, and convert ulAddress to a "relative"
+ // block number.
+ //
+ ulBank = ((ulAddress / 32) % 4);
+ ulAddress %= 32;
+
+ //
+ // Get the current protection for the specified flash bank.
+ //
+ ulProtectRE = HWREG(g_pulFMPRERegs[ulBank]);
+ ulProtectPE = HWREG(g_pulFMPPERegs[ulBank]);
+
+ //
+ // For Stellaris Sandstorm-class devices, revision C1 and C2, the upper
+ // bits of the FMPPE register are used for JTAG protect options, and are
+ // not available for the FLASH protection scheme. When setting protection,
+ // check to see if block 30 or 31 and protection is FlashExecuteOnly. If
+ // so, return an error condition.
+ //
+ if(CLASS_IS_SANDSTORM && (REVISION_IS_C1 || REVISION_IS_C2))
+ {
+ if((ulAddress >= 30) && (eProtect == FlashExecuteOnly))
+ {
+ return(-1);
+ }
+ }
+
+ //
+ // Set the protection based on the requested proection.
+ //
+ switch(eProtect)
+ {
+ //
+ // Make this block execute only.
+ //
+ case FlashExecuteOnly:
+ {
+ //
+ // Turn off the read and program bits for this block.
+ //
+ ulProtectRE &= ~(FLASH_FMP_BLOCK_0 << ulAddress);
+ ulProtectPE &= ~(FLASH_FMP_BLOCK_0 << ulAddress);
+
+ //
+ // We're done handling this protection.
+ //
+ break;
+ }
+
+ //
+ // Make this block read only.
+ //
+ case FlashReadOnly:
+ {
+ //
+ // The block can not be made read only if it is execute only.
+ //
+ if(((ulProtectRE >> ulAddress) & FLASH_FMP_BLOCK_0) !=
+ FLASH_FMP_BLOCK_0)
+ {
+ return(-1);
+ }
+
+ //
+ // Make this block read only.
+ //
+ ulProtectPE &= ~(FLASH_FMP_BLOCK_0 << ulAddress);
+
+ //
+ // We're done handling this protection.
+ //
+ break;
+ }
+
+ //
+ // Make this block read/write.
+ //
+ case FlashReadWrite:
+ default:
+ {
+ //
+ // The block can not be made read/write if it is not already
+ // read/write.
+ //
+ if((((ulProtectRE >> ulAddress) & FLASH_FMP_BLOCK_0) !=
+ FLASH_FMP_BLOCK_0) ||
+ (((ulProtectPE >> ulAddress) & FLASH_FMP_BLOCK_0) !=
+ FLASH_FMP_BLOCK_0))
+ {
+ return(-1);
+ }
+
+ //
+ // The block is already read/write, so there is nothing to do.
+ //
+ return(0);
+ }
+ }
+
+ //
+ // For Stellaris Sandstorm-class devices, revision C1 and C2, the upper
+ // bits of the FMPPE register are used for JTAG options, and are not
+ // available for the FLASH protection scheme. When setting block
+ // protection, ensure that these bits are not altered.
+ //
+ if(CLASS_IS_SANDSTORM && (REVISION_IS_C1 || REVISION_IS_C2))
+ {
+ ulProtectRE &= ~(FLASH_FMP_BLOCK_31 | FLASH_FMP_BLOCK_30);
+ ulProtectRE |= (HWREG(g_pulFMPRERegs[ulBank]) &
+ (FLASH_FMP_BLOCK_31 | FLASH_FMP_BLOCK_30));
+ }
+
+ //
+ // Set the new protection for the specified flash bank.
+ //
+ HWREG(g_pulFMPRERegs[ulBank]) = ulProtectRE;
+ HWREG(g_pulFMPPERegs[ulBank]) = ulProtectPE;
+
+ //
+ // Success.
+ //
+ return(0);
+}
+
+//*****************************************************************************
+//
+//! Saves the flash protection settings.
+//!
+//! This function will make the currently programmed flash protection settings
+//! permanent. This is a non-reversible operation; a chip reset or power cycle
+//! will not change the flash protection.
+//!
+//! This function will not return until the protection has been saved.
+//!
+//! \return Returns 0 on success, or -1 if a hardware error is encountered.
+//
+//*****************************************************************************
+long
+FlashProtectSave(void)
+{
+ int ulTemp, ulLimit;
+
+ //
+ // If running on a Sandstorm-class device, only trigger a save of the first
+ // two protection registers (FMPRE and FMPPE). Otherwise, save the
+ // entire bank of flash protection registers.
+ //
+ ulLimit = CLASS_IS_SANDSTORM ? 2 : 8;
+ for(ulTemp = 0; ulTemp < ulLimit; ulTemp++)
+ {
+ //
+ // Tell the flash controller to write the flash protection register.
+ //
+ HWREG(FLASH_FMA) = ulTemp;
+ HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_COMT;
+
+ //
+ // Wait until the write has completed.
+ //
+ while(HWREG(FLASH_FMC) & FLASH_FMC_COMT)
+ {
+ }
+ }
+
+ //
+ // Success.
+ //
+ return(0);
+}
+
+//*****************************************************************************
+//
+//! Gets the user registers.
+//!
+//! \param pulUser0 is a pointer to the location to store USER Register 0.
+//! \param pulUser1 is a pointer to the location to store USER Register 1.
+//!
+//! This function will read the contents of user registers (0 and 1), and
+//! store them in the specified locations.
+//!
+//! \return Returns 0 on success, or -1 if a hardware error is encountered.
+//
+//*****************************************************************************
+long
+FlashUserGet(unsigned long *pulUser0, unsigned long *pulUser1)
+{
+ //
+ // Verify that the pointers are valid.
+ //
+ ASSERT(pulUser0 != 0);
+ ASSERT(pulUser1 != 0);
+
+ //
+ // Verify that hardware supports user registers.
+ //
+ if(CLASS_IS_SANDSTORM)
+ {
+ return(-1);
+ }
+
+ //
+ // Get and store the current value of the user registers.
+ //
+ *pulUser0 = HWREG(FLASH_USERREG0);
+ *pulUser1 = HWREG(FLASH_USERREG1);
+
+ //
+ // Success.
+ //
+ return(0);
+}
+
+//*****************************************************************************
+//
+//! Sets the user registers.
+//!
+//! \param ulUser0 is the value to store in USER Register 0.
+//! \param ulUser1 is the value to store in USER Register 1.
+//!
+//! This function will set the contents of the user registers (0 and 1) to
+//! the specified values.
+//!
+//! \return Returns 0 on success, or -1 if a hardware error is encountered.
+//
+//*****************************************************************************
+long
+FlashUserSet(unsigned long ulUser0, unsigned long ulUser1)
+{
+ //
+ // Verify that hardware supports user registers.
+ //
+ if(CLASS_IS_SANDSTORM)
+ {
+ return(-1);
+ }
+
+ //
+ // Save the new values into the user registers.
+ //
+ HWREG(FLASH_USERREG0) = ulUser0;
+ HWREG(FLASH_USERREG1) = ulUser1;
+
+ //
+ // Success.
+ //
+ return(0);
+}
+
+//*****************************************************************************
+//
+//! Saves the user registers.
+//!
+//! This function will make the currently programmed user register settings
+//! permanent. This is a non-reversible operation; a chip reset or power cycle
+//! will not change this setting.
+//!
+//! This function will not return until the protection has been saved.
+//!
+//! \return Returns 0 on success, or -1 if a hardware error is encountered.
+//
+//*****************************************************************************
+long
+FlashUserSave(void)
+{
+ //
+ // Verify that hardware supports user registers.
+ //
+ if(CLASS_IS_SANDSTORM)
+ {
+ return(-1);
+ }
+
+ //
+ // Setting the MSB of FMA will trigger a permanent save of a USER
+ // register. Bit 0 will indicate User 0 (0) or User 1 (1).
+ //
+ HWREG(FLASH_FMA) = 0x80000000;
+ HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_COMT;
+
+ //
+ // Wait until the write has completed.
+ //
+ while(HWREG(FLASH_FMC) & FLASH_FMC_COMT)
+ {
+ }
+
+ //
+ // Tell the flash controller to write the USER1 Register.
+ //
+ HWREG(FLASH_FMA) = 0x80000001;
+ HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_COMT;
+
+ //
+ // Wait until the write has completed.
+ //
+ while(HWREG(FLASH_FMC) & FLASH_FMC_COMT)
+ {
+ }
+
+ //
+ // Success.
+ //
+ return(0);
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the flash interrupt.
+//!
+//! \param pfnHandler is a pointer to the function to be called when the flash
+//! interrupt occurs.
+//!
+//! This sets the handler to be called when the flash interrupt occurs. The
+//! flash controller can generate an interrupt when an invalid flash access
+//! occurs, such as trying to program or erase a read-only block, or trying to
+//! read from an execute-only block. It can also generate an interrupt when a
+//! program or erase operation has completed. The interrupt will be
+//! automatically enabled when the handler is registered.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+FlashIntRegister(void (*pfnHandler)(void))
+{
+ //
+ // Register the interrupt handler, returning an error if an error occurs.
+ //
+ IntRegister(INT_FLASH, pfnHandler);
+
+ //
+ // Enable the flash interrupt.
+ //
+ IntEnable(INT_FLASH);
+}
+
+//*****************************************************************************
+//
+//! Unregisters the interrupt handler for the flash interrupt.
+//!
+//! This function will clear the handler to be called when the flash interrupt
+//! occurs. This will also mask off the interrupt in the interrupt controller
+//! so that the interrupt handler is no longer called.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+FlashIntUnregister(void)
+{
+ //
+ // Disable the interrupt.
+ //
+ IntDisable(INT_FLASH);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(INT_FLASH);
+}
+
+//*****************************************************************************
+//
+//! Enables individual flash controller interrupt sources.
+//!
+//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled.
+//! Can be any of the \b FLASH_FCIM_PROGRAM or \b FLASH_FCIM_ACCESS values.
+//!
+//! Enables the indicated flash controller interrupt sources. Only the sources
+//! that are enabled can be reflected to the processor interrupt; disabled
+//! sources have no effect on the processor.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+FlashIntEnable(unsigned long ulIntFlags)
+{
+ //
+ // Enable the specified interrupts.
+ //
+ HWREG(FLASH_FCIM) |= ulIntFlags;
+}
+
+//*****************************************************************************
+//
+//! Disables individual flash controller interrupt sources.
+//!
+//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled.
+//! Can be any of the \b FLASH_FCIM_PROGRAM or \b FLASH_FCIM_ACCESS values.
+//!
+//! Disables the indicated flash controller interrupt sources. Only the
+//! sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+FlashIntDisable(unsigned long ulIntFlags)
+{
+ //
+ // Disable the specified interrupts.
+ //
+ HWREG(FLASH_FCIM) &= ~(ulIntFlags);
+}
+
+//*****************************************************************************
+//
+//! Gets the current interrupt status.
+//!
+//! \param bMasked is false if the raw interrupt status is required and true if
+//! the masked interrupt status is required.
+//!
+//! This returns the interrupt status for the flash controller. Either the raw
+//! interrupt status or the status of interrupts that are allowed to reflect to
+//! the processor can be returned.
+//!
+//! \return The current interrupt status, enumerated as a bit field of
+//! \b FLASH_FCMISC_PROGRAM and \b FLASH_FCMISC_AMISC.
+//
+//*****************************************************************************
+unsigned long
+FlashIntGetStatus(tBoolean bMasked)
+{
+ //
+ // Return either the interrupt status or the raw interrupt status as
+ // requested.
+ //
+ if(bMasked)
+ {
+ return(HWREG(FLASH_FCMISC));
+ }
+ else
+ {
+ return(HWREG(FLASH_FCRIS));
+ }
+}
+
+//*****************************************************************************
+//
+//! Clears flash controller interrupt sources.
+//!
+//! \param ulIntFlags is the bit mask of the interrupt sources to be cleared.
+//! Can be any of the \b FLASH_FCMISC_PROGRAM or \b FLASH_FCMISC_AMISC values.
+//!
+//! The specified flash controller interrupt sources are cleared, so that they
+//! no longer assert. This must be done in the interrupt handler to keep it
+//! from being called again immediately upon exit.
+//!
+//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
+//! several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared. Failure to do so may result in the interrupt handler
+//! being immediately reentered (since NVIC still sees the interrupt source
+//! asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+FlashIntClear(unsigned long ulIntFlags)
+{
+ //
+ // Clear the flash interrupt.
+ //
+ HWREG(FLASH_FCMISC) = ulIntFlags;
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
Property changes on: branches/eagle_mmc/src/platform/lm3s/flash.c
___________________________________________________________________
Name: svn:executable
+ *
Modified: branches/eagle_mmc/src/platform/lm3s/flash.h
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/flash.h 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lm3s/flash.h 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,89 +1,89 @@
-//*****************************************************************************
-//
-// flash.h - Prototypes for the flash driver.
-//
-// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved
-// Software License Agreement
-//
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
-//
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws. All rights are reserved. You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program. Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
-//
-// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-//
-// This is part of revision 3740 of the Stellaris Peripheral Driver Library.
-//
-//*****************************************************************************
-
-#ifndef __FLASH_H__
-#define __FLASH_H__
-
-//*****************************************************************************
-//
-// If building with a C++ compiler, make all of the definitions in this header
-// have a C binding.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-//*****************************************************************************
-//
-// Values that can be passed to FlashProtectSet(), and returned by
-// FlashProtectGet().
-//
-//*****************************************************************************
-typedef enum
-{
- FlashReadWrite, // Flash can be read and written
- FlashReadOnly, // Flash can only be read
- FlashExecuteOnly // Flash can only be executed
-}
-tFlashProtection;
-
-//*****************************************************************************
-//
-// Prototypes for the APIs.
-//
-//*****************************************************************************
-extern unsigned long FlashUsecGet(void);
-extern void FlashUsecSet(unsigned long ulClocks);
-extern long FlashErase(unsigned long ulAddress);
-extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress,
- unsigned long ulCount);
-extern tFlashProtection FlashProtectGet(unsigned long ulAddress);
-extern long FlashProtectSet(unsigned long ulAddress,
- tFlashProtection eProtect);
-extern long FlashProtectSave(void);
-extern long FlashUserGet(unsigned long *pulUser0, unsigned long *pulUser1);
-extern long FlashUserSet(unsigned long ulUser0, unsigned long ulUser1);
-extern long FlashUserSave(void);
-extern void FlashIntRegister(void (*pfnHandler)(void));
-extern void FlashIntUnregister(void);
-extern void FlashIntEnable(unsigned long ulIntFlags);
-extern void FlashIntDisable(unsigned long ulIntFlags);
-extern unsigned long FlashIntGetStatus(tBoolean bMasked);
-extern void FlashIntClear(unsigned long ulIntFlags);
-
-//*****************************************************************************
-//
-// Mark the end of the C bindings section for C++ compilers.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-}
-#endif
-
-#endif // __FLASH_H__
+//*****************************************************************************
+//
+// flash.h - Prototypes for the flash driver.
+//
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __FLASH_H__
+#define __FLASH_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to FlashProtectSet(), and returned by
+// FlashProtectGet().
+//
+//*****************************************************************************
+typedef enum
+{
+ FlashReadWrite, // Flash can be read and written
+ FlashReadOnly, // Flash can only be read
+ FlashExecuteOnly // Flash can only be executed
+}
+tFlashProtection;
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern unsigned long FlashUsecGet(void);
+extern void FlashUsecSet(unsigned long ulClocks);
+extern long FlashErase(unsigned long ulAddress);
+extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress,
+ unsigned long ulCount);
+extern tFlashProtection FlashProtectGet(unsigned long ulAddress);
+extern long FlashProtectSet(unsigned long ulAddress,
+ tFlashProtection eProtect);
+extern long FlashProtectSave(void);
+extern long FlashUserGet(unsigned long *pulUser0, unsigned long *pulUser1);
+extern long FlashUserSet(unsigned long ulUser0, unsigned long ulUser1);
+extern long FlashUserSave(void);
+extern void FlashIntRegister(void (*pfnHandler)(void));
+extern void FlashIntUnregister(void);
+extern void FlashIntEnable(unsigned long ulIntFlags);
+extern void FlashIntDisable(unsigned long ulIntFlags);
+extern unsigned long FlashIntGetStatus(tBoolean bMasked);
+extern void FlashIntClear(unsigned long ulIntFlags);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __FLASH_H__
Property changes on: branches/eagle_mmc/src/platform/lm3s/flash.h
___________________________________________________________________
Name: svn:executable
+ *
Modified: branches/eagle_mmc/src/platform/lm3s/gpio.c
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/gpio.c 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lm3s/gpio.c 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,1343 +1,1517 @@
-//*****************************************************************************
-//
-// gpio.c - API for GPIO ports
-//
-// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
-// Software License Agreement
-//
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
-//
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws. All rights are reserved. You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program. Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
-//
-// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-//
-// This is part of revision 3740 of the Stellaris Peripheral Driver Library.
-//
-//*****************************************************************************
-
-//*****************************************************************************
-//
-//! \addtogroup gpio_api
-//! @{
-//
-//*****************************************************************************
-
-#include "hw_gpio.h"
-#include "hw_ints.h"
-#include "hw_memmap.h"
-#include "hw_types.h"
-#include "debug.h"
-#include "gpio.h"
-#include "interrupt.h"
-
-//*****************************************************************************
-//
-//! \internal
-//! Checks a GPIO base address.
-//!
-//! \param ulPort is the base address of the GPIO port.
-//!
-//! This function determines if a GPIO port base address is valid.
-//!
-//! \return Returns \b true if the base address is valid and \b false
-//! otherwise.
-//
-//*****************************************************************************
-#ifdef DEBUG
-static tBoolean
-GPIOBaseValid(unsigned long ulPort)
-{
- return((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTA_AHB_BASE) ||
- (ulPort == GPIO_PORTB_BASE) || (ulPort == GPIO_PORTB_AHB_BASE) ||
- (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTC_AHB_BASE) ||
- (ulPort == GPIO_PORTD_BASE) || (ulPort == GPIO_PORTD_AHB_BASE) ||
- (ulPort == GPIO_PORTE_BASE) || (ulPort == GPIO_PORTE_AHB_BASE) ||
- (ulPort == GPIO_PORTF_BASE) || (ulPort == GPIO_PORTF_AHB_BASE) ||
- (ulPort == GPIO_PORTG_BASE) || (ulPort == GPIO_PORTG_AHB_BASE) ||
- (ulPort == GPIO_PORTH_BASE) || (ulPort == GPIO_PORTH_AHB_BASE));
-}
-#endif
-
-//*****************************************************************************
-//
-//! \internal
-//! Gets the GPIO interrupt number.
-//!
-//! \param ulPort is the base address of the GPIO port.
-//!
-//! Given a GPIO base address, returns the corresponding interrupt number.
-//!
-//! \return Returns a GPIO interrupt number, or -1 if \e ulPort is invalid.
-//
-//*****************************************************************************
-static long
-GPIOGetIntNumber(unsigned long ulPort)
-{
- unsigned int ulInt;
-
- //
- // Determine the GPIO interrupt number for the given module.
- //
- switch(ulPort)
- {
- case GPIO_PORTA_BASE:
- case GPIO_PORTA_AHB_BASE:
- {
- ulInt = INT_GPIOA;
- break;
- }
-
- case GPIO_PORTB_BASE:
- case GPIO_PORTB_AHB_BASE:
- {
- ulInt = INT_GPIOB;
- break;
- }
-
- case GPIO_PORTC_BASE:
- case GPIO_PORTC_AHB_BASE:
- {
- ulInt = INT_GPIOC;
- break;
- }
-
- case GPIO_PORTD_BASE:
- case GPIO_PORTD_AHB_BASE:
- {
- ulInt = INT_GPIOD;
- break;
- }
-
- case GPIO_PORTE_BASE:
- case GPIO_PORTE_AHB_BASE:
- {
- ulInt = INT_GPIOE;
- break;
- }
-
- case GPIO_PORTF_BASE:
- case GPIO_PORTF_AHB_BASE:
- {
- ulInt = INT_GPIOF;
- break;
- }
-
- case GPIO_PORTG_BASE:
- case GPIO_PORTG_AHB_BASE:
- {
- ulInt = INT_GPIOG;
- break;
- }
-
- case GPIO_PORTH_BASE:
- case GPIO_PORTH_AHB_BASE:
- {
- ulInt = INT_GPIOH;
- break;
- }
-
- default:
- {
- return(-1);
- }
- }
-
- //
- // Return GPIO interrupt number.
- //
- return(ulInt);
-}
-
-//*****************************************************************************
-//
-//! Sets the direction and mode of the specified pin(s).
-//!
-//! \param ulPort is the base address of the GPIO port
-//! \param ucPins is the bit-packed representation of the pin(s).
-//! \param ulPinIO is the pin direction and/or mode.
-//!
-//! This function will set the specified pin(s) on the selected GPIO port
-//! as either an input or output under software control, or it will set the
-//! pin to be under hardware control.
-//!
-//! The parameter \e ulPinIO is an enumerated data type that can be one of
-//! the following values:
-//!
-//! - \b GPIO_DIR_MODE_IN
-//! - \b GPIO_DIR_MODE_OUT
-//! - \b GPIO_DIR_MODE_HW
-//!
-//! where \b GPIO_DIR_MODE_IN specifies that the pin will be programmed as
-//! a software controlled input, \b GPIO_DIR_MODE_OUT specifies that the pin
-//! will be programmed as a software controlled output, and
-//! \b GPIO_DIR_MODE_HW specifies that the pin will be placed under
-//! hardware control.
-//!
-//! The pin(s) are specified using a bit-packed byte, where each bit that is
-//! set identifies the pin to be accessed, and where bit 0 of the byte
-//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-GPIODirModeSet(unsigned long ulPort, unsigned char ucPins,
- unsigned long ulPinIO)
-{
- //
- // Check the arguments.
- //
- ASSERT(GPIOBaseValid(ulPort));
- ASSERT((ulPinIO == GPIO_DIR_MODE_IN) || (ulPinIO == GPIO_DIR_MODE_OUT) ||
- (ulPinIO == GPIO_DIR_MODE_HW));
-
- //
- // Set the pin direction and mode.
- //
- HWREG(ulPort + GPIO_O_DIR) = ((ulPinIO & 1) ?
- (HWREG(ulPort + GPIO_O_DIR) | ucPins) :
- (HWREG(ulPort + GPIO_O_DIR) & ~(ucPins)));
- HWREG(ulPort + GPIO_O_AFSEL) = ((ulPinIO & 2) ?
- (HWREG(ulPort + GPIO_O_AFSEL) | ucPins) :
- (HWREG(ulPort + GPIO_O_AFSEL) &
- ~(ucPins)));
-}
-
-//*****************************************************************************
-//
-//! Gets the direction and mode of a pin.
-//!
-//! \param ulPort is the base address of the GPIO port.
-//! \param ucPin is the pin number.
-//!
-//! This function gets the direction and control mode for a specified pin on
-//! the selected GPIO port. The pin can be configured as either an input or
-//! output under software control, or it can be under hardware control. The
-//! type of control and direction are returned as an enumerated data type.
-//!
-//! \return Returns one of the enumerated data types described for
-//! GPIODirModeSet().
-//
-//*****************************************************************************
-unsigned long
-GPIODirModeGet(unsigned long ulPort, unsigned char ucPin)
-{
- unsigned long ulDir, ulAFSEL;
-
- //
- // Check the arguments.
- //
- ASSERT(GPIOBaseValid(ulPort));
- ASSERT(ucPin < 8);
-
- //
- // Convert from a pin number to a bit position.
- //
- ucPin = 1 << ucPin;
-
- //
- // Return the pin direction and mode.
- //
- ulDir = HWREG(ulPort + GPIO_O_DIR);
- ulAFSEL = HWREG(ulPort + GPIO_O_AFSEL);
- return(((ulDir & ucPin) ? 1 : 0) | ((ulAFSEL & ucPin) ? 2 : 0));
-}
-
-//*****************************************************************************
-//
-//! Sets the interrupt type for the specified pin(s).
-//!
-//! \param ulPort is the base address of the GPIO port.
-//! \param ucPins is the bit-packed representation of the pin(s).
-//! \param ulIntType specifies the type of interrupt trigger mechanism.
-//!
-//! This function sets up the various interrupt trigger mechanisms for the
-//! specified pin(s) on the selected GPIO port.
-//!
-//! The parameter \e ulIntType is an enumerated data type that can be one of
-//! the following values:
-//!
-//! - \b GPIO_FALLING_EDGE
-//! - \b GPIO_RISING_EDGE
-//! - \b GPIO_BOTH_EDGES
-//! - \b GPIO_LOW_LEVEL
-//! - \b GPIO_HIGH_LEVEL
-//!
-//! where the different values describe the interrupt detection mechanism
-//! (edge or level) and the particular triggering event (falling, rising,
-//! or both edges for edge detect, low or high for level detect).
-//!
-//! The pin(s) are specified using a bit-packed byte, where each bit that is
-//! set identifies the pin to be accessed, and where bit 0 of the byte
-//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
-//!
-//! \note In order to avoid any spurious interrupts, the user must
-//! ensure that the GPIO inputs remain stable for the duration of
-//! this function.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins,
- unsigned long ulIntType)
-{
- //
- // Check the arguments.
- //
- ASSERT(GPIOBaseValid(ulPort));
- ASSERT((ulIntType == GPIO_FALLING_EDGE) ||
- (ulIntType == GPIO_RISING_EDGE) || (ulIntType == GPIO_BOTH_EDGES) ||
- (ulIntType == GPIO_LOW_LEVEL) || (ulIntType == GPIO_HIGH_LEVEL));
-
- //
- // Set the pin interrupt type.
- //
- HWREG(ulPort + GPIO_O_IBE) = ((ulIntType & 1) ?
- (HWREG(ulPort + GPIO_O_IBE) | ucPins) :
- (HWREG(ulPort + GPIO_O_IBE) & ~(ucPins)));
- HWREG(ulPort + GPIO_O_IS) = ((ulIntType & 2) ?
- (HWREG(ulPort + GPIO_O_IS) | ucPins) :
- (HWREG(ulPort + GPIO_O_IS) & ~(ucPins)));
- HWREG(ulPort + GPIO_O_IEV) = ((ulIntType & 4) ?
- (HWREG(ulPort + GPIO_O_IEV) | ucPins) :
- (HWREG(ulPort + GPIO_O_IEV) & ~(ucPins)));
-}
-
-//*****************************************************************************
-//
-//! Gets the interrupt type for a pin.
-//!
-//! \param ulPort is the base address of the GPIO port.
-//! \param ucPin is the pin number.
-//!
-//! This function gets the interrupt type for a specified pin on the selected
-//! GPIO port. The pin can be configured as a falling edge, rising edge, or
-//! both edge detected interrupt, or it can be configured as a low level or
-//! high level detected interrupt. The type of interrupt detection mechanism
-//! is returned as an enumerated data type.
-//!
-//! \return Returns one of the enumerated data types described for
-//! GPIOIntTypeSet().
-//
-//*****************************************************************************
-unsigned long
-GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin)
-{
- unsigned long ulIBE, ulIS, ulIEV;
-
- //
- // Check the arguments.
- //
- ASSERT(GPIOBaseValid(ulPort));
- ASSERT(ucPin < 8);
-
- //
- // Convert from a pin number to a bit position.
- //
- ucPin = 1 << ucPin;
-
- //
- // Return the pin interrupt type.
- //
- ulIBE = HWREG(ulPort + GPIO_O_IBE);
- ulIS = HWREG(ulPort + GPIO_O_IS);
- ulIEV = HWREG(ulPort + GPIO_O_IEV);
- return(((ulIBE & ucPin) ? 1 : 0) | ((ulIS & ucPin) ? 2 : 0) |
- ((ulIEV & ucPin) ? 4 : 0));
-}
-
-//*****************************************************************************
-//
-//! Sets the pad configuration for the specified pin(s).
-//!
-//! \param ulPort is the base address of the GPIO port.
-//! \param ucPins is the bit-packed representation of the pin(s).
-//! \param ulStrength specifies the output drive strength.
-//! \param ulPinType specifies the pin type.
-//!
-//! This function sets the drive strength and type for the specified pin(s)
-//! on the selected GPIO port. For pin(s) configured as input ports, the
-//! pad is configured as requested, but the only real effect on the input
-//! is the configuration of the pull-up or pull-down termination.
-//!
-//! The parameter \e ulStrength can be one of the following values:
-//!
-//! - \b GPIO_STRENGTH_2MA
-//! - \b GPIO_STRENGTH_4MA
-//! - \b GPIO_STRENGTH_8MA
-//! - \b GPIO_STRENGTH_8MA_SC
-//!
-//! where \b GPIO_STRENGTH_xMA specifies either 2, 4, or 8 mA output drive
-//! strength, and \b GPIO_OUT_STRENGTH_8MA_SC specifies 8 mA output drive with
-//! slew control.
-//!
-//! The parameter \e ulPinType can be one of the following values:
-//!
-//! - \b GPIO_PIN_TYPE_STD
-//! - \b GPIO_PIN_TYPE_STD_WPU
-//! - \b GPIO_PIN_TYPE_STD_WPD
-//! - \b GPIO_PIN_TYPE_OD
-//! - \b GPIO_PIN_TYPE_OD_WPU
-//! - \b GPIO_PIN_TYPE_OD_WPD
-//! - \b GPIO_PIN_TYPE_ANALOG
-//!
-//! where \b GPIO_PIN_TYPE_STD* specifies a push-pull pin, \b GPIO_PIN_TYPE_OD*
-//! specifies an open-drain pin, \b *_WPU specifies a weak pull-up, \b *_WPD
-//! specifies a weak pull-down, and \b GPIO_PIN_TYPE_ANALOG specifies an
-//! analog input (for the comparators).
-//!
-//! The pin(s) are specified using a bit-packed byte, where each bit that is
-//! set identifies the pin to be accessed, and where bit 0 of the byte
-//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins,
- unsigned long ulStrength, unsigned long ulPinType)
-{
- //
- // Check the arguments.
- //
- ASSERT(GPIOBaseValid(ulPort));
- ASSERT((ulStrength == GPIO_STRENGTH_2MA) ||
- (ulStrength == GPIO_STRENGTH_4MA) ||
- (ulStrength == GPIO_STRENGTH_8MA) ||
- (ulStrength == GPIO_STRENGTH_8MA_SC));
- ASSERT((ulPinType == GPIO_PIN_TYPE_STD) ||
- (ulPinType == GPIO_PIN_TYPE_STD_WPU) ||
- (ulPinType == GPIO_PIN_TYPE_STD_WPD) ||
- (ulPinType == GPIO_PIN_TYPE_OD) ||
- (ulPinType == GPIO_PIN_TYPE_OD_WPU) ||
- (ulPinType == GPIO_PIN_TYPE_OD_WPD) ||
- (ulPinType == GPIO_PIN_TYPE_ANALOG))
-
- //
- // Set the output drive strength.
- //
- HWREG(ulPort + GPIO_O_DR2R) = ((ulStrength & 1) ?
- (HWREG(ulPort + GPIO_O_DR2R) | ucPins) :
- (HWREG(ulPort + GPIO_O_DR2R) & ~(ucPins)));
- HWREG(ulPort + GPIO_O_DR4R) = ((ulStrength & 2) ?
- (HWREG(ulPort + GPIO_O_DR4R) | ucPins) :
- (HWREG(ulPort + GPIO_O_DR4R) & ~(ucPins)));
- HWREG(ulPort + GPIO_O_DR8R) = ((ulStrength & 4) ?
- (HWREG(ulPort + GPIO_O_DR8R) | ucPins) :
- (HWREG(ulPort + GPIO_O_DR8R) & ~(ucPins)));
- HWREG(ulPort + GPIO_O_SLR) = ((ulStrength & 8) ?
- (HWREG(ulPort + GPIO_O_SLR) | ucPins) :
- (HWREG(ulPort + GPIO_O_SLR) & ~(ucPins)));
-
- //
- // Set the pin type.
- //
- HWREG(ulPort + GPIO_O_ODR) = ((ulPinType & 1) ?
- (HWREG(ulPort + GPIO_O_ODR) | ucPins) :
- (HWREG(ulPort + GPIO_O_ODR) & ~(ucPins)));
- HWREG(ulPort + GPIO_O_PUR) = ((ulPinType & 2) ?
- (HWREG(ulPort + GPIO_O_PUR) | ucPins) :
- (HWREG(ulPort + GPIO_O_PUR) & ~(ucPins)));
- HWREG(ulPort + GPIO_O_PDR) = ((ulPinType & 4) ?
- (HWREG(ulPort + GPIO_O_PDR) | ucPins) :
- (HWREG(ulPort + GPIO_O_PDR) & ~(ucPins)));
- HWREG(ulPort + GPIO_O_DEN) = ((ulPinType & 8) ?
- (HWREG(ulPort + GPIO_O_DEN) | ucPins) :
- (HWREG(ulPort + GPIO_O_DEN) & ~(ucPins)));
-
- //
- // Set the analog mode select register. This register only appears in
- // DustDevil-class (and later) devices, but is a harmless write on
- // Sandstorm- and Fury-class devices.
- //
- HWREG(ulPort + GPIO_O_AMSEL) =
- ((ulPinType == GPIO_PIN_TYPE_ANALOG) ?
- (HWREG(ulPort + GPIO_O_AMSEL) | ucPins) :
- (HWREG(ulPort + GPIO_O_AMSEL) & ~(ucPins)));
-}
-
-//*****************************************************************************
-//
-//! Gets the pad configuration for a pin.
-//!
-//! \param ulPort is the base address of the GPIO port.
-//! \param ucPin is the pin number.
-//! \param pulStrength is a pointer to storage for the output drive strength.
-//! \param pulPinType is a pointer to storage for the output drive type.
-//!
-//! This function gets the pad configuration for a specified pin on the
-//! selected GPIO port. The values returned in \e pulStrength and
-//! \e pulPinType correspond to the values used in GPIOPadConfigSet(). This
-//! function also works for pin(s) configured as input pin(s); however, the
-//! only meaningful data returned is whether the pin is terminated with a
-//! pull-up or down resistor.
-//!
-//! \return None
-//
-//*****************************************************************************
-void
-GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin,
- unsigned long *pulStrength, unsigned long *pulPinType)
-{
- unsigned long ulTemp1, ulTemp2, ulTemp3, ulTemp4;
-
- //
- // Check the arguments.
- //
- ASSERT(GPIOBaseValid(ulPort));
- ASSERT(ucPin < 8);
-
- //
- // Convert from a pin number to a bit position.
- //
- ucPin = (1 << ucPin);
-
- //
- // Get the drive strength for this pin.
- //
- ulTemp1 = HWREG(ulPort + GPIO_O_DR2R);
- ulTemp2 = HWREG(ulPort + GPIO_O_DR4R);
- ulTemp3 = HWREG(ulPort + GPIO_O_DR8R);
- ulTemp4 = HWREG(ulPort + GPIO_O_SLR);
- *pulStrength = (((ulTemp1 & ucPin) ? 1 : 0) | ((ulTemp2 & ucPin) ? 2 : 0) |
- ((ulTemp3 & ucPin) ? 4 : 0) | ((ulTemp4 & ucPin) ? 8 : 0));
-
- //
- // Get the pin type.
- //
- ulTemp1 = HWREG(ulPort + GPIO_O_ODR);
- ulTemp2 = HWREG(ulPort + GPIO_O_PUR);
- ulTemp3 = HWREG(ulPort + GPIO_O_PDR);
- ulTemp4 = HWREG(ulPort + GPIO_O_DEN);
- *pulPinType = (((ulTemp1 & ucPin) ? 1 : 0) | ((ulTemp2 & ucPin) ? 2 : 0) |
- ((ulTemp3 & ucPin) ? 4 : 0) | ((ulTemp4 & ucPin) ? 8 : 0));
-}
-
-//*****************************************************************************
-//
-//! Enables interrupts for the specified pin(s).
-//!
-//! \param ulPort is the base address of the GPIO port.
-//! \param ucPins is the bit-packed representation of the pin(s).
-//!
-//! Unmasks the interrupt for the specified pin(s).
-//!
-//! The pin(s) are specified using a bit-packed byte, where each bit that is
-//! set identifies the pin to be accessed, and where bit 0 of the byte
-//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins)
-{
- //
- // Check the arguments.
- //
- ASSERT(GPIOBaseValid(ulPort));
-
- //
- // Enable the interrupts.
- //
- HWREG(ulPort + GPIO_O_IM) |= ucPins;
-}
-
-//*****************************************************************************
-//
-//! Disables interrupts for the specified pin(s).
-//!
-//! \param ulPort is the base address of the GPIO port.
-//! \param ucPins is the bit-packed representation of the pin(s).
-//!
-//! Masks the interrupt for the specified pin(s).
-//!
-//! The pin(s) are specified using a bit-packed byte, where each bit that is
-//! set identifies the pin to be accessed, and where bit 0 of the byte
-//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins)
-{
- //
- // Check the arguments.
- //
- ASSERT(GPIOBaseValid(ulPort));
-
- //
- // Disable the interrupts.
- //
- HWREG(ulPort + GPIO_O_IM) &= ~(ucPins);
-}
-
-//*****************************************************************************
-//
-//! Gets interrupt status for the specified GPIO port.
-//!
-//! \param ulPort is the base address of the GPIO port.
-//! \param bMasked specifies whether masked or raw interrupt status is
-//! returned.
-//!
-//! If \e bMasked is set as \b true, then the masked interrupt status is
-//! returned; otherwise, the raw interrupt status will be returned.
-//!
-//! \return Returns a bit-packed byte, where each bit that is set identifies
-//! an active masked or raw interrupt, and where bit 0 of the byte
-//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
-//! Bits 31:8 should be ignored.
-//
-//*****************************************************************************
-long
-GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked)
-{
- //
- // Check the arguments.
- //
- ASSERT(GPIOBaseValid(ulPort));
-
- //
- // Return the interrupt status.
- //
- if(bMasked)
- {
- return(HWREG(ulPort + GPIO_O_MIS));
- }
- else
- {
- return(HWREG(ulPort + GPIO_O_RIS));
- }
-}
-
-//*****************************************************************************
-//
-//! Clears the interrupt for the specified pin(s).
-//!
-//! \param ulPort is the base address of the GPIO port.
-//! \param ucPins is the bit-packed representation of the pin(s).
-//!
-//! Clears the interrupt for the specified pin(s).
-//!
-//! The pin(s) are specified using a bit-packed byte, where each bit that is
-//! set identifies the pin to be accessed, and where bit 0 of the byte
-//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
-//!
-//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
-//! several clock cycles before the interrupt source is actually cleared.
-//! Therefore, it is recommended that the interrupt source be cleared early in
-//! the interrupt handler (as opposed to the very last action) to avoid
-//! returning from the interrupt handler before the interrupt source is
-//! actually cleared. Failure to do so may result in the interrupt handler
-//! being immediately reentered (since NVIC still sees the interrupt source
-//! asserted).
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins)
-{
- //
- // Check the arguments.
- //
- ASSERT(GPIOBaseValid(ulPort));
-
- //
- // Clear the interrupts.
- //
- HWREG(ulPort + GPIO_O_ICR) = ucPins;
-}
-
-//*****************************************************************************
-//
-//! Registers an interrupt handler for a GPIO port.
-//!
-//! \param ulPort is the base address of the GPIO port.
-//! \param pfnIntHandler is a pointer to the GPIO port interrupt handling
-//! function.
-//!
-//! This function will ensure that the interrupt handler specified by
-//! \e pfnIntHandler is called when an interrupt is detected from the selected
-//! GPIO port. This function will also enable the corresponding GPIO interrupt
-//! in the interrupt controller; individual pin interrupts and interrupt
-//! sources must be enabled with GPIOPinIntEnable().
-//!
-//! \sa IntRegister() for important information about registering interrupt
-//! handlers.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-GPIOPortIntRegister(unsigned long ulPort, void (*pfnIntHandler)(void))
-{
- //
- // Check the arguments.
- //
- ASSERT(GPIOBaseValid(ulPort));
-
- //
- // Get the interrupt number associated with the specified GPIO.
- //
- ulPort = GPIOGetIntNumber(ulPort);
-
- //
- // Register the interrupt handler.
- //
- IntRegister(ulPort, pfnIntHandler);
-
- //
- // Enable the GPIO interrupt.
- //
- IntEnable(ulPort);
-}
-
-//*****************************************************************************
-//
-//! Removes an interrupt handler for a GPIO port.
-//!
-//! \param ulPort is the base address of the GPIO port.
-//!
-//! This function will unregister the interrupt handler for the specified
-//! GPIO port. This function will also disable the corresponding
-//! GPIO port interrupt in the interrupt controller; individual GPIO interrupts
-//! and interrupt sources must be disabled with GPIOPinIntDisable().
-//!
-//! \sa IntRegister() for important information about registering interrupt
-//! handlers.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-GPIOPortIntUnregister(unsigned long ulPort)
-{
- //
- // Check the arguments.
- //
- ASSERT(GPIOBaseValid(ulPort));
-
- //
- // Get the interrupt number associated with the specified GPIO.
- //
- ulPort = GPIOGetIntNumber(ulPort);
-
- //
- // Disable the GPIO interrupt.
- //
- IntDisable(ulPort);
-
- //
- // Unregister the interrupt handler.
- //
- IntUnregister(ulPort);
-}
-
-//*****************************************************************************
-//
-//! Reads the values present of the specified pin(s).
-//!
-//! \param ulPort is the base address of the GPIO port.
-//! \param ucPins is the bit-packed representation of the pin(s).
-//!
-//! The values at the specified pin(s) are read, as specified by \e ucPins.
-//! Values are returned for both input and output pin(s), and the value
-//! for pin(s) that are not specified by \e ucPins are set to 0.
-//!
-//! The pin(s) are specified using a bit-packed byte, where each bit that is
-//! set identifies the pin to be accessed, and where bit 0 of the byte
-//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
-//!
-//! \return Returns a bit-packed byte providing the state of the specified
-//! pin, where bit 0 of the byte represents GPIO port pin 0, bit 1 represents
-//! GPIO port pin 1, and so on. Any bit that is not specified by \e ucPins
-//! is returned as a 0. Bits 31:8 should be ignored.
-//
-//*****************************************************************************
-long
-GPIOPinRead(unsigned long ulPort, unsigned char ucPins)
-{
- //
- // Check the arguments.
- //
- ASSERT(GPIOBaseValid(ulPort));
-
- //
- // Return the pin value(s).
- //
- return(HWREG(ulPort + (GPIO_O_DATA + (ucPins << 2))));
-}
-
-//*****************************************************************************
-//
-//! Writes a value to the specified pin(s).
-//!
-//! \param ulPort is the base address of the GPIO port.
-//! \param ucPins is the bit-packed representation of the pin(s).
-//! \param ucVal is the value to write to the pin(s).
-//!
-//! Writes the corresponding bit values to the output pin(s) specified by
-//! \e ucPins. Writing to a pin configured as an input pin has no effect.
-//!
-//! The pin(s) are specified using a bit-packed byte, where each bit that is
-//! set identifies the pin to be accessed, and where bit 0 of the byte
-//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-GPIOPinWrite(unsigned long ulPort, unsigned char ucPins, unsigned char ucVal)
-{
- //
- // Check the arguments.
- //
- ASSERT(GPIOBaseValid(ulPort));
-
- //
- // Write the pins.
- //
- HWREG(ulPort + (GPIO_O_DATA + (ucPins << 2))) = ucVal;
-}
-
-//*****************************************************************************
-//
-//! Configures pin(s) for use as analog-to-digital converter inputs.
-//!
-//! \param ulPort is the base address of the GPIO port.
-//! \param ucPins is the bit-packed representation of the pin(s).
-//!
-//! The analog-to-digital converter input pins must be properly configured
-//! to function correctly on DustDevil-class devices. This function provides
-//! the proper configuration for those pin(s).
-//!
-//! The pin(s) are specified using a bit-packed byte, where each bit that is
-//! set identifies the pin to be accessed, and where bit 0 of the byte
-//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
-//!
-//! \note This cannot be used to turn any pin into an ADC input; it only
-//! configures an ADC input pin for proper operation.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-GPIOPinTypeADC(unsigned long ulPort, unsigned char ucPins)
-{
- //
- // Check the arguments.
- //
- ASSERT(GPIOBaseValid(ulPort));
-
- //
- // Make the pin(s) be inputs.
- //
- GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_IN);
-
- //
- // Set the pad(s) for analog operation.
- //
- GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_ANALOG);
-
-}
-
-//*****************************************************************************
-//
-//! Configures pin(s) for use as a CAN device.
-//!
-//! \param ulPort is the base address of the GPIO port.
-//! \param ucPins is the bit-packed representation of the pin(s).
-//!
-//! The CAN pins must be properly configured for the CAN peripherals to
-//! function correctly. This function provides a typical configuration for
-//! those pin(s); other configurations may work as well depending upon the
-//! board setup (for example, using the on-chip pull-ups).
-//!
-//! The pin(s) are specified using a bit-packed byte, where each bit that is
-//! set identifies the pin to be accessed, and where bit 0 of the byte
-//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
-//!
-//! \note This cannot be used to turn any pin into a CAN pin; it only
-//! configures a CAN pin for proper operation.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-GPIOPinTypeCAN(unsigned long ulPort, unsigned char ucPins)
-{
- //
- // Check the arguments.
- //
- ASSERT(GPIOBaseValid(ulPort));
-
- //
- // Make the pin(s) be inputs.
- //
- GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW);
-
- //
- // Set the pad(s) for standard push-pull operation.
- //
- GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD);
-}
-
-//*****************************************************************************
-//
-//! Configures pin(s) for use as an analog comparator input.
-//!
-//! \param ulPort is the base address of the GPIO port.
-//! \param ucPins is the bit-packed representation of the pin(s).
-//!
-//! The analog comparator input pins must be properly configured for the analog
-//! comparator to function correctly. This function provides the proper
-//! configuration for those pin(s).
-//!
-//! The pin(s) are specified using a bit-packed byte, where each bit that is
-//! set identifies the pin to be accessed, and where bit 0 of the byte
-//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
-//!
-//! \note This cannot be used to turn any pin into an analog comparator input;
-//! it only configures an analog comparator pin for proper operation.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins)
-{
- //
- // Check the arguments.
- //
- ASSERT(GPIOBaseValid(ulPort));
-
- //
- // Make the pin(s) be inputs.
- //
- GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_IN);
-
- //
- // Set the pad(s) for analog operation.
- //
- GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_ANALOG);
-}
-
-//*****************************************************************************
-//
-//! Configures pin(s) for use as GPIO inputs.
-//!
-//! \param ulPort is the base address of the GPIO port.
-//! \param ucPins is the bit-packed representation of the pin(s).
-//!
-//! The GPIO pins must be properly configured in order to function correctly as
-//! GPIO inputs; this is especially true of Fury-class devices where the
-//! digital input enable is turned off by default. This function provides the
-//! proper configuration for those pin(s).
-//!
-//! The pin(s) are specified using a bit-packed byte, where each bit that is
-//! set identifies the pin to be accessed, and where bit 0 of the byte
-//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-GPIOPinTypeGPIOInput(unsigned long ulPort, unsigned char ucPins)
-{
- //
- // Check the arguments.
- //
- ASSERT(GPIOBaseValid(ulPort));
-
- //
- // Make the pin(s) be inputs.
- //
- GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_IN);
-
- //
- // Set the pad(s) for standard push-pull operation.
- //
- GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
-}
-
-//*****************************************************************************
-//
-//! Configures pin(s) for use as GPIO outputs.
-//!
-//! \param ulPort is the base address of the GPIO port.
-//! \param ucPins is the bit-packed representation of the pin(s).
-//!
-//! The GPIO pins must be properly configured in order to function correctly as
-//! GPIO outputs; this is especially true of Fury-class devices where the
-//! digital input enable is turned off by default. This function provides the
-//! proper configuration for those pin(s).
-//!
-//! The pin(s) are specified using a bit-packed byte, where each bit that is
-//! set identifies the pin to be accessed, and where bit 0 of the byte
-//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-GPIOPinTypeGPIOOutput(unsigned long ulPort, unsigned char ucPins)
-{
- //
- // Check the arguments.
- //
- ASSERT(GPIOBaseValid(ulPort));
-
- //
- // Make the pin(s) be outputs.
- //
- GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_OUT);
-
- //
- // Set the pad(s) for standard push-pull operation.
- //
- GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
-}
-
-//*****************************************************************************
-//
-//! Configures pin(s) for use as GPIO open drain outputs.
-//!
-//! \param ulPort is the base address of the GPIO port.
-//! \param ucPins is the bit-packed representation of the pin(s).
-//!
-//! The GPIO pins must be properly configured in order to function correctly as
-//! GPIO outputs; this is especially true of Fury-class devices where the
-//! digital input enable is turned off by default. This function provides the
-//! proper configuration for those pin(s).
-//!
-//! The pin(s) are specified using a bit-packed byte, where each bit that is
-//! set identifies the pin to be accessed, and where bit 0 of the byte
-//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-GPIOPinTypeGPIOOutputOD(unsigned long ulPort, unsigned char ucPins)
-{
- //
- // Check the arguments.
- //
- ASSERT(GPIOBaseValid(ulPort));
-
- //
- // Make the pin(s) be outputs.
- //
- GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_OUT);
-
- //
- // Set the pad(s) for standard push-pull operation.
- //
- GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_OD);
-}
-
-//*****************************************************************************
-//
-//! Configures pin(s) for use by the I2C peripheral.
-//!
-//! \param ulPort is the base address of the GPIO port.
-//! \param ucPins is the bit-packed representation of the pin(s).
-//!
-//! The I2C pins must be properly configured for the I2C peripheral to function
-//! correctly. This function provides the proper configuration for those
-//! pin(s).
-//!
-//! The pin(s) are specified using a bit-packed byte, where each bit that is
-//! set identifies the pin to be accessed, and where bit 0 of the byte
-//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
-//!
-//! \note This cannot be used to turn any pin into an I2C pin; it only
-//! configures an I2C pin for proper operation.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins)
-{
- //
- // Check the arguments.
- //
- ASSERT(GPIOBaseValid(ulPort));
-
- //
- // Make the pin(s) be peripheral controlled.
- //
- GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW);
-
- //
- // Set the pad(s) for open-drain operation with a weak pull-up.
- //
- GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_OD_WPU);
-}
-
-//*****************************************************************************
-//
-//! Configures pin(s) for use by the PWM peripheral.
-//!
-//! \param ulPort is the base address of the GPIO port.
-//! \param ucPins is the bit-packed representation of the pin(s).
-//!
-//! The PWM pins must be properly configured for the PWM peripheral to function
-//! correctly. This function provides a typical configuration for those
-//! pin(s); other configurations may work as well depending upon the board
-//! setup (for example, using the on-chip pull-ups).
-//!
-//! The pin(s) are specified using a bit-packed byte, where each bit that is
-//! set identifies the pin to be accessed, and where bit 0 of the byte
-//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
-//!
-//! \note This cannot be used to turn any pin into a PWM pin; it only
-//! configures a PWM pin for proper operation.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins)
-{
- //
- // Check the arguments.
- //
- ASSERT(GPIOBaseValid(ulPort));
-
- //
- // Make the pin(s) be peripheral controlled.
- //
- GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW);
-
- //
- // Set the pad(s) for standard push-pull operation.
- //
- GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
-}
-
-//*****************************************************************************
-//
-//! Configures pin(s) for use by the QEI peripheral.
-//!
-//! \param ulPort is the base address of the GPIO port.
-//! \param ucPins is the bit-packed representation of the pin(s).
-//!
-//! The QEI pins must be properly configured for the QEI peripheral to function
-//! correctly. This function provides a typical configuration for those
-//! pin(s); other configurations may work as well depending upon the board
-//! setup (for example, not using the on-chip pull-ups).
-//!
-//! The pin(s) are specified using a bit-packed byte, where each bit that is
-//! set identifies the pin to be accessed, and where bit 0 of the byte
-//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
-//!
-//! \note This cannot be used to turn any pin into a QEI pin; it only
-//! configures a QEI pin for proper operation.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins)
-{
- //
- // Check the arguments.
- //
- ASSERT(GPIOBaseValid(ulPort));
-
- //
- // Make the pin(s) be peripheral controlled.
- //
- GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW);
-
- //
- // Set the pad(s) for standard push-pull operation with a weak pull-up.
- //
- GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPU);
-}
-
-//*****************************************************************************
-//
-//! Configures pin(s) for use by the SSI peripheral.
-//!
-//! \param ulPort is the base address of the GPIO port.
-//! \param ucPins is the bit-packed representation of the pin(s).
-//!
-//! The SSI pins must be properly configured for the SSI peripheral to function
-//! correctly. This function provides a typical configuration for those
-//! pin(s); other configurations may work as well depending upon the board
-//! setup (for example, using the on-chip pull-ups).
-//!
-//! The pin(s) are specified using a bit-packed byte, where each bit that is
-//! set identifies the pin to be accessed, and where bit 0 of the byte
-//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
-//!
-//! \note This cannot be used to turn any pin into a SSI pin; it only
-//! configures a SSI pin for proper operation.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins)
-{
- //
- // Check the arguments.
- //
- ASSERT(GPIOBaseValid(ulPort));
-
- //
- // Make the pin(s) be peripheral controlled.
- //
- GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW);
-
- //
- // Set the pad(s) for standard push-pull operation.
- //
- GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
-}
-
-//*****************************************************************************
-//
-//! Configures pin(s) for use by the Timer peripheral.
-//!
-//! \param ulPort is the base address of the GPIO port.
-//! \param ucPins is the bit-packed representation of the pin(s).
-//!
-//! The CCP pins must be properly configured for the timer peripheral to
-//! function correctly. This function provides a typical configuration for
-//! those pin(s); other configurations may work as well depending upon the
-//! board setup (for example, using the on-chip pull-ups).
-//!
-//! The pin(s) are specified using a bit-packed byte, where each bit that is
-//! set identifies the pin to be accessed, and where bit 0 of the byte
-//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
-//!
-//! \note This cannot be used to turn any pin into a timer pin; it only
-//! configures a timer pin for proper operation.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins)
-{
- //
- // Check the arguments.
- //
- ASSERT(GPIOBaseValid(ulPort));
-
- //
- // Make the pin(s) be peripheral controlled.
- //
- GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW);
-
- //
- // Set the pad(s) for standard push-pull operation.
- //
- GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
-}
-
-//*****************************************************************************
-//
-//! Configures pin(s) for use by the UART peripheral.
-//!
-//! \param ulPort is the base address of the GPIO port.
-//! \param ucPins is the bit-packed representation of the pin(s).
-//!
-//! The UART pins must be properly configured for the UART peripheral to
-//! function correctly. This function provides a typical configuration for
-//! those pin(s); other configurations may work as well depending upon the
-//! board setup (for example, using the on-chip pull-ups).
-//!
-//! The pin(s) are specified using a bit-packed byte, where each bit that is
-//! set identifies the pin to be accessed, and where bit 0 of the byte
-//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
-//!
-//! \note This cannot be used to turn any pin into a UART pin; it only
-//! configures a UART pin for proper operation.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins)
-{
- //
- // Check the arguments.
- //
- ASSERT(GPIOBaseValid(ulPort));
-
- //
- // Make the pin(s) be peripheral controlled.
- //
- GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW);
-
- //
- // Set the pad(s) for standard push-pull operation.
- //
- GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
-}
-
-//*****************************************************************************
-//
-//! Configures pin(s) for use by the USB peripheral.
-//!
-//! \param ulPort is the base address of the USB port.
-//! \param ucPins is the bit-packed representation of the pin(s).
-//!
-//! Some USB pins must be properly configured for the USB peripheral to
-//! function correctly. This function provides a typical configuration for
-//! the digital USB pin(s); other configurations may work as well depending
-//! upon the board setup (for example, using the on-chip pull-ups).
-//!
-//! The pin(s) are specified using a bit-packed byte, where each bit that is
-//! set identifies the pin to be accessed, and where bit 0 of the byte
-//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
-//!
-//! \note This cannot be used to turn any pin into a USB pin; it only
-//! configures a USB pin for proper operation.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-GPIOPinTypeUSBDigital(unsigned long ulPort, unsigned char ucPins)
-{
- //
- // Check the arguments.
- //
- ASSERT(GPIOBaseValid(ulPort));
-
- //
- // Make the pin(s) be peripheral controlled.
- //
- GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW);
-
- //
- // Set the pad(s) for standard push-pull operation.
- //
- GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
-}
-
-//*****************************************************************************
-//
-// Close the Doxygen group.
-//! @}
-//
-//*****************************************************************************
+//*****************************************************************************
+//
+// gpio.c - API for GPIO ports
+//
+// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup gpio_api
+//! @{
+//
+//*****************************************************************************
+
+#include "hw_gpio.h"
+#include "hw_ints.h"
+#include "hw_memmap.h"
+#include "hw_sysctl.h"
+#include "hw_types.h"
+#include "debug.h"
+#include "gpio.h"
+#include "interrupt.h"
+
+//*****************************************************************************
+//
+// The base addresses of all the GPIO modules. Both the APB and AHB apertures
+// are provided.
+//
+//*****************************************************************************
+static const unsigned long g_pulGPIOBaseAddrs[] =
+{
+ GPIO_PORTA_BASE, GPIO_PORTA_AHB_BASE,
+ GPIO_PORTB_BASE, GPIO_PORTB_AHB_BASE,
+ GPIO_PORTC_BASE, GPIO_PORTC_AHB_BASE,
+ GPIO_PORTD_BASE, GPIO_PORTD_AHB_BASE,
+ GPIO_PORTE_BASE, GPIO_PORTE_AHB_BASE,
+ GPIO_PORTF_BASE, GPIO_PORTF_AHB_BASE,
+ GPIO_PORTG_BASE, GPIO_PORTG_AHB_BASE,
+ GPIO_PORTH_BASE, GPIO_PORTH_AHB_BASE,
+ GPIO_PORTJ_BASE, GPIO_PORTJ_AHB_BASE,
+};
+
+//*****************************************************************************
+//
+//! \internal
+//! Checks a GPIO base address.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//!
+//! This function determines if a GPIO port base address is valid.
+//!
+//! \return Returns \b true if the base address is valid and \b false
+//! otherwise.
+//
+//*****************************************************************************
+#ifdef DEBUG
+static tBoolean
+GPIOBaseValid(unsigned long ulPort)
+{
+ return((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTA_AHB_BASE) ||
+ (ulPort == GPIO_PORTB_BASE) || (ulPort == GPIO_PORTB_AHB_BASE) ||
+ (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTC_AHB_BASE) ||
+ (ulPort == GPIO_PORTD_BASE) || (ulPort == GPIO_PORTD_AHB_BASE) ||
+ (ulPort == GPIO_PORTE_BASE) || (ulPort == GPIO_PORTE_AHB_BASE) ||
+ (ulPort == GPIO_PORTF_BASE) || (ulPort == GPIO_PORTF_AHB_BASE) ||
+ (ulPort == GPIO_PORTG_BASE) || (ulPort == GPIO_PORTG_AHB_BASE) ||
+ (ulPort == GPIO_PORTH_BASE) || (ulPort == GPIO_PORTH_AHB_BASE) ||
+ (ulPort == GPIO_PORTJ_BASE) || (ulPort == GPIO_PORTJ_AHB_BASE));
+}
+#endif
+
+//*****************************************************************************
+//
+//! \internal
+//! Gets the GPIO interrupt number.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//!
+//! Given a GPIO base address, returns the corresponding interrupt number.
+//!
+//! \return Returns a GPIO interrupt number, or -1 if \e ulPort is invalid.
+//
+//*****************************************************************************
+static long
+GPIOGetIntNumber(unsigned long ulPort)
+{
+ unsigned int ulInt;
+
+ //
+ // Determine the GPIO interrupt number for the given module.
+ //
+ switch(ulPort)
+ {
+ case GPIO_PORTA_BASE:
+ case GPIO_PORTA_AHB_BASE:
+ {
+ ulInt = INT_GPIOA;
+ break;
+ }
+
+ case GPIO_PORTB_BASE:
+ case GPIO_PORTB_AHB_BASE:
+ {
+ ulInt = INT_GPIOB;
+ break;
+ }
+
+ case GPIO_PORTC_BASE:
+ case GPIO_PORTC_AHB_BASE:
+ {
+ ulInt = INT_GPIOC;
+ break;
+ }
+
+ case GPIO_PORTD_BASE:
+ case GPIO_PORTD_AHB_BASE:
+ {
+ ulInt = INT_GPIOD;
+ break;
+ }
+
+ case GPIO_PORTE_BASE:
+ case GPIO_PORTE_AHB_BASE:
+ {
+ ulInt = INT_GPIOE;
+ break;
+ }
+
+ case GPIO_PORTF_BASE:
+ case GPIO_PORTF_AHB_BASE:
+ {
+ ulInt = INT_GPIOF;
+ break;
+ }
+
+ case GPIO_PORTG_BASE:
+ case GPIO_PORTG_AHB_BASE:
+ {
+ ulInt = INT_GPIOG;
+ break;
+ }
+
+ case GPIO_PORTH_BASE:
+ case GPIO_PORTH_AHB_BASE:
+ {
+ ulInt = INT_GPIOH;
+ break;
+ }
+
+ case GPIO_PORTJ_BASE:
+ case GPIO_PORTJ_AHB_BASE:
+ {
+ ulInt = INT_GPIOJ;
+ break;
+ }
+
+ default:
+ {
+ return(-1);
+ }
+ }
+
+ //
+ // Return GPIO interrupt number.
+ //
+ return(ulInt);
+}
+
+//*****************************************************************************
+//
+//! Sets the direction and mode of the specified pin(s).
+//!
+//! \param ulPort is the base address of the GPIO port
+//! \param ucPins is the bit-packed representation of the pin(s).
+//! \param ulPinIO is the pin direction and/or mode.
+//!
+//! This function will set the specified pin(s) on the selected GPIO port
+//! as either an input or output under software control, or it will set the
+//! pin to be under hardware control.
+//!
+//! The parameter \e ulPinIO is an enumerated data type that can be one of
+//! the following values:
+//!
+//! - \b GPIO_DIR_MODE_IN
+//! - \b GPIO_DIR_MODE_OUT
+//! - \b GPIO_DIR_MODE_HW
+//!
+//! where \b GPIO_DIR_MODE_IN specifies that the pin will be programmed as
+//! a software controlled input, \b GPIO_DIR_MODE_OUT specifies that the pin
+//! will be programmed as a software controlled output, and
+//! \b GPIO_DIR_MODE_HW specifies that the pin will be placed under
+//! hardware control.
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIODirModeSet(unsigned long ulPort, unsigned char ucPins,
+ unsigned long ulPinIO)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+ ASSERT((ulPinIO == GPIO_DIR_MODE_IN) || (ulPinIO == GPIO_DIR_MODE_OUT) ||
+ (ulPinIO == GPIO_DIR_MODE_HW));
+
+ //
+ // Set the pin direction and mode.
+ //
+ HWREG(ulPort + GPIO_O_DIR) = ((ulPinIO & 1) ?
+ (HWREG(ulPort + GPIO_O_DIR) | ucPins) :
+ (HWREG(ulPort + GPIO_O_DIR) & ~(ucPins)));
+ HWREG(ulPort + GPIO_O_AFSEL) = ((ulPinIO & 2) ?
+ (HWREG(ulPort + GPIO_O_AFSEL) | ucPins) :
+ (HWREG(ulPort + GPIO_O_AFSEL) &
+ ~(ucPins)));
+}
+
+//*****************************************************************************
+//
+//! Gets the direction and mode of a pin.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPin is the pin number.
+//!
+//! This function gets the direction and control mode for a specified pin on
+//! the selected GPIO port. The pin can be configured as either an input or
+//! output under software control, or it can be under hardware control. The
+//! type of control and direction are returned as an enumerated data type.
+//!
+//! \return Returns one of the enumerated data types described for
+//! GPIODirModeSet().
+//
+//*****************************************************************************
+unsigned long
+GPIODirModeGet(unsigned long ulPort, unsigned char ucPin)
+{
+ unsigned long ulDir, ulAFSEL;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+ ASSERT(ucPin < 8);
+
+ //
+ // Convert from a pin number to a bit position.
+ //
+ ucPin = 1 << ucPin;
+
+ //
+ // Return the pin direction and mode.
+ //
+ ulDir = HWREG(ulPort + GPIO_O_DIR);
+ ulAFSEL = HWREG(ulPort + GPIO_O_AFSEL);
+ return(((ulDir & ucPin) ? 1 : 0) | ((ulAFSEL & ucPin) ? 2 : 0));
+}
+
+//*****************************************************************************
+//
+//! Sets the interrupt type for the specified pin(s).
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//! \param ulIntType specifies the type of interrupt trigger mechanism.
+//!
+//! This function sets up the various interrupt trigger mechanisms for the
+//! specified pin(s) on the selected GPIO port.
+//!
+//! The parameter \e ulIntType is an enumerated data type that can be one of
+//! the following values:
+//!
+//! - \b GPIO_FALLING_EDGE
+//! - \b GPIO_RISING_EDGE
+//! - \b GPIO_BOTH_EDGES
+//! - \b GPIO_LOW_LEVEL
+//! - \b GPIO_HIGH_LEVEL
+//!
+//! where the different values describe the interrupt detection mechanism
+//! (edge or level) and the particular triggering event (falling, rising,
+//! or both edges for edge detect, low or high for level detect).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note In order to avoid any spurious interrupts, the user must
+//! ensure that the GPIO inputs remain stable for the duration of
+//! this function.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins,
+ unsigned long ulIntType)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+ ASSERT((ulIntType == GPIO_FALLING_EDGE) ||
+ (ulIntType == GPIO_RISING_EDGE) || (ulIntType == GPIO_BOTH_EDGES) ||
+ (ulIntType == GPIO_LOW_LEVEL) || (ulIntType == GPIO_HIGH_LEVEL));
+
+ //
+ // Set the pin interrupt type.
+ //
+ HWREG(ulPort + GPIO_O_IBE) = ((ulIntType & 1) ?
+ (HWREG(ulPort + GPIO_O_IBE) | ucPins) :
+ (HWREG(ulPort + GPIO_O_IBE) & ~(ucPins)));
+ HWREG(ulPort + GPIO_O_IS) = ((ulIntType & 2) ?
+ (HWREG(ulPort + GPIO_O_IS) | ucPins) :
+ (HWREG(ulPort + GPIO_O_IS) & ~(ucPins)));
+ HWREG(ulPort + GPIO_O_IEV) = ((ulIntType & 4) ?
+ (HWREG(ulPort + GPIO_O_IEV) | ucPins) :
+ (HWREG(ulPort + GPIO_O_IEV) & ~(ucPins)));
+}
+
+//*****************************************************************************
+//
+//! Gets the interrupt type for a pin.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPin is the pin number.
+//!
+//! This function gets the interrupt type for a specified pin on the selected
+//! GPIO port. The pin can be configured as a falling edge, rising edge, or
+//! both edge detected interrupt, or it can be configured as a low level or
+//! high level detected interrupt. The type of interrupt detection mechanism
+//! is returned as an enumerated data type.
+//!
+//! \return Returns one of the enumerated data types described for
+//! GPIOIntTypeSet().
+//
+//*****************************************************************************
+unsigned long
+GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin)
+{
+ unsigned long ulIBE, ulIS, ulIEV;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+ ASSERT(ucPin < 8);
+
+ //
+ // Convert from a pin number to a bit position.
+ //
+ ucPin = 1 << ucPin;
+
+ //
+ // Return the pin interrupt type.
+ //
+ ulIBE = HWREG(ulPort + GPIO_O_IBE);
+ ulIS = HWREG(ulPort + GPIO_O_IS);
+ ulIEV = HWREG(ulPort + GPIO_O_IEV);
+ return(((ulIBE & ucPin) ? 1 : 0) | ((ulIS & ucPin) ? 2 : 0) |
+ ((ulIEV & ucPin) ? 4 : 0));
+}
+
+//*****************************************************************************
+//
+//! Sets the pad configuration for the specified pin(s).
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//! \param ulStrength specifies the output drive strength.
+//! \param ulPinType specifies the pin type.
+//!
+//! This function sets the drive strength and type for the specified pin(s)
+//! on the selected GPIO port. For pin(s) configured as input ports, the
+//! pad is configured as requested, but the only real effect on the input
+//! is the configuration of the pull-up or pull-down termination.
+//!
+//! The parameter \e ulStrength can be one of the following values:
+//!
+//! - \b GPIO_STRENGTH_2MA
+//! - \b GPIO_STRENGTH_4MA
+//! - \b GPIO_STRENGTH_8MA
+//! - \b GPIO_STRENGTH_8MA_SC
+//!
+//! where \b GPIO_STRENGTH_xMA specifies either 2, 4, or 8 mA output drive
+//! strength, and \b GPIO_OUT_STRENGTH_8MA_SC specifies 8 mA output drive with
+//! slew control.
+//!
+//! The parameter \e ulPinType can be one of the following values:
+//!
+//! - \b GPIO_PIN_TYPE_STD
+//! - \b GPIO_PIN_TYPE_STD_WPU
+//! - \b GPIO_PIN_TYPE_STD_WPD
+//! - \b GPIO_PIN_TYPE_OD
+//! - \b GPIO_PIN_TYPE_OD_WPU
+//! - \b GPIO_PIN_TYPE_OD_WPD
+//! - \b GPIO_PIN_TYPE_ANALOG
+//!
+//! where \b GPIO_PIN_TYPE_STD* specifies a push-pull pin, \b GPIO_PIN_TYPE_OD*
+//! specifies an open-drain pin, \b *_WPU specifies a weak pull-up, \b *_WPD
+//! specifies a weak pull-down, and \b GPIO_PIN_TYPE_ANALOG specifies an
+//! analog input (for the comparators).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins,
+ unsigned long ulStrength, unsigned long ulPinType)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+ ASSERT((ulStrength == GPIO_STRENGTH_2MA) ||
+ (ulStrength == GPIO_STRENGTH_4MA) ||
+ (ulStrength == GPIO_STRENGTH_8MA) ||
+ (ulStrength == GPIO_STRENGTH_8MA_SC));
+ ASSERT((ulPinType == GPIO_PIN_TYPE_STD) ||
+ (ulPinType == GPIO_PIN_TYPE_STD_WPU) ||
+ (ulPinType == GPIO_PIN_TYPE_STD_WPD) ||
+ (ulPinType == GPIO_PIN_TYPE_OD) ||
+ (ulPinType == GPIO_PIN_TYPE_OD_WPU) ||
+ (ulPinType == GPIO_PIN_TYPE_OD_WPD) ||
+ (ulPinType == GPIO_PIN_TYPE_ANALOG))
+
+ //
+ // Set the output drive strength.
+ //
+ HWREG(ulPort + GPIO_O_DR2R) = ((ulStrength & 1) ?
+ (HWREG(ulPort + GPIO_O_DR2R) | ucPins) :
+ (HWREG(ulPort + GPIO_O_DR2R) & ~(ucPins)));
+ HWREG(ulPort + GPIO_O_DR4R) = ((ulStrength & 2) ?
+ (HWREG(ulPort + GPIO_O_DR4R) | ucPins) :
+ (HWREG(ulPort + GPIO_O_DR4R) & ~(ucPins)));
+ HWREG(ulPort + GPIO_O_DR8R) = ((ulStrength & 4) ?
+ (HWREG(ulPort + GPIO_O_DR8R) | ucPins) :
+ (HWREG(ulPort + GPIO_O_DR8R) & ~(ucPins)));
+ HWREG(ulPort + GPIO_O_SLR) = ((ulStrength & 8) ?
+ (HWREG(ulPort + GPIO_O_SLR) | ucPins) :
+ (HWREG(ulPort + GPIO_O_SLR) & ~(ucPins)));
+
+ //
+ // Set the pin type.
+ //
+ HWREG(ulPort + GPIO_O_ODR) = ((ulPinType & 1) ?
+ (HWREG(ulPort + GPIO_O_ODR) | ucPins) :
+ (HWREG(ulPort + GPIO_O_ODR) & ~(ucPins)));
+ HWREG(ulPort + GPIO_O_PUR) = ((ulPinType & 2) ?
+ (HWREG(ulPort + GPIO_O_PUR) | ucPins) :
+ (HWREG(ulPort + GPIO_O_PUR) & ~(ucPins)));
+ HWREG(ulPort + GPIO_O_PDR) = ((ulPinType & 4) ?
+ (HWREG(ulPort + GPIO_O_PDR) | ucPins) :
+ (HWREG(ulPort + GPIO_O_PDR) & ~(ucPins)));
+ HWREG(ulPort + GPIO_O_DEN) = ((ulPinType & 8) ?
+ (HWREG(ulPort + GPIO_O_DEN) | ucPins) :
+ (HWREG(ulPort + GPIO_O_DEN) & ~(ucPins)));
+
+ //
+ // Set the analog mode select register. This register only appears in
+ // DustDevil-class (and later) devices, but is a harmless write on
+ // Sandstorm- and Fury-class devices.
+ //
+ HWREG(ulPort + GPIO_O_AMSEL) =
+ ((ulPinType == GPIO_PIN_TYPE_ANALOG) ?
+ (HWREG(ulPort + GPIO_O_AMSEL) | ucPins) :
+ (HWREG(ulPort + GPIO_O_AMSEL) & ~(ucPins)));
+}
+
+//*****************************************************************************
+//
+//! Gets the pad configuration for a pin.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPin is the pin number.
+//! \param pulStrength is a pointer to storage for the output drive strength.
+//! \param pulPinType is a pointer to storage for the output drive type.
+//!
+//! This function gets the pad configuration for a specified pin on the
+//! selected GPIO port. The values returned in \e pulStrength and
+//! \e pulPinType correspond to the values used in GPIOPadConfigSet(). This
+//! function also works for pin(s) configured as input pin(s); however, the
+//! only meaningful data returned is whether the pin is terminated with a
+//! pull-up or down resistor.
+//!
+//! \return None
+//
+//*****************************************************************************
+void
+GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin,
+ unsigned long *pulStrength, unsigned long *pulPinType)
+{
+ unsigned long ulTemp1, ulTemp2, ulTemp3, ulTemp4;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+ ASSERT(ucPin < 8);
+
+ //
+ // Convert from a pin number to a bit position.
+ //
+ ucPin = (1 << ucPin);
+
+ //
+ // Get the drive strength for this pin.
+ //
+ ulTemp1 = HWREG(ulPort + GPIO_O_DR2R);
+ ulTemp2 = HWREG(ulPort + GPIO_O_DR4R);
+ ulTemp3 = HWREG(ulPort + GPIO_O_DR8R);
+ ulTemp4 = HWREG(ulPort + GPIO_O_SLR);
+ *pulStrength = (((ulTemp1 & ucPin) ? 1 : 0) | ((ulTemp2 & ucPin) ? 2 : 0) |
+ ((ulTemp3 & ucPin) ? 4 : 0) | ((ulTemp4 & ucPin) ? 8 : 0));
+
+ //
+ // Get the pin type.
+ //
+ ulTemp1 = HWREG(ulPort + GPIO_O_ODR);
+ ulTemp2 = HWREG(ulPort + GPIO_O_PUR);
+ ulTemp3 = HWREG(ulPort + GPIO_O_PDR);
+ ulTemp4 = HWREG(ulPort + GPIO_O_DEN);
+ *pulPinType = (((ulTemp1 & ucPin) ? 1 : 0) | ((ulTemp2 & ucPin) ? 2 : 0) |
+ ((ulTemp3 & ucPin) ? 4 : 0) | ((ulTemp4 & ucPin) ? 8 : 0));
+}
+
+//*****************************************************************************
+//
+//! Enables interrupts for the specified pin(s).
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! Unmasks the interrupt for the specified pin(s).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Enable the interrupts.
+ //
+ HWREG(ulPort + GPIO_O_IM) |= ucPins;
+}
+
+//*****************************************************************************
+//
+//! Disables interrupts for the specified pin(s).
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! Masks the interrupt for the specified pin(s).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Disable the interrupts.
+ //
+ HWREG(ulPort + GPIO_O_IM) &= ~(ucPins);
+}
+
+//*****************************************************************************
+//
+//! Gets interrupt status for the specified GPIO port.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param bMasked specifies whether masked or raw interrupt status is
+//! returned.
+//!
+//! If \e bMasked is set as \b true, then the masked interrupt status is
+//! returned; otherwise, the raw interrupt status will be returned.
+//!
+//! \return Returns a bit-packed byte, where each bit that is set identifies
+//! an active masked or raw interrupt, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//! Bits 31:8 should be ignored.
+//
+//*****************************************************************************
+long
+GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Return the interrupt status.
+ //
+ if(bMasked)
+ {
+ return(HWREG(ulPort + GPIO_O_MIS));
+ }
+ else
+ {
+ return(HWREG(ulPort + GPIO_O_RIS));
+ }
+}
+
+//*****************************************************************************
+//
+//! Clears the interrupt for the specified pin(s).
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! Clears the interrupt for the specified pin(s).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
+//! several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared. Failure to do so may result in the interrupt handler
+//! being immediately reentered (since NVIC still sees the interrupt source
+//! asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Clear the interrupts.
+ //
+ HWREG(ulPort + GPIO_O_ICR) = ucPins;
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for a GPIO port.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param pfnIntHandler is a pointer to the GPIO port interrupt handling
+//! function.
+//!
+//! This function will ensure that the interrupt handler specified by
+//! \e pfnIntHandler is called when an interrupt is detected from the selected
+//! GPIO port. This function will also enable the corresponding GPIO interrupt
+//! in the interrupt controller; individual pin interrupts and interrupt
+//! sources must be enabled with GPIOPinIntEnable().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPortIntRegister(unsigned long ulPort, void (*pfnIntHandler)(void))
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Get the interrupt number associated with the specified GPIO.
+ //
+ ulPort = GPIOGetIntNumber(ulPort);
+
+ //
+ // Register the interrupt handler.
+ //
+ IntRegister(ulPort, pfnIntHandler);
+
+ //
+ // Enable the GPIO interrupt.
+ //
+ IntEnable(ulPort);
+}
+
+//*****************************************************************************
+//
+//! Removes an interrupt handler for a GPIO port.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//!
+//! This function will unregister the interrupt handler for the specified
+//! GPIO port. This function will also disable the corresponding
+//! GPIO port interrupt in the interrupt controller; individual GPIO interrupts
+//! and interrupt sources must be disabled with GPIOPinIntDisable().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPortIntUnregister(unsigned long ulPort)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Get the interrupt number associated with the specified GPIO.
+ //
+ ulPort = GPIOGetIntNumber(ulPort);
+
+ //
+ // Disable the GPIO interrupt.
+ //
+ IntDisable(ulPort);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(ulPort);
+}
+
+//*****************************************************************************
+//
+//! Reads the values present of the specified pin(s).
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! The values at the specified pin(s) are read, as specified by \e ucPins.
+//! Values are returned for both input and output pin(s), and the value
+//! for pin(s) that are not specified by \e ucPins are set to 0.
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \return Returns a bit-packed byte providing the state of the specified
+//! pin, where bit 0 of the byte represents GPIO port pin 0, bit 1 represents
+//! GPIO port pin 1, and so on. Any bit that is not specified by \e ucPins
+//! is returned as a 0. Bits 31:8 should be ignored.
+//
+//*****************************************************************************
+long
+GPIOPinRead(unsigned long ulPort, unsigned char ucPins)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Return the pin value(s).
+ //
+ return(HWREG(ulPort + (GPIO_O_DATA + (ucPins << 2))));
+}
+
+//*****************************************************************************
+//
+//! Writes a value to the specified pin(s).
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//! \param ucVal is the value to write to the pin(s).
+//!
+//! Writes the corresponding bit values to the output pin(s) specified by
+//! \e ucPins. Writing to a pin configured as an input pin has no effect.
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinWrite(unsigned long ulPort, unsigned char ucPins, unsigned char ucVal)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Write the pins.
+ //
+ HWREG(ulPort + (GPIO_O_DATA + (ucPins << 2))) = ucVal;
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use as analog-to-digital converter inputs.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! The analog-to-digital converter input pins must be properly configured
+//! to function correctly on DustDevil-class devices. This function provides
+//! the proper configuration for those pin(s).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This cannot be used to turn any pin into an ADC input; it only
+//! configures an ADC input pin for proper operation.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeADC(unsigned long ulPort, unsigned char ucPins)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Make the pin(s) be inputs.
+ //
+ GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_IN);
+
+ //
+ // Set the pad(s) for analog operation.
+ //
+ GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_ANALOG);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use as a CAN device.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! The CAN pins must be properly configured for the CAN peripherals to
+//! function correctly. This function provides a typical configuration for
+//! those pin(s); other configurations may work as well depending upon the
+//! board setup (for example, using the on-chip pull-ups).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This cannot be used to turn any pin into a CAN pin; it only
+//! configures a CAN pin for proper operation.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeCAN(unsigned long ulPort, unsigned char ucPins)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Make the pin(s) be inputs.
+ //
+ GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW);
+
+ //
+ // Set the pad(s) for standard push-pull operation.
+ //
+ GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use as an analog comparator input.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! The analog comparator input pins must be properly configured for the analog
+//! comparator to function correctly. This function provides the proper
+//! configuration for those pin(s).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This cannot be used to turn any pin into an analog comparator input;
+//! it only configures an analog comparator pin for proper operation.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Make the pin(s) be inputs.
+ //
+ GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_IN);
+
+ //
+ // Set the pad(s) for analog operation.
+ //
+ GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_ANALOG);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use as GPIO inputs.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! The GPIO pins must be properly configured in order to function correctly as
+//! GPIO inputs; this is especially true of Fury-class devices where the
+//! digital input enable is turned off by default. This function provides the
+//! proper configuration for those pin(s).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeGPIOInput(unsigned long ulPort, unsigned char ucPins)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Make the pin(s) be inputs.
+ //
+ GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_IN);
+
+ //
+ // Set the pad(s) for standard push-pull operation.
+ //
+ GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use as GPIO outputs.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! The GPIO pins must be properly configured in order to function correctly as
+//! GPIO outputs; this is especially true of Fury-class devices where the
+//! digital input enable is turned off by default. This function provides the
+//! proper configuration for those pin(s).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeGPIOOutput(unsigned long ulPort, unsigned char ucPins)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Make the pin(s) be outputs.
+ //
+ GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_OUT);
+
+ //
+ // Set the pad(s) for standard push-pull operation.
+ //
+ GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use as GPIO open drain outputs.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! The GPIO pins must be properly configured in order to function correctly as
+//! GPIO outputs; this is especially true of Fury-class devices where the
+//! digital input enable is turned off by default. This function provides the
+//! proper configuration for those pin(s).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeGPIOOutputOD(unsigned long ulPort, unsigned char ucPins)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Make the pin(s) be outputs.
+ //
+ GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_OUT);
+
+ //
+ // Set the pad(s) for standard push-pull operation.
+ //
+ GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_OD);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use by the I2C peripheral.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! The I2C pins must be properly configured for the I2C peripheral to function
+//! correctly. This function provides the proper configuration for those
+//! pin(s).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This cannot be used to turn any pin into an I2C pin; it only
+//! configures an I2C pin for proper operation.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Make the pin(s) be peripheral controlled.
+ //
+ GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW);
+
+ //
+ // Set the pad(s) for open-drain operation with a weak pull-up.
+ //
+ GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_OD_WPU);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use by the PWM peripheral.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! The PWM pins must be properly configured for the PWM peripheral to function
+//! correctly. This function provides a typical configuration for those
+//! pin(s); other configurations may work as well depending upon the board
+//! setup (for example, using the on-chip pull-ups).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This cannot be used to turn any pin into a PWM pin; it only
+//! configures a PWM pin for proper operation.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Make the pin(s) be peripheral controlled.
+ //
+ GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW);
+
+ //
+ // Set the pad(s) for standard push-pull operation.
+ //
+ GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use by the QEI peripheral.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! The QEI pins must be properly configured for the QEI peripheral to function
+//! correctly. This function provides a typical configuration for those
+//! pin(s); other configurations may work as well depending upon the board
+//! setup (for example, not using the on-chip pull-ups).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This cannot be used to turn any pin into a QEI pin; it only
+//! configures a QEI pin for proper operation.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Make the pin(s) be peripheral controlled.
+ //
+ GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW);
+
+ //
+ // Set the pad(s) for standard push-pull operation with a weak pull-up.
+ //
+ GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPU);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use by the SSI peripheral.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! The SSI pins must be properly configured for the SSI peripheral to function
+//! correctly. This function provides a typical configuration for those
+//! pin(s); other configurations may work as well depending upon the board
+//! setup (for example, using the on-chip pull-ups).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This cannot be used to turn any pin into a SSI pin; it only
+//! configures a SSI pin for proper operation.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Make the pin(s) be peripheral controlled.
+ //
+ GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW);
+
+ //
+ // Set the pad(s) for standard push-pull operation.
+ //
+ GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use by the Timer peripheral.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! The CCP pins must be properly configured for the timer peripheral to
+//! function correctly. This function provides a typical configuration for
+//! those pin(s); other configurations may work as well depending upon the
+//! board setup (for example, using the on-chip pull-ups).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This cannot be used to turn any pin into a timer pin; it only
+//! configures a timer pin for proper operation.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Make the pin(s) be peripheral controlled.
+ //
+ GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW);
+
+ //
+ // Set the pad(s) for standard push-pull operation.
+ //
+ GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use by the UART peripheral.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! The UART pins must be properly configured for the UART peripheral to
+//! function correctly. This function provides a typical configuration for
+//! those pin(s); other configurations may work as well depending upon the
+//! board setup (for example, using the on-chip pull-ups).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This cannot be used to turn any pin into a UART pin; it only
+//! configures a UART pin for proper operation.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Make the pin(s) be peripheral controlled.
+ //
+ GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW);
+
+ //
+ // Set the pad(s) for standard push-pull operation.
+ //
+ GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use by the USB peripheral.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! Some USB digital pins must be properly configured for the USB peripheral to
+//! function correctly. This function provides a typical configuration for
+//! the digital USB pin(s); other configurations may work as well depending
+//! upon the board setup (for example, using the on-chip pull-ups).
+//!
+//! This function should only be used with EPEN and PFAULT pins as all other
+//! USB pins are analog in nature or are not used in devices without OTG
+//! functionality.
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This cannot be used to turn any pin into a USB pin; it only
+//! configures a USB pin for proper operation.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeUSBDigital(unsigned long ulPort, unsigned char ucPins)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Make the pin(s) be peripheral controlled.
+ //
+ GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW);
+
+ //
+ // Set the pad(s) for standard push-pull operation.
+ //
+ GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use by the USB peripheral.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! Some USB analog pins must be properly configured for the USB peripheral to
+//! function correctly. This function provides the proper configuration for
+//! any USB pin(s). This can also be used to configure the EPEN and PFAULT pins
+//! so that they are no longer used by the USB controller.
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This cannot be used to turn any pin into a USB pin; it only
+//! configures a USB pin for proper operation.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeUSBAnalog(unsigned long ulPort, unsigned char ucPins)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Make the pin(s) be inputs.
+ //
+ GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_IN);
+
+ //
+ // Set the pad(s) for analog operation.
+ //
+ GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_ANALOG);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use by the I2S peripheral.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! Some I2S pins must be properly configured for the I2S peripheral to
+//! function correctly. This function provides a typical configuration for
+//! the digital I2S pin(s); other configurations may work as well depending
+//! upon the board setup (for example, using the on-chip pull-ups).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This cannot be used to turn any pin into a I2S pin; it only
+//! configures a I2S pin for proper operation.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeI2S(unsigned long ulPort, unsigned char ucPins)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Make the pin(s) be peripheral controlled.
+ //
+ GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW);
+
+ //
+ // Set the pad(s) for standard push-pull operation.
+ //
+ GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
+}
+
+//*****************************************************************************
+//
+//! Configures the alternate function of a GPIO pin.
+//!
+//! \param ulPinConfig is the pin configuration value, specified as one of the
+//! \b GPIO_P??_??? values.
+//!
+//! This function configures the pin mux that selects the peripheral function
+//! associated with a particular GPIO pin. Only one peripheral function at a
+//! time can be associated with a GPIO pin, and each peripheral function should
+//! only be associated with a single GPIO pin at a time (despite the fact that
+//! many of them can be associated with more than one GPIO pin).
+//!
+//! \note This function is only valid on Tempest-class devices.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinConfigure(unsigned long ulPinConfig)
+{
+ unsigned long ulBase, ulShift;
+
+ //
+ // Check the argument.
+ //
+ ASSERT(((ulPinConfig >> 16) & 0xff) < 9);
+ ASSERT(((ulPinConfig >> 8) & 0xe3) == 0);
+
+ //
+ // Extract the base address index from the input value.
+ //
+ ulBase = (ulPinConfig >> 16) & 0xff;
+
+ //
+ // Get the base address of the GPIO module, selecting either the APB or the
+ // AHB aperture as appropriate.
+ //
+ if(HWREG(SYSCTL_GPIOHSCTL) & (1 << ulBase))
+ {
+ ulBase = g_pulGPIOBaseAddrs[(ulBase << 1) + 1];
+ }
+ else
+ {
+ ulBase = g_pulGPIOBaseAddrs[ulBase << 1];
+ }
+
+ //
+ // Extract the shift from the input value.
+ //
+ ulShift = (ulPinConfig >> 8) & 0xff;
+
+ //
+ // Write the requested pin muxing value for this GPIO pin.
+ //
+ HWREG(ulBase + GPIO_O_PCTL) = ((HWREG(ulBase + GPIO_O_PCTL) &
+ ~(0xf << ulShift)) |
+ ((ulPinConfig & 0xf) << ulShift));
+
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
Property changes on: branches/eagle_mmc/src/platform/lm3s/gpio.c
___________________________________________________________________
Name: svn:executable
+ *
Modified: branches/eagle_mmc/src/platform/lm3s/gpio.h
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/gpio.h 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lm3s/gpio.h 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,155 +1,768 @@
-//*****************************************************************************
-//
-// gpio.h - Defines and Macros for GPIO API.
-//
-// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
-// Software License Agreement
-//
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
-//
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws. All rights are reserved. You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program. Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
-//
-// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-//
-// This is part of revision 3740 of the Stellaris Peripheral Driver Library.
-//
-//*****************************************************************************
-
-#ifndef __GPIO_H__
-#define __GPIO_H__
-
-//*****************************************************************************
-//
-// If building with a C++ compiler, make all of the definitions in this header
-// have a C binding.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-//*****************************************************************************
-//
-// The following values define the bit field for the ucPins argument to several
-// of the APIs.
-//
-//*****************************************************************************
-#define GPIO_PIN_0 0x00000001 // GPIO pin 0
-#define GPIO_PIN_1 0x00000002 // GPIO pin 1
-#define GPIO_PIN_2 0x00000004 // GPIO pin 2
-#define GPIO_PIN_3 0x00000008 // GPIO pin 3
-#define GPIO_PIN_4 0x00000010 // GPIO pin 4
-#define GPIO_PIN_5 0x00000020 // GPIO pin 5
-#define GPIO_PIN_6 0x00000040 // GPIO pin 6
-#define GPIO_PIN_7 0x00000080 // GPIO pin 7
-
-//*****************************************************************************
-//
-// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and
-// returned from GPIODirModeGet.
-//
-//*****************************************************************************
-#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input
-#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output
-#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function
-
-//*****************************************************************************
-//
-// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and
-// returned from GPIOIntTypeGet.
-//
-//*****************************************************************************
-#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge
-#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge
-#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges
-#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level
-#define GPIO_HIGH_LEVEL 0x00000007 // Interrupt on high level
-
-//*****************************************************************************
-//
-// Values that can be passed to GPIOPadConfigSet as the ulStrength parameter,
-// and returned by GPIOPadConfigGet in the *pulStrength parameter.
-//
-//*****************************************************************************
-#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength
-#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength
-#define GPIO_STRENGTH_8MA 0x00000004 // 8mA drive strength
-#define GPIO_STRENGTH_8MA_SC 0x0000000C // 8mA drive with slew rate control
-
-//*****************************************************************************
-//
-// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter,
-// and returned by GPIOPadConfigGet in the *pulPadType parameter.
-//
-//*****************************************************************************
-#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull
-#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up
-#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down
-#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain
-#define GPIO_PIN_TYPE_OD_WPU 0x0000000B // Open-drain with weak pull-up
-#define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down
-#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator
-
-//*****************************************************************************
-//
-// Prototypes for the APIs.
-//
-//*****************************************************************************
-extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins,
- unsigned long ulPinIO);
-extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin);
-extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins,
- unsigned long ulIntType);
-extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin);
-extern void GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins,
- unsigned long ulStrength,
- unsigned long ulPadType);
-extern void GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin,
- unsigned long *pulStrength,
- unsigned long *pulPadType);
-extern void GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins);
-extern void GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins);
-extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked);
-extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins);
-extern void GPIOPortIntRegister(unsigned long ulPort,
- void (*pfnIntHandler)(void));
-extern void GPIOPortIntUnregister(unsigned long ulPort);
-extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins);
-extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins,
- unsigned char ucVal);
-extern void GPIOPinTypeADC(unsigned long ulPort, unsigned char ucPins);
-extern void GPIOPinTypeCAN(unsigned long ulPort, unsigned char ucPins);
-extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins);
-extern void GPIOPinTypeGPIOInput(unsigned long ulPort, unsigned char ucPins);
-extern void GPIOPinTypeGPIOOutput(unsigned long ulPort, unsigned char ucPins);
-extern void GPIOPinTypeGPIOOutputOD(unsigned long ulPort,
- unsigned char ucPins);
-extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins);
-extern void GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins);
-extern void GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins);
-extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins);
-extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins);
-extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins);
-extern void GPIOPinTypeUSBDigital(unsigned long ulPort, unsigned char ucPins);
-
-//*****************************************************************************
-//
-// Mark the end of the C bindings section for C++ compilers.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-}
-#endif
-
-#endif // __GPIO_H__
+//*****************************************************************************
+//
+// gpio.h - Defines and Macros for GPIO API.
+//
+// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __GPIO_H__
+#define __GPIO_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// The following values define the bit field for the ucPins argument to several
+// of the APIs.
+//
+//*****************************************************************************
+#define GPIO_PIN_0 0x00000001 // GPIO pin 0
+#define GPIO_PIN_1 0x00000002 // GPIO pin 1
+#define GPIO_PIN_2 0x00000004 // GPIO pin 2
+#define GPIO_PIN_3 0x00000008 // GPIO pin 3
+#define GPIO_PIN_4 0x00000010 // GPIO pin 4
+#define GPIO_PIN_5 0x00000020 // GPIO pin 5
+#define GPIO_PIN_6 0x00000040 // GPIO pin 6
+#define GPIO_PIN_7 0x00000080 // GPIO pin 7
+
+//*****************************************************************************
+//
+// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and
+// returned from GPIODirModeGet.
+//
+//*****************************************************************************
+#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input
+#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output
+#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function
+
+//*****************************************************************************
+//
+// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and
+// returned from GPIOIntTypeGet.
+//
+//*****************************************************************************
+#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge
+#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge
+#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges
+#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level
+#define GPIO_HIGH_LEVEL 0x00000007 // Interrupt on high level
+
+//*****************************************************************************
+//
+// Values that can be passed to GPIOPadConfigSet as the ulStrength parameter,
+// and returned by GPIOPadConfigGet in the *pulStrength parameter.
+//
+//*****************************************************************************
+#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength
+#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength
+#define GPIO_STRENGTH_8MA 0x00000004 // 8mA drive strength
+#define GPIO_STRENGTH_8MA_SC 0x0000000C // 8mA drive with slew rate control
+
+//*****************************************************************************
+//
+// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter,
+// and returned by GPIOPadConfigGet in the *pulPadType parameter.
+//
+//*****************************************************************************
+#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull
+#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up
+#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down
+#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain
+#define GPIO_PIN_TYPE_OD_WPU 0x0000000B // Open-drain with weak pull-up
+#define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down
+#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator
+
+//*****************************************************************************
+//
+// Values that can be passed to GPIOPinConfigure as the ulPinConfig parameter.
+//
+//*****************************************************************************
+//
+// GPIO pin A0
+//
+#define GPIO_PA0_U0RX 0x00000001
+#define GPIO_PA0_I2C1SCL 0x00000008
+#define GPIO_PA0_U1RX 0x00000009
+
+//
+// GPIO pin A1
+//
+#define GPIO_PA1_U0TX 0x00000401
+#define GPIO_PA1_I2C1SDA 0x00000408
+#define GPIO_PA1_U1TX 0x00000409
+
+//
+// GPIO pin A2
+//
+#define GPIO_PA2_SSI0CLK 0x00000801
+#define GPIO_PA2_PWM4 0x00000804
+#define GPIO_PA2_I2S0RXSD 0x00000809
+
+//
+// GPIO pin A3
+//
+#define GPIO_PA3_SSI0FSS 0x00000c01
+#define GPIO_PA3_PWM5 0x00000c04
+#define GPIO_PA3_I2S0RXMCLK 0x00000c09
+
+//
+// GPIO pin A4
+//
+#define GPIO_PA4_SSI0RX 0x00001001
+#define GPIO_PA4_PWM6 0x00001004
+#define GPIO_PA4_CAN0RX 0x00001005
+#define GPIO_PA4_I2S0TXSCK 0x00001009
+
+//
+// GPIO pin A5
+//
+#define GPIO_PA5_SSI0TX 0x00001401
+#define GPIO_PA5_PWM7 0x00001404
+#define GPIO_PA5_CAN0TX 0x00001405
+#define GPIO_PA5_I2S0TXWS 0x00001409
+
+//
+// GPIO pin A6
+//
+#define GPIO_PA6_I2C1SCL 0x00001801
+#define GPIO_PA6_CCP1 0x00001802
+#define GPIO_PA6_PWM0 0x00001804
+#define GPIO_PA6_PWM4 0x00001805
+#define GPIO_PA6_CAN0RX 0x00001806
+#define GPIO_PA6_USB0EPEN 0x00001808
+#define GPIO_PA6_U1CTS 0x00001809
+
+//
+// GPIO pin A7
+//
+#define GPIO_PA7_I2C1SDA 0x00001c01
+#define GPIO_PA7_CCP4 0x00001c02
+#define GPIO_PA7_PWM1 0x00001c04
+#define GPIO_PA7_PWM5 0x00001c05
+#define GPIO_PA7_CAN0TX 0x00001c06
+#define GPIO_PA7_CCP3 0x00001c07
+#define GPIO_PA7_USB0PFLT 0x00001c08
+#define GPIO_PA7_U1DCD 0x00001c09
+
+//
+// GPIO pin B0
+//
+#define GPIO_PB0_CCP0 0x00010001
+#define GPIO_PB0_PWM2 0x00010002
+#define GPIO_PB0_U1RX 0x00010005
+
+//
+// GPIO pin B1
+//
+#define GPIO_PB1_CCP2 0x00010401
+#define GPIO_PB1_PWM3 0x00010402
+#define GPIO_PB1_CCP1 0x00010404
+#define GPIO_PB1_U1TX 0x00010405
+
+//
+// GPIO pin B2
+//
+#define GPIO_PB2_I2C0SCL 0x00010801
+#define GPIO_PB2_IDX0 0x00010802
+#define GPIO_PB2_CCP3 0x00010804
+#define GPIO_PB2_CCP0 0x00010805
+#define GPIO_PB2_USB0EPEN 0x00010808
+
+//
+// GPIO pin B3
+//
+#define GPIO_PB3_I2C0SDA 0x00010c01
+#define GPIO_PB3_FAULT0 0x00010c02
+#define GPIO_PB3_FAULT3 0x00010c04
+#define GPIO_PB3_USB0PFLT 0x00010c08
+
+//
+// GPIO pin B4
+//
+#define GPIO_PB4_U2RX 0x00011004
+#define GPIO_PB4_CAN0RX 0x00011005
+#define GPIO_PB4_IDX0 0x00011006
+#define GPIO_PB4_U1RX 0x00011007
+#define GPIO_PB4_EPI0S23 0x00011008
+
+//
+// GPIO pin B5
+//
+#define GPIO_PB5_C0O 0x00011401
+#define GPIO_PB5_CCP5 0x00011402
+#define GPIO_PB5_CCP6 0x00011403
+#define GPIO_PB5_CCP0 0x00011404
+#define GPIO_PB5_CAN0TX 0x00011405
+#define GPIO_PB5_CCP2 0x00011406
+#define GPIO_PB5_U1TX 0x00011407
+#define GPIO_PB5_EPI0S22 0x00011408
+
+//
+// GPIO pin B6
+//
+#define GPIO_PB6_CCP1 0x00011801
+#define GPIO_PB6_CCP7 0x00011802
+#define GPIO_PB6_C0O 0x00011803
+#define GPIO_PB6_FAULT1 0x00011804
+#define GPIO_PB6_IDX0 0x00011805
+#define GPIO_PB6_CCP5 0x00011806
+#define GPIO_PB6_I2S0TXSCK 0x00011809
+
+//
+// GPIO pin B7
+//
+#define GPIO_PB7_NMI 0x00011c04
+
+//
+// GPIO pin C0
+//
+#define GPIO_PC0_TCK 0x00020003
+
+//
+// GPIO pin C1
+//
+#define GPIO_PC1_TMS 0x00020403
+
+//
+// GPIO pin C2
+//
+#define GPIO_PC2_TDI 0x00020803
+
+//
+// GPIO pin C3
+//
+#define GPIO_PC3_TDO 0x00020c03
+
+//
+// GPIO pin C4
+//
+#define GPIO_PC4_CCP5 0x00021001
+#define GPIO_PC4_PHA0 0x00021002
+#define GPIO_PC4_PWM6 0x00021004
+#define GPIO_PC4_CCP2 0x00021005
+#define GPIO_PC4_CCP4 0x00021006
+#define GPIO_PC4_EPI0S2 0x00021008
+#define GPIO_PC4_CCP1 0x00021009
+
+//
+// GPIO pin C5
+//
+#define GPIO_PC5_CCP1 0x00021401
+#define GPIO_PC5_C1O 0x00021402
+#define GPIO_PC5_C0O 0x00021403
+#define GPIO_PC5_FAULT2 0x00021404
+#define GPIO_PC5_CCP3 0x00021405
+#define GPIO_PC5_USB0EPEN 0x00021406
+#define GPIO_PC5_EPI0S3 0x00021408
+
+//
+// GPIO pin C6
+//
+#define GPIO_PC6_CCP3 0x00021801
+#define GPIO_PC6_PHB0 0x00021802
+#define GPIO_PC6_C2O 0x00021803
+#define GPIO_PC6_PWM7 0x00021804
+#define GPIO_PC6_U1RX 0x00021805
+#define GPIO_PC6_CCP0 0x00021806
+#define GPIO_PC6_USB0PFLT 0x00021807
+#define GPIO_PC6_EPI0S4 0x00021808
+
+//
+// GPIO pin C7
+//
+#define GPIO_PC7_CCP4 0x00021c01
+#define GPIO_PC7_PHB0 0x00021c02
+#define GPIO_PC7_CCP0 0x00021c04
+#define GPIO_PC7_U1TX 0x00021c05
+#define GPIO_PC7_USB0PFLT 0x00021c06
+#define GPIO_PC7_C1O 0x00021c07
+#define GPIO_PC7_EPI0S5 0x00021c08
+
+//
+// GPIO pin D0
+//
+#define GPIO_PD0_PWM0 0x00030001
+#define GPIO_PD0_CAN0RX 0x00030002
+#define GPIO_PD0_IDX0 0x00030003
+#define GPIO_PD0_U2RX 0x00030004
+#define GPIO_PD0_U1RX 0x00030005
+#define GPIO_PD0_CCP6 0x00030006
+#define GPIO_PD0_I2S0RXSCK 0x00030008
+#define GPIO_PD0_U1CTS 0x00030009
+
+//
+// GPIO pin D1
+//
+#define GPIO_PD1_PWM1 0x00030401
+#define GPIO_PD1_CAN0TX 0x00030402
+#define GPIO_PD1_PHA0 0x00030403
+#define GPIO_PD1_U2TX 0x00030404
+#define GPIO_PD1_U1TX 0x00030405
+#define GPIO_PD1_CCP7 0x00030406
+#define GPIO_PD1_I2S0RXWS 0x00030408
+#define GPIO_PD1_U1DCD 0x00030409
+#define GPIO_PD1_CCP2 0x0003040a
+#define GPIO_PD1_PHB1 0x0003040b
+
+//
+// GPIO pin D2
+//
+#define GPIO_PD2_U1RX 0x00030801
+#define GPIO_PD2_CCP6 0x00030802
+#define GPIO_PD2_PWM2 0x00030803
+#define GPIO_PD2_CCP5 0x00030804
+#define GPIO_PD2_EPI0S20 0x00030808
+
+//
+// GPIO pin D3
+//
+#define GPIO_PD3_U1TX 0x00030c01
+#define GPIO_PD3_CCP7 0x00030c02
+#define GPIO_PD3_PWM3 0x00030c03
+#define GPIO_PD3_CCP0 0x00030c04
+#define GPIO_PD3_EPI0S21 0x00030c08
+
+//
+// GPIO pin D4
+//
+#define GPIO_PD4_CCP0 0x00031001
+#define GPIO_PD4_CCP3 0x00031002
+#define GPIO_PD4_I2S0RXSD 0x00031008
+#define GPIO_PD4_U1RI 0x00031009
+#define GPIO_PD4_EPI0S19 0x0003100a
+
+//
+// GPIO pin D5
+//
+#define GPIO_PD5_CCP2 0x00031401
+#define GPIO_PD5_CCP4 0x00031402
+#define GPIO_PD5_I2S0RXMCLK 0x00031408
+#define GPIO_PD5_U2RX 0x00031409
+#define GPIO_PD5_EPI0S28 0x0003140a
+
+//
+// GPIO pin D6
+//
+#define GPIO_PD6_FAULT0 0x00031801
+#define GPIO_PD6_I2S0TXSCK 0x00031808
+#define GPIO_PD6_U2TX 0x00031809
+#define GPIO_PD6_EPI0S29 0x0003180a
+
+//
+// GPIO pin D7
+//
+#define GPIO_PD7_IDX0 0x00031c01
+#define GPIO_PD7_C0O 0x00031c02
+#define GPIO_PD7_CCP1 0x00031c03
+#define GPIO_PD7_I2S0TXWS 0x00031c08
+#define GPIO_PD7_U1DTR 0x00031c09
+#define GPIO_PD7_EPI0S30 0x00031c0a
+
+//
+// GPIO pin E0
+//
+#define GPIO_PE0_PWM4 0x00040001
+#define GPIO_PE0_SSI1CLK 0x00040002
+#define GPIO_PE0_CCP3 0x00040003
+#define GPIO_PE0_EPI0S8 0x00040008
+#define GPIO_PE0_USB0PFLT 0x00040009
+
+//
+// GPIO pin E1
+//
+#define GPIO_PE1_PWM5 0x00040401
+#define GPIO_PE1_SSI1FSS 0x00040402
+#define GPIO_PE1_FAULT0 0x00040403
+#define GPIO_PE1_CCP2 0x00040404
+#define GPIO_PE1_CCP6 0x00040405
+#define GPIO_PE1_EPI0S9 0x00040408
+
+//
+// GPIO pin E2
+//
+#define GPIO_PE2_CCP4 0x00040801
+#define GPIO_PE2_SSI1RX 0x00040802
+#define GPIO_PE2_PHB1 0x00040803
+#define GPIO_PE2_PHA0 0x00040804
+#define GPIO_PE2_CCP2 0x00040805
+#define GPIO_PE2_EPI0S24 0x00040808
+
+//
+// GPIO pin E3
+//
+#define GPIO_PE3_CCP1 0x00040c01
+#define GPIO_PE3_SSI1TX 0x00040c02
+#define GPIO_PE3_PHA1 0x00040c03
+#define GPIO_PE3_PHB0 0x00040c04
+#define GPIO_PE3_CCP7 0x00040c05
+#define GPIO_PE3_EPI0S25 0x00040c08
+
+//
+// GPIO pin E4
+//
+#define GPIO_PE4_CCP3 0x00041001
+#define GPIO_PE4_FAULT0 0x00041004
+#define GPIO_PE4_U2TX 0x00041005
+#define GPIO_PE4_CCP2 0x00041006
+#define GPIO_PE4_I2S0TXWS 0x00041009
+
+//
+// GPIO pin E5
+//
+#define GPIO_PE5_CCP5 0x00041401
+#define GPIO_PE5_I2S0TXSD 0x00041409
+
+//
+// GPIO pin E6
+//
+#define GPIO_PE6_PWM4 0x00041801
+#define GPIO_PE6_C1O 0x00041802
+#define GPIO_PE6_U1CTS 0x00041809
+
+//
+// GPIO pin E7
+//
+#define GPIO_PE7_PWM5 0x00041c01
+#define GPIO_PE7_C2O 0x00041c02
+#define GPIO_PE7_U1DCD 0x00041c09
+
+//
+// GPIO pin F0
+//
+#define GPIO_PF0_CAN1RX 0x00050001
+#define GPIO_PF0_PHB0 0x00050002
+#define GPIO_PF0_PWM0 0x00050003
+#define GPIO_PF0_I2S0TXSD 0x00050008
+#define GPIO_PF0_U1DSR 0x00050009
+
+//
+// GPIO pin F1
+//
+#define GPIO_PF1_CAN1TX 0x00050401
+#define GPIO_PF1_IDX1 0x00050402
+#define GPIO_PF1_PWM1 0x00050403
+#define GPIO_PF1_I2S0TXMCLK 0x00050408
+#define GPIO_PF1_U1RTS 0x00050409
+#define GPIO_PF1_CCP3 0x0005040a
+
+//
+// GPIO pin F2
+//
+#define GPIO_PF2_LED1 0x00050801
+#define GPIO_PF2_PWM4 0x00050802
+#define GPIO_PF2_PWM2 0x00050804
+#define GPIO_PF2_SSI1CLK 0x00050809
+
+//
+// GPIO pin F3
+//
+#define GPIO_PF3_LED0 0x00050c01
+#define GPIO_PF3_PWM5 0x00050c02
+#define GPIO_PF3_PWM3 0x00050c04
+#define GPIO_PF3_SSI1FSS 0x00050c09
+
+//
+// GPIO pin F4
+//
+#define GPIO_PF4_CCP0 0x00051001
+#define GPIO_PF4_C0O 0x00051002
+#define GPIO_PF4_FAULT0 0x00051004
+#define GPIO_PF4_EPI0S12 0x00051008
+#define GPIO_PF4_SSI1RX 0x00051009
+
+//
+// GPIO pin F5
+//
+#define GPIO_PF5_CCP2 0x00051401
+#define GPIO_PF5_C1O 0x00051402
+#define GPIO_PF5_EPI0S15 0x00051408
+#define GPIO_PF5_SSI1TX 0x00051409
+
+//
+// GPIO pin F6
+//
+#define GPIO_PF6_CCP1 0x00051801
+#define GPIO_PF6_C2O 0x00051802
+#define GPIO_PF6_PHA0 0x00051804
+#define GPIO_PF6_I2S0TXMCLK 0x00051809
+#define GPIO_PF6_U1RTS 0x0005180a
+
+//
+// GPIO pin F7
+//
+#define GPIO_PF7_CCP4 0x00051c01
+#define GPIO_PF7_PHB0 0x00051c04
+#define GPIO_PF7_EPI0S12 0x00051c08
+#define GPIO_PF7_FAULT1 0x00051c09
+
+//
+// GPIO pin G0
+//
+#define GPIO_PG0_U2RX 0x00060001
+#define GPIO_PG0_PWM0 0x00060002
+#define GPIO_PG0_I2C1SCL 0x00060003
+#define GPIO_PG0_PWM4 0x00060004
+#define GPIO_PG0_USB0EPEN 0x00060007
+#define GPIO_PG0_EPI0S13 0x00060008
+
+//
+// GPIO pin G1
+//
+#define GPIO_PG1_U2TX 0x00060401
+#define GPIO_PG1_PWM1 0x00060402
+#define GPIO_PG1_I2C1SDA 0x00060403
+#define GPIO_PG1_PWM5 0x00060404
+#define GPIO_PG1_EPI0S14 0x00060408
+
+//
+// GPIO pin G2
+//
+#define GPIO_PG2_PWM0 0x00060801
+#define GPIO_PG2_FAULT0 0x00060804
+#define GPIO_PG2_IDX1 0x00060808
+#define GPIO_PG2_I2S0RXSD 0x00060809
+
+//
+// GPIO pin G3
+//
+#define GPIO_PG3_PWM1 0x00060c01
+#define GPIO_PG3_FAULT2 0x00060c04
+#define GPIO_PG3_FAULT0 0x00060c08
+#define GPIO_PG3_I2S0RXMCLK 0x00060c09
+
+//
+// GPIO pin G4
+//
+#define GPIO_PG4_CCP3 0x00061001
+#define GPIO_PG4_FAULT1 0x00061004
+#define GPIO_PG4_EPI0S15 0x00061008
+#define GPIO_PG4_PWM6 0x00061009
+#define GPIO_PG4_U1RI 0x0006100a
+
+//
+// GPIO pin G5
+//
+#define GPIO_PG5_CCP5 0x00061401
+#define GPIO_PG5_IDX0 0x00061404
+#define GPIO_PG5_FAULT1 0x00061405
+#define GPIO_PG5_PWM7 0x00061408
+#define GPIO_PG5_I2S0RXSCK 0x00061409
+#define GPIO_PG5_U1DTR 0x0006140a
+
+//
+// GPIO pin G6
+//
+#define GPIO_PG6_PHA1 0x00061801
+#define GPIO_PG6_PWM6 0x00061804
+#define GPIO_PG6_FAULT1 0x00061808
+#define GPIO_PG6_I2S0RXWS 0x00061809
+#define GPIO_PG6_U1RI 0x0006180a
+
+//
+// GPIO pin G7
+//
+#define GPIO_PG7_PHB1 0x00061c01
+#define GPIO_PG7_PWM7 0x00061c04
+#define GPIO_PG7_CCP5 0x00061c08
+#define GPIO_PG7_EPI0S31 0x00061c09
+
+//
+// GPIO pin H0
+//
+#define GPIO_PH0_CCP6 0x00070001
+#define GPIO_PH0_PWM2 0x00070002
+#define GPIO_PH0_EPI0S6 0x00070008
+#define GPIO_PH0_PWM4 0x00070009
+
+//
+// GPIO pin H1
+//
+#define GPIO_PH1_CCP7 0x00070401
+#define GPIO_PH1_PWM3 0x00070402
+#define GPIO_PH1_EPI0S7 0x00070408
+#define GPIO_PH1_PWM5 0x00070409
+
+//
+// GPIO pin H2
+//
+#define GPIO_PH2_IDX1 0x00070801
+#define GPIO_PH2_C1O 0x00070802
+#define GPIO_PH2_FAULT3 0x00070804
+#define GPIO_PH2_EPI0S1 0x00070808
+
+//
+// GPIO pin H3
+//
+#define GPIO_PH3_PHB0 0x00070c01
+#define GPIO_PH3_FAULT0 0x00070c02
+#define GPIO_PH3_USB0EPEN 0x00070c04
+#define GPIO_PH3_EPI0S0 0x00070c08
+
+//
+// GPIO pin H4
+//
+#define GPIO_PH4_USB0PFLT 0x00071004
+#define GPIO_PH4_EPI0S10 0x00071008
+#define GPIO_PH4_SSI1CLK 0x0007100b
+
+//
+// GPIO pin H5
+//
+#define GPIO_PH5_EPI0S11 0x00071408
+#define GPIO_PH5_FAULT2 0x0007140a
+#define GPIO_PH5_SSI1FSS 0x0007140b
+
+//
+// GPIO pin H6
+//
+#define GPIO_PH6_EPI0S26 0x00071808
+#define GPIO_PH6_PWM4 0x0007180a
+#define GPIO_PH6_SSI1RX 0x0007180b
+
+//
+// GPIO pin H7
+//
+#define GPIO_PH7_EPI0S27 0x00071c08
+#define GPIO_PH7_PWM5 0x00071c0a
+#define GPIO_PH7_SSI1TX 0x00071c0b
+
+//
+// GPIO pin J0
+//
+#define GPIO_PJ0_EPI0S16 0x00080008
+#define GPIO_PJ0_PWM0 0x0008000a
+#define GPIO_PJ0_I2C1SCL 0x0008000b
+
+//
+// GPIO pin J1
+//
+#define GPIO_PJ1_EPI0S17 0x00080408
+#define GPIO_PJ1_USB0PFLT 0x00080409
+#define GPIO_PJ1_PWM1 0x0008040a
+#define GPIO_PJ1_I2C1SDA 0x0008040b
+
+//
+// GPIO pin J2
+//
+#define GPIO_PJ2_EPI0S18 0x00080808
+#define GPIO_PJ2_CCP0 0x00080809
+#define GPIO_PJ2_FAULT0 0x0008080a
+
+//
+// GPIO pin J3
+//
+#define GPIO_PJ3_EPI0S19 0x00080c08
+#define GPIO_PJ3_U1CTS 0x00080c09
+#define GPIO_PJ3_CCP6 0x00080c0a
+
+//
+// GPIO pin J4
+//
+#define GPIO_PJ4_EPI0S28 0x00081008
+#define GPIO_PJ4_U1DCD 0x00081009
+#define GPIO_PJ4_CCP4 0x0008100a
+
+//
+// GPIO pin J5
+//
+#define GPIO_PJ5_EPI0S29 0x00081408
+#define GPIO_PJ5_U1DSR 0x00081409
+#define GPIO_PJ5_CCP2 0x0008140a
+
+//
+// GPIO pin J6
+//
+#define GPIO_PJ6_EPI0S30 0x00081808
+#define GPIO_PJ6_U1RTS 0x00081809
+#define GPIO_PJ6_CCP1 0x0008180a
+
+//
+// GPIO pin J7
+//
+#define GPIO_PJ7_U1DTR 0x00081c09
+#define GPIO_PJ7_CCP0 0x00081c0a
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins,
+ unsigned long ulPinIO);
+extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin);
+extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins,
+ unsigned long ulIntType);
+extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin);
+extern void GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins,
+ unsigned long ulStrength,
+ unsigned long ulPadType);
+extern void GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin,
+ unsigned long *pulStrength,
+ unsigned long *pulPadType);
+extern void GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins);
+extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked);
+extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPortIntRegister(unsigned long ulPort,
+ void (*pfnIntHandler)(void));
+extern void GPIOPortIntUnregister(unsigned long ulPort);
+extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins,
+ unsigned char ucVal);
+extern void GPIOPinConfigure(unsigned long ulPinConfig);
+extern void GPIOPinTypeADC(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinTypeCAN(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinTypeGPIOInput(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinTypeGPIOOutput(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinTypeGPIOOutputOD(unsigned long ulPort,
+ unsigned char ucPins);
+extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinTypeI2S(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinTypeUSBAnalog(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinTypeUSBDigital(unsigned long ulPort, unsigned char ucPins);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __GPIO_H__
Property changes on: branches/eagle_mmc/src/platform/lm3s/gpio.h
___________________________________________________________________
Name: svn:executable
+ *
Modified: branches/eagle_mmc/src/platform/lm3s/hw_adc.h
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/hw_adc.h 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lm3s/hw_adc.h 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,634 +1,1159 @@
-//*****************************************************************************
-//
-// hw_adc.h - Macros used when accessing the ADC hardware.
-//
-// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
-// Software License Agreement
-//
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
-//
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws. All rights are reserved. You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program. Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
-//
-// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-//
-// This is part of revision 3740 of the Stellaris Firmware Development Package.
-//
-//*****************************************************************************
-
-#ifndef __HW_ADC_H__
-#define __HW_ADC_H__
-
-//*****************************************************************************
-//
-// The following are defines for the ADC register offsets.
-//
-//*****************************************************************************
-#define ADC_O_ACTSS 0x00000000 // Active sample register
-#define ADC_O_RIS 0x00000004 // Raw interrupt status register
-#define ADC_O_IM 0x00000008 // Interrupt mask register
-#define ADC_O_ISC 0x0000000C // Interrupt status/clear register
-#define ADC_O_OSTAT 0x00000010 // Overflow status register
-#define ADC_O_EMUX 0x00000014 // Event multiplexer select reg.
-#define ADC_O_USTAT 0x00000018 // Underflow status register
-#define ADC_O_SSPRI 0x00000020 // Channel priority register
-#define ADC_O_PSSI 0x00000028 // Processor sample initiate reg.
-#define ADC_O_SAC 0x00000030 // Sample Averaging Control reg.
-#define ADC_O_SSMUX0 0x00000040 // Multiplexer select 0 register
-#define ADC_O_SSCTL0 0x00000044 // Sample sequence control 0 reg.
-#define ADC_O_SSFIFO0 0x00000048 // Result FIFO 0 register
-#define ADC_O_SSFSTAT0 0x0000004C // FIFO 0 status register
-#define ADC_O_SSMUX1 0x00000060 // Multiplexer select 1 register
-#define ADC_O_SSCTL1 0x00000064 // Sample sequence control 1 reg.
-#define ADC_O_SSFIFO1 0x00000068 // Result FIFO 1 register
-#define ADC_O_SSFSTAT1 0x0000006C // FIFO 1 status register
-#define ADC_O_SSMUX2 0x00000080 // Multiplexer select 2 register
-#define ADC_O_SSCTL2 0x00000084 // Sample sequence control 2 reg.
-#define ADC_O_SSFIFO2 0x00000088 // Result FIFO 2 register
-#define ADC_O_SSFSTAT2 0x0000008C // FIFO 2 status register
-#define ADC_O_SSMUX3 0x000000A0 // Multiplexer select 3 register
-#define ADC_O_SSCTL3 0x000000A4 // Sample sequence control 3 reg.
-#define ADC_O_SSFIFO3 0x000000A8 // Result FIFO 3 register
-#define ADC_O_SSFSTAT3 0x000000AC // FIFO 3 status register
-#define ADC_O_TMLB 0x00000100 // Test mode loopback register
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_ACTSS register.
-//
-//*****************************************************************************
-#define ADC_ACTSS_ASEN3 0x00000008 // Sample sequence 3 enable
-#define ADC_ACTSS_ASEN2 0x00000004 // Sample sequence 2 enable
-#define ADC_ACTSS_ASEN1 0x00000002 // Sample sequence 1 enable
-#define ADC_ACTSS_ASEN0 0x00000001 // Sample sequence 0 enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_RIS register.
-//
-//*****************************************************************************
-#define ADC_RIS_INR3 0x00000008 // Sample sequence 3 interrupt
-#define ADC_RIS_INR2 0x00000004 // Sample sequence 2 interrupt
-#define ADC_RIS_INR1 0x00000002 // Sample sequence 1 interrupt
-#define ADC_RIS_INR0 0x00000001 // Sample sequence 0 interrupt
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_IM register.
-//
-//*****************************************************************************
-#define ADC_IM_MASK3 0x00000008 // Sample sequence 3 mask
-#define ADC_IM_MASK2 0x00000004 // Sample sequence 2 mask
-#define ADC_IM_MASK1 0x00000002 // Sample sequence 1 mask
-#define ADC_IM_MASK0 0x00000001 // Sample sequence 0 mask
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_ISC register.
-//
-//*****************************************************************************
-#define ADC_ISC_IN3 0x00000008 // Sample sequence 3 interrupt
-#define ADC_ISC_IN2 0x00000004 // Sample sequence 2 interrupt
-#define ADC_ISC_IN1 0x00000002 // Sample sequence 1 interrupt
-#define ADC_ISC_IN0 0x00000001 // Sample sequence 0 interrupt
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_OSTAT register.
-//
-//*****************************************************************************
-#define ADC_OSTAT_OV3 0x00000008 // Sample sequence 3 overflow
-#define ADC_OSTAT_OV2 0x00000004 // Sample sequence 2 overflow
-#define ADC_OSTAT_OV1 0x00000002 // Sample sequence 1 overflow
-#define ADC_OSTAT_OV0 0x00000001 // Sample sequence 0 overflow
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_EMUX register.
-//
-//*****************************************************************************
-#define ADC_EMUX_EM3_M 0x0000F000 // Event mux 3 mask
-#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Processor event
-#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog comparator 0 event
-#define ADC_EMUX_EM3_COMP1 0x00002000 // Analog comparator 1 event
-#define ADC_EMUX_EM3_COMP2 0x00003000 // Analog comparator 2 event
-#define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External event
-#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer event
-#define ADC_EMUX_EM3_PWM0 0x00006000 // PWM0 event
-#define ADC_EMUX_EM3_PWM1 0x00007000 // PWM1 event
-#define ADC_EMUX_EM3_PWM2 0x00008000 // PWM2 event
-#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always event
-#define ADC_EMUX_EM2_M 0x00000F00 // Event mux 2 mask
-#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Processor event
-#define ADC_EMUX_EM2_COMP0 0x00000100 // Analog comparator 0 event
-#define ADC_EMUX_EM2_COMP1 0x00000200 // Analog comparator 1 event
-#define ADC_EMUX_EM2_COMP2 0x00000300 // Analog comparator 2 event
-#define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External event
-#define ADC_EMUX_EM2_TIMER 0x00000500 // Timer event
-#define ADC_EMUX_EM2_PWM0 0x00000600 // PWM0 event
-#define ADC_EMUX_EM2_PWM1 0x00000700 // PWM1 event
-#define ADC_EMUX_EM2_PWM2 0x00000800 // PWM2 event
-#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always event
-#define ADC_EMUX_EM1_M 0x000000F0 // Event mux 1 mask
-#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Processor event
-#define ADC_EMUX_EM1_COMP0 0x00000010 // Analog comparator 0 event
-#define ADC_EMUX_EM1_COMP1 0x00000020 // Analog comparator 1 event
-#define ADC_EMUX_EM1_COMP2 0x00000030 // Analog comparator 2 event
-#define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External event
-#define ADC_EMUX_EM1_TIMER 0x00000050 // Timer event
-#define ADC_EMUX_EM1_PWM0 0x00000060 // PWM0 event
-#define ADC_EMUX_EM1_PWM1 0x00000070 // PWM1 event
-#define ADC_EMUX_EM1_PWM2 0x00000080 // PWM2 event
-#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always event
-#define ADC_EMUX_EM0_M 0x0000000F // Event mux 0 mask
-#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Processor event
-#define ADC_EMUX_EM0_COMP0 0x00000001 // Analog comparator 0 event
-#define ADC_EMUX_EM0_COMP1 0x00000002 // Analog comparator 1 event
-#define ADC_EMUX_EM0_COMP2 0x00000003 // Analog comparator 2 event
-#define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External event
-#define ADC_EMUX_EM0_TIMER 0x00000005 // Timer event
-#define ADC_EMUX_EM0_PWM0 0x00000006 // PWM0 event
-#define ADC_EMUX_EM0_PWM1 0x00000007 // PWM1 event
-#define ADC_EMUX_EM0_PWM2 0x00000008 // PWM2 event
-#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always event
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_USTAT register.
-//
-//*****************************************************************************
-#define ADC_USTAT_UV3 0x00000008 // Sample sequence 3 underflow
-#define ADC_USTAT_UV2 0x00000004 // Sample sequence 2 underflow
-#define ADC_USTAT_UV1 0x00000002 // Sample sequence 1 underflow
-#define ADC_USTAT_UV0 0x00000001 // Sample sequence 0 underflow
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_SSPRI register.
-//
-//*****************************************************************************
-#define ADC_SSPRI_SS3_M 0x00003000 // Sequencer 3 priority mask
-#define ADC_SSPRI_SS3_1ST 0x00000000 // First priority
-#define ADC_SSPRI_SS3_2ND 0x00001000 // Second priority
-#define ADC_SSPRI_SS3_3RD 0x00002000 // Third priority
-#define ADC_SSPRI_SS3_4TH 0x00003000 // Fourth priority
-#define ADC_SSPRI_SS2_M 0x00000300 // Sequencer 2 priority mask
-#define ADC_SSPRI_SS2_1ST 0x00000000 // First priority
-#define ADC_SSPRI_SS2_2ND 0x00000100 // Second priority
-#define ADC_SSPRI_SS2_3RD 0x00000200 // Third priority
-#define ADC_SSPRI_SS2_4TH 0x00000300 // Fourth priority
-#define ADC_SSPRI_SS1_M 0x00000030 // Sequencer 1 priority mask
-#define ADC_SSPRI_SS1_1ST 0x00000000 // First priority
-#define ADC_SSPRI_SS1_2ND 0x00000010 // Second priority
-#define ADC_SSPRI_SS1_3RD 0x00000020 // Third priority
-#define ADC_SSPRI_SS1_4TH 0x00000030 // Fourth priority
-#define ADC_SSPRI_SS0_M 0x00000003 // Sequencer 0 priority mask
-#define ADC_SSPRI_SS0_1ST 0x00000000 // First priority
-#define ADC_SSPRI_SS0_2ND 0x00000001 // Second priority
-#define ADC_SSPRI_SS0_3RD 0x00000002 // Third priority
-#define ADC_SSPRI_SS0_4TH 0x00000003 // Fourth priority
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_PSSI register.
-//
-//*****************************************************************************
-#define ADC_PSSI_SS3 0x00000008 // Trigger sample sequencer 3
-#define ADC_PSSI_SS2 0x00000004 // Trigger sample sequencer 2
-#define ADC_PSSI_SS1 0x00000002 // Trigger sample sequencer 1
-#define ADC_PSSI_SS0 0x00000001 // Trigger sample sequencer 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_SAC register.
-//
-//*****************************************************************************
-#define ADC_SAC_AVG_M 0x00000007 // Hardware Averaging Control.
-#define ADC_SAC_AVG_64X 0x00000006 // 64x hardware oversampling
-#define ADC_SAC_AVG_32X 0x00000005 // 32x hardware oversampling
-#define ADC_SAC_AVG_16X 0x00000004 // 16x hardware oversampling
-#define ADC_SAC_AVG_8X 0x00000003 // 8x hardware oversampling
-#define ADC_SAC_AVG_4X 0x00000002 // 4x hardware oversampling
-#define ADC_SAC_AVG_2X 0x00000001 // 2x hardware oversampling
-#define ADC_SAC_AVG_OFF 0x00000000 // No hardware oversampling
-
-//*****************************************************************************
-//
-// The following are defines for the the interpretation of the data in the
-// SSFIFOx when the ADC TMLB is enabled.
-//
-//*****************************************************************************
-#define ADC_SSFIFO_TMLB_CNT_M 0x000003C0 // Continuous Sample Counter.
-#define ADC_SSFIFO_TMLB_CONT 0x00000020 // Continuation Sample Indicator.
-#define ADC_SSFIFO_TMLB_DIFF 0x00000010 // Differential Sample Indicator.
-#define ADC_SSFIFO_TMLB_TS 0x00000008 // Temp Sensor Sample Indicator.
-#define ADC_SSFIFO_TMLB_MUX_M 0x00000007 // Analog Input Indicator.
-#define ADC_SSFIFO_TMLB_CNT_S 6 // Sample counter shift
-#define ADC_SSFIFO_TMLB_MUX_S 0 // Input channel number shift
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_TMLB register.
-//
-//*****************************************************************************
-#define ADC_TMLB_LB 0x00000001 // Loopback control signals
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_SSMUX0 register.
-//
-//*****************************************************************************
-#define ADC_SSMUX0_MUX7_M 0x70000000 // 8th Sample Input Select.
-#define ADC_SSMUX0_MUX6_M 0x07000000 // 7th Sample Input Select.
-#define ADC_SSMUX0_MUX5_M 0x00700000 // 6th Sample Input Select.
-#define ADC_SSMUX0_MUX4_M 0x00070000 // 5th Sample Input Select.
-#define ADC_SSMUX0_MUX3_M 0x00007000 // 4th Sample Input Select.
-#define ADC_SSMUX0_MUX2_M 0x00000700 // 3rd Sample Input Select.
-#define ADC_SSMUX0_MUX1_M 0x00000070 // 2nd Sample Input Select.
-#define ADC_SSMUX0_MUX0_M 0x00000007 // 1st Sample Input Select.
-#define ADC_SSMUX0_MUX7_S 28
-#define ADC_SSMUX0_MUX6_S 24
-#define ADC_SSMUX0_MUX5_S 20
-#define ADC_SSMUX0_MUX4_S 16
-#define ADC_SSMUX0_MUX3_S 12
-#define ADC_SSMUX0_MUX2_S 8
-#define ADC_SSMUX0_MUX1_S 4
-#define ADC_SSMUX0_MUX0_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_SSCTL0 register.
-//
-//*****************************************************************************
-#define ADC_SSCTL0_TS7 0x80000000 // 8th Sample Temp Sensor Select.
-#define ADC_SSCTL0_IE7 0x40000000 // 8th Sample Interrupt Enable.
-#define ADC_SSCTL0_END7 0x20000000 // 8th Sample is End of Sequence.
-#define ADC_SSCTL0_D7 0x10000000 // 8th Sample Diff Input Select.
-#define ADC_SSCTL0_TS6 0x08000000 // 7th Sample Temp Sensor Select.
-#define ADC_SSCTL0_IE6 0x04000000 // 7th Sample Interrupt Enable.
-#define ADC_SSCTL0_END6 0x02000000 // 7th Sample is End of Sequence.
-#define ADC_SSCTL0_D6 0x01000000 // 7th Sample Diff Input Select.
-#define ADC_SSCTL0_TS5 0x00800000 // 6th Sample Temp Sensor Select.
-#define ADC_SSCTL0_IE5 0x00400000 // 6th Sample Interrupt Enable.
-#define ADC_SSCTL0_END5 0x00200000 // 6th Sample is End of Sequence.
-#define ADC_SSCTL0_D5 0x00100000 // 6th Sample Diff Input Select.
-#define ADC_SSCTL0_TS4 0x00080000 // 5th Sample Temp Sensor Select.
-#define ADC_SSCTL0_IE4 0x00040000 // 5th Sample Interrupt Enable.
-#define ADC_SSCTL0_END4 0x00020000 // 5th Sample is End of Sequence.
-#define ADC_SSCTL0_D4 0x00010000 // 5th Sample Diff Input Select.
-#define ADC_SSCTL0_TS3 0x00008000 // 4th Sample Temp Sensor Select.
-#define ADC_SSCTL0_IE3 0x00004000 // 4th Sample Interrupt Enable.
-#define ADC_SSCTL0_END3 0x00002000 // 4th Sample is End of Sequence.
-#define ADC_SSCTL0_D3 0x00001000 // 4th Sample Diff Input Select.
-#define ADC_SSCTL0_TS2 0x00000800 // 3rd Sample Temp Sensor Select.
-#define ADC_SSCTL0_IE2 0x00000400 // 3rd Sample Interrupt Enable.
-#define ADC_SSCTL0_END2 0x00000200 // 3rd Sample is End of Sequence.
-#define ADC_SSCTL0_D2 0x00000100 // 3rd Sample Diff Input Select.
-#define ADC_SSCTL0_TS1 0x00000080 // 2nd Sample Temp Sensor Select.
-#define ADC_SSCTL0_IE1 0x00000040 // 2nd Sample Interrupt Enable.
-#define ADC_SSCTL0_END1 0x00000020 // 2nd Sample is End of Sequence.
-#define ADC_SSCTL0_D1 0x00000010 // 2nd Sample Diff Input Select.
-#define ADC_SSCTL0_TS0 0x00000008 // 1st Sample Temp Sensor Select.
-#define ADC_SSCTL0_IE0 0x00000004 // 1st Sample Interrupt Enable.
-#define ADC_SSCTL0_END0 0x00000002 // 1st Sample is End of Sequence.
-#define ADC_SSCTL0_D0 0x00000001 // 1st Sample Diff Input Select.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_SSFIFO0 register.
-//
-//*****************************************************************************
-#define ADC_SSFIFO0_DATA_M 0x000003FF // Conversion Result Data.
-#define ADC_SSFIFO0_DATA_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_SSFSTAT0 register.
-//
-//*****************************************************************************
-#define ADC_SSFSTAT0_FULL 0x00001000 // FIFO Full.
-#define ADC_SSFSTAT0_EMPTY 0x00000100 // FIFO Empty.
-#define ADC_SSFSTAT0_HPTR_M 0x000000F0 // FIFO Head Pointer.
-#define ADC_SSFSTAT0_TPTR_M 0x0000000F // FIFO Tail Pointer.
-#define ADC_SSFSTAT0_HPTR_S 4
-#define ADC_SSFSTAT0_TPTR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_SSMUX1 register.
-//
-//*****************************************************************************
-#define ADC_SSMUX1_MUX3_M 0x00007000 // 4th Sample Input Select.
-#define ADC_SSMUX1_MUX2_M 0x00000700 // 3rd Sample Input Select.
-#define ADC_SSMUX1_MUX1_M 0x00000070 // 2nd Sample Input Select.
-#define ADC_SSMUX1_MUX0_M 0x00000007 // 1st Sample Input Select.
-#define ADC_SSMUX1_MUX3_S 12
-#define ADC_SSMUX1_MUX2_S 8
-#define ADC_SSMUX1_MUX1_S 4
-#define ADC_SSMUX1_MUX0_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_SSCTL1 register.
-//
-//*****************************************************************************
-#define ADC_SSCTL1_TS3 0x00008000 // 4th Sample Temp Sensor Select.
-#define ADC_SSCTL1_IE3 0x00004000 // 4th Sample Interrupt Enable.
-#define ADC_SSCTL1_END3 0x00002000 // 4th Sample is End of Sequence.
-#define ADC_SSCTL1_D3 0x00001000 // 4th Sample Diff Input Select.
-#define ADC_SSCTL1_TS2 0x00000800 // 3rd Sample Temp Sensor Select.
-#define ADC_SSCTL1_IE2 0x00000400 // 3rd Sample Interrupt Enable.
-#define ADC_SSCTL1_END2 0x00000200 // 3rd Sample is End of Sequence.
-#define ADC_SSCTL1_D2 0x00000100 // 3rd Sample Diff Input Select.
-#define ADC_SSCTL1_TS1 0x00000080 // 2nd Sample Temp Sensor Select.
-#define ADC_SSCTL1_IE1 0x00000040 // 2nd Sample Interrupt Enable.
-#define ADC_SSCTL1_END1 0x00000020 // 2nd Sample is End of Sequence.
-#define ADC_SSCTL1_D1 0x00000010 // 2nd Sample Diff Input Select.
-#define ADC_SSCTL1_TS0 0x00000008 // 1st Sample Temp Sensor Select.
-#define ADC_SSCTL1_IE0 0x00000004 // 1st Sample Interrupt Enable.
-#define ADC_SSCTL1_END0 0x00000002 // 1st Sample is End of Sequence.
-#define ADC_SSCTL1_D0 0x00000001 // 1st Sample Diff Input Select.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_SSFIFO1 register.
-//
-//*****************************************************************************
-#define ADC_SSFIFO1_DATA_M 0x000003FF // Conversion Result Data.
-#define ADC_SSFIFO1_DATA_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_SSFSTAT1 register.
-//
-//*****************************************************************************
-#define ADC_SSFSTAT1_FULL 0x00001000 // FIFO Full.
-#define ADC_SSFSTAT1_EMPTY 0x00000100 // FIFO Empty.
-#define ADC_SSFSTAT1_HPTR_M 0x000000F0 // FIFO Head Pointer.
-#define ADC_SSFSTAT1_TPTR_M 0x0000000F // FIFO Tail Pointer.
-#define ADC_SSFSTAT1_HPTR_S 4
-#define ADC_SSFSTAT1_TPTR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_SSMUX2 register.
-//
-//*****************************************************************************
-#define ADC_SSMUX2_MUX3_M 0x00007000 // 4th Sample Input Select.
-#define ADC_SSMUX2_MUX2_M 0x00000700 // 3rd Sample Input Select.
-#define ADC_SSMUX2_MUX1_M 0x00000070 // 2nd Sample Input Select.
-#define ADC_SSMUX2_MUX0_M 0x00000007 // 1st Sample Input Select.
-#define ADC_SSMUX2_MUX3_S 12
-#define ADC_SSMUX2_MUX2_S 8
-#define ADC_SSMUX2_MUX1_S 4
-#define ADC_SSMUX2_MUX0_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_SSCTL2 register.
-//
-//*****************************************************************************
-#define ADC_SSCTL2_TS3 0x00008000 // 4th Sample Temp Sensor Select.
-#define ADC_SSCTL2_IE3 0x00004000 // 4th Sample Interrupt Enable.
-#define ADC_SSCTL2_END3 0x00002000 // 4th Sample is End of Sequence.
-#define ADC_SSCTL2_D3 0x00001000 // 4th Sample Diff Input Select.
-#define ADC_SSCTL2_TS2 0x00000800 // 3rd Sample Temp Sensor Select.
-#define ADC_SSCTL2_IE2 0x00000400 // 3rd Sample Interrupt Enable.
-#define ADC_SSCTL2_END2 0x00000200 // 3rd Sample is End of Sequence.
-#define ADC_SSCTL2_D2 0x00000100 // 3rd Sample Diff Input Select.
-#define ADC_SSCTL2_TS1 0x00000080 // 2nd Sample Temp Sensor Select.
-#define ADC_SSCTL2_IE1 0x00000040 // 2nd Sample Interrupt Enable.
-#define ADC_SSCTL2_END1 0x00000020 // 2nd Sample is End of Sequence.
-#define ADC_SSCTL2_D1 0x00000010 // 2nd Sample Diff Input Select.
-#define ADC_SSCTL2_TS0 0x00000008 // 1st Sample Temp Sensor Select.
-#define ADC_SSCTL2_IE0 0x00000004 // 1st Sample Interrupt Enable.
-#define ADC_SSCTL2_END0 0x00000002 // 1st Sample is End of Sequence.
-#define ADC_SSCTL2_D0 0x00000001 // 1st Sample Diff Input Select.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_SSFIFO2 register.
-//
-//*****************************************************************************
-#define ADC_SSFIFO2_DATA_M 0x000003FF // Conversion Result Data.
-#define ADC_SSFIFO2_DATA_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_SSFSTAT2 register.
-//
-//*****************************************************************************
-#define ADC_SSFSTAT2_FULL 0x00001000 // FIFO Full.
-#define ADC_SSFSTAT2_EMPTY 0x00000100 // FIFO Empty.
-#define ADC_SSFSTAT2_HPTR_M 0x000000F0 // FIFO Head Pointer.
-#define ADC_SSFSTAT2_TPTR_M 0x0000000F // FIFO Tail Pointer.
-#define ADC_SSFSTAT2_HPTR_S 4
-#define ADC_SSFSTAT2_TPTR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_SSMUX3 register.
-//
-//*****************************************************************************
-#define ADC_SSMUX3_MUX0_M 0x00000007 // 1st Sample Input Select.
-#define ADC_SSMUX3_MUX0_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_SSCTL3 register.
-//
-//*****************************************************************************
-#define ADC_SSCTL3_TS0 0x00000008 // 1st Sample Temp Sensor Select.
-#define ADC_SSCTL3_IE0 0x00000004 // 1st Sample Interrupt Enable.
-#define ADC_SSCTL3_END0 0x00000002 // 1st Sample is End of Sequence.
-#define ADC_SSCTL3_D0 0x00000001 // 1st Sample Diff Input Select.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_SSFIFO3 register.
-//
-//*****************************************************************************
-#define ADC_SSFIFO3_DATA_M 0x000003FF // Conversion Result Data.
-#define ADC_SSFIFO3_DATA_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_SSFSTAT3 register.
-//
-//*****************************************************************************
-#define ADC_SSFSTAT3_FULL 0x00001000 // FIFO Full.
-#define ADC_SSFSTAT3_EMPTY 0x00000100 // FIFO Empty.
-#define ADC_SSFSTAT3_HPTR_M 0x000000F0 // FIFO Head Pointer.
-#define ADC_SSFSTAT3_TPTR_M 0x0000000F // FIFO Tail Pointer.
-#define ADC_SSFSTAT3_HPTR_S 4
-#define ADC_SSFSTAT3_TPTR_S 0
-
-//*****************************************************************************
-//
-// The following definitions are deprecated.
-//
-//*****************************************************************************
-#ifndef DEPRECATED
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the ADC sequence register offsets.
-//
-//*****************************************************************************
-#define ADC_O_SEQ 0x00000040 // Offset to the first sequence
-#define ADC_O_SEQ_STEP 0x00000020 // Increment to the next sequence
-#define ADC_O_X_SSFSTAT 0x0000000C // FIFO status register
-#define ADC_O_X_SSFIFO 0x00000008 // Result FIFO register
-#define ADC_O_X_SSCTL 0x00000004 // Sample sequence control register
-#define ADC_O_X_SSMUX 0x00000000 // Multiplexer select register
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the ADC_EMUX
-// register.
-//
-//*****************************************************************************
-#define ADC_EMUX_EM3_MASK 0x0000F000 // Event mux 3 mask
-#define ADC_EMUX_EM2_MASK 0x00000F00 // Event mux 2 mask
-#define ADC_EMUX_EM1_MASK 0x000000F0 // Event mux 1 mask
-#define ADC_EMUX_EM0_MASK 0x0000000F // Event mux 0 mask
-#define ADC_EMUX_EM3_SHIFT 12 // The shift for the fourth event
-#define ADC_EMUX_EM2_SHIFT 8 // The shift for the third event
-#define ADC_EMUX_EM1_SHIFT 4 // The shift for the second event
-#define ADC_EMUX_EM0_SHIFT 0 // The shift for the first event
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the ADC_SSPRI
-// register.
-//
-//*****************************************************************************
-#define ADC_SSPRI_SS3_MASK 0x00003000 // Sequencer 3 priority mask
-#define ADC_SSPRI_SS2_MASK 0x00000300 // Sequencer 2 priority mask
-#define ADC_SSPRI_SS1_MASK 0x00000030 // Sequencer 1 priority mask
-#define ADC_SSPRI_SS0_MASK 0x00000003 // Sequencer 0 priority mask
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the ADC_SSMUX0,
-// ADC_SSMUX1, ADC_SSMUX2, and ADC_SSMUX3 registers. Not all fields are present
-// in all registers.
-//
-//*****************************************************************************
-#define ADC_SSMUX_MUX7_MASK 0x70000000 // 8th mux select mask
-#define ADC_SSMUX_MUX6_MASK 0x07000000 // 7th mux select mask
-#define ADC_SSMUX_MUX5_MASK 0x00700000 // 6th mux select mask
-#define ADC_SSMUX_MUX4_MASK 0x00070000 // 5th mux select mask
-#define ADC_SSMUX_MUX3_MASK 0x00007000 // 4th mux select mask
-#define ADC_SSMUX_MUX2_MASK 0x00000700 // 3rd mux select mask
-#define ADC_SSMUX_MUX1_MASK 0x00000070 // 2nd mux select mask
-#define ADC_SSMUX_MUX0_MASK 0x00000007 // 1st mux select mask
-#define ADC_SSMUX_MUX7_SHIFT 28
-#define ADC_SSMUX_MUX6_SHIFT 24
-#define ADC_SSMUX_MUX5_SHIFT 20
-#define ADC_SSMUX_MUX4_SHIFT 16
-#define ADC_SSMUX_MUX3_SHIFT 12
-#define ADC_SSMUX_MUX2_SHIFT 8
-#define ADC_SSMUX_MUX1_SHIFT 4
-#define ADC_SSMUX_MUX0_SHIFT 0
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the ADC_SSCTL0,
-// ADC_SSCTL1, ADC_SSCTL2, and ADC_SSCTL3 registers. Not all fields are present
-// in all registers.
-//
-//*****************************************************************************
-#define ADC_SSCTL_TS7 0x80000000 // 8th temperature sensor select
-#define ADC_SSCTL_IE7 0x40000000 // 8th interrupt enable
-#define ADC_SSCTL_END7 0x20000000 // 8th sequence end select
-#define ADC_SSCTL_D7 0x10000000 // 8th differential select
-#define ADC_SSCTL_TS6 0x08000000 // 7th temperature sensor select
-#define ADC_SSCTL_IE6 0x04000000 // 7th interrupt enable
-#define ADC_SSCTL_END6 0x02000000 // 7th sequence end select
-#define ADC_SSCTL_D6 0x01000000 // 7th differential select
-#define ADC_SSCTL_TS5 0x00800000 // 6th temperature sensor select
-#define ADC_SSCTL_IE5 0x00400000 // 6th interrupt enable
-#define ADC_SSCTL_END5 0x00200000 // 6th sequence end select
-#define ADC_SSCTL_D5 0x00100000 // 6th differential select
-#define ADC_SSCTL_TS4 0x00080000 // 5th temperature sensor select
-#define ADC_SSCTL_IE4 0x00040000 // 5th interrupt enable
-#define ADC_SSCTL_END4 0x00020000 // 5th sequence end select
-#define ADC_SSCTL_D4 0x00010000 // 5th differential select
-#define ADC_SSCTL_TS3 0x00008000 // 4th temperature sensor select
-#define ADC_SSCTL_IE3 0x00004000 // 4th interrupt enable
-#define ADC_SSCTL_END3 0x00002000 // 4th sequence end select
-#define ADC_SSCTL_D3 0x00001000 // 4th differential select
-#define ADC_SSCTL_TS2 0x00000800 // 3rd temperature sensor select
-#define ADC_SSCTL_IE2 0x00000400 // 3rd interrupt enable
-#define ADC_SSCTL_END2 0x00000200 // 3rd sequence end select
-#define ADC_SSCTL_D2 0x00000100 // 3rd differential select
-#define ADC_SSCTL_TS1 0x00000080 // 2nd temperature sensor select
-#define ADC_SSCTL_IE1 0x00000040 // 2nd interrupt enable
-#define ADC_SSCTL_END1 0x00000020 // 2nd sequence end select
-#define ADC_SSCTL_D1 0x00000010 // 2nd differential select
-#define ADC_SSCTL_TS0 0x00000008 // 1st temperature sensor select
-#define ADC_SSCTL_IE0 0x00000004 // 1st interrupt enable
-#define ADC_SSCTL_END0 0x00000002 // 1st sequence end select
-#define ADC_SSCTL_D0 0x00000001 // 1st differential select
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the ADC_SSFIFO0,
-// ADC_SSFIFO1, ADC_SSFIFO2, and ADC_SSFIFO3 registers.
-//
-//*****************************************************************************
-#define ADC_SSFIFO_DATA_MASK 0x000003FF // Sample data
-#define ADC_SSFIFO_DATA_SHIFT 0
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the ADC_SSFSTAT0,
-// ADC_SSFSTAT1, ADC_SSFSTAT2, and ADC_SSFSTAT3 registers.
-//
-//*****************************************************************************
-#define ADC_SSFSTAT_FULL 0x00001000 // FIFO is full
-#define ADC_SSFSTAT_EMPTY 0x00000100 // FIFO is empty
-#define ADC_SSFSTAT_HPTR 0x000000F0 // FIFO head pointer
-#define ADC_SSFSTAT_TPTR 0x0000000F // FIFO tail pointer
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the the interpretation of the data
-// in the SSFIFOx when the ADC TMLB is enabled.
-//
-//*****************************************************************************
-#define ADC_TMLB_CNT_M 0x000003C0 // Continuous Sample Counter.
-#define ADC_TMLB_CONT 0x00000020 // Continuation Sample Indicator.
-#define ADC_TMLB_DIFF 0x00000010 // Differential Sample Indicator.
-#define ADC_TMLB_TS 0x00000008 // Temp Sensor Sample Indicator.
-#define ADC_TMLB_MUX_M 0x00000007 // Analog Input Indicator.
-#define ADC_TMLB_CNT_S 6 // Sample counter shift
-#define ADC_TMLB_MUX_S 0 // Input channel number shift
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the loopback ADC
-// data.
-//
-//*****************************************************************************
-#define ADC_LB_CNT_MASK 0x000003C0 // Sample counter mask
-#define ADC_LB_CONT 0x00000020 // Continuation sample
-#define ADC_LB_DIFF 0x00000010 // Differential sample
-#define ADC_LB_TS 0x00000008 // Temperature sensor sample
-#define ADC_LB_MUX_MASK 0x00000007 // Input channel number mask
-#define ADC_LB_CNT_SHIFT 6 // Sample counter shift
-#define ADC_LB_MUX_SHIFT 0 // Input channel number shift
-
-#endif
-
-#endif // __HW_ADC_H__
+//*****************************************************************************
+//
+// hw_adc.h - Macros used when accessing the ADC hardware.
+//
+// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4781 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_ADC_H__
+#define __HW_ADC_H__
+
+//*****************************************************************************
+//
+// The following are defines for the ADC register offsets.
+//
+//*****************************************************************************
+#define ADC_O_ACTSS 0x00000000 // Active sample register
+#define ADC_O_RIS 0x00000004 // Raw interrupt status register
+#define ADC_O_IM 0x00000008 // Interrupt mask register
+#define ADC_O_ISC 0x0000000C // Interrupt status/clear register
+#define ADC_O_OSTAT 0x00000010 // Overflow status register
+#define ADC_O_EMUX 0x00000014 // Event multiplexer select reg.
+#define ADC_O_USTAT 0x00000018 // Underflow status register
+#define ADC_O_SSPRI 0x00000020 // Channel priority register
+#define ADC_O_PSSI 0x00000028 // Processor sample initiate reg.
+#define ADC_O_SAC 0x00000030 // Sample Averaging Control reg.
+#define ADC_O_DCISC 0x00000034 // ADC Digital Comparator Interrupt
+ // Status and Clear
+#define ADC_O_CTL 0x00000038 // ADC Control
+#define ADC_O_SSMUX0 0x00000040 // Multiplexer select 0 register
+#define ADC_O_SSCTL0 0x00000044 // Sample sequence control 0 reg.
+#define ADC_O_SSFIFO0 0x00000048 // Result FIFO 0 register
+#define ADC_O_SSFSTAT0 0x0000004C // FIFO 0 status register
+#define ADC_O_SSOP0 0x00000050 // ADC Sample Sequence 0 Operation
+#define ADC_O_SSDC0 0x00000054 // ADC Sample Sequence 0 Digital
+ // Comparator Select
+#define ADC_O_SSMUX1 0x00000060 // Multiplexer select 1 register
+#define ADC_O_SSCTL1 0x00000064 // Sample sequence control 1 reg.
+#define ADC_O_SSFIFO1 0x00000068 // Result FIFO 1 register
+#define ADC_O_SSFSTAT1 0x0000006C // FIFO 1 status register
+#define ADC_O_SSOP1 0x00000070 // ADC Sample Sequence 1 Operation
+#define ADC_O_SSDC1 0x00000074 // ADC Sample Sequence 1 Digital
+ // Comparator Select
+#define ADC_O_SSMUX2 0x00000080 // Multiplexer select 2 register
+#define ADC_O_SSCTL2 0x00000084 // Sample sequence control 2 reg.
+#define ADC_O_SSFIFO2 0x00000088 // Result FIFO 2 register
+#define ADC_O_SSFSTAT2 0x0000008C // FIFO 2 status register
+#define ADC_O_SSOP2 0x00000090 // ADC Sample Sequence 2 Operation
+#define ADC_O_SSDC2 0x00000094 // ADC Sample Sequence 2 Digital
+ // Comparator Select
+#define ADC_O_SSMUX3 0x000000A0 // Multiplexer select 3 register
+#define ADC_O_SSCTL3 0x000000A4 // Sample sequence control 3 reg.
+#define ADC_O_SSFIFO3 0x000000A8 // Result FIFO 3 register
+#define ADC_O_SSFSTAT3 0x000000AC // FIFO 3 status register
+#define ADC_O_SSOP3 0x000000B0 // ADC Sample Sequence 3 Operation
+#define ADC_O_SSDC3 0x000000B4 // ADC Sample Sequence 3 Digital
+ // Comparator Select
+#define ADC_O_TMLB 0x00000100 // Test mode loopback register
+#define ADC_O_DCRIC 0x00000D00 // ADC Digital Comparator Reset
+ // Initial Conditions
+#define ADC_O_DCCTL0 0x00000E00 // ADC Digital Comparator Control 0
+#define ADC_O_DCCTL1 0x00000E04 // ADC Digital Comparator Control 1
+#define ADC_O_DCCTL2 0x00000E08 // ADC Digital Comparator Control 2
+#define ADC_O_DCCTL3 0x00000E0C // ADC Digital Comparator Control 3
+#define ADC_O_DCCTL4 0x00000E10 // ADC Digital Comparator Control 4
+#define ADC_O_DCCTL5 0x00000E14 // ADC Digital Comparator Control 5
+#define ADC_O_DCCTL6 0x00000E18 // ADC Digital Comparator Control 6
+#define ADC_O_DCCTL7 0x00000E1C // ADC Digital Comparator Control 7
+#define ADC_O_DCCMP0 0x00000E40 // ADC Digital Comparator Range 0
+#define ADC_O_DCCMP1 0x00000E44 // ADC Digital Comparator Range 1
+#define ADC_O_DCCMP2 0x00000E48 // ADC Digital Comparator Range 2
+#define ADC_O_DCCMP3 0x00000E4C // ADC Digital Comparator Range 3
+#define ADC_O_DCCMP4 0x00000E50 // ADC Digital Comparator Range 4
+#define ADC_O_DCCMP5 0x00000E54 // ADC Digital Comparator Range 5
+#define ADC_O_DCCMP6 0x00000E58 // ADC Digital Comparator Range 6
+#define ADC_O_DCCMP7 0x00000E5C // ADC Digital Comparator Range 7
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_ACTSS register.
+//
+//*****************************************************************************
+#define ADC_ACTSS_ASEN3 0x00000008 // Sample sequence 3 enable
+#define ADC_ACTSS_ASEN2 0x00000004 // Sample sequence 2 enable
+#define ADC_ACTSS_ASEN1 0x00000002 // Sample sequence 1 enable
+#define ADC_ACTSS_ASEN0 0x00000001 // Sample sequence 0 enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_RIS register.
+//
+//*****************************************************************************
+#define ADC_RIS_INRDC 0x00010000 // Digital Comparator Raw Interrupt
+ // Status.
+#define ADC_RIS_INR3 0x00000008 // Sample sequence 3 interrupt
+#define ADC_RIS_INR2 0x00000004 // Sample sequence 2 interrupt
+#define ADC_RIS_INR1 0x00000002 // Sample sequence 1 interrupt
+#define ADC_RIS_INR0 0x00000001 // Sample sequence 0 interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_IM register.
+//
+//*****************************************************************************
+#define ADC_IM_DCONSS3 0x00080000 // Digital Comparator Interrupt on
+ // SS3.
+#define ADC_IM_DCONSS2 0x00040000 // Digital Comparator Interrupt on
+ // SS2.
+#define ADC_IM_DCONSS1 0x00020000 // Digital Comparator Interrupt on
+ // SS1.
+#define ADC_IM_DCONSS0 0x00010000 // Digital Comparator Interrupt on
+ // SS0.
+#define ADC_IM_MASK3 0x00000008 // Sample sequence 3 mask
+#define ADC_IM_MASK2 0x00000004 // Sample sequence 2 mask
+#define ADC_IM_MASK1 0x00000002 // Sample sequence 1 mask
+#define ADC_IM_MASK0 0x00000001 // Sample sequence 0 mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_ISC register.
+//
+//*****************************************************************************
+#define ADC_ISC_DCINSS3 0x00080000 // Digital Comparator Interrupt
+ // Status on SS3.
+#define ADC_ISC_DCINSS2 0x00040000 // Digital Comparator Interrupt
+ // Status on SS2.
+#define ADC_ISC_DCINSS1 0x00020000 // Digital Comparator Interrupt
+ // Status on SS1.
+#define ADC_ISC_DCINSS0 0x00010000 // Digital Comparator Interrupt
+ // Status on SS0.
+#define ADC_ISC_IN3 0x00000008 // Sample sequence 3 interrupt
+#define ADC_ISC_IN2 0x00000004 // Sample sequence 2 interrupt
+#define ADC_ISC_IN1 0x00000002 // Sample sequence 1 interrupt
+#define ADC_ISC_IN0 0x00000001 // Sample sequence 0 interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_OSTAT register.
+//
+//*****************************************************************************
+#define ADC_OSTAT_OV3 0x00000008 // Sample sequence 3 overflow
+#define ADC_OSTAT_OV2 0x00000004 // Sample sequence 2 overflow
+#define ADC_OSTAT_OV1 0x00000002 // Sample sequence 1 overflow
+#define ADC_OSTAT_OV0 0x00000001 // Sample sequence 0 overflow
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_EMUX register.
+//
+//*****************************************************************************
+#define ADC_EMUX_EM3_M 0x0000F000 // Event mux 3 mask
+#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Processor event
+#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog comparator 0 event
+#define ADC_EMUX_EM3_COMP1 0x00002000 // Analog comparator 1 event
+#define ADC_EMUX_EM3_COMP2 0x00003000 // Analog comparator 2 event
+#define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External event
+#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer event
+#define ADC_EMUX_EM3_PWM0 0x00006000 // PWM0 event
+#define ADC_EMUX_EM3_PWM1 0x00007000 // PWM1 event
+#define ADC_EMUX_EM3_PWM2 0x00008000 // PWM2 event
+#define ADC_EMUX_EM3_PWM3 0x00009000 // PWM3
+#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always event
+#define ADC_EMUX_EM2_M 0x00000F00 // Event mux 2 mask
+#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Processor event
+#define ADC_EMUX_EM2_COMP0 0x00000100 // Analog comparator 0 event
+#define ADC_EMUX_EM2_COMP1 0x00000200 // Analog comparator 1 event
+#define ADC_EMUX_EM2_COMP2 0x00000300 // Analog comparator 2 event
+#define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External event
+#define ADC_EMUX_EM2_TIMER 0x00000500 // Timer event
+#define ADC_EMUX_EM2_PWM0 0x00000600 // PWM0 event
+#define ADC_EMUX_EM2_PWM1 0x00000700 // PWM1 event
+#define ADC_EMUX_EM2_PWM2 0x00000800 // PWM2 event
+#define ADC_EMUX_EM2_PWM3 0x00000900 // PWM3
+#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always event
+#define ADC_EMUX_EM1_M 0x000000F0 // Event mux 1 mask
+#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Processor event
+#define ADC_EMUX_EM1_COMP0 0x00000010 // Analog comparator 0 event
+#define ADC_EMUX_EM1_COMP1 0x00000020 // Analog comparator 1 event
+#define ADC_EMUX_EM1_COMP2 0x00000030 // Analog comparator 2 event
+#define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External event
+#define ADC_EMUX_EM1_TIMER 0x00000050 // Timer event
+#define ADC_EMUX_EM1_PWM0 0x00000060 // PWM0 event
+#define ADC_EMUX_EM1_PWM1 0x00000070 // PWM1 event
+#define ADC_EMUX_EM1_PWM2 0x00000080 // PWM2 event
+#define ADC_EMUX_EM1_PWM3 0x00000090 // PWM3
+#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always event
+#define ADC_EMUX_EM0_M 0x0000000F // Event mux 0 mask
+#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Processor event
+#define ADC_EMUX_EM0_COMP0 0x00000001 // Analog comparator 0 event
+#define ADC_EMUX_EM0_COMP1 0x00000002 // Analog comparator 1 event
+#define ADC_EMUX_EM0_COMP2 0x00000003 // Analog comparator 2 event
+#define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External event
+#define ADC_EMUX_EM0_TIMER 0x00000005 // Timer event
+#define ADC_EMUX_EM0_PWM0 0x00000006 // PWM0 event
+#define ADC_EMUX_EM0_PWM1 0x00000007 // PWM1 event
+#define ADC_EMUX_EM0_PWM2 0x00000008 // PWM2 event
+#define ADC_EMUX_EM0_PWM3 0x00000009 // PWM3
+#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always event
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_USTAT register.
+//
+//*****************************************************************************
+#define ADC_USTAT_UV3 0x00000008 // Sample sequence 3 underflow
+#define ADC_USTAT_UV2 0x00000004 // Sample sequence 2 underflow
+#define ADC_USTAT_UV1 0x00000002 // Sample sequence 1 underflow
+#define ADC_USTAT_UV0 0x00000001 // Sample sequence 0 underflow
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_SSPRI register.
+//
+//*****************************************************************************
+#define ADC_SSPRI_SS3_M 0x00003000 // Sequencer 3 priority mask
+#define ADC_SSPRI_SS3_1ST 0x00000000 // First priority
+#define ADC_SSPRI_SS3_2ND 0x00001000 // Second priority
+#define ADC_SSPRI_SS3_3RD 0x00002000 // Third priority
+#define ADC_SSPRI_SS3_4TH 0x00003000 // Fourth priority
+#define ADC_SSPRI_SS2_M 0x00000300 // Sequencer 2 priority mask
+#define ADC_SSPRI_SS2_1ST 0x00000000 // First priority
+#define ADC_SSPRI_SS2_2ND 0x00000100 // Second priority
+#define ADC_SSPRI_SS2_3RD 0x00000200 // Third priority
+#define ADC_SSPRI_SS2_4TH 0x00000300 // Fourth priority
+#define ADC_SSPRI_SS1_M 0x00000030 // Sequencer 1 priority mask
+#define ADC_SSPRI_SS1_1ST 0x00000000 // First priority
+#define ADC_SSPRI_SS1_2ND 0x00000010 // Second priority
+#define ADC_SSPRI_SS1_3RD 0x00000020 // Third priority
+#define ADC_SSPRI_SS1_4TH 0x00000030 // Fourth priority
+#define ADC_SSPRI_SS0_M 0x00000003 // Sequencer 0 priority mask
+#define ADC_SSPRI_SS0_1ST 0x00000000 // First priority
+#define ADC_SSPRI_SS0_2ND 0x00000001 // Second priority
+#define ADC_SSPRI_SS0_3RD 0x00000002 // Third priority
+#define ADC_SSPRI_SS0_4TH 0x00000003 // Fourth priority
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_PSSI register.
+//
+//*****************************************************************************
+#define ADC_PSSI_GSYNC 0x80000000 // Global Synchronize.
+#define ADC_PSSI_SYNCWAIT 0x08000000 // Synchronize Wait.
+#define ADC_PSSI_SS3 0x00000008 // Trigger sample sequencer 3
+#define ADC_PSSI_SS2 0x00000004 // Trigger sample sequencer 2
+#define ADC_PSSI_SS1 0x00000002 // Trigger sample sequencer 1
+#define ADC_PSSI_SS0 0x00000001 // Trigger sample sequencer 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_SAC register.
+//
+//*****************************************************************************
+#define ADC_SAC_AVG_M 0x00000007 // Hardware Averaging Control.
+#define ADC_SAC_AVG_64X 0x00000006 // 64x hardware oversampling
+#define ADC_SAC_AVG_32X 0x00000005 // 32x hardware oversampling
+#define ADC_SAC_AVG_16X 0x00000004 // 16x hardware oversampling
+#define ADC_SAC_AVG_8X 0x00000003 // 8x hardware oversampling
+#define ADC_SAC_AVG_4X 0x00000002 // 4x hardware oversampling
+#define ADC_SAC_AVG_2X 0x00000001 // 2x hardware oversampling
+#define ADC_SAC_AVG_OFF 0x00000000 // No hardware oversampling
+
+//*****************************************************************************
+//
+// The following are defines for the the interpretation of the data in the
+// SSFIFOx when the ADC TMLB is enabled.
+//
+//*****************************************************************************
+#define ADC_SSFIFO_TMLB_CNT_M 0x000003C0 // Continuous Sample Counter.
+#define ADC_SSFIFO_TMLB_CONT 0x00000020 // Continuation Sample Indicator.
+#define ADC_SSFIFO_TMLB_DIFF 0x00000010 // Differential Sample Indicator.
+#define ADC_SSFIFO_TMLB_TS 0x00000008 // Temp Sensor Sample Indicator.
+#define ADC_SSFIFO_TMLB_MUX_M 0x00000007 // Analog Input Indicator.
+#define ADC_SSFIFO_TMLB_CNT_S 6 // Sample counter shift
+#define ADC_SSFIFO_TMLB_MUX_S 0 // Input channel number shift
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_TMLB register.
+//
+//*****************************************************************************
+#define ADC_TMLB_LB 0x00000001 // Loopback control signals
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX0 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX0_MUX7_M 0xF0000000 // 8th Sample Input Select.
+#define ADC_SSMUX0_MUX6_M 0x0F000000 // 7th Sample Input Select.
+#define ADC_SSMUX0_MUX5_M 0x00F00000 // 6th Sample Input Select.
+#define ADC_SSMUX0_MUX4_M 0x000F0000 // 5th Sample Input Select.
+#define ADC_SSMUX0_MUX3_M 0x0000F000 // 4th Sample Input Select.
+#define ADC_SSMUX0_MUX2_M 0x00000F00 // 3rd Sample Input Select.
+#define ADC_SSMUX0_MUX1_M 0x000000F0 // 2nd Sample Input Select.
+#define ADC_SSMUX0_MUX0_M 0x0000000F // 1st Sample Input Select.
+#define ADC_SSMUX0_MUX7_S 28
+#define ADC_SSMUX0_MUX6_S 24
+#define ADC_SSMUX0_MUX5_S 20
+#define ADC_SSMUX0_MUX4_S 16
+#define ADC_SSMUX0_MUX3_S 12
+#define ADC_SSMUX0_MUX2_S 8
+#define ADC_SSMUX0_MUX1_S 4
+#define ADC_SSMUX0_MUX0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL0 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL0_TS7 0x80000000 // 8th Sample Temp Sensor Select.
+#define ADC_SSCTL0_IE7 0x40000000 // 8th Sample Interrupt Enable.
+#define ADC_SSCTL0_END7 0x20000000 // 8th Sample is End of Sequence.
+#define ADC_SSCTL0_D7 0x10000000 // 8th Sample Diff Input Select.
+#define ADC_SSCTL0_TS6 0x08000000 // 7th Sample Temp Sensor Select.
+#define ADC_SSCTL0_IE6 0x04000000 // 7th Sample Interrupt Enable.
+#define ADC_SSCTL0_END6 0x02000000 // 7th Sample is End of Sequence.
+#define ADC_SSCTL0_D6 0x01000000 // 7th Sample Diff Input Select.
+#define ADC_SSCTL0_TS5 0x00800000 // 6th Sample Temp Sensor Select.
+#define ADC_SSCTL0_IE5 0x00400000 // 6th Sample Interrupt Enable.
+#define ADC_SSCTL0_END5 0x00200000 // 6th Sample is End of Sequence.
+#define ADC_SSCTL0_D5 0x00100000 // 6th Sample Diff Input Select.
+#define ADC_SSCTL0_TS4 0x00080000 // 5th Sample Temp Sensor Select.
+#define ADC_SSCTL0_IE4 0x00040000 // 5th Sample Interrupt Enable.
+#define ADC_SSCTL0_END4 0x00020000 // 5th Sample is End of Sequence.
+#define ADC_SSCTL0_D4 0x00010000 // 5th Sample Diff Input Select.
+#define ADC_SSCTL0_TS3 0x00008000 // 4th Sample Temp Sensor Select.
+#define ADC_SSCTL0_IE3 0x00004000 // 4th Sample Interrupt Enable.
+#define ADC_SSCTL0_END3 0x00002000 // 4th Sample is End of Sequence.
+#define ADC_SSCTL0_D3 0x00001000 // 4th Sample Diff Input Select.
+#define ADC_SSCTL0_TS2 0x00000800 // 3rd Sample Temp Sensor Select.
+#define ADC_SSCTL0_IE2 0x00000400 // 3rd Sample Interrupt Enable.
+#define ADC_SSCTL0_END2 0x00000200 // 3rd Sample is End of Sequence.
+#define ADC_SSCTL0_D2 0x00000100 // 3rd Sample Diff Input Select.
+#define ADC_SSCTL0_TS1 0x00000080 // 2nd Sample Temp Sensor Select.
+#define ADC_SSCTL0_IE1 0x00000040 // 2nd Sample Interrupt Enable.
+#define ADC_SSCTL0_END1 0x00000020 // 2nd Sample is End of Sequence.
+#define ADC_SSCTL0_D1 0x00000010 // 2nd Sample Diff Input Select.
+#define ADC_SSCTL0_TS0 0x00000008 // 1st Sample Temp Sensor Select.
+#define ADC_SSCTL0_IE0 0x00000004 // 1st Sample Interrupt Enable.
+#define ADC_SSCTL0_END0 0x00000002 // 1st Sample is End of Sequence.
+#define ADC_SSCTL0_D0 0x00000001 // 1st Sample Diff Input Select.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO0 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO0_DATA_M 0x000003FF // Conversion Result Data.
+#define ADC_SSFIFO0_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT0 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT0_FULL 0x00001000 // FIFO Full.
+#define ADC_SSFSTAT0_EMPTY 0x00000100 // FIFO Empty.
+#define ADC_SSFSTAT0_HPTR_M 0x000000F0 // FIFO Head Pointer.
+#define ADC_SSFSTAT0_TPTR_M 0x0000000F // FIFO Tail Pointer.
+#define ADC_SSFSTAT0_HPTR_S 4
+#define ADC_SSFSTAT0_TPTR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX1 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX1_MUX3_M 0x0000F000 // 4th Sample Input Select.
+#define ADC_SSMUX1_MUX2_M 0x00000F00 // 3rd Sample Input Select.
+#define ADC_SSMUX1_MUX1_M 0x000000F0 // 2nd Sample Input Select.
+#define ADC_SSMUX1_MUX0_M 0x0000000F // 1st Sample Input Select.
+#define ADC_SSMUX1_MUX3_S 12
+#define ADC_SSMUX1_MUX2_S 8
+#define ADC_SSMUX1_MUX1_S 4
+#define ADC_SSMUX1_MUX0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL1 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL1_TS3 0x00008000 // 4th Sample Temp Sensor Select.
+#define ADC_SSCTL1_IE3 0x00004000 // 4th Sample Interrupt Enable.
+#define ADC_SSCTL1_END3 0x00002000 // 4th Sample is End of Sequence.
+#define ADC_SSCTL1_D3 0x00001000 // 4th Sample Diff Input Select.
+#define ADC_SSCTL1_TS2 0x00000800 // 3rd Sample Temp Sensor Select.
+#define ADC_SSCTL1_IE2 0x00000400 // 3rd Sample Interrupt Enable.
+#define ADC_SSCTL1_END2 0x00000200 // 3rd Sample is End of Sequence.
+#define ADC_SSCTL1_D2 0x00000100 // 3rd Sample Diff Input Select.
+#define ADC_SSCTL1_TS1 0x00000080 // 2nd Sample Temp Sensor Select.
+#define ADC_SSCTL1_IE1 0x00000040 // 2nd Sample Interrupt Enable.
+#define ADC_SSCTL1_END1 0x00000020 // 2nd Sample is End of Sequence.
+#define ADC_SSCTL1_D1 0x00000010 // 2nd Sample Diff Input Select.
+#define ADC_SSCTL1_TS0 0x00000008 // 1st Sample Temp Sensor Select.
+#define ADC_SSCTL1_IE0 0x00000004 // 1st Sample Interrupt Enable.
+#define ADC_SSCTL1_END0 0x00000002 // 1st Sample is End of Sequence.
+#define ADC_SSCTL1_D0 0x00000001 // 1st Sample Diff Input Select.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO1 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO1_DATA_M 0x000003FF // Conversion Result Data.
+#define ADC_SSFIFO1_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT1 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT1_FULL 0x00001000 // FIFO Full.
+#define ADC_SSFSTAT1_EMPTY 0x00000100 // FIFO Empty.
+#define ADC_SSFSTAT1_HPTR_M 0x000000F0 // FIFO Head Pointer.
+#define ADC_SSFSTAT1_TPTR_M 0x0000000F // FIFO Tail Pointer.
+#define ADC_SSFSTAT1_HPTR_S 4
+#define ADC_SSFSTAT1_TPTR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX2 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX2_MUX3_M 0x0000F000 // 4th Sample Input Select.
+#define ADC_SSMUX2_MUX2_M 0x00000F00 // 3rd Sample Input Select.
+#define ADC_SSMUX2_MUX1_M 0x000000F0 // 2nd Sample Input Select.
+#define ADC_SSMUX2_MUX0_M 0x0000000F // 1st Sample Input Select.
+#define ADC_SSMUX2_MUX3_S 12
+#define ADC_SSMUX2_MUX2_S 8
+#define ADC_SSMUX2_MUX1_S 4
+#define ADC_SSMUX2_MUX0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL2 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL2_TS3 0x00008000 // 4th Sample Temp Sensor Select.
+#define ADC_SSCTL2_IE3 0x00004000 // 4th Sample Interrupt Enable.
+#define ADC_SSCTL2_END3 0x00002000 // 4th Sample is End of Sequence.
+#define ADC_SSCTL2_D3 0x00001000 // 4th Sample Diff Input Select.
+#define ADC_SSCTL2_TS2 0x00000800 // 3rd Sample Temp Sensor Select.
+#define ADC_SSCTL2_IE2 0x00000400 // 3rd Sample Interrupt Enable.
+#define ADC_SSCTL2_END2 0x00000200 // 3rd Sample is End of Sequence.
+#define ADC_SSCTL2_D2 0x00000100 // 3rd Sample Diff Input Select.
+#define ADC_SSCTL2_TS1 0x00000080 // 2nd Sample Temp Sensor Select.
+#define ADC_SSCTL2_IE1 0x00000040 // 2nd Sample Interrupt Enable.
+#define ADC_SSCTL2_END1 0x00000020 // 2nd Sample is End of Sequence.
+#define ADC_SSCTL2_D1 0x00000010 // 2nd Sample Diff Input Select.
+#define ADC_SSCTL2_TS0 0x00000008 // 1st Sample Temp Sensor Select.
+#define ADC_SSCTL2_IE0 0x00000004 // 1st Sample Interrupt Enable.
+#define ADC_SSCTL2_END0 0x00000002 // 1st Sample is End of Sequence.
+#define ADC_SSCTL2_D0 0x00000001 // 1st Sample Diff Input Select.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO2 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO2_DATA_M 0x000003FF // Conversion Result Data.
+#define ADC_SSFIFO2_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT2 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT2_FULL 0x00001000 // FIFO Full.
+#define ADC_SSFSTAT2_EMPTY 0x00000100 // FIFO Empty.
+#define ADC_SSFSTAT2_HPTR_M 0x000000F0 // FIFO Head Pointer.
+#define ADC_SSFSTAT2_TPTR_M 0x0000000F // FIFO Tail Pointer.
+#define ADC_SSFSTAT2_HPTR_S 4
+#define ADC_SSFSTAT2_TPTR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX3 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX3_MUX0_M 0x0000000F // 1st Sample Input Select.
+#define ADC_SSMUX3_MUX0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL3 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL3_TS0 0x00000008 // 1st Sample Temp Sensor Select.
+#define ADC_SSCTL3_IE0 0x00000004 // 1st Sample Interrupt Enable.
+#define ADC_SSCTL3_END0 0x00000002 // 1st Sample is End of Sequence.
+#define ADC_SSCTL3_D0 0x00000001 // 1st Sample Diff Input Select.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO3 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO3_DATA_M 0x000003FF // Conversion Result Data.
+#define ADC_SSFIFO3_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT3 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT3_FULL 0x00001000 // FIFO Full.
+#define ADC_SSFSTAT3_EMPTY 0x00000100 // FIFO Empty.
+#define ADC_SSFSTAT3_HPTR_M 0x000000F0 // FIFO Head Pointer.
+#define ADC_SSFSTAT3_TPTR_M 0x0000000F // FIFO Tail Pointer.
+#define ADC_SSFSTAT3_HPTR_S 4
+#define ADC_SSFSTAT3_TPTR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSDC0 register.
+//
+//*****************************************************************************
+#define ADC_SSDC0_S7DCSEL_M 0xF0000000 // Sample 7 Digital Comparator
+ // Select.
+#define ADC_SSDC0_S6DCSEL_M 0x0F000000 // Sample 6 Digital Comparator
+ // Select.
+#define ADC_SSDC0_S5DCSEL_M 0x00F00000 // Sample 5 Digital Comparator
+ // Select.
+#define ADC_SSDC0_S4DCSEL_M 0x000F0000 // Sample 4 Digital Comparator
+ // Select.
+#define ADC_SSDC0_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator
+ // Select.
+#define ADC_SSDC0_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator
+ // Select.
+#define ADC_SSDC0_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator
+ // Select.
+#define ADC_SSDC0_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator
+ // Select.
+#define ADC_SSDC0_S6DCSEL_S 24
+#define ADC_SSDC0_S5DCSEL_S 20
+#define ADC_SSDC0_S4DCSEL_S 16
+#define ADC_SSDC0_S3DCSEL_S 12
+#define ADC_SSDC0_S2DCSEL_S 8
+#define ADC_SSDC0_S1DCSEL_S 4
+#define ADC_SSDC0_S0DCSEL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSDC1 register.
+//
+//*****************************************************************************
+#define ADC_SSDC1_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator
+ // Select.
+#define ADC_SSDC1_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator
+ // Select.
+#define ADC_SSDC1_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator
+ // Select.
+#define ADC_SSDC1_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator
+ // Select.
+#define ADC_SSDC1_S2DCSEL_S 8
+#define ADC_SSDC1_S1DCSEL_S 4
+#define ADC_SSDC1_S0DCSEL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSDC2 register.
+//
+//*****************************************************************************
+#define ADC_SSDC2_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator
+ // Select.
+#define ADC_SSDC2_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator
+ // Select.
+#define ADC_SSDC2_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator
+ // Select.
+#define ADC_SSDC2_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator
+ // Select.
+#define ADC_SSDC2_S2DCSEL_S 8
+#define ADC_SSDC2_S1DCSEL_S 4
+#define ADC_SSDC2_S0DCSEL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSDC3 register.
+//
+//*****************************************************************************
+#define ADC_SSDC3_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator
+ // Select.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCISC register.
+//
+//*****************************************************************************
+#define ADC_DCISC_DCINT7 0x00000080 // Digital Comparator 7 Interrupt
+ // Status and Clear.
+#define ADC_DCISC_DCINT6 0x00000040 // Digital Comparator 6 Interrupt
+ // Status and Clear.
+#define ADC_DCISC_DCINT5 0x00000020 // Digital Comparator 5 Interrupt
+ // Status and Clear.
+#define ADC_DCISC_DCINT4 0x00000010 // Digital Comparator 4 Interrupt
+ // Status and Clear.
+#define ADC_DCISC_DCINT3 0x00000008 // Digital Comparator 3 Interrupt
+ // Status and Clear.
+#define ADC_DCISC_DCINT2 0x00000004 // Digital Comparator 2 Interrupt
+ // Status and Clear.
+#define ADC_DCISC_DCINT1 0x00000002 // Digital Comparator 1 Interrupt
+ // Status and Clear.
+#define ADC_DCISC_DCINT0 0x00000001 // Digital Comparator 0 Interrupt
+ // Status and Clear.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSOP0 register.
+//
+//*****************************************************************************
+#define ADC_SSOP0_S7DCOP 0x10000000 // Sample 7 Digital Comparator
+ // Operation.
+#define ADC_SSOP0_S6DCOP 0x01000000 // Sample 6 Digital Comparator
+ // Operation.
+#define ADC_SSOP0_S5DCOP 0x00100000 // Sample 5 Digital Comparator
+ // Operation.
+#define ADC_SSOP0_S4DCOP 0x00010000 // Sample 4 Digital Comparator
+ // Operation.
+#define ADC_SSOP0_S3DCOP 0x00001000 // Sample 3 Digital Comparator
+ // Operation.
+#define ADC_SSOP0_S2DCOP 0x00000100 // Sample 2 Digital Comparator
+ // Operation.
+#define ADC_SSOP0_S1DCOP 0x00000010 // Sample 1 Digital Comparator
+ // Operation.
+#define ADC_SSOP0_S0DCOP 0x00000001 // Sample 0 Digital Comparator
+ // Operation.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSOP1 register.
+//
+//*****************************************************************************
+#define ADC_SSOP1_S3DCOP 0x00001000 // Sample 7 Digital Comparator
+ // Operation.
+#define ADC_SSOP1_S2DCOP 0x00000100 // Sample 2 Digital Comparator
+ // Operation.
+#define ADC_SSOP1_S1DCOP 0x00000010 // Sample 1 Digital Comparator
+ // Operation.
+#define ADC_SSOP1_S0DCOP 0x00000001 // Sample 0 Digital Comparator
+ // Operation.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSOP2 register.
+//
+//*****************************************************************************
+#define ADC_SSOP2_S3DCOP 0x00001000 // Sample 7 Digital Comparator
+ // Operation.
+#define ADC_SSOP2_S2DCOP 0x00000100 // Sample 2 Digital Comparator
+ // Operation.
+#define ADC_SSOP2_S1DCOP 0x00000010 // Sample 1 Digital Comparator
+ // Operation.
+#define ADC_SSOP2_S0DCOP 0x00000001 // Sample 0 Digital Comparator
+ // Operation.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSOP3 register.
+//
+//*****************************************************************************
+#define ADC_SSOP3_S0DCOP 0x00000001 // Sample 7 Digital Comparator
+ // Operation.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCRIC register.
+//
+//*****************************************************************************
+#define ADC_DCRIC_DCTRIG7 0x00800000 // Digital Comparator Trigger 7.
+#define ADC_DCRIC_DCTRIG6 0x00400000 // Digital Comparator Trigger 6.
+#define ADC_DCRIC_DCTRIG5 0x00200000 // Digital Comparator Trigger 5.
+#define ADC_DCRIC_DCTRIG4 0x00100000 // Digital Comparator Trigger 4.
+#define ADC_DCRIC_DCTRIG3 0x00080000 // Digital Comparator Trigger 3.
+#define ADC_DCRIC_DCTRIG2 0x00040000 // Digital Comparator Trigger 2.
+#define ADC_DCRIC_DCTRIG1 0x00020000 // Digital Comparator Trigger 1.
+#define ADC_DCRIC_DCTRIG0 0x00010000 // Digital Comparator Trigger 0.
+#define ADC_DCRIC_DCINT7 0x00000080 // Digital Comparator Interrupt 7.
+#define ADC_DCRIC_DCINT6 0x00000040 // Digital Comparator Interrupt 6.
+#define ADC_DCRIC_DCINT5 0x00000020 // Digital Comparator Interrupt 5.
+#define ADC_DCRIC_DCINT4 0x00000010 // Digital Comparator Interrupt 4.
+#define ADC_DCRIC_DCINT3 0x00000008 // Digital Comparator Interrupt 3.
+#define ADC_DCRIC_DCINT2 0x00000004 // Digital Comparator Interrupt 2.
+#define ADC_DCRIC_DCINT1 0x00000002 // Digital Comparator Interrupt 1.
+#define ADC_DCRIC_DCINT0 0x00000001 // Digital Comparator Interrupt 0.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL0 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL0_CTE 0x00001000 // Comparison Trigger Enable.
+#define ADC_DCCTL0_CTC_M 0x00000C00 // Comparison Trigger Condition.
+#define ADC_DCCTL0_CTC_LOW 0x00000000 // CV < COMP0 and < COMP1
+#define ADC_DCCTL0_CTC_MID 0x00000400 // COMP0 >= CV < COMP1
+#define ADC_DCCTL0_CTC_HIGH 0x00000C00 // CV <= COMP0 and <= COMP1
+#define ADC_DCCTL0_CTM_M 0x00000300 // Comparison Trigger Mode.
+#define ADC_DCCTL0_CTM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL0_CTM_ONCE 0x00000100 // Once
+#define ADC_DCCTL0_CTM_HALWAYS 0x00000200 // Hysteresis always
+#define ADC_DCCTL0_CTM_HONCE 0x00000300 // Hysteresis once
+#define ADC_DCCTL0_CIE 0x00000010 // Comparison Interrupt Enable.
+#define ADC_DCCTL0_CIC_M 0x0000000C // Comparison Interrupt Condition.
+#define ADC_DCCTL0_CIC_LOW 0x00000000 // CV < COMP0 and < COMP1
+#define ADC_DCCTL0_CIC_MID 0x00000004 // COMP0 >= CV < COMP1
+#define ADC_DCCTL0_CIC_HIGH 0x0000000C // CV <= COMP0 and <= COMP1
+#define ADC_DCCTL0_CIM_M 0x00000003 // Comparison Interrupt Mode.
+#define ADC_DCCTL0_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL0_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL0_CIM_HALWAYS 0x00000002 // Hysteresis always
+#define ADC_DCCTL0_CIM_HONCE 0x00000003 // Hysteresis once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL1 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL1_CTE 0x00001000 // Comparison Trigger Enable.
+#define ADC_DCCTL1_CTC_M 0x00000C00 // Comparison Trigger Condition.
+#define ADC_DCCTL1_CTC_LOW 0x00000000 // CV < COMP0 and < COMP1
+#define ADC_DCCTL1_CTC_MID 0x00000400 // COMP0 >= CV < COMP1
+#define ADC_DCCTL1_CTC_HIGH 0x00000C00 // CV <= COMP0 and <= COMP1
+#define ADC_DCCTL1_CTM_M 0x00000300 // Comparison Trigger Mode.
+#define ADC_DCCTL1_CTM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL1_CTM_ONCE 0x00000100 // Once
+#define ADC_DCCTL1_CTM_HALWAYS 0x00000200 // Hysteresis always
+#define ADC_DCCTL1_CTM_HONCE 0x00000300 // Hysteresis once
+#define ADC_DCCTL1_CIE 0x00000010 // Comparison Interrupt Enable.
+#define ADC_DCCTL1_CIC_M 0x0000000C // Comparison Interrupt Condition.
+#define ADC_DCCTL1_CIC_LOW 0x00000000 // CV < COMP0 and < COMP1
+#define ADC_DCCTL1_CIC_MID 0x00000004 // COMP0 >= CV < COMP1
+#define ADC_DCCTL1_CIC_HIGH 0x0000000C // CV <= COMP0 and <= COMP1
+#define ADC_DCCTL1_CIM_M 0x00000003 // Comparison Interrupt Mode.
+#define ADC_DCCTL1_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL1_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL1_CIM_HALWAYS 0x00000002 // Hysteresis always
+#define ADC_DCCTL1_CIM_HONCE 0x00000003 // Hysteresis once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL2 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL2_CTE 0x00001000 // Comparison Trigger Enable.
+#define ADC_DCCTL2_CTC_M 0x00000C00 // Comparison Trigger Condition.
+#define ADC_DCCTL2_CTC_LOW 0x00000000 // CV < COMP0 and < COMP1
+#define ADC_DCCTL2_CTC_MID 0x00000400 // COMP0 >= CV < COMP1
+#define ADC_DCCTL2_CTC_HIGH 0x00000C00 // CV <= COMP0 and <= COMP1
+#define ADC_DCCTL2_CTM_M 0x00000300 // Comparison Trigger Mode.
+#define ADC_DCCTL2_CTM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL2_CTM_ONCE 0x00000100 // Once
+#define ADC_DCCTL2_CTM_HALWAYS 0x00000200 // Hysteresis always
+#define ADC_DCCTL2_CTM_HONCE 0x00000300 // Hysteresis once
+#define ADC_DCCTL2_CIE 0x00000010 // Comparison Interrupt Enable.
+#define ADC_DCCTL2_CIC_M 0x0000000C // Comparison Interrupt Condition.
+#define ADC_DCCTL2_CIC_LOW 0x00000000 // CV < COMP0 and < COMP1
+#define ADC_DCCTL2_CIC_MID 0x00000004 // COMP0 >= CV < COMP1
+#define ADC_DCCTL2_CIC_HIGH 0x0000000C // CV <= COMP0 and <= COMP1
+#define ADC_DCCTL2_CIM_M 0x00000003 // Comparison Interrupt Mode.
+#define ADC_DCCTL2_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL2_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL2_CIM_HALWAYS 0x00000002 // Hysteresis always
+#define ADC_DCCTL2_CIM_HONCE 0x00000003 // Hysteresis once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL3 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL3_CTE 0x00001000 // Comparison Trigger Enable.
+#define ADC_DCCTL3_CTC_M 0x00000C00 // Comparison Trigger Condition.
+#define ADC_DCCTL3_CTC_LOW 0x00000000 // CV < COMP0 and < COMP1
+#define ADC_DCCTL3_CTC_MID 0x00000400 // COMP0 >= CV < COMP1
+#define ADC_DCCTL3_CTC_HIGH 0x00000C00 // CV <= COMP0 and <= COMP1
+#define ADC_DCCTL3_CTM_M 0x00000300 // Comparison Trigger Mode.
+#define ADC_DCCTL3_CTM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL3_CTM_ONCE 0x00000100 // Once
+#define ADC_DCCTL3_CTM_HALWAYS 0x00000200 // Hysteresis always
+#define ADC_DCCTL3_CTM_HONCE 0x00000300 // Hysteresis once
+#define ADC_DCCTL3_CIE 0x00000010 // Comparison Interrupt Enable.
+#define ADC_DCCTL3_CIC_M 0x0000000C // Comparison Interrupt Condition.
+#define ADC_DCCTL3_CIC_LOW 0x00000000 // CV < COMP0 and < COMP1
+#define ADC_DCCTL3_CIC_MID 0x00000004 // COMP0 >= CV < COMP1
+#define ADC_DCCTL3_CIC_HIGH 0x0000000C // CV <= COMP0 and <= COMP1
+#define ADC_DCCTL3_CIM_M 0x00000003 // Comparison Interrupt Mode.
+#define ADC_DCCTL3_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL3_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL3_CIM_HALWAYS 0x00000002 // Hysteresis always
+#define ADC_DCCTL3_CIM_HONCE 0x00000003 // Hysteresis once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL4 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL4_CTE 0x00001000 // Comparison Trigger Enable.
+#define ADC_DCCTL4_CTC_M 0x00000C00 // Comparison Trigger Condition.
+#define ADC_DCCTL4_CTC_LOW 0x00000000 // CV < COMP0 and < COMP1
+#define ADC_DCCTL4_CTC_MID 0x00000400 // COMP0 >= CV < COMP1
+#define ADC_DCCTL4_CTC_HIGH 0x00000C00 // CV <= COMP0 and <= COMP1
+#define ADC_DCCTL4_CTM_M 0x00000300 // Comparison Trigger Mode.
+#define ADC_DCCTL4_CTM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL4_CTM_ONCE 0x00000100 // Once
+#define ADC_DCCTL4_CTM_HALWAYS 0x00000200 // Hysteresis always
+#define ADC_DCCTL4_CTM_HONCE 0x00000300 // Hysteresis once
+#define ADC_DCCTL4_CIE 0x00000010 // Comparison Interrupt Enable.
+#define ADC_DCCTL4_CIC_M 0x0000000C // Comparison Interrupt Condition.
+#define ADC_DCCTL4_CIC_LOW 0x00000000 // CV < COMP0 and < COMP1
+#define ADC_DCCTL4_CIC_MID 0x00000004 // COMP0 >= CV < COMP1
+#define ADC_DCCTL4_CIC_HIGH 0x0000000C // CV <= COMP0 and <= COMP1
+#define ADC_DCCTL4_CIM_M 0x00000003 // Comparison Interrupt Mode.
+#define ADC_DCCTL4_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL4_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL4_CIM_HALWAYS 0x00000002 // Hysteresis always
+#define ADC_DCCTL4_CIM_HONCE 0x00000003 // Hysteresis once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL5 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL5_CTE 0x00001000 // Comparison Trigger Enable.
+#define ADC_DCCTL5_CTC_M 0x00000C00 // Comparison Trigger Condition.
+#define ADC_DCCTL5_CTC_LOW 0x00000000 // CV < COMP0 and < COMP1
+#define ADC_DCCTL5_CTC_MID 0x00000400 // COMP0 >= CV < COMP1
+#define ADC_DCCTL5_CTC_HIGH 0x00000C00 // CV <= COMP0 and <= COMP1
+#define ADC_DCCTL5_CTM_M 0x00000300 // Comparison Trigger Mode.
+#define ADC_DCCTL5_CTM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL5_CTM_ONCE 0x00000100 // Once
+#define ADC_DCCTL5_CTM_HALWAYS 0x00000200 // Hysteresis always
+#define ADC_DCCTL5_CTM_HONCE 0x00000300 // Hysteresis once
+#define ADC_DCCTL5_CIE 0x00000010 // Comparison Interrupt Enable.
+#define ADC_DCCTL5_CIC_M 0x0000000C // Comparison Interrupt Condition.
+#define ADC_DCCTL5_CIC_LOW 0x00000000 // CV < COMP0 and < COMP1
+#define ADC_DCCTL5_CIC_MID 0x00000004 // COMP0 >= CV < COMP1
+#define ADC_DCCTL5_CIC_HIGH 0x0000000C // CV <= COMP0 and <= COMP1
+#define ADC_DCCTL5_CIM_M 0x00000003 // Comparison Interrupt Mode.
+#define ADC_DCCTL5_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL5_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL5_CIM_HALWAYS 0x00000002 // Hysteresis always
+#define ADC_DCCTL5_CIM_HONCE 0x00000003 // Hysteresis once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL6 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL6_CTE 0x00001000 // Comparison Trigger Enable.
+#define ADC_DCCTL6_CTC_M 0x00000C00 // Comparison Trigger Condition.
+#define ADC_DCCTL6_CTC_LOW 0x00000000 // CV < COMP0 and < COMP1
+#define ADC_DCCTL6_CTC_MID 0x00000400 // COMP0 >= CV < COMP1
+#define ADC_DCCTL6_CTC_HIGH 0x00000C00 // CV <= COMP0 and <= COMP1
+#define ADC_DCCTL6_CTM_M 0x00000300 // Comparison Trigger Mode.
+#define ADC_DCCTL6_CTM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL6_CTM_ONCE 0x00000100 // Once
+#define ADC_DCCTL6_CTM_HALWAYS 0x00000200 // Hysteresis always
+#define ADC_DCCTL6_CTM_HONCE 0x00000300 // Hysteresis once
+#define ADC_DCCTL6_CIE 0x00000010 // Comparison Interrupt Enable.
+#define ADC_DCCTL6_CIC_M 0x0000000C // Comparison Interrupt Condition.
+#define ADC_DCCTL6_CIC_LOW 0x00000000 // CV < COMP0 and < COMP1
+#define ADC_DCCTL6_CIC_MID 0x00000004 // COMP0 >= CV < COMP1
+#define ADC_DCCTL6_CIC_HIGH 0x0000000C // CV <= COMP0 and <= COMP1
+#define ADC_DCCTL6_CIM_M 0x00000003 // Comparison Interrupt Mode.
+#define ADC_DCCTL6_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL6_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL6_CIM_HALWAYS 0x00000002 // Hysteresis always
+#define ADC_DCCTL6_CIM_HONCE 0x00000003 // Hysteresis once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL7 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL7_CTE 0x00001000 // Comparison Trigger Enable.
+#define ADC_DCCTL7_CTC_M 0x00000C00 // Comparison Trigger Condition.
+#define ADC_DCCTL7_CTC_LOW 0x00000000 // CV < COMP0 and < COMP1
+#define ADC_DCCTL7_CTC_MID 0x00000400 // COMP0 >= CV < COMP1
+#define ADC_DCCTL7_CTC_HIGH 0x00000C00 // CV <= COMP0 and <= COMP1
+#define ADC_DCCTL7_CTM_M 0x00000300 // Comparison Trigger Mode.
+#define ADC_DCCTL7_CTM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL7_CTM_ONCE 0x00000100 // Once
+#define ADC_DCCTL7_CTM_HALWAYS 0x00000200 // Hysteresis always
+#define ADC_DCCTL7_CTM_HONCE 0x00000300 // Hysteresis once
+#define ADC_DCCTL7_CIE 0x00000010 // Comparison Interrupt Enable.
+#define ADC_DCCTL7_CIC_M 0x0000000C // Comparison Interrupt Condition.
+#define ADC_DCCTL7_CIC_LOW 0x00000000 // CV < COMP0 and < COMP1
+#define ADC_DCCTL7_CIC_MID 0x00000004 // COMP0 >= CV < COMP1
+#define ADC_DCCTL7_CIC_HIGH 0x0000000C // CV <= COMP0 and <= COMP1
+#define ADC_DCCTL7_CIM_M 0x00000003 // Comparison Interrupt Mode.
+#define ADC_DCCTL7_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL7_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL7_CIM_HALWAYS 0x00000002 // Hysteresis always
+#define ADC_DCCTL7_CIM_HONCE 0x00000003 // Hysteresis once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP0 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP0_COMP1_M 0x03FF0000 // Compare 1.
+#define ADC_DCCMP0_COMP0_M 0x000003FF // Compare 0.
+#define ADC_DCCMP0_COMP1_S 16
+#define ADC_DCCMP0_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP1 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP1_COMP1_M 0x03FF0000 // Compare 1.
+#define ADC_DCCMP1_COMP0_M 0x000003FF // Compare 0.
+#define ADC_DCCMP1_COMP1_S 16
+#define ADC_DCCMP1_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP2 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP2_COMP1_M 0x03FF0000 // Compare 1.
+#define ADC_DCCMP2_COMP0_M 0x000003FF // Compare 0.
+#define ADC_DCCMP2_COMP1_S 16
+#define ADC_DCCMP2_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP3 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP3_COMP1_M 0x03FF0000 // Compare 1.
+#define ADC_DCCMP3_COMP0_M 0x000003FF // Compare 0.
+#define ADC_DCCMP3_COMP1_S 16
+#define ADC_DCCMP3_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP4 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP4_COMP1_M 0x03FF0000 // Compare 1.
+#define ADC_DCCMP4_COMP0_M 0x000003FF // Compare 0.
+#define ADC_DCCMP4_COMP1_S 16
+#define ADC_DCCMP4_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP5 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP5_COMP1_M 0x03FF0000 // Compare 1.
+#define ADC_DCCMP5_COMP0_M 0x000003FF // Compare 0.
+#define ADC_DCCMP5_COMP1_S 16
+#define ADC_DCCMP5_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP6 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP6_COMP1_M 0x03FF0000 // Compare 1.
+#define ADC_DCCMP6_COMP0_M 0x000003FF // Compare 0.
+#define ADC_DCCMP6_COMP1_S 16
+#define ADC_DCCMP6_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP7 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP7_COMP1_M 0x03FF0000 // Compare 1.
+#define ADC_DCCMP7_COMP0_M 0x000003FF // Compare 0.
+#define ADC_DCCMP7_COMP1_S 16
+#define ADC_DCCMP7_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_CTL register.
+//
+//*****************************************************************************
+#define ADC_CTL_VREF 0x00000001 // Voltage Reference Select.
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the ADC sequence register offsets.
+//
+//*****************************************************************************
+#define ADC_O_SEQ 0x00000040 // Offset to the first sequence
+#define ADC_O_SEQ_STEP 0x00000020 // Increment to the next sequence
+#define ADC_O_X_SSFSTAT 0x0000000C // FIFO status register
+#define ADC_O_X_SSFIFO 0x00000008 // Result FIFO register
+#define ADC_O_X_SSCTL 0x00000004 // Sample sequence control register
+#define ADC_O_X_SSMUX 0x00000000 // Multiplexer select register
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the ADC_EMUX
+// register.
+//
+//*****************************************************************************
+#define ADC_EMUX_EM3_MASK 0x0000F000 // Event mux 3 mask
+#define ADC_EMUX_EM2_MASK 0x00000F00 // Event mux 2 mask
+#define ADC_EMUX_EM1_MASK 0x000000F0 // Event mux 1 mask
+#define ADC_EMUX_EM0_MASK 0x0000000F // Event mux 0 mask
+#define ADC_EMUX_EM3_SHIFT 12 // The shift for the fourth event
+#define ADC_EMUX_EM2_SHIFT 8 // The shift for the third event
+#define ADC_EMUX_EM1_SHIFT 4 // The shift for the second event
+#define ADC_EMUX_EM0_SHIFT 0 // The shift for the first event
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the ADC_SSPRI
+// register.
+//
+//*****************************************************************************
+#define ADC_SSPRI_SS3_MASK 0x00003000 // Sequencer 3 priority mask
+#define ADC_SSPRI_SS2_MASK 0x00000300 // Sequencer 2 priority mask
+#define ADC_SSPRI_SS1_MASK 0x00000030 // Sequencer 1 priority mask
+#define ADC_SSPRI_SS0_MASK 0x00000003 // Sequencer 0 priority mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the ADC_SSMUX0,
+// ADC_SSMUX1, ADC_SSMUX2, and ADC_SSMUX3 registers. Not all fields are present
+// in all registers.
+//
+//*****************************************************************************
+#define ADC_SSMUX_MUX7_MASK 0x70000000 // 8th mux select mask
+#define ADC_SSMUX_MUX6_MASK 0x07000000 // 7th mux select mask
+#define ADC_SSMUX_MUX5_MASK 0x00700000 // 6th mux select mask
+#define ADC_SSMUX_MUX4_MASK 0x00070000 // 5th mux select mask
+#define ADC_SSMUX_MUX3_MASK 0x00007000 // 4th mux select mask
+#define ADC_SSMUX_MUX2_MASK 0x00000700 // 3rd mux select mask
+#define ADC_SSMUX_MUX1_MASK 0x00000070 // 2nd mux select mask
+#define ADC_SSMUX_MUX0_MASK 0x00000007 // 1st mux select mask
+#define ADC_SSMUX_MUX7_SHIFT 28
+#define ADC_SSMUX_MUX6_SHIFT 24
+#define ADC_SSMUX_MUX5_SHIFT 20
+#define ADC_SSMUX_MUX4_SHIFT 16
+#define ADC_SSMUX_MUX3_SHIFT 12
+#define ADC_SSMUX_MUX2_SHIFT 8
+#define ADC_SSMUX_MUX1_SHIFT 4
+#define ADC_SSMUX_MUX0_SHIFT 0
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the ADC_SSCTL0,
+// ADC_SSCTL1, ADC_SSCTL2, and ADC_SSCTL3 registers. Not all fields are present
+// in all registers.
+//
+//*****************************************************************************
+#define ADC_SSCTL_TS7 0x80000000 // 8th temperature sensor select
+#define ADC_SSCTL_IE7 0x40000000 // 8th interrupt enable
+#define ADC_SSCTL_END7 0x20000000 // 8th sequence end select
+#define ADC_SSCTL_D7 0x10000000 // 8th differential select
+#define ADC_SSCTL_TS6 0x08000000 // 7th temperature sensor select
+#define ADC_SSCTL_IE6 0x04000000 // 7th interrupt enable
+#define ADC_SSCTL_END6 0x02000000 // 7th sequence end select
+#define ADC_SSCTL_D6 0x01000000 // 7th differential select
+#define ADC_SSCTL_TS5 0x00800000 // 6th temperature sensor select
+#define ADC_SSCTL_IE5 0x00400000 // 6th interrupt enable
+#define ADC_SSCTL_END5 0x00200000 // 6th sequence end select
+#define ADC_SSCTL_D5 0x00100000 // 6th differential select
+#define ADC_SSCTL_TS4 0x00080000 // 5th temperature sensor select
+#define ADC_SSCTL_IE4 0x00040000 // 5th interrupt enable
+#define ADC_SSCTL_END4 0x00020000 // 5th sequence end select
+#define ADC_SSCTL_D4 0x00010000 // 5th differential select
+#define ADC_SSCTL_TS3 0x00008000 // 4th temperature sensor select
+#define ADC_SSCTL_IE3 0x00004000 // 4th interrupt enable
+#define ADC_SSCTL_END3 0x00002000 // 4th sequence end select
+#define ADC_SSCTL_D3 0x00001000 // 4th differential select
+#define ADC_SSCTL_TS2 0x00000800 // 3rd temperature sensor select
+#define ADC_SSCTL_IE2 0x00000400 // 3rd interrupt enable
+#define ADC_SSCTL_END2 0x00000200 // 3rd sequence end select
+#define ADC_SSCTL_D2 0x00000100 // 3rd differential select
+#define ADC_SSCTL_TS1 0x00000080 // 2nd temperature sensor select
+#define ADC_SSCTL_IE1 0x00000040 // 2nd interrupt enable
+#define ADC_SSCTL_END1 0x00000020 // 2nd sequence end select
+#define ADC_SSCTL_D1 0x00000010 // 2nd differential select
+#define ADC_SSCTL_TS0 0x00000008 // 1st temperature sensor select
+#define ADC_SSCTL_IE0 0x00000004 // 1st interrupt enable
+#define ADC_SSCTL_END0 0x00000002 // 1st sequence end select
+#define ADC_SSCTL_D0 0x00000001 // 1st differential select
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the ADC_SSFIFO0,
+// ADC_SSFIFO1, ADC_SSFIFO2, and ADC_SSFIFO3 registers.
+//
+//*****************************************************************************
+#define ADC_SSFIFO_DATA_MASK 0x000003FF // Sample data
+#define ADC_SSFIFO_DATA_SHIFT 0
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the ADC_SSFSTAT0,
+// ADC_SSFSTAT1, ADC_SSFSTAT2, and ADC_SSFSTAT3 registers.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT_FULL 0x00001000 // FIFO is full
+#define ADC_SSFSTAT_EMPTY 0x00000100 // FIFO is empty
+#define ADC_SSFSTAT_HPTR 0x000000F0 // FIFO head pointer
+#define ADC_SSFSTAT_TPTR 0x0000000F // FIFO tail pointer
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the the interpretation of the data
+// in the SSFIFOx when the ADC TMLB is enabled.
+//
+//*****************************************************************************
+#define ADC_TMLB_CNT_M 0x000003C0 // Continuous Sample Counter.
+#define ADC_TMLB_CONT 0x00000020 // Continuation Sample Indicator.
+#define ADC_TMLB_DIFF 0x00000010 // Differential Sample Indicator.
+#define ADC_TMLB_TS 0x00000008 // Temp Sensor Sample Indicator.
+#define ADC_TMLB_MUX_M 0x00000007 // Analog Input Indicator.
+#define ADC_TMLB_CNT_S 6 // Sample counter shift
+#define ADC_TMLB_MUX_S 0 // Input channel number shift
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the loopback ADC
+// data.
+//
+//*****************************************************************************
+#define ADC_LB_CNT_MASK 0x000003C0 // Sample counter mask
+#define ADC_LB_CONT 0x00000020 // Continuation sample
+#define ADC_LB_DIFF 0x00000010 // Differential sample
+#define ADC_LB_TS 0x00000008 // Temperature sensor sample
+#define ADC_LB_MUX_MASK 0x00000007 // Input channel number mask
+#define ADC_LB_CNT_SHIFT 6 // Sample counter shift
+#define ADC_LB_MUX_SHIFT 0 // Input channel number shift
+
+#endif
+
+#endif // __HW_ADC_H__
Property changes on: branches/eagle_mmc/src/platform/lm3s/hw_adc.h
___________________________________________________________________
Name: svn:executable
+ *
Added: branches/eagle_mmc/src/platform/lm3s/hw_can.h
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/hw_can.h 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lm3s/hw_can.h 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,756 @@
+//*****************************************************************************
+//
+// hw_can.h - Defines and macros used when accessing the can.
+//
+// Copyright (c) 2006-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4781 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_CAN_H__
+#define __HW_CAN_H__
+
+//*****************************************************************************
+//
+// The following are defines for the CAN register offsets.
+//
+//*****************************************************************************
+#define CAN_O_CTL 0x00000000 // Control register
+#define CAN_O_STS 0x00000004 // Status register
+#define CAN_O_ERR 0x00000008 // Error register
+#define CAN_O_BIT 0x0000000C // Bit Timing register
+#define CAN_O_INT 0x00000010 // Interrupt register
+#define CAN_O_TST 0x00000014 // Test register
+#define CAN_O_BRPE 0x00000018 // Baud Rate Prescaler register
+#define CAN_O_IF1CRQ 0x00000020 // Interface 1 Command Request reg.
+#define CAN_O_IF1CMSK 0x00000024 // Interface 1 Command Mask reg.
+#define CAN_O_IF1MSK1 0x00000028 // Interface 1 Mask 1 register
+#define CAN_O_IF1MSK2 0x0000002C // Interface 1 Mask 2 register
+#define CAN_O_IF1ARB1 0x00000030 // Interface 1 Arbitration 1 reg.
+#define CAN_O_IF1ARB2 0x00000034 // Interface 1 Arbitration 2 reg.
+#define CAN_O_IF1MCTL 0x00000038 // Interface 1 Message Control reg.
+#define CAN_O_IF1DA1 0x0000003C // Interface 1 DataA 1 register
+#define CAN_O_IF1DA2 0x00000040 // Interface 1 DataA 2 register
+#define CAN_O_IF1DB1 0x00000044 // Interface 1 DataB 1 register
+#define CAN_O_IF1DB2 0x00000048 // Interface 1 DataB 2 register
+#define CAN_O_IF2CRQ 0x00000080 // Interface 2 Command Request reg.
+#define CAN_O_IF2CMSK 0x00000084 // Interface 2 Command Mask reg.
+#define CAN_O_IF2MSK1 0x00000088 // Interface 2 Mask 1 register
+#define CAN_O_IF2MSK2 0x0000008C // Interface 2 Mask 2 register
+#define CAN_O_IF2ARB1 0x00000090 // Interface 2 Arbitration 1 reg.
+#define CAN_O_IF2ARB2 0x00000094 // Interface 2 Arbitration 2 reg.
+#define CAN_O_IF2MCTL 0x00000098 // Interface 2 Message Control reg.
+#define CAN_O_IF2DA1 0x0000009C // Interface 2 DataA 1 register
+#define CAN_O_IF2DA2 0x000000A0 // Interface 2 DataA 2 register
+#define CAN_O_IF2DB1 0x000000A4 // Interface 2 DataB 1 register
+#define CAN_O_IF2DB2 0x000000A8 // Interface 2 DataB 2 register
+#define CAN_O_TXRQ1 0x00000100 // Transmission Request 1 register
+#define CAN_O_TXRQ2 0x00000104 // Transmission Request 2 register
+#define CAN_O_NWDA1 0x00000120 // New Data 1 register
+#define CAN_O_NWDA2 0x00000124 // New Data 2 register
+#define CAN_O_MSG1INT 0x00000140 // CAN Message 1 Interrupt Pending
+#define CAN_O_MSG2INT 0x00000144 // CAN Message 2 Interrupt Pending
+#define CAN_O_MSG1VAL 0x00000160 // CAN Message 1 Valid
+#define CAN_O_MSG2VAL 0x00000164 // CAN Message 2 Valid
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_CTL register.
+//
+//*****************************************************************************
+#define CAN_CTL_TEST 0x00000080 // Test mode enable
+#define CAN_CTL_CCE 0x00000040 // Configuration change enable
+#define CAN_CTL_DAR 0x00000020 // Disable automatic retransmission
+#define CAN_CTL_EIE 0x00000008 // Error interrupt enable
+#define CAN_CTL_SIE 0x00000004 // Status change interrupt enable
+#define CAN_CTL_IE 0x00000002 // Module interrupt enable
+#define CAN_CTL_INIT 0x00000001 // Initialization
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_STS register.
+//
+//*****************************************************************************
+#define CAN_STS_BOFF 0x00000080 // Bus Off status
+#define CAN_STS_EWARN 0x00000040 // Error Warning status
+#define CAN_STS_EPASS 0x00000020 // Error Passive status
+#define CAN_STS_RXOK 0x00000010 // Received Message Successful
+#define CAN_STS_TXOK 0x00000008 // Transmitted Message Successful
+#define CAN_STS_LEC_M 0x00000007 // Last Error Code
+#define CAN_STS_LEC_NONE 0x00000000 // No error
+#define CAN_STS_LEC_STUFF 0x00000001 // Stuff error
+#define CAN_STS_LEC_FORM 0x00000002 // Form(at) error
+#define CAN_STS_LEC_ACK 0x00000003 // Ack error
+#define CAN_STS_LEC_BIT1 0x00000004 // Bit 1 error
+#define CAN_STS_LEC_BIT0 0x00000005 // Bit 0 error
+#define CAN_STS_LEC_CRC 0x00000006 // CRC error
+#define CAN_STS_LEC_NOEVENT 0x00000007 // Unused
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_ERR register.
+//
+//*****************************************************************************
+#define CAN_ERR_RP 0x00008000 // Receive error passive status
+#define CAN_ERR_REC_M 0x00007F00 // Receive Error Counter.
+#define CAN_ERR_TEC_M 0x000000FF // Transmit Error Counter.
+#define CAN_ERR_REC_S 8 // Receive error counter bit pos
+#define CAN_ERR_TEC_S 0 // Transmit error counter bit pos
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_BIT register.
+//
+//*****************************************************************************
+#define CAN_BIT_TSEG2_M 0x00007000 // Time Segment after Sample Point.
+#define CAN_BIT_TSEG1_M 0x00000F00 // Time Segment Before Sample
+ // Point.
+#define CAN_BIT_SJW_M 0x000000C0 // (Re)Synchronization Jump Width.
+#define CAN_BIT_BRP_M 0x0000003F // Baud Rate Prescalar.
+#define CAN_BIT_TSEG2_S 12
+#define CAN_BIT_TSEG1_S 8
+#define CAN_BIT_SJW_S 6
+#define CAN_BIT_BRP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_INT register.
+//
+//*****************************************************************************
+#define CAN_INT_INTID_M 0x0000FFFF // Interrupt Identifier.
+#define CAN_INT_INTID_NONE 0x00000000 // No Interrupt Pending
+#define CAN_INT_INTID_STATUS 0x00008000 // Status Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_TST register.
+//
+//*****************************************************************************
+#define CAN_TST_RX 0x00000080 // CAN_RX pin status
+#define CAN_TST_TX_M 0x00000060 // Overide control of CAN_TX pin
+#define CAN_TST_TX_CANCTL 0x00000000 // CAN core controls CAN_TX
+#define CAN_TST_TX_SAMPLE 0x00000020 // Sample Point on CAN_TX
+#define CAN_TST_TX_DOMINANT 0x00000040 // Dominant value on CAN_TX
+#define CAN_TST_TX_RECESSIVE 0x00000060 // Recessive value on CAN_TX
+#define CAN_TST_LBACK 0x00000010 // Loop back mode
+#define CAN_TST_SILENT 0x00000008 // Silent mode
+#define CAN_TST_BASIC 0x00000004 // Basic mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_BRPE register.
+//
+//*****************************************************************************
+#define CAN_BRPE_BRPE_M 0x0000000F // Baud Rate Prescalar Extension.
+#define CAN_BRPE_BRPE_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_TXRQ1 register.
+//
+//*****************************************************************************
+#define CAN_TXRQ1_TXRQST_M 0x0000FFFF // Transmission Request Bits.
+#define CAN_TXRQ1_TXRQST_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_TXRQ2 register.
+//
+//*****************************************************************************
+#define CAN_TXRQ2_TXRQST_M 0x0000FFFF // Transmission Request Bits.
+#define CAN_TXRQ2_TXRQST_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_NWDA1 register.
+//
+//*****************************************************************************
+#define CAN_NWDA1_NEWDAT_M 0x0000FFFF // New Data Bits.
+#define CAN_NWDA1_NEWDAT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_NWDA2 register.
+//
+//*****************************************************************************
+#define CAN_NWDA2_NEWDAT_M 0x0000FFFF // New Data Bits.
+#define CAN_NWDA2_NEWDAT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1CRQ register.
+//
+//*****************************************************************************
+#define CAN_IF1CRQ_BUSY 0x00008000 // Busy Flag.
+#define CAN_IF1CRQ_MNUM_M 0x0000003F // Message Number.
+#define CAN_IF1CRQ_MNUM_RSVD 0x00000000 // 0 is not a valid message number;
+ // it is interpreted as 0x20, or
+ // object 32.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1CMSK register.
+//
+//*****************************************************************************
+#define CAN_IF1CMSK_WRNRD 0x00000080 // Write, Not Read.
+#define CAN_IF1CMSK_MASK 0x00000040 // Access Mask Bits.
+#define CAN_IF1CMSK_ARB 0x00000020 // Access Arbitration Bits.
+#define CAN_IF1CMSK_CONTROL 0x00000010 // Access Control Bits.
+#define CAN_IF1CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit.
+#define CAN_IF1CMSK_NEWDAT 0x00000004 // Access New Data.
+#define CAN_IF1CMSK_TXRQST 0x00000004 // Access Transmission Request.
+#define CAN_IF1CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3.
+#define CAN_IF1CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1MSK1 register.
+//
+//*****************************************************************************
+#define CAN_IF1MSK1_IDMSK_M 0x0000FFFF // Identifier Mask.
+#define CAN_IF1MSK1_IDMSK_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1MSK2 register.
+//
+//*****************************************************************************
+#define CAN_IF1MSK2_MXTD 0x00008000 // Mask Extended Identifier.
+#define CAN_IF1MSK2_MDIR 0x00004000 // Mask Message Direction.
+#define CAN_IF1MSK2_IDMSK_M 0x00001FFF // Identifier Mask.
+#define CAN_IF1MSK2_IDMSK_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1ARB1 register.
+//
+//*****************************************************************************
+#define CAN_IF1ARB1_ID_M 0x0000FFFF // Message Identifier.
+#define CAN_IF1ARB1_ID_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1ARB2 register.
+//
+//*****************************************************************************
+#define CAN_IF1ARB2_MSGVAL 0x00008000 // Message Valid.
+#define CAN_IF1ARB2_XTD 0x00004000 // Extended Identifier.
+#define CAN_IF1ARB2_DIR 0x00002000 // Message Direction.
+#define CAN_IF1ARB2_ID_M 0x00001FFF // Message Identifier.
+#define CAN_IF1ARB2_ID_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1MCTL register.
+//
+//*****************************************************************************
+#define CAN_IF1MCTL_NEWDAT 0x00008000 // New Data.
+#define CAN_IF1MCTL_MSGLST 0x00004000 // Message Lost.
+#define CAN_IF1MCTL_INTPND 0x00002000 // Interrupt Pending.
+#define CAN_IF1MCTL_UMASK 0x00001000 // Use Acceptance Mask.
+#define CAN_IF1MCTL_TXIE 0x00000800 // Transmit Interrupt Enable.
+#define CAN_IF1MCTL_RXIE 0x00000400 // Receive Interrupt Enable.
+#define CAN_IF1MCTL_RMTEN 0x00000200 // Remote Enable.
+#define CAN_IF1MCTL_TXRQST 0x00000100 // Transmit Request.
+#define CAN_IF1MCTL_EOB 0x00000080 // End of Buffer.
+#define CAN_IF1MCTL_DLC_M 0x0000000F // Data Length Code.
+#define CAN_IF1MCTL_DLC_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1DA1 register.
+//
+//*****************************************************************************
+#define CAN_IF1DA1_DATA_M 0x0000FFFF // Data.
+#define CAN_IF1DA1_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1DA2 register.
+//
+//*****************************************************************************
+#define CAN_IF1DA2_DATA_M 0x0000FFFF // Data.
+#define CAN_IF1DA2_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1DB1 register.
+//
+//*****************************************************************************
+#define CAN_IF1DB1_DATA_M 0x0000FFFF // Data.
+#define CAN_IF1DB1_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1DB2 register.
+//
+//*****************************************************************************
+#define CAN_IF1DB2_DATA_M 0x0000FFFF // Data.
+#define CAN_IF1DB2_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2CRQ register.
+//
+//*****************************************************************************
+#define CAN_IF2CRQ_BUSY 0x00008000 // Busy Flag.
+#define CAN_IF2CRQ_MNUM_M 0x0000003F // Message Number.
+#define CAN_IF2CRQ_MNUM_RSVD 0x00000000 // 0 is not a valid message number;
+ // it is interpreted as 0x20, or
+ // object 32.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2CMSK register.
+//
+//*****************************************************************************
+#define CAN_IF2CMSK_WRNRD 0x00000080 // Write, Not Read.
+#define CAN_IF2CMSK_MASK 0x00000040 // Access Mask Bits.
+#define CAN_IF2CMSK_ARB 0x00000020 // Access Arbitration Bits.
+#define CAN_IF2CMSK_CONTROL 0x00000010 // Access Control Bits.
+#define CAN_IF2CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit.
+#define CAN_IF2CMSK_NEWDAT 0x00000004 // Access New Data.
+#define CAN_IF2CMSK_TXRQST 0x00000004 // Access Transmission Request.
+#define CAN_IF2CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3.
+#define CAN_IF2CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2MSK1 register.
+//
+//*****************************************************************************
+#define CAN_IF2MSK1_IDMSK_M 0x0000FFFF // Identifier Mask.
+#define CAN_IF2MSK1_IDMSK_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2MSK2 register.
+//
+//*****************************************************************************
+#define CAN_IF2MSK2_MXTD 0x00008000 // Mask Extended Identifier.
+#define CAN_IF2MSK2_MDIR 0x00004000 // Mask Message Direction.
+#define CAN_IF2MSK2_IDMSK_M 0x00001FFF // Identifier Mask.
+#define CAN_IF2MSK2_IDMSK_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2ARB1 register.
+//
+//*****************************************************************************
+#define CAN_IF2ARB1_ID_M 0x0000FFFF // Message Identifier.
+#define CAN_IF2ARB1_ID_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2ARB2 register.
+//
+//*****************************************************************************
+#define CAN_IF2ARB2_MSGVAL 0x00008000 // Message Valid.
+#define CAN_IF2ARB2_XTD 0x00004000 // Extended Identifier.
+#define CAN_IF2ARB2_DIR 0x00002000 // Message Direction.
+#define CAN_IF2ARB2_ID_M 0x00001FFF // Message Identifier.
+#define CAN_IF2ARB2_ID_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2MCTL register.
+//
+//*****************************************************************************
+#define CAN_IF2MCTL_NEWDAT 0x00008000 // New Data.
+#define CAN_IF2MCTL_MSGLST 0x00004000 // Message Lost.
+#define CAN_IF2MCTL_INTPND 0x00002000 // Interrupt Pending.
+#define CAN_IF2MCTL_UMASK 0x00001000 // Use Acceptance Mask.
+#define CAN_IF2MCTL_TXIE 0x00000800 // Transmit Interrupt Enable.
+#define CAN_IF2MCTL_RXIE 0x00000400 // Receive Interrupt Enable.
+#define CAN_IF2MCTL_RMTEN 0x00000200 // Remote Enable.
+#define CAN_IF2MCTL_TXRQST 0x00000100 // Transmit Request.
+#define CAN_IF2MCTL_EOB 0x00000080 // End of Buffer.
+#define CAN_IF2MCTL_DLC_M 0x0000000F // Data Length Code.
+#define CAN_IF2MCTL_DLC_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2DA1 register.
+//
+//*****************************************************************************
+#define CAN_IF2DA1_DATA_M 0x0000FFFF // Data.
+#define CAN_IF2DA1_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2DA2 register.
+//
+//*****************************************************************************
+#define CAN_IF2DA2_DATA_M 0x0000FFFF // Data.
+#define CAN_IF2DA2_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2DB1 register.
+//
+//*****************************************************************************
+#define CAN_IF2DB1_DATA_M 0x0000FFFF // Data.
+#define CAN_IF2DB1_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2DB2 register.
+//
+//*****************************************************************************
+#define CAN_IF2DB2_DATA_M 0x0000FFFF // Data.
+#define CAN_IF2DB2_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_MSG1INT register.
+//
+//*****************************************************************************
+#define CAN_MSG1INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits.
+#define CAN_MSG1INT_INTPND_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_MSG2INT register.
+//
+//*****************************************************************************
+#define CAN_MSG2INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits.
+#define CAN_MSG2INT_INTPND_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_MSG1VAL register.
+//
+//*****************************************************************************
+#define CAN_MSG1VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits.
+#define CAN_MSG1VAL_MSGVAL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_MSG2VAL register.
+//
+//*****************************************************************************
+#define CAN_MSG2VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits.
+#define CAN_MSG2VAL_MSGVAL_S 0
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the CAN register offsets.
+//
+//*****************************************************************************
+#define CAN_O_MSGINT1 0x00000140 // Intr. Pending in Msg Obj 1 reg.
+#define CAN_O_MSGINT2 0x00000144 // Intr. Pending in Msg Obj 2 reg.
+#define CAN_O_MSGVAL1 0x00000160 // Message Valid in Msg Obj 1 reg.
+#define CAN_O_MSGVAL2 0x00000164 // Message Valid in Msg Obj 2 reg.
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the reset values of the can
+// registers.
+//
+//*****************************************************************************
+#define CAN_RV_IF1MSK2 0x0000FFFF
+#define CAN_RV_IF1MSK1 0x0000FFFF
+#define CAN_RV_IF2MSK1 0x0000FFFF
+#define CAN_RV_IF2MSK2 0x0000FFFF
+#define CAN_RV_BIT 0x00002301
+#define CAN_RV_CTL 0x00000001
+#define CAN_RV_IF1CRQ 0x00000001
+#define CAN_RV_IF2CRQ 0x00000001
+#define CAN_RV_TXRQ2 0x00000000
+#define CAN_RV_IF2DB1 0x00000000
+#define CAN_RV_INT 0x00000000
+#define CAN_RV_IF1DB2 0x00000000
+#define CAN_RV_BRPE 0x00000000
+#define CAN_RV_IF2DA2 0x00000000
+#define CAN_RV_MSGVAL2 0x00000000
+#define CAN_RV_TXRQ1 0x00000000
+#define CAN_RV_IF1MCTL 0x00000000
+#define CAN_RV_IF1DB1 0x00000000
+#define CAN_RV_STS 0x00000000
+#define CAN_RV_MSGINT1 0x00000000
+#define CAN_RV_IF1DA2 0x00000000
+#define CAN_RV_TST 0x00000000
+#define CAN_RV_IF1ARB1 0x00000000
+#define CAN_RV_IF1ARB2 0x00000000
+#define CAN_RV_NWDA2 0x00000000
+#define CAN_RV_IF2CMSK 0x00000000
+#define CAN_RV_NWDA1 0x00000000
+#define CAN_RV_IF1DA1 0x00000000
+#define CAN_RV_IF2DA1 0x00000000
+#define CAN_RV_IF2MCTL 0x00000000
+#define CAN_RV_MSGVAL1 0x00000000
+#define CAN_RV_IF1CMSK 0x00000000
+#define CAN_RV_ERR 0x00000000
+#define CAN_RV_IF2ARB2 0x00000000
+#define CAN_RV_MSGINT2 0x00000000
+#define CAN_RV_IF2ARB1 0x00000000
+#define CAN_RV_IF2DB2 0x00000000
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_STS
+// register.
+//
+//*****************************************************************************
+#define CAN_STS_LEC_MSK 0x00000007 // Last Error Code
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_ERR
+// register.
+//
+//*****************************************************************************
+#define CAN_ERR_REC_MASK 0x00007F00 // Receive error counter status
+#define CAN_ERR_TEC_MASK 0x000000FF // Transmit error counter status
+#define CAN_ERR_REC_SHIFT 8 // Receive error counter bit pos
+#define CAN_ERR_TEC_SHIFT 0 // Transmit error counter bit pos
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_BIT
+// register.
+//
+//*****************************************************************************
+#define CAN_BIT_TSEG2 0x00007000 // Time segment after sample point
+#define CAN_BIT_TSEG1 0x00000F00 // Time segment before sample point
+#define CAN_BIT_SJW 0x000000C0 // (Re)Synchronization jump width
+#define CAN_BIT_BRP 0x0000003F // Baud rate prescaler
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_INT
+// register.
+//
+//*****************************************************************************
+#define CAN_INT_INTID_MSK 0x0000FFFF // Interrupt Identifier
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_TST
+// register.
+//
+//*****************************************************************************
+#define CAN_TST_TX_MSK 0x00000060 // Overide control of CAN_TX pin
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_BRPE
+// register.
+//
+//*****************************************************************************
+#define CAN_BRPE_BRPE 0x0000000F // Baud rate prescaler extension
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_IF1CRQ
+// and CAN_IF1CRQ registers.
+// Note: All bits may not be available in all registers
+//
+//*****************************************************************************
+#define CAN_IFCRQ_BUSY 0x00008000 // Busy flag status
+#define CAN_IFCRQ_MNUM_MSK 0x0000003F // Message Number
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_IF1CMSK
+// and CAN_IF2CMSK registers.
+// Note: All bits may not be available in all registers
+//
+//*****************************************************************************
+#define CAN_IFCMSK_WRNRD 0x00000080 // Write, not Read
+#define CAN_IFCMSK_MASK 0x00000040 // Access Mask Bits
+#define CAN_IFCMSK_ARB 0x00000020 // Access Arbitration Bits
+#define CAN_IFCMSK_CONTROL 0x00000010 // Access Control Bits
+#define CAN_IFCMSK_CLRINTPND 0x00000008 // Clear interrupt pending Bit
+#define CAN_IFCMSK_TXRQST 0x00000004 // Access Tx request bit (WRNRD=1)
+#define CAN_IFCMSK_NEWDAT 0x00000004 // Access New Data bit (WRNRD=0)
+#define CAN_IFCMSK_DATAA 0x00000002 // DataA access - bytes 0 to 3
+#define CAN_IFCMSK_DATAB 0x00000001 // DataB access - bytes 4 to 7
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_IF1MSK1
+// and CAN_IF2MSK1 registers.
+// Note: All bits may not be available in all registers
+//
+//*****************************************************************************
+#define CAN_IFMSK1_MSK 0x0000FFFF // Identifier Mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_IF1MSK2
+// and CAN_IF2MSK2 registers.
+// Note: All bits may not be available in all registers
+//
+//*****************************************************************************
+#define CAN_IFMSK2_MXTD 0x00008000 // Mask extended identifier
+#define CAN_IFMSK2_MDIR 0x00004000 // Mask message direction
+#define CAN_IFMSK2_MSK 0x00001FFF // Mask identifier
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_IF1ARB1
+// and CAN_IF2ARB1 registers.
+// Note: All bits may not be available in all registers
+//
+//*****************************************************************************
+#define CAN_IFARB1_ID 0x0000FFFF // Identifier
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_IF1ARB2
+// and CAN_IF2ARB2 registers.
+// Note: All bits may not be available in all registers
+//
+//*****************************************************************************
+#define CAN_IFARB2_MSGVAL 0x00008000 // Message valid
+#define CAN_IFARB2_XTD 0x00004000 // Extended identifier
+#define CAN_IFARB2_DIR 0x00002000 // Message direction
+#define CAN_IFARB2_ID 0x00001FFF // Message identifier
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_IF1MCTL
+// and CAN_IF2MCTL registers.
+// Note: All bits may not be available in all registers
+//
+//*****************************************************************************
+#define CAN_IFMCTL_NEWDAT 0x00008000 // New Data
+#define CAN_IFMCTL_MSGLST 0x00004000 // Message lost
+#define CAN_IFMCTL_INTPND 0x00002000 // Interrupt pending
+#define CAN_IFMCTL_UMASK 0x00001000 // Use acceptance mask
+#define CAN_IFMCTL_TXIE 0x00000800 // Transmit interrupt enable
+#define CAN_IFMCTL_RXIE 0x00000400 // Receive interrupt enable
+#define CAN_IFMCTL_RMTEN 0x00000200 // Remote enable
+#define CAN_IFMCTL_TXRQST 0x00000100 // Transmit request
+#define CAN_IFMCTL_EOB 0x00000080 // End of buffer
+#define CAN_IFMCTL_DLC 0x0000000F // Data length code
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_IF1DA1
+// and CAN_IF2DA1 registers.
+// Note: All bits may not be available in all registers
+//
+//*****************************************************************************
+#define CAN_IFDA1_DATA 0x0000FFFF // Data - bytes 1 and 0
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_IF1DA2
+// and CAN_IF2DA2 registers.
+// Note: All bits may not be available in all registers
+//
+//*****************************************************************************
+#define CAN_IFDA2_DATA 0x0000FFFF // Data - bytes 3 and 2
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_IF1DB1
+// and CAN_IF2DB1 registers.
+// Note: All bits may not be available in all registers
+//
+//*****************************************************************************
+#define CAN_IFDB1_DATA 0x0000FFFF // Data - bytes 5 and 4
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_IF1DB2
+// and CAN_IF2DB2 registers.
+// Note: All bits may not be available in all registers
+//
+//*****************************************************************************
+#define CAN_IFDB2_DATA 0x0000FFFF // Data - bytes 7 and 6
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_TXRQ1
+// register.
+//
+//*****************************************************************************
+#define CAN_TXRQ1_TXRQST 0x0000FFFF // Transmission Request Bits
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_TXRQ2
+// register.
+//
+//*****************************************************************************
+#define CAN_TXRQ2_TXRQST 0x0000FFFF // Transmission Request Bits
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_NWDA1
+// register.
+//
+//*****************************************************************************
+#define CAN_NWDA1_NEWDATA 0x0000FFFF // New Data Bits
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_NWDA2
+// register.
+//
+//*****************************************************************************
+#define CAN_NWDA2_NEWDATA 0x0000FFFF // New Data Bits
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_MSGINT1
+// register.
+//
+//*****************************************************************************
+#define CAN_MSGINT1_INTPND 0x0000FFFF // Interrupt Pending Bits
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_MSGINT2
+// register.
+//
+//*****************************************************************************
+#define CAN_MSGINT2_INTPND 0x0000FFFF // Interrupt Pending Bits
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_MSGVAL1
+// register.
+//
+//*****************************************************************************
+#define CAN_MSGVAL1_MSGVAL 0x0000FFFF // Message Valid Bits
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_MSGVAL2
+// register.
+//
+//*****************************************************************************
+#define CAN_MSGVAL2_MSGVAL 0x0000FFFF // Message Valid Bits
+
+#endif
+
+#endif // __HW_CAN_H__
Property changes on: branches/eagle_mmc/src/platform/lm3s/hw_can.h
___________________________________________________________________
Name: svn:executable
+ *
Added: branches/eagle_mmc/src/platform/lm3s/hw_comp.h
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/hw_comp.h 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lm3s/hw_comp.h 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,277 @@
+//*****************************************************************************
+//
+// hw_comp.h - Macros used when accessing the comparator hardware.
+//
+// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4781 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_COMP_H__
+#define __HW_COMP_H__
+
+//*****************************************************************************
+//
+// The following are defines for the comparator register offsets.
+//
+//*****************************************************************************
+#define COMP_O_ACMIS 0x00000000 // Analog Comparator Masked
+ // Interrupt Status
+#define COMP_O_ACRIS 0x00000004 // Analog Comparator Raw Interrupt
+ // Status
+#define COMP_O_ACINTEN 0x00000008 // Analog Comparator Interrupt
+ // Enable
+#define COMP_O_ACREFCTL 0x00000010 // Analog Comparator Reference
+ // Voltage Control
+#define COMP_O_ACSTAT0 0x00000020 // Comp0 status register
+#define COMP_O_ACCTL0 0x00000024 // Comp0 control register
+#define COMP_O_ACSTAT1 0x00000040 // Comp1 status register
+#define COMP_O_ACCTL1 0x00000044 // Comp1 control register
+#define COMP_O_ACSTAT2 0x00000060 // Comp2 status register
+#define COMP_O_ACCTL2 0x00000064 // Comp2 control register
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACMIS register.
+//
+//*****************************************************************************
+#define COMP_ACMIS_IN2 0x00000004 // Comparator 2 Masked Interrupt
+ // Status.
+#define COMP_ACMIS_IN1 0x00000002 // Comparator 1 Masked Interrupt
+ // Status.
+#define COMP_ACMIS_IN0 0x00000001 // Comparator 0 Masked Interrupt
+ // Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACRIS register.
+//
+//*****************************************************************************
+#define COMP_ACRIS_IN2 0x00000004 // Comparator 2 Interrupt Status.
+#define COMP_ACRIS_IN1 0x00000002 // Comparator 1 Interrupt Status.
+#define COMP_ACRIS_IN0 0x00000001 // Comparator 0 Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACINTEN register.
+//
+//*****************************************************************************
+#define COMP_ACINTEN_IN2 0x00000004 // Comparator 2 Interrupt Enable.
+#define COMP_ACINTEN_IN1 0x00000002 // Comparator 1 Interrupt Enable.
+#define COMP_ACINTEN_IN0 0x00000001 // Comparator 0 Interrupt Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACREFCTL
+// register.
+//
+//*****************************************************************************
+#define COMP_ACREFCTL_EN 0x00000200 // Resistor Ladder Enable.
+#define COMP_ACREFCTL_RNG 0x00000100 // Resistor Ladder Range.
+#define COMP_ACREFCTL_VREF_M 0x0000000F // Resistor Ladder Voltage Ref.
+#define COMP_ACREFCTL_VREF_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACSTAT0 register.
+//
+//*****************************************************************************
+#define COMP_ACSTAT0_OVAL 0x00000002 // Comparator Output Value.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACCTL0 register.
+//
+//*****************************************************************************
+#define COMP_ACCTL0_TOEN 0x00000800 // Trigger Output Enable.
+#define COMP_ACCTL0_ASRCP_M 0x00000600 // Analog Source Positive.
+#define COMP_ACCTL0_ASRCP_PIN 0x00000000 // Pin value
+#define COMP_ACCTL0_ASRCP_PIN0 0x00000200 // Pin value of C0+
+#define COMP_ACCTL0_ASRCP_REF 0x00000400 // Internal voltage reference
+#define COMP_ACCTL0_TSLVAL 0x00000080 // Trigger Sense Level Value.
+#define COMP_ACCTL0_TSEN_M 0x00000060 // Trigger Sense.
+#define COMP_ACCTL0_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL
+#define COMP_ACCTL0_TSEN_FALL 0x00000020 // Falling edge
+#define COMP_ACCTL0_TSEN_RISE 0x00000040 // Rising edge
+#define COMP_ACCTL0_TSEN_BOTH 0x00000060 // Either edge
+#define COMP_ACCTL0_ISLVAL 0x00000010 // Interrupt Sense Level Value.
+#define COMP_ACCTL0_ISEN_M 0x0000000C // Interrupt Sense.
+#define COMP_ACCTL0_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL
+#define COMP_ACCTL0_ISEN_FALL 0x00000004 // Falling edge
+#define COMP_ACCTL0_ISEN_RISE 0x00000008 // Rising edge
+#define COMP_ACCTL0_ISEN_BOTH 0x0000000C // Either edge
+#define COMP_ACCTL0_CINV 0x00000002 // Comparator Output Invert.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACSTAT1 register.
+//
+//*****************************************************************************
+#define COMP_ACSTAT1_OVAL 0x00000002 // Comparator Output Value.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACCTL1 register.
+//
+//*****************************************************************************
+#define COMP_ACCTL1_TOEN 0x00000800 // Trigger Output Enable.
+#define COMP_ACCTL1_ASRCP_M 0x00000600 // Analog Source Positive.
+#define COMP_ACCTL1_ASRCP_PIN 0x00000000 // Pin value
+#define COMP_ACCTL1_ASRCP_PIN0 0x00000200 // Pin value of C0+
+#define COMP_ACCTL1_ASRCP_REF 0x00000400 // Internal voltage reference
+#define COMP_ACCTL1_TSLVAL 0x00000080 // Trigger Sense Level Value.
+#define COMP_ACCTL1_TSEN_M 0x00000060 // Trigger Sense.
+#define COMP_ACCTL1_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL
+#define COMP_ACCTL1_TSEN_FALL 0x00000020 // Falling edge
+#define COMP_ACCTL1_TSEN_RISE 0x00000040 // Rising edge
+#define COMP_ACCTL1_TSEN_BOTH 0x00000060 // Either edge
+#define COMP_ACCTL1_ISLVAL 0x00000010 // Interrupt Sense Level Value.
+#define COMP_ACCTL1_ISEN_M 0x0000000C // Interrupt Sense.
+#define COMP_ACCTL1_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL
+#define COMP_ACCTL1_ISEN_FALL 0x00000004 // Falling edge
+#define COMP_ACCTL1_ISEN_RISE 0x00000008 // Rising edge
+#define COMP_ACCTL1_ISEN_BOTH 0x0000000C // Either edge
+#define COMP_ACCTL1_CINV 0x00000002 // Comparator Output Invert.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACSTAT2 register.
+//
+//*****************************************************************************
+#define COMP_ACSTAT2_OVAL 0x00000002 // Comparator Output Value.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACCTL2 register.
+//
+//*****************************************************************************
+#define COMP_ACCTL2_TOEN 0x00000800 // Trigger Output Enable.
+#define COMP_ACCTL2_ASRCP_M 0x00000600 // Analog Source Positive.
+#define COMP_ACCTL2_ASRCP_PIN 0x00000000 // Pin value
+#define COMP_ACCTL2_ASRCP_PIN0 0x00000200 // Pin value of C0+
+#define COMP_ACCTL2_ASRCP_REF 0x00000400 // Internal voltage reference
+#define COMP_ACCTL2_TSLVAL 0x00000080 // Trigger Sense Level Value.
+#define COMP_ACCTL2_TSEN_M 0x00000060 // Trigger Sense.
+#define COMP_ACCTL2_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL
+#define COMP_ACCTL2_TSEN_FALL 0x00000020 // Falling edge
+#define COMP_ACCTL2_TSEN_RISE 0x00000040 // Rising edge
+#define COMP_ACCTL2_TSEN_BOTH 0x00000060 // Either edge
+#define COMP_ACCTL2_ISLVAL 0x00000010 // Interrupt Sense Level Value.
+#define COMP_ACCTL2_ISEN_M 0x0000000C // Interrupt Sense.
+#define COMP_ACCTL2_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL
+#define COMP_ACCTL2_ISEN_FALL 0x00000004 // Falling edge
+#define COMP_ACCTL2_ISEN_RISE 0x00000008 // Rising edge
+#define COMP_ACCTL2_ISEN_BOTH 0x0000000C // Either edge
+#define COMP_ACCTL2_CINV 0x00000002 // Comparator Output Invert.
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the comparator register offsets.
+//
+//*****************************************************************************
+#define COMP_O_MIS 0x00000000 // Interrupt status register
+#define COMP_O_RIS 0x00000004 // Raw interrupt status register
+#define COMP_O_INTEN 0x00000008 // Interrupt enable register
+#define COMP_O_REFCTL 0x00000010 // Reference voltage control reg.
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the COMP_MIS,
+// COMP_RIS, and COMP_INTEN registers.
+//
+//*****************************************************************************
+#define COMP_INT_2 0x00000004 // Comp2 interrupt
+#define COMP_INT_1 0x00000002 // Comp1 interrupt
+#define COMP_INT_0 0x00000001 // Comp0 interrupt
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the COMP_REFCTL
+// register.
+//
+//*****************************************************************************
+#define COMP_REFCTL_EN 0x00000200 // Reference voltage enable
+#define COMP_REFCTL_RNG 0x00000100 // Reference voltage range
+#define COMP_REFCTL_VREF_MASK 0x0000000F // Reference voltage select mask
+#define COMP_REFCTL_VREF_SHIFT 0
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the COMP_ACSTAT0,
+// COMP_ACSTAT1, and COMP_ACSTAT2 registers.
+//
+//*****************************************************************************
+#define COMP_ACSTAT_OVAL 0x00000002 // Comparator output value
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the COMP_ACCTL0,
+// COMP_ACCTL1, and COMP_ACCTL2 registers.
+//
+//*****************************************************************************
+#define COMP_ACCTL_TMASK 0x00000800 // Trigger enable
+#define COMP_ACCTL_ASRCP_MASK 0x00000600 // Vin+ source select mask
+#define COMP_ACCTL_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin
+#define COMP_ACCTL_ASRCP_PIN0 0x00000200 // Comp0+ pin
+#define COMP_ACCTL_ASRCP_REF 0x00000400 // Internal voltage reference
+#define COMP_ACCTL_ASRCP_RES 0x00000600 // Reserved
+#define COMP_ACCTL_OEN 0x00000100 // Comparator output enable
+#define COMP_ACCTL_TSVAL 0x00000080 // Trigger polarity select
+#define COMP_ACCTL_TSEN_MASK 0x00000060 // Trigger sense mask
+#define COMP_ACCTL_TSEN_LEVEL 0x00000000 // Trigger is level sense
+#define COMP_ACCTL_TSEN_FALL 0x00000020 // Trigger is falling edge
+#define COMP_ACCTL_TSEN_RISE 0x00000040 // Trigger is rising edge
+#define COMP_ACCTL_TSEN_BOTH 0x00000060 // Trigger is both edges
+#define COMP_ACCTL_ISLVAL 0x00000010 // Interrupt polarity select
+#define COMP_ACCTL_ISEN_MASK 0x0000000C // Interrupt sense mask
+#define COMP_ACCTL_ISEN_LEVEL 0x00000000 // Interrupt is level sense
+#define COMP_ACCTL_ISEN_FALL 0x00000004 // Interrupt is falling edge
+#define COMP_ACCTL_ISEN_RISE 0x00000008 // Interrupt is rising edge
+#define COMP_ACCTL_ISEN_BOTH 0x0000000C // Interrupt is both edges
+#define COMP_ACCTL_CINV 0x00000002 // Comparator output invert
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the reset values for the comparator
+// registers.
+//
+//*****************************************************************************
+#define COMP_RV_ACCTL1 0x00000000 // Comp1 control register
+#define COMP_RV_ACSTAT2 0x00000000 // Comp2 status register
+#define COMP_RV_ACSTAT0 0x00000000 // Comp0 status register
+#define COMP_RV_RIS 0x00000000 // Raw interrupt status register
+#define COMP_RV_INTEN 0x00000000 // Interrupt enable register
+#define COMP_RV_ACCTL2 0x00000000 // Comp2 control register
+#define COMP_RV_MIS 0x00000000 // Interrupt status register
+#define COMP_RV_ACCTL0 0x00000000 // Comp0 control register
+#define COMP_RV_ACSTAT1 0x00000000 // Comp1 status register
+#define COMP_RV_REFCTL 0x00000000 // Reference voltage control reg.
+
+#endif
+
+#endif // __HW_COMP_H__
Property changes on: branches/eagle_mmc/src/platform/lm3s/hw_comp.h
___________________________________________________________________
Name: svn:executable
+ *
Added: branches/eagle_mmc/src/platform/lm3s/hw_epi.h
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/hw_epi.h 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lm3s/hw_epi.h 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,428 @@
+//*****************************************************************************
+//
+// hw_epi.h - Macros for use in accessing the EPI registers.
+//
+// Copyright (c) 2008-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4781 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_EPI_H__
+#define __HW_EPI_H__
+
+//*****************************************************************************
+//
+// The following are defines for the External Peripheral Interface (EPI)
+//
+//*****************************************************************************
+#define EPI_O_CFG 0x00000000 // EPI Configuration
+#define EPI_O_BAUD 0x00000004 // EPI Main Baud Rate
+#define EPI_O_GPCFG 0x00000010 // EPI General Purpose
+ // Configuration
+#define EPI_O_SDRAMCFG 0x00000010 // EPI SDRAM Mode Configuration
+#define EPI_O_HB8CFG 0x00000010 // EPI Host-Bus 8 Mode
+ // Configuration
+#define EPI_O_HB8CFG2 0x00000014 // EPI Host-Bus 8 Configuration 2
+#define EPI_O_SDRAMCFG2 0x00000014 // EPI SDRAM Configuration 2
+#define EPI_O_GPCFG2 0x00000014 // EPI General-Purpose
+ // Configuration 2
+#define EPI_O_ADDRMAP 0x0000001C // EPI Address Map
+#define EPI_O_RSIZE0 0x00000020 // EPI Read Size 0
+#define EPI_O_RADDR0 0x00000024 // EPI Read Address 0
+#define EPI_O_RPSTD0 0x00000028 // EPI Non-Blocking Read Data 0
+#define EPI_O_RSIZE1 0x00000030 // EPI Read Size 1
+#define EPI_O_RADDR1 0x00000034 // EPI Read Address 1
+#define EPI_O_RPSTD1 0x00000038 // EPI Non-Blocking Read Data 1
+#define EPI_O_STAT 0x00000060 // EPI Status
+#define EPI_O_RFIFOCNT 0x0000006C // EPI Read FIFO Count
+#define EPI_O_READFIFO 0x00000070 // EPI Read FIFO
+#define EPI_O_READFIFO1 0x00000074 // EPI Read FIFO Alias 1
+#define EPI_O_READFIFO2 0x00000078 // EPI Read FIFO Alias 2
+#define EPI_O_READFIFO3 0x0000007C // EPI Read FIFO Alias 3
+#define EPI_O_READFIFO4 0x00000080 // EPI Read FIFO Alias 4
+#define EPI_O_READFIFO5 0x00000084 // EPI Read FIFO Alias 5
+#define EPI_O_READFIFO6 0x00000088 // EPI Read FIFO Alias 6
+#define EPI_O_READFIFO7 0x0000008C // EPI Read FIFO Alias 7
+#define EPI_O_FIFOLVL 0x00000200 // EPI FIFO Level Selects
+#define EPI_O_WFIFOCNT 0x00000204 // EPI Write FIFO Count
+#define EPI_O_IM 0x00000210 // EPI Interrupt Mask
+#define EPI_O_RIS 0x00000214 // EPI Raw Interrupt Status
+#define EPI_O_MIS 0x00000218 // EPI Masked Interrupt Status
+#define EPI_O_EISC 0x0000021C // EPI Error Interrupt Status and
+ // Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_CFG register.
+//
+//*****************************************************************************
+#define EPI_CFG_BLKEN 0x00000010 // Block Enable.
+#define EPI_CFG_MODE_M 0x0000000F // Mode Select.
+#define EPI_CFG_MODE_NONE 0x00000000 // None
+#define EPI_CFG_MODE_SDRAM 0x00000001 // SDRAM
+#define EPI_CFG_MODE_HB8 0x00000002 // 8-Bit Host-Bus (HB8)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_BAUD register.
+//
+//*****************************************************************************
+#define EPI_BAUD_COUNT_M 0x0000FFFF // Baud Rate Counter.
+#define EPI_BAUD_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_SDRAMCFG register.
+//
+//*****************************************************************************
+#define EPI_SDRAMCFG_FREQ_M 0xC0000000 // Frequency Range.
+#define EPI_SDRAMCFG_FREQ_NONE 0x00000000 // 0
+#define EPI_SDRAMCFG_FREQ_15MHZ 0x40000000 // 15
+#define EPI_SDRAMCFG_FREQ_30MHZ 0x80000000 // 30
+#define EPI_SDRAMCFG_FREQ_50MHZ 0xC0000000 // 50
+#define EPI_SDRAMCFG_RFSH_M 0x07FF0000 // Refresh Counter.
+#define EPI_SDRAMCFG_SLEEP 0x00000200 // Sleep Mode.
+#define EPI_SDRAMCFG_SIZE_M 0x00000003 // Size of SDRAM.
+#define EPI_SDRAMCFG_SIZE_8MB 0x00000000 // 64Mb (8MB)
+#define EPI_SDRAMCFG_SIZE_16MB 0x00000001 // 128Mb (16MB)
+#define EPI_SDRAMCFG_SIZE_32MB 0x00000002 // 256Mb (32MB)
+#define EPI_SDRAMCFG_SIZE_64MB 0x00000003 // 512Mb (64MB)
+#define EPI_SDRAMCFG_RFSH_S 16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_GPCFG register.
+//
+//*****************************************************************************
+#define EPI_GPCFG_CLKPIN 0x80000000 // Clock Pin.
+#define EPI_GPCFG_CLKGATE 0x40000000 // Clock Gated.
+#define EPI_GPCFG_RDYEN 0x10000000 // Ready Enable.
+#define EPI_GPCFG_FRMPIN 0x08000000 // Framing Pin.
+#define EPI_GPCFG_FRM50 0x04000000 // 50/50 Frame.
+#define EPI_GPCFG_FRMCNT_M 0x03C00000 // Frame Count.
+#define EPI_GPCFG_RW 0x00200000 // Read and Write.
+#define EPI_GPCFG_WR2CYC 0x00080000 // 2-Cycle Writes.
+#define EPI_GPCFG_RD2CYC 0x00040000 // 2-Cycle Reads.
+#define EPI_GPCFG_MAXWAIT_M 0x0000FF00 // Maximum Wait.
+#define EPI_GPCFG_ASIZE_M 0x00000030 // Address Bus Size.
+#define EPI_GPCFG_ASIZE_NONE 0x00000000 // No address
+#define EPI_GPCFG_ASIZE_4BIT 0x00000010 // 4 Bits Wide (EPI24 to EPI27)
+#define EPI_GPCFG_ASIZE_12BIT 0x00000020 // 12 Bits Wide (EPI16 to EPI27).
+ // Cannot be used with 24-bit data
+#define EPI_GPCFG_ASIZE_20BIT 0x00000030 // 20 Bits Wide
+#define EPI_GPCFG_DSIZE_M 0x00000003 // Size of Data Bus.
+#define EPI_GPCFG_DSIZE_4BIT 0x00000000 // 4 Bits Wide (EPI0 to EPI7)
+#define EPI_GPCFG_DSIZE_16BIT 0x00000001 // 16 Bits Wide (EPI0 to EPI15)
+#define EPI_GPCFG_DSIZE_24BIT 0x00000002 // 24 Bits Wide (EPI0 to EPI23)
+#define EPI_GPCFG_DSIZE_32BIT 0x00000003 // 32 Bits Wide. May not be used
+ // with clock (EPI0 to EPI31). This
+ // value is normally used for
+ // acquisition input and actuator
+ // control as well as other general
+ // purpose uses.
+#define EPI_GPCFG_FRMCNT_S 22
+#define EPI_GPCFG_MAXWAIT_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB8CFG register.
+//
+//*****************************************************************************
+#define EPI_HB8CFG_XFFEN 0x00800000 // External FIFO FULL Enable.
+#define EPI_HB8CFG_XFEEN 0x00400000 // External FIFO EMPTY Enable.
+#define EPI_HB8CFG_WRHIGH 0x00200000 // WRITE Strobe Polarity.
+#define EPI_HB8CFG_RDHIGH 0x00100000 // READ Strobe Polarity.
+#define EPI_HB8CFG_MAXWAIT_M 0x0000FF00 // Maximum Wait.
+#define EPI_HB8CFG_WRWS_M 0x000000C0 // Write Wait States.
+#define EPI_HB8CFG_WRWS_0 0x00000000 // No wait states
+#define EPI_HB8CFG_WRWS_1 0x00000040 // 1 wait state
+#define EPI_HB8CFG_WRWS_2 0x00000080 // 2 wait states
+#define EPI_HB8CFG_WRWS_3 0x000000C0 // 3 wait states
+#define EPI_HB8CFG_RDWS_M 0x00000030 // Read Wait States.
+#define EPI_HB8CFG_RDWS_0 0x00000000 // No wait states
+#define EPI_HB8CFG_RDWS_1 0x00000010 // 1 wait state
+#define EPI_HB8CFG_RDWS_2 0x00000020 // 2 wait states
+#define EPI_HB8CFG_RDWS_3 0x00000030 // 3 wait states
+#define EPI_HB8CFG_MODE_M 0x00000003 // Host Bus Sub-Mode.
+#define EPI_HB8CFG_MODE_MUX 0x00000000 // ADMUX - AD[7:0]
+#define EPI_HB8CFG_MODE_NMUX 0x00000001 // ADNONMUX - D[7:0]
+#define EPI_HB8CFG_MODE_SRAM 0x00000002 // SRAM
+#define EPI_HB8CFG_MODE_FIFO 0x00000003 // FIFO - D[7:0]
+#define EPI_HB8CFG_MAXWAIT_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_ADDRMAP register.
+//
+//*****************************************************************************
+#define EPI_ADDRMAP_EPSZ_M 0x000000C0 // External Peripheral Size.
+#define EPI_ADDRMAP_EPSZ_256B 0x00000000 // 0x100 (256)
+#define EPI_ADDRMAP_EPSZ_64KB 0x00000040 // 0x10000 (64 KB)
+#define EPI_ADDRMAP_EPSZ_16MB 0x00000080 // 0x1000000 (16 MB)
+#define EPI_ADDRMAP_EPSZ_512MB 0x000000C0 // 0x20000000 (512 MB)
+#define EPI_ADDRMAP_EPADR_M 0x00000030 // External Peripheral Address.
+#define EPI_ADDRMAP_EPADR_NONE 0x00000000 // Not mapped
+#define EPI_ADDRMAP_EPADR_A000 0x00000010 // At 0xA0000000
+#define EPI_ADDRMAP_EPADR_C000 0x00000020 // At 0xC0000000
+#define EPI_ADDRMAP_ERSZ_M 0x0000000C // External RAM Size.
+#define EPI_ADDRMAP_ERSZ_256B 0x00000000 // 0x100 (256)
+#define EPI_ADDRMAP_ERSZ_64KB 0x00000004 // 0x10000 (64KB)
+#define EPI_ADDRMAP_ERSZ_16MB 0x00000008 // 0x1000000 (16MB)
+#define EPI_ADDRMAP_ERSZ_512MB 0x0000000C // 0x20000000 (512MB)
+#define EPI_ADDRMAP_ERADR_M 0x00000003 // External RAM Address.
+#define EPI_ADDRMAP_ERADR_NONE 0x00000000 // Not mapped
+#define EPI_ADDRMAP_ERADR_6000 0x00000001 // At 0x60000000
+#define EPI_ADDRMAP_ERADR_8000 0x00000002 // At 0x80000000
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RSIZE0 register.
+//
+//*****************************************************************************
+#define EPI_RSIZE0_SIZE_M 0x00000003 // Current Size.
+#define EPI_RSIZE0_SIZE_8BIT 0x00000001 // Byte (8 bits)
+#define EPI_RSIZE0_SIZE_16BIT 0x00000002 // Half-word (16 bits)
+#define EPI_RSIZE0_SIZE_32BIT 0x00000003 // Word (32 bits)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RADDR0 register.
+//
+//*****************************************************************************
+#define EPI_RADDR0_ADDR_M 0x1FFFFFFF // Current Address.
+#define EPI_RADDR0_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RPSTD0 register.
+//
+//*****************************************************************************
+#define EPI_RPSTD0_POSTCNT_M 0x00001FFF // Post Count.
+#define EPI_RPSTD0_POSTCNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RSIZE1 register.
+//
+//*****************************************************************************
+#define EPI_RSIZE1_SIZE_M 0x00000003 // Current Size.
+#define EPI_RSIZE1_SIZE_8BIT 0x00000001 // Byte (8 bits)
+#define EPI_RSIZE1_SIZE_16BIT 0x00000002 // Half-word (16 bits)
+#define EPI_RSIZE1_SIZE_32BIT 0x00000003 // Word (32 bits)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RADDR1 register.
+//
+//*****************************************************************************
+#define EPI_RADDR1_ADDR_M 0x1FFFFFFF // Current Address.
+#define EPI_RADDR1_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RPSTD1 register.
+//
+//*****************************************************************************
+#define EPI_RPSTD1_POSTCNT_M 0x00001FFF // Post Count.
+#define EPI_RPSTD1_POSTCNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RFIFOCNT register.
+//
+//*****************************************************************************
+#define EPI_RFIFOCNT_COUNT_M 0x00000007 // FIFO Count.
+#define EPI_RFIFOCNT_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO register.
+//
+//*****************************************************************************
+#define EPI_READFIFO_DATA_M 0xFFFFFFFF // Reads Data.
+#define EPI_READFIFO_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO1
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO1_DATA_M 0xFFFFFFFF // Reads Data.
+#define EPI_READFIFO1_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO2
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO2_DATA_M 0xFFFFFFFF // Reads Data.
+#define EPI_READFIFO2_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO3
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO3_DATA_M 0xFFFFFFFF // Reads Data.
+#define EPI_READFIFO3_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO4
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO4_DATA_M 0xFFFFFFFF // Reads Data.
+#define EPI_READFIFO4_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO5
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO5_DATA_M 0xFFFFFFFF // Reads Data.
+#define EPI_READFIFO5_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO6
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO6_DATA_M 0xFFFFFFFF // Reads Data.
+#define EPI_READFIFO6_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO7
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO7_DATA_M 0xFFFFFFFF // Reads Data.
+#define EPI_READFIFO7_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_FIFOLVL register.
+//
+//*****************************************************************************
+#define EPI_FIFOLVL_WFERR 0x00020000 // Write Full Error.
+#define EPI_FIFOLVL_RSERR 0x00010000 // Read Stall Error.
+#define EPI_FIFOLVL_WRFIFO_M 0x00000070 // Write FIFO.
+#define EPI_FIFOLVL_WRFIFO_EMPT 0x00000000 // Empty
+#define EPI_FIFOLVL_WRFIFO_1_4 0x00000020 // >= 1/4 full
+#define EPI_FIFOLVL_WRFIFO_1_2 0x00000030 // >= 1/2 full
+#define EPI_FIFOLVL_WRFIFO_3_4 0x00000040 // >= 3/4 full
+#define EPI_FIFOLVL_RDFIFO_M 0x00000007 // Read FIFO.
+#define EPI_FIFOLVL_RDFIFO_EMPT 0x00000000 // Empty
+#define EPI_FIFOLVL_RDFIFO_1_8 0x00000001 // <= 1/8 full
+#define EPI_FIFOLVL_RDFIFO_1_4 0x00000002 // <= 1/4 full
+#define EPI_FIFOLVL_RDFIFO_1_2 0x00000003 // <= 1/2 full
+#define EPI_FIFOLVL_RDFIFO_3_4 0x00000004 // <= 3/4 full
+#define EPI_FIFOLVL_RDFIFO_7_8 0x00000005 // <= 7/8 full
+#define EPI_FIFOLVL_RDFIFO_FULL 0x00000006 // Trigger when there are 8 entries
+ // in the NBRFIFO.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_IM register.
+//
+//*****************************************************************************
+#define EPI_IM_WRIM 0x00000004 // Write Interrupt Mask.
+#define EPI_IM_RDIM 0x00000002 // Read Interrupt Mask.
+#define EPI_IM_ERRIM 0x00000001 // Error Interrupt Mask.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RIS register.
+//
+//*****************************************************************************
+#define EPI_RIS_WRRIS 0x00000004 // Write Raw Interrupt Status.
+#define EPI_RIS_RDRIS 0x00000002 // Read Raw Interrupt Status.
+#define EPI_RIS_ERRRIS 0x00000001 // Error Raw Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_MIS register.
+//
+//*****************************************************************************
+#define EPI_MIS_WRMIS 0x00000004 // Write Masked Interrupt Status.
+#define EPI_MIS_RDMIS 0x00000002 // Read Masked Interrupt Status.
+#define EPI_MIS_ERRMIS 0x00000001 // Error Masked Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_SDRAMCFG2
+// register.
+//
+//*****************************************************************************
+#define EPI_SDRAMCFG2_RCM 0x80000000 // Read Capture Mode.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB8CFG2 register.
+//
+//*****************************************************************************
+#define EPI_HB8CFG2_WORD 0x80000000 // Word Access Mode.
+#define EPI_HB8CFG2_CSCFG 0x01000000 // Chip Select Configuration.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_GPCFG2 register.
+//
+//*****************************************************************************
+#define EPI_GPCFG2_WORD 0x80000000 // Word Access Mode.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_STAT register.
+//
+//*****************************************************************************
+#define EPI_STAT_CELOW 0x00000200 // Clock Enable Low.
+#define EPI_STAT_XFFULL 0x00000100 // External FIFO Full.
+#define EPI_STAT_XFEMPTY 0x00000080 // External FIFO Empty.
+#define EPI_STAT_INITSEQ 0x00000040 // Initialization Sequence.
+#define EPI_STAT_WBUSY 0x00000020 // Write Busy.
+#define EPI_STAT_NBRBUSY 0x00000010 // Non-Blocking Read Busy.
+#define EPI_STAT_ACTIVE 0x00000001 // Register Active.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_WFIFOCNT register.
+//
+//*****************************************************************************
+#define EPI_WFIFOCNT_WTAV_M 0x00000007 // Available Write Transactions.
+#define EPI_WFIFOCNT_WTAV_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_EISC register.
+//
+//*****************************************************************************
+#define EPI_EISC_WTFULL 0x00000004 // Write FIFO Full Error.
+#define EPI_EISC_RSTALL 0x00000002 // Read Stalled Error.
+#define EPI_EISC_TOUT 0x00000001 // Timeout Error.
+
+#endif // __HW_EPI_H__
Property changes on: branches/eagle_mmc/src/platform/lm3s/hw_epi.h
___________________________________________________________________
Name: svn:executable
+ *
Modified: branches/eagle_mmc/src/platform/lm3s/hw_ethernet.h
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/hw_ethernet.h 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lm3s/hw_ethernet.h 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,575 +1,683 @@
-//*****************************************************************************
-//
-// hw_ethernet.h - Macros used when accessing the Ethernet hardware.
-//
-// Copyright (c) 2006-2008 Luminary Micro, Inc. All rights reserved.
-// Software License Agreement
-//
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
-//
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws. All rights are reserved. You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program. Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
-//
-// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-//
-// This is part of revision 3740 of the Stellaris Firmware Development Package.
-//
-//*****************************************************************************
-
-#ifndef __HW_ETHERNET_H__
-#define __HW_ETHERNET_H__
-
-//*****************************************************************************
-//
-// The following are defines for the MAC register offsets in the Ethernet
-// Controller.
-//
-//*****************************************************************************
-#define MAC_O_RIS 0x00000000 // Ethernet MAC Raw Interrupt
- // Status
-#define MAC_O_IACK 0x00000000 // Interrupt Acknowledge Register
-#define MAC_O_IM 0x00000004 // Interrupt Mask Register
-#define MAC_O_RCTL 0x00000008 // Receive Control Register
-#define MAC_O_TCTL 0x0000000C // Transmit Control Register
-#define MAC_O_DATA 0x00000010 // Data Register
-#define MAC_O_IA0 0x00000014 // Individual Address Register 0
-#define MAC_O_IA1 0x00000018 // Individual Address Register 1
-#define MAC_O_THR 0x0000001C // Threshold Register
-#define MAC_O_MCTL 0x00000020 // Management Control Register
-#define MAC_O_MDV 0x00000024 // Management Divider Register
-#define MAC_O_MTXD 0x0000002C // Management Transmit Data Reg
-#define MAC_O_MRXD 0x00000030 // Management Receive Data Reg
-#define MAC_O_NP 0x00000034 // Number of Packets Register
-#define MAC_O_TR 0x00000038 // Transmission Request Register
-#define MAC_O_TS 0x0000003C // Timer Support Register
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_IACK register.
-//
-//*****************************************************************************
-#define MAC_IACK_PHYINT 0x00000040 // Clear PHY Interrupt
-#define MAC_IACK_MDINT 0x00000020 // Clear MDI Transaction Complete
-#define MAC_IACK_RXER 0x00000010 // Clear RX Error
-#define MAC_IACK_FOV 0x00000008 // Clear RX FIFO Overrun
-#define MAC_IACK_TXEMP 0x00000004 // Clear TX FIFO Empy
-#define MAC_IACK_TXER 0x00000002 // Clear TX Error
-#define MAC_IACK_RXINT 0x00000001 // Clear RX Packet Available
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_IM register.
-//
-//*****************************************************************************
-#define MAC_IM_PHYINTM 0x00000040 // Mask PHY Interrupt
-#define MAC_IM_MDINTM 0x00000020 // Mask MDI Transaction Complete
-#define MAC_IM_RXERM 0x00000010 // Mask RX Error
-#define MAC_IM_FOVM 0x00000008 // Mask RX FIFO Overrun
-#define MAC_IM_TXEMPM 0x00000004 // Mask TX FIFO Empy
-#define MAC_IM_TXERM 0x00000002 // Mask TX Error
-#define MAC_IM_RXINTM 0x00000001 // Mask RX Packet Available
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_RCTL register.
-//
-//*****************************************************************************
-#define MAC_RCTL_RSTFIFO 0x00000010 // Clear the Receive FIFO
-#define MAC_RCTL_BADCRC 0x00000008 // Reject Packets With Bad CRC
-#define MAC_RCTL_PRMS 0x00000004 // Enable Promiscuous Mode
-#define MAC_RCTL_AMUL 0x00000002 // Enable Multicast Packets
-#define MAC_RCTL_RXEN 0x00000001 // Enable Ethernet Receiver
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_TCTL register.
-//
-//*****************************************************************************
-#define MAC_TCTL_DUPLEX 0x00000010 // Enable Duplex mode
-#define MAC_TCTL_CRC 0x00000004 // Enable CRC Generation
-#define MAC_TCTL_PADEN 0x00000002 // Enable Automatic Padding
-#define MAC_TCTL_TXEN 0x00000001 // Enable Ethernet Transmitter
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_IA0 register.
-//
-//*****************************************************************************
-#define MAC_IA0_MACOCT4_M 0xFF000000 // MAC Address Octet 4.
-#define MAC_IA0_MACOCT3_M 0x00FF0000 // MAC Address Octet 3.
-#define MAC_IA0_MACOCT2_M 0x0000FF00 // MAC Address Octet 2.
-#define MAC_IA0_MACOCT1_M 0x000000FF // MAC Address Octet 1.
-#define MAC_IA0_MACOCT4_S 24
-#define MAC_IA0_MACOCT3_S 16
-#define MAC_IA0_MACOCT2_S 8
-#define MAC_IA0_MACOCT1_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_IA1 register.
-//
-//*****************************************************************************
-#define MAC_IA1_MACOCT6_M 0x0000FF00 // MAC Address Octet 6.
-#define MAC_IA1_MACOCT5_M 0x000000FF // MAC Address Octet 5.
-#define MAC_IA1_MACOCT6_S 8
-#define MAC_IA1_MACOCT5_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_TXTH register.
-//
-//*****************************************************************************
-#define MAC_THR_THRESH_M 0x0000003F // Threshold Value.
-#define MAC_THR_THRESH_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_MCTL register.
-//
-//*****************************************************************************
-#define MAC_MCTL_REGADR_M 0x000000F8 // MII Register Address.
-#define MAC_MCTL_WRITE 0x00000002 // Next MII Transaction is Write
-#define MAC_MCTL_START 0x00000001 // Start MII Transaction
-#define MAC_MCTL_REGADR_S 3
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_MDV register.
-//
-//*****************************************************************************
-#define MAC_MDV_DIV_M 0x000000FF // Clock Divider.
-#define MAC_MDV_DIV_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_MTXD register.
-//
-//*****************************************************************************
-#define MAC_MTXD_MDTX_M 0x0000FFFF // MII Register Transmit Data.
-#define MAC_MTXD_MDTX_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_MRXD register.
-//
-//*****************************************************************************
-#define MAC_MRXD_MDRX_M 0x0000FFFF // MII Register Receive Data.
-#define MAC_MRXD_MDRX_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_NP register.
-//
-//*****************************************************************************
-#define MAC_NP_NPR_M 0x0000003F // Number of Packets in Receive
- // FIFO.
-#define MAC_NP_NPR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_TXRQ register.
-//
-//*****************************************************************************
-#define MAC_TR_NEWTX 0x00000001 // Start an Ethernet Transmission
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_TS register.
-//
-//*****************************************************************************
-#define MAC_TS_TSEN 0x00000001 // Enable Timestamp Logic
-
-//*****************************************************************************
-//
-// The following are defines for the Ethernet Controller PHY registers.
-//
-//*****************************************************************************
-#define PHY_MR0 0x00000000 // Ethernet PHY Management Register
- // 0 - Control
-#define PHY_MR1 0x00000001 // Ethernet PHY Management Register
- // 1 - Status
-#define PHY_MR2 0x00000002 // Ethernet PHY Management Register
- // 2 - PHY Identifier 1
-#define PHY_MR3 0x00000003 // Ethernet PHY Management Register
- // 3 - PHY Identifier 2
-#define PHY_MR4 0x00000004 // Ethernet PHY Management Register
- // 4 - Auto-Negotiation
- // Advertisement
-#define PHY_MR5 0x00000005 // Ethernet PHY Management Register
- // 5 - Auto-Negotiation Link
- // Partner Base Page Ability
-#define PHY_MR6 0x00000006 // Ethernet PHY Management Register
- // 6 - Auto-Negotiation Expansion
-#define PHY_MR16 0x00000010 // Ethernet PHY Management Register
- // 16 - Vendor-Specific
-#define PHY_MR17 0x00000011 // Ethernet PHY Management Register
- // 17 - Interrupt Control/Status
-#define PHY_MR18 0x00000012 // Ethernet PHY Management Register
- // 18 - Diagnostic
-#define PHY_MR19 0x00000013 // Ethernet PHY Management Register
- // 19 - Transceiver Control
-#define PHY_MR23 0x00000017 // Ethernet PHY Management Register
- // 23 - LED Configuration
-#define PHY_MR24 0x00000018 // Ethernet PHY Management Register
- // 24 -MDI/MDIX Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the PHY_MR0 register.
-//
-//*****************************************************************************
-#define PHY_MR0_RESET 0x00008000 // Reset Registers.
-#define PHY_MR0_LOOPBK 0x00004000 // Loopback Mode.
-#define PHY_MR0_SPEEDSL 0x00002000 // Speed Select.
-#define PHY_MR0_ANEGEN 0x00001000 // Auto-Negotiation Enable.
-#define PHY_MR0_PWRDN 0x00000800 // Power Down.
-#define PHY_MR0_ISO 0x00000400 // Isolate.
-#define PHY_MR0_RANEG 0x00000200 // Restart Auto-Negotiation.
-#define PHY_MR0_DUPLEX 0x00000100 // Set Duplex Mode.
-#define PHY_MR0_COLT 0x00000080 // Collision Test.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_RIS register.
-//
-//*****************************************************************************
-#define MAC_RIS_PHYINT 0x00000040 // PHY Interrupt.
-#define MAC_RIS_MDINT 0x00000020 // MII Transaction Complete.
-#define MAC_RIS_RXER 0x00000010 // Receive Error.
-#define MAC_RIS_FOV 0x00000008 // FIFO Overrrun.
-#define MAC_RIS_TXEMP 0x00000004 // Transmit FIFO Empty.
-#define MAC_RIS_TXER 0x00000002 // Transmit Error.
-#define MAC_RIS_RXINT 0x00000001 // Packet Received.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the PHY_MR1 register.
-//
-//*****************************************************************************
-#define PHY_MR1_100X_F 0x00004000 // 100BASE-TX Full-Duplex Mode.
-#define PHY_MR1_100X_H 0x00002000 // 100BASE-TX Half-Duplex Mode.
-#define PHY_MR1_10T_F 0x00001000 // 10BASE-T Full-Duplex Mode.
-#define PHY_MR1_10T_H 0x00000800 // 10BASE-T Half-Duplex Mode.
-#define PHY_MR1_MFPS 0x00000040 // Management Frames with Preamble
- // Suppressed.
-#define PHY_MR1_ANEGC 0x00000020 // Auto-Negotiation Complete.
-#define PHY_MR1_RFAULT 0x00000010 // Remote Fault.
-#define PHY_MR1_ANEGA 0x00000008 // Auto-Negotiation.
-#define PHY_MR1_LINK 0x00000004 // Link Made.
-#define PHY_MR1_JAB 0x00000002 // Jabber Condition.
-#define PHY_MR1_EXTD 0x00000001 // Extended Capabilities.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the PHY_MR2 register.
-//
-//*****************************************************************************
-#define PHY_MR2_OUI_M 0x0000FFFF // Organizationally Unique
- // Identifier[21:6].
-#define PHY_MR2_OUI_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the PHY_MR3 register.
-//
-//*****************************************************************************
-#define PHY_MR3_OUI_M 0x0000FC00 // Organizationally Unique
- // Identifier[5:0].
-#define PHY_MR3_MN_M 0x000003F0 // Model Number.
-#define PHY_MR3_RN_M 0x0000000F // Revision Number.
-#define PHY_MR3_OUI_S 10
-#define PHY_MR3_MN_S 4
-#define PHY_MR3_RN_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the PHY_MR4 register.
-//
-//*****************************************************************************
-#define PHY_MR4_NP 0x00008000 // Next Page.
-#define PHY_MR4_RF 0x00002000 // Remote Fault.
-#define PHY_MR4_A3 0x00000100 // Technology Ability Field[3].
-#define PHY_MR4_A2 0x00000080 // Technology Ability Field[2].
-#define PHY_MR4_A1 0x00000040 // Technology Ability Field[1].
-#define PHY_MR4_A0 0x00000020 // Technology Ability Field[0].
-#define PHY_MR4_S_M 0x0000001F // Selector Field.
-#define PHY_MR4_S_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the PHY_MR5 register.
-//
-//*****************************************************************************
-#define PHY_MR5_NP 0x00008000 // Next Page.
-#define PHY_MR5_ACK 0x00004000 // Acknowledge.
-#define PHY_MR5_RF 0x00002000 // Remote Fault.
-#define PHY_MR5_A_M 0x00001FE0 // Technology Ability Field.
-#define PHY_MR5_S_M 0x0000001F // Selector Field.
-#define PHY_MR5_S_8023 0x00000001 // IEEE Std 802.3
-#define PHY_MR5_S_8029 0x00000002 // IEEE Std 802.9 ISLAN-16T
-#define PHY_MR5_S_8025 0x00000003 // IEEE Std 802.5
-#define PHY_MR5_S_1394 0x00000004 // IEEE Std 1394
-#define PHY_MR5_A_S 5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the PHY_MR6 register.
-//
-//*****************************************************************************
-#define PHY_MR6_PDF 0x00000010 // Parallel Detection Fault.
-#define PHY_MR6_LPNPA 0x00000008 // Link Partner is Next Page Able.
-#define PHY_MR6_PRX 0x00000002 // New Page Received.
-#define PHY_MR6_LPANEGA 0x00000001 // Link Partner is Auto-Negotiation
- // Able.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_DATA register.
-//
-//*****************************************************************************
-#define MAC_DATA_TXDATA_M 0xFFFFFFFF // Transmit FIFO Data.
-#define MAC_DATA_RXDATA_M 0xFFFFFFFF // Receive FIFO Data.
-#define MAC_DATA_RXDATA_S 0
-#define MAC_DATA_TXDATA_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the PHY_MR16 register.
-//
-//*****************************************************************************
-#define PHY_MR16_RPTR 0x00008000 // Repeater Mode.
-#define PHY_MR16_INPOL 0x00004000 // Interrupt Polarity.
-#define PHY_MR16_TXHIM 0x00001000 // Transmit High Impedance Mode.
-#define PHY_MR16_SQEI 0x00000800 // SQE Inhibit Testing.
-#define PHY_MR16_NL10 0x00000400 // Natural Loopback Mode.
-#define PHY_MR16_APOL 0x00000020 // Auto-Polarity Disable.
-#define PHY_MR16_RVSPOL 0x00000010 // Receive Data Polarity.
-#define PHY_MR16_PCSBP 0x00000002 // PCS Bypass.
-#define PHY_MR16_RXCC 0x00000001 // Receive Clock Control.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the PHY_MR17 register.
-//
-//*****************************************************************************
-#define PHY_MR17_JABBER_IE 0x00008000 // Jabber Interrupt Enable.
-#define PHY_MR17_RXER_IE 0x00004000 // Receive Error Interrupt Enable.
-#define PHY_MR17_PRX_IE 0x00002000 // Page Received Interrupt Enable.
-#define PHY_MR17_PDF_IE 0x00001000 // Parallel Detection Fault
- // Interrupt Enable.
-#define PHY_MR17_LPACK_IE 0x00000800 // LP Acknowledge Interrupt Enable.
-#define PHY_MR17_LSCHG_IE 0x00000400 // Link Status Change Interrupt
- // Enable.
-#define PHY_MR17_RFAULT_IE 0x00000200 // Remote Fault Interrupt Enable.
-#define PHY_MR17_ANEGCOMP_IE 0x00000100 // Auto-Negotiation Complete
- // Interrupt Enable.
-#define PHY_MR17_JABBER_INT 0x00000080 // Jabber Event Interrupt.
-#define PHY_MR17_RXER_INT 0x00000040 // Receive Error Interrupt.
-#define PHY_MR17_PRX_INT 0x00000020 // Page Receive Interrupt.
-#define PHY_MR17_PDF_INT 0x00000010 // Parallel Detection Fault
- // Interrupt.
-#define PHY_MR17_LPACK_INT 0x00000008 // LP Acknowledge Interrupt.
-#define PHY_MR17_LSCHG_INT 0x00000004 // Link Status Change Interrupt.
-#define PHY_MR17_RFAULT_INT 0x00000002 // Remote Fault Interrupt.
-#define PHY_MR17_ANEGCOMP_INT 0x00000001 // Auto-Negotiation Complete
- // Interrupt.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the PHY_MR18 register.
-//
-//*****************************************************************************
-#define PHY_MR18_ANEGF 0x00001000 // Auto-Negotiation Failure.
-#define PHY_MR18_DPLX 0x00000800 // Duplex Mode.
-#define PHY_MR18_RATE 0x00000400 // Rate.
-#define PHY_MR18_RXSD 0x00000200 // Receive Detection.
-#define PHY_MR18_RX_LOCK 0x00000100 // Receive PLL Lock.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the PHY_MR19 register.
-//
-//*****************************************************************************
-#define PHY_MR19_TXO_M 0x0000C000 // Transmit Amplitude Selection.
-#define PHY_MR19_TXO_00DB 0x00000000 // Gain set for 0.0dB of insertion
- // loss
-#define PHY_MR19_TXO_04DB 0x00004000 // Gain set for 0.4dB of insertion
- // loss
-#define PHY_MR19_TXO_08DB 0x00008000 // Gain set for 0.8dB of insertion
- // loss
-#define PHY_MR19_TXO_12DB 0x0000C000 // Gain set for 1.2dB of insertion
- // loss
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the PHY_MR23 register.
-//
-//*****************************************************************************
-#define PHY_MR23_LED1_M 0x000000F0 // LED1 Source.
-#define PHY_MR23_LED1_LINK 0x00000000 // Link OK
-#define PHY_MR23_LED1_RXTX 0x00000010 // RX or TX Activity (Default LED1)
-#define PHY_MR23_LED1_TX 0x00000020 // TX Activity
-#define PHY_MR23_LED1_RX 0x00000030 // RX Activity
-#define PHY_MR23_LED1_COL 0x00000040 // Collision
-#define PHY_MR23_LED1_100 0x00000050 // 100BASE-TX mode
-#define PHY_MR23_LED1_10 0x00000060 // 10BASE-T mode
-#define PHY_MR23_LED1_DUPLEX 0x00000070 // Full-Duplex
-#define PHY_MR23_LED1_LINKACT 0x00000080 // Link OK & Blink=RX or TX
- // Activity
-#define PHY_MR23_LED0_M 0x0000000F // LED0 Source.
-#define PHY_MR23_LED0_LINK 0x00000000 // Link OK (Default LED0)
-#define PHY_MR23_LED0_RXTX 0x00000001 // RX or TX Activity
-#define PHY_MR23_LED0_TX 0x00000002 // TX Activity
-#define PHY_MR23_LED0_RX 0x00000003 // RX Activity
-#define PHY_MR23_LED0_COL 0x00000004 // Collision
-#define PHY_MR23_LED0_100 0x00000005 // 100BASE-TX mode
-#define PHY_MR23_LED0_10 0x00000006 // 10BASE-T mode
-#define PHY_MR23_LED0_DUPLEX 0x00000007 // Full-Duplex
-#define PHY_MR23_LED0_LINKACT 0x00000008 // Link OK & Blink=RX or TX
- // Activity
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the PHY_MR24 register.
-//
-//*****************************************************************************
-#define PHY_MR24_PD_MODE 0x00000080 // Parallel Detection Mode.
-#define PHY_MR24_AUTO_SW 0x00000040 // Auto-Switching Enable.
-#define PHY_MR24_MDIX 0x00000020 // Auto-Switching Configuration.
-#define PHY_MR24_MDIX_CM 0x00000010 // Auto-Switching Complete.
-#define PHY_MR24_MDIX_SD_M 0x0000000F // Auto-Switching Seed.
-#define PHY_MR24_MDIX_SD_S 0
-
-//*****************************************************************************
-//
-// The following definitions are deprecated.
-//
-//*****************************************************************************
-#ifndef DEPRECATED
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the MAC register offsets in the
-// Ethernet Controller.
-//
-//*****************************************************************************
-#define MAC_O_IS 0x00000000 // Interrupt Status Register
-#define MAC_O_MADD 0x00000028 // Management Address Register
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the reset values of the MAC
-// registers.
-//
-//*****************************************************************************
-#define MAC_RV_MDV 0x00000080
-#define MAC_RV_IM 0x0000007F
-#define MAC_RV_THR 0x0000003F
-#define MAC_RV_RCTL 0x00000008
-#define MAC_RV_IA0 0x00000000
-#define MAC_RV_TCTL 0x00000000
-#define MAC_RV_DATA 0x00000000
-#define MAC_RV_MRXD 0x00000000
-#define MAC_RV_TR 0x00000000
-#define MAC_RV_IS 0x00000000
-#define MAC_RV_NP 0x00000000
-#define MAC_RV_MCTL 0x00000000
-#define MAC_RV_MTXD 0x00000000
-#define MAC_RV_IA1 0x00000000
-#define MAC_RV_IACK 0x00000000
-#define MAC_RV_MADD 0x00000000
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the MAC_IS
-// register.
-//
-//*****************************************************************************
-#define MAC_IS_PHYINT 0x00000040 // PHY Interrupt
-#define MAC_IS_MDINT 0x00000020 // MDI Transaction Complete
-#define MAC_IS_RXER 0x00000010 // RX Error
-#define MAC_IS_FOV 0x00000008 // RX FIFO Overrun
-#define MAC_IS_TXEMP 0x00000004 // TX FIFO Empy
-#define MAC_IS_TXER 0x00000002 // TX Error
-#define MAC_IS_RXINT 0x00000001 // RX Packet Available
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the MAC_IA0
-// register.
-//
-//*****************************************************************************
-#define MAC_IA0_MACOCT4 0xFF000000 // 4th Octet of MAC address
-#define MAC_IA0_MACOCT3 0x00FF0000 // 3rd Octet of MAC address
-#define MAC_IA0_MACOCT2 0x0000FF00 // 2nd Octet of MAC address
-#define MAC_IA0_MACOCT1 0x000000FF // 1st Octet of MAC address
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the MAC_IA1
-// register.
-//
-//*****************************************************************************
-#define MAC_IA1_MACOCT6 0x0000FF00 // 6th Octet of MAC address
-#define MAC_IA1_MACOCT5 0x000000FF // 5th Octet of MAC address
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the MAC_TXTH
-// register.
-//
-//*****************************************************************************
-#define MAC_THR_THRESH 0x0000003F // Transmit Threshold Value
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the MAC_MCTL
-// register.
-//
-//*****************************************************************************
-#define MAC_MCTL_REGADR 0x000000F8 // Address for Next MII Transaction
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the MAC_MDV
-// register.
-//
-//*****************************************************************************
-#define MAC_MDV_DIV 0x000000FF // Clock Divider for MDC for TX
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the MAC_MTXD
-// register.
-//
-//*****************************************************************************
-#define MAC_MTXD_MDTX 0x0000FFFF // Data for Next MII Transaction
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the MAC_MRXD
-// register.
-//
-//*****************************************************************************
-#define MAC_MRXD_MDRX 0x0000FFFF // Data Read from Last MII Trans.
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the MAC_NP
-// register.
-//
-//*****************************************************************************
-#define MAC_NP_NPR 0x0000003F // Number of RX Frames in FIFO
-
-#endif
-
-#endif // __HW_ETHERNET_H__
+//*****************************************************************************
+//
+// hw_ethernet.h - Macros used when accessing the Ethernet hardware.
+//
+// Copyright (c) 2006-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4781 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_ETHERNET_H__
+#define __HW_ETHERNET_H__
+
+//*****************************************************************************
+//
+// The following are defines for the MAC register offsets in the Ethernet
+// Controller.
+//
+//*****************************************************************************
+#define MAC_O_RIS 0x00000000 // Ethernet MAC Raw Interrupt
+ // Status
+#define MAC_O_IACK 0x00000000 // Interrupt Acknowledge Register
+#define MAC_O_IM 0x00000004 // Interrupt Mask Register
+#define MAC_O_RCTL 0x00000008 // Receive Control Register
+#define MAC_O_TCTL 0x0000000C // Transmit Control Register
+#define MAC_O_DATA 0x00000010 // Data Register
+#define MAC_O_IA0 0x00000014 // Individual Address Register 0
+#define MAC_O_IA1 0x00000018 // Individual Address Register 1
+#define MAC_O_THR 0x0000001C // Threshold Register
+#define MAC_O_MCTL 0x00000020 // Management Control Register
+#define MAC_O_MDV 0x00000024 // Management Divider Register
+#define MAC_O_MTXD 0x0000002C // Management Transmit Data Reg
+#define MAC_O_MRXD 0x00000030 // Management Receive Data Reg
+#define MAC_O_NP 0x00000034 // Number of Packets Register
+#define MAC_O_TR 0x00000038 // Transmission Request Register
+#define MAC_O_TS 0x0000003C // Timer Support Register
+#define MAC_O_LED 0x00000040 // Ethernet MAC LED Encoding
+#define MAC_O_MDIX 0x00000044 // MDIX Register
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_IACK register.
+//
+//*****************************************************************************
+#define MAC_IACK_PHYINT 0x00000040 // Clear PHY Interrupt
+#define MAC_IACK_MDINT 0x00000020 // Clear MDI Transaction Complete
+#define MAC_IACK_RXER 0x00000010 // Clear RX Error
+#define MAC_IACK_FOV 0x00000008 // Clear RX FIFO Overrun
+#define MAC_IACK_TXEMP 0x00000004 // Clear TX FIFO Empy
+#define MAC_IACK_TXER 0x00000002 // Clear TX Error
+#define MAC_IACK_RXINT 0x00000001 // Clear RX Packet Available
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_IM register.
+//
+//*****************************************************************************
+#define MAC_IM_PHYINTM 0x00000040 // Mask PHY Interrupt
+#define MAC_IM_MDINTM 0x00000020 // Mask MDI Transaction Complete
+#define MAC_IM_RXERM 0x00000010 // Mask RX Error
+#define MAC_IM_FOVM 0x00000008 // Mask RX FIFO Overrun
+#define MAC_IM_TXEMPM 0x00000004 // Mask TX FIFO Empy
+#define MAC_IM_TXERM 0x00000002 // Mask TX Error
+#define MAC_IM_RXINTM 0x00000001 // Mask RX Packet Available
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_RCTL register.
+//
+//*****************************************************************************
+#define MAC_RCTL_RSTFIFO 0x00000010 // Clear the Receive FIFO
+#define MAC_RCTL_BADCRC 0x00000008 // Reject Packets With Bad CRC
+#define MAC_RCTL_PRMS 0x00000004 // Enable Promiscuous Mode
+#define MAC_RCTL_AMUL 0x00000002 // Enable Multicast Packets
+#define MAC_RCTL_RXEN 0x00000001 // Enable Ethernet Receiver
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_TCTL register.
+//
+//*****************************************************************************
+#define MAC_TCTL_DUPLEX 0x00000010 // Enable Duplex mode
+#define MAC_TCTL_CRC 0x00000004 // Enable CRC Generation
+#define MAC_TCTL_PADEN 0x00000002 // Enable Automatic Padding
+#define MAC_TCTL_TXEN 0x00000001 // Enable Ethernet Transmitter
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_IA0 register.
+//
+//*****************************************************************************
+#define MAC_IA0_MACOCT4_M 0xFF000000 // MAC Address Octet 4.
+#define MAC_IA0_MACOCT3_M 0x00FF0000 // MAC Address Octet 3.
+#define MAC_IA0_MACOCT2_M 0x0000FF00 // MAC Address Octet 2.
+#define MAC_IA0_MACOCT1_M 0x000000FF // MAC Address Octet 1.
+#define MAC_IA0_MACOCT4_S 24
+#define MAC_IA0_MACOCT3_S 16
+#define MAC_IA0_MACOCT2_S 8
+#define MAC_IA0_MACOCT1_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_IA1 register.
+//
+//*****************************************************************************
+#define MAC_IA1_MACOCT6_M 0x0000FF00 // MAC Address Octet 6.
+#define MAC_IA1_MACOCT5_M 0x000000FF // MAC Address Octet 5.
+#define MAC_IA1_MACOCT6_S 8
+#define MAC_IA1_MACOCT5_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_TXTH register.
+//
+//*****************************************************************************
+#define MAC_THR_THRESH_M 0x0000003F // Threshold Value.
+#define MAC_THR_THRESH_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_MCTL register.
+//
+//*****************************************************************************
+#define MAC_MCTL_REGADR_M 0x000000F8 // MII Register Address.
+#define MAC_MCTL_WRITE 0x00000002 // Next MII Transaction is Write
+#define MAC_MCTL_START 0x00000001 // Start MII Transaction
+#define MAC_MCTL_REGADR_S 3
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_MDV register.
+//
+//*****************************************************************************
+#define MAC_MDV_DIV_M 0x000000FF // Clock Divider.
+#define MAC_MDV_DIV_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_MTXD register.
+//
+//*****************************************************************************
+#define MAC_MTXD_MDTX_M 0x0000FFFF // MII Register Transmit Data.
+#define MAC_MTXD_MDTX_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_MRXD register.
+//
+//*****************************************************************************
+#define MAC_MRXD_MDRX_M 0x0000FFFF // MII Register Receive Data.
+#define MAC_MRXD_MDRX_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_NP register.
+//
+//*****************************************************************************
+#define MAC_NP_NPR_M 0x0000003F // Number of Packets in Receive
+ // FIFO.
+#define MAC_NP_NPR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_TXRQ register.
+//
+//*****************************************************************************
+#define MAC_TR_NEWTX 0x00000001 // Start an Ethernet Transmission
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_TS register.
+//
+//*****************************************************************************
+#define MAC_TS_TSEN 0x00000001 // Enable Timestamp Logic
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_MDIX register.
+//
+//*****************************************************************************
+#define MAC_MDIX_EN 0x00000001 // MDI/MDI-X Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the Ethernet Controller PHY registers.
+//
+//*****************************************************************************
+#define PHY_MR0 0x00000000 // Ethernet PHY Management Register
+ // 0 - Control
+#define PHY_MR1 0x00000001 // Ethernet PHY Management Register
+ // 1 - Status
+#define PHY_MR2 0x00000002 // Ethernet PHY Management Register
+ // 2 - PHY Identifier 1
+#define PHY_MR3 0x00000003 // Ethernet PHY Management Register
+ // 3 - PHY Identifier 2
+#define PHY_MR4 0x00000004 // Ethernet PHY Management Register
+ // 4 - Auto-Negotiation
+ // Advertisement
+#define PHY_MR5 0x00000005 // Ethernet PHY Management Register
+ // 5 - Auto-Negotiation Link
+ // Partner Base Page Ability
+#define PHY_MR6 0x00000006 // Ethernet PHY Management Register
+ // 6 - Auto-Negotiation Expansion
+#define PHY_MR16 0x00000010 // Ethernet PHY Management Register
+ // 16 - Vendor-Specific
+#define PHY_MR17 0x00000011 // Ethernet PHY Management Register
+ // 17 - Interrupt Control/Status
+#define PHY_MR18 0x00000012 // Ethernet PHY Management Register
+ // 18 - Diagnostic
+#define PHY_MR19 0x00000013 // Ethernet PHY Management Register
+ // 19 - Transceiver Control
+#define PHY_MR23 0x00000017 // Ethernet PHY Management Register
+ // 23 - LED Configuration
+#define PHY_MR24 0x00000018 // Ethernet PHY Management Register
+ // 24 -MDI/MDIX Control
+#define PHY_MR27 0x0000001B // Ethernet PHY Management Register
+ // 27 -Special Control/Status
+#define PHY_MR29 0x0000001D // Ethernet PHY Management Register
+ // 29 - Interrupt Status
+#define PHY_MR30 0x0000001E // Ethernet PHY Management Register
+ // 30 - Interrupt Mask
+#define PHY_MR31 0x0000001F // Ethernet PHY Management Register
+ // 31 - PHY Special Control/Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR0 register.
+//
+//*****************************************************************************
+#define PHY_MR0_RESET 0x00008000 // Reset Registers.
+#define PHY_MR0_LOOPBK 0x00004000 // Loopback Mode.
+#define PHY_MR0_SPEEDSL 0x00002000 // Speed Select.
+#define PHY_MR0_ANEGEN 0x00001000 // Auto-Negotiation Enable.
+#define PHY_MR0_PWRDN 0x00000800 // Power Down.
+#define PHY_MR0_ISO 0x00000400 // Isolate.
+#define PHY_MR0_RANEG 0x00000200 // Restart Auto-Negotiation.
+#define PHY_MR0_DUPLEX 0x00000100 // Set Duplex Mode.
+#define PHY_MR0_COLT 0x00000080 // Collision Test.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_RIS register.
+//
+//*****************************************************************************
+#define MAC_RIS_PHYINT 0x00000040 // PHY Interrupt.
+#define MAC_RIS_MDINT 0x00000020 // MII Transaction Complete.
+#define MAC_RIS_RXER 0x00000010 // Receive Error.
+#define MAC_RIS_FOV 0x00000008 // FIFO Overrrun.
+#define MAC_RIS_TXEMP 0x00000004 // Transmit FIFO Empty.
+#define MAC_RIS_TXER 0x00000002 // Transmit Error.
+#define MAC_RIS_RXINT 0x00000001 // Packet Received.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR1 register.
+//
+//*****************************************************************************
+#define PHY_MR1_100X_F 0x00004000 // 100BASE-TX Full-Duplex Mode.
+#define PHY_MR1_100X_H 0x00002000 // 100BASE-TX Half-Duplex Mode.
+#define PHY_MR1_10T_F 0x00001000 // 10BASE-T Full-Duplex Mode.
+#define PHY_MR1_10T_H 0x00000800 // 10BASE-T Half-Duplex Mode.
+#define PHY_MR1_MFPS 0x00000040 // Management Frames with Preamble
+ // Suppressed.
+#define PHY_MR1_ANEGC 0x00000020 // Auto-Negotiation Complete.
+#define PHY_MR1_RFAULT 0x00000010 // Remote Fault.
+#define PHY_MR1_ANEGA 0x00000008 // Auto-Negotiation.
+#define PHY_MR1_LINK 0x00000004 // Link Made.
+#define PHY_MR1_JAB 0x00000002 // Jabber Condition.
+#define PHY_MR1_EXTD 0x00000001 // Extended Capabilities.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR2 register.
+//
+//*****************************************************************************
+#define PHY_MR2_OUI_M 0x0000FFFF // Organizationally Unique
+ // Identifier[21:6].
+#define PHY_MR2_OUI_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR3 register.
+//
+//*****************************************************************************
+#define PHY_MR3_OUI_M 0x0000FC00 // Organizationally Unique
+ // Identifier[5:0].
+#define PHY_MR3_MN_M 0x000003F0 // Model Number.
+#define PHY_MR3_RN_M 0x0000000F // Revision Number.
+#define PHY_MR3_OUI_S 10
+#define PHY_MR3_MN_S 4
+#define PHY_MR3_RN_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR4 register.
+//
+//*****************************************************************************
+#define PHY_MR4_NP 0x00008000 // Next Page.
+#define PHY_MR4_RF 0x00002000 // Remote Fault.
+#define PHY_MR4_A3 0x00000100 // Technology Ability Field[3].
+#define PHY_MR4_A2 0x00000080 // Technology Ability Field[2].
+#define PHY_MR4_A1 0x00000040 // Technology Ability Field[1].
+#define PHY_MR4_A0 0x00000020 // Technology Ability Field[0].
+#define PHY_MR4_S_M 0x0000001F // Selector Field.
+#define PHY_MR4_S_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR5 register.
+//
+//*****************************************************************************
+#define PHY_MR5_NP 0x00008000 // Next Page.
+#define PHY_MR5_ACK 0x00004000 // Acknowledge.
+#define PHY_MR5_RF 0x00002000 // Remote Fault.
+#define PHY_MR5_A_M 0x00001FE0 // Technology Ability Field.
+#define PHY_MR5_S_M 0x0000001F // Selector Field.
+#define PHY_MR5_S_8023 0x00000001 // IEEE Std 802.3
+#define PHY_MR5_S_8029 0x00000002 // IEEE Std 802.9 ISLAN-16T
+#define PHY_MR5_S_8025 0x00000003 // IEEE Std 802.5
+#define PHY_MR5_S_1394 0x00000004 // IEEE Std 1394
+#define PHY_MR5_A_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR6 register.
+//
+//*****************************************************************************
+#define PHY_MR6_PDF 0x00000010 // Parallel Detection Fault.
+#define PHY_MR6_LPNPA 0x00000008 // Link Partner is Next Page Able.
+#define PHY_MR6_PRX 0x00000002 // New Page Received.
+#define PHY_MR6_LPANEGA 0x00000001 // Link Partner is Auto-Negotiation
+ // Able.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_DATA register.
+//
+//*****************************************************************************
+#define MAC_DATA_TXDATA_M 0xFFFFFFFF // Transmit FIFO Data.
+#define MAC_DATA_RXDATA_M 0xFFFFFFFF // Receive FIFO Data.
+#define MAC_DATA_RXDATA_S 0
+#define MAC_DATA_TXDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR16 register.
+//
+//*****************************************************************************
+#define PHY_MR16_RPTR 0x00008000 // Repeater Mode.
+#define PHY_MR16_INPOL 0x00004000 // Interrupt Polarity.
+#define PHY_MR16_TXHIM 0x00001000 // Transmit High Impedance Mode.
+#define PHY_MR16_SQEI 0x00000800 // SQE Inhibit Testing.
+#define PHY_MR16_NL10 0x00000400 // Natural Loopback Mode.
+#define PHY_MR16_SR_M 0x000003C0 // Silicon Revision Identifier.
+#define PHY_MR16_APOL 0x00000020 // Auto-Polarity Disable.
+#define PHY_MR16_RVSPOL 0x00000010 // Receive Data Polarity.
+#define PHY_MR16_PCSBP 0x00000002 // PCS Bypass.
+#define PHY_MR16_RXCC 0x00000001 // Receive Clock Control.
+#define PHY_MR16_SR_S 6
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR17 register.
+//
+//*****************************************************************************
+#define PHY_MR17_JABBER_IE 0x00008000 // Jabber Interrupt Enable.
+#define PHY_MR17_FASTRIP 0x00004000 // 10-BASE-T Fast Mode Enable.
+#define PHY_MR17_RXER_IE 0x00004000 // Receive Error Interrupt Enable.
+#define PHY_MR17_EDPD 0x00002000 // Enable Energy Detect Power Down.
+#define PHY_MR17_PRX_IE 0x00002000 // Page Received Interrupt Enable.
+#define PHY_MR17_PDF_IE 0x00001000 // Parallel Detection Fault
+ // Interrupt Enable.
+#define PHY_MR17_LSQE 0x00000800 // Low Squelch Enable.
+#define PHY_MR17_LPACK_IE 0x00000800 // LP Acknowledge Interrupt Enable.
+#define PHY_MR17_LSCHG_IE 0x00000400 // Link Status Change Interrupt
+ // Enable.
+#define PHY_MR17_MDPB 0x00000400 // Management Data Preamble Bypass.
+#define PHY_MR17_RFAULT_IE 0x00000200 // Remote Fault Interrupt Enable.
+#define PHY_MR17_FLPBK 0x00000200 // Far Loopback Mode.
+#define PHY_MR17_ANEGCOMP_IE 0x00000100 // Auto-Negotiation Complete
+ // Interrupt Enable.
+#define PHY_MR17_FASTEST 0x00000100 // Auto-Negotiation Test Mode.
+#define PHY_MR17_JABBER_INT 0x00000080 // Jabber Event Interrupt.
+#define PHY_MR17_RXER_INT 0x00000040 // Receive Error Interrupt.
+#define PHY_MR17_PRX_INT 0x00000020 // Page Receive Interrupt.
+#define PHY_MR17_PDF_INT 0x00000010 // Parallel Detection Fault
+ // Interrupt.
+#define PHY_MR17_REFCE 0x00000010 // Reference Clock Enable.
+#define PHY_MR17_LPACK_INT 0x00000008 // LP Acknowledge Interrupt.
+#define PHY_MR17_PADBP 0x00000008 // PHY Address Bypass.
+#define PHY_MR17_LSCHG_INT 0x00000004 // Link Status Change Interrupt.
+#define PHY_MR17_FGLS 0x00000004 // Force Good Link Status.
+#define PHY_MR17_RFAULT_INT 0x00000002 // Remote Fault Interrupt.
+#define PHY_MR17_ENON 0x00000002 // Energy On.
+#define PHY_MR17_ANEGCOMP_INT 0x00000001 // Auto-Negotiation Complete
+ // Interrupt.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR18 register.
+//
+//*****************************************************************************
+#define PHY_MR18_ANEGF 0x00001000 // Auto-Negotiation Failure.
+#define PHY_MR18_DPLX 0x00000800 // Duplex Mode.
+#define PHY_MR18_RATE 0x00000400 // Rate.
+#define PHY_MR18_RXSD 0x00000200 // Receive Detection.
+#define PHY_MR18_RX_LOCK 0x00000100 // Receive PLL Lock.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR19 register.
+//
+//*****************************************************************************
+#define PHY_MR19_TXO_M 0x0000C000 // Transmit Amplitude Selection.
+#define PHY_MR19_TXO_00DB 0x00000000 // Gain set for 0.0dB of insertion
+ // loss
+#define PHY_MR19_TXO_04DB 0x00004000 // Gain set for 0.4dB of insertion
+ // loss
+#define PHY_MR19_TXO_08DB 0x00008000 // Gain set for 0.8dB of insertion
+ // loss
+#define PHY_MR19_TXO_12DB 0x0000C000 // Gain set for 1.2dB of insertion
+ // loss
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR23 register.
+//
+//*****************************************************************************
+#define PHY_MR23_LED1_M 0x000000F0 // LED1 Source.
+#define PHY_MR23_LED1_LINK 0x00000000 // Link OK
+#define PHY_MR23_LED1_RXTX 0x00000010 // RX or TX Activity (Default LED1)
+#define PHY_MR23_LED1_100 0x00000050 // 100BASE-TX mode
+#define PHY_MR23_LED1_10 0x00000060 // 10BASE-T mode
+#define PHY_MR23_LED1_DUPLEX 0x00000070 // Full-Duplex
+#define PHY_MR23_LED1_LINKACT 0x00000080 // Link OK & Blink=RX or TX
+ // Activity
+#define PHY_MR23_LED0_M 0x0000000F // LED0 Source.
+#define PHY_MR23_LED0_LINK 0x00000000 // Link OK (Default LED0)
+#define PHY_MR23_LED0_RXTX 0x00000001 // RX or TX Activity
+#define PHY_MR23_LED0_100 0x00000005 // 100BASE-TX mode
+#define PHY_MR23_LED0_10 0x00000006 // 10BASE-T mode
+#define PHY_MR23_LED0_DUPLEX 0x00000007 // Full-Duplex
+#define PHY_MR23_LED0_LINKACT 0x00000008 // Link OK & Blink=RX or TX
+ // Activity
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR24 register.
+//
+//*****************************************************************************
+#define PHY_MR24_PD_MODE 0x00000080 // Parallel Detection Mode.
+#define PHY_MR24_AUTO_SW 0x00000040 // Auto-Switching Enable.
+#define PHY_MR24_MDIX 0x00000020 // Auto-Switching Configuration.
+#define PHY_MR24_MDIX_CM 0x00000010 // Auto-Switching Complete.
+#define PHY_MR24_MDIX_SD_M 0x0000000F // Auto-Switching Seed.
+#define PHY_MR24_MDIX_SD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR27 register.
+//
+//*****************************************************************************
+#define PHY_MR27_XPOL 0x00000010 // Polarity State of 10 BASE-T.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR29 register.
+//
+//*****************************************************************************
+#define PHY_MR29_EONIS 0x00000080 // ENERGYON Interrupt.
+#define PHY_MR29_ANCOMPIS 0x00000040 // Auto-Negotiation Complete
+ // Interrupt.
+#define PHY_MR29_RFLTIS 0x00000020 // Remote Fault Interrupt.
+#define PHY_MR29_LDIS 0x00000010 // Link Down Interrupt.
+#define PHY_MR29_LPACKIS 0x00000008 // Auto-Negotiation LP Acknowledge.
+#define PHY_MR29_PDFIS 0x00000004 // Parallel Detection Fault.
+#define PHY_MR29_PRXIS 0x00000002 // Auto Negotiation Page Received.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR30 register.
+//
+//*****************************************************************************
+#define PHY_MR30_EONIM 0x00000080 // ENERGYON Interrupt Enabled.
+#define PHY_MR30_ANCOMPIM 0x00000040 // Auto-Negotiation Complete
+ // Interrupt Enabled.
+#define PHY_MR30_RFLTIM 0x00000020 // Remote Fault Interrupt Enabled.
+#define PHY_MR30_LDIM 0x00000010 // Link Down Interrupt Enabled.
+#define PHY_MR30_LPACKIM 0x00000008 // Auto-Negotiation LP Acknowledge
+ // Enabled.
+#define PHY_MR30_PDFIM 0x00000004 // Parallel Detection Fault
+ // Enabled.
+#define PHY_MR30_PRXIM 0x00000002 // Auto Negotiation Page Received
+ // Enabled.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR31 register.
+//
+//*****************************************************************************
+#define PHY_MR31_BPRMG 0x00008000 // Bypass Remove Glitch.
+#define PHY_MR31_AUTODONE 0x00001000 // Auto Negotiation Done.
+#define PHY_MR31_EN4B5B 0x00000040 // Enable 4B5B Encoding/Decoding.
+#define PHY_MR31_SPEED_M 0x0000001C // HCD Speed Value.
+#define PHY_MR31_SCRDIS 0x00000001 // Scramble Disable.
+#define PHY_MR31_SPEED_S 2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_LED register.
+//
+//*****************************************************************************
+#define MAC_LED_LED1_M 0x000000F0 // LED1 Source.
+#define MAC_LED_LED1_LINK 0x00000000 // Link OK
+#define MAC_LED_LED1_RXTX 0x00000010 // RX or TX Activity (Default LED1)
+#define MAC_LED_LED1_100 0x00000050 // 100BASE-TX mode
+#define MAC_LED_LED1_10 0x00000060 // 10BASE-T mode
+#define MAC_LED_LED1_DUPLEX 0x00000070 // Full-Duplex
+#define MAC_LED_LED1_LINKACT 0x00000080 // Link OK & Blink=RX or TX
+ // Activity
+#define MAC_LED_LED0_M 0x0000000F // LED0 Source.
+#define MAC_LED_LED0_LINK 0x00000000 // Link OK (Default LED0)
+#define MAC_LED_LED0_RXTX 0x00000001 // RX or TX Activity
+#define MAC_LED_LED0_100 0x00000005 // 100BASE-TX mode
+#define MAC_LED_LED0_10 0x00000006 // 10BASE-T mode
+#define MAC_LED_LED0_DUPLEX 0x00000007 // Full-Duplex
+#define MAC_LED_LED0_LINKACT 0x00000008 // Link OK & Blink=RX or TX
+ // Activity
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the MAC register offsets in the
+// Ethernet Controller.
+//
+//*****************************************************************************
+#define MAC_O_IS 0x00000000 // Interrupt Status Register
+#define MAC_O_MADD 0x00000028 // Management Address Register
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the reset values of the MAC
+// registers.
+//
+//*****************************************************************************
+#define MAC_RV_MDV 0x00000080
+#define MAC_RV_IM 0x0000007F
+#define MAC_RV_THR 0x0000003F
+#define MAC_RV_RCTL 0x00000008
+#define MAC_RV_IA0 0x00000000
+#define MAC_RV_TCTL 0x00000000
+#define MAC_RV_DATA 0x00000000
+#define MAC_RV_MRXD 0x00000000
+#define MAC_RV_TR 0x00000000
+#define MAC_RV_IS 0x00000000
+#define MAC_RV_NP 0x00000000
+#define MAC_RV_MCTL 0x00000000
+#define MAC_RV_MTXD 0x00000000
+#define MAC_RV_IA1 0x00000000
+#define MAC_RV_IACK 0x00000000
+#define MAC_RV_MADD 0x00000000
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the MAC_IS
+// register.
+//
+//*****************************************************************************
+#define MAC_IS_PHYINT 0x00000040 // PHY Interrupt
+#define MAC_IS_MDINT 0x00000020 // MDI Transaction Complete
+#define MAC_IS_RXER 0x00000010 // RX Error
+#define MAC_IS_FOV 0x00000008 // RX FIFO Overrun
+#define MAC_IS_TXEMP 0x00000004 // TX FIFO Empy
+#define MAC_IS_TXER 0x00000002 // TX Error
+#define MAC_IS_RXINT 0x00000001 // RX Packet Available
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the MAC_IA0
+// register.
+//
+//*****************************************************************************
+#define MAC_IA0_MACOCT4 0xFF000000 // 4th Octet of MAC address
+#define MAC_IA0_MACOCT3 0x00FF0000 // 3rd Octet of MAC address
+#define MAC_IA0_MACOCT2 0x0000FF00 // 2nd Octet of MAC address
+#define MAC_IA0_MACOCT1 0x000000FF // 1st Octet of MAC address
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the MAC_IA1
+// register.
+//
+//*****************************************************************************
+#define MAC_IA1_MACOCT6 0x0000FF00 // 6th Octet of MAC address
+#define MAC_IA1_MACOCT5 0x000000FF // 5th Octet of MAC address
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the MAC_TXTH
+// register.
+//
+//*****************************************************************************
+#define MAC_THR_THRESH 0x0000003F // Transmit Threshold Value
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the MAC_MCTL
+// register.
+//
+//*****************************************************************************
+#define MAC_MCTL_REGADR 0x000000F8 // Address for Next MII Transaction
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the MAC_MDV
+// register.
+//
+//*****************************************************************************
+#define MAC_MDV_DIV 0x000000FF // Clock Divider for MDC for TX
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the MAC_MTXD
+// register.
+//
+//*****************************************************************************
+#define MAC_MTXD_MDTX 0x0000FFFF // Data for Next MII Transaction
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the MAC_MRXD
+// register.
+//
+//*****************************************************************************
+#define MAC_MRXD_MDRX 0x0000FFFF // Data Read from Last MII Trans.
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the MAC_NP
+// register.
+//
+//*****************************************************************************
+#define MAC_NP_NPR 0x0000003F // Number of RX Frames in FIFO
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the PHY_MR23
+// register.
+//
+//*****************************************************************************
+#define PHY_MR23_LED1_TX 0x00000020 // TX Activity
+#define PHY_MR23_LED1_RX 0x00000030 // RX Activity
+#define PHY_MR23_LED1_COL 0x00000040 // Collision
+#define PHY_MR23_LED0_TX 0x00000002 // TX Activity
+#define PHY_MR23_LED0_RX 0x00000003 // RX Activity
+#define PHY_MR23_LED0_COL 0x00000004 // Collision
+
+#endif
+
+#endif // __HW_ETHERNET_H__
Property changes on: branches/eagle_mmc/src/platform/lm3s/hw_ethernet.h
___________________________________________________________________
Name: svn:executable
+ *
Modified: branches/eagle_mmc/src/platform/lm3s/hw_flash.h
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/hw_flash.h 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lm3s/hw_flash.h 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,295 +1,328 @@
-//*****************************************************************************
-//
-// hw_flash.h - Macros used when accessing the flash controller.
-//
-// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
-// Software License Agreement
-//
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
-//
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws. All rights are reserved. You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program. Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
-//
-// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-//
-// This is part of revision 3740 of the Stellaris Firmware Development Package.
-//
-//*****************************************************************************
-
-#ifndef __HW_FLASH_H__
-#define __HW_FLASH_H__
-
-//*****************************************************************************
-//
-// The following are defines for the FLASH register offsets.
-//
-//*****************************************************************************
-#define FLASH_FMA 0x400FD000 // Memory address register
-#define FLASH_FMD 0x400FD004 // Memory data register
-#define FLASH_FMC 0x400FD008 // Memory control register
-#define FLASH_FCRIS 0x400FD00C // Raw interrupt status register
-#define FLASH_FCIM 0x400FD010 // Interrupt mask register
-#define FLASH_FCMISC 0x400FD014 // Interrupt status register
-#define FLASH_RMCTL 0x400FE0F0 // ROM Control
-#define FLASH_RMVER 0x400FE0F4 // ROM Version Register
-#define FLASH_FMPRE 0x400FE130 // FLASH read protect register
-#define FLASH_FMPPE 0x400FE134 // FLASH program protect register
-#define FLASH_USECRL 0x400FE140 // uSec reload register
-#define FLASH_USERDBG 0x400FE1D0 // User Debug
-#define FLASH_USERREG0 0x400FE1E0 // User Register 0
-#define FLASH_USERREG1 0x400FE1E4 // User Register 1
-#define FLASH_USERREG2 0x400FE1E8 // User Register 2
-#define FLASH_USERREG3 0x400FE1EC // User Register 3
-#define FLASH_FMPRE0 0x400FE200 // FLASH read protect register 0
-#define FLASH_FMPRE1 0x400FE204 // FLASH read protect register 1
-#define FLASH_FMPRE2 0x400FE208 // FLASH read protect register 2
-#define FLASH_FMPRE3 0x400FE20C // FLASH read protect register 3
-#define FLASH_FMPPE0 0x400FE400 // FLASH program protect register 0
-#define FLASH_FMPPE1 0x400FE404 // FLASH program protect register 1
-#define FLASH_FMPPE2 0x400FE408 // FLASH program protect register 2
-#define FLASH_FMPPE3 0x400FE40C // FLASH program protect register 3
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the FLASH_FMC register.
-//
-//*****************************************************************************
-#define FLASH_FMC_WRKEY_M 0xFFFF0000 // FLASH write key mask
-#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key
-#define FLASH_FMC_COMT 0x00000008 // Commit user register
-#define FLASH_FMC_MERASE 0x00000004 // Mass erase FLASH
-#define FLASH_FMC_ERASE 0x00000002 // Erase FLASH page
-#define FLASH_FMC_WRITE 0x00000001 // Write FLASH word
-#define FLASH_FMC_WRKEY_S 16
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the FLASH_FCRIS register.
-//
-//*****************************************************************************
-#define FLASH_FCRIS_PRIS 0x00000002 // Programming Raw Interrupt
- // Status.
-#define FLASH_FCRIS_ARIS 0x00000001 // Access Raw Interrupt Status.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the FLASH_FCIM register.
-//
-//*****************************************************************************
-#define FLASH_FCIM_PMASK 0x00000002 // Programming Interrupt Mask.
-#define FLASH_FCIM_AMASK 0x00000001 // Access Interrupt Mask.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the FLASH_FMIS register.
-//
-//*****************************************************************************
-#define FLASH_FCMISC_PMISC 0x00000002 // Programming Masked Interrupt
- // Status and Clear.
-#define FLASH_FCMISC_AMISC 0x00000001 // Access Masked Interrupt Status
- // and Clear.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the FLASH_FMPRE and
-// FLASH_FMPPE registers.
-//
-//*****************************************************************************
-#define FLASH_FMP_BLOCK_31 0x80000000 // Enable for block 31
-#define FLASH_FMP_BLOCK_30 0x40000000 // Enable for block 30
-#define FLASH_FMP_BLOCK_29 0x20000000 // Enable for block 29
-#define FLASH_FMP_BLOCK_28 0x10000000 // Enable for block 28
-#define FLASH_FMP_BLOCK_27 0x08000000 // Enable for block 27
-#define FLASH_FMP_BLOCK_26 0x04000000 // Enable for block 26
-#define FLASH_FMP_BLOCK_25 0x02000000 // Enable for block 25
-#define FLASH_FMP_BLOCK_24 0x01000000 // Enable for block 24
-#define FLASH_FMP_BLOCK_23 0x00800000 // Enable for block 23
-#define FLASH_FMP_BLOCK_22 0x00400000 // Enable for block 22
-#define FLASH_FMP_BLOCK_21 0x00200000 // Enable for block 21
-#define FLASH_FMP_BLOCK_20 0x00100000 // Enable for block 20
-#define FLASH_FMP_BLOCK_19 0x00080000 // Enable for block 19
-#define FLASH_FMP_BLOCK_18 0x00040000 // Enable for block 18
-#define FLASH_FMP_BLOCK_17 0x00020000 // Enable for block 17
-#define FLASH_FMP_BLOCK_16 0x00010000 // Enable for block 16
-#define FLASH_FMP_BLOCK_15 0x00008000 // Enable for block 15
-#define FLASH_FMP_BLOCK_14 0x00004000 // Enable for block 14
-#define FLASH_FMP_BLOCK_13 0x00002000 // Enable for block 13
-#define FLASH_FMP_BLOCK_12 0x00001000 // Enable for block 12
-#define FLASH_FMP_BLOCK_11 0x00000800 // Enable for block 11
-#define FLASH_FMP_BLOCK_10 0x00000400 // Enable for block 10
-#define FLASH_FMP_BLOCK_9 0x00000200 // Enable for block 9
-#define FLASH_FMP_BLOCK_8 0x00000100 // Enable for block 8
-#define FLASH_FMP_BLOCK_7 0x00000080 // Enable for block 7
-#define FLASH_FMP_BLOCK_6 0x00000040 // Enable for block 6
-#define FLASH_FMP_BLOCK_5 0x00000020 // Enable for block 5
-#define FLASH_FMP_BLOCK_4 0x00000010 // Enable for block 4
-#define FLASH_FMP_BLOCK_3 0x00000008 // Enable for block 3
-#define FLASH_FMP_BLOCK_2 0x00000004 // Enable for block 2
-#define FLASH_FMP_BLOCK_1 0x00000002 // Enable for block 1
-#define FLASH_FMP_BLOCK_0 0x00000001 // Enable for block 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the FLASH_USECRL register.
-//
-//*****************************************************************************
-#define FLASH_USECRL_M 0x000000FF // Microsecond Reload Value.
-#define FLASH_USECRL_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the erase size of the FLASH block that is
-// erased by an erase operation, and the protect size is the size of the FLASH
-// block that is protected by each protection register.
-//
-//*****************************************************************************
-#define FLASH_PROTECT_SIZE 0x00000800
-#define FLASH_ERASE_SIZE 0x00000400
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the FLASH_FMA register.
-//
-//*****************************************************************************
-#define FLASH_FMA_OFFSET_M 0x0003FFFF // Address Offset.
-#define FLASH_FMA_OFFSET_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the FLASH_FMD register.
-//
-//*****************************************************************************
-#define FLASH_FMD_DATA_M 0xFFFFFFFF // Data Value.
-#define FLASH_FMD_DATA_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the FLASH_USERDBG register.
-//
-//*****************************************************************************
-#define FLASH_USERDBG_NW 0x80000000 // User Debug Not Written.
-#define FLASH_USERDBG_DATA_M 0x7FFFFFFC // User Data.
-#define FLASH_USERDBG_DBG1 0x00000002 // Debug Control 1.
-#define FLASH_USERDBG_DBG0 0x00000001 // Debug Control 0.
-#define FLASH_USERDBG_DATA_S 2
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the FLASH_USERREG0 register.
-//
-//*****************************************************************************
-#define FLASH_USERREG0_NW 0x80000000 // Not Written.
-#define FLASH_USERREG0_DATA_M 0x7FFFFFFF // User Data.
-#define FLASH_USERREG0_DATA_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the FLASH_USERREG1 register.
-//
-//*****************************************************************************
-#define FLASH_USERREG1_NW 0x80000000 // Not Written.
-#define FLASH_USERREG1_DATA_M 0x7FFFFFFF // User Data.
-#define FLASH_USERREG1_DATA_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the FLASH_RMCTL register.
-//
-//*****************************************************************************
-#define FLASH_RMCTL_BA 0x00000001 // Boot Alias.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the FLASH_RMVER register.
-//
-//*****************************************************************************
-#define FLASH_RMVER_CONT_M 0xFF000000 // ROM Contents.
-#define FLASH_RMVER_CONT_LM 0x00000000 // Boot Loader & DriverLib
-#define FLASH_RMVER_SIZE_M 0x00FF0000 // ROM Size.
-#define FLASH_RMVER_SIZE_11K 0x00000000 // 11KB Size
-#define FLASH_RMVER_VER_M 0x0000FF00 // ROM Version.
-#define FLASH_RMVER_REV_M 0x000000FF // ROM Revision.
-#define FLASH_RMVER_VER_S 8
-#define FLASH_RMVER_REV_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the FLASH_USERREG2 register.
-//
-//*****************************************************************************
-#define FLASH_USERREG2_NW 0x80000000 // Not Written.
-#define FLASH_USERREG2_DATA_M 0x7FFFFFFF // User Data.
-#define FLASH_USERREG2_DATA_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the FLASH_USERREG3 register.
-//
-//*****************************************************************************
-#define FLASH_USERREG3_NW 0x80000000 // Not Written.
-#define FLASH_USERREG3_DATA_M 0x7FFFFFFF // User Data.
-#define FLASH_USERREG3_DATA_S 0
-
-//*****************************************************************************
-//
-// The following definitions are deprecated.
-//
-//*****************************************************************************
-#ifndef DEPRECATED
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the FLASH_FMC
-// register.
-//
-//*****************************************************************************
-#define FLASH_FMC_WRKEY_MASK 0xFFFF0000 // FLASH write key mask
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the FLASH_FCRIS
-// register.
-//
-//*****************************************************************************
-#define FLASH_FCRIS_PROGRAM 0x00000002 // Programming status
-#define FLASH_FCRIS_ACCESS 0x00000001 // Invalid access status
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the FLASH_FCIM
-// register.
-//
-//*****************************************************************************
-#define FLASH_FCIM_PROGRAM 0x00000002 // Programming mask
-#define FLASH_FCIM_ACCESS 0x00000001 // Invalid access mask
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the FLASH_FMIS
-// register.
-//
-//*****************************************************************************
-#define FLASH_FCMISC_PROGRAM 0x00000002 // Programming status
-#define FLASH_FCMISC_ACCESS 0x00000001 // Invalid access status
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the FLASH_USECRL
-// register.
-//
-//*****************************************************************************
-#define FLASH_USECRL_MASK 0x000000FF // Clock per uSec
-#define FLASH_USECRL_SHIFT 0
-
-#endif
-
-#endif // __HW_FLASH_H__
+//*****************************************************************************
+//
+// hw_flash.h - Macros used when accessing the flash controller.
+//
+// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4781 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_FLASH_H__
+#define __HW_FLASH_H__
+
+//*****************************************************************************
+//
+// The following are defines for the FLASH register offsets.
+//
+//*****************************************************************************
+#define FLASH_FMA 0x400FD000 // Memory address register
+#define FLASH_FMD 0x400FD004 // Memory data register
+#define FLASH_FMC 0x400FD008 // Memory control register
+#define FLASH_FCRIS 0x400FD00C // Raw interrupt status register
+#define FLASH_FCIM 0x400FD010 // Interrupt mask register
+#define FLASH_FCMISC 0x400FD014 // Interrupt status register
+#define FLASH_FMC2 0x400FD020 // Flash Memory Control 2
+#define FLASH_FWBVAL 0x400FD030 // Flash Write Buffer Valid
+#define FLASH_FWBN 0x400FD100 // Flash Write Buffer Register n
+#define FLASH_RMCTL 0x400FE0F0 // ROM Control
+#define FLASH_RMVER 0x400FE0F4 // ROM Version Register
+#define FLASH_FMPRE 0x400FE130 // FLASH read protect register
+#define FLASH_FMPPE 0x400FE134 // FLASH program protect register
+#define FLASH_USECRL 0x400FE140 // uSec reload register
+#define FLASH_USERDBG 0x400FE1D0 // User Debug
+#define FLASH_USERREG0 0x400FE1E0 // User Register 0
+#define FLASH_USERREG1 0x400FE1E4 // User Register 1
+#define FLASH_USERREG2 0x400FE1E8 // User Register 2
+#define FLASH_USERREG3 0x400FE1EC // User Register 3
+#define FLASH_FMPRE0 0x400FE200 // FLASH read protect register 0
+#define FLASH_FMPRE1 0x400FE204 // FLASH read protect register 1
+#define FLASH_FMPRE2 0x400FE208 // FLASH read protect register 2
+#define FLASH_FMPRE3 0x400FE20C // FLASH read protect register 3
+#define FLASH_FMPPE0 0x400FE400 // FLASH program protect register 0
+#define FLASH_FMPPE1 0x400FE404 // FLASH program protect register 1
+#define FLASH_FMPPE2 0x400FE408 // FLASH program protect register 2
+#define FLASH_FMPPE3 0x400FE40C // FLASH program protect register 3
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMC register.
+//
+//*****************************************************************************
+#define FLASH_FMC_WRKEY_M 0xFFFF0000 // FLASH write key mask
+#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key
+#define FLASH_FMC_COMT 0x00000008 // Commit user register
+#define FLASH_FMC_MERASE 0x00000004 // Mass erase FLASH
+#define FLASH_FMC_ERASE 0x00000002 // Erase FLASH page
+#define FLASH_FMC_WRITE 0x00000001 // Write FLASH word
+#define FLASH_FMC_WRKEY_S 16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMC2 register.
+//
+//*****************************************************************************
+#define FLASH_FMC2_WRKEY 0xA4420000 // FLASH write key
+#define FLASH_FMC2_WRBUF 0x00000001 // Buffered Flash Write.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FCRIS register.
+//
+//*****************************************************************************
+#define FLASH_FCRIS_PRIS 0x00000002 // Programming Raw Interrupt
+ // Status.
+#define FLASH_FCRIS_ARIS 0x00000001 // Access Raw Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FCIM register.
+//
+//*****************************************************************************
+#define FLASH_FCIM_PMASK 0x00000002 // Programming Interrupt Mask.
+#define FLASH_FCIM_AMASK 0x00000001 // Access Interrupt Mask.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMIS register.
+//
+//*****************************************************************************
+#define FLASH_FCMISC_PMISC 0x00000002 // Programming Masked Interrupt
+ // Status and Clear.
+#define FLASH_FCMISC_AMISC 0x00000001 // Access Masked Interrupt Status
+ // and Clear.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPRE and
+// FLASH_FMPPE registers.
+//
+//*****************************************************************************
+#define FLASH_FMP_BLOCK_31 0x80000000 // Enable for block 31
+#define FLASH_FMP_BLOCK_30 0x40000000 // Enable for block 30
+#define FLASH_FMP_BLOCK_29 0x20000000 // Enable for block 29
+#define FLASH_FMP_BLOCK_28 0x10000000 // Enable for block 28
+#define FLASH_FMP_BLOCK_27 0x08000000 // Enable for block 27
+#define FLASH_FMP_BLOCK_26 0x04000000 // Enable for block 26
+#define FLASH_FMP_BLOCK_25 0x02000000 // Enable for block 25
+#define FLASH_FMP_BLOCK_24 0x01000000 // Enable for block 24
+#define FLASH_FMP_BLOCK_23 0x00800000 // Enable for block 23
+#define FLASH_FMP_BLOCK_22 0x00400000 // Enable for block 22
+#define FLASH_FMP_BLOCK_21 0x00200000 // Enable for block 21
+#define FLASH_FMP_BLOCK_20 0x00100000 // Enable for block 20
+#define FLASH_FMP_BLOCK_19 0x00080000 // Enable for block 19
+#define FLASH_FMP_BLOCK_18 0x00040000 // Enable for block 18
+#define FLASH_FMP_BLOCK_17 0x00020000 // Enable for block 17
+#define FLASH_FMP_BLOCK_16 0x00010000 // Enable for block 16
+#define FLASH_FMP_BLOCK_15 0x00008000 // Enable for block 15
+#define FLASH_FMP_BLOCK_14 0x00004000 // Enable for block 14
+#define FLASH_FMP_BLOCK_13 0x00002000 // Enable for block 13
+#define FLASH_FMP_BLOCK_12 0x00001000 // Enable for block 12
+#define FLASH_FMP_BLOCK_11 0x00000800 // Enable for block 11
+#define FLASH_FMP_BLOCK_10 0x00000400 // Enable for block 10
+#define FLASH_FMP_BLOCK_9 0x00000200 // Enable for block 9
+#define FLASH_FMP_BLOCK_8 0x00000100 // Enable for block 8
+#define FLASH_FMP_BLOCK_7 0x00000080 // Enable for block 7
+#define FLASH_FMP_BLOCK_6 0x00000040 // Enable for block 6
+#define FLASH_FMP_BLOCK_5 0x00000020 // Enable for block 5
+#define FLASH_FMP_BLOCK_4 0x00000010 // Enable for block 4
+#define FLASH_FMP_BLOCK_3 0x00000008 // Enable for block 3
+#define FLASH_FMP_BLOCK_2 0x00000004 // Enable for block 2
+#define FLASH_FMP_BLOCK_1 0x00000002 // Enable for block 1
+#define FLASH_FMP_BLOCK_0 0x00000001 // Enable for block 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USECRL register.
+//
+//*****************************************************************************
+#define FLASH_USECRL_M 0x000000FF // Microsecond Reload Value.
+#define FLASH_USECRL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the erase size of the FLASH block that is
+// erased by an erase operation, and the protect size is the size of the FLASH
+// block that is protected by each protection register.
+//
+//*****************************************************************************
+#define FLASH_PROTECT_SIZE 0x00000800
+#define FLASH_ERASE_SIZE 0x00000400
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMA register.
+//
+//*****************************************************************************
+#define FLASH_FMA_OFFSET_M 0x0003FFFF // Address Offset.
+#define FLASH_FMA_OFFSET_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMD register.
+//
+//*****************************************************************************
+#define FLASH_FMD_DATA_M 0xFFFFFFFF // Data Value.
+#define FLASH_FMD_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERDBG register.
+//
+//*****************************************************************************
+#define FLASH_USERDBG_NW 0x80000000 // User Debug Not Written.
+#define FLASH_USERDBG_DATA_M 0x7FFFFFFC // User Data.
+#define FLASH_USERDBG_DBG1 0x00000002 // Debug Control 1.
+#define FLASH_USERDBG_DBG0 0x00000001 // Debug Control 0.
+#define FLASH_USERDBG_DATA_S 2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG0 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG0_NW 0x80000000 // Not Written.
+#define FLASH_USERREG0_DATA_M 0x7FFFFFFF // User Data.
+#define FLASH_USERREG0_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG1 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG1_NW 0x80000000 // Not Written.
+#define FLASH_USERREG1_DATA_M 0x7FFFFFFF // User Data.
+#define FLASH_USERREG1_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_RMCTL register.
+//
+//*****************************************************************************
+#define FLASH_RMCTL_BA 0x00000001 // Boot Alias.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_RMVER register.
+//
+//*****************************************************************************
+#define FLASH_RMVER_CONT_M 0xFF000000 // ROM Contents.
+#define FLASH_RMVER_CONT_LM 0x00000000 // Stellaris Boot Loader &
+ // DriverLib
+#define FLASH_RMVER_CONT_LM_AES 0x02000000 // Stellaris Boot Loader &
+ // DriverLib with AES
+#define FLASH_RMVER_CONT_LM_AES_SAFERTOS \
+ 0x03000000 // Stellaris Boot Loader &
+ // DriverLib with AES and SAFERTOS
+#define FLASH_RMVER_SIZE_M 0x00FF0000 // ROM Size.
+#define FLASH_RMVER_SIZE_11K 0x00000000 // 11KB Size
+#define FLASH_RMVER_SIZE_23_75K 0x00020000 // 23.75KB Size
+#define FLASH_RMVER_SIZE_28_25K 0x00030000 // 28.25KB Size
+#define FLASH_RMVER_VER_M 0x0000FF00 // ROM Version.
+#define FLASH_RMVER_REV_M 0x000000FF // ROM Revision.
+#define FLASH_RMVER_VER_S 8
+#define FLASH_RMVER_REV_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG2 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG2_NW 0x80000000 // Not Written.
+#define FLASH_USERREG2_DATA_M 0x7FFFFFFF // User Data.
+#define FLASH_USERREG2_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG3 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG3_NW 0x80000000 // Not Written.
+#define FLASH_USERREG3_DATA_M 0x7FFFFFFF // User Data.
+#define FLASH_USERREG3_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FWBVAL register.
+//
+//*****************************************************************************
+#define FLASH_FWBVAL_FWB_M 0xFFFFFFFF // Flash Write Buffer.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FWBN register.
+//
+//*****************************************************************************
+#define FLASH_FWBN_DATA_M 0xFFFFFFFF // Data.
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the FLASH_FMC
+// register.
+//
+//*****************************************************************************
+#define FLASH_FMC_WRKEY_MASK 0xFFFF0000 // FLASH write key mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the FLASH_FCRIS
+// register.
+//
+//*****************************************************************************
+#define FLASH_FCRIS_PROGRAM 0x00000002 // Programming status
+#define FLASH_FCRIS_ACCESS 0x00000001 // Invalid access status
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the FLASH_FCIM
+// register.
+//
+//*****************************************************************************
+#define FLASH_FCIM_PROGRAM 0x00000002 // Programming mask
+#define FLASH_FCIM_ACCESS 0x00000001 // Invalid access mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the FLASH_FMIS
+// register.
+//
+//*****************************************************************************
+#define FLASH_FCMISC_PROGRAM 0x00000002 // Programming status
+#define FLASH_FCMISC_ACCESS 0x00000001 // Invalid access status
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the FLASH_USECRL
+// register.
+//
+//*****************************************************************************
+#define FLASH_USECRL_MASK 0x000000FF // Clock per uSec
+#define FLASH_USECRL_SHIFT 0
+
+#endif
+
+#endif // __HW_FLASH_H__
Property changes on: branches/eagle_mmc/src/platform/lm3s/hw_flash.h
___________________________________________________________________
Name: svn:executable
+ *
Modified: branches/eagle_mmc/src/platform/lm3s/hw_gpio.h
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/hw_gpio.h 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lm3s/hw_gpio.h 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,135 +1,593 @@
-//*****************************************************************************
-//
-// hw_gpio.h - Defines and Macros for GPIO hardware.
-//
-// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
-// Software License Agreement
-//
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
-//
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws. All rights are reserved. You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program. Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
-//
-// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-//
-// This is part of revision 3740 of the Stellaris Firmware Development Package.
-//
-//*****************************************************************************
-
-#ifndef __HW_GPIO_H__
-#define __HW_GPIO_H__
-
-//*****************************************************************************
-//
-// The following are defines for the GPIO Register offsets.
-//
-//*****************************************************************************
-#define GPIO_O_DATA 0x00000000 // Data register.
-#define GPIO_O_DIR 0x00000400 // Data direction register.
-#define GPIO_O_IS 0x00000404 // Interrupt sense register.
-#define GPIO_O_IBE 0x00000408 // Interrupt both edges register.
-#define GPIO_O_IEV 0x0000040C // Interrupt event register.
-#define GPIO_O_IM 0x00000410 // Interrupt mask register.
-#define GPIO_O_RIS 0x00000414 // Raw interrupt status register.
-#define GPIO_O_MIS 0x00000418 // Masked interrupt status reg.
-#define GPIO_O_ICR 0x0000041C // Interrupt clear register.
-#define GPIO_O_AFSEL 0x00000420 // Mode control select register.
-#define GPIO_O_DR2R 0x00000500 // 2ma drive select register.
-#define GPIO_O_DR4R 0x00000504 // 4ma drive select register.
-#define GPIO_O_DR8R 0x00000508 // 8ma drive select register.
-#define GPIO_O_ODR 0x0000050C // Open drain select register.
-#define GPIO_O_PUR 0x00000510 // Pull up select register.
-#define GPIO_O_PDR 0x00000514 // Pull down select register.
-#define GPIO_O_SLR 0x00000518 // Slew rate control enable reg.
-#define GPIO_O_DEN 0x0000051C // Digital input enable register.
-#define GPIO_O_LOCK 0x00000520 // Lock register.
-#define GPIO_O_CR 0x00000524 // Commit register.
-#define GPIO_O_AMSEL 0x00000528 // GPIO Analog Mode Select
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPIO_LOCK register.
-//
-//*****************************************************************************
-#define GPIO_LOCK_M 0xFFFFFFFF // GPIO Lock.
-#define GPIO_LOCK_UNLOCKED 0x00000000 // GPIO_CR register is unlocked
-#define GPIO_LOCK_LOCKED 0x00000001 // GPIO_CR register is locked
-#define GPIO_LOCK_KEY 0x1ACCE551 // Unlocks the GPIO_CR register
-#define GPIO_LOCK_KEY_DD 0x4C4F434B // Unlocks the GPIO_CR register on
- // DustDevil-class devices and
- // later.
-
-//*****************************************************************************
-//
-// The following definitions are deprecated.
-//
-//*****************************************************************************
-#ifndef DEPRECATED
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the GPIO Register offsets.
-//
-//*****************************************************************************
-#define GPIO_O_PeriphID4 0x00000FD0
-#define GPIO_O_PeriphID5 0x00000FD4
-#define GPIO_O_PeriphID6 0x00000FD8
-#define GPIO_O_PeriphID7 0x00000FDC
-#define GPIO_O_PeriphID0 0x00000FE0
-#define GPIO_O_PeriphID1 0x00000FE4
-#define GPIO_O_PeriphID2 0x00000FE8
-#define GPIO_O_PeriphID3 0x00000FEC
-#define GPIO_O_PCellID0 0x00000FF0
-#define GPIO_O_PCellID1 0x00000FF4
-#define GPIO_O_PCellID2 0x00000FF8
-#define GPIO_O_PCellID3 0x00000FFC
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the GPIO Register reset values.
-//
-//*****************************************************************************
-#define GPIO_RV_DEN 0x000000FF // Digital input enable reg RV.
-#define GPIO_RV_PUR 0x000000FF // Pull up select reg RV.
-#define GPIO_RV_DR2R 0x000000FF // 2ma drive select reg RV.
-#define GPIO_RV_PCellID1 0x000000F0
-#define GPIO_RV_PCellID3 0x000000B1
-#define GPIO_RV_PeriphID0 0x00000061
-#define GPIO_RV_PeriphID1 0x00000010
-#define GPIO_RV_PCellID0 0x0000000D
-#define GPIO_RV_PCellID2 0x00000005
-#define GPIO_RV_PeriphID2 0x00000004
-#define GPIO_RV_LOCK 0x00000001 // Lock register RV.
-#define GPIO_RV_PeriphID7 0x00000000
-#define GPIO_RV_PDR 0x00000000 // Pull down select reg RV.
-#define GPIO_RV_IC 0x00000000 // Interrupt clear reg RV.
-#define GPIO_RV_SLR 0x00000000 // Slew rate control enable reg RV.
-#define GPIO_RV_ODR 0x00000000 // Open drain select reg RV.
-#define GPIO_RV_IBE 0x00000000 // Interrupt both edges reg RV.
-#define GPIO_RV_AFSEL 0x00000000 // Mode control select reg RV.
-#define GPIO_RV_IS 0x00000000 // Interrupt sense reg RV.
-#define GPIO_RV_IM 0x00000000 // Interrupt mask reg RV.
-#define GPIO_RV_PeriphID4 0x00000000
-#define GPIO_RV_PeriphID5 0x00000000
-#define GPIO_RV_DR8R 0x00000000 // 8ma drive select reg RV.
-#define GPIO_RV_RIS 0x00000000 // Raw interrupt status reg RV.
-#define GPIO_RV_DR4R 0x00000000 // 4ma drive select reg RV.
-#define GPIO_RV_IEV 0x00000000 // Intterupt event reg RV.
-#define GPIO_RV_DIR 0x00000000 // Data direction reg RV.
-#define GPIO_RV_PeriphID6 0x00000000
-#define GPIO_RV_PeriphID3 0x00000000
-#define GPIO_RV_DATA 0x00000000 // Data register reset value.
-#define GPIO_RV_MIS 0x00000000 // Masked interrupt status reg RV.
-
-#endif
-
-#endif // __HW_GPIO_H__
+//*****************************************************************************
+//
+// hw_gpio.h - Defines and Macros for GPIO hardware.
+//
+// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4781 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_GPIO_H__
+#define __HW_GPIO_H__
+
+//*****************************************************************************
+//
+// The following are defines for the GPIO Register offsets.
+//
+//*****************************************************************************
+#define GPIO_O_DATA 0x00000000 // Data register.
+#define GPIO_O_DIR 0x00000400 // Data direction register.
+#define GPIO_O_IS 0x00000404 // Interrupt sense register.
+#define GPIO_O_IBE 0x00000408 // Interrupt both edges register.
+#define GPIO_O_IEV 0x0000040C // Interrupt event register.
+#define GPIO_O_IM 0x00000410 // Interrupt mask register.
+#define GPIO_O_RIS 0x00000414 // Raw interrupt status register.
+#define GPIO_O_MIS 0x00000418 // Masked interrupt status reg.
+#define GPIO_O_ICR 0x0000041C // Interrupt clear register.
+#define GPIO_O_AFSEL 0x00000420 // Mode control select register.
+#define GPIO_O_DR2R 0x00000500 // 2ma drive select register.
+#define GPIO_O_DR4R 0x00000504 // 4ma drive select register.
+#define GPIO_O_DR8R 0x00000508 // 8ma drive select register.
+#define GPIO_O_ODR 0x0000050C // Open drain select register.
+#define GPIO_O_PUR 0x00000510 // Pull up select register.
+#define GPIO_O_PDR 0x00000514 // Pull down select register.
+#define GPIO_O_SLR 0x00000518 // Slew rate control enable reg.
+#define GPIO_O_DEN 0x0000051C // Digital input enable register.
+#define GPIO_O_LOCK 0x00000520 // Lock register.
+#define GPIO_O_CR 0x00000524 // Commit register.
+#define GPIO_O_AMSEL 0x00000528 // GPIO Analog Mode Select
+#define GPIO_O_PCTL 0x0000052C // GPIO Port Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_LOCK register.
+//
+//*****************************************************************************
+#define GPIO_LOCK_M 0xFFFFFFFF // GPIO Lock.
+#define GPIO_LOCK_UNLOCKED 0x00000000 // GPIO_CR register is unlocked
+#define GPIO_LOCK_LOCKED 0x00000001 // GPIO_CR register is locked
+#define GPIO_LOCK_KEY 0x1ACCE551 // Unlocks the GPIO_CR register
+#define GPIO_LOCK_KEY_DD 0x4C4F434B // Unlocks the GPIO_CR register on
+ // DustDevil-class devices and
+ // later.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_PCTL register for
+// port A.
+//
+//*****************************************************************************
+#define GPIO_PCTL_PA0_M 0x0000000F // PA0 mask
+#define GPIO_PCTL_PA0_U0RX 0x00000001 // U0RX on PA0
+#define GPIO_PCTL_PA0_I2C1SCL 0x00000008 // I2C1SCL on PA0
+#define GPIO_PCTL_PA0_U1RX 0x00000009 // U1RX on PA0
+#define GPIO_PCTL_PA1_M 0x000000F0 // PA1 mask
+#define GPIO_PCTL_PA1_U0TX 0x00000010 // U0TX on PA1
+#define GPIO_PCTL_PA1_I2C1SDA 0x00000080 // I2C1SDA on PA1
+#define GPIO_PCTL_PA1_U1TX 0x00000090 // U1TX on PA1
+#define GPIO_PCTL_PA2_M 0x00000F00 // PA2 mask
+#define GPIO_PCTL_PA2_SSI0CLK 0x00000100 // SSI0CLK on PA2
+#define GPIO_PCTL_PA2_PWM4 0x00000400 // PWM4 on PA2
+#define GPIO_PCTL_PA2_I2S0RXSD 0x00000900 // I2S0RXSD on PA2
+#define GPIO_PCTL_PA3_M 0x0000F000 // PA3 mask
+#define GPIO_PCTL_PA3_SSI0FSS 0x00001000 // SSI0FSS on PA3
+#define GPIO_PCTL_PA3_PWM5 0x00004000 // PWM5 on PA3
+#define GPIO_PCTL_PA3_I2S0RXMCLK \
+ 0x00009000 // I2S0RXMCLK on PA3
+#define GPIO_PCTL_PA4_M 0x000F0000 // PA4 mask
+#define GPIO_PCTL_PA4_SSI0RX 0x00010000 // SSI0RX on PA4
+#define GPIO_PCTL_PA4_PWM6 0x00040000 // PWM6 on PA4
+#define GPIO_PCTL_PA4_CAN0RX 0x00050000 // CAN0RX on PA4
+#define GPIO_PCTL_PA4_I2S0TXSCK 0x00090000 // I2S0TXSCK on PA4
+#define GPIO_PCTL_PA5_M 0x00F00000 // PA5 mask
+#define GPIO_PCTL_PA5_SSI0TX 0x00100000 // SSI0TX on PA5
+#define GPIO_PCTL_PA5_PWM7 0x00400000 // PWM7 on PA5
+#define GPIO_PCTL_PA5_CAN0TX 0x00500000 // CAN0TX on PA5
+#define GPIO_PCTL_PA5_I2S0TXWS 0x00900000 // I2S0TXWS on PA5
+#define GPIO_PCTL_PA6_M 0x0F000000 // PA6 mask
+#define GPIO_PCTL_PA6_I2C1SCL 0x01000000 // I2C1SCL on PA6
+#define GPIO_PCTL_PA6_CCP1 0x02000000 // CCP1 on PA6
+#define GPIO_PCTL_PA6_PWM0 0x04000000 // PWM0 on PA6
+#define GPIO_PCTL_PA6_PWM4 0x05000000 // PWM4 on PA6
+#define GPIO_PCTL_PA6_CAN0RX 0x06000000 // CAN0RX on PA6
+#define GPIO_PCTL_PA6_USB0EPEN 0x08000000 // USB0EPEN on PA6
+#define GPIO_PCTL_PA6_U1CTS 0x09000000 // U1CTS on PA6
+#define GPIO_PCTL_PA7_M 0xF0000000 // PA7 mask
+#define GPIO_PCTL_PA7_I2C1SDA 0x10000000 // I2C1SDA on PA7
+#define GPIO_PCTL_PA7_CCP4 0x20000000 // CCP4 on PA7
+#define GPIO_PCTL_PA7_PWM1 0x40000000 // PWM1 on PA7
+#define GPIO_PCTL_PA7_PWM5 0x50000000 // PWM5 on PA7
+#define GPIO_PCTL_PA7_CAN0TX 0x60000000 // CAN0TX on PA7
+#define GPIO_PCTL_PA7_CCP3 0x70000000 // CCP3 on PA7
+#define GPIO_PCTL_PA7_USB0PFLT 0x80000000 // USB0PFLT on PA7
+#define GPIO_PCTL_PA7_U1DCD 0x90000000 // U1DCD on PA7
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_PCTL register for
+// port B.
+//
+//*****************************************************************************
+#define GPIO_PCTL_PB0_M 0x0000000F // PB0 mask
+#define GPIO_PCTL_PB0_CCP0 0x00000001 // CCP0 on PB0
+#define GPIO_PCTL_PB0_PWM2 0x00000002 // PWM2 on PB0
+#define GPIO_PCTL_PB0_U1RX 0x00000005 // U1RX on PB0
+#define GPIO_PCTL_PB1_M 0x000000F0 // PB1 mask
+#define GPIO_PCTL_PB1_CCP2 0x00000010 // CCP2 on PB1
+#define GPIO_PCTL_PB1_PWM3 0x00000020 // PWM3 on PB1
+#define GPIO_PCTL_PB1_CCP1 0x00000040 // CCP1 on PB1
+#define GPIO_PCTL_PB1_U1TX 0x00000050 // U1TX on PB1
+#define GPIO_PCTL_PB2_M 0x00000F00 // PB2 mask
+#define GPIO_PCTL_PB2_I2C0SCL 0x00000100 // I2C0SCL on PB2
+#define GPIO_PCTL_PB2_IDX0 0x00000200 // IDX0 on PB2
+#define GPIO_PCTL_PB2_CCP3 0x00000400 // CCP3 on PB2
+#define GPIO_PCTL_PB2_CCP0 0x00000500 // CCP0 on PB2
+#define GPIO_PCTL_PB2_USB0EPEN 0x00000800 // USB0EPEN on PB2
+#define GPIO_PCTL_PB3_M 0x0000F000 // PB3 mask
+#define GPIO_PCTL_PB3_I2C0SDA 0x00001000 // I2C0SDA on PB3
+#define GPIO_PCTL_PB3_FAULT0 0x00002000 // FAULT0 on PB3
+#define GPIO_PCTL_PB3_FAULT3 0x00004000 // FAULT3 on PB3
+#define GPIO_PCTL_PB3_USB0PFLT 0x00008000 // USB0PFLT on PB3
+#define GPIO_PCTL_PB4_M 0x000F0000 // PB4 mask
+#define GPIO_PCTL_PB4_U2RX 0x00040000 // U2RX on PB4
+#define GPIO_PCTL_PB4_CAN0RX 0x00050000 // CAN0RX on PB4
+#define GPIO_PCTL_PB4_IDX0 0x00060000 // IDX0 on PB4
+#define GPIO_PCTL_PB4_U1RX 0x00070000 // U1RX on PB4
+#define GPIO_PCTL_PB4_EPI0S23 0x00080000 // EPI0S23 on PB4
+#define GPIO_PCTL_PB5_M 0x00F00000 // PB5 mask
+#define GPIO_PCTL_PB5_C0O 0x00100000 // C0O on PB5
+#define GPIO_PCTL_PB5_CCP5 0x00200000 // CCP5 on PB5
+#define GPIO_PCTL_PB5_CCP6 0x00300000 // CCP6 on PB5
+#define GPIO_PCTL_PB5_CCP0 0x00400000 // CCP0 on PB5
+#define GPIO_PCTL_PB5_CAN0TX 0x00500000 // CAN0TX on PB5
+#define GPIO_PCTL_PB5_CCP2 0x00600000 // CCP2 on PB5
+#define GPIO_PCTL_PB5_U1TX 0x00700000 // U1TX on PB5
+#define GPIO_PCTL_PB5_EPI0S22 0x00800000 // EPI0S22 on PB5
+#define GPIO_PCTL_PB6_M 0x0F000000 // PB6 mask
+#define GPIO_PCTL_PB6_CCP1 0x01000000 // CCP1 on PB6
+#define GPIO_PCTL_PB6_CCP7 0x02000000 // CCP7 on PB6
+#define GPIO_PCTL_PB6_C0O 0x03000000 // C0O on PB6
+#define GPIO_PCTL_PB6_FAULT1 0x04000000 // FAULT1 on PB6
+#define GPIO_PCTL_PB6_IDX0 0x05000000 // IDX0 on PB6
+#define GPIO_PCTL_PB6_CCP5 0x06000000 // CCP5 on PB6
+#define GPIO_PCTL_PB6_I2S0TXSCK 0x09000000 // I2S0TXSCK on PB6
+#define GPIO_PCTL_PB7_M 0xF0000000 // PB7 mask
+#define GPIO_PCTL_PB7_NMI 0x40000000 // NMI on PB7
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_PCTL register for
+// port C.
+//
+//*****************************************************************************
+#define GPIO_PCTL_PC0_M 0x0000000F // PC0 mask
+#define GPIO_PCTL_PC0_TCK 0x00000003 // TCK on PC0
+#define GPIO_PCTL_PC1_M 0x000000F0 // PC1 mask
+#define GPIO_PCTL_PC1_TMS 0x00000030 // TMS on PC1
+#define GPIO_PCTL_PC2_M 0x00000F00 // PC2 mask
+#define GPIO_PCTL_PC2_TDI 0x00000300 // TDI on PC2
+#define GPIO_PCTL_PC3_M 0x0000F000 // PC3 mask
+#define GPIO_PCTL_PC3_TDO 0x00003000 // TDO on PC3
+#define GPIO_PCTL_PC4_M 0x000F0000 // PC4 mask
+#define GPIO_PCTL_PC4_CCP5 0x00010000 // CCP5 on PC4
+#define GPIO_PCTL_PC4_PHA0 0x00020000 // PHA0 on PC4
+#define GPIO_PCTL_PC4_PWM6 0x00040000 // PWM6 on PC4
+#define GPIO_PCTL_PC4_CCP2 0x00050000 // CCP2 on PC4
+#define GPIO_PCTL_PC4_CCP4 0x00060000 // CCP4 on PC4
+#define GPIO_PCTL_PC4_EPI0S2 0x00080000 // EPI0S2 on PC4
+#define GPIO_PCTL_PC4_CCP1 0x00090000 // CCP1 on PC4
+#define GPIO_PCTL_PC5_M 0x00F00000 // PC5 mask
+#define GPIO_PCTL_PC5_CCP1 0x00100000 // CCP1 on PC5
+#define GPIO_PCTL_PC5_C1O 0x00200000 // C1O on PC5
+#define GPIO_PCTL_PC5_C0O 0x00300000 // C0O on PC5
+#define GPIO_PCTL_PC5_FAULT2 0x00400000 // FAULT2 on PC5
+#define GPIO_PCTL_PC5_CCP3 0x00500000 // CCP3 on PC5
+#define GPIO_PCTL_PC5_USB0EPEN 0x00600000 // USB0EPEN on PC5
+#define GPIO_PCTL_PC5_EPI0S3 0x00800000 // EPI0S3 on PC5
+#define GPIO_PCTL_PC6_M 0x0F000000 // PC6 mask
+#define GPIO_PCTL_PC6_CCP3 0x01000000 // CCP3 on PC6
+#define GPIO_PCTL_PC6_PHB0 0x02000000 // PHB0 on PC6
+#define GPIO_PCTL_PC6_C2O 0x03000000 // C2O on PC6
+#define GPIO_PCTL_PC6_PWM7 0x04000000 // PWM7 on PC6
+#define GPIO_PCTL_PC6_U1RX 0x05000000 // U1RX on PC6
+#define GPIO_PCTL_PC6_CCP0 0x06000000 // CCP0 on PC6
+#define GPIO_PCTL_PC6_USB0PFLT 0x07000000 // USB0PFLT on PC6
+#define GPIO_PCTL_PC6_EPI0S4 0x08000000 // EPI0S4 on PC6
+#define GPIO_PCTL_PC7_M 0xF0000000 // PC7 mask
+#define GPIO_PCTL_PC7_CCP4 0x10000000 // CCP4 on PC7
+#define GPIO_PCTL_PC7_PHB0 0x20000000 // PHB0 on PC7
+#define GPIO_PCTL_PC7_CCP0 0x40000000 // CCP0 on PC7
+#define GPIO_PCTL_PC7_U1TX 0x50000000 // U1TX on PC7
+#define GPIO_PCTL_PC7_USB0PFLT 0x60000000 // USB0PFLT on PC7
+#define GPIO_PCTL_PC7_C1O 0x70000000 // C1O on PC7
+#define GPIO_PCTL_PC7_EPI0S5 0x80000000 // EPI0S5 on PC7
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_PCTL register for
+// port D.
+//
+//*****************************************************************************
+#define GPIO_PCTL_PD0_M 0x0000000F // PD0 mask
+#define GPIO_PCTL_PD0_PWM0 0x00000001 // PWM0 on PD0
+#define GPIO_PCTL_PD0_CAN0RX 0x00000002 // CAN0RX on PD0
+#define GPIO_PCTL_PD0_IDX0 0x00000003 // IDX0 on PD0
+#define GPIO_PCTL_PD0_U2RX 0x00000004 // U2RX on PD0
+#define GPIO_PCTL_PD0_U1RX 0x00000005 // U1RX on PD0
+#define GPIO_PCTL_PD0_CCP6 0x00000006 // CCP6 on PD0
+#define GPIO_PCTL_PD0_I2S0RXSCK 0x00000008 // I2S0RXSCK on PD0
+#define GPIO_PCTL_PD0_U1CTS 0x00000009 // U1CTS on PD0
+#define GPIO_PCTL_PD1_M 0x000000F0 // PD1 mask
+#define GPIO_PCTL_PD1_PWM1 0x00000010 // PWM1 on PD1
+#define GPIO_PCTL_PD1_CAN0TX 0x00000020 // CAN0TX on PD1
+#define GPIO_PCTL_PD1_PHA0 0x00000030 // PHA0 on PD1
+#define GPIO_PCTL_PD1_U2TX 0x00000040 // U2TX on PD1
+#define GPIO_PCTL_PD1_U1TX 0x00000050 // U1TX on PD1
+#define GPIO_PCTL_PD1_CCP7 0x00000060 // CCP7 on PD1
+#define GPIO_PCTL_PD1_I2S0RXWS 0x00000080 // I2S0RXWS on PD1
+#define GPIO_PCTL_PD1_U1DCD 0x00000090 // U1DCD on PD1
+#define GPIO_PCTL_PD1_CCP2 0x000000A0 // CCP2 on PD1
+#define GPIO_PCTL_PD1_PHB1 0x000000B0 // PHB1 on PD1
+#define GPIO_PCTL_PD2_M 0x00000F00 // PD2 mask
+#define GPIO_PCTL_PD2_U1RX 0x00000100 // U1RX on PD2
+#define GPIO_PCTL_PD2_CCP6 0x00000200 // CCP6 on PD2
+#define GPIO_PCTL_PD2_PWM2 0x00000300 // PWM2 on PD2
+#define GPIO_PCTL_PD2_CCP5 0x00000400 // CCP5 on PD2
+#define GPIO_PCTL_PD2_EPI0S20 0x00000800 // EPI0S20 on PD2
+#define GPIO_PCTL_PD3_M 0x0000F000 // PD3 mask
+#define GPIO_PCTL_PD3_U1TX 0x00001000 // U1TX on PD3
+#define GPIO_PCTL_PD3_CCP7 0x00002000 // CCP7 on PD3
+#define GPIO_PCTL_PD3_PWM3 0x00003000 // PWM3 on PD3
+#define GPIO_PCTL_PD3_CCP0 0x00004000 // CCP0 on PD3
+#define GPIO_PCTL_PD3_EPI0S21 0x00008000 // EPI0S21 on PD3
+#define GPIO_PCTL_PD4_M 0x000F0000 // PD4 mask
+#define GPIO_PCTL_PD4_CCP0 0x00010000 // CCP0 on PD4
+#define GPIO_PCTL_PD4_CCP3 0x00020000 // CCP3 on PD4
+#define GPIO_PCTL_PD4_I2S0RXSD 0x00080000 // I2S0RXSD on PD4
+#define GPIO_PCTL_PD4_U1RI 0x00090000 // U1RI on PD4
+#define GPIO_PCTL_PD4_EPI0S19 0x000A0000 // EPI0S19 on PD4
+#define GPIO_PCTL_PD5_M 0x00F00000 // PD5 mask
+#define GPIO_PCTL_PD5_CCP2 0x00100000 // CCP2 on PD5
+#define GPIO_PCTL_PD5_CCP4 0x00200000 // CCP4 on PD5
+#define GPIO_PCTL_PD5_I2S0RXMCLK \
+ 0x00800000 // I2S0RXMCLK on PD5
+#define GPIO_PCTL_PD5_U2RX 0x00900000 // U2RX on PD5
+#define GPIO_PCTL_PD5_EPI0S28 0x00A00000 // EPI0S28 on PD5
+#define GPIO_PCTL_PD6_M 0x0F000000 // PD6 mask
+#define GPIO_PCTL_PD6_FAULT0 0x01000000 // FAULT0 on PD6
+#define GPIO_PCTL_PD6_I2S0TXSCK 0x08000000 // I2S0TXSCK on PD6
+#define GPIO_PCTL_PD6_U2TX 0x09000000 // U2TX on PD6
+#define GPIO_PCTL_PD6_EPI0S29 0x0A000000 // EPI0S29 on PD6
+#define GPIO_PCTL_PD7_M 0xF0000000 // PD7 mask
+#define GPIO_PCTL_PD7_IDX0 0x10000000 // IDX0 on PD7
+#define GPIO_PCTL_PD7_C0O 0x20000000 // C0O on PD7
+#define GPIO_PCTL_PD7_CCP1 0x30000000 // CCP1 on PD7
+#define GPIO_PCTL_PD7_I2S0TXWS 0x80000000 // I2S0TXWS on PD7
+#define GPIO_PCTL_PD7_U1DTR 0x90000000 // U1DTR on PD7
+#define GPIO_PCTL_PD7_EPI0S30 0xA0000000 // EPI0S30 on PD7
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_PCTL register for
+// port E.
+//
+//*****************************************************************************
+#define GPIO_PCTL_PE0_M 0x0000000F // PE0 mask
+#define GPIO_PCTL_PE0_PWM4 0x00000001 // PWM4 on PE0
+#define GPIO_PCTL_PE0_SSI1CLK 0x00000002 // SSI1CLK on PE0
+#define GPIO_PCTL_PE0_CCP3 0x00000003 // CCP3 on PE0
+#define GPIO_PCTL_PE0_EPI0S8 0x00000008 // EPI0S8 on PE0
+#define GPIO_PCTL_PE0_USB0PFLT 0x00000009 // USB0PFLT on PE0
+#define GPIO_PCTL_PE1_M 0x000000F0 // PE1 mask
+#define GPIO_PCTL_PE1_PWM5 0x00000010 // PWM5 on PE1
+#define GPIO_PCTL_PE1_SSI1FSS 0x00000020 // SSI1FSS on PE1
+#define GPIO_PCTL_PE1_FAULT0 0x00000030 // FAULT0 on PE1
+#define GPIO_PCTL_PE1_CCP2 0x00000040 // CCP2 on PE1
+#define GPIO_PCTL_PE1_CCP6 0x00000050 // CCP6 on PE1
+#define GPIO_PCTL_PE1_EPI0S9 0x00000080 // EPI0S9 on PE1
+#define GPIO_PCTL_PE2_M 0x00000F00 // PE2 mask
+#define GPIO_PCTL_PE2_CCP4 0x00000100 // CCP4 on PE2
+#define GPIO_PCTL_PE2_SSI1RX 0x00000200 // SSI1RX on PE2
+#define GPIO_PCTL_PE2_PHB1 0x00000300 // PHB1 on PE2
+#define GPIO_PCTL_PE2_PHA0 0x00000400 // PHA0 on PE2
+#define GPIO_PCTL_PE2_CCP2 0x00000500 // CCP2 on PE2
+#define GPIO_PCTL_PE2_EPI0S24 0x00000800 // EPI0S24 on PE2
+#define GPIO_PCTL_PE3_M 0x0000F000 // PE3 mask
+#define GPIO_PCTL_PE3_CCP1 0x00001000 // CCP1 on PE3
+#define GPIO_PCTL_PE3_SSI1TX 0x00002000 // SSI1TX on PE3
+#define GPIO_PCTL_PE3_PHA1 0x00003000 // PHA1 on PE3
+#define GPIO_PCTL_PE3_PHB0 0x00004000 // PHB0 on PE3
+#define GPIO_PCTL_PE3_CCP7 0x00005000 // CCP7 on PE3
+#define GPIO_PCTL_PE3_EPI0S25 0x00008000 // EPI0S25 on PE3
+#define GPIO_PCTL_PE4_M 0x000F0000 // PE4 mask
+#define GPIO_PCTL_PE4_CCP3 0x00010000 // CCP3 on PE4
+#define GPIO_PCTL_PE4_FAULT0 0x00040000 // FAULT0 on PE4
+#define GPIO_PCTL_PE4_U2TX 0x00050000 // U2TX on PE4
+#define GPIO_PCTL_PE4_CCP2 0x00060000 // CCP2 on PE4
+#define GPIO_PCTL_PE4_I2S0TXWS 0x00090000 // I2S0TXWS on PE4
+#define GPIO_PCTL_PE5_M 0x00F00000 // PE5 mask
+#define GPIO_PCTL_PE5_CCP5 0x00100000 // CCP5 on PE5
+#define GPIO_PCTL_PE5_I2S0TXSD 0x00900000 // I2S0TXSD on PE5
+#define GPIO_PCTL_PE6_M 0x0F000000 // PE6 mask
+#define GPIO_PCTL_PE6_PWM4 0x01000000 // PWM4 on PE6
+#define GPIO_PCTL_PE6_C1O 0x02000000 // C1O on PE6
+#define GPIO_PCTL_PE6_U1CTS 0x09000000 // U1CTS on PE6
+#define GPIO_PCTL_PE7_M 0xF0000000 // PE7 mask
+#define GPIO_PCTL_PE7_PWM5 0x10000000 // PWM5 on PE7
+#define GPIO_PCTL_PE7_C2O 0x20000000 // C2O on PE7
+#define GPIO_PCTL_PE7_U1DCD 0x90000000 // U1DCD on PE7
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_PCTL register for
+// port F.
+//
+//*****************************************************************************
+#define GPIO_PCTL_PF0_M 0x0000000F // PF0 mask
+#define GPIO_PCTL_PF0_CAN1RX 0x00000001 // CAN1RX on PF0
+#define GPIO_PCTL_PF0_PHB0 0x00000002 // PHB0 on PF0
+#define GPIO_PCTL_PF0_PWM0 0x00000003 // PWM0 on PF0
+#define GPIO_PCTL_PF0_I2S0TXSD 0x00000008 // I2S0TXSD on PF0
+#define GPIO_PCTL_PF0_U1DSR 0x00000009 // U1DSR on PF0
+#define GPIO_PCTL_PF1_M 0x000000F0 // PF1 mask
+#define GPIO_PCTL_PF1_CAN1TX 0x00000010 // CAN1TX on PF1
+#define GPIO_PCTL_PF1_IDX1 0x00000020 // IDX1 on PF1
+#define GPIO_PCTL_PF1_PWM1 0x00000030 // PWM1 on PF1
+#define GPIO_PCTL_PF1_I2S0TXMCLK \
+ 0x00000080 // I2S0TXMCLK on PF1
+#define GPIO_PCTL_PF1_U1RTS 0x00000090 // U1RTS on PF1
+#define GPIO_PCTL_PF1_CCP3 0x000000A0 // CCP3 on PF1
+#define GPIO_PCTL_PF2_M 0x00000F00 // PF2 mask
+#define GPIO_PCTL_PF2_LED1 0x00000100 // LED1 on PF2
+#define GPIO_PCTL_PF2_PWM4 0x00000200 // PWM4 on PF2
+#define GPIO_PCTL_PF2_PWM2 0x00000400 // PWM2 on PF2
+#define GPIO_PCTL_PF2_SSI1CLK 0x00000900 // SSI1CLK on PF2
+#define GPIO_PCTL_PF3_M 0x0000F000 // PF3 mask
+#define GPIO_PCTL_PF3_LED0 0x00001000 // LED0 on PF3
+#define GPIO_PCTL_PF3_PWM5 0x00002000 // PWM5 on PF3
+#define GPIO_PCTL_PF3_PWM3 0x00004000 // PWM3 on PF3
+#define GPIO_PCTL_PF3_SSI1FSS 0x00009000 // SSI1FSS on PF3
+#define GPIO_PCTL_PF4_M 0x000F0000 // PF4 mask
+#define GPIO_PCTL_PF4_CCP0 0x00010000 // CCP0 on PF4
+#define GPIO_PCTL_PF4_C0O 0x00020000 // C0O on PF4
+#define GPIO_PCTL_PF4_FAULT0 0x00040000 // FAULT0 on PF4
+#define GPIO_PCTL_PF4_EPI0S12 0x00080000 // EPI0S12 on PF4
+#define GPIO_PCTL_PF4_SSI1RX 0x00090000 // SSI1RX on PF4
+#define GPIO_PCTL_PF5_M 0x00F00000 // PF5 mask
+#define GPIO_PCTL_PF5_CCP2 0x00100000 // CCP2 on PF5
+#define GPIO_PCTL_PF5_C1O 0x00200000 // C1O on PF5
+#define GPIO_PCTL_PF5_EPI0S15 0x00800000 // EPI0S15 on PF5
+#define GPIO_PCTL_PF5_SSI1TX 0x00900000 // SSI1TX on PF5
+#define GPIO_PCTL_PF6_M 0x0F000000 // PF6 mask
+#define GPIO_PCTL_PF6_CCP1 0x01000000 // CCP1 on PF6
+#define GPIO_PCTL_PF6_C2O 0x02000000 // C2O on PF6
+#define GPIO_PCTL_PF6_PHA0 0x04000000 // PHA0 on PF6
+#define GPIO_PCTL_PF6_I2S0TXMCLK \
+ 0x09000000 // I2S0TXMCLK on PF6
+#define GPIO_PCTL_PF6_U1RTS 0x0A000000 // U1RTS on PF6
+#define GPIO_PCTL_PF7_M 0xF0000000 // PF7 mask
+#define GPIO_PCTL_PF7_CCP4 0x10000000 // CCP4 on PF7
+#define GPIO_PCTL_PF7_PHB0 0x40000000 // PHB0 on PF7
+#define GPIO_PCTL_PF7_EPI0S12 0x80000000 // EPI0S12 on PF7
+#define GPIO_PCTL_PF7_FAULT1 0x90000000 // FAULT1 on PF7
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_PCTL register for
+// port G.
+//
+//*****************************************************************************
+#define GPIO_PCTL_PG0_M 0x0000000F // PG0 mask
+#define GPIO_PCTL_PG0_U2RX 0x00000001 // U2RX on PG0
+#define GPIO_PCTL_PG0_PWM0 0x00000002 // PWM0 on PG0
+#define GPIO_PCTL_PG0_I2C1SCL 0x00000003 // I2C1SCL on PG0
+#define GPIO_PCTL_PG0_PWM4 0x00000004 // PWM4 on PG0
+#define GPIO_PCTL_PG0_USB0EPEN 0x00000007 // USB0EPEN on PG0
+#define GPIO_PCTL_PG0_EPI0S13 0x00000008 // EPI0S13 on PG0
+#define GPIO_PCTL_PG1_M 0x000000F0 // PG1 mask
+#define GPIO_PCTL_PG1_U2TX 0x00000010 // U2TX on PG1
+#define GPIO_PCTL_PG1_PWM1 0x00000020 // PWM1 on PG1
+#define GPIO_PCTL_PG1_I2C1SDA 0x00000030 // I2C1SDA on PG1
+#define GPIO_PCTL_PG1_PWM5 0x00000040 // PWM5 on PG1
+#define GPIO_PCTL_PG1_EPI0S14 0x00000080 // EPI0S14 on PG1
+#define GPIO_PCTL_PG2_M 0x00000F00 // PG2 mask
+#define GPIO_PCTL_PG2_PWM0 0x00000100 // PWM0 on PG2
+#define GPIO_PCTL_PG2_FAULT0 0x00000400 // FAULT0 on PG2
+#define GPIO_PCTL_PG2_IDX1 0x00000800 // IDX1 on PG2
+#define GPIO_PCTL_PG2_I2S0RXSD 0x00000900 // I2S0RXSD on PG2
+#define GPIO_PCTL_PG3_M 0x0000F000 // PG3 mask
+#define GPIO_PCTL_PG3_PWM1 0x00001000 // PWM1 on PG3
+#define GPIO_PCTL_PG3_FAULT2 0x00004000 // FAULT2 on PG3
+#define GPIO_PCTL_PG3_FAULT0 0x00008000 // FAULT0 on PG3
+#define GPIO_PCTL_PG3_I2S0RXMCLK \
+ 0x00009000 // I2S0RXMCLK on PG3
+#define GPIO_PCTL_PG4_M 0x000F0000 // PG4 mask
+#define GPIO_PCTL_PG4_CCP3 0x00010000 // CCP3 on PG4
+#define GPIO_PCTL_PG4_FAULT1 0x00040000 // FAULT1 on PG4
+#define GPIO_PCTL_PG4_EPI0S15 0x00080000 // EPI0S15 on PG4
+#define GPIO_PCTL_PG4_PWM6 0x00090000 // PWM6 on PG4
+#define GPIO_PCTL_PG4_U1RI 0x000A0000 // U1RI on PG4
+#define GPIO_PCTL_PG5_M 0x00F00000 // PG5 mask
+#define GPIO_PCTL_PG5_CCP5 0x00100000 // CCP5 on PG5
+#define GPIO_PCTL_PG5_IDX0 0x00400000 // IDX0 on PG5
+#define GPIO_PCTL_PG5_FAULT1 0x00500000 // FAULT1 on PG5
+#define GPIO_PCTL_PG5_PWM7 0x00800000 // PWM7 on PG5
+#define GPIO_PCTL_PG5_I2S0RXSCK 0x00900000 // I2S0RXSCK on PG5
+#define GPIO_PCTL_PG5_U1DTR 0x00A00000 // U1DTR on PG5
+#define GPIO_PCTL_PG6_M 0x0F000000 // PG6 mask
+#define GPIO_PCTL_PG6_PHA1 0x01000000 // PHA1 on PG6
+#define GPIO_PCTL_PG6_PWM6 0x04000000 // PWM6 on PG6
+#define GPIO_PCTL_PG6_FAULT1 0x08000000 // FAULT1 on PG6
+#define GPIO_PCTL_PG6_I2S0RXWS 0x09000000 // I2S0RXWS on PG6
+#define GPIO_PCTL_PG6_U1RI 0x0A000000 // U1RI on PG6
+#define GPIO_PCTL_PG7_M 0xF0000000 // PG7 mask
+#define GPIO_PCTL_PG7_PHB1 0x10000000 // PHB1 on PG7
+#define GPIO_PCTL_PG7_PWM7 0x40000000 // PWM7 on PG7
+#define GPIO_PCTL_PG7_CCP5 0x80000000 // CCP5 on PG7
+#define GPIO_PCTL_PG7_EPI0S31 0x90000000 // EPI0S31 on PG7
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_PCTL register for
+// port H.
+//
+//*****************************************************************************
+#define GPIO_PCTL_PH0_M 0x0000000F // PH0 mask
+#define GPIO_PCTL_PH0_CCP6 0x00000001 // CCP6 on PH0
+#define GPIO_PCTL_PH0_PWM2 0x00000002 // PWM2 on PH0
+#define GPIO_PCTL_PH0_EPI0S6 0x00000008 // EPI0S6 on PH0
+#define GPIO_PCTL_PH0_PWM4 0x00000009 // PWM4 on PH0
+#define GPIO_PCTL_PH1_M 0x000000F0 // PH1 mask
+#define GPIO_PCTL_PH1_CCP7 0x00000010 // CCP7 on PH1
+#define GPIO_PCTL_PH1_PWM3 0x00000020 // PWM3 on PH1
+#define GPIO_PCTL_PH1_EPI0S7 0x00000080 // EPI0S7 on PH1
+#define GPIO_PCTL_PH1_PWM5 0x00000090 // PWM5 on PH1
+#define GPIO_PCTL_PH2_M 0x00000F00 // PH2 mask
+#define GPIO_PCTL_PH2_IDX1 0x00000100 // IDX1 on PH2
+#define GPIO_PCTL_PH2_C1O 0x00000200 // C1O on PH2
+#define GPIO_PCTL_PH2_FAULT3 0x00000400 // FAULT3 on PH2
+#define GPIO_PCTL_PH2_EPI0S1 0x00000800 // EPI0S1 on PH2
+#define GPIO_PCTL_PH3_M 0x0000F000 // PH3 mask
+#define GPIO_PCTL_PH3_PHB0 0x00001000 // PHB0 on PH3
+#define GPIO_PCTL_PH3_FAULT0 0x00002000 // FAULT0 on PH3
+#define GPIO_PCTL_PH3_USB0EPEN 0x00004000 // USB0EPEN on PH3
+#define GPIO_PCTL_PH3_EPI0S0 0x00008000 // EPI0S0 on PH3
+#define GPIO_PCTL_PH4_M 0x000F0000 // PH4 mask
+#define GPIO_PCTL_PH4_USB0PFLT 0x00040000 // USB0PFLT on PH4
+#define GPIO_PCTL_PH4_EPI0S10 0x00080000 // EPI0S10 on PH4
+#define GPIO_PCTL_PH4_SSI1CLK 0x000B0000 // SSI1CLK on PH4
+#define GPIO_PCTL_PH5_M 0x00F00000 // PH5 mask
+#define GPIO_PCTL_PH5_EPI0S11 0x00800000 // EPI0S11 on PH5
+#define GPIO_PCTL_PH5_FAULT2 0x00A00000 // FAULT2 on PH5
+#define GPIO_PCTL_PH5_SSI1FSS 0x00B00000 // SSI1FSS on PH5
+#define GPIO_PCTL_PH6_M 0x0F000000 // PH6 mask
+#define GPIO_PCTL_PH6_EPI0S26 0x08000000 // EPI0S26 on PH6
+#define GPIO_PCTL_PH6_PWM4 0x0A000000 // PWM4 on PH6
+#define GPIO_PCTL_PH6_SSI1RX 0x0B000000 // SSI1RX on PH6
+#define GPIO_PCTL_PH7_M 0xF0000000 // PH7 mask
+#define GPIO_PCTL_PH7_EPI0S27 0x80000000 // EPI0S27 on PH7
+#define GPIO_PCTL_PH7_PWM5 0xA0000000 // PWM5 on PH7
+#define GPIO_PCTL_PH7_SSI1TX 0xB0000000 // SSI1TX on PH7
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_PCTL register for
+// port J.
+//
+//*****************************************************************************
+#define GPIO_PCTL_PJ0_M 0x0000000F // PJ0 mask
+#define GPIO_PCTL_PJ0_EPI0S16 0x00000008 // EPI0S16 on PJ0
+#define GPIO_PCTL_PJ0_PWM0 0x0000000A // PWM0 on PJ0
+#define GPIO_PCTL_PJ0_I2C1SCL 0x0000000B // I2C1SCL on PJ0
+#define GPIO_PCTL_PJ1_M 0x000000F0 // PJ1 mask
+#define GPIO_PCTL_PJ1_EPI0S17 0x00000080 // EPI0S17 on PJ1
+#define GPIO_PCTL_PJ1_USB0PFLT 0x00000090 // USB0PFLT on PJ1
+#define GPIO_PCTL_PJ1_PWM1 0x000000A0 // PWM1 on PJ1
+#define GPIO_PCTL_PJ1_I2C1SDA 0x000000B0 // I2C1SDA on PJ1
+#define GPIO_PCTL_PJ2_M 0x00000F00 // PJ2 mask
+#define GPIO_PCTL_PJ2_EPI0S18 0x00000800 // EPI0S18 on PJ2
+#define GPIO_PCTL_PJ2_CCP0 0x00000900 // CCP0 on PJ2
+#define GPIO_PCTL_PJ2_FAULT0 0x00000A00 // FAULT0 on PJ2
+#define GPIO_PCTL_PJ3_M 0x0000F000 // PJ3 mask
+#define GPIO_PCTL_PJ3_EPI0S19 0x00008000 // EPI0S19 on PJ3
+#define GPIO_PCTL_PJ3_U1CTS 0x00009000 // U1CTS on PJ3
+#define GPIO_PCTL_PJ3_CCP6 0x0000A000 // CCP6 on PJ3
+#define GPIO_PCTL_PJ4_M 0x000F0000 // PJ4 mask
+#define GPIO_PCTL_PJ4_EPI0S28 0x00080000 // EPI0S28 on PJ4
+#define GPIO_PCTL_PJ4_U1DCD 0x00090000 // U1DCD on PJ4
+#define GPIO_PCTL_PJ4_CCP4 0x000A0000 // CCP4 on PJ4
+#define GPIO_PCTL_PJ5_M 0x00F00000 // PJ5 mask
+#define GPIO_PCTL_PJ5_EPI0S29 0x00800000 // EPI0S29 on PJ5
+#define GPIO_PCTL_PJ5_U1DSR 0x00900000 // U1DSR on PJ5
+#define GPIO_PCTL_PJ5_CCP2 0x00A00000 // CCP2 on PJ5
+#define GPIO_PCTL_PJ6_M 0x0F000000 // PJ6 mask
+#define GPIO_PCTL_PJ6_EPI0S30 0x08000000 // EPI0S30 on PJ6
+#define GPIO_PCTL_PJ6_U1RTS 0x09000000 // U1RTS on PJ6
+#define GPIO_PCTL_PJ6_CCP1 0x0A000000 // CCP1 on PJ6
+#define GPIO_PCTL_PJ7_M 0xF0000000 // PJ7 mask
+#define GPIO_PCTL_PJ7_U1DTR 0x90000000 // U1DTR on PJ7
+#define GPIO_PCTL_PJ7_CCP0 0xA0000000 // CCP0 on PJ7
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the GPIO Register offsets.
+//
+//*****************************************************************************
+#define GPIO_O_PeriphID4 0x00000FD0
+#define GPIO_O_PeriphID5 0x00000FD4
+#define GPIO_O_PeriphID6 0x00000FD8
+#define GPIO_O_PeriphID7 0x00000FDC
+#define GPIO_O_PeriphID0 0x00000FE0
+#define GPIO_O_PeriphID1 0x00000FE4
+#define GPIO_O_PeriphID2 0x00000FE8
+#define GPIO_O_PeriphID3 0x00000FEC
+#define GPIO_O_PCellID0 0x00000FF0
+#define GPIO_O_PCellID1 0x00000FF4
+#define GPIO_O_PCellID2 0x00000FF8
+#define GPIO_O_PCellID3 0x00000FFC
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the GPIO Register reset values.
+//
+//*****************************************************************************
+#define GPIO_RV_DEN 0x000000FF // Digital input enable reg RV.
+#define GPIO_RV_PUR 0x000000FF // Pull up select reg RV.
+#define GPIO_RV_DR2R 0x000000FF // 2ma drive select reg RV.
+#define GPIO_RV_PCellID1 0x000000F0
+#define GPIO_RV_PCellID3 0x000000B1
+#define GPIO_RV_PeriphID0 0x00000061
+#define GPIO_RV_PeriphID1 0x00000010
+#define GPIO_RV_PCellID0 0x0000000D
+#define GPIO_RV_PCellID2 0x00000005
+#define GPIO_RV_PeriphID2 0x00000004
+#define GPIO_RV_LOCK 0x00000001 // Lock register RV.
+#define GPIO_RV_PeriphID7 0x00000000
+#define GPIO_RV_PDR 0x00000000 // Pull down select reg RV.
+#define GPIO_RV_IC 0x00000000 // Interrupt clear reg RV.
+#define GPIO_RV_SLR 0x00000000 // Slew rate control enable reg RV.
+#define GPIO_RV_ODR 0x00000000 // Open drain select reg RV.
+#define GPIO_RV_IBE 0x00000000 // Interrupt both edges reg RV.
+#define GPIO_RV_AFSEL 0x00000000 // Mode control select reg RV.
+#define GPIO_RV_IS 0x00000000 // Interrupt sense reg RV.
+#define GPIO_RV_IM 0x00000000 // Interrupt mask reg RV.
+#define GPIO_RV_PeriphID4 0x00000000
+#define GPIO_RV_PeriphID5 0x00000000
+#define GPIO_RV_DR8R 0x00000000 // 8ma drive select reg RV.
+#define GPIO_RV_RIS 0x00000000 // Raw interrupt status reg RV.
+#define GPIO_RV_DR4R 0x00000000 // 4ma drive select reg RV.
+#define GPIO_RV_IEV 0x00000000 // Intterupt event reg RV.
+#define GPIO_RV_DIR 0x00000000 // Data direction reg RV.
+#define GPIO_RV_PeriphID6 0x00000000
+#define GPIO_RV_PeriphID3 0x00000000
+#define GPIO_RV_DATA 0x00000000 // Data register reset value.
+#define GPIO_RV_MIS 0x00000000 // Masked interrupt status reg RV.
+
+#endif
+
+#endif // __HW_GPIO_H__
Property changes on: branches/eagle_mmc/src/platform/lm3s/hw_gpio.h
___________________________________________________________________
Name: svn:executable
+ *
Added: branches/eagle_mmc/src/platform/lm3s/hw_hibernate.h
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/hw_hibernate.h 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lm3s/hw_hibernate.h 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,245 @@
+//*****************************************************************************
+//
+// hw_hibernate.h - Defines and Macros for the Hibernation module.
+//
+// Copyright (c) 2007-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4781 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_HIBERNATE_H__
+#define __HW_HIBERNATE_H__
+
+//*****************************************************************************
+//
+// The following are defines for the Hibernation module register addresses.
+//
+//*****************************************************************************
+#define HIB_RTCC 0x400FC000 // Hibernate RTC counter
+#define HIB_RTCM0 0x400FC004 // Hibernate RTC match 0
+#define HIB_RTCM1 0x400FC008 // Hibernate RTC match 1
+#define HIB_RTCLD 0x400FC00C // Hibernate RTC load
+#define HIB_CTL 0x400FC010 // Hibernate RTC control
+#define HIB_IM 0x400FC014 // Hibernate interrupt mask
+#define HIB_RIS 0x400FC018 // Hibernate raw interrupt status
+#define HIB_MIS 0x400FC01C // Hibernate masked interrupt stat
+#define HIB_IC 0x400FC020 // Hibernate interrupt clear
+#define HIB_RTCT 0x400FC024 // Hibernate RTC trim
+#define HIB_DATA 0x400FC030 // Hibernate data area
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the Hibernate RTC counter
+// register.
+//
+//*****************************************************************************
+#define HIB_RTCC_M 0xFFFFFFFF // RTC Counter.
+#define HIB_RTCC_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the Hibernate RTC match 0
+// register.
+//
+//*****************************************************************************
+#define HIB_RTCM0_M 0xFFFFFFFF // RTC Match 0.
+#define HIB_RTCM0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the Hibernate RTC match 1
+// register.
+//
+//*****************************************************************************
+#define HIB_RTCM1_M 0xFFFFFFFF // RTC Match 1.
+#define HIB_RTCM1_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the Hibernate RTC load
+// register.
+//
+//*****************************************************************************
+#define HIB_RTCLD_M 0xFFFFFFFF // RTC Load.
+#define HIB_RTCLD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the Hibernate control
+// register
+//
+//*****************************************************************************
+#define HIB_CTL_WRC 0x80000000 // Write Complete/Capable.
+#define HIB_CTL_VDD3ON 0x00000100 // VDD Powered.
+#define HIB_CTL_VABORT 0x00000080 // low bat abort
+#define HIB_CTL_CLK32EN 0x00000040 // enable clock/oscillator
+#define HIB_CTL_LOWBATEN 0x00000020 // enable low battery detect
+#define HIB_CTL_PINWEN 0x00000010 // enable wake on WAKE pin
+#define HIB_CTL_RTCWEN 0x00000008 // enable wake on RTC match
+#define HIB_CTL_CLKSEL 0x00000004 // clock input selection
+#define HIB_CTL_HIBREQ 0x00000002 // request hibernation
+#define HIB_CTL_RTCEN 0x00000001 // RTC enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the Hibernate interrupt mask
+// reg.
+//
+//*****************************************************************************
+#define HIB_IM_EXTW 0x00000008 // wake from external pin interrupt
+#define HIB_IM_LOWBAT 0x00000004 // low battery interrupt
+#define HIB_IM_RTCALT1 0x00000002 // RTC match 1 interrupt
+#define HIB_IM_RTCALT0 0x00000001 // RTC match 0 interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the Hibernate raw interrupt
+// status.
+//
+//*****************************************************************************
+#define HIB_RIS_EXTW 0x00000008 // wake from external pin interrupt
+#define HIB_RIS_LOWBAT 0x00000004 // low battery interrupt
+#define HIB_RIS_RTCALT1 0x00000002 // RTC match 1 interrupt
+#define HIB_RIS_RTCALT0 0x00000001 // RTC Alert0 Raw Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the Hibernate masked int
+// status.
+//
+//*****************************************************************************
+#define HIB_MIS_EXTW 0x00000008 // wake from external pin interrupt
+#define HIB_MIS_LOWBAT 0x00000004 // low battery interrupt
+#define HIB_MIS_RTCALT1 0x00000002 // RTC match 1 interrupt
+#define HIB_MIS_RTCALT0 0x00000001 // RTC Alert0 Masked Interrupt
+ // Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the Hibernate interrupt
+// clear reg.
+//
+//*****************************************************************************
+#define HIB_IC_EXTW 0x00000008 // wake from external pin interrupt
+#define HIB_IC_LOWBAT 0x00000004 // low battery interrupt
+#define HIB_IC_RTCALT1 0x00000002 // RTC match 1 interrupt
+#define HIB_IC_RTCALT0 0x00000001 // RTC match 0 interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the Hibernate RTC trim
+// register.
+//
+//*****************************************************************************
+#define HIB_RTCT_TRIM_M 0x0000FFFF // RTC Trim Value.
+#define HIB_RTCT_TRIM_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the Hibernate data register.
+//
+//*****************************************************************************
+#define HIB_DATA_RTD_M 0xFFFFFFFF // Hibernation Module NV
+ // Registers[63:0].
+#define HIB_DATA_RTD_S 0
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the Hibernation module register
+// addresses.
+//
+//*****************************************************************************
+#define HIB_DATA_END 0x400FC130 // end of data area, exclusive
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the Hibernate RTC
+// counter register.
+//
+//*****************************************************************************
+#define HIB_RTCC_MASK 0xFFFFFFFF // RTC counter mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the Hibernate RTC
+// match 0 register.
+//
+//*****************************************************************************
+#define HIB_RTCM0_MASK 0xFFFFFFFF // RTC match 0 mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the Hibernate RTC
+// match 1 register.
+//
+//*****************************************************************************
+#define HIB_RTCM1_MASK 0xFFFFFFFF // RTC match 1 mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the Hibernate RTC
+// load register.
+//
+//*****************************************************************************
+#define HIB_RTCLD_MASK 0xFFFFFFFF // RTC load mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the Hibernate raw
+// interrupt status.
+//
+//*****************************************************************************
+#define HIB_RID_RTCALT0 0x00000001 // RTC match 0 interrupt
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the Hibernate
+// masked int status.
+//
+//*****************************************************************************
+#define HIB_MID_RTCALT0 0x00000001 // RTC match 0 interrupt
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the Hibernate RTC
+// trim register.
+//
+//*****************************************************************************
+#define HIB_RTCT_MASK 0x0000FFFF // RTC trim mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the Hibernate
+// data register.
+//
+//*****************************************************************************
+#define HIB_DATA_MASK 0xFFFFFFFF // NV memory data mask
+
+#endif
+
+#endif // __HW_HIBERNATE_H__
Property changes on: branches/eagle_mmc/src/platform/lm3s/hw_hibernate.h
___________________________________________________________________
Name: svn:executable
+ *
Added: branches/eagle_mmc/src/platform/lm3s/hw_i2c.h
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/hw_i2c.h 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lm3s/hw_i2c.h 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,412 @@
+//*****************************************************************************
+//
+// hw_i2c.h - Macros used when accessing the I2C master and slave hardware.
+//
+// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4781 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_I2C_H__
+#define __HW_I2C_H__
+
+//*****************************************************************************
+//
+// The following are defines for the offsets between the I2C master and slave
+// registers.
+//
+//*****************************************************************************
+#define I2C_O_MSA 0x00000000 // I2C Master Slave Address
+#define I2C_O_SOAR 0x00000000 // I2C Slave Own Address
+#define I2C_O_SCSR 0x00000004 // I2C Slave Control/Status
+#define I2C_O_MCS 0x00000004 // I2C Master Control/Status
+#define I2C_O_SDR 0x00000008 // I2C Slave Data
+#define I2C_O_MDR 0x00000008 // I2C Master Data
+#define I2C_O_MTPR 0x0000000C // I2C Master Timer Period
+#define I2C_O_SIMR 0x0000000C // I2C Slave Interrupt Mask
+#define I2C_O_SRIS 0x00000010 // I2C Slave Raw Interrupt Status
+#define I2C_O_MIMR 0x00000010 // I2C Master Interrupt Mask
+#define I2C_O_MRIS 0x00000014 // I2C Master Raw Interrupt Status
+#define I2C_O_SMIS 0x00000014 // I2C Slave Masked Interrupt
+ // Status
+#define I2C_O_SICR 0x00000018 // I2C Slave Interrupt Clear
+#define I2C_O_MMIS 0x00000018 // I2C Master Masked Interrupt
+ // Status
+#define I2C_O_MICR 0x0000001C // I2C Master Interrupt Clear
+#define I2C_O_MCR 0x00000020 // I2C Master Configuration
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MSA register.
+//
+//*****************************************************************************
+#define I2C_MSA_SA_M 0x000000FE // I2C Slave Address.
+#define I2C_MSA_RS 0x00000001 // Receive not Send
+#define I2C_MSA_SA_S 1
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SOAR register.
+//
+//*****************************************************************************
+#define I2C_SOAR_OAR_M 0x0000007F // I2C Slave Own Address.
+#define I2C_SOAR_OAR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SCSR register.
+//
+//*****************************************************************************
+#define I2C_SCSR_FBR 0x00000004 // First Byte Received.
+#define I2C_SCSR_TREQ 0x00000002 // Transmit Request.
+#define I2C_SCSR_DA 0x00000001 // Device Active.
+#define I2C_SCSR_RREQ 0x00000001 // Receive Request.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MCS register.
+//
+//*****************************************************************************
+#define I2C_MCS_BUSBSY 0x00000040 // Bus Busy.
+#define I2C_MCS_IDLE 0x00000020 // I2C Idle.
+#define I2C_MCS_ARBLST 0x00000010 // Arbitration Lost.
+#define I2C_MCS_ACK 0x00000008 // Data Acknowledge Enable.
+#define I2C_MCS_DATACK 0x00000008 // Acknowledge Data.
+#define I2C_MCS_ADRACK 0x00000004 // Acknowledge Address.
+#define I2C_MCS_STOP 0x00000004 // Generate STOP.
+#define I2C_MCS_START 0x00000002 // Generate START.
+#define I2C_MCS_ERROR 0x00000002 // Error.
+#define I2C_MCS_RUN 0x00000001 // I2C Master Enable.
+#define I2C_MCS_BUSY 0x00000001 // I2C Busy.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SDR register.
+//
+//*****************************************************************************
+#define I2C_SDR_DATA_M 0x000000FF // Data for Transfer.
+#define I2C_SDR_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MDR register.
+//
+//*****************************************************************************
+#define I2C_MDR_DATA_M 0x000000FF // Data Transferred.
+#define I2C_MDR_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MTPR register.
+//
+//*****************************************************************************
+#define I2C_MTPR_TPR_M 0x000000FF // SCL Clock Period.
+#define I2C_MTPR_TPR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SIMR register.
+//
+//*****************************************************************************
+#define I2C_SIMR_STOPIM 0x00000004 // Stop Condition Interrupt Mask.
+#define I2C_SIMR_STARTIM 0x00000002 // Start Condition Interrupt Mask.
+#define I2C_SIMR_DATAIM 0x00000001 // Data Interrupt Mask.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SRIS register.
+//
+//*****************************************************************************
+#define I2C_SRIS_STOPRIS 0x00000004 // Stop Condition Raw Interrupt
+ // Status.
+#define I2C_SRIS_STARTRIS 0x00000002 // Start Condition Raw Interrupt
+ // Status.
+#define I2C_SRIS_DATARIS 0x00000001 // Data Raw Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MIMR register.
+//
+//*****************************************************************************
+#define I2C_MIMR_IM 0x00000001 // Interrupt Mask.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MRIS register.
+//
+//*****************************************************************************
+#define I2C_MRIS_RIS 0x00000001 // Raw Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SMIS register.
+//
+//*****************************************************************************
+#define I2C_SMIS_STOPMIS 0x00000004 // Stop Condition Masked Interrupt
+ // Status.
+#define I2C_SMIS_STARTMIS 0x00000002 // Start Condition Masked Interrupt
+ // Status.
+#define I2C_SMIS_DATAMIS 0x00000001 // Data Masked Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SICR register.
+//
+//*****************************************************************************
+#define I2C_SICR_STOPIC 0x00000004 // Stop Condition Interrupt Clear.
+#define I2C_SICR_STARTIC 0x00000002 // Start Condition Interrupt Clear.
+#define I2C_SICR_DATAIC 0x00000001 // Data Clear Interrupt.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MMIS register.
+//
+//*****************************************************************************
+#define I2C_MMIS_MIS 0x00000001 // Masked Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MICR register.
+//
+//*****************************************************************************
+#define I2C_MICR_IC 0x00000001 // Interrupt Clear.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MCR register.
+//
+//*****************************************************************************
+#define I2C_MCR_SFE 0x00000020 // I2C Slave Function Enable.
+#define I2C_MCR_MFE 0x00000010 // I2C Master Function Enable.
+#define I2C_MCR_LPBK 0x00000001 // I2C Loopback.
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the offsets between the I2C master
+// and slave registers.
+//
+//*****************************************************************************
+#define I2C_O_SLAVE 0x00000800 // Offset from master to slave
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the I2C master register offsets.
+//
+//*****************************************************************************
+#define I2C_MASTER_O_SA 0x00000000 // Slave address register
+#define I2C_MASTER_O_CS 0x00000004 // Control and Status register
+#define I2C_MASTER_O_DR 0x00000008 // Data register
+#define I2C_MASTER_O_TPR 0x0000000C // Timer period register
+#define I2C_MASTER_O_IMR 0x00000010 // Interrupt mask register
+#define I2C_MASTER_O_RIS 0x00000014 // Raw interrupt status register
+#define I2C_MASTER_O_MIS 0x00000018 // Masked interrupt status reg
+#define I2C_MASTER_O_MICR 0x0000001C // Interrupt clear register
+#define I2C_MASTER_O_CR 0x00000020 // Configuration register
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the I2C slave register offsets.
+//
+//*****************************************************************************
+#define I2C_SLAVE_O_SICR 0x00000018 // Interrupt clear register
+#define I2C_SLAVE_O_MIS 0x00000014 // Masked interrupt status reg
+#define I2C_SLAVE_O_RIS 0x00000010 // Raw interrupt status register
+#define I2C_SLAVE_O_IM 0x0000000C // Interrupt mask register
+#define I2C_SLAVE_O_DR 0x00000008 // Data register
+#define I2C_SLAVE_O_CSR 0x00000004 // Control/Status register
+#define I2C_SLAVE_O_OAR 0x00000000 // Own address register
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C master
+// slave address register.
+//
+//*****************************************************************************
+#define I2C_MASTER_SA_SA_MASK 0x000000FE // Slave address
+#define I2C_MASTER_SA_RS 0x00000001 // Receive/send
+#define I2C_MASTER_SA_SA_SHIFT 1
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C Master
+// Control and Status register.
+//
+//*****************************************************************************
+#define I2C_MASTER_CS_BUS_BUSY 0x00000040 // Bus busy
+#define I2C_MASTER_CS_IDLE 0x00000020 // Idle
+#define I2C_MASTER_CS_ERR_MASK 0x0000001C
+#define I2C_MASTER_CS_BUSY 0x00000001 // Controller is TX/RX data
+#define I2C_MASTER_CS_ERROR 0x00000002 // Error occurred
+#define I2C_MASTER_CS_ADDR_ACK 0x00000004 // Address byte not acknowledged
+#define I2C_MASTER_CS_DATA_ACK 0x00000008 // Data byte not acknowledged
+#define I2C_MASTER_CS_ARB_LOST 0x00000010 // Lost arbitration
+#define I2C_MASTER_CS_ACK 0x00000008 // Acknowlegde
+#define I2C_MASTER_CS_STOP 0x00000004 // Stop
+#define I2C_MASTER_CS_START 0x00000002 // Start
+#define I2C_MASTER_CS_RUN 0x00000001 // Run
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the values used in determining the
+// contents of the I2C Master Timer Period register.
+//
+//*****************************************************************************
+#define I2C_SCL_FAST 400000 // SCL fast frequency
+#define I2C_SCL_STANDARD 100000 // SCL standard frequency
+#define I2C_MASTER_TPR_SCL_LP 0x00000006 // SCL low period
+#define I2C_MASTER_TPR_SCL_HP 0x00000004 // SCL high period
+#define I2C_MASTER_TPR_SCL (I2C_MASTER_TPR_SCL_HP + I2C_MASTER_TPR_SCL_LP)
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C Master
+// Interrupt Mask register.
+//
+//*****************************************************************************
+#define I2C_MASTER_IMR_IM 0x00000001 // Master interrupt mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C Master
+// Raw Interrupt Status register.
+//
+//*****************************************************************************
+#define I2C_MASTER_RIS_RIS 0x00000001 // Master raw interrupt status
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C Master
+// Masked Interrupt Status register.
+//
+//*****************************************************************************
+#define I2C_MASTER_MIS_MIS 0x00000001 // Master masked interrupt status
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C Master
+// Interrupt Clear register.
+//
+//*****************************************************************************
+#define I2C_MASTER_MICR_IC 0x00000001 // Master interrupt clear
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C Master
+// Configuration register.
+//
+//*****************************************************************************
+#define I2C_MASTER_CR_SFE 0x00000020 // Slave function enable
+#define I2C_MASTER_CR_MFE 0x00000010 // Master function enable
+#define I2C_MASTER_CR_LPBK 0x00000001 // Loopback enable
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C Slave Own
+// Address register.
+//
+//*****************************************************************************
+#define I2C_SLAVE_SOAR_OAR_MASK 0x0000007F // Slave address
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C Slave
+// Control/Status register.
+//
+//*****************************************************************************
+#define I2C_SLAVE_CSR_FBR 0x00000004 // First byte received from master
+#define I2C_SLAVE_CSR_TREQ 0x00000002 // Transmit request received
+#define I2C_SLAVE_CSR_DA 0x00000001 // Enable the device
+#define I2C_SLAVE_CSR_RREQ 0x00000001 // Receive data from I2C master
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C Slave
+// Interrupt Mask register.
+//
+//*****************************************************************************
+#define I2C_SLAVE_IMR_IM 0x00000001 // Slave interrupt mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C Slave Raw
+// Interrupt Status register.
+//
+//*****************************************************************************
+#define I2C_SLAVE_RIS_RIS 0x00000001 // Slave raw interrupt status
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C Slave
+// Masked Interrupt Status register.
+//
+//*****************************************************************************
+#define I2C_SLAVE_MIS_MIS 0x00000001 // Slave masked interrupt status
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C Slave
+// Interrupt Clear register.
+//
+//*****************************************************************************
+#define I2C_SLAVE_SICR_IC 0x00000001 // Slave interrupt clear
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C_O_SIMR
+// register.
+//
+//*****************************************************************************
+#define I2C_SIMR_IM 0x00000001 // Interrupt Mask.
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C_O_SRIS
+// register.
+//
+//*****************************************************************************
+#define I2C_SRIS_RIS 0x00000001 // Raw Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C_O_SMIS
+// register.
+//
+//*****************************************************************************
+#define I2C_SMIS_MIS 0x00000001 // Masked Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C_O_SICR
+// register.
+//
+//*****************************************************************************
+#define I2C_SICR_IC 0x00000001 // Clear Interrupt.
+
+#endif
+
+#endif // __HW_I2C_H__
Property changes on: branches/eagle_mmc/src/platform/lm3s/hw_i2c.h
___________________________________________________________________
Name: svn:executable
+ *
Added: branches/eagle_mmc/src/platform/lm3s/hw_i2s.h
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/hw_i2s.h 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lm3s/hw_i2s.h 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,233 @@
+//*****************************************************************************
+//
+// hw_i2s.h - Macros for use in accessing the I2S registers.
+//
+// Copyright (c) 2008-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4781 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_I2S_H__
+#define __HW_I2S_H__
+
+//*****************************************************************************
+//
+// The following are defines for the Inter-Integrated Circuit Sound (I2S)
+// Interface
+//
+//*****************************************************************************
+#define I2S_O_TXFIFO 0x00000000 // I2S Transmit FIFO Data
+#define I2S_O_TXFIFOCFG 0x00000004 // I2S Transmit FIFO Configuration
+#define I2S_O_TXCFG 0x00000008 // I2S Transmit Module
+ // Configuration
+#define I2S_O_TXLIMIT 0x0000000C // I2S Transmit FIFO Limit
+#define I2S_O_TXISM 0x00000010 // I2S Transmit Interrupt Status
+ // and Mask
+#define I2S_O_TXLEV 0x00000018 // I2S Transmit FIFO Level
+#define I2S_O_RXFIFO 0x00000800 // I2S Receive FIFO Data
+#define I2S_O_RXFIFOCFG 0x00000804 // I2S Receive FIFO Configuration
+#define I2S_O_RXCFG 0x00000808 // I2S Receive Module Configuration
+#define I2S_O_RXLIMIT 0x0000080C // I2S Receive FIFO Limit
+#define I2S_O_RXISM 0x00000810 // I2S Receive Interrupt Status and
+ // Mask
+#define I2S_O_RXLEV 0x00000818 // I2S Receive FIFO Level
+#define I2S_O_CFG 0x00000C00 // I2S Module Configuration
+#define I2S_O_IM 0x00000C10 // I2S Interrupt Mask
+#define I2S_O_RIS 0x00000C14 // I2S Raw Interrupt Status
+#define I2S_O_MIS 0x00000C18 // I2S Masked Interrupt Status
+#define I2S_O_IC 0x00000C1C // I2S Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_TXFIFO register.
+//
+//*****************************************************************************
+#define I2S_TXFIFO_M 0xFFFFFFFF // TX Data.
+#define I2S_TXFIFO_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_TXFIFOCFG
+// register.
+//
+//*****************************************************************************
+#define I2S_TXFIFOCFG_CSS 0x00000002 // Compact Stereo Sample Size.
+#define I2S_TXFIFOCFG_LRS 0x00000001 // Left-Right Sample Indicator.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_TXCFG register.
+//
+//*****************************************************************************
+#define I2S_TXCFG_JST 0x20000000 // Justification of Output Data.
+#define I2S_TXCFG_DLY 0x10000000 // Data Delay.
+#define I2S_TXCFG_SCP 0x08000000 // SCLK Polarity.
+#define I2S_TXCFG_LRP 0x04000000 // Left/Right Clock Polarity.
+#define I2S_TXCFG_WM_M 0x03000000 // Write Mode.
+#define I2S_TXCFG_WM_DUAL 0x00000000 // Stereo mode
+#define I2S_TXCFG_WM_COMPACT 0x01000000 // Compact Stereo mode
+#define I2S_TXCFG_WM_MONO 0x02000000 // Mono mode
+#define I2S_TXCFG_FMT 0x00800000 // FIFO Empty.
+#define I2S_TXCFG_MSL 0x00400000 // SCLK Master/Slave.
+#define I2S_TXCFG_SSZ_M 0x0000FC00 // Sample Size.
+#define I2S_TXCFG_SDSZ_M 0x000003F0 // System Data Size.
+#define I2S_TXCFG_SSZ_S 10
+#define I2S_TXCFG_SDSZ_S 4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_TXLIMIT register.
+//
+//*****************************************************************************
+#define I2S_TXLIMIT_LIMIT_M 0x0000001F // FIFO Limit.
+#define I2S_TXLIMIT_LIMIT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_TXISM register.
+//
+//*****************************************************************************
+#define I2S_TXISM_FFI 0x00010000 // Transmit FIFO Service Request
+ // Interrupt.
+#define I2S_TXISM_FFM 0x00000001 // FIFO Interrupt Mask.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_TXLEV register.
+//
+//*****************************************************************************
+#define I2S_TXLEV_LEVEL_M 0x0000001F // Number of Audio Samples.
+#define I2S_TXLEV_LEVEL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_RXFIFO register.
+//
+//*****************************************************************************
+#define I2S_RXFIFO_M 0xFFFFFFFF // RX Data.
+#define I2S_RXFIFO_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_RXFIFOCFG
+// register.
+//
+//*****************************************************************************
+#define I2S_RXFIFOCFG_FMM 0x00000004 // FIFO Mono Mode.
+#define I2S_RXFIFOCFG_CSS 0x00000002 // Compact Stereo Sample Size.
+#define I2S_RXFIFOCFG_LRS 0x00000001 // Left-Right Sample Indicator.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_RXCFG register.
+//
+//*****************************************************************************
+#define I2S_RXCFG_JST 0x20000000 // Justification of Input Data.
+#define I2S_RXCFG_DLY 0x10000000 // Data Delay.
+#define I2S_RXCFG_SCP 0x08000000 // SCLK Polarity.
+#define I2S_RXCFG_LRP 0x04000000 // Left/Right Clock Polarity.
+#define I2S_RXCFG_RM 0x01000000 // Read Mode.
+#define I2S_RXCFG_MSL 0x00400000 // SCLK Master/Slave.
+#define I2S_RXCFG_SSZ_M 0x0000FC00 // Sample Size.
+#define I2S_RXCFG_SDSZ_M 0x000003F0 // System Data Size.
+#define I2S_RXCFG_SSZ_S 10
+#define I2S_RXCFG_SDSZ_S 4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_RXLIMIT register.
+//
+//*****************************************************************************
+#define I2S_RXLIMIT_LIMIT_M 0x0000001F // FIFO Limit.
+#define I2S_RXLIMIT_LIMIT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_RXISM register.
+//
+//*****************************************************************************
+#define I2S_RXISM_FFI 0x00010000 // Receive FIFO Service Request
+ // Interrupt.
+#define I2S_RXISM_FFM 0x00000001 // FIFO Interrupt Mask.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_RXLEV register.
+//
+//*****************************************************************************
+#define I2S_RXLEV_LEVEL_M 0x0000001F // Number of Audio Samples.
+#define I2S_RXLEV_LEVEL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_CFG register.
+//
+//*****************************************************************************
+#define I2S_CFG_RXSLV 0x00000020 // When clear, this bit configures
+ // the receiver to use the
+ // externally driven I2S0RXMCLK
+ // signal.
+#define I2S_CFG_TXSLV 0x00000010 // When clear, this bit configures
+ // the transmitter to use the
+ // externally driven I2S0TXMCLK
+ // signal.
+#define I2S_CFG_RXEN 0x00000002 // Serial Receive Engine Enable.
+#define I2S_CFG_TXEN 0x00000001 // Serial Transmit Engine Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_IM register.
+//
+//*****************************************************************************
+#define I2S_IM_RXRE 0x00000020 // Receive FIFO Read Error.
+#define I2S_IM_RXFSR 0x00000010 // Receive FIFO Service Request.
+#define I2S_IM_TXWE 0x00000002 // Transmit FIFO Write Error.
+#define I2S_IM_TXFSR 0x00000001 // Transmit FIFO Service Request.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_RIS register.
+//
+//*****************************************************************************
+#define I2S_RIS_RXRE 0x00000020 // Receive FIFO Read Error.
+#define I2S_RIS_RXFSR 0x00000010 // Receive FIFO Service Request.
+#define I2S_RIS_TXWE 0x00000002 // Transmit FIFO Write Error.
+#define I2S_RIS_TXFSR 0x00000001 // Transmit FIFO Service Request.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_MIS register.
+//
+//*****************************************************************************
+#define I2S_MIS_RXRE 0x00000020 // Receive FIFO Read Error.
+#define I2S_MIS_RXFSR 0x00000010 // Receive FIFO Service Request.
+#define I2S_MIS_TXWE 0x00000002 // Transmit FIFO Write Error.
+#define I2S_MIS_TXFSR 0x00000001 // Transmit FIFO Service Request.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_IC register.
+//
+//*****************************************************************************
+#define I2S_IC_RXRE 0x00000020 // Receive FIFO Read Error.
+#define I2S_IC_TXWE 0x00000002 // Transmit FIFO Write Error.
+
+#endif // __HW_I2S_H__
Property changes on: branches/eagle_mmc/src/platform/lm3s/hw_i2s.h
___________________________________________________________________
Name: svn:executable
+ *
Modified: branches/eagle_mmc/src/platform/lm3s/hw_ints.h
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/hw_ints.h 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lm3s/hw_ints.h 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,133 +1,140 @@
-//*****************************************************************************
-//
-// hw_ints.h - Macros that define the interrupt assignment on Stellaris.
-//
-// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
-// Software License Agreement
-//
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
-//
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws. All rights are reserved. You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program. Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
-//
-// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-//
-// This is part of revision 3740 of the Stellaris Firmware Development Package.
-//
-//*****************************************************************************
-
-#ifndef __HW_INTS_H__
-#define __HW_INTS_H__
-
-//*****************************************************************************
-//
-// The following are defines for the fault assignments.
-//
-//*****************************************************************************
-#define FAULT_NMI 2 // NMI fault
-#define FAULT_HARD 3 // Hard fault
-#define FAULT_MPU 4 // MPU fault
-#define FAULT_BUS 5 // Bus fault
-#define FAULT_USAGE 6 // Usage fault
-#define FAULT_SVCALL 11 // SVCall
-#define FAULT_DEBUG 12 // Debug monitor
-#define FAULT_PENDSV 14 // PendSV
-#define FAULT_SYSTICK 15 // System Tick
-
-//*****************************************************************************
-//
-// The following are defines for the interrupt assignments.
-//
-//*****************************************************************************
-#define INT_GPIOA 16 // GPIO Port A
-#define INT_GPIOB 17 // GPIO Port B
-#define INT_GPIOC 18 // GPIO Port C
-#define INT_GPIOD 19 // GPIO Port D
-#define INT_GPIOE 20 // GPIO Port E
-#define INT_UART0 21 // UART0 Rx and Tx
-#define INT_UART1 22 // UART1 Rx and Tx
-#define INT_SSI0 23 // SSI0 Rx and Tx
-#define INT_I2C0 24 // I2C0 Master and Slave
-#define INT_PWM_FAULT 25 // PWM Fault
-#define INT_PWM0 26 // PWM Generator 0
-#define INT_PWM1 27 // PWM Generator 1
-#define INT_PWM2 28 // PWM Generator 2
-#define INT_QEI0 29 // Quadrature Encoder 0
-#define INT_ADC0 30 // ADC Sequence 0
-#define INT_ADC1 31 // ADC Sequence 1
-#define INT_ADC2 32 // ADC Sequence 2
-#define INT_ADC3 33 // ADC Sequence 3
-#define INT_WATCHDOG 34 // Watchdog timer
-#define INT_TIMER0A 35 // Timer 0 subtimer A
-#define INT_TIMER0B 36 // Timer 0 subtimer B
-#define INT_TIMER1A 37 // Timer 1 subtimer A
-#define INT_TIMER1B 38 // Timer 1 subtimer B
-#define INT_TIMER2A 39 // Timer 2 subtimer A
-#define INT_TIMER2B 40 // Timer 2 subtimer B
-#define INT_COMP0 41 // Analog Comparator 0
-#define INT_COMP1 42 // Analog Comparator 1
-#define INT_COMP2 43 // Analog Comparator 2
-#define INT_SYSCTL 44 // System Control (PLL, OSC, BO)
-#define INT_FLASH 45 // FLASH Control
-#define INT_GPIOF 46 // GPIO Port F
-#define INT_GPIOG 47 // GPIO Port G
-#define INT_GPIOH 48 // GPIO Port H
-#define INT_UART2 49 // UART2 Rx and Tx
-#define INT_SSI1 50 // SSI1 Rx and Tx
-#define INT_TIMER3A 51 // Timer 3 subtimer A
-#define INT_TIMER3B 52 // Timer 3 subtimer B
-#define INT_I2C1 53 // I2C1 Master and Slave
-#define INT_QEI1 54 // Quadrature Encoder 1
-#define INT_CAN0 55 // CAN0
-#define INT_CAN1 56 // CAN1
-#define INT_CAN2 57 // CAN2
-#define INT_ETH 58 // Ethernet
-#define INT_HIBERNATE 59 // Hibernation module
-#define INT_USB0 60 // USB 0 Controller
-#define INT_PWM3 61 // PWM Generator 3
-#define INT_UDMA 62 // uDMA controller
-#define INT_UDMAERR 63 // uDMA Error
-
-//*****************************************************************************
-//
-// The following are defines for the total number of interrupts.
-//
-//*****************************************************************************
-#define NUM_INTERRUPTS 64
-
-//*****************************************************************************
-//
-// The following are defines for the total number of priority levels.
-//
-//*****************************************************************************
-#define NUM_PRIORITY 8
-#define NUM_PRIORITY_BITS 3
-
-//*****************************************************************************
-//
-// The following definitions are deprecated.
-//
-//*****************************************************************************
-#ifndef DEPRECATED
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the interrupt assignments.
-//
-//*****************************************************************************
-#define INT_SSI 23 // SSI Rx and Tx
-#define INT_I2C 24 // I2C Master and Slave
-#define INT_QEI 29 // Quadrature Encoder
-
-#endif
-
-#endif // __HW_INTS_H__
+//*****************************************************************************
+//
+// hw_ints.h - Macros that define the interrupt assignment on Stellaris.
+//
+// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4781 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_INTS_H__
+#define __HW_INTS_H__
+
+//*****************************************************************************
+//
+// The following are defines for the fault assignments.
+//
+//*****************************************************************************
+#define FAULT_NMI 2 // NMI fault
+#define FAULT_HARD 3 // Hard fault
+#define FAULT_MPU 4 // MPU fault
+#define FAULT_BUS 5 // Bus fault
+#define FAULT_USAGE 6 // Usage fault
+#define FAULT_SVCALL 11 // SVCall
+#define FAULT_DEBUG 12 // Debug monitor
+#define FAULT_PENDSV 14 // PendSV
+#define FAULT_SYSTICK 15 // System Tick
+
+//*****************************************************************************
+//
+// The following are defines for the interrupt assignments.
+//
+//*****************************************************************************
+#define INT_GPIOA 16 // GPIO Port A
+#define INT_GPIOB 17 // GPIO Port B
+#define INT_GPIOC 18 // GPIO Port C
+#define INT_GPIOD 19 // GPIO Port D
+#define INT_GPIOE 20 // GPIO Port E
+#define INT_UART0 21 // UART0 Rx and Tx
+#define INT_UART1 22 // UART1 Rx and Tx
+#define INT_SSI0 23 // SSI0 Rx and Tx
+#define INT_I2C0 24 // I2C0 Master and Slave
+#define INT_PWM_FAULT 25 // PWM Fault
+#define INT_PWM0 26 // PWM Generator 0
+#define INT_PWM1 27 // PWM Generator 1
+#define INT_PWM2 28 // PWM Generator 2
+#define INT_QEI0 29 // Quadrature Encoder 0
+#define INT_ADC0 30 // ADC Sequence 0
+#define INT_ADC1 31 // ADC Sequence 1
+#define INT_ADC2 32 // ADC Sequence 2
+#define INT_ADC3 33 // ADC Sequence 3
+#define INT_WATCHDOG 34 // Watchdog timer
+#define INT_TIMER0A 35 // Timer 0 subtimer A
+#define INT_TIMER0B 36 // Timer 0 subtimer B
+#define INT_TIMER1A 37 // Timer 1 subtimer A
+#define INT_TIMER1B 38 // Timer 1 subtimer B
+#define INT_TIMER2A 39 // Timer 2 subtimer A
+#define INT_TIMER2B 40 // Timer 2 subtimer B
+#define INT_COMP0 41 // Analog Comparator 0
+#define INT_COMP1 42 // Analog Comparator 1
+#define INT_COMP2 43 // Analog Comparator 2
+#define INT_SYSCTL 44 // System Control (PLL, OSC, BO)
+#define INT_FLASH 45 // FLASH Control
+#define INT_GPIOF 46 // GPIO Port F
+#define INT_GPIOG 47 // GPIO Port G
+#define INT_GPIOH 48 // GPIO Port H
+#define INT_UART2 49 // UART2 Rx and Tx
+#define INT_SSI1 50 // SSI1 Rx and Tx
+#define INT_TIMER3A 51 // Timer 3 subtimer A
+#define INT_TIMER3B 52 // Timer 3 subtimer B
+#define INT_I2C1 53 // I2C1 Master and Slave
+#define INT_QEI1 54 // Quadrature Encoder 1
+#define INT_CAN0 55 // CAN0
+#define INT_CAN1 56 // CAN1
+#define INT_CAN2 57 // CAN2
+#define INT_ETH 58 // Ethernet
+#define INT_HIBERNATE 59 // Hibernation module
+#define INT_USB0 60 // USB 0 Controller
+#define INT_PWM3 61 // PWM Generator 3
+#define INT_UDMA 62 // uDMA controller
+#define INT_UDMAERR 63 // uDMA Error
+#define INT_ADC1SS0 64 // ADC1 Sequence 0
+#define INT_ADC1SS1 65 // ADC1 Sequence 1
+#define INT_ADC1SS2 66 // ADC1 Sequence 2
+#define INT_ADC1SS3 67 // ADC1 Sequence 3
+#define INT_I2S0 68 // I2S0
+#define INT_EPI0 69 // EPI0
+#define INT_GPIOJ 70 // GPIO Port J
+
+//*****************************************************************************
+//
+// The following are defines for the total number of interrupts.
+//
+//*****************************************************************************
+#define NUM_INTERRUPTS 70
+
+//*****************************************************************************
+//
+// The following are defines for the total number of priority levels.
+//
+//*****************************************************************************
+#define NUM_PRIORITY 8
+#define NUM_PRIORITY_BITS 3
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the interrupt assignments.
+//
+//*****************************************************************************
+#define INT_SSI 23 // SSI Rx and Tx
+#define INT_I2C 24 // I2C Master and Slave
+#define INT_QEI 29 // Quadrature Encoder
+
+#endif
+
+#endif // __HW_INTS_H__
Property changes on: branches/eagle_mmc/src/platform/lm3s/hw_ints.h
___________________________________________________________________
Name: svn:executable
+ *
Modified: branches/eagle_mmc/src/platform/lm3s/hw_memmap.h
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/hw_memmap.h 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lm3s/hw_memmap.h 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,110 +1,118 @@
-//*****************************************************************************
-//
-// hw_memmap.h - Macros defining the memory map of Stellaris.
-//
-// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
-// Software License Agreement
-//
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
-//
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws. All rights are reserved. You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program. Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
-//
-// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-//
-// This is part of revision 3740 of the Stellaris Firmware Development Package.
-//
-//*****************************************************************************
-
-#ifndef __HW_MEMMAP_H__
-#define __HW_MEMMAP_H__
-
-//*****************************************************************************
-//
-// The following are defines for the base address of the memories and
-// peripherals.
-//
-//*****************************************************************************
-#define FLASH_BASE 0x00000000 // FLASH memory
-#define SRAM_BASE 0x20000000 // SRAM memory
-#define WATCHDOG_BASE 0x40000000 // Watchdog
-#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A
-#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B
-#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C
-#define GPIO_PORTD_BASE 0x40007000 // GPIO Port D
-#define SSI0_BASE 0x40008000 // SSI0
-#define SSI1_BASE 0x40009000 // SSI1
-#define UART0_BASE 0x4000C000 // UART0
-#define UART1_BASE 0x4000D000 // UART1
-#define UART2_BASE 0x4000E000 // UART2
-#define I2C0_MASTER_BASE 0x40020000 // I2C0 Master
-#define I2C0_SLAVE_BASE 0x40020800 // I2C0 Slave
-#define I2C1_MASTER_BASE 0x40021000 // I2C1 Master
-#define I2C1_SLAVE_BASE 0x40021800 // I2C1 Slave
-#define GPIO_PORTE_BASE 0x40024000 // GPIO Port E
-#define GPIO_PORTF_BASE 0x40025000 // GPIO Port F
-#define GPIO_PORTG_BASE 0x40026000 // GPIO Port G
-#define GPIO_PORTH_BASE 0x40027000 // GPIO Port H
-#define PWM_BASE 0x40028000 // PWM
-#define QEI0_BASE 0x4002C000 // QEI0
-#define QEI1_BASE 0x4002D000 // QEI1
-#define TIMER0_BASE 0x40030000 // Timer0
-#define TIMER1_BASE 0x40031000 // Timer1
-#define TIMER2_BASE 0x40032000 // Timer2
-#define TIMER3_BASE 0x40033000 // Timer3
-#define ADC_BASE 0x40038000 // ADC
-#define COMP_BASE 0x4003C000 // Analog comparators
-#define CAN0_BASE 0x40040000 // CAN0
-#define CAN1_BASE 0x40041000 // CAN1
-#define CAN2_BASE 0x40042000 // CAN2
-#define ETH_BASE 0x40048000 // Ethernet
-#define MAC_BASE 0x40048000 // Ethernet
-#define USB0_BASE 0x40050000 // USB 0 Controller
-#define GPIO_PORTA_AHB_BASE 0x40058000 // GPIO Port A (high speed)
-#define GPIO_PORTB_AHB_BASE 0x40059000 // GPIO Port B (high speed)
-#define GPIO_PORTC_AHB_BASE 0x4005A000 // GPIO Port C (high speed)
-#define GPIO_PORTD_AHB_BASE 0x4005B000 // GPIO Port D (high speed)
-#define GPIO_PORTE_AHB_BASE 0x4005C000 // GPIO Port E (high speed)
-#define GPIO_PORTF_AHB_BASE 0x4005D000 // GPIO Port F (high speed)
-#define GPIO_PORTG_AHB_BASE 0x4005E000 // GPIO Port G (high speed)
-#define GPIO_PORTH_AHB_BASE 0x4005F000 // GPIO Port H (high speed)
-#define HIB_BASE 0x400FC000 // Hibernation Module
-#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller
-#define SYSCTL_BASE 0x400FE000 // System Control
-#define UDMA_BASE 0x400FF000 // uDMA Controller
-#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell
-#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace
-#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint
-#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl
-#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit
-
-//*****************************************************************************
-//
-// The following definitions are deprecated.
-//
-//*****************************************************************************
-#ifndef DEPRECATED
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the base address of the memories
-// and peripherals.
-//
-//*****************************************************************************
-#define SSI_BASE 0x40008000 // SSI
-#define I2C_MASTER_BASE 0x40020000 // I2C Master
-#define I2C_SLAVE_BASE 0x40020800 // I2C Slave
-#define QEI_BASE 0x4002C000 // QEI
-
-#endif
-
-#endif // __HW_MEMMAP_H__
+//*****************************************************************************
+//
+// hw_memmap.h - Macros defining the memory map of Stellaris.
+//
+// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4781 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_MEMMAP_H__
+#define __HW_MEMMAP_H__
+
+//*****************************************************************************
+//
+// The following are defines for the base address of the memories and
+// peripherals.
+//
+//*****************************************************************************
+#define FLASH_BASE 0x00000000 // FLASH memory
+#define SRAM_BASE 0x20000000 // SRAM memory
+#define WATCHDOG0_BASE 0x40000000 // Watchdog0
+#define WATCHDOG1_BASE 0x40001000 // Watchdog1
+#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A
+#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B
+#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C
+#define GPIO_PORTD_BASE 0x40007000 // GPIO Port D
+#define SSI0_BASE 0x40008000 // SSI0
+#define SSI1_BASE 0x40009000 // SSI1
+#define UART0_BASE 0x4000C000 // UART0
+#define UART1_BASE 0x4000D000 // UART1
+#define UART2_BASE 0x4000E000 // UART2
+#define I2C0_MASTER_BASE 0x40020000 // I2C0 Master
+#define I2C0_SLAVE_BASE 0x40020800 // I2C0 Slave
+#define I2C1_MASTER_BASE 0x40021000 // I2C1 Master
+#define I2C1_SLAVE_BASE 0x40021800 // I2C1 Slave
+#define GPIO_PORTE_BASE 0x40024000 // GPIO Port E
+#define GPIO_PORTF_BASE 0x40025000 // GPIO Port F
+#define GPIO_PORTG_BASE 0x40026000 // GPIO Port G
+#define GPIO_PORTH_BASE 0x40027000 // GPIO Port H
+#define PWM_BASE 0x40028000 // PWM
+#define QEI0_BASE 0x4002C000 // QEI0
+#define QEI1_BASE 0x4002D000 // QEI1
+#define TIMER0_BASE 0x40030000 // Timer0
+#define TIMER1_BASE 0x40031000 // Timer1
+#define TIMER2_BASE 0x40032000 // Timer2
+#define TIMER3_BASE 0x40033000 // Timer3
+#define ADC0_BASE 0x40038000 // ADC0
+#define ADC1_BASE 0x40039000 // ADC1
+#define COMP_BASE 0x4003C000 // Analog comparators
+#define GPIO_PORTJ_BASE 0x4003D000 // GPIO Port J
+#define CAN0_BASE 0x40040000 // CAN0
+#define CAN1_BASE 0x40041000 // CAN1
+#define CAN2_BASE 0x40042000 // CAN2
+#define ETH_BASE 0x40048000 // Ethernet
+#define MAC_BASE 0x40048000 // Ethernet
+#define USB0_BASE 0x40050000 // USB 0 Controller
+#define I2S0_BASE 0x40054000 // I2S0
+#define GPIO_PORTA_AHB_BASE 0x40058000 // GPIO Port A (high speed)
+#define GPIO_PORTB_AHB_BASE 0x40059000 // GPIO Port B (high speed)
+#define GPIO_PORTC_AHB_BASE 0x4005A000 // GPIO Port C (high speed)
+#define GPIO_PORTD_AHB_BASE 0x4005B000 // GPIO Port D (high speed)
+#define GPIO_PORTE_AHB_BASE 0x4005C000 // GPIO Port E (high speed)
+#define GPIO_PORTF_AHB_BASE 0x4005D000 // GPIO Port F (high speed)
+#define GPIO_PORTG_AHB_BASE 0x4005E000 // GPIO Port G (high speed)
+#define GPIO_PORTH_AHB_BASE 0x4005F000 // GPIO Port H (high speed)
+#define GPIO_PORTJ_AHB_BASE 0x40060000 // GPIO Port J (high speed)
+#define EPI0_BASE 0x400D0000 // EPI0
+#define HIB_BASE 0x400FC000 // Hibernation Module
+#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller
+#define SYSCTL_BASE 0x400FE000 // System Control
+#define UDMA_BASE 0x400FF000 // uDMA Controller
+#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell
+#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace
+#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint
+#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl
+#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the base address of the memories
+// and peripherals.
+//
+//*****************************************************************************
+#define WATCHDOG_BASE 0x40000000 // Watchdog
+#define SSI_BASE 0x40008000 // SSI
+#define I2C_MASTER_BASE 0x40020000 // I2C Master
+#define I2C_SLAVE_BASE 0x40020800 // I2C Slave
+#define QEI_BASE 0x4002C000 // QEI
+#define ADC_BASE 0x40038000 // ADC
+
+#endif
+
+#endif // __HW_MEMMAP_H__
Property changes on: branches/eagle_mmc/src/platform/lm3s/hw_memmap.h
___________________________________________________________________
Name: svn:executable
+ *
Modified: branches/eagle_mmc/src/platform/lm3s/hw_nvic.h
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/hw_nvic.h 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lm3s/hw_nvic.h 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,1025 +1,1027 @@
-//*****************************************************************************
-//
-// hw_nvic.h - Macros used when accessing the NVIC hardware.
-//
-// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
-// Software License Agreement
-//
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
-//
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws. All rights are reserved. You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program. Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
-//
-// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-//
-// This is part of revision 3740 of the Stellaris Firmware Development Package.
-//
-//*****************************************************************************
-
-#ifndef __HW_NVIC_H__
-#define __HW_NVIC_H__
-
-//*****************************************************************************
-//
-// The following are defines for the NVIC register addresses.
-//
-//*****************************************************************************
-#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg.
-#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status Reg.
-#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register
-#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register
-#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg.
-#define NVIC_EN0 0xE000E100 // IRQ 0 to 31 Set Enable Register
-#define NVIC_EN1 0xE000E104 // IRQ 32 to 63 Set Enable Register
-#define NVIC_DIS0 0xE000E180 // IRQ 0 to 31 Clear Enable Reg.
-#define NVIC_DIS1 0xE000E184 // IRQ 32 to 63 Clear Enable Reg.
-#define NVIC_PEND0 0xE000E200 // IRQ 0 to 31 Set Pending Register
-#define NVIC_PEND1 0xE000E204 // IRQ 32 to 63 Set Pending Reg.
-#define NVIC_UNPEND0 0xE000E280 // IRQ 0 to 31 Clear Pending Reg.
-#define NVIC_UNPEND1 0xE000E284 // IRQ 32 to 63 Clear Pending Reg.
-#define NVIC_ACTIVE0 0xE000E300 // IRQ 0 to 31 Active Register
-#define NVIC_ACTIVE1 0xE000E304 // IRQ 32 to 63 Active Register
-#define NVIC_PRI0 0xE000E400 // IRQ 0 to 3 Priority Register
-#define NVIC_PRI1 0xE000E404 // IRQ 4 to 7 Priority Register
-#define NVIC_PRI2 0xE000E408 // IRQ 8 to 11 Priority Register
-#define NVIC_PRI3 0xE000E40C // IRQ 12 to 15 Priority Register
-#define NVIC_PRI4 0xE000E410 // IRQ 16 to 19 Priority Register
-#define NVIC_PRI5 0xE000E414 // IRQ 20 to 23 Priority Register
-#define NVIC_PRI6 0xE000E418 // IRQ 24 to 27 Priority Register
-#define NVIC_PRI7 0xE000E41C // IRQ 28 to 31 Priority Register
-#define NVIC_PRI8 0xE000E420 // IRQ 32 to 35 Priority Register
-#define NVIC_PRI9 0xE000E424 // IRQ 36 to 39 Priority Register
-#define NVIC_PRI10 0xE000E428 // IRQ 40 to 43 Priority Register
-#define NVIC_PRI11 0xE000E42C // IRQ 44 to 47 Priority Register
-#define NVIC_CPUID 0xE000ED00 // CPUID Base Register
-#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control State Register
-#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset Register
-#define NVIC_APINT 0xE000ED0C // App. Int & Reset Control Reg.
-#define NVIC_SYS_CTRL 0xE000ED10 // System Control Register
-#define NVIC_CFG_CTRL 0xE000ED14 // Configuration Control Register
-#define NVIC_SYS_PRI1 0xE000ED18 // Sys. Handlers 4 to 7 Priority
-#define NVIC_SYS_PRI2 0xE000ED1C // Sys. Handlers 8 to 11 Priority
-#define NVIC_SYS_PRI3 0xE000ED20 // Sys. Handlers 12 to 15 Priority
-#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State
-#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status Reg.
-#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status Register
-#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register
-#define NVIC_MM_ADDR 0xE000ED34 // Mem Manage Address Register
-#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address Register
-#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type Register
-#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control Register
-#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number Register
-#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address Register
-#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute & Size Reg.
-#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg.
-#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select
-#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data
-#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control
-#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt Reg.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_INT_TYPE register.
-//
-//*****************************************************************************
-#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32)
-#define NVIC_INT_TYPE_LINES_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_ST_CTRL register.
-//
-//*****************************************************************************
-#define NVIC_ST_CTRL_COUNT 0x00010000 // Count flag
-#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source
-#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt enable
-#define NVIC_ST_CTRL_ENABLE 0x00000001 // Counter mode
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_ST_RELOAD register.
-//
-//*****************************************************************************
-#define NVIC_ST_RELOAD_M 0x00FFFFFF // Counter load value
-#define NVIC_ST_RELOAD_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_ST_CURRENT
-// register.
-//
-//*****************************************************************************
-#define NVIC_ST_CURRENT_M 0x00FFFFFF // Counter current value
-#define NVIC_ST_CURRENT_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_ST_CAL register.
-//
-//*****************************************************************************
-#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock
-#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew
-#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value
-#define NVIC_ST_CAL_ONEMS_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_EN0 register.
-//
-//*****************************************************************************
-#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable
-#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable
-#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable
-#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable
-#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable
-#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable
-#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable
-#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable
-#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable
-#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable
-#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable
-#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable
-#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable
-#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable
-#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable
-#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable
-#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable
-#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable
-#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable
-#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable
-#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable
-#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable
-#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable
-#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable
-#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable
-#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable
-#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable
-#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable
-#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable
-#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable
-#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable
-#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_EN1 register.
-//
-//*****************************************************************************
-#define NVIC_EN1_INT59 0x08000000 // Interrupt 59 enable
-#define NVIC_EN1_INT58 0x04000000 // Interrupt 58 enable
-#define NVIC_EN1_INT57 0x02000000 // Interrupt 57 enable
-#define NVIC_EN1_INT56 0x01000000 // Interrupt 56 enable
-#define NVIC_EN1_INT55 0x00800000 // Interrupt 55 enable
-#define NVIC_EN1_INT54 0x00400000 // Interrupt 54 enable
-#define NVIC_EN1_INT53 0x00200000 // Interrupt 53 enable
-#define NVIC_EN1_INT52 0x00100000 // Interrupt 52 enable
-#define NVIC_EN1_INT51 0x00080000 // Interrupt 51 enable
-#define NVIC_EN1_INT50 0x00040000 // Interrupt 50 enable
-#define NVIC_EN1_INT49 0x00020000 // Interrupt 49 enable
-#define NVIC_EN1_INT48 0x00010000 // Interrupt 48 enable
-#define NVIC_EN1_INT47 0x00008000 // Interrupt 47 enable
-#define NVIC_EN1_INT46 0x00004000 // Interrupt 46 enable
-#define NVIC_EN1_INT45 0x00002000 // Interrupt 45 enable
-#define NVIC_EN1_INT44 0x00001000 // Interrupt 44 enable
-#define NVIC_EN1_INT43 0x00000800 // Interrupt 43 enable
-#define NVIC_EN1_INT42 0x00000400 // Interrupt 42 enable
-#define NVIC_EN1_INT41 0x00000200 // Interrupt 41 enable
-#define NVIC_EN1_INT40 0x00000100 // Interrupt 40 enable
-#define NVIC_EN1_INT39 0x00000080 // Interrupt 39 enable
-#define NVIC_EN1_INT38 0x00000040 // Interrupt 38 enable
-#define NVIC_EN1_INT37 0x00000020 // Interrupt 37 enable
-#define NVIC_EN1_INT36 0x00000010 // Interrupt 36 enable
-#define NVIC_EN1_INT35 0x00000008 // Interrupt 35 enable
-#define NVIC_EN1_INT34 0x00000004 // Interrupt 34 enable
-#define NVIC_EN1_INT33 0x00000002 // Interrupt 33 enable
-#define NVIC_EN1_INT32 0x00000001 // Interrupt 32 enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_DIS0 register.
-//
-//*****************************************************************************
-#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable
-#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable
-#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable
-#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable
-#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable
-#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable
-#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable
-#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable
-#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable
-#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable
-#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable
-#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable
-#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable
-#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable
-#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable
-#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable
-#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable
-#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable
-#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable
-#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable
-#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable
-#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable
-#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable
-#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable
-#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable
-#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable
-#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable
-#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable
-#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable
-#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable
-#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable
-#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_DIS1 register.
-//
-//*****************************************************************************
-#define NVIC_DIS1_INT59 0x08000000 // Interrupt 59 disable
-#define NVIC_DIS1_INT58 0x04000000 // Interrupt 58 disable
-#define NVIC_DIS1_INT57 0x02000000 // Interrupt 57 disable
-#define NVIC_DIS1_INT56 0x01000000 // Interrupt 56 disable
-#define NVIC_DIS1_INT55 0x00800000 // Interrupt 55 disable
-#define NVIC_DIS1_INT54 0x00400000 // Interrupt 54 disable
-#define NVIC_DIS1_INT53 0x00200000 // Interrupt 53 disable
-#define NVIC_DIS1_INT52 0x00100000 // Interrupt 52 disable
-#define NVIC_DIS1_INT51 0x00080000 // Interrupt 51 disable
-#define NVIC_DIS1_INT50 0x00040000 // Interrupt 50 disable
-#define NVIC_DIS1_INT49 0x00020000 // Interrupt 49 disable
-#define NVIC_DIS1_INT48 0x00010000 // Interrupt 48 disable
-#define NVIC_DIS1_INT47 0x00008000 // Interrupt 47 disable
-#define NVIC_DIS1_INT46 0x00004000 // Interrupt 46 disable
-#define NVIC_DIS1_INT45 0x00002000 // Interrupt 45 disable
-#define NVIC_DIS1_INT44 0x00001000 // Interrupt 44 disable
-#define NVIC_DIS1_INT43 0x00000800 // Interrupt 43 disable
-#define NVIC_DIS1_INT42 0x00000400 // Interrupt 42 disable
-#define NVIC_DIS1_INT41 0x00000200 // Interrupt 41 disable
-#define NVIC_DIS1_INT40 0x00000100 // Interrupt 40 disable
-#define NVIC_DIS1_INT39 0x00000080 // Interrupt 39 disable
-#define NVIC_DIS1_INT38 0x00000040 // Interrupt 38 disable
-#define NVIC_DIS1_INT37 0x00000020 // Interrupt 37 disable
-#define NVIC_DIS1_INT36 0x00000010 // Interrupt 36 disable
-#define NVIC_DIS1_INT35 0x00000008 // Interrupt 35 disable
-#define NVIC_DIS1_INT34 0x00000004 // Interrupt 34 disable
-#define NVIC_DIS1_INT33 0x00000002 // Interrupt 33 disable
-#define NVIC_DIS1_INT32 0x00000001 // Interrupt 32 disable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PEND0 register.
-//
-//*****************************************************************************
-#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend
-#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend
-#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend
-#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend
-#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend
-#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend
-#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend
-#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend
-#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend
-#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend
-#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend
-#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend
-#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend
-#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend
-#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend
-#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend
-#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend
-#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend
-#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend
-#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend
-#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend
-#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend
-#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend
-#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend
-#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend
-#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend
-#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend
-#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend
-#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend
-#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend
-#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend
-#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PEND1 register.
-//
-//*****************************************************************************
-#define NVIC_PEND1_INT59 0x08000000 // Interrupt 59 pend
-#define NVIC_PEND1_INT58 0x04000000 // Interrupt 58 pend
-#define NVIC_PEND1_INT57 0x02000000 // Interrupt 57 pend
-#define NVIC_PEND1_INT56 0x01000000 // Interrupt 56 pend
-#define NVIC_PEND1_INT55 0x00800000 // Interrupt 55 pend
-#define NVIC_PEND1_INT54 0x00400000 // Interrupt 54 pend
-#define NVIC_PEND1_INT53 0x00200000 // Interrupt 53 pend
-#define NVIC_PEND1_INT52 0x00100000 // Interrupt 52 pend
-#define NVIC_PEND1_INT51 0x00080000 // Interrupt 51 pend
-#define NVIC_PEND1_INT50 0x00040000 // Interrupt 50 pend
-#define NVIC_PEND1_INT49 0x00020000 // Interrupt 49 pend
-#define NVIC_PEND1_INT48 0x00010000 // Interrupt 48 pend
-#define NVIC_PEND1_INT47 0x00008000 // Interrupt 47 pend
-#define NVIC_PEND1_INT46 0x00004000 // Interrupt 46 pend
-#define NVIC_PEND1_INT45 0x00002000 // Interrupt 45 pend
-#define NVIC_PEND1_INT44 0x00001000 // Interrupt 44 pend
-#define NVIC_PEND1_INT43 0x00000800 // Interrupt 43 pend
-#define NVIC_PEND1_INT42 0x00000400 // Interrupt 42 pend
-#define NVIC_PEND1_INT41 0x00000200 // Interrupt 41 pend
-#define NVIC_PEND1_INT40 0x00000100 // Interrupt 40 pend
-#define NVIC_PEND1_INT39 0x00000080 // Interrupt 39 pend
-#define NVIC_PEND1_INT38 0x00000040 // Interrupt 38 pend
-#define NVIC_PEND1_INT37 0x00000020 // Interrupt 37 pend
-#define NVIC_PEND1_INT36 0x00000010 // Interrupt 36 pend
-#define NVIC_PEND1_INT35 0x00000008 // Interrupt 35 pend
-#define NVIC_PEND1_INT34 0x00000004 // Interrupt 34 pend
-#define NVIC_PEND1_INT33 0x00000002 // Interrupt 33 pend
-#define NVIC_PEND1_INT32 0x00000001 // Interrupt 32 pend
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_UNPEND0 register.
-//
-//*****************************************************************************
-#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend
-#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend
-#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend
-#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend
-#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend
-#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend
-#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend
-#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend
-#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend
-#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend
-#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend
-#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend
-#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend
-#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend
-#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend
-#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend
-#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend
-#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend
-#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend
-#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend
-#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend
-#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend
-#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend
-#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend
-#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend
-#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend
-#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend
-#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend
-#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend
-#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend
-#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend
-#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_UNPEND1 register.
-//
-//*****************************************************************************
-#define NVIC_UNPEND1_INT59 0x08000000 // Interrupt 59 unpend
-#define NVIC_UNPEND1_INT58 0x04000000 // Interrupt 58 unpend
-#define NVIC_UNPEND1_INT57 0x02000000 // Interrupt 57 unpend
-#define NVIC_UNPEND1_INT56 0x01000000 // Interrupt 56 unpend
-#define NVIC_UNPEND1_INT55 0x00800000 // Interrupt 55 unpend
-#define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend
-#define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend
-#define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend
-#define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend
-#define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend
-#define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend
-#define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend
-#define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend
-#define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend
-#define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend
-#define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend
-#define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend
-#define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend
-#define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend
-#define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend
-#define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend
-#define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend
-#define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend
-#define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend
-#define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend
-#define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend
-#define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend
-#define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_ACTIVE0 register.
-//
-//*****************************************************************************
-#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active
-#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active
-#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active
-#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active
-#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active
-#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active
-#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active
-#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active
-#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active
-#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active
-#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active
-#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active
-#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active
-#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active
-#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active
-#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active
-#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active
-#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active
-#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active
-#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active
-#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active
-#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active
-#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active
-#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active
-#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active
-#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active
-#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active
-#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active
-#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active
-#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active
-#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active
-#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_ACTIVE1 register.
-//
-//*****************************************************************************
-#define NVIC_ACTIVE1_INT59 0x08000000 // Interrupt 59 active
-#define NVIC_ACTIVE1_INT58 0x04000000 // Interrupt 58 active
-#define NVIC_ACTIVE1_INT57 0x02000000 // Interrupt 57 active
-#define NVIC_ACTIVE1_INT56 0x01000000 // Interrupt 56 active
-#define NVIC_ACTIVE1_INT55 0x00800000 // Interrupt 55 active
-#define NVIC_ACTIVE1_INT54 0x00400000 // Interrupt 54 active
-#define NVIC_ACTIVE1_INT53 0x00200000 // Interrupt 53 active
-#define NVIC_ACTIVE1_INT52 0x00100000 // Interrupt 52 active
-#define NVIC_ACTIVE1_INT51 0x00080000 // Interrupt 51 active
-#define NVIC_ACTIVE1_INT50 0x00040000 // Interrupt 50 active
-#define NVIC_ACTIVE1_INT49 0x00020000 // Interrupt 49 active
-#define NVIC_ACTIVE1_INT48 0x00010000 // Interrupt 48 active
-#define NVIC_ACTIVE1_INT47 0x00008000 // Interrupt 47 active
-#define NVIC_ACTIVE1_INT46 0x00004000 // Interrupt 46 active
-#define NVIC_ACTIVE1_INT45 0x00002000 // Interrupt 45 active
-#define NVIC_ACTIVE1_INT44 0x00001000 // Interrupt 44 active
-#define NVIC_ACTIVE1_INT43 0x00000800 // Interrupt 43 active
-#define NVIC_ACTIVE1_INT42 0x00000400 // Interrupt 42 active
-#define NVIC_ACTIVE1_INT41 0x00000200 // Interrupt 41 active
-#define NVIC_ACTIVE1_INT40 0x00000100 // Interrupt 40 active
-#define NVIC_ACTIVE1_INT39 0x00000080 // Interrupt 39 active
-#define NVIC_ACTIVE1_INT38 0x00000040 // Interrupt 38 active
-#define NVIC_ACTIVE1_INT37 0x00000020 // Interrupt 37 active
-#define NVIC_ACTIVE1_INT36 0x00000010 // Interrupt 36 active
-#define NVIC_ACTIVE1_INT35 0x00000008 // Interrupt 35 active
-#define NVIC_ACTIVE1_INT34 0x00000004 // Interrupt 34 active
-#define NVIC_ACTIVE1_INT33 0x00000002 // Interrupt 33 active
-#define NVIC_ACTIVE1_INT32 0x00000001 // Interrupt 32 active
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI0 register.
-//
-//*****************************************************************************
-#define NVIC_PRI0_INT3_M 0xFF000000 // Interrupt 3 priority mask
-#define NVIC_PRI0_INT2_M 0x00FF0000 // Interrupt 2 priority mask
-#define NVIC_PRI0_INT1_M 0x0000FF00 // Interrupt 1 priority mask
-#define NVIC_PRI0_INT0_M 0x000000FF // Interrupt 0 priority mask
-#define NVIC_PRI0_INT3_S 24
-#define NVIC_PRI0_INT2_S 16
-#define NVIC_PRI0_INT1_S 8
-#define NVIC_PRI0_INT0_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI1 register.
-//
-//*****************************************************************************
-#define NVIC_PRI1_INT7_M 0xFF000000 // Interrupt 7 priority mask
-#define NVIC_PRI1_INT6_M 0x00FF0000 // Interrupt 6 priority mask
-#define NVIC_PRI1_INT5_M 0x0000FF00 // Interrupt 5 priority mask
-#define NVIC_PRI1_INT4_M 0x000000FF // Interrupt 4 priority mask
-#define NVIC_PRI1_INT7_S 24
-#define NVIC_PRI1_INT6_S 16
-#define NVIC_PRI1_INT5_S 8
-#define NVIC_PRI1_INT4_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI2 register.
-//
-//*****************************************************************************
-#define NVIC_PRI2_INT11_M 0xFF000000 // Interrupt 11 priority mask
-#define NVIC_PRI2_INT10_M 0x00FF0000 // Interrupt 10 priority mask
-#define NVIC_PRI2_INT9_M 0x0000FF00 // Interrupt 9 priority mask
-#define NVIC_PRI2_INT8_M 0x000000FF // Interrupt 8 priority mask
-#define NVIC_PRI2_INT11_S 24
-#define NVIC_PRI2_INT10_S 16
-#define NVIC_PRI2_INT9_S 8
-#define NVIC_PRI2_INT8_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI3 register.
-//
-//*****************************************************************************
-#define NVIC_PRI3_INT15_M 0xFF000000 // Interrupt 15 priority mask
-#define NVIC_PRI3_INT14_M 0x00FF0000 // Interrupt 14 priority mask
-#define NVIC_PRI3_INT13_M 0x0000FF00 // Interrupt 13 priority mask
-#define NVIC_PRI3_INT12_M 0x000000FF // Interrupt 12 priority mask
-#define NVIC_PRI3_INT15_S 24
-#define NVIC_PRI3_INT14_S 16
-#define NVIC_PRI3_INT13_S 8
-#define NVIC_PRI3_INT12_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI4 register.
-//
-//*****************************************************************************
-#define NVIC_PRI4_INT19_M 0xFF000000 // Interrupt 19 priority mask
-#define NVIC_PRI4_INT18_M 0x00FF0000 // Interrupt 18 priority mask
-#define NVIC_PRI4_INT17_M 0x0000FF00 // Interrupt 17 priority mask
-#define NVIC_PRI4_INT16_M 0x000000FF // Interrupt 16 priority mask
-#define NVIC_PRI4_INT19_S 24
-#define NVIC_PRI4_INT18_S 16
-#define NVIC_PRI4_INT17_S 8
-#define NVIC_PRI4_INT16_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI5 register.
-//
-//*****************************************************************************
-#define NVIC_PRI5_INT23_M 0xFF000000 // Interrupt 23 priority mask
-#define NVIC_PRI5_INT22_M 0x00FF0000 // Interrupt 22 priority mask
-#define NVIC_PRI5_INT21_M 0x0000FF00 // Interrupt 21 priority mask
-#define NVIC_PRI5_INT20_M 0x000000FF // Interrupt 20 priority mask
-#define NVIC_PRI5_INT23_S 24
-#define NVIC_PRI5_INT22_S 16
-#define NVIC_PRI5_INT21_S 8
-#define NVIC_PRI5_INT20_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI6 register.
-//
-//*****************************************************************************
-#define NVIC_PRI6_INT27_M 0xFF000000 // Interrupt 27 priority mask
-#define NVIC_PRI6_INT26_M 0x00FF0000 // Interrupt 26 priority mask
-#define NVIC_PRI6_INT25_M 0x0000FF00 // Interrupt 25 priority mask
-#define NVIC_PRI6_INT24_M 0x000000FF // Interrupt 24 priority mask
-#define NVIC_PRI6_INT27_S 24
-#define NVIC_PRI6_INT26_S 16
-#define NVIC_PRI6_INT25_S 8
-#define NVIC_PRI6_INT24_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI7 register.
-//
-//*****************************************************************************
-#define NVIC_PRI7_INT31_M 0xFF000000 // Interrupt 31 priority mask
-#define NVIC_PRI7_INT30_M 0x00FF0000 // Interrupt 30 priority mask
-#define NVIC_PRI7_INT29_M 0x0000FF00 // Interrupt 29 priority mask
-#define NVIC_PRI7_INT28_M 0x000000FF // Interrupt 28 priority mask
-#define NVIC_PRI7_INT31_S 24
-#define NVIC_PRI7_INT30_S 16
-#define NVIC_PRI7_INT29_S 8
-#define NVIC_PRI7_INT28_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI8 register.
-//
-//*****************************************************************************
-#define NVIC_PRI8_INT35_M 0xFF000000 // Interrupt 35 priority mask
-#define NVIC_PRI8_INT34_M 0x00FF0000 // Interrupt 34 priority mask
-#define NVIC_PRI8_INT33_M 0x0000FF00 // Interrupt 33 priority mask
-#define NVIC_PRI8_INT32_M 0x000000FF // Interrupt 32 priority mask
-#define NVIC_PRI8_INT35_S 24
-#define NVIC_PRI8_INT34_S 16
-#define NVIC_PRI8_INT33_S 8
-#define NVIC_PRI8_INT32_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI9 register.
-//
-//*****************************************************************************
-#define NVIC_PRI9_INT39_M 0xFF000000 // Interrupt 39 priority mask
-#define NVIC_PRI9_INT38_M 0x00FF0000 // Interrupt 38 priority mask
-#define NVIC_PRI9_INT37_M 0x0000FF00 // Interrupt 37 priority mask
-#define NVIC_PRI9_INT36_M 0x000000FF // Interrupt 36 priority mask
-#define NVIC_PRI9_INT39_S 24
-#define NVIC_PRI9_INT38_S 16
-#define NVIC_PRI9_INT37_S 8
-#define NVIC_PRI9_INT36_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI10 register.
-//
-//*****************************************************************************
-#define NVIC_PRI10_INT43_M 0xFF000000 // Interrupt 43 priority mask
-#define NVIC_PRI10_INT42_M 0x00FF0000 // Interrupt 42 priority mask
-#define NVIC_PRI10_INT41_M 0x0000FF00 // Interrupt 41 priority mask
-#define NVIC_PRI10_INT40_M 0x000000FF // Interrupt 40 priority mask
-#define NVIC_PRI10_INT43_S 24
-#define NVIC_PRI10_INT42_S 16
-#define NVIC_PRI10_INT41_S 8
-#define NVIC_PRI10_INT40_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_CPUID register.
-//
-//*****************************************************************************
-#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer
-#define NVIC_CPUID_VAR_M 0x00F00000 // Variant
-#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Processor part number
-#define NVIC_CPUID_REV_M 0x0000000F // Revision
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_INT_CTRL register.
-//
-//*****************************************************************************
-#define NVIC_INT_CTRL_NMI_SET 0x80000000 // Pend a NMI
-#define NVIC_INT_CTRL_PEND_SV 0x10000000 // Pend a PendSV
-#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // Unpend a PendSV
-#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug interrupt handling
-#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Debug interrupt pending
-#define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000 // Highest pending exception
-#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to base
-#define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF // Current active exception
-#define NVIC_INT_CTRL_VEC_PEN_S 12
-#define NVIC_INT_CTRL_VEC_ACT_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_VTABLE register.
-//
-//*****************************************************************************
-#define NVIC_VTABLE_BASE 0x20000000 // Vector table base
-#define NVIC_VTABLE_OFFSET_M 0x1FFFFF00 // Vector table offset
-#define NVIC_VTABLE_OFFSET_S 8
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_APINT register.
-//
-//*****************************************************************************
-#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Vector key mask
-#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key
-#define NVIC_APINT_ENDIANESS 0x00008000 // Data endianess
-#define NVIC_APINT_PRIGROUP_M 0x00000700 // Priority group
-#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split
-#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split
-#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split
-#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split
-#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split
-#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split
-#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split
-#define NVIC_APINT_SYSRESETREQ 0x00000004 // System reset request
-#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear active NMI/fault info
-#define NVIC_APINT_VECT_RESET 0x00000001 // System reset
-#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_SYS_CTRL register.
-//
-//*****************************************************************************
-#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wakeup on pend
-#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep sleep enable
-#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR exit
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_CFG_CTRL register.
-//
-//*****************************************************************************
-#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore bus fault in NMI/fault
-#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on divide by 0
-#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on unaligned access
-#define NVIC_CFG_CTRL_DEEP_PEND 0x00000004 // Allow deep interrupt trigger
-#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow main interrupt trigger
-#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread state control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_SYS_PRI1 register.
-//
-//*****************************************************************************
-#define NVIC_SYS_PRI1_RES_M 0xFF000000 // Priority of reserved handler
-#define NVIC_SYS_PRI1_USAGE_M 0x00FF0000 // Priority of usage fault handler
-#define NVIC_SYS_PRI1_BUS_M 0x0000FF00 // Priority of bus fault handler
-#define NVIC_SYS_PRI1_MEM_M 0x000000FF // Priority of mem manage handler
-#define NVIC_SYS_PRI1_USAGE_S 16
-#define NVIC_SYS_PRI1_BUS_S 8
-#define NVIC_SYS_PRI1_MEM_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_SYS_PRI2 register.
-//
-//*****************************************************************************
-#define NVIC_SYS_PRI2_SVC_M 0xFF000000 // Priority of SVCall handler
-#define NVIC_SYS_PRI2_RES_M 0x00FFFFFF // Priority of reserved handlers
-#define NVIC_SYS_PRI2_SVC_S 24
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_SYS_PRI3 register.
-//
-//*****************************************************************************
-#define NVIC_SYS_PRI3_TICK_M 0xFF000000 // Priority of Sys Tick handler
-#define NVIC_SYS_PRI3_PENDSV_M 0x00FF0000 // Priority of PendSV handler
-#define NVIC_SYS_PRI3_RES_M 0x0000FF00 // Priority of reserved handler
-#define NVIC_SYS_PRI3_DEBUG_M 0x000000FF // Priority of debug handler
-#define NVIC_SYS_PRI3_TICK_S 24
-#define NVIC_SYS_PRI3_PENDSV_S 16
-#define NVIC_SYS_PRI3_DEBUG_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_SYS_HND_CTRL
-// register.
-//
-//*****************************************************************************
-#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage fault enable
-#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus fault enable
-#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Mem manage fault enable
-#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVCall is pended
-#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus fault is pended
-#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // Sys tick is active
-#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV is active
-#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Monitor is active
-#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVCall is active
-#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage fault is active
-#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus fault is active
-#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Mem manage is active
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_FAULT_STAT
-// register.
-//
-//*****************************************************************************
-#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide by zero fault
-#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned access fault
-#define NVIC_FAULT_STAT_NOCP 0x00080000 // No coprocessor fault
-#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC fault
-#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid state fault
-#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined instruction fault
-#define NVIC_FAULT_STAT_BFARV 0x00008000 // BFAR is valid
-#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack bus fault
-#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack bus fault
-#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise data bus error
-#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise data bus error
-#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction bus fault
-#define NVIC_FAULT_STAT_MMARV 0x00000080 // MMAR is valid
-#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack access violation
-#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack access violation
-#define NVIC_FAULT_STAT_DERR 0x00000002 // Data access violation
-#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction access violation
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_HFAULT_STAT
-// register.
-//
-//*****************************************************************************
-#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug event
-#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Cannot execute fault handler
-#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector table read fault
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_DEBUG_STAT
-// register.
-//
-//*****************************************************************************
-#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted
-#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch
-#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match
-#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction
-#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_MM_ADDR register.
-//
-//*****************************************************************************
-#define NVIC_MM_ADDR_M 0xFFFFFFFF // Data fault address
-#define NVIC_MM_ADDR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_FAULT_ADDR
-// register.
-//
-//*****************************************************************************
-#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Data bus fault address
-#define NVIC_FAULT_ADDR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_MPU_TYPE register.
-//
-//*****************************************************************************
-#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I regions
-#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D regions
-#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or unified MPU
-#define NVIC_MPU_TYPE_IREGION_S 16
-#define NVIC_MPU_TYPE_DREGION_S 8
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_MPU_CTRL register.
-//
-//*****************************************************************************
-#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004 // MPU default region in priv mode
-#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU enabled during faults
-#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_MPU_NUMBER
-// register.
-//
-//*****************************************************************************
-#define NVIC_MPU_NUMBER_M 0x000000FF // MPU region to access
-#define NVIC_MPU_NUMBER_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_MPU_BASE register.
-//
-//*****************************************************************************
-#define NVIC_MPU_BASE_ADDR_M 0xFFFFFFE0 // Base address mask
-#define NVIC_MPU_BASE_VALID 0x00000010 // Region number valid
-#define NVIC_MPU_BASE_REGION_M 0x0000000F // Region number
-#define NVIC_MPU_BASE_ADDR_S 8
-#define NVIC_MPU_BASE_REGION_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_MPU_ATTR register.
-//
-//*****************************************************************************
-#define NVIC_MPU_ATTR_M 0xFFFF0000 // Attributes
-#define NVIC_MPU_ATTR_AP_NO_NO 0x00000000 // prv: no access, usr: no access
-#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000 // Bufferable
-#define NVIC_MPU_ATTR_CACHEABLE 0x00020000 // Cacheable
-#define NVIC_MPU_ATTR_SHAREABLE 0x00040000 // Shareable
-#define NVIC_MPU_ATTR_TEX_M 0x00380000 // Type extension mask
-#define NVIC_MPU_ATTR_AP_RW_NO 0x01000000 // prv: rw, usr: none
-#define NVIC_MPU_ATTR_AP_RW_RO 0x02000000 // prv: rw, usr: read-only
-#define NVIC_MPU_ATTR_AP_RW_RW 0x03000000 // prv: rw, usr: rw
-#define NVIC_MPU_ATTR_AP_RO_NO 0x05000000 // prv: ro, usr: none
-#define NVIC_MPU_ATTR_AP_RO_RO 0x06000000 // prv: ro, usr: ro
-#define NVIC_MPU_ATTR_AP_M 0x07000000 // Access permissions mask
-#define NVIC_MPU_ATTR_XN 0x10000000 // Execute disable
-#define NVIC_MPU_ATTR_SRD_M 0x0000FF00 // Sub-region disable mask
-#define NVIC_MPU_ATTR_SRD_0 0x00000100 // Sub-region 0 disable
-#define NVIC_MPU_ATTR_SRD_1 0x00000200 // Sub-region 1 disable
-#define NVIC_MPU_ATTR_SRD_2 0x00000400 // Sub-region 2 disable
-#define NVIC_MPU_ATTR_SRD_3 0x00000800 // Sub-region 3 disable
-#define NVIC_MPU_ATTR_SRD_4 0x00001000 // Sub-region 4 disable
-#define NVIC_MPU_ATTR_SRD_5 0x00002000 // Sub-region 5 disable
-#define NVIC_MPU_ATTR_SRD_6 0x00004000 // Sub-region 6 disable
-#define NVIC_MPU_ATTR_SRD_7 0x00008000 // Sub-region 7 disable
-#define NVIC_MPU_ATTR_SIZE_M 0x0000003E // Region size mask
-#define NVIC_MPU_ATTR_SIZE_32B 0x00000008 // Region size 32 bytes
-#define NVIC_MPU_ATTR_SIZE_64B 0x0000000A // Region size 64 bytes
-#define NVIC_MPU_ATTR_SIZE_128B 0x0000000C // Region size 128 bytes
-#define NVIC_MPU_ATTR_SIZE_256B 0x0000000E // Region size 256 bytes
-#define NVIC_MPU_ATTR_SIZE_512B 0x00000010 // Region size 512 bytes
-#define NVIC_MPU_ATTR_SIZE_1K 0x00000012 // Region size 1 Kbytes
-#define NVIC_MPU_ATTR_SIZE_2K 0x00000014 // Region size 2 Kbytes
-#define NVIC_MPU_ATTR_SIZE_4K 0x00000016 // Region size 4 Kbytes
-#define NVIC_MPU_ATTR_SIZE_8K 0x00000018 // Region size 8 Kbytes
-#define NVIC_MPU_ATTR_SIZE_16K 0x0000001A // Region size 16 Kbytes
-#define NVIC_MPU_ATTR_SIZE_32K 0x0000001C // Region size 32 Kbytes
-#define NVIC_MPU_ATTR_SIZE_64K 0x0000001E // Region size 64 Kbytes
-#define NVIC_MPU_ATTR_SIZE_128K 0x00000020 // Region size 128 Kbytes
-#define NVIC_MPU_ATTR_SIZE_256K 0x00000022 // Region size 256 Kbytes
-#define NVIC_MPU_ATTR_SIZE_512K 0x00000024 // Region size 512 Kbytes
-#define NVIC_MPU_ATTR_SIZE_1M 0x00000026 // Region size 1 Mbytes
-#define NVIC_MPU_ATTR_SIZE_2M 0x00000028 // Region size 2 Mbytes
-#define NVIC_MPU_ATTR_SIZE_4M 0x0000002A // Region size 4 Mbytes
-#define NVIC_MPU_ATTR_SIZE_8M 0x0000002C // Region size 8 Mbytes
-#define NVIC_MPU_ATTR_SIZE_16M 0x0000002E // Region size 16 Mbytes
-#define NVIC_MPU_ATTR_SIZE_32M 0x00000030 // Region size 32 Mbytes
-#define NVIC_MPU_ATTR_SIZE_64M 0x00000032 // Region size 64 Mbytes
-#define NVIC_MPU_ATTR_SIZE_128M 0x00000034 // Region size 128 Mbytes
-#define NVIC_MPU_ATTR_SIZE_256M 0x00000036 // Region size 256 Mbytes
-#define NVIC_MPU_ATTR_SIZE_512M 0x00000038 // Region size 512 Mbytes
-#define NVIC_MPU_ATTR_SIZE_1G 0x0000003A // Region size 1 Gbytes
-#define NVIC_MPU_ATTR_SIZE_2G 0x0000003C // Region size 2 Gbytes
-#define NVIC_MPU_ATTR_SIZE_4G 0x0000003E // Region size 4 Gbytes
-#define NVIC_MPU_ATTR_ENABLE 0x00000001 // Region enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_DBG_CTRL register.
-//
-//*****************************************************************************
-#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask
-#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key
-#define NVIC_DBG_CTRL_S_RESET_ST \
- 0x02000000 // Core has reset since last read
-#define NVIC_DBG_CTRL_S_RETIRE_ST \
- 0x01000000 // Core has executed insruction
- // since last read
-#define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 // Core is locked up
-#define NVIC_DBG_CTRL_S_SLEEP 0x00040000 // Core is sleeping
-#define NVIC_DBG_CTRL_S_HALT 0x00020000 // Core status on halt
-#define NVIC_DBG_CTRL_S_REGRDY 0x00010000 // Register read/write available
-#define NVIC_DBG_CTRL_C_SNAPSTALL \
- 0x00000020 // Breaks a stalled load/store
-#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping
-#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core
-#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core
-#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_DBG_XFER register.
-//
-//*****************************************************************************
-#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read
-#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register
-#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask
-#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP
-#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP
-#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP
-#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register
-#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15
-#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14
-#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13
-#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12
-#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11
-#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10
-#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9
-#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8
-#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7
-#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6
-#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5
-#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4
-#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3
-#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2
-#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1
-#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_DBG_DATA register.
-//
-//*****************************************************************************
-#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache
-#define NVIC_DBG_DATA_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_DBG_INT register.
-//
-//*****************************************************************************
-#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault
-#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors
-#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error
-#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state
-#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check
-#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error
-#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault
-#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status
-#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset
-#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending
-#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_SW_TRIG register.
-//
-//*****************************************************************************
-#define NVIC_SW_TRIG_INTID_M 0x000003FF // Interrupt to trigger
-#define NVIC_SW_TRIG_INTID_S 0
-
-#endif // __HW_NVIC_H__
+//*****************************************************************************
+//
+// hw_nvic.h - Macros used when accessing the NVIC hardware.
+//
+// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4781 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_NVIC_H__
+#define __HW_NVIC_H__
+
+//*****************************************************************************
+//
+// The following are defines for the NVIC register addresses.
+//
+//*****************************************************************************
+#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg.
+#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status Reg.
+#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register
+#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register
+#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg.
+#define NVIC_EN0 0xE000E100 // IRQ 0 to 31 Set Enable Register
+#define NVIC_EN1 0xE000E104 // IRQ 32 to 63 Set Enable Register
+#define NVIC_DIS0 0xE000E180 // IRQ 0 to 31 Clear Enable Reg.
+#define NVIC_DIS1 0xE000E184 // IRQ 32 to 63 Clear Enable Reg.
+#define NVIC_PEND0 0xE000E200 // IRQ 0 to 31 Set Pending Register
+#define NVIC_PEND1 0xE000E204 // IRQ 32 to 63 Set Pending Reg.
+#define NVIC_UNPEND0 0xE000E280 // IRQ 0 to 31 Clear Pending Reg.
+#define NVIC_UNPEND1 0xE000E284 // IRQ 32 to 63 Clear Pending Reg.
+#define NVIC_ACTIVE0 0xE000E300 // IRQ 0 to 31 Active Register
+#define NVIC_ACTIVE1 0xE000E304 // IRQ 32 to 63 Active Register
+#define NVIC_PRI0 0xE000E400 // IRQ 0 to 3 Priority Register
+#define NVIC_PRI1 0xE000E404 // IRQ 4 to 7 Priority Register
+#define NVIC_PRI2 0xE000E408 // IRQ 8 to 11 Priority Register
+#define NVIC_PRI3 0xE000E40C // IRQ 12 to 15 Priority Register
+#define NVIC_PRI4 0xE000E410 // IRQ 16 to 19 Priority Register
+#define NVIC_PRI5 0xE000E414 // IRQ 20 to 23 Priority Register
+#define NVIC_PRI6 0xE000E418 // IRQ 24 to 27 Priority Register
+#define NVIC_PRI7 0xE000E41C // IRQ 28 to 31 Priority Register
+#define NVIC_PRI8 0xE000E420 // IRQ 32 to 35 Priority Register
+#define NVIC_PRI9 0xE000E424 // IRQ 36 to 39 Priority Register
+#define NVIC_PRI10 0xE000E428 // IRQ 40 to 43 Priority Register
+#define NVIC_PRI11 0xE000E42C // IRQ 44 to 47 Priority Register
+#define NVIC_PRI12 0xE000E430 // IRQ 48 to 51 Priority Register
+#define NVIC_PRI13 0xE000E434 // IRQ 52 to 55 Priority Register
+#define NVIC_CPUID 0xE000ED00 // CPUID Base Register
+#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control State Register
+#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset Register
+#define NVIC_APINT 0xE000ED0C // App. Int & Reset Control Reg.
+#define NVIC_SYS_CTRL 0xE000ED10 // System Control Register
+#define NVIC_CFG_CTRL 0xE000ED14 // Configuration Control Register
+#define NVIC_SYS_PRI1 0xE000ED18 // Sys. Handlers 4 to 7 Priority
+#define NVIC_SYS_PRI2 0xE000ED1C // Sys. Handlers 8 to 11 Priority
+#define NVIC_SYS_PRI3 0xE000ED20 // Sys. Handlers 12 to 15 Priority
+#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State
+#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status Reg.
+#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status Register
+#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register
+#define NVIC_MM_ADDR 0xE000ED34 // Mem Manage Address Register
+#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address Register
+#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type Register
+#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control Register
+#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number Register
+#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address Register
+#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute & Size Reg.
+#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg.
+#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select
+#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data
+#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control
+#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt Reg.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_INT_TYPE register.
+//
+//*****************************************************************************
+#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32)
+#define NVIC_INT_TYPE_LINES_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_ST_CTRL_COUNT 0x00010000 // Count flag
+#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source
+#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt enable
+#define NVIC_ST_CTRL_ENABLE 0x00000001 // Counter mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_RELOAD register.
+//
+//*****************************************************************************
+#define NVIC_ST_RELOAD_M 0x00FFFFFF // Counter load value
+#define NVIC_ST_RELOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_CURRENT
+// register.
+//
+//*****************************************************************************
+#define NVIC_ST_CURRENT_M 0x00FFFFFF // Counter current value
+#define NVIC_ST_CURRENT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_CAL register.
+//
+//*****************************************************************************
+#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock
+#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew
+#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value
+#define NVIC_ST_CAL_ONEMS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN0 register.
+//
+//*****************************************************************************
+#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable
+#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable
+#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable
+#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable
+#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable
+#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable
+#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable
+#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable
+#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable
+#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable
+#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable
+#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable
+#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable
+#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable
+#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable
+#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable
+#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable
+#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable
+#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable
+#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable
+#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable
+#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable
+#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable
+#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable
+#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable
+#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable
+#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable
+#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable
+#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable
+#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable
+#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable
+#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN1 register.
+//
+//*****************************************************************************
+#define NVIC_EN1_INT59 0x08000000 // Interrupt 59 enable
+#define NVIC_EN1_INT58 0x04000000 // Interrupt 58 enable
+#define NVIC_EN1_INT57 0x02000000 // Interrupt 57 enable
+#define NVIC_EN1_INT56 0x01000000 // Interrupt 56 enable
+#define NVIC_EN1_INT55 0x00800000 // Interrupt 55 enable
+#define NVIC_EN1_INT54 0x00400000 // Interrupt 54 enable
+#define NVIC_EN1_INT53 0x00200000 // Interrupt 53 enable
+#define NVIC_EN1_INT52 0x00100000 // Interrupt 52 enable
+#define NVIC_EN1_INT51 0x00080000 // Interrupt 51 enable
+#define NVIC_EN1_INT50 0x00040000 // Interrupt 50 enable
+#define NVIC_EN1_INT49 0x00020000 // Interrupt 49 enable
+#define NVIC_EN1_INT48 0x00010000 // Interrupt 48 enable
+#define NVIC_EN1_INT47 0x00008000 // Interrupt 47 enable
+#define NVIC_EN1_INT46 0x00004000 // Interrupt 46 enable
+#define NVIC_EN1_INT45 0x00002000 // Interrupt 45 enable
+#define NVIC_EN1_INT44 0x00001000 // Interrupt 44 enable
+#define NVIC_EN1_INT43 0x00000800 // Interrupt 43 enable
+#define NVIC_EN1_INT42 0x00000400 // Interrupt 42 enable
+#define NVIC_EN1_INT41 0x00000200 // Interrupt 41 enable
+#define NVIC_EN1_INT40 0x00000100 // Interrupt 40 enable
+#define NVIC_EN1_INT39 0x00000080 // Interrupt 39 enable
+#define NVIC_EN1_INT38 0x00000040 // Interrupt 38 enable
+#define NVIC_EN1_INT37 0x00000020 // Interrupt 37 enable
+#define NVIC_EN1_INT36 0x00000010 // Interrupt 36 enable
+#define NVIC_EN1_INT35 0x00000008 // Interrupt 35 enable
+#define NVIC_EN1_INT34 0x00000004 // Interrupt 34 enable
+#define NVIC_EN1_INT33 0x00000002 // Interrupt 33 enable
+#define NVIC_EN1_INT32 0x00000001 // Interrupt 32 enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS0 register.
+//
+//*****************************************************************************
+#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable
+#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable
+#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable
+#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable
+#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable
+#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable
+#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable
+#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable
+#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable
+#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable
+#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable
+#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable
+#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable
+#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable
+#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable
+#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable
+#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable
+#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable
+#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable
+#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable
+#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable
+#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable
+#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable
+#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable
+#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable
+#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable
+#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable
+#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable
+#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable
+#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable
+#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable
+#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS1 register.
+//
+//*****************************************************************************
+#define NVIC_DIS1_INT59 0x08000000 // Interrupt 59 disable
+#define NVIC_DIS1_INT58 0x04000000 // Interrupt 58 disable
+#define NVIC_DIS1_INT57 0x02000000 // Interrupt 57 disable
+#define NVIC_DIS1_INT56 0x01000000 // Interrupt 56 disable
+#define NVIC_DIS1_INT55 0x00800000 // Interrupt 55 disable
+#define NVIC_DIS1_INT54 0x00400000 // Interrupt 54 disable
+#define NVIC_DIS1_INT53 0x00200000 // Interrupt 53 disable
+#define NVIC_DIS1_INT52 0x00100000 // Interrupt 52 disable
+#define NVIC_DIS1_INT51 0x00080000 // Interrupt 51 disable
+#define NVIC_DIS1_INT50 0x00040000 // Interrupt 50 disable
+#define NVIC_DIS1_INT49 0x00020000 // Interrupt 49 disable
+#define NVIC_DIS1_INT48 0x00010000 // Interrupt 48 disable
+#define NVIC_DIS1_INT47 0x00008000 // Interrupt 47 disable
+#define NVIC_DIS1_INT46 0x00004000 // Interrupt 46 disable
+#define NVIC_DIS1_INT45 0x00002000 // Interrupt 45 disable
+#define NVIC_DIS1_INT44 0x00001000 // Interrupt 44 disable
+#define NVIC_DIS1_INT43 0x00000800 // Interrupt 43 disable
+#define NVIC_DIS1_INT42 0x00000400 // Interrupt 42 disable
+#define NVIC_DIS1_INT41 0x00000200 // Interrupt 41 disable
+#define NVIC_DIS1_INT40 0x00000100 // Interrupt 40 disable
+#define NVIC_DIS1_INT39 0x00000080 // Interrupt 39 disable
+#define NVIC_DIS1_INT38 0x00000040 // Interrupt 38 disable
+#define NVIC_DIS1_INT37 0x00000020 // Interrupt 37 disable
+#define NVIC_DIS1_INT36 0x00000010 // Interrupt 36 disable
+#define NVIC_DIS1_INT35 0x00000008 // Interrupt 35 disable
+#define NVIC_DIS1_INT34 0x00000004 // Interrupt 34 disable
+#define NVIC_DIS1_INT33 0x00000002 // Interrupt 33 disable
+#define NVIC_DIS1_INT32 0x00000001 // Interrupt 32 disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND0 register.
+//
+//*****************************************************************************
+#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend
+#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend
+#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend
+#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend
+#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend
+#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend
+#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend
+#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend
+#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend
+#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend
+#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend
+#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend
+#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend
+#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend
+#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend
+#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend
+#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend
+#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend
+#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend
+#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend
+#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend
+#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend
+#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend
+#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend
+#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend
+#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend
+#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend
+#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend
+#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend
+#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend
+#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend
+#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND1 register.
+//
+//*****************************************************************************
+#define NVIC_PEND1_INT59 0x08000000 // Interrupt 59 pend
+#define NVIC_PEND1_INT58 0x04000000 // Interrupt 58 pend
+#define NVIC_PEND1_INT57 0x02000000 // Interrupt 57 pend
+#define NVIC_PEND1_INT56 0x01000000 // Interrupt 56 pend
+#define NVIC_PEND1_INT55 0x00800000 // Interrupt 55 pend
+#define NVIC_PEND1_INT54 0x00400000 // Interrupt 54 pend
+#define NVIC_PEND1_INT53 0x00200000 // Interrupt 53 pend
+#define NVIC_PEND1_INT52 0x00100000 // Interrupt 52 pend
+#define NVIC_PEND1_INT51 0x00080000 // Interrupt 51 pend
+#define NVIC_PEND1_INT50 0x00040000 // Interrupt 50 pend
+#define NVIC_PEND1_INT49 0x00020000 // Interrupt 49 pend
+#define NVIC_PEND1_INT48 0x00010000 // Interrupt 48 pend
+#define NVIC_PEND1_INT47 0x00008000 // Interrupt 47 pend
+#define NVIC_PEND1_INT46 0x00004000 // Interrupt 46 pend
+#define NVIC_PEND1_INT45 0x00002000 // Interrupt 45 pend
+#define NVIC_PEND1_INT44 0x00001000 // Interrupt 44 pend
+#define NVIC_PEND1_INT43 0x00000800 // Interrupt 43 pend
+#define NVIC_PEND1_INT42 0x00000400 // Interrupt 42 pend
+#define NVIC_PEND1_INT41 0x00000200 // Interrupt 41 pend
+#define NVIC_PEND1_INT40 0x00000100 // Interrupt 40 pend
+#define NVIC_PEND1_INT39 0x00000080 // Interrupt 39 pend
+#define NVIC_PEND1_INT38 0x00000040 // Interrupt 38 pend
+#define NVIC_PEND1_INT37 0x00000020 // Interrupt 37 pend
+#define NVIC_PEND1_INT36 0x00000010 // Interrupt 36 pend
+#define NVIC_PEND1_INT35 0x00000008 // Interrupt 35 pend
+#define NVIC_PEND1_INT34 0x00000004 // Interrupt 34 pend
+#define NVIC_PEND1_INT33 0x00000002 // Interrupt 33 pend
+#define NVIC_PEND1_INT32 0x00000001 // Interrupt 32 pend
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND0 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend
+#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend
+#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend
+#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend
+#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend
+#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend
+#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend
+#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend
+#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend
+#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend
+#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend
+#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend
+#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend
+#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend
+#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend
+#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend
+#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend
+#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend
+#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend
+#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend
+#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend
+#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend
+#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend
+#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend
+#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend
+#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend
+#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend
+#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend
+#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend
+#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend
+#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend
+#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND1 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND1_INT59 0x08000000 // Interrupt 59 unpend
+#define NVIC_UNPEND1_INT58 0x04000000 // Interrupt 58 unpend
+#define NVIC_UNPEND1_INT57 0x02000000 // Interrupt 57 unpend
+#define NVIC_UNPEND1_INT56 0x01000000 // Interrupt 56 unpend
+#define NVIC_UNPEND1_INT55 0x00800000 // Interrupt 55 unpend
+#define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend
+#define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend
+#define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend
+#define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend
+#define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend
+#define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend
+#define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend
+#define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend
+#define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend
+#define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend
+#define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend
+#define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend
+#define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend
+#define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend
+#define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend
+#define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend
+#define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend
+#define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend
+#define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend
+#define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend
+#define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend
+#define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend
+#define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE0 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active
+#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active
+#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active
+#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active
+#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active
+#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active
+#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active
+#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active
+#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active
+#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active
+#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active
+#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active
+#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active
+#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active
+#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active
+#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active
+#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active
+#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active
+#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active
+#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active
+#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active
+#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active
+#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active
+#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active
+#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active
+#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active
+#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active
+#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active
+#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active
+#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active
+#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active
+#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE1 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE1_INT59 0x08000000 // Interrupt 59 active
+#define NVIC_ACTIVE1_INT58 0x04000000 // Interrupt 58 active
+#define NVIC_ACTIVE1_INT57 0x02000000 // Interrupt 57 active
+#define NVIC_ACTIVE1_INT56 0x01000000 // Interrupt 56 active
+#define NVIC_ACTIVE1_INT55 0x00800000 // Interrupt 55 active
+#define NVIC_ACTIVE1_INT54 0x00400000 // Interrupt 54 active
+#define NVIC_ACTIVE1_INT53 0x00200000 // Interrupt 53 active
+#define NVIC_ACTIVE1_INT52 0x00100000 // Interrupt 52 active
+#define NVIC_ACTIVE1_INT51 0x00080000 // Interrupt 51 active
+#define NVIC_ACTIVE1_INT50 0x00040000 // Interrupt 50 active
+#define NVIC_ACTIVE1_INT49 0x00020000 // Interrupt 49 active
+#define NVIC_ACTIVE1_INT48 0x00010000 // Interrupt 48 active
+#define NVIC_ACTIVE1_INT47 0x00008000 // Interrupt 47 active
+#define NVIC_ACTIVE1_INT46 0x00004000 // Interrupt 46 active
+#define NVIC_ACTIVE1_INT45 0x00002000 // Interrupt 45 active
+#define NVIC_ACTIVE1_INT44 0x00001000 // Interrupt 44 active
+#define NVIC_ACTIVE1_INT43 0x00000800 // Interrupt 43 active
+#define NVIC_ACTIVE1_INT42 0x00000400 // Interrupt 42 active
+#define NVIC_ACTIVE1_INT41 0x00000200 // Interrupt 41 active
+#define NVIC_ACTIVE1_INT40 0x00000100 // Interrupt 40 active
+#define NVIC_ACTIVE1_INT39 0x00000080 // Interrupt 39 active
+#define NVIC_ACTIVE1_INT38 0x00000040 // Interrupt 38 active
+#define NVIC_ACTIVE1_INT37 0x00000020 // Interrupt 37 active
+#define NVIC_ACTIVE1_INT36 0x00000010 // Interrupt 36 active
+#define NVIC_ACTIVE1_INT35 0x00000008 // Interrupt 35 active
+#define NVIC_ACTIVE1_INT34 0x00000004 // Interrupt 34 active
+#define NVIC_ACTIVE1_INT33 0x00000002 // Interrupt 33 active
+#define NVIC_ACTIVE1_INT32 0x00000001 // Interrupt 32 active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI0 register.
+//
+//*****************************************************************************
+#define NVIC_PRI0_INT3_M 0xFF000000 // Interrupt 3 priority mask
+#define NVIC_PRI0_INT2_M 0x00FF0000 // Interrupt 2 priority mask
+#define NVIC_PRI0_INT1_M 0x0000FF00 // Interrupt 1 priority mask
+#define NVIC_PRI0_INT0_M 0x000000FF // Interrupt 0 priority mask
+#define NVIC_PRI0_INT3_S 24
+#define NVIC_PRI0_INT2_S 16
+#define NVIC_PRI0_INT1_S 8
+#define NVIC_PRI0_INT0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI1 register.
+//
+//*****************************************************************************
+#define NVIC_PRI1_INT7_M 0xFF000000 // Interrupt 7 priority mask
+#define NVIC_PRI1_INT6_M 0x00FF0000 // Interrupt 6 priority mask
+#define NVIC_PRI1_INT5_M 0x0000FF00 // Interrupt 5 priority mask
+#define NVIC_PRI1_INT4_M 0x000000FF // Interrupt 4 priority mask
+#define NVIC_PRI1_INT7_S 24
+#define NVIC_PRI1_INT6_S 16
+#define NVIC_PRI1_INT5_S 8
+#define NVIC_PRI1_INT4_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI2 register.
+//
+//*****************************************************************************
+#define NVIC_PRI2_INT11_M 0xFF000000 // Interrupt 11 priority mask
+#define NVIC_PRI2_INT10_M 0x00FF0000 // Interrupt 10 priority mask
+#define NVIC_PRI2_INT9_M 0x0000FF00 // Interrupt 9 priority mask
+#define NVIC_PRI2_INT8_M 0x000000FF // Interrupt 8 priority mask
+#define NVIC_PRI2_INT11_S 24
+#define NVIC_PRI2_INT10_S 16
+#define NVIC_PRI2_INT9_S 8
+#define NVIC_PRI2_INT8_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI3 register.
+//
+//*****************************************************************************
+#define NVIC_PRI3_INT15_M 0xFF000000 // Interrupt 15 priority mask
+#define NVIC_PRI3_INT14_M 0x00FF0000 // Interrupt 14 priority mask
+#define NVIC_PRI3_INT13_M 0x0000FF00 // Interrupt 13 priority mask
+#define NVIC_PRI3_INT12_M 0x000000FF // Interrupt 12 priority mask
+#define NVIC_PRI3_INT15_S 24
+#define NVIC_PRI3_INT14_S 16
+#define NVIC_PRI3_INT13_S 8
+#define NVIC_PRI3_INT12_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI4 register.
+//
+//*****************************************************************************
+#define NVIC_PRI4_INT19_M 0xFF000000 // Interrupt 19 priority mask
+#define NVIC_PRI4_INT18_M 0x00FF0000 // Interrupt 18 priority mask
+#define NVIC_PRI4_INT17_M 0x0000FF00 // Interrupt 17 priority mask
+#define NVIC_PRI4_INT16_M 0x000000FF // Interrupt 16 priority mask
+#define NVIC_PRI4_INT19_S 24
+#define NVIC_PRI4_INT18_S 16
+#define NVIC_PRI4_INT17_S 8
+#define NVIC_PRI4_INT16_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI5 register.
+//
+//*****************************************************************************
+#define NVIC_PRI5_INT23_M 0xFF000000 // Interrupt 23 priority mask
+#define NVIC_PRI5_INT22_M 0x00FF0000 // Interrupt 22 priority mask
+#define NVIC_PRI5_INT21_M 0x0000FF00 // Interrupt 21 priority mask
+#define NVIC_PRI5_INT20_M 0x000000FF // Interrupt 20 priority mask
+#define NVIC_PRI5_INT23_S 24
+#define NVIC_PRI5_INT22_S 16
+#define NVIC_PRI5_INT21_S 8
+#define NVIC_PRI5_INT20_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI6 register.
+//
+//*****************************************************************************
+#define NVIC_PRI6_INT27_M 0xFF000000 // Interrupt 27 priority mask
+#define NVIC_PRI6_INT26_M 0x00FF0000 // Interrupt 26 priority mask
+#define NVIC_PRI6_INT25_M 0x0000FF00 // Interrupt 25 priority mask
+#define NVIC_PRI6_INT24_M 0x000000FF // Interrupt 24 priority mask
+#define NVIC_PRI6_INT27_S 24
+#define NVIC_PRI6_INT26_S 16
+#define NVIC_PRI6_INT25_S 8
+#define NVIC_PRI6_INT24_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI7 register.
+//
+//*****************************************************************************
+#define NVIC_PRI7_INT31_M 0xFF000000 // Interrupt 31 priority mask
+#define NVIC_PRI7_INT30_M 0x00FF0000 // Interrupt 30 priority mask
+#define NVIC_PRI7_INT29_M 0x0000FF00 // Interrupt 29 priority mask
+#define NVIC_PRI7_INT28_M 0x000000FF // Interrupt 28 priority mask
+#define NVIC_PRI7_INT31_S 24
+#define NVIC_PRI7_INT30_S 16
+#define NVIC_PRI7_INT29_S 8
+#define NVIC_PRI7_INT28_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI8 register.
+//
+//*****************************************************************************
+#define NVIC_PRI8_INT35_M 0xFF000000 // Interrupt 35 priority mask
+#define NVIC_PRI8_INT34_M 0x00FF0000 // Interrupt 34 priority mask
+#define NVIC_PRI8_INT33_M 0x0000FF00 // Interrupt 33 priority mask
+#define NVIC_PRI8_INT32_M 0x000000FF // Interrupt 32 priority mask
+#define NVIC_PRI8_INT35_S 24
+#define NVIC_PRI8_INT34_S 16
+#define NVIC_PRI8_INT33_S 8
+#define NVIC_PRI8_INT32_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI9 register.
+//
+//*****************************************************************************
+#define NVIC_PRI9_INT39_M 0xFF000000 // Interrupt 39 priority mask
+#define NVIC_PRI9_INT38_M 0x00FF0000 // Interrupt 38 priority mask
+#define NVIC_PRI9_INT37_M 0x0000FF00 // Interrupt 37 priority mask
+#define NVIC_PRI9_INT36_M 0x000000FF // Interrupt 36 priority mask
+#define NVIC_PRI9_INT39_S 24
+#define NVIC_PRI9_INT38_S 16
+#define NVIC_PRI9_INT37_S 8
+#define NVIC_PRI9_INT36_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI10 register.
+//
+//*****************************************************************************
+#define NVIC_PRI10_INT43_M 0xFF000000 // Interrupt 43 priority mask
+#define NVIC_PRI10_INT42_M 0x00FF0000 // Interrupt 42 priority mask
+#define NVIC_PRI10_INT41_M 0x0000FF00 // Interrupt 41 priority mask
+#define NVIC_PRI10_INT40_M 0x000000FF // Interrupt 40 priority mask
+#define NVIC_PRI10_INT43_S 24
+#define NVIC_PRI10_INT42_S 16
+#define NVIC_PRI10_INT41_S 8
+#define NVIC_PRI10_INT40_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_CPUID register.
+//
+//*****************************************************************************
+#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer
+#define NVIC_CPUID_VAR_M 0x00F00000 // Variant
+#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Processor part number
+#define NVIC_CPUID_REV_M 0x0000000F // Revision
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_INT_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_INT_CTRL_NMI_SET 0x80000000 // Pend a NMI
+#define NVIC_INT_CTRL_PEND_SV 0x10000000 // Pend a PendSV
+#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // Unpend a PendSV
+#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug interrupt handling
+#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Debug interrupt pending
+#define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000 // Highest pending exception
+#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to base
+#define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF // Current active exception
+#define NVIC_INT_CTRL_VEC_PEN_S 12
+#define NVIC_INT_CTRL_VEC_ACT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_VTABLE register.
+//
+//*****************************************************************************
+#define NVIC_VTABLE_BASE 0x20000000 // Vector table base
+#define NVIC_VTABLE_OFFSET_M 0x1FFFFF00 // Vector table offset
+#define NVIC_VTABLE_OFFSET_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_APINT register.
+//
+//*****************************************************************************
+#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Vector key mask
+#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key
+#define NVIC_APINT_ENDIANESS 0x00008000 // Data endianess
+#define NVIC_APINT_PRIGROUP_M 0x00000700 // Priority group
+#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split
+#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split
+#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split
+#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split
+#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split
+#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split
+#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split
+#define NVIC_APINT_SYSRESETREQ 0x00000004 // System reset request
+#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear active NMI/fault info
+#define NVIC_APINT_VECT_RESET 0x00000001 // System reset
+#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wakeup on pend
+#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep sleep enable
+#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR exit
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_CFG_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore bus fault in NMI/fault
+#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on divide by 0
+#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on unaligned access
+#define NVIC_CFG_CTRL_DEEP_PEND 0x00000004 // Allow deep interrupt trigger
+#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow main interrupt trigger
+#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread state control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_PRI1 register.
+//
+//*****************************************************************************
+#define NVIC_SYS_PRI1_RES_M 0xFF000000 // Priority of reserved handler
+#define NVIC_SYS_PRI1_USAGE_M 0x00FF0000 // Priority of usage fault handler
+#define NVIC_SYS_PRI1_BUS_M 0x0000FF00 // Priority of bus fault handler
+#define NVIC_SYS_PRI1_MEM_M 0x000000FF // Priority of mem manage handler
+#define NVIC_SYS_PRI1_USAGE_S 16
+#define NVIC_SYS_PRI1_BUS_S 8
+#define NVIC_SYS_PRI1_MEM_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_PRI2 register.
+//
+//*****************************************************************************
+#define NVIC_SYS_PRI2_SVC_M 0xFF000000 // Priority of SVCall handler
+#define NVIC_SYS_PRI2_RES_M 0x00FFFFFF // Priority of reserved handlers
+#define NVIC_SYS_PRI2_SVC_S 24
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_PRI3 register.
+//
+//*****************************************************************************
+#define NVIC_SYS_PRI3_TICK_M 0xFF000000 // Priority of Sys Tick handler
+#define NVIC_SYS_PRI3_PENDSV_M 0x00FF0000 // Priority of PendSV handler
+#define NVIC_SYS_PRI3_RES_M 0x0000FF00 // Priority of reserved handler
+#define NVIC_SYS_PRI3_DEBUG_M 0x000000FF // Priority of debug handler
+#define NVIC_SYS_PRI3_TICK_S 24
+#define NVIC_SYS_PRI3_PENDSV_S 16
+#define NVIC_SYS_PRI3_DEBUG_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_HND_CTRL
+// register.
+//
+//*****************************************************************************
+#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage fault enable
+#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus fault enable
+#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Mem manage fault enable
+#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVCall is pended
+#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus fault is pended
+#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // Sys tick is active
+#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV is active
+#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Monitor is active
+#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVCall is active
+#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage fault is active
+#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus fault is active
+#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Mem manage is active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FAULT_STAT
+// register.
+//
+//*****************************************************************************
+#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide by zero fault
+#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned access fault
+#define NVIC_FAULT_STAT_NOCP 0x00080000 // No coprocessor fault
+#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC fault
+#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid state fault
+#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined instruction fault
+#define NVIC_FAULT_STAT_BFARV 0x00008000 // BFAR is valid
+#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack bus fault
+#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack bus fault
+#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise data bus error
+#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise data bus error
+#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction bus fault
+#define NVIC_FAULT_STAT_MMARV 0x00000080 // MMAR is valid
+#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack access violation
+#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack access violation
+#define NVIC_FAULT_STAT_DERR 0x00000002 // Data access violation
+#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction access violation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_HFAULT_STAT
+// register.
+//
+//*****************************************************************************
+#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug event
+#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Cannot execute fault handler
+#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector table read fault
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DEBUG_STAT
+// register.
+//
+//*****************************************************************************
+#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted
+#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch
+#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match
+#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction
+#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MM_ADDR register.
+//
+//*****************************************************************************
+#define NVIC_MM_ADDR_M 0xFFFFFFFF // Data fault address
+#define NVIC_MM_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FAULT_ADDR
+// register.
+//
+//*****************************************************************************
+#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Data bus fault address
+#define NVIC_FAULT_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_TYPE register.
+//
+//*****************************************************************************
+#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I regions
+#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D regions
+#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or unified MPU
+#define NVIC_MPU_TYPE_IREGION_S 16
+#define NVIC_MPU_TYPE_DREGION_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004 // MPU default region in priv mode
+#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU enabled during faults
+#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_NUMBER
+// register.
+//
+//*****************************************************************************
+#define NVIC_MPU_NUMBER_M 0x000000FF // MPU region to access
+#define NVIC_MPU_NUMBER_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE_ADDR_M 0xFFFFFFE0 // Base address mask
+#define NVIC_MPU_BASE_VALID 0x00000010 // Region number valid
+#define NVIC_MPU_BASE_REGION_M 0x0000000F // Region number
+#define NVIC_MPU_BASE_ADDR_S 8
+#define NVIC_MPU_BASE_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR_M 0xFFFF0000 // Attributes
+#define NVIC_MPU_ATTR_AP_NO_NO 0x00000000 // prv: no access, usr: no access
+#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000 // Bufferable
+#define NVIC_MPU_ATTR_CACHEABLE 0x00020000 // Cacheable
+#define NVIC_MPU_ATTR_SHAREABLE 0x00040000 // Shareable
+#define NVIC_MPU_ATTR_TEX_M 0x00380000 // Type extension mask
+#define NVIC_MPU_ATTR_AP_RW_NO 0x01000000 // prv: rw, usr: none
+#define NVIC_MPU_ATTR_AP_RW_RO 0x02000000 // prv: rw, usr: read-only
+#define NVIC_MPU_ATTR_AP_RW_RW 0x03000000 // prv: rw, usr: rw
+#define NVIC_MPU_ATTR_AP_RO_NO 0x05000000 // prv: ro, usr: none
+#define NVIC_MPU_ATTR_AP_RO_RO 0x06000000 // prv: ro, usr: ro
+#define NVIC_MPU_ATTR_AP_M 0x07000000 // Access permissions mask
+#define NVIC_MPU_ATTR_XN 0x10000000 // Execute disable
+#define NVIC_MPU_ATTR_SRD_M 0x0000FF00 // Sub-region disable mask
+#define NVIC_MPU_ATTR_SRD_0 0x00000100 // Sub-region 0 disable
+#define NVIC_MPU_ATTR_SRD_1 0x00000200 // Sub-region 1 disable
+#define NVIC_MPU_ATTR_SRD_2 0x00000400 // Sub-region 2 disable
+#define NVIC_MPU_ATTR_SRD_3 0x00000800 // Sub-region 3 disable
+#define NVIC_MPU_ATTR_SRD_4 0x00001000 // Sub-region 4 disable
+#define NVIC_MPU_ATTR_SRD_5 0x00002000 // Sub-region 5 disable
+#define NVIC_MPU_ATTR_SRD_6 0x00004000 // Sub-region 6 disable
+#define NVIC_MPU_ATTR_SRD_7 0x00008000 // Sub-region 7 disable
+#define NVIC_MPU_ATTR_SIZE_M 0x0000003E // Region size mask
+#define NVIC_MPU_ATTR_SIZE_32B 0x00000008 // Region size 32 bytes
+#define NVIC_MPU_ATTR_SIZE_64B 0x0000000A // Region size 64 bytes
+#define NVIC_MPU_ATTR_SIZE_128B 0x0000000C // Region size 128 bytes
+#define NVIC_MPU_ATTR_SIZE_256B 0x0000000E // Region size 256 bytes
+#define NVIC_MPU_ATTR_SIZE_512B 0x00000010 // Region size 512 bytes
+#define NVIC_MPU_ATTR_SIZE_1K 0x00000012 // Region size 1 Kbytes
+#define NVIC_MPU_ATTR_SIZE_2K 0x00000014 // Region size 2 Kbytes
+#define NVIC_MPU_ATTR_SIZE_4K 0x00000016 // Region size 4 Kbytes
+#define NVIC_MPU_ATTR_SIZE_8K 0x00000018 // Region size 8 Kbytes
+#define NVIC_MPU_ATTR_SIZE_16K 0x0000001A // Region size 16 Kbytes
+#define NVIC_MPU_ATTR_SIZE_32K 0x0000001C // Region size 32 Kbytes
+#define NVIC_MPU_ATTR_SIZE_64K 0x0000001E // Region size 64 Kbytes
+#define NVIC_MPU_ATTR_SIZE_128K 0x00000020 // Region size 128 Kbytes
+#define NVIC_MPU_ATTR_SIZE_256K 0x00000022 // Region size 256 Kbytes
+#define NVIC_MPU_ATTR_SIZE_512K 0x00000024 // Region size 512 Kbytes
+#define NVIC_MPU_ATTR_SIZE_1M 0x00000026 // Region size 1 Mbytes
+#define NVIC_MPU_ATTR_SIZE_2M 0x00000028 // Region size 2 Mbytes
+#define NVIC_MPU_ATTR_SIZE_4M 0x0000002A // Region size 4 Mbytes
+#define NVIC_MPU_ATTR_SIZE_8M 0x0000002C // Region size 8 Mbytes
+#define NVIC_MPU_ATTR_SIZE_16M 0x0000002E // Region size 16 Mbytes
+#define NVIC_MPU_ATTR_SIZE_32M 0x00000030 // Region size 32 Mbytes
+#define NVIC_MPU_ATTR_SIZE_64M 0x00000032 // Region size 64 Mbytes
+#define NVIC_MPU_ATTR_SIZE_128M 0x00000034 // Region size 128 Mbytes
+#define NVIC_MPU_ATTR_SIZE_256M 0x00000036 // Region size 256 Mbytes
+#define NVIC_MPU_ATTR_SIZE_512M 0x00000038 // Region size 512 Mbytes
+#define NVIC_MPU_ATTR_SIZE_1G 0x0000003A // Region size 1 Gbytes
+#define NVIC_MPU_ATTR_SIZE_2G 0x0000003C // Region size 2 Gbytes
+#define NVIC_MPU_ATTR_SIZE_4G 0x0000003E // Region size 4 Gbytes
+#define NVIC_MPU_ATTR_ENABLE 0x00000001 // Region enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask
+#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key
+#define NVIC_DBG_CTRL_S_RESET_ST \
+ 0x02000000 // Core has reset since last read
+#define NVIC_DBG_CTRL_S_RETIRE_ST \
+ 0x01000000 // Core has executed insruction
+ // since last read
+#define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 // Core is locked up
+#define NVIC_DBG_CTRL_S_SLEEP 0x00040000 // Core is sleeping
+#define NVIC_DBG_CTRL_S_HALT 0x00020000 // Core status on halt
+#define NVIC_DBG_CTRL_S_REGRDY 0x00010000 // Register read/write available
+#define NVIC_DBG_CTRL_C_SNAPSTALL \
+ 0x00000020 // Breaks a stalled load/store
+#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping
+#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core
+#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core
+#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_XFER register.
+//
+//*****************************************************************************
+#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read
+#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register
+#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask
+#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP
+#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP
+#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP
+#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register
+#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15
+#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14
+#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13
+#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12
+#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11
+#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10
+#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9
+#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8
+#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7
+#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6
+#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5
+#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4
+#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3
+#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2
+#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1
+#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_DATA register.
+//
+//*****************************************************************************
+#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache
+#define NVIC_DBG_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_INT register.
+//
+//*****************************************************************************
+#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault
+#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors
+#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error
+#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state
+#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check
+#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error
+#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault
+#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status
+#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset
+#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending
+#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SW_TRIG register.
+//
+//*****************************************************************************
+#define NVIC_SW_TRIG_INTID_M 0x000003FF // Interrupt to trigger
+#define NVIC_SW_TRIG_INTID_S 0
+
+#endif // __HW_NVIC_H__
Property changes on: branches/eagle_mmc/src/platform/lm3s/hw_nvic.h
___________________________________________________________________
Name: svn:executable
+ *
Modified: branches/eagle_mmc/src/platform/lm3s/hw_pwm.h
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/hw_pwm.h 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lm3s/hw_pwm.h 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,676 +1,716 @@
-//*****************************************************************************
-//
-// hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports
-//
-// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
-// Software License Agreement
-//
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
-//
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws. All rights are reserved. You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program. Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
-//
-// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-//
-// This is part of revision 3740 of the Stellaris Firmware Development Package.
-//
-//*****************************************************************************
-
-#ifndef __HW_PWM_H__
-#define __HW_PWM_H__
-
-//*****************************************************************************
-//
-// The following are defines for the PWM Module Register offsets.
-//
-//*****************************************************************************
-#define PWM_O_CTL 0x00000000 // PWM Master Control register
-#define PWM_O_SYNC 0x00000004 // PWM Time Base Sync register
-#define PWM_O_ENABLE 0x00000008 // PWM Output Enable register
-#define PWM_O_INVERT 0x0000000C // PWM Output Inversion register
-#define PWM_O_FAULT 0x00000010 // PWM Output Fault register
-#define PWM_O_INTEN 0x00000014 // PWM Interrupt Enable register
-#define PWM_O_RIS 0x00000018 // PWM Interrupt Raw Status reg.
-#define PWM_O_ISC 0x0000001C // PWM Interrupt Status register
-#define PWM_O_STATUS 0x00000020 // PWM Status register
-#define PWM_O_FAULTVAL 0x00000024 // PWM Fault Condition Value
-#define PWM_O_0_CTL 0x00000040 // PWM0 Control
-#define PWM_O_0_INTEN 0x00000044 // PWM0 Interrupt and Trigger
- // Enable
-#define PWM_O_0_RIS 0x00000048 // PWM0 Raw Interrupt Status
-#define PWM_O_0_ISC 0x0000004C // PWM0 Interrupt Status and Clear
-#define PWM_O_0_LOAD 0x00000050 // PWM0 Load
-#define PWM_O_0_COUNT 0x00000054 // PWM0 Counter
-#define PWM_O_0_CMPA 0x00000058 // PWM0 Compare A
-#define PWM_O_0_CMPB 0x0000005C // PWM0 Compare B
-#define PWM_O_0_GENA 0x00000060 // PWM0 Generator A Control
-#define PWM_O_0_GENB 0x00000064 // PWM0 Generator B Control
-#define PWM_O_0_DBCTL 0x00000068 // PWM0 Dead-Band Control
-#define PWM_O_0_DBRISE 0x0000006C // PWM0 Dead-Band Rising-Edge Delay
-#define PWM_O_0_DBFALL 0x00000070 // PWM0 Dead-Band
- // Falling-Edge-Delay
-#define PWM_O_0_FLTSRC0 0x00000074 // PWM0 Fault Source 0
-#define PWM_O_0_MINFLTPER 0x0000007C // PWM0 Minimum Fault Period
-#define PWM_O_1_CTL 0x00000080 // PWM1 Control
-#define PWM_O_1_INTEN 0x00000084 // PWM1 Interrupt Enable
-#define PWM_O_1_RIS 0x00000088 // PWM1 Raw Interrupt Status
-#define PWM_O_1_ISC 0x0000008C // PWM1 Interrupt Status and Clear
-#define PWM_O_1_LOAD 0x00000090 // PWM1 Load
-#define PWM_O_1_COUNT 0x00000094 // PWM1 Counter
-#define PWM_O_1_CMPA 0x00000098 // PWM1 Compare A
-#define PWM_O_1_CMPB 0x0000009C // PWM1 Compare B
-#define PWM_O_1_GENA 0x000000A0 // PWM1 Generator A Control
-#define PWM_O_1_GENB 0x000000A4 // PWM1 Generator B Control
-#define PWM_O_1_DBCTL 0x000000A8 // PWM1 Dead-Band Control
-#define PWM_O_1_DBRISE 0x000000AC // PWM1 Dead-Band Rising-Edge Delay
-#define PWM_O_1_DBFALL 0x000000B0 // PWM1 Dead-Band
- // Falling-Edge-Delay
-#define PWM_O_1_FLTSRC0 0x000000B4 // PWM1 Fault Source 0
-#define PWM_O_1_MINFLTPER 0x000000BC // PWM1 Minimum Fault Period
-#define PWM_O_2_CTL 0x000000C0 // PWM2 Control
-#define PWM_O_2_INTEN 0x000000C4 // PWM2 InterruptEnable
-#define PWM_O_2_RIS 0x000000C8 // PWM2 Raw Interrupt Status
-#define PWM_O_2_ISC 0x000000CC // PWM2 Interrupt Status and Clear
-#define PWM_O_2_LOAD 0x000000D0 // PWM2 Load
-#define PWM_O_2_COUNT 0x000000D4 // PWM2 Counter
-#define PWM_O_2_CMPA 0x000000D8 // PWM2 Compare A
-#define PWM_O_2_CMPB 0x000000DC // PWM2 Compare B
-#define PWM_O_2_GENA 0x000000E0 // PWM2 Generator A Control
-#define PWM_O_2_GENB 0x000000E4 // PWM2 Generator B Control
-#define PWM_O_2_DBCTL 0x000000E8 // PWM2 Dead-Band Control
-#define PWM_O_2_DBRISE 0x000000EC // PWM2 Dead-Band Rising-Edge Delay
-#define PWM_O_2_DBFALL 0x000000F0 // PWM2 Dead-Band
- // Falling-Edge-Delay
-#define PWM_O_2_FLTSRC0 0x000000F4 // PWM2 Fault Source 0
-#define PWM_O_2_MINFLTPER 0x000000FC // PWM2 Minimum Fault Period
-#define PWM_O_3_CTL 0x00000100 // PWM3 Control
-#define PWM_O_3_INTEN 0x00000104 // PWM3 Interrupt and Trigger
- // Enable
-#define PWM_O_3_RIS 0x00000108 // PWM3 Raw Interrupt Status
-#define PWM_O_3_ISC 0x0000010C // PWM3 Interrupt Status and Clear
-#define PWM_O_3_LOAD 0x00000110 // PWM3 Load
-#define PWM_O_3_COUNT 0x00000114 // PWM3 Counter
-#define PWM_O_3_CMPA 0x00000118 // PWM3 Compare A
-#define PWM_O_3_CMPB 0x0000011C // PWM3 Compare B
-#define PWM_O_3_GENA 0x00000120 // PWM3 Generator A Control
-#define PWM_O_3_GENB 0x00000124 // PWM3 Generator B Control
-#define PWM_O_3_DBCTL 0x00000128 // PWM3 Dead-Band Control
-#define PWM_O_3_DBRISE 0x0000012C // PWM3 Dead-Band Rising-Edge Delay
-#define PWM_O_3_DBFALL 0x00000130 // PWM3 Dead-Band
- // Falling-Edge-Delay
-#define PWM_O_3_FLTSRC0 0x00000134 // PWM3 Fault Source 0
-#define PWM_O_3_MINFLTPER 0x0000013C // PWM3 Minimum Fault Period
-#define PWM_O_0_FLTSEN 0x00000800 // PWM0 Fault Pin Logic Sense
-#define PWM_O_0_FLTSTAT0 0x00000804 // PWM0 Fault Status 0
-#define PWM_O_1_FLTSEN 0x00000880 // PWM1 Fault Pin Logic Sense
-#define PWM_O_1_FLTSTAT0 0x00000884 // PWM1 Fault Status 0
-#define PWM_O_2_FLTSEN 0x00000900 // PWM2 Fault Pin Logic Sense
-#define PWM_O_2_FLTSTAT0 0x00000904 // PWM2 Fault Status 0
-#define PWM_O_3_FLTSEN 0x00000980 // PWM3 Fault Pin Logic Sense
-#define PWM_O_3_FLTSTAT0 0x00000984 // PWM3 Fault Status 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the PWM Master Control
-// register.
-//
-//*****************************************************************************
-#define PWM_CTL_GLOBALSYNC3 0x00000008 // Update PWM Generator 3.
-#define PWM_CTL_GLOBALSYNC2 0x00000004 // Update PWM Generator 2.
-#define PWM_CTL_GLOBALSYNC1 0x00000002 // Update PWM Generator 1.
-#define PWM_CTL_GLOBALSYNC0 0x00000001 // Update PWM Generator 0.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the PWM Time Base Sync
-// register.
-//
-//*****************************************************************************
-#define PWM_SYNC_SYNC3 0x00000008 // Reset generator 3 counter
-#define PWM_SYNC_SYNC2 0x00000004 // Reset generator 2 counter
-#define PWM_SYNC_SYNC1 0x00000002 // Reset generator 1 counter
-#define PWM_SYNC_SYNC0 0x00000001 // Reset generator 0 counter
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the PWM Output Enable
-// register.
-//
-//*****************************************************************************
-#define PWM_ENABLE_PWM7EN 0x00000080 // PWM7 pin enable
-#define PWM_ENABLE_PWM6EN 0x00000040 // PWM6 pin enable
-#define PWM_ENABLE_PWM5EN 0x00000020 // PWM5 pin enable
-#define PWM_ENABLE_PWM4EN 0x00000010 // PWM4 pin enable
-#define PWM_ENABLE_PWM3EN 0x00000008 // PWM3 pin enable
-#define PWM_ENABLE_PWM2EN 0x00000004 // PWM2 pin enable
-#define PWM_ENABLE_PWM1EN 0x00000002 // PWM1 pin enable
-#define PWM_ENABLE_PWM0EN 0x00000001 // PWM0 pin enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the PWM Inversion register.
-//
-//*****************************************************************************
-#define PWM_INVERT_PWM7INV 0x00000080 // PWM7 pin invert
-#define PWM_INVERT_PWM6INV 0x00000040 // PWM6 pin invert
-#define PWM_INVERT_PWM5INV 0x00000020 // PWM5 pin invert
-#define PWM_INVERT_PWM4INV 0x00000010 // PWM4 pin invert
-#define PWM_INVERT_PWM3INV 0x00000008 // PWM3 pin invert
-#define PWM_INVERT_PWM2INV 0x00000004 // PWM2 pin invert
-#define PWM_INVERT_PWM1INV 0x00000002 // PWM1 pin invert
-#define PWM_INVERT_PWM0INV 0x00000001 // PWM0 pin invert
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the PWM Fault register.
-//
-//*****************************************************************************
-#define PWM_FAULT_FAULT7 0x00000080 // PWM7 pin fault
-#define PWM_FAULT_FAULT6 0x00000040 // PWM6 pin fault
-#define PWM_FAULT_FAULT5 0x00000020 // PWM5 pin fault
-#define PWM_FAULT_FAULT4 0x00000010 // PWM4 pin fault
-#define PWM_FAULT_FAULT3 0x00000008 // PWM3 pin fault
-#define PWM_FAULT_FAULT2 0x00000004 // PWM2 pin fault
-#define PWM_FAULT_FAULT1 0x00000002 // PWM1 pin fault
-#define PWM_FAULT_FAULT0 0x00000001 // PWM0 pin fault
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the PWM Status register.
-//
-//*****************************************************************************
-#define PWM_STATUS_FAULT3 0x00000008 // Fault3 Interrupt Status.
-#define PWM_STATUS_FAULT2 0x00000004 // Fault2 Interrupt Status.
-#define PWM_STATUS_FAULT1 0x00000002 // Fault1 Interrupt Status.
-#define PWM_STATUS_FAULT0 0x00000001 // Fault0 Interrupt Status.
-
-//*****************************************************************************
-//
-// The following are defines for the PWM Generator standard offsets.
-//
-//*****************************************************************************
-#define PWM_O_X_CTL 0x00000000 // Gen Control Reg
-#define PWM_O_X_INTEN 0x00000004 // Gen Int/Trig Enable Reg
-#define PWM_O_X_RIS 0x00000008 // Gen Raw Int Status Reg
-#define PWM_O_X_ISC 0x0000000C // Gen Int Status Reg
-#define PWM_O_X_LOAD 0x00000010 // Gen Load Reg
-#define PWM_O_X_COUNT 0x00000014 // Gen Counter Reg
-#define PWM_O_X_CMPA 0x00000018 // Gen Compare A Reg
-#define PWM_O_X_CMPB 0x0000001C // Gen Compare B Reg
-#define PWM_O_X_GENA 0x00000020 // Gen Generator A Ctrl Reg
-#define PWM_O_X_GENB 0x00000024 // Gen Generator B Ctrl Reg
-#define PWM_O_X_DBCTL 0x00000028 // Gen Dead Band Ctrl Reg
-#define PWM_O_X_DBRISE 0x0000002C // Gen DB Rising Edge Delay Reg
-#define PWM_O_X_DBFALL 0x00000030 // Gen DB Falling Edge Delay Reg
-#define PWM_O_X_FLTSRC0 0x00000034 // Fault pin, comparator condition
-#define PWM_O_X_MINFLTPER 0x0000003C // Fault minimum period extension
-#define PWM_GEN_0_OFFSET 0x00000040 // PWM0 base
-#define PWM_GEN_1_OFFSET 0x00000080 // PWM1 base
-#define PWM_GEN_2_OFFSET 0x000000C0 // PWM2 base
-#define PWM_GEN_3_OFFSET 0x00000100 // PWM3 base
-
-//*****************************************************************************
-//
-// The following are defines for the PWM_X Control Register bit definitions.
-//
-//*****************************************************************************
-#define PWM_X_CTL_LATCH 0x00040000 // Latch Fault Input.
-#define PWM_X_CTL_MINFLTPER 0x00020000 // Minimum fault period enabled
-#define PWM_X_CTL_FLTSRC 0x00010000 // Fault Condition Source.
-#define PWM_X_CTL_DBFALLUPD_M 0x0000C000 // Specifies the update mode for
- // the PWMnDBFALL register.
-#define PWM_X_CTL_DBFALLUPD_I 0x00000000 // Immediate
-#define PWM_X_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized
-#define PWM_X_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized
-#define PWM_X_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode.
-#define PWM_X_CTL_DBRISEUPD_I 0x00000000 // Immediate
-#define PWM_X_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized
-#define PWM_X_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized
-#define PWM_X_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode.
-#define PWM_X_CTL_DBCTLUPD_I 0x00000000 // Immediate
-#define PWM_X_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized
-#define PWM_X_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized
-#define PWM_X_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode.
-#define PWM_X_CTL_GENBUPD_I 0x00000000 // Immediate
-#define PWM_X_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized
-#define PWM_X_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized
-#define PWM_X_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode.
-#define PWM_X_CTL_GENAUPD_I 0x00000000 // Immediate
-#define PWM_X_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized
-#define PWM_X_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized
-#define PWM_X_CTL_CMPBUPD 0x00000020 // Update mode for comp B reg
-#define PWM_X_CTL_CMPAUPD 0x00000010 // Update mode for comp A reg
-#define PWM_X_CTL_LOADUPD 0x00000008 // Update mode for the load reg
-#define PWM_X_CTL_DEBUG 0x00000004 // Debug mode
-#define PWM_X_CTL_MODE 0x00000002 // Counter mode, down or up/down
-#define PWM_X_CTL_ENABLE 0x00000001 // Master enable for gen block
-
-//*****************************************************************************
-//
-// The following are defines for the PWM Generator extended offsets.
-//
-//*****************************************************************************
-#define PWM_O_X_FLTSEN 0x00000000 // Fault logic sense
-#define PWM_O_X_FLTSTAT0 0x00000004 // Pin and comparator status
-#define PWM_EXT_0_OFFSET 0x00000800 // PWM0 extended base
-#define PWM_EXT_1_OFFSET 0x00000880 // PWM1 extended base
-#define PWM_EXT_2_OFFSET 0x00000900 // PWM2 extended base
-#define PWM_EXT_3_OFFSET 0x00000980 // PWM3 extended base
-
-//*****************************************************************************
-//
-// The following are defines for the PWM_X Interrupt/Trigger Enable Register
-// bit definitions.
-//
-//*****************************************************************************
-#define PWM_X_INTEN_TRCMPBD 0x00002000 // Trig if COUNT = CMPB D
-#define PWM_X_INTEN_TRCMPBU 0x00001000 // Trig if COUNT = CMPB U
-#define PWM_X_INTEN_TRCMPAD 0x00000800 // Trig if COUNT = CMPA D
-#define PWM_X_INTEN_TRCMPAU 0x00000400 // Trig if COUNT = CMPA U
-#define PWM_X_INTEN_TRCNTLOAD 0x00000200 // Trig if COUNT = LOAD
-#define PWM_X_INTEN_TRCNTZERO 0x00000100 // Trig if COUNT = 0
-#define PWM_X_INTEN_INTCMPBD 0x00000020 // Int if COUNT = CMPA D
-#define PWM_X_INTEN_INTCMPBU 0x00000010 // Int if COUNT = CMPA U
-#define PWM_X_INTEN_INTCMPAD 0x00000008 // Int if COUNT = CMPA D
-#define PWM_X_INTEN_INTCMPAU 0x00000004 // Int if COUNT = CMPA U
-#define PWM_X_INTEN_INTCNTLOAD 0x00000002 // Int if COUNT = LOAD
-#define PWM_X_INTEN_INTCNTZERO 0x00000001 // Int if COUNT = 0
-
-//*****************************************************************************
-//
-// The following are defines for the PWM_X Raw Interrupt Status Register bit
-// definitions.
-//
-//*****************************************************************************
-#define PWM_X_RIS_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D int
-#define PWM_X_RIS_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U int
-#define PWM_X_RIS_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D int
-#define PWM_X_RIS_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U int
-#define PWM_X_RIS_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD int
-#define PWM_X_RIS_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 int
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the PWM_O_INTEN register.
-//
-//*****************************************************************************
-#define PWM_INTEN_INTFAULT3 0x00080000 // Interrupt Fault 3.
-#define PWM_INTEN_INTFAULT2 0x00040000 // Interrupt Fault 2.
-#define PWM_INTEN_INTFAULT1 0x00020000 // Interrupt Fault 1.
-#define PWM_INTEN_INTFAULT 0x00010000 // Fault Interrupt Enable.
-#define PWM_INTEN_INTFAULT0 0x00010000 // Interrupt Fault 0.
-#define PWM_INTEN_INTPWM3 0x00000008 // PWM3 Interrupt Enable.
-#define PWM_INTEN_INTPWM2 0x00000004 // PWM2 Interrupt Enable.
-#define PWM_INTEN_INTPWM1 0x00000002 // PWM1 Interrupt Enable.
-#define PWM_INTEN_INTPWM0 0x00000001 // PWM0 Interrupt Enable.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the PWM_O_RIS register.
-//
-//*****************************************************************************
-#define PWM_RIS_INTFAULT3 0x00080000 // Interrupt Fault PWM 3.
-#define PWM_RIS_INTFAULT2 0x00040000 // Interrupt Fault PWM 2.
-#define PWM_RIS_INTFAULT1 0x00020000 // Interrupt Fault PWM 1.
-#define PWM_RIS_INTFAULT0 0x00010000 // Interrupt Fault PWM 0.
-#define PWM_RIS_INTFAULT 0x00010000 // Fault Interrupt Asserted.
-#define PWM_RIS_INTPWM3 0x00000008 // PWM3 Interrupt Asserted.
-#define PWM_RIS_INTPWM2 0x00000004 // PWM2 Interrupt Asserted.
-#define PWM_RIS_INTPWM1 0x00000002 // PWM1 Interrupt Asserted.
-#define PWM_RIS_INTPWM0 0x00000001 // PWM0 Interrupt Asserted.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the PWM_O_ISC register.
-//
-//*****************************************************************************
-#define PWM_ISC_INTFAULT3 0x00080000 // FAULT3 Interrupt Asserted.
-#define PWM_ISC_INTFAULT2 0x00040000 // FAULT2 Interrupt Asserted.
-#define PWM_ISC_INTFAULT1 0x00020000 // FAULT1 Interrupt Asserted.
-#define PWM_ISC_INTFAULT 0x00010000 // Fault Interrupt Asserted.
-#define PWM_ISC_INTFAULT0 0x00010000 // FAULT0 Interrupt Asserted.
-#define PWM_ISC_INTPWM3 0x00000008 // PWM3 Interrupt Status.
-#define PWM_ISC_INTPWM2 0x00000004 // PWM2 Interrupt Status.
-#define PWM_ISC_INTPWM1 0x00000002 // PWM1 Interrupt Status.
-#define PWM_ISC_INTPWM0 0x00000001 // PWM0 Interrupt Status.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the PWM_O_X_ISC register.
-//
-//*****************************************************************************
-#define PWM_X_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt.
-#define PWM_X_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt.
-#define PWM_X_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt.
-#define PWM_X_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt.
-#define PWM_X_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt.
-#define PWM_X_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the PWM_O_X_LOAD register.
-//
-//*****************************************************************************
-#define PWM_X_LOAD_M 0x0000FFFF // Counter Load Value.
-#define PWM_X_LOAD_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the PWM_O_X_COUNT register.
-//
-//*****************************************************************************
-#define PWM_X_COUNT_M 0x0000FFFF // Counter Value.
-#define PWM_X_COUNT_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the PWM_O_X_CMPA register.
-//
-//*****************************************************************************
-#define PWM_X_CMPA_M 0x0000FFFF // Comparator A Value.
-#define PWM_X_CMPA_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the PWM_O_X_CMPB register.
-//
-//*****************************************************************************
-#define PWM_X_CMPB_M 0x0000FFFF // Comparator B Value.
-#define PWM_X_CMPB_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the PWM_O_X_GENA register.
-//
-//*****************************************************************************
-#define PWM_X_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down.
-#define PWM_X_GENA_ACTCMPBD_NONE \
- 0x00000000 // Do nothing.
-#define PWM_X_GENA_ACTCMPBD_INV 0x00000400 // Invert the output signal.
-#define PWM_X_GENA_ACTCMPBD_ZERO \
- 0x00000800 // Set the output signal to 0.
-#define PWM_X_GENA_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1.
-#define PWM_X_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up.
-#define PWM_X_GENA_ACTCMPBU_NONE \
- 0x00000000 // Do nothing.
-#define PWM_X_GENA_ACTCMPBU_INV 0x00000100 // Invert the output signal.
-#define PWM_X_GENA_ACTCMPBU_ZERO \
- 0x00000200 // Set the output signal to 0.
-#define PWM_X_GENA_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1.
-#define PWM_X_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down.
-#define PWM_X_GENA_ACTCMPAD_NONE \
- 0x00000000 // Do nothing.
-#define PWM_X_GENA_ACTCMPAD_INV 0x00000040 // Invert the output signal.
-#define PWM_X_GENA_ACTCMPAD_ZERO \
- 0x00000080 // Set the output signal to 0.
-#define PWM_X_GENA_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1.
-#define PWM_X_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up.
-#define PWM_X_GENA_ACTCMPAU_NONE \
- 0x00000000 // Do nothing.
-#define PWM_X_GENA_ACTCMPAU_INV 0x00000010 // Invert the output signal.
-#define PWM_X_GENA_ACTCMPAU_ZERO \
- 0x00000020 // Set the output signal to 0.
-#define PWM_X_GENA_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1.
-#define PWM_X_GENA_ACTLOAD_M 0x0000000C // Action for Counter=Load.
-#define PWM_X_GENA_ACTLOAD_NONE 0x00000000 // Do nothing.
-#define PWM_X_GENA_ACTLOAD_INV 0x00000004 // Invert the output signal.
-#define PWM_X_GENA_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0.
-#define PWM_X_GENA_ACTLOAD_ONE 0x0000000C // Set the output signal to 1.
-#define PWM_X_GENA_ACTZERO_M 0x00000003 // Action for Counter=0.
-#define PWM_X_GENA_ACTZERO_NONE 0x00000000 // Do nothing.
-#define PWM_X_GENA_ACTZERO_INV 0x00000001 // Invert the output signal.
-#define PWM_X_GENA_ACTZERO_ZERO 0x00000002 // Set the output signal to 0.
-#define PWM_X_GENA_ACTZERO_ONE 0x00000003 // Set the output signal to 1.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the PWM_O_X_GENB register.
-//
-//*****************************************************************************
-#define PWM_X_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down.
-#define PWM_X_GENB_ACTCMPBD_NONE \
- 0x00000000 // Do nothing.
-#define PWM_X_GENB_ACTCMPBD_INV 0x00000400 // Invert the output signal.
-#define PWM_X_GENB_ACTCMPBD_ZERO \
- 0x00000800 // Set the output signal to 0.
-#define PWM_X_GENB_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1.
-#define PWM_X_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up.
-#define PWM_X_GENB_ACTCMPBU_NONE \
- 0x00000000 // Do nothing.
-#define PWM_X_GENB_ACTCMPBU_INV 0x00000100 // Invert the output signal.
-#define PWM_X_GENB_ACTCMPBU_ZERO \
- 0x00000200 // Set the output signal to 0.
-#define PWM_X_GENB_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1.
-#define PWM_X_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down.
-#define PWM_X_GENB_ACTCMPAD_NONE \
- 0x00000000 // Do nothing.
-#define PWM_X_GENB_ACTCMPAD_INV 0x00000040 // Invert the output signal.
-#define PWM_X_GENB_ACTCMPAD_ZERO \
- 0x00000080 // Set the output signal to 0.
-#define PWM_X_GENB_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1.
-#define PWM_X_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up.
-#define PWM_X_GENB_ACTCMPAU_NONE \
- 0x00000000 // Do nothing.
-#define PWM_X_GENB_ACTCMPAU_INV 0x00000010 // Invert the output signal.
-#define PWM_X_GENB_ACTCMPAU_ZERO \
- 0x00000020 // Set the output signal to 0.
-#define PWM_X_GENB_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1.
-#define PWM_X_GENB_ACTLOAD_M 0x0000000C // Action for Counter=Load.
-#define PWM_X_GENB_ACTLOAD_NONE 0x00000000 // Do nothing.
-#define PWM_X_GENB_ACTLOAD_INV 0x00000004 // Invert the output signal.
-#define PWM_X_GENB_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0.
-#define PWM_X_GENB_ACTLOAD_ONE 0x0000000C // Set the output signal to 1.
-#define PWM_X_GENB_ACTZERO_M 0x00000003 // Action for Counter=0.
-#define PWM_X_GENB_ACTZERO_NONE 0x00000000 // Do nothing.
-#define PWM_X_GENB_ACTZERO_INV 0x00000001 // Invert the output signal.
-#define PWM_X_GENB_ACTZERO_ZERO 0x00000002 // Set the output signal to 0.
-#define PWM_X_GENB_ACTZERO_ONE 0x00000003 // Set the output signal to 1.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the PWM_O_X_DBCTL register.
-//
-//*****************************************************************************
-#define PWM_X_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the PWM_O_X_DBRISE register.
-//
-//*****************************************************************************
-#define PWM_X_DBRISE_DELAY_M 0x00000FFF // Dead-Band Rise Delay.
-#define PWM_X_DBRISE_DELAY_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the PWM_O_X_DBFALL register.
-//
-//*****************************************************************************
-#define PWM_X_DBFALL_DELAY_M 0x00000FFF // Dead-Band Fall Delay.
-#define PWM_X_DBFALL_DELAY_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the PWM_O_FAULTVAL register.
-//
-//*****************************************************************************
-#define PWM_FAULTVAL_PWM7 0x00000080 // PWM7 Fault Value.
-#define PWM_FAULTVAL_PWM6 0x00000040 // PWM6 Fault Value.
-#define PWM_FAULTVAL_PWM5 0x00000020 // PWM5 Fault Value.
-#define PWM_FAULTVAL_PWM4 0x00000010 // PWM4 Fault Value.
-#define PWM_FAULTVAL_PWM3 0x00000008 // PWM3 Fault Value.
-#define PWM_FAULTVAL_PWM2 0x00000004 // PWM2 Fault Value.
-#define PWM_FAULTVAL_PWM1 0x00000002 // PWM1 Fault Value.
-#define PWM_FAULTVAL_PWM0 0x00000001 // PWM0 Fault Value.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the PWM_O_X_MINFLTPER
-// register.
-//
-//*****************************************************************************
-#define PWM_X_MINFLTPER_M 0x0000FFFF // Minimum Fault Period.
-#define PWM_X_MINFLTPER_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the PWM_O_X_FLTSEN register.
-//
-//*****************************************************************************
-#define PWM_X_FLTSEN_FAULT3 0x00000008 // Fault3 Sense.
-#define PWM_X_FLTSEN_FAULT2 0x00000004 // Fault2 Sense.
-#define PWM_X_FLTSEN_FAULT1 0x00000002 // Fault1 Sense.
-#define PWM_X_FLTSEN_FAULT0 0x00000001 // Fault0 Sense.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the PWM_O_X_FLTSRC0
-// register.
-//
-//*****************************************************************************
-#define PWM_X_FLTSRC0_FAULT3 0x00000008 // Fault3.
-#define PWM_X_FLTSRC0_FAULT2 0x00000004 // Fault2.
-#define PWM_X_FLTSRC0_FAULT1 0x00000002 // Fault1.
-#define PWM_X_FLTSRC0_FAULT0 0x00000001 // Fault0.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the PWM_O_X_FLTSTAT0
-// register.
-//
-//*****************************************************************************
-#define PWM_X_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3.
-#define PWM_X_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2.
-#define PWM_X_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1.
-#define PWM_X_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0.
-
-//*****************************************************************************
-//
-// The following definitions are deprecated.
-//
-//*****************************************************************************
-#ifndef DEPRECATED
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the PWM Master
-// Control register.
-//
-//*****************************************************************************
-#define PWM_CTL_GLOBAL_SYNC2 0x00000004 // Global sync generator 2
-#define PWM_CTL_GLOBAL_SYNC1 0x00000002 // Global sync generator 1
-#define PWM_CTL_GLOBAL_SYNC0 0x00000001 // Global sync generator 0
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the PWM Interrupt Register bit
-// definitions.
-//
-//*****************************************************************************
-#define PWM_INT_INTFAULT 0x00010000 // Fault interrupt pending
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the PWM Status
-// register.
-//
-//*****************************************************************************
-#define PWM_STATUS_FAULT 0x00000001 // Fault status
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the PWM_X Interrupt Status Register
-// bit definitions.
-//
-//*****************************************************************************
-#define PWM_X_INT_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D rcvd
-#define PWM_X_INT_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U rcvd
-#define PWM_X_INT_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D rcvd
-#define PWM_X_INT_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U rcvd
-#define PWM_X_INT_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD rcvd
-#define PWM_X_INT_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 received
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the PWM_X Generator A/B Control
-// Register bit definitions.
-//
-//*****************************************************************************
-#define PWM_X_GEN_Y_ACTCMPBD 0x00000C00 // Act PWM_X_COUNT = PWM_X_CMPB D
-#define PWM_X_GEN_Y_ACTCMPBU 0x00000300 // Act PWM_X_COUNT = PWM_X_CMPB U
-#define PWM_X_GEN_Y_ACTCMPAD 0x000000C0 // Act PWM_X_COUNT = PWM_X_CMPA D
-#define PWM_X_GEN_Y_ACTCMPAU 0x00000030 // Act PWM_X_COUNT = PWM_X_CMPA U
-#define PWM_X_GEN_Y_ACTLOAD 0x0000000C // Act PWM_X_COUNT = PWM_X_LOAD
-#define PWM_X_GEN_Y_ACTZERO 0x00000003 // Act PWM_X_COUNT = 0
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the PWM_X Generator A/B Control
-// Register action definitions.
-//
-//*****************************************************************************
-#define PWM_GEN_ACT_ONE 0x00000003 // Set the output signal to one
-#define PWM_GEN_ACT_ZERO 0x00000002 // Set the output signal to zero
-#define PWM_GEN_ACT_INV 0x00000001 // Invert the output signal
-#define PWM_GEN_ACT_NONE 0x00000000 // Do nothing
-#define PWM_GEN_ACT_B_DN_SHIFT 10 // Shift amount for the B dn action
-#define PWM_GEN_ACT_B_UP_SHIFT 8 // Shift amount for the B up action
-#define PWM_GEN_ACT_A_DN_SHIFT 6 // Shift amount for the A dn action
-#define PWM_GEN_ACT_A_UP_SHIFT 4 // Shift amount for the A up action
-#define PWM_GEN_ACT_LOAD_SHIFT 2 // Shift amount for the load action
-#define PWM_GEN_ACT_ZERO_SHIFT 0 // Shift amount for the zero action
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the PWM_X Dead Band Control
-// Register bit definitions.
-//
-//*****************************************************************************
-#define PWM_DBCTL_ENABLE 0x00000001 // Enable dead band insertion
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the PWM Register reset values.
-//
-//*****************************************************************************
-#define PWM_RV_X_DBCTL 0x00000000 // Control the dead band generator
-#define PWM_RV_STATUS 0x00000000 // Status
-#define PWM_RV_X_ISC 0x00000000 // Interrupt status and clearing
-#define PWM_RV_X_RIS 0x00000000 // Raw interrupt status
-#define PWM_RV_X_CTL 0x00000000 // Master control of the PWM
- // generator block
-#define PWM_RV_SYNC 0x00000000 // Counter synch for PWM generators
-#define PWM_RV_X_DBFALL 0x00000000 // The dead band falling edge delay
- // count
-#define PWM_RV_X_INTEN 0x00000000 // Interrupt and trigger enable
-#define PWM_RV_X_LOAD 0x00000000 // The load value for the counter
-#define PWM_RV_X_GENA 0x00000000 // Controls PWM generator A
-#define PWM_RV_CTL 0x00000000 // Master control of the PWM module
-#define PWM_RV_FAULT 0x00000000 // Fault handling for the PWM
- // output pins
-#define PWM_RV_RIS 0x00000000 // Raw interrupt status
-#define PWM_RV_X_CMPA 0x00000000 // The comparator A value
-#define PWM_RV_INVERT 0x00000000 // Inversion control for PWM output
- // pins
-#define PWM_RV_X_DBRISE 0x00000000 // The dead band rising edge delay
- // count
-#define PWM_RV_ENABLE 0x00000000 // Master enable for the PWM output
- // pins
-#define PWM_RV_X_GENB 0x00000000 // Controls PWM generator B
-#define PWM_RV_X_CMPB 0x00000000 // The comparator B value
-#define PWM_RV_ISC 0x00000000 // Interrupt status and clearing
-#define PWM_RV_INTEN 0x00000000 // Interrupt enable
-#define PWM_RV_X_COUNT 0x00000000 // The current counter value
-
-#endif
-
-#endif // __HW_PWM_H__
+//*****************************************************************************
+//
+// hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports
+//
+// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4781 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_PWM_H__
+#define __HW_PWM_H__
+
+//*****************************************************************************
+//
+// The following are defines for the PWM Module Register offsets.
+//
+//*****************************************************************************
+#define PWM_O_CTL 0x00000000 // PWM Master Control register
+#define PWM_O_SYNC 0x00000004 // PWM Time Base Sync register
+#define PWM_O_ENABLE 0x00000008 // PWM Output Enable register
+#define PWM_O_INVERT 0x0000000C // PWM Output Inversion register
+#define PWM_O_FAULT 0x00000010 // PWM Output Fault register
+#define PWM_O_INTEN 0x00000014 // PWM Interrupt Enable register
+#define PWM_O_RIS 0x00000018 // PWM Interrupt Raw Status reg.
+#define PWM_O_ISC 0x0000001C // PWM Interrupt Status register
+#define PWM_O_STATUS 0x00000020 // PWM Status register
+#define PWM_O_FAULTVAL 0x00000024 // PWM Fault Condition Value
+#define PWM_O_0_CTL 0x00000040 // PWM0 Control
+#define PWM_O_0_INTEN 0x00000044 // PWM0 Interrupt and Trigger
+ // Enable
+#define PWM_O_0_RIS 0x00000048 // PWM0 Raw Interrupt Status
+#define PWM_O_0_ISC 0x0000004C // PWM0 Interrupt Status and Clear
+#define PWM_O_0_LOAD 0x00000050 // PWM0 Load
+#define PWM_O_0_COUNT 0x00000054 // PWM0 Counter
+#define PWM_O_0_CMPA 0x00000058 // PWM0 Compare A
+#define PWM_O_0_CMPB 0x0000005C // PWM0 Compare B
+#define PWM_O_0_GENA 0x00000060 // PWM0 Generator A Control
+#define PWM_O_0_GENB 0x00000064 // PWM0 Generator B Control
+#define PWM_O_0_DBCTL 0x00000068 // PWM0 Dead-Band Control
+#define PWM_O_0_DBRISE 0x0000006C // PWM0 Dead-Band Rising-Edge Delay
+#define PWM_O_0_DBFALL 0x00000070 // PWM0 Dead-Band
+ // Falling-Edge-Delay
+#define PWM_O_0_FLTSRC0 0x00000074 // PWM0 Fault Source 0
+#define PWM_O_0_FLTSRC1 0x00000078 // PWM0 Fault Source 1
+#define PWM_O_0_MINFLTPER 0x0000007C // PWM0 Minimum Fault Period
+#define PWM_O_1_CTL 0x00000080 // PWM1 Control
+#define PWM_O_1_INTEN 0x00000084 // PWM1 Interrupt Enable
+#define PWM_O_1_RIS 0x00000088 // PWM1 Raw Interrupt Status
+#define PWM_O_1_ISC 0x0000008C // PWM1 Interrupt Status and Clear
+#define PWM_O_1_LOAD 0x00000090 // PWM1 Load
+#define PWM_O_1_COUNT 0x00000094 // PWM1 Counter
+#define PWM_O_1_CMPA 0x00000098 // PWM1 Compare A
+#define PWM_O_1_CMPB 0x0000009C // PWM1 Compare B
+#define PWM_O_1_GENA 0x000000A0 // PWM1 Generator A Control
+#define PWM_O_1_GENB 0x000000A4 // PWM1 Generator B Control
+#define PWM_O_1_DBCTL 0x000000A8 // PWM1 Dead-Band Control
+#define PWM_O_1_DBRISE 0x000000AC // PWM1 Dead-Band Rising-Edge Delay
+#define PWM_O_1_DBFALL 0x000000B0 // PWM1 Dead-Band
+ // Falling-Edge-Delay
+#define PWM_O_1_FLTSRC0 0x000000B4 // PWM1 Fault Source 0
+#define PWM_O_1_FLTSRC1 0x000000B8 // PWM1 Fault Source 1
+#define PWM_O_1_MINFLTPER 0x000000BC // PWM1 Minimum Fault Period
+#define PWM_O_2_CTL 0x000000C0 // PWM2 Control
+#define PWM_O_2_INTEN 0x000000C4 // PWM2 InterruptEnable
+#define PWM_O_2_RIS 0x000000C8 // PWM2 Raw Interrupt Status
+#define PWM_O_2_ISC 0x000000CC // PWM2 Interrupt Status and Clear
+#define PWM_O_2_LOAD 0x000000D0 // PWM2 Load
+#define PWM_O_2_COUNT 0x000000D4 // PWM2 Counter
+#define PWM_O_2_CMPA 0x000000D8 // PWM2 Compare A
+#define PWM_O_2_CMPB 0x000000DC // PWM2 Compare B
+#define PWM_O_2_GENA 0x000000E0 // PWM2 Generator A Control
+#define PWM_O_2_GENB 0x000000E4 // PWM2 Generator B Control
+#define PWM_O_2_DBCTL 0x000000E8 // PWM2 Dead-Band Control
+#define PWM_O_2_DBRISE 0x000000EC // PWM2 Dead-Band Rising-Edge Delay
+#define PWM_O_2_DBFALL 0x000000F0 // PWM2 Dead-Band
+ // Falling-Edge-Delay
+#define PWM_O_2_FLTSRC0 0x000000F4 // PWM2 Fault Source 0
+#define PWM_O_2_FLTSRC1 0x000000F8 // PWM2 Fault Source 1
+#define PWM_O_2_MINFLTPER 0x000000FC // PWM2 Minimum Fault Period
+#define PWM_O_3_CTL 0x00000100 // PWM3 Control
+#define PWM_O_3_INTEN 0x00000104 // PWM3 Interrupt and Trigger
+ // Enable
+#define PWM_O_3_RIS 0x00000108 // PWM3 Raw Interrupt Status
+#define PWM_O_3_ISC 0x0000010C // PWM3 Interrupt Status and Clear
+#define PWM_O_3_LOAD 0x00000110 // PWM3 Load
+#define PWM_O_3_COUNT 0x00000114 // PWM3 Counter
+#define PWM_O_3_CMPA 0x00000118 // PWM3 Compare A
+#define PWM_O_3_CMPB 0x0000011C // PWM3 Compare B
+#define PWM_O_3_GENA 0x00000120 // PWM3 Generator A Control
+#define PWM_O_3_GENB 0x00000124 // PWM3 Generator B Control
+#define PWM_O_3_DBCTL 0x00000128 // PWM3 Dead-Band Control
+#define PWM_O_3_DBRISE 0x0000012C // PWM3 Dead-Band Rising-Edge Delay
+#define PWM_O_3_DBFALL 0x00000130 // PWM3 Dead-Band
+ // Falling-Edge-Delay
+#define PWM_O_3_FLTSRC0 0x00000134 // PWM3 Fault Source 0
+#define PWM_O_3_FLTSRC1 0x00000138 // PWM3 Fault Source 1
+#define PWM_O_3_MINFLTPER 0x0000013C // PWM3 Minimum Fault Period
+#define PWM_O_0_FLTSEN 0x00000800 // PWM0 Fault Pin Logic Sense
+#define PWM_O_0_FLTSTAT0 0x00000804 // PWM0 Fault Status 0
+#define PWM_O_0_FLTSTAT1 0x00000808 // PWM0 Fault Status 1
+#define PWM_O_1_FLTSEN 0x00000880 // PWM1 Fault Pin Logic Sense
+#define PWM_O_1_FLTSTAT0 0x00000884 // PWM1 Fault Status 0
+#define PWM_O_1_FLTSTAT1 0x00000888 // PWM1 Fault Status 1
+#define PWM_O_2_FLTSEN 0x00000900 // PWM2 Fault Pin Logic Sense
+#define PWM_O_2_FLTSTAT0 0x00000904 // PWM2 Fault Status 0
+#define PWM_O_2_FLTSTAT1 0x00000908 // PWM2 Fault Status 1
+#define PWM_O_3_FLTSEN 0x00000980 // PWM3 Fault Pin Logic Sense
+#define PWM_O_3_FLTSTAT0 0x00000984 // PWM3 Fault Status 0
+#define PWM_O_3_FLTSTAT1 0x00000988 // PWM3 Fault Status 1
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM Master Control
+// register.
+//
+//*****************************************************************************
+#define PWM_CTL_GLOBALSYNC3 0x00000008 // Update PWM Generator 3.
+#define PWM_CTL_GLOBALSYNC2 0x00000004 // Update PWM Generator 2.
+#define PWM_CTL_GLOBALSYNC1 0x00000002 // Update PWM Generator 1.
+#define PWM_CTL_GLOBALSYNC0 0x00000001 // Update PWM Generator 0.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM Time Base Sync
+// register.
+//
+//*****************************************************************************
+#define PWM_SYNC_SYNC3 0x00000008 // Reset generator 3 counter
+#define PWM_SYNC_SYNC2 0x00000004 // Reset generator 2 counter
+#define PWM_SYNC_SYNC1 0x00000002 // Reset generator 1 counter
+#define PWM_SYNC_SYNC0 0x00000001 // Reset generator 0 counter
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM Output Enable
+// register.
+//
+//*****************************************************************************
+#define PWM_ENABLE_PWM7EN 0x00000080 // PWM7 pin enable
+#define PWM_ENABLE_PWM6EN 0x00000040 // PWM6 pin enable
+#define PWM_ENABLE_PWM5EN 0x00000020 // PWM5 pin enable
+#define PWM_ENABLE_PWM4EN 0x00000010 // PWM4 pin enable
+#define PWM_ENABLE_PWM3EN 0x00000008 // PWM3 pin enable
+#define PWM_ENABLE_PWM2EN 0x00000004 // PWM2 pin enable
+#define PWM_ENABLE_PWM1EN 0x00000002 // PWM1 pin enable
+#define PWM_ENABLE_PWM0EN 0x00000001 // PWM0 pin enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM Inversion register.
+//
+//*****************************************************************************
+#define PWM_INVERT_PWM7INV 0x00000080 // PWM7 pin invert
+#define PWM_INVERT_PWM6INV 0x00000040 // PWM6 pin invert
+#define PWM_INVERT_PWM5INV 0x00000020 // PWM5 pin invert
+#define PWM_INVERT_PWM4INV 0x00000010 // PWM4 pin invert
+#define PWM_INVERT_PWM3INV 0x00000008 // PWM3 pin invert
+#define PWM_INVERT_PWM2INV 0x00000004 // PWM2 pin invert
+#define PWM_INVERT_PWM1INV 0x00000002 // PWM1 pin invert
+#define PWM_INVERT_PWM0INV 0x00000001 // PWM0 pin invert
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM Fault register.
+//
+//*****************************************************************************
+#define PWM_FAULT_FAULT7 0x00000080 // PWM7 pin fault
+#define PWM_FAULT_FAULT6 0x00000040 // PWM6 pin fault
+#define PWM_FAULT_FAULT5 0x00000020 // PWM5 pin fault
+#define PWM_FAULT_FAULT4 0x00000010 // PWM4 pin fault
+#define PWM_FAULT_FAULT3 0x00000008 // PWM3 pin fault
+#define PWM_FAULT_FAULT2 0x00000004 // PWM2 pin fault
+#define PWM_FAULT_FAULT1 0x00000002 // PWM1 pin fault
+#define PWM_FAULT_FAULT0 0x00000001 // PWM0 pin fault
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM Status register.
+//
+//*****************************************************************************
+#define PWM_STATUS_FAULT3 0x00000008 // Fault3 Interrupt Status.
+#define PWM_STATUS_FAULT2 0x00000004 // Fault2 Interrupt Status.
+#define PWM_STATUS_FAULT1 0x00000002 // Fault1 Interrupt Status.
+#define PWM_STATUS_FAULT0 0x00000001 // Fault0 Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the PWM Generator standard offsets.
+//
+//*****************************************************************************
+#define PWM_O_X_CTL 0x00000000 // Gen Control Reg
+#define PWM_O_X_INTEN 0x00000004 // Gen Int/Trig Enable Reg
+#define PWM_O_X_RIS 0x00000008 // Gen Raw Int Status Reg
+#define PWM_O_X_ISC 0x0000000C // Gen Int Status Reg
+#define PWM_O_X_LOAD 0x00000010 // Gen Load Reg
+#define PWM_O_X_COUNT 0x00000014 // Gen Counter Reg
+#define PWM_O_X_CMPA 0x00000018 // Gen Compare A Reg
+#define PWM_O_X_CMPB 0x0000001C // Gen Compare B Reg
+#define PWM_O_X_GENA 0x00000020 // Gen Generator A Ctrl Reg
+#define PWM_O_X_GENB 0x00000024 // Gen Generator B Ctrl Reg
+#define PWM_O_X_DBCTL 0x00000028 // Gen Dead Band Ctrl Reg
+#define PWM_O_X_DBRISE 0x0000002C // Gen DB Rising Edge Delay Reg
+#define PWM_O_X_DBFALL 0x00000030 // Gen DB Falling Edge Delay Reg
+#define PWM_O_X_FLTSRC0 0x00000034 // Fault pin, comparator condition
+#define PWM_O_X_FLTSRC1 0x00000038 // Digital comparator condition
+#define PWM_O_X_MINFLTPER 0x0000003C // Fault minimum period extension
+#define PWM_GEN_0_OFFSET 0x00000040 // PWM0 base
+#define PWM_GEN_1_OFFSET 0x00000080 // PWM1 base
+#define PWM_GEN_2_OFFSET 0x000000C0 // PWM2 base
+#define PWM_GEN_3_OFFSET 0x00000100 // PWM3 base
+
+//*****************************************************************************
+//
+// The following are defines for the PWM_X Control Register bit definitions.
+//
+//*****************************************************************************
+#define PWM_X_CTL_LATCH 0x00040000 // Latch Fault Input.
+#define PWM_X_CTL_MINFLTPER 0x00020000 // Minimum fault period enabled
+#define PWM_X_CTL_FLTSRC 0x00010000 // Fault Condition Source.
+#define PWM_X_CTL_DBFALLUPD_M 0x0000C000 // Specifies the update mode for
+ // the PWMnDBFALL register.
+#define PWM_X_CTL_DBFALLUPD_I 0x00000000 // Immediate
+#define PWM_X_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized
+#define PWM_X_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized
+#define PWM_X_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode.
+#define PWM_X_CTL_DBRISEUPD_I 0x00000000 // Immediate
+#define PWM_X_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized
+#define PWM_X_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized
+#define PWM_X_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode.
+#define PWM_X_CTL_DBCTLUPD_I 0x00000000 // Immediate
+#define PWM_X_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized
+#define PWM_X_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized
+#define PWM_X_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode.
+#define PWM_X_CTL_GENBUPD_I 0x00000000 // Immediate
+#define PWM_X_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized
+#define PWM_X_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized
+#define PWM_X_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode.
+#define PWM_X_CTL_GENAUPD_I 0x00000000 // Immediate
+#define PWM_X_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized
+#define PWM_X_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized
+#define PWM_X_CTL_CMPBUPD 0x00000020 // Update mode for comp B reg
+#define PWM_X_CTL_CMPAUPD 0x00000010 // Update mode for comp A reg
+#define PWM_X_CTL_LOADUPD 0x00000008 // Update mode for the load reg
+#define PWM_X_CTL_DEBUG 0x00000004 // Debug mode
+#define PWM_X_CTL_MODE 0x00000002 // Counter mode, down or up/down
+#define PWM_X_CTL_ENABLE 0x00000001 // Master enable for gen block
+
+//*****************************************************************************
+//
+// The following are defines for the PWM Generator extended offsets.
+//
+//*****************************************************************************
+#define PWM_O_X_FLTSEN 0x00000000 // Fault logic sense
+#define PWM_O_X_FLTSTAT0 0x00000004 // Pin and comparator status
+#define PWM_O_X_FLTSTAT1 0x00000008 // Digital comparator status
+#define PWM_EXT_0_OFFSET 0x00000800 // PWM0 extended base
+#define PWM_EXT_1_OFFSET 0x00000880 // PWM1 extended base
+#define PWM_EXT_2_OFFSET 0x00000900 // PWM2 extended base
+#define PWM_EXT_3_OFFSET 0x00000980 // PWM3 extended base
+
+//*****************************************************************************
+//
+// The following are defines for the PWM_X Interrupt/Trigger Enable Register
+// bit definitions.
+//
+//*****************************************************************************
+#define PWM_X_INTEN_TRCMPBD 0x00002000 // Trig if COUNT = CMPB D
+#define PWM_X_INTEN_TRCMPBU 0x00001000 // Trig if COUNT = CMPB U
+#define PWM_X_INTEN_TRCMPAD 0x00000800 // Trig if COUNT = CMPA D
+#define PWM_X_INTEN_TRCMPAU 0x00000400 // Trig if COUNT = CMPA U
+#define PWM_X_INTEN_TRCNTLOAD 0x00000200 // Trig if COUNT = LOAD
+#define PWM_X_INTEN_TRCNTZERO 0x00000100 // Trig if COUNT = 0
+#define PWM_X_INTEN_INTCMPBD 0x00000020 // Int if COUNT = CMPA D
+#define PWM_X_INTEN_INTCMPBU 0x00000010 // Int if COUNT = CMPA U
+#define PWM_X_INTEN_INTCMPAD 0x00000008 // Int if COUNT = CMPA D
+#define PWM_X_INTEN_INTCMPAU 0x00000004 // Int if COUNT = CMPA U
+#define PWM_X_INTEN_INTCNTLOAD 0x00000002 // Int if COUNT = LOAD
+#define PWM_X_INTEN_INTCNTZERO 0x00000001 // Int if COUNT = 0
+
+//*****************************************************************************
+//
+// The following are defines for the PWM_X Raw Interrupt Status Register bit
+// definitions.
+//
+//*****************************************************************************
+#define PWM_X_RIS_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D int
+#define PWM_X_RIS_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U int
+#define PWM_X_RIS_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D int
+#define PWM_X_RIS_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U int
+#define PWM_X_RIS_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD int
+#define PWM_X_RIS_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 int
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_INTEN register.
+//
+//*****************************************************************************
+#define PWM_INTEN_INTFAULT3 0x00080000 // Interrupt Fault 3.
+#define PWM_INTEN_INTFAULT2 0x00040000 // Interrupt Fault 2.
+#define PWM_INTEN_INTFAULT1 0x00020000 // Interrupt Fault 1.
+#define PWM_INTEN_INTFAULT 0x00010000 // Fault Interrupt Enable.
+#define PWM_INTEN_INTFAULT0 0x00010000 // Interrupt Fault 0.
+#define PWM_INTEN_INTPWM3 0x00000008 // PWM3 Interrupt Enable.
+#define PWM_INTEN_INTPWM2 0x00000004 // PWM2 Interrupt Enable.
+#define PWM_INTEN_INTPWM1 0x00000002 // PWM1 Interrupt Enable.
+#define PWM_INTEN_INTPWM0 0x00000001 // PWM0 Interrupt Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_RIS register.
+//
+//*****************************************************************************
+#define PWM_RIS_INTFAULT3 0x00080000 // Interrupt Fault PWM 3.
+#define PWM_RIS_INTFAULT2 0x00040000 // Interrupt Fault PWM 2.
+#define PWM_RIS_INTFAULT1 0x00020000 // Interrupt Fault PWM 1.
+#define PWM_RIS_INTFAULT0 0x00010000 // Interrupt Fault PWM 0.
+#define PWM_RIS_INTFAULT 0x00010000 // Fault Interrupt Asserted.
+#define PWM_RIS_INTPWM3 0x00000008 // PWM3 Interrupt Asserted.
+#define PWM_RIS_INTPWM2 0x00000004 // PWM2 Interrupt Asserted.
+#define PWM_RIS_INTPWM1 0x00000002 // PWM1 Interrupt Asserted.
+#define PWM_RIS_INTPWM0 0x00000001 // PWM0 Interrupt Asserted.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_ISC register.
+//
+//*****************************************************************************
+#define PWM_ISC_INTFAULT3 0x00080000 // FAULT3 Interrupt Asserted.
+#define PWM_ISC_INTFAULT2 0x00040000 // FAULT2 Interrupt Asserted.
+#define PWM_ISC_INTFAULT1 0x00020000 // FAULT1 Interrupt Asserted.
+#define PWM_ISC_INTFAULT 0x00010000 // Fault Interrupt Asserted.
+#define PWM_ISC_INTFAULT0 0x00010000 // FAULT0 Interrupt Asserted.
+#define PWM_ISC_INTPWM3 0x00000008 // PWM3 Interrupt Status.
+#define PWM_ISC_INTPWM2 0x00000004 // PWM2 Interrupt Status.
+#define PWM_ISC_INTPWM1 0x00000002 // PWM1 Interrupt Status.
+#define PWM_ISC_INTPWM0 0x00000001 // PWM0 Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_ISC register.
+//
+//*****************************************************************************
+#define PWM_X_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt.
+#define PWM_X_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt.
+#define PWM_X_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt.
+#define PWM_X_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt.
+#define PWM_X_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt.
+#define PWM_X_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_LOAD register.
+//
+//*****************************************************************************
+#define PWM_X_LOAD_M 0x0000FFFF // Counter Load Value.
+#define PWM_X_LOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_COUNT register.
+//
+//*****************************************************************************
+#define PWM_X_COUNT_M 0x0000FFFF // Counter Value.
+#define PWM_X_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_CMPA register.
+//
+//*****************************************************************************
+#define PWM_X_CMPA_M 0x0000FFFF // Comparator A Value.
+#define PWM_X_CMPA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_CMPB register.
+//
+//*****************************************************************************
+#define PWM_X_CMPB_M 0x0000FFFF // Comparator B Value.
+#define PWM_X_CMPB_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_GENA register.
+//
+//*****************************************************************************
+#define PWM_X_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down.
+#define PWM_X_GENA_ACTCMPBD_NONE \
+ 0x00000000 // Do nothing.
+#define PWM_X_GENA_ACTCMPBD_INV 0x00000400 // Invert the output signal.
+#define PWM_X_GENA_ACTCMPBD_ZERO \
+ 0x00000800 // Set the output signal to 0.
+#define PWM_X_GENA_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1.
+#define PWM_X_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up.
+#define PWM_X_GENA_ACTCMPBU_NONE \
+ 0x00000000 // Do nothing.
+#define PWM_X_GENA_ACTCMPBU_INV 0x00000100 // Invert the output signal.
+#define PWM_X_GENA_ACTCMPBU_ZERO \
+ 0x00000200 // Set the output signal to 0.
+#define PWM_X_GENA_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1.
+#define PWM_X_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down.
+#define PWM_X_GENA_ACTCMPAD_NONE \
+ 0x00000000 // Do nothing.
+#define PWM_X_GENA_ACTCMPAD_INV 0x00000040 // Invert the output signal.
+#define PWM_X_GENA_ACTCMPAD_ZERO \
+ 0x00000080 // Set the output signal to 0.
+#define PWM_X_GENA_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1.
+#define PWM_X_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up.
+#define PWM_X_GENA_ACTCMPAU_NONE \
+ 0x00000000 // Do nothing.
+#define PWM_X_GENA_ACTCMPAU_INV 0x00000010 // Invert the output signal.
+#define PWM_X_GENA_ACTCMPAU_ZERO \
+ 0x00000020 // Set the output signal to 0.
+#define PWM_X_GENA_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1.
+#define PWM_X_GENA_ACTLOAD_M 0x0000000C // Action for Counter=Load.
+#define PWM_X_GENA_ACTLOAD_NONE 0x00000000 // Do nothing.
+#define PWM_X_GENA_ACTLOAD_INV 0x00000004 // Invert the output signal.
+#define PWM_X_GENA_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0.
+#define PWM_X_GENA_ACTLOAD_ONE 0x0000000C // Set the output signal to 1.
+#define PWM_X_GENA_ACTZERO_M 0x00000003 // Action for Counter=0.
+#define PWM_X_GENA_ACTZERO_NONE 0x00000000 // Do nothing.
+#define PWM_X_GENA_ACTZERO_INV 0x00000001 // Invert the output signal.
+#define PWM_X_GENA_ACTZERO_ZERO 0x00000002 // Set the output signal to 0.
+#define PWM_X_GENA_ACTZERO_ONE 0x00000003 // Set the output signal to 1.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_GENB register.
+//
+//*****************************************************************************
+#define PWM_X_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down.
+#define PWM_X_GENB_ACTCMPBD_NONE \
+ 0x00000000 // Do nothing.
+#define PWM_X_GENB_ACTCMPBD_INV 0x00000400 // Invert the output signal.
+#define PWM_X_GENB_ACTCMPBD_ZERO \
+ 0x00000800 // Set the output signal to 0.
+#define PWM_X_GENB_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1.
+#define PWM_X_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up.
+#define PWM_X_GENB_ACTCMPBU_NONE \
+ 0x00000000 // Do nothing.
+#define PWM_X_GENB_ACTCMPBU_INV 0x00000100 // Invert the output signal.
+#define PWM_X_GENB_ACTCMPBU_ZERO \
+ 0x00000200 // Set the output signal to 0.
+#define PWM_X_GENB_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1.
+#define PWM_X_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down.
+#define PWM_X_GENB_ACTCMPAD_NONE \
+ 0x00000000 // Do nothing.
+#define PWM_X_GENB_ACTCMPAD_INV 0x00000040 // Invert the output signal.
+#define PWM_X_GENB_ACTCMPAD_ZERO \
+ 0x00000080 // Set the output signal to 0.
+#define PWM_X_GENB_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1.
+#define PWM_X_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up.
+#define PWM_X_GENB_ACTCMPAU_NONE \
+ 0x00000000 // Do nothing.
+#define PWM_X_GENB_ACTCMPAU_INV 0x00000010 // Invert the output signal.
+#define PWM_X_GENB_ACTCMPAU_ZERO \
+ 0x00000020 // Set the output signal to 0.
+#define PWM_X_GENB_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1.
+#define PWM_X_GENB_ACTLOAD_M 0x0000000C // Action for Counter=Load.
+#define PWM_X_GENB_ACTLOAD_NONE 0x00000000 // Do nothing.
+#define PWM_X_GENB_ACTLOAD_INV 0x00000004 // Invert the output signal.
+#define PWM_X_GENB_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0.
+#define PWM_X_GENB_ACTLOAD_ONE 0x0000000C // Set the output signal to 1.
+#define PWM_X_GENB_ACTZERO_M 0x00000003 // Action for Counter=0.
+#define PWM_X_GENB_ACTZERO_NONE 0x00000000 // Do nothing.
+#define PWM_X_GENB_ACTZERO_INV 0x00000001 // Invert the output signal.
+#define PWM_X_GENB_ACTZERO_ZERO 0x00000002 // Set the output signal to 0.
+#define PWM_X_GENB_ACTZERO_ONE 0x00000003 // Set the output signal to 1.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_DBCTL register.
+//
+//*****************************************************************************
+#define PWM_X_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_DBRISE register.
+//
+//*****************************************************************************
+#define PWM_X_DBRISE_DELAY_M 0x00000FFF // Dead-Band Rise Delay.
+#define PWM_X_DBRISE_DELAY_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_DBFALL register.
+//
+//*****************************************************************************
+#define PWM_X_DBFALL_DELAY_M 0x00000FFF // Dead-Band Fall Delay.
+#define PWM_X_DBFALL_DELAY_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_FAULTVAL register.
+//
+//*****************************************************************************
+#define PWM_FAULTVAL_PWM7 0x00000080 // PWM7 Fault Value.
+#define PWM_FAULTVAL_PWM6 0x00000040 // PWM6 Fault Value.
+#define PWM_FAULTVAL_PWM5 0x00000020 // PWM5 Fault Value.
+#define PWM_FAULTVAL_PWM4 0x00000010 // PWM4 Fault Value.
+#define PWM_FAULTVAL_PWM3 0x00000008 // PWM3 Fault Value.
+#define PWM_FAULTVAL_PWM2 0x00000004 // PWM2 Fault Value.
+#define PWM_FAULTVAL_PWM1 0x00000002 // PWM1 Fault Value.
+#define PWM_FAULTVAL_PWM0 0x00000001 // PWM0 Fault Value.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_MINFLTPER
+// register.
+//
+//*****************************************************************************
+#define PWM_X_MINFLTPER_M 0x0000FFFF // Minimum Fault Period.
+#define PWM_X_MINFLTPER_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_FLTSEN register.
+//
+//*****************************************************************************
+#define PWM_X_FLTSEN_FAULT3 0x00000008 // Fault3 Sense.
+#define PWM_X_FLTSEN_FAULT2 0x00000004 // Fault2 Sense.
+#define PWM_X_FLTSEN_FAULT1 0x00000002 // Fault1 Sense.
+#define PWM_X_FLTSEN_FAULT0 0x00000001 // Fault0 Sense.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_FLTSRC0
+// register.
+//
+//*****************************************************************************
+#define PWM_X_FLTSRC0_FAULT3 0x00000008 // Fault3.
+#define PWM_X_FLTSRC0_FAULT2 0x00000004 // Fault2.
+#define PWM_X_FLTSRC0_FAULT1 0x00000002 // Fault1.
+#define PWM_X_FLTSRC0_FAULT0 0x00000001 // Fault0.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_FLTSTAT0
+// register.
+//
+//*****************************************************************************
+#define PWM_X_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3.
+#define PWM_X_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2.
+#define PWM_X_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1.
+#define PWM_X_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_FLTSRC1
+// register.
+//
+//*****************************************************************************
+#define PWM_X_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7.
+#define PWM_X_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6.
+#define PWM_X_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5.
+#define PWM_X_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4.
+#define PWM_X_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3.
+#define PWM_X_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2.
+#define PWM_X_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1.
+#define PWM_X_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_FLTSTAT1
+// register.
+//
+//*****************************************************************************
+#define PWM_X_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger.
+#define PWM_X_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger.
+#define PWM_X_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger.
+#define PWM_X_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger.
+#define PWM_X_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger.
+#define PWM_X_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger.
+#define PWM_X_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger.
+#define PWM_X_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger.
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the PWM Master
+// Control register.
+//
+//*****************************************************************************
+#define PWM_CTL_GLOBAL_SYNC2 0x00000004 // Global sync generator 2
+#define PWM_CTL_GLOBAL_SYNC1 0x00000002 // Global sync generator 1
+#define PWM_CTL_GLOBAL_SYNC0 0x00000001 // Global sync generator 0
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the PWM Interrupt Register bit
+// definitions.
+//
+//*****************************************************************************
+#define PWM_INT_INTFAULT 0x00010000 // Fault interrupt pending
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the PWM Status
+// register.
+//
+//*****************************************************************************
+#define PWM_STATUS_FAULT 0x00000001 // Fault status
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the PWM_X Interrupt Status Register
+// bit definitions.
+//
+//*****************************************************************************
+#define PWM_X_INT_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D rcvd
+#define PWM_X_INT_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U rcvd
+#define PWM_X_INT_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D rcvd
+#define PWM_X_INT_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U rcvd
+#define PWM_X_INT_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD rcvd
+#define PWM_X_INT_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 received
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the PWM_X Generator A/B Control
+// Register bit definitions.
+//
+//*****************************************************************************
+#define PWM_X_GEN_Y_ACTCMPBD 0x00000C00 // Act PWM_X_COUNT = PWM_X_CMPB D
+#define PWM_X_GEN_Y_ACTCMPBU 0x00000300 // Act PWM_X_COUNT = PWM_X_CMPB U
+#define PWM_X_GEN_Y_ACTCMPAD 0x000000C0 // Act PWM_X_COUNT = PWM_X_CMPA D
+#define PWM_X_GEN_Y_ACTCMPAU 0x00000030 // Act PWM_X_COUNT = PWM_X_CMPA U
+#define PWM_X_GEN_Y_ACTLOAD 0x0000000C // Act PWM_X_COUNT = PWM_X_LOAD
+#define PWM_X_GEN_Y_ACTZERO 0x00000003 // Act PWM_X_COUNT = 0
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the PWM_X Generator A/B Control
+// Register action definitions.
+//
+//*****************************************************************************
+#define PWM_GEN_ACT_ONE 0x00000003 // Set the output signal to one
+#define PWM_GEN_ACT_ZERO 0x00000002 // Set the output signal to zero
+#define PWM_GEN_ACT_INV 0x00000001 // Invert the output signal
+#define PWM_GEN_ACT_NONE 0x00000000 // Do nothing
+#define PWM_GEN_ACT_B_DN_SHIFT 10 // Shift amount for the B dn action
+#define PWM_GEN_ACT_B_UP_SHIFT 8 // Shift amount for the B up action
+#define PWM_GEN_ACT_A_DN_SHIFT 6 // Shift amount for the A dn action
+#define PWM_GEN_ACT_A_UP_SHIFT 4 // Shift amount for the A up action
+#define PWM_GEN_ACT_LOAD_SHIFT 2 // Shift amount for the load action
+#define PWM_GEN_ACT_ZERO_SHIFT 0 // Shift amount for the zero action
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the PWM_X Dead Band Control
+// Register bit definitions.
+//
+//*****************************************************************************
+#define PWM_DBCTL_ENABLE 0x00000001 // Enable dead band insertion
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the PWM Register reset values.
+//
+//*****************************************************************************
+#define PWM_RV_X_DBCTL 0x00000000 // Control the dead band generator
+#define PWM_RV_STATUS 0x00000000 // Status
+#define PWM_RV_X_ISC 0x00000000 // Interrupt status and clearing
+#define PWM_RV_X_RIS 0x00000000 // Raw interrupt status
+#define PWM_RV_X_CTL 0x00000000 // Master control of the PWM
+ // generator block
+#define PWM_RV_SYNC 0x00000000 // Counter synch for PWM generators
+#define PWM_RV_X_DBFALL 0x00000000 // The dead band falling edge delay
+ // count
+#define PWM_RV_X_INTEN 0x00000000 // Interrupt and trigger enable
+#define PWM_RV_X_LOAD 0x00000000 // The load value for the counter
+#define PWM_RV_X_GENA 0x00000000 // Controls PWM generator A
+#define PWM_RV_CTL 0x00000000 // Master control of the PWM module
+#define PWM_RV_FAULT 0x00000000 // Fault handling for the PWM
+ // output pins
+#define PWM_RV_RIS 0x00000000 // Raw interrupt status
+#define PWM_RV_X_CMPA 0x00000000 // The comparator A value
+#define PWM_RV_INVERT 0x00000000 // Inversion control for PWM output
+ // pins
+#define PWM_RV_X_DBRISE 0x00000000 // The dead band rising edge delay
+ // count
+#define PWM_RV_ENABLE 0x00000000 // Master enable for the PWM output
+ // pins
+#define PWM_RV_X_GENB 0x00000000 // Controls PWM generator B
+#define PWM_RV_X_CMPB 0x00000000 // The comparator B value
+#define PWM_RV_ISC 0x00000000 // Interrupt status and clearing
+#define PWM_RV_INTEN 0x00000000 // Interrupt enable
+#define PWM_RV_X_COUNT 0x00000000 // The current counter value
+
+#endif
+
+#endif // __HW_PWM_H__
Property changes on: branches/eagle_mmc/src/platform/lm3s/hw_pwm.h
___________________________________________________________________
Name: svn:executable
+ *
Added: branches/eagle_mmc/src/platform/lm3s/hw_qei.h
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/hw_qei.h 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lm3s/hw_qei.h 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,201 @@
+//*****************************************************************************
+//
+// hw_qei.h - Macros used when accessing the QEI hardware.
+//
+// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4781 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_QEI_H__
+#define __HW_QEI_H__
+
+//*****************************************************************************
+//
+// The following are defines for the QEI register offsets.
+//
+//*****************************************************************************
+#define QEI_O_CTL 0x00000000 // Configuration and control reg.
+#define QEI_O_STAT 0x00000004 // Status register
+#define QEI_O_POS 0x00000008 // Current position register
+#define QEI_O_MAXPOS 0x0000000C // Maximum position register
+#define QEI_O_LOAD 0x00000010 // Velocity timer load register
+#define QEI_O_TIME 0x00000014 // Velocity timer register
+#define QEI_O_COUNT 0x00000018 // Velocity pulse count register
+#define QEI_O_SPEED 0x0000001C // Velocity speed register
+#define QEI_O_INTEN 0x00000020 // Interrupt enable register
+#define QEI_O_RIS 0x00000024 // Raw interrupt status register
+#define QEI_O_ISC 0x00000028 // Interrupt status register
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_CTL register.
+//
+//*****************************************************************************
+#define QEI_CTL_FILTCNT_M 0x000F0000 // Input Filter Pre-Scale Count.
+#define QEI_CTL_FILTEN 0x00002000 // Enable Input Filter.
+#define QEI_CTL_STALLEN 0x00001000 // Stall enable
+#define QEI_CTL_INVI 0x00000800 // Invert Index input
+#define QEI_CTL_INVB 0x00000400 // Invert PhB input
+#define QEI_CTL_INVA 0x00000200 // Invert PhA input
+#define QEI_CTL_VELDIV_M 0x000001C0 // Velocity predivider mask
+#define QEI_CTL_VELDIV_1 0x00000000 // Predivide by 1
+#define QEI_CTL_VELDIV_2 0x00000040 // Predivide by 2
+#define QEI_CTL_VELDIV_4 0x00000080 // Predivide by 4
+#define QEI_CTL_VELDIV_8 0x000000C0 // Predivide by 8
+#define QEI_CTL_VELDIV_16 0x00000100 // Predivide by 16
+#define QEI_CTL_VELDIV_32 0x00000140 // Predivide by 32
+#define QEI_CTL_VELDIV_64 0x00000180 // Predivide by 64
+#define QEI_CTL_VELDIV_128 0x000001C0 // Predivide by 128
+#define QEI_CTL_VELEN 0x00000020 // Velocity enable
+#define QEI_CTL_RESMODE 0x00000010 // Position counter reset mode
+#define QEI_CTL_CAPMODE 0x00000008 // Edge capture mode
+#define QEI_CTL_SIGMODE 0x00000004 // Encoder signaling mode
+#define QEI_CTL_SWAP 0x00000002 // Swap input signals
+#define QEI_CTL_ENABLE 0x00000001 // QEI enable
+#define QEI_CTL_FILTCNT_S 16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_STAT register.
+//
+//*****************************************************************************
+#define QEI_STAT_DIRECTION 0x00000002 // Direction of rotation
+#define QEI_STAT_ERROR 0x00000001 // Signalling error detected
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_POS register.
+//
+//*****************************************************************************
+#define QEI_POS_M 0xFFFFFFFF // Current encoder position
+#define QEI_POS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_MAXPOS register.
+//
+//*****************************************************************************
+#define QEI_MAXPOS_M 0xFFFFFFFF // Maximum encoder position
+#define QEI_MAXPOS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_LOAD register.
+//
+//*****************************************************************************
+#define QEI_LOAD_M 0xFFFFFFFF // Velocity timer load value
+#define QEI_LOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_TIME register.
+//
+//*****************************************************************************
+#define QEI_TIME_M 0xFFFFFFFF // Velocity timer current value
+#define QEI_TIME_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_COUNT register.
+//
+//*****************************************************************************
+#define QEI_COUNT_M 0xFFFFFFFF // Encoder running pulse count
+#define QEI_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_SPEED register.
+//
+//*****************************************************************************
+#define QEI_SPEED_M 0xFFFFFFFF // Encoder pulse count
+#define QEI_SPEED_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_INTEN register.
+//
+//*****************************************************************************
+#define QEI_INTEN_ERROR 0x00000008 // Phase error detected
+#define QEI_INTEN_DIR 0x00000004 // Direction change
+#define QEI_INTEN_TIMER 0x00000002 // Velocity timer expired
+#define QEI_INTEN_INDEX 0x00000001 // Index pulse detected
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_RIS register.
+//
+//*****************************************************************************
+#define QEI_RIS_ERROR 0x00000008 // Phase error detected
+#define QEI_RIS_DIR 0x00000004 // Direction change
+#define QEI_RIS_TIMER 0x00000002 // Velocity timer expired
+#define QEI_RIS_INDEX 0x00000001 // Index pulse detected
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_ISC register.
+//
+//*****************************************************************************
+#define QEI_ISC_ERROR 0x00000008 // Phase Error Interrupt.
+#define QEI_ISC_DIR 0x00000004 // Direction Change Interrupt.
+#define QEI_ISC_TIMER 0x00000002 // Velocity Timer Expired
+ // Interrupt.
+#define QEI_ISC_INDEX 0x00000001 // Index Pulse Interrupt.
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the QEI_ISC
+// register.
+//
+//*****************************************************************************
+#define QEI_INT_ERROR 0x00000008 // Phase error detected
+#define QEI_INT_DIR 0x00000004 // Direction change
+#define QEI_INT_TIMER 0x00000002 // Velocity timer expired
+#define QEI_INT_INDEX 0x00000001 // Index pulse detected
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the reset values for the QEI
+// registers.
+//
+//*****************************************************************************
+#define QEI_RV_POS 0x00000000 // Current position register
+#define QEI_RV_LOAD 0x00000000 // Velocity timer load register
+#define QEI_RV_CTL 0x00000000 // Configuration and control reg.
+#define QEI_RV_RIS 0x00000000 // Raw interrupt status register
+#define QEI_RV_ISC 0x00000000 // Interrupt status register
+#define QEI_RV_SPEED 0x00000000 // Velocity speed register
+#define QEI_RV_INTEN 0x00000000 // Interrupt enable register
+#define QEI_RV_STAT 0x00000000 // Status register
+#define QEI_RV_COUNT 0x00000000 // Velocity pulse count register
+#define QEI_RV_MAXPOS 0x00000000 // Maximum position register
+#define QEI_RV_TIME 0x00000000 // Velocity timer register
+
+#endif
+
+#endif // __HW_QEI_H__
Property changes on: branches/eagle_mmc/src/platform/lm3s/hw_qei.h
___________________________________________________________________
Name: svn:executable
+ *
Modified: branches/eagle_mmc/src/platform/lm3s/hw_ssi.h
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/hw_ssi.h 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lm3s/hw_ssi.h 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,219 +1,220 @@
-//*****************************************************************************
-//
-// hw_ssi.h - Macros used when accessing the SSI hardware.
-//
-// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
-// Software License Agreement
-//
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
-//
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws. All rights are reserved. You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program. Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
-//
-// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-//
-// This is part of revision 3740 of the Stellaris Firmware Development Package.
-//
-//*****************************************************************************
-
-#ifndef __HW_SSI_H__
-#define __HW_SSI_H__
-
-//*****************************************************************************
-//
-// The following are defines for the SSI register offsets.
-//
-//*****************************************************************************
-#define SSI_O_CR0 0x00000000 // Control register 0
-#define SSI_O_CR1 0x00000004 // Control register 1
-#define SSI_O_DR 0x00000008 // Data register
-#define SSI_O_SR 0x0000000C // Status register
-#define SSI_O_CPSR 0x00000010 // Clock prescale register
-#define SSI_O_IM 0x00000014 // Int mask set and clear register
-#define SSI_O_RIS 0x00000018 // Raw interrupt register
-#define SSI_O_MIS 0x0000001C // Masked interrupt register
-#define SSI_O_ICR 0x00000020 // Interrupt clear register
-#define SSI_O_DMACTL 0x00000024 // SSI DMA Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SSI Control register 0.
-//
-//*****************************************************************************
-#define SSI_CR0_SCR_M 0x0000FF00 // SSI Serial Clock Rate.
-#define SSI_CR0_SPH 0x00000080 // SSPCLKOUT phase
-#define SSI_CR0_SPO 0x00000040 // SSPCLKOUT polarity
-#define SSI_CR0_FRF_M 0x00000030 // Frame format mask
-#define SSI_CR0_FRF_MOTO 0x00000000 // Motorola SPI frame format
-#define SSI_CR0_FRF_TI 0x00000010 // TI sync serial frame format
-#define SSI_CR0_FRF_NMW 0x00000020 // National Microwire frame format
-#define SSI_CR0_DSS_M 0x0000000F // SSI Data Size Select.
-#define SSI_CR0_DSS_4 0x00000003 // 4 bit data
-#define SSI_CR0_DSS_5 0x00000004 // 5 bit data
-#define SSI_CR0_DSS_6 0x00000005 // 6 bit data
-#define SSI_CR0_DSS_7 0x00000006 // 7 bit data
-#define SSI_CR0_DSS_8 0x00000007 // 8 bit data
-#define SSI_CR0_DSS_9 0x00000008 // 9 bit data
-#define SSI_CR0_DSS_10 0x00000009 // 10 bit data
-#define SSI_CR0_DSS_11 0x0000000A // 11 bit data
-#define SSI_CR0_DSS_12 0x0000000B // 12 bit data
-#define SSI_CR0_DSS_13 0x0000000C // 13 bit data
-#define SSI_CR0_DSS_14 0x0000000D // 14 bit data
-#define SSI_CR0_DSS_15 0x0000000E // 15 bit data
-#define SSI_CR0_DSS_16 0x0000000F // 16 bit data
-#define SSI_CR0_SCR_S 8
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SSI Control register 1.
-//
-//*****************************************************************************
-#define SSI_CR1_SOD 0x00000008 // Slave mode output disable
-#define SSI_CR1_MS 0x00000004 // Master or slave mode select
-#define SSI_CR1_SSE 0x00000002 // Sync serial port enable
-#define SSI_CR1_LBM 0x00000001 // Loopback mode
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SSI Status register.
-//
-//*****************************************************************************
-#define SSI_SR_BSY 0x00000010 // SSI busy
-#define SSI_SR_RFF 0x00000008 // RX FIFO full
-#define SSI_SR_RNE 0x00000004 // RX FIFO not empty
-#define SSI_SR_TNF 0x00000002 // TX FIFO not full
-#define SSI_SR_TFE 0x00000001 // TX FIFO empty
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SSI clock prescale
-// register.
-//
-//*****************************************************************************
-#define SSI_CPSR_CPSDVSR_M 0x000000FF // SSI Clock Prescale Divisor.
-#define SSI_CPSR_CPSDVSR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SSI_O_DR register.
-//
-//*****************************************************************************
-#define SSI_DR_DATA_M 0x0000FFFF // SSI Receive/Transmit Data.
-#define SSI_DR_DATA_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SSI_O_IM register.
-//
-//*****************************************************************************
-#define SSI_IM_TXIM 0x00000008 // SSI Transmit FIFO Interrupt
- // Mask.
-#define SSI_IM_RXIM 0x00000004 // SSI Receive FIFO Interrupt Mask.
-#define SSI_IM_RTIM 0x00000002 // SSI Receive Time-Out Interrupt
- // Mask.
-#define SSI_IM_RORIM 0x00000001 // SSI Receive Overrun Interrupt
- // Mask.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SSI_O_RIS register.
-//
-//*****************************************************************************
-#define SSI_RIS_TXRIS 0x00000008 // SSI Transmit FIFO Raw Interrupt
- // Status.
-#define SSI_RIS_RXRIS 0x00000004 // SSI Receive FIFO Raw Interrupt
- // Status.
-#define SSI_RIS_RTRIS 0x00000002 // SSI Receive Time-Out Raw
- // Interrupt Status.
-#define SSI_RIS_RORRIS 0x00000001 // SSI Receive Overrun Raw
- // Interrupt Status.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SSI_O_MIS register.
-//
-//*****************************************************************************
-#define SSI_MIS_TXMIS 0x00000008 // SSI Transmit FIFO Masked
- // Interrupt Status.
-#define SSI_MIS_RXMIS 0x00000004 // SSI Receive FIFO Masked
- // Interrupt Status.
-#define SSI_MIS_RTMIS 0x00000002 // SSI Receive Time-Out Masked
- // Interrupt Status.
-#define SSI_MIS_RORMIS 0x00000001 // SSI Receive Overrun Masked
- // Interrupt Status.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SSI_O_ICR register.
-//
-//*****************************************************************************
-#define SSI_ICR_RTIC 0x00000002 // SSI Receive Time-Out Interrupt
- // Clear.
-#define SSI_ICR_RORIC 0x00000001 // SSI Receive Overrun Interrupt
- // Clear.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SSI_O_DMACTL register.
-//
-//*****************************************************************************
-#define SSI_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable.
-#define SSI_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable.
-
-//*****************************************************************************
-//
-// The following definitions are deprecated.
-//
-//*****************************************************************************
-#ifndef DEPRECATED
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the SSI Control
-// register 0.
-//
-//*****************************************************************************
-#define SSI_CR0_SCR 0x0000FF00 // Serial clock rate
-#define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask
-#define SSI_CR0_DSS 0x0000000F // Data size select
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the SSI clock
-// prescale register.
-//
-//*****************************************************************************
-#define SSI_CPSR_CPSDVSR_MASK 0x000000FF // Clock prescale
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the SSI controller's FIFO size.
-//
-//*****************************************************************************
-#define TX_FIFO_SIZE (8) // Number of entries in the TX FIFO
-#define RX_FIFO_SIZE (8) // Number of entries in the RX FIFO
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the interrupt
-// mask set and clear, raw interrupt, masked interrupt, and interrupt clear
-// registers.
-//
-//*****************************************************************************
-#define SSI_INT_TXFF 0x00000008 // TX FIFO interrupt
-#define SSI_INT_RXFF 0x00000004 // RX FIFO interrupt
-#define SSI_INT_RXTO 0x00000002 // RX timeout interrupt
-#define SSI_INT_RXOR 0x00000001 // RX overrun interrupt
-
-#endif
-
-#endif // __HW_SSI_H__
+//*****************************************************************************
+//
+// hw_ssi.h - Macros used when accessing the SSI hardware.
+//
+// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4781 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_SSI_H__
+#define __HW_SSI_H__
+
+//*****************************************************************************
+//
+// The following are defines for the SSI register offsets.
+//
+//*****************************************************************************
+#define SSI_O_CR0 0x00000000 // Control register 0
+#define SSI_O_CR1 0x00000004 // Control register 1
+#define SSI_O_DR 0x00000008 // Data register
+#define SSI_O_SR 0x0000000C // Status register
+#define SSI_O_CPSR 0x00000010 // Clock prescale register
+#define SSI_O_IM 0x00000014 // Int mask set and clear register
+#define SSI_O_RIS 0x00000018 // Raw interrupt register
+#define SSI_O_MIS 0x0000001C // Masked interrupt register
+#define SSI_O_ICR 0x00000020 // Interrupt clear register
+#define SSI_O_DMACTL 0x00000024 // SSI DMA Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI Control register 0.
+//
+//*****************************************************************************
+#define SSI_CR0_SCR_M 0x0000FF00 // SSI Serial Clock Rate.
+#define SSI_CR0_SPH 0x00000080 // SSPCLKOUT phase
+#define SSI_CR0_SPO 0x00000040 // SSPCLKOUT polarity
+#define SSI_CR0_FRF_M 0x00000030 // Frame format mask
+#define SSI_CR0_FRF_MOTO 0x00000000 // Motorola SPI frame format
+#define SSI_CR0_FRF_TI 0x00000010 // TI sync serial frame format
+#define SSI_CR0_FRF_NMW 0x00000020 // National Microwire frame format
+#define SSI_CR0_DSS_M 0x0000000F // SSI Data Size Select.
+#define SSI_CR0_DSS_4 0x00000003 // 4 bit data
+#define SSI_CR0_DSS_5 0x00000004 // 5 bit data
+#define SSI_CR0_DSS_6 0x00000005 // 6 bit data
+#define SSI_CR0_DSS_7 0x00000006 // 7 bit data
+#define SSI_CR0_DSS_8 0x00000007 // 8 bit data
+#define SSI_CR0_DSS_9 0x00000008 // 9 bit data
+#define SSI_CR0_DSS_10 0x00000009 // 10 bit data
+#define SSI_CR0_DSS_11 0x0000000A // 11 bit data
+#define SSI_CR0_DSS_12 0x0000000B // 12 bit data
+#define SSI_CR0_DSS_13 0x0000000C // 13 bit data
+#define SSI_CR0_DSS_14 0x0000000D // 14 bit data
+#define SSI_CR0_DSS_15 0x0000000E // 15 bit data
+#define SSI_CR0_DSS_16 0x0000000F // 16 bit data
+#define SSI_CR0_SCR_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI Control register 1.
+//
+//*****************************************************************************
+#define SSI_CR1_EOT 0x00000010 // End of Transmission.
+#define SSI_CR1_SOD 0x00000008 // Slave mode output disable
+#define SSI_CR1_MS 0x00000004 // Master or slave mode select
+#define SSI_CR1_SSE 0x00000002 // Sync serial port enable
+#define SSI_CR1_LBM 0x00000001 // Loopback mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI Status register.
+//
+//*****************************************************************************
+#define SSI_SR_BSY 0x00000010 // SSI busy
+#define SSI_SR_RFF 0x00000008 // RX FIFO full
+#define SSI_SR_RNE 0x00000004 // RX FIFO not empty
+#define SSI_SR_TNF 0x00000002 // TX FIFO not full
+#define SSI_SR_TFE 0x00000001 // TX FIFO empty
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI clock prescale
+// register.
+//
+//*****************************************************************************
+#define SSI_CPSR_CPSDVSR_M 0x000000FF // SSI Clock Prescale Divisor.
+#define SSI_CPSR_CPSDVSR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_DR register.
+//
+//*****************************************************************************
+#define SSI_DR_DATA_M 0x0000FFFF // SSI Receive/Transmit Data.
+#define SSI_DR_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_IM register.
+//
+//*****************************************************************************
+#define SSI_IM_TXIM 0x00000008 // SSI Transmit FIFO Interrupt
+ // Mask.
+#define SSI_IM_RXIM 0x00000004 // SSI Receive FIFO Interrupt Mask.
+#define SSI_IM_RTIM 0x00000002 // SSI Receive Time-Out Interrupt
+ // Mask.
+#define SSI_IM_RORIM 0x00000001 // SSI Receive Overrun Interrupt
+ // Mask.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_RIS register.
+//
+//*****************************************************************************
+#define SSI_RIS_TXRIS 0x00000008 // SSI Transmit FIFO Raw Interrupt
+ // Status.
+#define SSI_RIS_RXRIS 0x00000004 // SSI Receive FIFO Raw Interrupt
+ // Status.
+#define SSI_RIS_RTRIS 0x00000002 // SSI Receive Time-Out Raw
+ // Interrupt Status.
+#define SSI_RIS_RORRIS 0x00000001 // SSI Receive Overrun Raw
+ // Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_MIS register.
+//
+//*****************************************************************************
+#define SSI_MIS_TXMIS 0x00000008 // SSI Transmit FIFO Masked
+ // Interrupt Status.
+#define SSI_MIS_RXMIS 0x00000004 // SSI Receive FIFO Masked
+ // Interrupt Status.
+#define SSI_MIS_RTMIS 0x00000002 // SSI Receive Time-Out Masked
+ // Interrupt Status.
+#define SSI_MIS_RORMIS 0x00000001 // SSI Receive Overrun Masked
+ // Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_ICR register.
+//
+//*****************************************************************************
+#define SSI_ICR_RTIC 0x00000002 // SSI Receive Time-Out Interrupt
+ // Clear.
+#define SSI_ICR_RORIC 0x00000001 // SSI Receive Overrun Interrupt
+ // Clear.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_DMACTL register.
+//
+//*****************************************************************************
+#define SSI_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable.
+#define SSI_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable.
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SSI Control
+// register 0.
+//
+//*****************************************************************************
+#define SSI_CR0_SCR 0x0000FF00 // Serial clock rate
+#define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask
+#define SSI_CR0_DSS 0x0000000F // Data size select
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SSI clock
+// prescale register.
+//
+//*****************************************************************************
+#define SSI_CPSR_CPSDVSR_MASK 0x000000FF // Clock prescale
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the SSI controller's FIFO size.
+//
+//*****************************************************************************
+#define TX_FIFO_SIZE (8) // Number of entries in the TX FIFO
+#define RX_FIFO_SIZE (8) // Number of entries in the RX FIFO
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the interrupt
+// mask set and clear, raw interrupt, masked interrupt, and interrupt clear
+// registers.
+//
+//*****************************************************************************
+#define SSI_INT_TXFF 0x00000008 // TX FIFO interrupt
+#define SSI_INT_RXFF 0x00000004 // RX FIFO interrupt
+#define SSI_INT_RXTO 0x00000002 // RX timeout interrupt
+#define SSI_INT_RXOR 0x00000001 // RX overrun interrupt
+
+#endif
+
+#endif // __HW_SSI_H__
Property changes on: branches/eagle_mmc/src/platform/lm3s/hw_ssi.h
___________________________________________________________________
Name: svn:executable
+ *
Modified: branches/eagle_mmc/src/platform/lm3s/hw_sysctl.h
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/hw_sysctl.h 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lm3s/hw_sysctl.h 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,1333 +1,1625 @@
-//*****************************************************************************
-//
-// hw_sysctl.h - Macros used when accessing the system control hardware.
-//
-// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
-// Software License Agreement
-//
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
-//
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws. All rights are reserved. You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program. Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
-//
-// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-//
-// This is part of revision 3740 of the Stellaris Firmware Development Package.
-//
-//*****************************************************************************
-
-#ifndef __HW_SYSCTL_H__
-#define __HW_SYSCTL_H__
-
-//*****************************************************************************
-//
-// The following are defines for the system control register addresses.
-//
-//*****************************************************************************
-#define SYSCTL_DID0 0x400FE000 // Device identification register 0
-#define SYSCTL_DID1 0x400FE004 // Device identification register 1
-#define SYSCTL_DC0 0x400FE008 // Device capabilities register 0
-#define SYSCTL_DC1 0x400FE010 // Device capabilities register 1
-#define SYSCTL_DC2 0x400FE014 // Device capabilities register 2
-#define SYSCTL_DC3 0x400FE018 // Device capabilities register 3
-#define SYSCTL_DC4 0x400FE01C // Device capabilities register 4
-#define SYSCTL_DC5 0x400FE020 // Device capabilities register 5
-#define SYSCTL_DC6 0x400FE024 // Device capabilities register 6
-#define SYSCTL_DC7 0x400FE028 // Device capabilities register 7
-#define SYSCTL_PBORCTL 0x400FE030 // POR/BOR reset control register
-#define SYSCTL_LDOPCTL 0x400FE034 // LDO power control register
-#define SYSCTL_SRCR0 0x400FE040 // Software reset control reg 0
-#define SYSCTL_SRCR1 0x400FE044 // Software reset control reg 1
-#define SYSCTL_SRCR2 0x400FE048 // Software reset control reg 2
-#define SYSCTL_RIS 0x400FE050 // Raw interrupt status register
-#define SYSCTL_IMC 0x400FE054 // Interrupt mask/control register
-#define SYSCTL_MISC 0x400FE058 // Interrupt status register
-#define SYSCTL_RESC 0x400FE05C // Reset cause register
-#define SYSCTL_RCC 0x400FE060 // Run-mode clock config register
-#define SYSCTL_PLLCFG 0x400FE064 // PLL configuration register
-#define SYSCTL_GPIOHSCTL 0x400FE06C // GPIO High Speed Control
-#define SYSCTL_RCC2 0x400FE070 // Run-mode clock config register 2
-#define SYSCTL_MOSCCTL 0x400FE07C // Main Oscillator Control
-#define SYSCTL_RCGC0 0x400FE100 // Run-mode clock gating register 0
-#define SYSCTL_RCGC1 0x400FE104 // Run-mode clock gating register 1
-#define SYSCTL_RCGC2 0x400FE108 // Run-mode clock gating register 2
-#define SYSCTL_SCGC0 0x400FE110 // Sleep-mode clock gating reg 0
-#define SYSCTL_SCGC1 0x400FE114 // Sleep-mode clock gating reg 1
-#define SYSCTL_SCGC2 0x400FE118 // Sleep-mode clock gating reg 2
-#define SYSCTL_DCGC0 0x400FE120 // Deep Sleep-mode clock gate reg 0
-#define SYSCTL_DCGC1 0x400FE124 // Deep Sleep-mode clock gate reg 1
-#define SYSCTL_DCGC2 0x400FE128 // Deep Sleep-mode clock gate reg 2
-#define SYSCTL_DSLPCLKCFG 0x400FE144 // Deep Sleep-mode clock config reg
-#define SYSCTL_CLKVCLR 0x400FE150 // Clock verifcation clear register
-#define SYSCTL_LDOARST 0x400FE160 // LDO reset control register
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_DID0 register.
-//
-//*****************************************************************************
-#define SYSCTL_DID0_VER_M 0x70000000 // DID0 version mask
-#define SYSCTL_DID0_VER_0 0x00000000 // DID0 version 0
-#define SYSCTL_DID0_VER_1 0x10000000 // DID0 version 1
-#define SYSCTL_DID0_CLASS_M 0x00FF0000 // Device Class
-#define SYSCTL_DID0_CLASS_SANDSTORM \
- 0x00000000 // Sandstorm-class Device
-#define SYSCTL_DID0_CLASS_FURY 0x00010000 // Fury-class Device
-#define SYSCTL_DID0_CLASS_DUSTDEVIL \
- 0x00030000 // DustDevil-class Device
-#define SYSCTL_DID0_MAJ_M 0x0000FF00 // Major revision mask
-#define SYSCTL_DID0_MAJ_REVA 0x00000000 // Revision A (initial device)
-#define SYSCTL_DID0_MAJ_REVB 0x00000100 // Revision B (first base layer
- // revision)
-#define SYSCTL_DID0_MAJ_REVC 0x00000200 // Revision C (second base layer
- // revision)
-#define SYSCTL_DID0_MIN_M 0x000000FF // Minor revision mask
-#define SYSCTL_DID0_MIN_0 0x00000000 // Minor revision 0
-#define SYSCTL_DID0_MIN_1 0x00000001 // Minor revision 1
-#define SYSCTL_DID0_MIN_2 0x00000002 // Minor revision 2
-#define SYSCTL_DID0_MIN_3 0x00000003 // Minor revision 3
-#define SYSCTL_DID0_MIN_4 0x00000004 // Minor revision 4
-#define SYSCTL_DID0_MIN_5 0x00000005 // Minor revision 5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_DID1 register.
-//
-//*****************************************************************************
-#define SYSCTL_DID1_VER_M 0xF0000000 // DID1 Version.
-#define SYSCTL_DID1_VER_0 0x00000000 // Initial DID1 register format
- // definition, indicating a
- // Stellaris LM3Snnn device.
-#define SYSCTL_DID1_VER_1 0x10000000 // First revision of the DID1
- // register format, indicating a
- // Stellaris Fury-class device.
-#define SYSCTL_DID1_FAM_M 0x0F000000 // Family.
-#define SYSCTL_DID1_FAM_STELLARIS \
- 0x00000000 // Stellaris family of
- // microcontollers, that is, all
- // devices with external part
- // numbers starting with LM3S.
-#define SYSCTL_DID1_PRTNO_M 0x00FF0000 // Part number mask
-#define SYSCTL_DID1_PRTNO_101 0x00010000 // LM3S101
-#define SYSCTL_DID1_PRTNO_102 0x00020000 // LM3S102
-#define SYSCTL_DID1_PRTNO_300 0x00190000 // LM3S300
-#define SYSCTL_DID1_PRTNO_301 0x00110000 // LM3S301
-#define SYSCTL_DID1_PRTNO_308 0x001A0000 // LM3S308
-#define SYSCTL_DID1_PRTNO_310 0x00120000 // LM3S310
-#define SYSCTL_DID1_PRTNO_315 0x00130000 // LM3S315
-#define SYSCTL_DID1_PRTNO_316 0x00140000 // LM3S316
-#define SYSCTL_DID1_PRTNO_317 0x00170000 // LM3S317
-#define SYSCTL_DID1_PRTNO_328 0x00150000 // LM3S328
-#define SYSCTL_DID1_PRTNO_600 0x002A0000 // LM3S600
-#define SYSCTL_DID1_PRTNO_601 0x00210000 // LM3S601
-#define SYSCTL_DID1_PRTNO_608 0x002B0000 // LM3S608
-#define SYSCTL_DID1_PRTNO_610 0x00220000 // LM3S610
-#define SYSCTL_DID1_PRTNO_611 0x00230000 // LM3S611
-#define SYSCTL_DID1_PRTNO_612 0x00240000 // LM3S612
-#define SYSCTL_DID1_PRTNO_613 0x00250000 // LM3S613
-#define SYSCTL_DID1_PRTNO_615 0x00260000 // LM3S615
-#define SYSCTL_DID1_PRTNO_617 0x00280000 // LM3S617
-#define SYSCTL_DID1_PRTNO_618 0x00290000 // LM3S618
-#define SYSCTL_DID1_PRTNO_628 0x00270000 // LM3S628
-#define SYSCTL_DID1_PRTNO_800 0x00380000 // LM3S800
-#define SYSCTL_DID1_PRTNO_801 0x00310000 // LM3S801
-#define SYSCTL_DID1_PRTNO_808 0x00390000 // LM3S808
-#define SYSCTL_DID1_PRTNO_811 0x00320000 // LM3S811
-#define SYSCTL_DID1_PRTNO_812 0x00330000 // LM3S812
-#define SYSCTL_DID1_PRTNO_815 0x00340000 // LM3S815
-#define SYSCTL_DID1_PRTNO_817 0x00360000 // LM3S817
-#define SYSCTL_DID1_PRTNO_818 0x00370000 // LM3S818
-#define SYSCTL_DID1_PRTNO_828 0x00350000 // LM3S828
-#define SYSCTL_DID1_PRTNO_1110 0x00BF0000 // LM3S1110
-#define SYSCTL_DID1_PRTNO_1133 0x00C30000 // LM3S1133
-#define SYSCTL_DID1_PRTNO_1138 0x00C50000 // LM3S1138
-#define SYSCTL_DID1_PRTNO_1150 0x00C10000 // LM3S1150
-#define SYSCTL_DID1_PRTNO_1162 0x00C40000 // LM3S1162
-#define SYSCTL_DID1_PRTNO_1165 0x00C20000 // LM3S1165
-#define SYSCTL_DID1_PRTNO_1332 0x00C60000 // LM3S1332
-#define SYSCTL_DID1_PRTNO_1435 0x00BC0000 // LM3S1435
-#define SYSCTL_DID1_PRTNO_1439 0x00BA0000 // LM3S1439
-#define SYSCTL_DID1_PRTNO_1512 0x00BB0000 // LM3S1512
-#define SYSCTL_DID1_PRTNO_1538 0x00C70000 // LM3S1538
-#define SYSCTL_DID1_PRTNO_1601 0x00DB0000 // LM3S1601
-#define SYSCTL_DID1_PRTNO_1607 0x00060000 // LM3S1607
-#define SYSCTL_DID1_PRTNO_1608 0x00DA0000 // LM3S1608
-#define SYSCTL_DID1_PRTNO_1620 0x00C00000 // LM3S1620
-#define SYSCTL_DID1_PRTNO_1625 0x00030000 // LM3S1625
-#define SYSCTL_DID1_PRTNO_1626 0x00040000 // LM3S1626
-#define SYSCTL_DID1_PRTNO_1627 0x00050000 // LM3S1627
-#define SYSCTL_DID1_PRTNO_1635 0x00B30000 // LM3S1635
-#define SYSCTL_DID1_PRTNO_1637 0x00BD0000 // LM3S1637
-#define SYSCTL_DID1_PRTNO_1751 0x00B90000 // LM3S1751
-#define SYSCTL_DID1_PRTNO_1776 0x00100000 // LM3S1776
-#define SYSCTL_DID1_PRTNO_1850 0x00B40000 // LM3S1850
-#define SYSCTL_DID1_PRTNO_1911 0x00DD0000 // LM3S1911
-#define SYSCTL_DID1_PRTNO_1918 0x00DC0000 // LM3S1918
-#define SYSCTL_DID1_PRTNO_1937 0x00B70000 // LM3S1937
-#define SYSCTL_DID1_PRTNO_1958 0x00BE0000 // LM3S1958
-#define SYSCTL_DID1_PRTNO_1960 0x00B50000 // LM3S1960
-#define SYSCTL_DID1_PRTNO_1968 0x00B80000 // LM3S1968
-#define SYSCTL_DID1_PRTNO_2110 0x00510000 // LM3S2110
-#define SYSCTL_DID1_PRTNO_2139 0x00840000 // LM3S2139
-#define SYSCTL_DID1_PRTNO_2276 0x00390000 // LM3S2276
-#define SYSCTL_DID1_PRTNO_2410 0x00A20000 // LM3S2410
-#define SYSCTL_DID1_PRTNO_2412 0x00590000 // LM3S2412
-#define SYSCTL_DID1_PRTNO_2432 0x00560000 // LM3S2432
-#define SYSCTL_DID1_PRTNO_2533 0x005A0000 // LM3S2533
-#define SYSCTL_DID1_PRTNO_2601 0x00E10000 // LM3S2601
-#define SYSCTL_DID1_PRTNO_2608 0x00E00000 // LM3S2608
-#define SYSCTL_DID1_PRTNO_2616 0x00330000 // LM3S2616
-#define SYSCTL_DID1_PRTNO_2620 0x00570000 // LM3S2620
-#define SYSCTL_DID1_PRTNO_2637 0x00850000 // LM3S2637
-#define SYSCTL_DID1_PRTNO_2651 0x00530000 // LM3S2651
-#define SYSCTL_DID1_PRTNO_2671 0x00800000 // LM3S2671
-#define SYSCTL_DID1_PRTNO_2678 0x00500000 // LM3S2678
-#define SYSCTL_DID1_PRTNO_2730 0x00A40000 // LM3S2730
-#define SYSCTL_DID1_PRTNO_2739 0x00520000 // LM3S2739
-#define SYSCTL_DID1_PRTNO_2776 0x003A0000 // LM3S2776
-#define SYSCTL_DID1_PRTNO_2911 0x00E30000 // LM3S2911
-#define SYSCTL_DID1_PRTNO_2918 0x00E20000 // LM3S2918
-#define SYSCTL_DID1_PRTNO_2939 0x00540000 // LM3S2939
-#define SYSCTL_DID1_PRTNO_2948 0x008F0000 // LM3S2948
-#define SYSCTL_DID1_PRTNO_2950 0x00580000 // LM3S2950
-#define SYSCTL_DID1_PRTNO_2965 0x00550000 // LM3S2965
-#define SYSCTL_DID1_PRTNO_3651 0x00430000 // LM3S3651
-#define SYSCTL_DID1_PRTNO_3739 0x00440000 // LM3S3739
-#define SYSCTL_DID1_PRTNO_3748 0x00490000 // LM3S3748
-#define SYSCTL_DID1_PRTNO_3749 0x00450000 // LM3S3749
-#define SYSCTL_DID1_PRTNO_3759 0x00460000 // LM3S3759
-#define SYSCTL_DID1_PRTNO_3768 0x00480000 // LM3S3768
-#define SYSCTL_DID1_PRTNO_5632 0x00810000 // LM3S5632
-#define SYSCTL_DID1_PRTNO_5652 0x008A0000 // LM3S5652
-#define SYSCTL_DID1_PRTNO_5662 0x00910000 // LM3S5662
-#define SYSCTL_DID1_PRTNO_5732 0x00960000 // LM3S5732
-#define SYSCTL_DID1_PRTNO_5737 0x00970000 // LM3S5737
-#define SYSCTL_DID1_PRTNO_5739 0x00A00000 // LM3S5739
-#define SYSCTL_DID1_PRTNO_5747 0x00990000 // LM3S5747
-#define SYSCTL_DID1_PRTNO_5749 0x00A70000 // LM3S5749
-#define SYSCTL_DID1_PRTNO_5752 0x009A0000 // LM3S5752
-#define SYSCTL_DID1_PRTNO_5757 0x009B0000 // LM3S5757
-#define SYSCTL_DID1_PRTNO_5762 0x009C0000 // LM3S5762
-#define SYSCTL_DID1_PRTNO_5767 0x009D0000 // LM3S5767
-#define SYSCTL_DID1_PRTNO_5768 0x00A90000 // LM3S5768
-#define SYSCTL_DID1_PRTNO_5769 0x00A80000 // LM3S5769
-#define SYSCTL_DID1_PRTNO_6100 0x00A10000 // LM3S6100
-#define SYSCTL_DID1_PRTNO_6110 0x00740000 // LM3S6110
-#define SYSCTL_DID1_PRTNO_6420 0x00A50000 // LM3S6420
-#define SYSCTL_DID1_PRTNO_6422 0x00820000 // LM3S6422
-#define SYSCTL_DID1_PRTNO_6432 0x00750000 // LM3S6432
-#define SYSCTL_DID1_PRTNO_6537 0x00760000 // LM3S6537
-#define SYSCTL_DID1_PRTNO_6610 0x00710000 // LM3S6610
-#define SYSCTL_DID1_PRTNO_6611 0x00E70000 // LM3S6611
-#define SYSCTL_DID1_PRTNO_6618 0x00E60000 // LM3S6618
-#define SYSCTL_DID1_PRTNO_6633 0x00830000 // LM3S6633
-#define SYSCTL_DID1_PRTNO_6637 0x008B0000 // LM3S6637
-#define SYSCTL_DID1_PRTNO_6730 0x00A30000 // LM3S6730
-#define SYSCTL_DID1_PRTNO_6753 0x00770000 // LM3S6753
-#define SYSCTL_DID1_PRTNO_6911 0x00E90000 // LM3S6911
-#define SYSCTL_DID1_PRTNO_6918 0x00E80000 // LM3S6918
-#define SYSCTL_DID1_PRTNO_6938 0x00890000 // LM3S6938
-#define SYSCTL_DID1_PRTNO_6950 0x00720000 // LM3S6950
-#define SYSCTL_DID1_PRTNO_6952 0x00780000 // LM3S6952
-#define SYSCTL_DID1_PRTNO_6965 0x00730000 // LM3S6965
-#define SYSCTL_DID1_PRTNO_8530 0x00640000 // LM3S8530
-#define SYSCTL_DID1_PRTNO_8538 0x008E0000 // LM3S8538
-#define SYSCTL_DID1_PRTNO_8630 0x00610000 // LM3S8630
-#define SYSCTL_DID1_PRTNO_8730 0x00630000 // LM3S8730
-#define SYSCTL_DID1_PRTNO_8733 0x008D0000 // LM3S8733
-#define SYSCTL_DID1_PRTNO_8738 0x00860000 // LM3S8738
-#define SYSCTL_DID1_PRTNO_8930 0x00650000 // LM3S8930
-#define SYSCTL_DID1_PRTNO_8933 0x008C0000 // LM3S8933
-#define SYSCTL_DID1_PRTNO_8938 0x00880000 // LM3S8938
-#define SYSCTL_DID1_PRTNO_8962 0x00A60000 // LM3S8962
-#define SYSCTL_DID1_PRTNO_8970 0x00620000 // LM3S8970
-#define SYSCTL_DID1_PRTNO_8971 0x00D70000 // LM3S8971
-#define SYSCTL_DID1_PINCNT_M 0x0000E000 // Package Pin Count.
-#define SYSCTL_DID1_PINCNT_28 0x00000000 // 28 pin package
-#define SYSCTL_DID1_PINCNT_48 0x00002000 // 48 pin package
-#define SYSCTL_DID1_PINCNT_100 0x00004000 // 100 pin package
-#define SYSCTL_DID1_PINCNT_64 0x00006000 // 64 pin package
-#define SYSCTL_DID1_TEMP_M 0x000000E0 // Temperature range mask
-#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temp range (0..70C)
-#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temp range (-40..85C)
-#define SYSCTL_DID1_TEMP_E 0x00000040 // Extended temperature range (-40C
- // to 105C)
-#define SYSCTL_DID1_PKG_M 0x00000018 // Package Type.
-#define SYSCTL_DID1_PKG_28SOIC 0x00000000 // 28-pin SOIC
-#define SYSCTL_DID1_PKG_48QFP 0x00000008 // 48-pin QFP
-#define SYSCTL_DID1_PKG_BGA 0x00000010 // BGA package
-#define SYSCTL_DID1_ROHS 0x00000004 // Part is RoHS compliant
-#define SYSCTL_DID1_QUAL_M 0x00000003 // Qualification status mask
-#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering sample (unqualified)
-#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot production (unqualified)
-#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully qualified
-#define SYSCTL_DID1_PRTNO_S 16 // Part number shift
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_DC0 register.
-//
-//*****************************************************************************
-#define SYSCTL_DC0_SRAMSZ_M 0xFFFF0000 // SRAM size mask
-#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2 KB of SRAM
-#define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 // 4 KB of SRAM
-#define SYSCTL_DC0_SRAMSZ_8KB 0x001F0000 // 8 KB of SRAM
-#define SYSCTL_DC0_SRAMSZ_16KB 0x003F0000 // 16 KB of SRAM
-#define SYSCTL_DC0_SRAMSZ_32KB 0x007F0000 // 32 KB of SRAM
-#define SYSCTL_DC0_SRAMSZ_64KB 0x00FF0000 // 64 KB of SRAM
-#define SYSCTL_DC0_FLASHSZ_M 0x0000FFFF // Flash size mask
-#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8 KB of flash
-#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 // 16 KB of flash
-#define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F // 32 KB of flash
-#define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F // 64 KB of flash
-#define SYSCTL_DC0_FLASHSZ_96KB 0x0000002F // 96 KB of flash
-#define SYSCTL_DC0_FLASHSZ_128K 0x0000003F // 128 KB of flash
-#define SYSCTL_DC0_FLASHSZ_256K 0x0000007F // 256 KB of flash
-#define SYSCTL_DC0_SRAMSZ_S 16 // SRAM size shift
-#define SYSCTL_DC0_FLASHSZ_S 0 // Flash size shift
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_DC1 register.
-//
-//*****************************************************************************
-#define SYSCTL_DC1_CAN2 0x04000000 // CAN2 module present
-#define SYSCTL_DC1_CAN1 0x02000000 // CAN1 module present
-#define SYSCTL_DC1_CAN0 0x01000000 // CAN0 module present
-#define SYSCTL_DC1_PWM 0x00100000 // PWM module present
-#define SYSCTL_DC1_ADC 0x00010000 // ADC module present
-#define SYSCTL_DC1_MINSYSDIV_M 0x0000F000 // System Clock Divider.
-#define SYSCTL_DC1_MINSYSDIV_50 0x00003000 // Specifies a 50-MHz CPU clock
- // with a PLL divider of 4.
-#define SYSCTL_DC1_MINSYSDIV_25 0x00007000 // Specifies a 25-MHz clock with a
- // PLL divider of 8.
-#define SYSCTL_DC1_MINSYSDIV_20 0x00009000 // Specifies a 20-MHz clock with a
- // PLL divider of 10.
-#define SYSCTL_DC1_ADCSPD_M 0x00000F00 // ADC speed mask
-#define SYSCTL_DC1_ADCSPD_125K 0x00000000 // 125Ksps ADC
-#define SYSCTL_DC1_ADCSPD_250K 0x00000100 // 250Ksps ADC
-#define SYSCTL_DC1_ADCSPD_500K 0x00000200 // 500Ksps ADC
-#define SYSCTL_DC1_ADCSPD_1M 0x00000300 // 1Msps ADC
-#define SYSCTL_DC1_MPU 0x00000080 // Cortex M3 MPU present
-#define SYSCTL_DC1_HIB 0x00000040 // Hibernation module present
-#define SYSCTL_DC1_TEMP 0x00000020 // Temperature sensor present
-#define SYSCTL_DC1_PLL 0x00000010 // PLL present
-#define SYSCTL_DC1_WDT 0x00000008 // Watchdog Timer Present.
-#define SYSCTL_DC1_SWO 0x00000004 // Serial wire output present
-#define SYSCTL_DC1_SWD 0x00000002 // Serial wire debug present
-#define SYSCTL_DC1_JTAG 0x00000001 // JTAG debug present
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_DC2 register.
-//
-//*****************************************************************************
-#define SYSCTL_DC2_COMP2 0x04000000 // Analog comparator 2 present
-#define SYSCTL_DC2_COMP1 0x02000000 // Analog comparator 1 present
-#define SYSCTL_DC2_COMP0 0x01000000 // Analog comparator 0 present
-#define SYSCTL_DC2_TIMER3 0x00080000 // Timer 3 present
-#define SYSCTL_DC2_TIMER2 0x00040000 // Timer 2 present
-#define SYSCTL_DC2_TIMER1 0x00020000 // Timer 1 present
-#define SYSCTL_DC2_TIMER0 0x00010000 // Timer 0 present
-#define SYSCTL_DC2_I2C1 0x00004000 // I2C 1 present
-#define SYSCTL_DC2_I2C0 0x00001000 // I2C 0 present
-#define SYSCTL_DC2_QEI1 0x00000200 // QEI 1 present
-#define SYSCTL_DC2_QEI0 0x00000100 // QEI 0 present
-#define SYSCTL_DC2_SSI1 0x00000020 // SSI 1 present
-#define SYSCTL_DC2_SSI0 0x00000010 // SSI 0 present
-#define SYSCTL_DC2_UART2 0x00000004 // UART 2 present
-#define SYSCTL_DC2_UART1 0x00000002 // UART 1 present
-#define SYSCTL_DC2_UART0 0x00000001 // UART 0 present
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_DC3 register.
-//
-//*****************************************************************************
-#define SYSCTL_DC3_32KHZ 0x80000000 // 32KHz Pin Present.
-#define SYSCTL_DC3_CCP5 0x20000000 // CCP5 pin present
-#define SYSCTL_DC3_CCP4 0x10000000 // CCP4 pin present
-#define SYSCTL_DC3_CCP3 0x08000000 // CCP3 pin present
-#define SYSCTL_DC3_CCP2 0x04000000 // CCP2 pin present
-#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 pin present
-#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 pin present
-#define SYSCTL_DC3_ADC7 0x00800000 // ADC7 pin present
-#define SYSCTL_DC3_ADC6 0x00400000 // ADC6 pin present
-#define SYSCTL_DC3_ADC5 0x00200000 // ADC5 pin present
-#define SYSCTL_DC3_ADC4 0x00100000 // ADC4 pin present
-#define SYSCTL_DC3_ADC3 0x00080000 // ADC3 pin present
-#define SYSCTL_DC3_ADC2 0x00040000 // ADC2 pin present
-#define SYSCTL_DC3_ADC1 0x00020000 // ADC1 pin present
-#define SYSCTL_DC3_ADC0 0x00010000 // ADC0 pin present
-#define SYSCTL_DC3_PWMFAULT 0x00008000 // PWM Fault Pin Present.
-#define SYSCTL_DC3_C2O 0x00004000 // C2o pin present
-#define SYSCTL_DC3_C2PLUS 0x00002000 // C2+ pin present
-#define SYSCTL_DC3_C2MINUS 0x00001000 // C2- pin present
-#define SYSCTL_DC3_C1O 0x00000800 // C1o pin present
-#define SYSCTL_DC3_C1PLUS 0x00000400 // C1+ pin present
-#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- pin present
-#define SYSCTL_DC3_C0O 0x00000100 // C0o pin present
-#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ pin present
-#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- pin present
-#define SYSCTL_DC3_PWM5 0x00000020 // PWM5 pin present
-#define SYSCTL_DC3_PWM4 0x00000010 // PWM4 pin present
-#define SYSCTL_DC3_PWM3 0x00000008 // PWM3 pin present
-#define SYSCTL_DC3_PWM2 0x00000004 // PWM2 pin present
-#define SYSCTL_DC3_PWM1 0x00000002 // PWM1 pin present
-#define SYSCTL_DC3_PWM0 0x00000001 // PWM0 pin present
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_DC4 register.
-//
-//*****************************************************************************
-#define SYSCTL_DC4_ETH 0x50000000 // Ethernet present
-#define SYSCTL_DC4_EPHY0 0x40000000 // Ethernet PHY0 Present.
-#define SYSCTL_DC4_EMAC0 0x10000000 // Ethernet MAC0 Present.
-#define SYSCTL_DC4_E1588 0x01000000 // 1588 Capable.
-#define SYSCTL_DC4_CCP7 0x00008000 // CCP7 Pin Present.
-#define SYSCTL_DC4_CCP6 0x00004000 // CCP6 Pin Present.
-#define SYSCTL_DC4_UDMA 0x00002000 // Micro-DMA is present.
-#define SYSCTL_DC4_ROM 0x00001000 // Internal Code ROM is present.
-#define SYSCTL_DC4_GPIOH 0x00000080 // GPIO port H present
-#define SYSCTL_DC4_GPIOG 0x00000040 // GPIO port G present
-#define SYSCTL_DC4_GPIOF 0x00000020 // GPIO port F present
-#define SYSCTL_DC4_GPIOE 0x00000010 // GPIO port E present
-#define SYSCTL_DC4_GPIOD 0x00000008 // GPIO port D present
-#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO port C present
-#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO port B present
-#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO port A present
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_PBORCTL register.
-//
-//*****************************************************************************
-#define SYSCTL_PBORCTL_BORTIM_M 0x0000FFFC // BOR Time Delay.
-#define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR interrupt or reset
-#define SYSCTL_PBORCTL_BORWT 0x00000001 // BOR wait and check for noise
-#define SYSCTL_PBORCTL_BORTIM_S 2
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_LDOPCTL register.
-//
-//*****************************************************************************
-#define SYSCTL_LDOPCTL_M 0x0000003F // LDO Output Voltage.
-#define SYSCTL_LDOPCTL_2_55V 0x0000001F // LDO output of 2.55V
-#define SYSCTL_LDOPCTL_2_60V 0x0000001E // LDO output of 2.60V
-#define SYSCTL_LDOPCTL_2_65V 0x0000001D // LDO output of 2.65V
-#define SYSCTL_LDOPCTL_2_70V 0x0000001C // LDO output of 2.70V
-#define SYSCTL_LDOPCTL_2_75V 0x0000001B // LDO output of 2.75V
-#define SYSCTL_LDOPCTL_2_25V 0x00000005 // LDO output of 2.25V
-#define SYSCTL_LDOPCTL_2_30V 0x00000004 // LDO output of 2.30V
-#define SYSCTL_LDOPCTL_2_35V 0x00000003 // LDO output of 2.35V
-#define SYSCTL_LDOPCTL_2_40V 0x00000002 // LDO output of 2.40V
-#define SYSCTL_LDOPCTL_2_45V 0x00000001 // LDO output of 2.45V
-#define SYSCTL_LDOPCTL_2_50V 0x00000000 // LDO output of 2.50V
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_RESC register.
-//
-//*****************************************************************************
-#define SYSCTL_RESC_MOSCFAIL 0x00010000 // MOSC Failure Reset.
-#define SYSCTL_RESC_LDO 0x00000020 // LDO power OK lost reset
-#define SYSCTL_RESC_SW 0x00000010 // Software reset
-#define SYSCTL_RESC_WDT 0x00000008 // Watchdog Timer Reset.
-#define SYSCTL_RESC_BOR 0x00000004 // Brown-out reset
-#define SYSCTL_RESC_POR 0x00000002 // Power on reset
-#define SYSCTL_RESC_EXT 0x00000001 // External reset
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_RCC register.
-//
-//*****************************************************************************
-#define SYSCTL_RCC_ACG 0x08000000 // Automatic clock gating
-#define SYSCTL_RCC_SYSDIV_M 0x07800000 // System Clock Divisor.
-#define SYSCTL_RCC_SYSDIV_2 0x00800000 // System clock /2
-#define SYSCTL_RCC_SYSDIV_3 0x01000000 // System clock /3
-#define SYSCTL_RCC_SYSDIV_4 0x01800000 // System clock /4
-#define SYSCTL_RCC_SYSDIV_5 0x02000000 // System clock /5
-#define SYSCTL_RCC_SYSDIV_6 0x02800000 // System clock /6
-#define SYSCTL_RCC_SYSDIV_7 0x03000000 // System clock /7
-#define SYSCTL_RCC_SYSDIV_8 0x03800000 // System clock /8
-#define SYSCTL_RCC_SYSDIV_9 0x04000000 // System clock /9
-#define SYSCTL_RCC_SYSDIV_10 0x04800000 // System clock /10
-#define SYSCTL_RCC_SYSDIV_11 0x05000000 // System clock /11
-#define SYSCTL_RCC_SYSDIV_12 0x05800000 // System clock /12
-#define SYSCTL_RCC_SYSDIV_13 0x06000000 // System clock /13
-#define SYSCTL_RCC_SYSDIV_14 0x06800000 // System clock /14
-#define SYSCTL_RCC_SYSDIV_15 0x07000000 // System clock /15
-#define SYSCTL_RCC_SYSDIV_16 0x07800000 // System clock /16
-#define SYSCTL_RCC_USESYSDIV 0x00400000 // Enable System Clock Divider.
-#define SYSCTL_RCC_USEPWMDIV 0x00100000 // Enable PWM Clock Divisor.
-#define SYSCTL_RCC_PWMDIV_M 0x000E0000 // PWM clock divider
-#define SYSCTL_RCC_PWMDIV_2 0x00000000 // PWM clock /2
-#define SYSCTL_RCC_PWMDIV_4 0x00020000 // PWM clock /4
-#define SYSCTL_RCC_PWMDIV_8 0x00040000 // PWM clock /8
-#define SYSCTL_RCC_PWMDIV_16 0x00060000 // PWM clock /16
-#define SYSCTL_RCC_PWMDIV_32 0x00080000 // PWM clock /32
-#define SYSCTL_RCC_PWMDIV_64 0x000A0000 // PWM clock /64
-#define SYSCTL_RCC_PWRDN 0x00002000 // PLL power down
-#define SYSCTL_RCC_OEN 0x00001000 // PLL Output Enable.
-#define SYSCTL_RCC_BYPASS 0x00000800 // PLL bypass
-#define SYSCTL_RCC_XTAL_M 0x000007C0 // Crystal attached to main osc
-#define SYSCTL_RCC_XTAL_1MHZ 0x00000000 // Using a 1MHz crystal
-#define SYSCTL_RCC_XTAL_1_84MHZ 0x00000040 // Using a 1.8432MHz crystal
-#define SYSCTL_RCC_XTAL_2MHZ 0x00000080 // Using a 2MHz crystal
-#define SYSCTL_RCC_XTAL_2_45MHZ 0x000000C0 // Using a 2.4576MHz crystal
-#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100 // Using a 3.579545MHz crystal
-#define SYSCTL_RCC_XTAL_3_68MHZ 0x00000140 // Using a 3.6864MHz crystal
-#define SYSCTL_RCC_XTAL_4MHZ 0x00000180 // Using a 4MHz crystal
-#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // Using a 4.096MHz crystal
-#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // Using a 4.9152MHz crystal
-#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // Using a 5MHz crystal
-#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // Using a 5.12MHz crystal
-#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // Using a 6MHz crystal
-#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // Using a 6.144MHz crystal
-#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // Using a 7.3728MHz crystal
-#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // Using a 8MHz crystal
-#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // Using a 8.192MHz crystal
-#define SYSCTL_RCC_XTAL_10MHZ 0x00000400 // 10.0 MHz (USB)
-#define SYSCTL_RCC_XTAL_12MHZ 0x00000440 // 12.0 MHz (USB)
-#define SYSCTL_RCC_XTAL_12_2MHZ 0x00000480 // 12.288 MHz
-#define SYSCTL_RCC_XTAL_13_5MHZ 0x000004C0 // 13.56 MHz
-#define SYSCTL_RCC_XTAL_14_3MHZ 0x00000500 // 14.31818 MHz
-#define SYSCTL_RCC_XTAL_16MHZ 0x00000540 // 16.0 MHz (USB)
-#define SYSCTL_RCC_XTAL_16_3MHZ 0x00000580 // 16.384 MHz
-#define SYSCTL_RCC_PLLVER 0x00000400 // PLL verification timer enable
-#define SYSCTL_RCC_OSCSRC_M 0x00000030 // Oscillator input select
-#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // Use the main oscillator
-#define SYSCTL_RCC_OSCSRC_INT 0x00000010 // Use the internal oscillator
-#define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // Use the internal oscillator / 4
-#define SYSCTL_RCC_OSCSRC_30 0x00000030 // 30 KHz internal oscillator
-#define SYSCTL_RCC_IOSCVER 0x00000008 // Int. osc. verification timer en
-#define SYSCTL_RCC_MOSCVER 0x00000004 // Main osc. verification timer en
-#define SYSCTL_RCC_IOSCDIS 0x00000002 // Internal oscillator disable
-#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main oscillator disable
-#define SYSCTL_RCC_SYSDIV_S 23 // Shift to the SYSDIV field
-#define SYSCTL_RCC_PWMDIV_S 17 // Shift to the PWMDIV field
-#define SYSCTL_RCC_XTAL_S 6 // Shift to the XTAL field
-#define SYSCTL_RCC_OSCSRC_S 4 // Shift to the OSCSRC field
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_PLLCFG register.
-//
-//*****************************************************************************
-#define SYSCTL_PLLCFG_OD_M 0x0000C000 // Output divider
-#define SYSCTL_PLLCFG_OD_1 0x00000000 // Output divider is 1
-#define SYSCTL_PLLCFG_OD_2 0x00004000 // Output divider is 2
-#define SYSCTL_PLLCFG_OD_4 0x00008000 // Output divider is 4
-#define SYSCTL_PLLCFG_F_M 0x00003FE0 // PLL F Value.
-#define SYSCTL_PLLCFG_R_M 0x0000001F // PLL R Value.
-#define SYSCTL_PLLCFG_F_S 5
-#define SYSCTL_PLLCFG_R_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_RCC2 register.
-//
-//*****************************************************************************
-#define SYSCTL_RCC2_USERCC2 0x80000000 // Use RCC2
-#define SYSCTL_RCC2_SYSDIV2_M 0x1F800000 // System clock divider
-#define SYSCTL_RCC2_SYSDIV2_2 0x00800000 // System clock /2
-#define SYSCTL_RCC2_SYSDIV2_3 0x01000000 // System clock /3
-#define SYSCTL_RCC2_SYSDIV2_4 0x01800000 // System clock /4
-#define SYSCTL_RCC2_SYSDIV2_5 0x02000000 // System clock /5
-#define SYSCTL_RCC2_SYSDIV2_6 0x02800000 // System clock /6
-#define SYSCTL_RCC2_SYSDIV2_7 0x03000000 // System clock /7
-#define SYSCTL_RCC2_SYSDIV2_8 0x03800000 // System clock /8
-#define SYSCTL_RCC2_SYSDIV2_9 0x04000000 // System clock /9
-#define SYSCTL_RCC2_SYSDIV2_10 0x04800000 // System clock /10
-#define SYSCTL_RCC2_SYSDIV2_11 0x05000000 // System clock /11
-#define SYSCTL_RCC2_SYSDIV2_12 0x05800000 // System clock /12
-#define SYSCTL_RCC2_SYSDIV2_13 0x06000000 // System clock /13
-#define SYSCTL_RCC2_SYSDIV2_14 0x06800000 // System clock /14
-#define SYSCTL_RCC2_SYSDIV2_15 0x07000000 // System clock /15
-#define SYSCTL_RCC2_SYSDIV2_16 0x07800000 // System clock /16
-#define SYSCTL_RCC2_SYSDIV2_17 0x08000000 // System clock /17
-#define SYSCTL_RCC2_SYSDIV2_18 0x08800000 // System clock /18
-#define SYSCTL_RCC2_SYSDIV2_19 0x09000000 // System clock /19
-#define SYSCTL_RCC2_SYSDIV2_20 0x09800000 // System clock /20
-#define SYSCTL_RCC2_SYSDIV2_21 0x0A000000 // System clock /21
-#define SYSCTL_RCC2_SYSDIV2_22 0x0A800000 // System clock /22
-#define SYSCTL_RCC2_SYSDIV2_23 0x0B000000 // System clock /23
-#define SYSCTL_RCC2_SYSDIV2_24 0x0B800000 // System clock /24
-#define SYSCTL_RCC2_SYSDIV2_25 0x0C000000 // System clock /25
-#define SYSCTL_RCC2_SYSDIV2_26 0x0C800000 // System clock /26
-#define SYSCTL_RCC2_SYSDIV2_27 0x0D000000 // System clock /27
-#define SYSCTL_RCC2_SYSDIV2_28 0x0D800000 // System clock /28
-#define SYSCTL_RCC2_SYSDIV2_29 0x0E000000 // System clock /29
-#define SYSCTL_RCC2_SYSDIV2_30 0x0E800000 // System clock /30
-#define SYSCTL_RCC2_SYSDIV2_31 0x0F000000 // System clock /31
-#define SYSCTL_RCC2_SYSDIV2_32 0x0F800000 // System clock /32
-#define SYSCTL_RCC2_SYSDIV2_33 0x10000000 // System clock /33
-#define SYSCTL_RCC2_SYSDIV2_34 0x10800000 // System clock /34
-#define SYSCTL_RCC2_SYSDIV2_35 0x11000000 // System clock /35
-#define SYSCTL_RCC2_SYSDIV2_36 0x11800000 // System clock /36
-#define SYSCTL_RCC2_SYSDIV2_37 0x12000000 // System clock /37
-#define SYSCTL_RCC2_SYSDIV2_38 0x12800000 // System clock /38
-#define SYSCTL_RCC2_SYSDIV2_39 0x13000000 // System clock /39
-#define SYSCTL_RCC2_SYSDIV2_40 0x13800000 // System clock /40
-#define SYSCTL_RCC2_SYSDIV2_41 0x14000000 // System clock /41
-#define SYSCTL_RCC2_SYSDIV2_42 0x14800000 // System clock /42
-#define SYSCTL_RCC2_SYSDIV2_43 0x15000000 // System clock /43
-#define SYSCTL_RCC2_SYSDIV2_44 0x15800000 // System clock /44
-#define SYSCTL_RCC2_SYSDIV2_45 0x16000000 // System clock /45
-#define SYSCTL_RCC2_SYSDIV2_46 0x16800000 // System clock /46
-#define SYSCTL_RCC2_SYSDIV2_47 0x17000000 // System clock /47
-#define SYSCTL_RCC2_SYSDIV2_48 0x17800000 // System clock /48
-#define SYSCTL_RCC2_SYSDIV2_49 0x18000000 // System clock /49
-#define SYSCTL_RCC2_SYSDIV2_50 0x18800000 // System clock /50
-#define SYSCTL_RCC2_SYSDIV2_51 0x19000000 // System clock /51
-#define SYSCTL_RCC2_SYSDIV2_52 0x19800000 // System clock /52
-#define SYSCTL_RCC2_SYSDIV2_53 0x1A000000 // System clock /53
-#define SYSCTL_RCC2_SYSDIV2_54 0x1A800000 // System clock /54
-#define SYSCTL_RCC2_SYSDIV2_55 0x1B000000 // System clock /55
-#define SYSCTL_RCC2_SYSDIV2_56 0x1B800000 // System clock /56
-#define SYSCTL_RCC2_SYSDIV2_57 0x1C000000 // System clock /57
-#define SYSCTL_RCC2_SYSDIV2_58 0x1C800000 // System clock /58
-#define SYSCTL_RCC2_SYSDIV2_59 0x1D000000 // System clock /59
-#define SYSCTL_RCC2_SYSDIV2_60 0x1D800000 // System clock /60
-#define SYSCTL_RCC2_SYSDIV2_61 0x1E000000 // System clock /61
-#define SYSCTL_RCC2_SYSDIV2_62 0x1E800000 // System clock /62
-#define SYSCTL_RCC2_SYSDIV2_63 0x1F000000 // System clock /63
-#define SYSCTL_RCC2_SYSDIV2_64 0x1F800000 // System clock /64
-#define SYSCTL_RCC2_USBPWRDN 0x00004000 // Power-Down USB PLL.
-#define SYSCTL_RCC2_PWRDN2 0x00002000 // PLL power down
-#define SYSCTL_RCC2_BYPASS2 0x00000800 // PLL bypass
-#define SYSCTL_RCC2_OSCSRC2_M 0x00000070 // System Clock Source.
-#define SYSCTL_RCC2_OSCSRC2_MO 0x00000000 // Use the main oscillator
-#define SYSCTL_RCC2_OSCSRC2_IO 0x00000010 // Use the internal oscillator
-#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020 // Use the internal oscillator / 4
-#define SYSCTL_RCC2_OSCSRC2_30 0x00000030 // Use the 30 KHz internal osc.
-#define SYSCTL_RCC2_OSCSRC2_32 0x00000070 // Use the 32 KHz external osc.
-#define SYSCTL_RCC2_SYSDIV2_S 23 // Shift to the SYSDIV2 field
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_DSLPCLKCFG
-// register.
-//
-//*****************************************************************************
-#define SYSCTL_DSLPCLKCFG_D_M 0x1F800000 // Divider Field Override.
-#define SYSCTL_DSLPCLKCFG_D_2 0x00800000 // System clock /2
-#define SYSCTL_DSLPCLKCFG_D_3 0x01000000 // System clock /3
-#define SYSCTL_DSLPCLKCFG_D_4 0x01800000 // System clock /4
-#define SYSCTL_DSLPCLKCFG_D_5 0x02000000 // System clock /5
-#define SYSCTL_DSLPCLKCFG_D_6 0x02800000 // System clock /6
-#define SYSCTL_DSLPCLKCFG_D_7 0x03000000 // System clock /7
-#define SYSCTL_DSLPCLKCFG_D_8 0x03800000 // System clock /8
-#define SYSCTL_DSLPCLKCFG_D_9 0x04000000 // System clock /9
-#define SYSCTL_DSLPCLKCFG_D_10 0x04800000 // System clock /10
-#define SYSCTL_DSLPCLKCFG_D_11 0x05000000 // System clock /11
-#define SYSCTL_DSLPCLKCFG_D_12 0x05800000 // System clock /12
-#define SYSCTL_DSLPCLKCFG_D_13 0x06000000 // System clock /13
-#define SYSCTL_DSLPCLKCFG_D_14 0x06800000 // System clock /14
-#define SYSCTL_DSLPCLKCFG_D_15 0x07000000 // System clock /15
-#define SYSCTL_DSLPCLKCFG_D_16 0x07800000 // System clock /16
-#define SYSCTL_DSLPCLKCFG_D_17 0x08000000 // System clock /17
-#define SYSCTL_DSLPCLKCFG_D_18 0x08800000 // System clock /18
-#define SYSCTL_DSLPCLKCFG_D_19 0x09000000 // System clock /19
-#define SYSCTL_DSLPCLKCFG_D_20 0x09800000 // System clock /20
-#define SYSCTL_DSLPCLKCFG_D_21 0x0A000000 // System clock /21
-#define SYSCTL_DSLPCLKCFG_D_22 0x0A800000 // System clock /22
-#define SYSCTL_DSLPCLKCFG_D_23 0x0B000000 // System clock /23
-#define SYSCTL_DSLPCLKCFG_D_24 0x0B800000 // System clock /24
-#define SYSCTL_DSLPCLKCFG_D_25 0x0C000000 // System clock /25
-#define SYSCTL_DSLPCLKCFG_D_26 0x0C800000 // System clock /26
-#define SYSCTL_DSLPCLKCFG_D_27 0x0D000000 // System clock /27
-#define SYSCTL_DSLPCLKCFG_D_28 0x0D800000 // System clock /28
-#define SYSCTL_DSLPCLKCFG_D_29 0x0E000000 // System clock /29
-#define SYSCTL_DSLPCLKCFG_D_30 0x0E800000 // System clock /30
-#define SYSCTL_DSLPCLKCFG_D_31 0x0F000000 // System clock /31
-#define SYSCTL_DSLPCLKCFG_D_32 0x0F800000 // System clock /32
-#define SYSCTL_DSLPCLKCFG_D_33 0x10000000 // System clock /33
-#define SYSCTL_DSLPCLKCFG_D_34 0x10800000 // System clock /34
-#define SYSCTL_DSLPCLKCFG_D_35 0x11000000 // System clock /35
-#define SYSCTL_DSLPCLKCFG_D_36 0x11800000 // System clock /36
-#define SYSCTL_DSLPCLKCFG_D_37 0x12000000 // System clock /37
-#define SYSCTL_DSLPCLKCFG_D_38 0x12800000 // System clock /38
-#define SYSCTL_DSLPCLKCFG_D_39 0x13000000 // System clock /39
-#define SYSCTL_DSLPCLKCFG_D_40 0x13800000 // System clock /40
-#define SYSCTL_DSLPCLKCFG_D_41 0x14000000 // System clock /41
-#define SYSCTL_DSLPCLKCFG_D_42 0x14800000 // System clock /42
-#define SYSCTL_DSLPCLKCFG_D_43 0x15000000 // System clock /43
-#define SYSCTL_DSLPCLKCFG_D_44 0x15800000 // System clock /44
-#define SYSCTL_DSLPCLKCFG_D_45 0x16000000 // System clock /45
-#define SYSCTL_DSLPCLKCFG_D_46 0x16800000 // System clock /46
-#define SYSCTL_DSLPCLKCFG_D_47 0x17000000 // System clock /47
-#define SYSCTL_DSLPCLKCFG_D_48 0x17800000 // System clock /48
-#define SYSCTL_DSLPCLKCFG_D_49 0x18000000 // System clock /49
-#define SYSCTL_DSLPCLKCFG_D_50 0x18800000 // System clock /50
-#define SYSCTL_DSLPCLKCFG_D_51 0x19000000 // System clock /51
-#define SYSCTL_DSLPCLKCFG_D_52 0x19800000 // System clock /52
-#define SYSCTL_DSLPCLKCFG_D_53 0x1A000000 // System clock /53
-#define SYSCTL_DSLPCLKCFG_D_54 0x1A800000 // System clock /54
-#define SYSCTL_DSLPCLKCFG_D_55 0x1B000000 // System clock /55
-#define SYSCTL_DSLPCLKCFG_D_56 0x1B800000 // System clock /56
-#define SYSCTL_DSLPCLKCFG_D_57 0x1C000000 // System clock /57
-#define SYSCTL_DSLPCLKCFG_D_58 0x1C800000 // System clock /58
-#define SYSCTL_DSLPCLKCFG_D_59 0x1D000000 // System clock /59
-#define SYSCTL_DSLPCLKCFG_D_60 0x1D800000 // System clock /60
-#define SYSCTL_DSLPCLKCFG_D_61 0x1E000000 // System clock /61
-#define SYSCTL_DSLPCLKCFG_D_62 0x1E800000 // System clock /62
-#define SYSCTL_DSLPCLKCFG_D_63 0x1F000000 // System clock /63
-#define SYSCTL_DSLPCLKCFG_D_64 0x1F800000 // System clock /64
-#define SYSCTL_DSLPCLKCFG_O_M 0x00000070 // Clock Source.
-#define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000 // Do not override
-#define SYSCTL_DSLPCLKCFG_O_IO 0x00000010 // Use the internal oscillator
-#define SYSCTL_DSLPCLKCFG_O_30 0x00000030 // Use the 30 KHz internal osc.
-#define SYSCTL_DSLPCLKCFG_O_32 0x00000070 // Use the 32 KHz external osc.
-#define SYSCTL_DSLPCLKCFG_IOSC 0x00000001 // IOSC Clock Source.
-#define SYSCTL_DSLPCLKCFG_D_S 23
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_CLKVCLR register.
-//
-//*****************************************************************************
-#define SYSCTL_CLKVCLR_VERCLR 0x00000001 // Clock Verification Clear.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_LDOARST register.
-//
-//*****************************************************************************
-#define SYSCTL_LDOARST_LDOARST 0x00000001 // LDO Reset.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_SRCR0 register.
-//
-//*****************************************************************************
-#define SYSCTL_SRCR0_CAN2 0x04000000 // CAN2 Reset Control.
-#define SYSCTL_SRCR0_CAN1 0x02000000 // CAN1 Reset Control.
-#define SYSCTL_SRCR0_CAN0 0x01000000 // CAN0 Reset Control.
-#define SYSCTL_SRCR0_PWM 0x00100000 // PWM Reset Control.
-#define SYSCTL_SRCR0_ADC 0x00010000 // ADC0 Reset Control.
-#define SYSCTL_SRCR0_HIB 0x00000040 // HIB Reset Control.
-#define SYSCTL_SRCR0_WDT 0x00000008 // WDT Reset Control.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_SRCR1 register.
-//
-//*****************************************************************************
-#define SYSCTL_SRCR1_COMP2 0x04000000 // Analog Comp 2 Reset Control.
-#define SYSCTL_SRCR1_COMP1 0x02000000 // Analog Comp 1 Reset Control.
-#define SYSCTL_SRCR1_COMP0 0x01000000 // Analog Comp 0 Reset Control.
-#define SYSCTL_SRCR1_TIMER3 0x00080000 // Timer 3 Reset Control.
-#define SYSCTL_SRCR1_TIMER2 0x00040000 // Timer 2 Reset Control.
-#define SYSCTL_SRCR1_TIMER1 0x00020000 // Timer 1 Reset Control.
-#define SYSCTL_SRCR1_TIMER0 0x00010000 // Timer 0 Reset Control.
-#define SYSCTL_SRCR1_I2C1 0x00004000 // I2C1 Reset Control.
-#define SYSCTL_SRCR1_I2C0 0x00001000 // I2C0 Reset Control.
-#define SYSCTL_SRCR1_QEI1 0x00000200 // QEI1 Reset Control.
-#define SYSCTL_SRCR1_QEI0 0x00000100 // QEI0 Reset Control.
-#define SYSCTL_SRCR1_SSI1 0x00000020 // SSI1 Reset Control.
-#define SYSCTL_SRCR1_SSI0 0x00000010 // SSI0 Reset Control.
-#define SYSCTL_SRCR1_UART2 0x00000004 // UART2 Reset Control.
-#define SYSCTL_SRCR1_UART1 0x00000002 // UART1 Reset Control.
-#define SYSCTL_SRCR1_UART0 0x00000001 // UART0 Reset Control.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_SRCR2 register.
-//
-//*****************************************************************************
-#define SYSCTL_SRCR2_EPHY0 0x40000000 // PHY0 Reset Control.
-#define SYSCTL_SRCR2_EMAC0 0x10000000 // MAC0 Reset Control.
-#define SYSCTL_SRCR2_USB0 0x00010000 // USB0 Reset Control.
-#define SYSCTL_SRCR2_UDMA 0x00002000 // UDMA Reset Control.
-#define SYSCTL_SRCR2_GPIOH 0x00000080 // Port H Reset Control.
-#define SYSCTL_SRCR2_GPIOG 0x00000040 // Port G Reset Control.
-#define SYSCTL_SRCR2_GPIOF 0x00000020 // Port F Reset Control.
-#define SYSCTL_SRCR2_GPIOE 0x00000010 // Port E Reset Control.
-#define SYSCTL_SRCR2_GPIOD 0x00000008 // Port D Reset Control.
-#define SYSCTL_SRCR2_GPIOC 0x00000004 // Port C Reset Control.
-#define SYSCTL_SRCR2_GPIOB 0x00000002 // Port B Reset Control.
-#define SYSCTL_SRCR2_GPIOA 0x00000001 // Port A Reset Control.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_RIS register.
-//
-//*****************************************************************************
-#define SYSCTL_RIS_MOSCPUPRIS 0x00000100 // MOSC Power Up Raw Interrupt
- // Status.
-#define SYSCTL_RIS_USBPLLLRIS 0x00000080 // USB PLL Lock Raw Interrupt
- // Status.
-#define SYSCTL_RIS_PLLLRIS 0x00000040 // PLL Lock Raw Interrupt Status.
-#define SYSCTL_RIS_CLRIS 0x00000020 // Current Limit Raw Interrupt
- // Status.
-#define SYSCTL_RIS_IOFRIS 0x00000010 // Internal Oscillator Fault Raw
- // Interrupt Status.
-#define SYSCTL_RIS_MOFRIS 0x00000008 // Main Oscillator Fault Raw
- // Interrupt Status.
-#define SYSCTL_RIS_LDORIS 0x00000004 // LDO Power Unregulated Raw
- // Interrupt Status.
-#define SYSCTL_RIS_BORRIS 0x00000002 // Brown-Out Reset Raw Interrupt
- // Status.
-#define SYSCTL_RIS_PLLFRIS 0x00000001 // PLL Fault Raw Interrupt Status.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_IMC register.
-//
-//*****************************************************************************
-#define SYSCTL_IMC_MOSCPUPIM 0x00000100 // MOSC Power Up Interrupt Mask.
-#define SYSCTL_IMC_USBPLLLIM 0x00000080 // USB PLL Lock Interrupt Mask.
-#define SYSCTL_IMC_PLLLIM 0x00000040 // PLL Lock Interrupt Mask.
-#define SYSCTL_IMC_CLIM 0x00000020 // Current Limit Interrupt Mask.
-#define SYSCTL_IMC_IOFIM 0x00000010 // Internal Oscillator Fault
- // Interrupt Mask.
-#define SYSCTL_IMC_MOFIM 0x00000008 // Main Oscillator Fault Interrupt
- // Mask.
-#define SYSCTL_IMC_LDOIM 0x00000004 // LDO Power Unregulated Interrupt
- // Mask.
-#define SYSCTL_IMC_BORIM 0x00000002 // Brown-Out Reset Interrupt Mask.
-#define SYSCTL_IMC_PLLFIM 0x00000001 // PLL Fault Interrupt Mask.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_MISC register.
-//
-//*****************************************************************************
-#define SYSCTL_MISC_MOSCPUPMIS 0x00000100 // MOSC Power Up Masked Interrupt
- // Status.
-#define SYSCTL_MISC_USBPLLLMIS 0x00000080 // USB PLL Lock Masked Interrupt
- // Status.
-#define SYSCTL_MISC_PLLLMIS 0x00000040 // PLL Lock Masked Interrupt
- // Status.
-#define SYSCTL_MISC_CLMIS 0x00000020 // Current Limit Masked Interrupt
- // Status.
-#define SYSCTL_MISC_IOFMIS 0x00000010 // Internal Oscillator Fault Masked
- // Interrupt Status.
-#define SYSCTL_MISC_MOFMIS 0x00000008 // Main Oscillator Fault Masked
- // Interrupt Status.
-#define SYSCTL_MISC_LDOMIS 0x00000004 // LDO Power Unregulated Masked
- // Interrupt Status.
-#define SYSCTL_MISC_BORMIS 0x00000002 // BOR Masked Interrupt Status.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_RCGC0 register.
-//
-//*****************************************************************************
-#define SYSCTL_RCGC0_CAN2 0x04000000 // CAN2 Clock Gating Control.
-#define SYSCTL_RCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control.
-#define SYSCTL_RCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control.
-#define SYSCTL_RCGC0_PWM 0x00100000 // PWM Clock Gating Control.
-#define SYSCTL_RCGC0_ADC 0x00010000 // ADC0 Clock Gating Control.
-#define SYSCTL_RCGC0_ADCSPD_M 0x00000F00 // ADC Sample Speed.
-#define SYSCTL_RCGC0_ADCSPD125K 0x00000000 // 125K samples/second
-#define SYSCTL_RCGC0_ADCSPD250K 0x00000100 // 250K samples/second
-#define SYSCTL_RCGC0_ADCSPD500K 0x00000200 // 500K samples/second
-#define SYSCTL_RCGC0_ADCSPD1M 0x00000300 // 1M samples/second
-#define SYSCTL_RCGC0_HIB 0x00000040 // HIB Clock Gating Control.
-#define SYSCTL_RCGC0_WDT 0x00000008 // WDT Clock Gating Control.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_RCGC1 register.
-//
-//*****************************************************************************
-#define SYSCTL_RCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock
- // Gating.
-#define SYSCTL_RCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock
- // Gating.
-#define SYSCTL_RCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock
- // Gating.
-#define SYSCTL_RCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control.
-#define SYSCTL_RCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control.
-#define SYSCTL_RCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control.
-#define SYSCTL_RCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control.
-#define SYSCTL_RCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control.
-#define SYSCTL_RCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control.
-#define SYSCTL_RCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control.
-#define SYSCTL_RCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control.
-#define SYSCTL_RCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control.
-#define SYSCTL_RCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control.
-#define SYSCTL_RCGC1_UART2 0x00000004 // UART2 Clock Gating Control.
-#define SYSCTL_RCGC1_UART1 0x00000002 // UART1 Clock Gating Control.
-#define SYSCTL_RCGC1_UART0 0x00000001 // UART0 Clock Gating Control.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_RCGC2 register.
-//
-//*****************************************************************************
-#define SYSCTL_RCGC2_EPHY0 0x40000000 // PHY0 Clock Gating Control.
-#define SYSCTL_RCGC2_EMAC0 0x10000000 // MAC0 Clock Gating Control.
-#define SYSCTL_RCGC2_USB0 0x00010000 // USB0 Clock Gating Control.
-#define SYSCTL_RCGC2_UDMA 0x00002000 // UDMA Clock Gating Control.
-#define SYSCTL_RCGC2_GPIOH 0x00000080 // Port H Clock Gating Control.
-#define SYSCTL_RCGC2_GPIOG 0x00000040 // Port G Clock Gating Control.
-#define SYSCTL_RCGC2_GPIOF 0x00000020 // Port F Clock Gating Control.
-#define SYSCTL_RCGC2_GPIOE 0x00000010 // Port E Clock Gating Control.
-#define SYSCTL_RCGC2_GPIOD 0x00000008 // Port D Clock Gating Control.
-#define SYSCTL_RCGC2_GPIOC 0x00000004 // Port C Clock Gating Control.
-#define SYSCTL_RCGC2_GPIOB 0x00000002 // Port B Clock Gating Control.
-#define SYSCTL_RCGC2_GPIOA 0x00000001 // Port A Clock Gating Control.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_SCGC0 register.
-//
-//*****************************************************************************
-#define SYSCTL_SCGC0_CAN2 0x04000000 // CAN2 Clock Gating Control.
-#define SYSCTL_SCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control.
-#define SYSCTL_SCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control.
-#define SYSCTL_SCGC0_PWM 0x00100000 // PWM Clock Gating Control.
-#define SYSCTL_SCGC0_ADC 0x00010000 // ADC0 Clock Gating Control.
-#define SYSCTL_SCGC0_ADCSPD_M 0x00000F00 // ADC Sample Speed.
-#define SYSCTL_SCGC0_ADCSPD125K 0x00000000 // 125K samples/second
-#define SYSCTL_SCGC0_ADCSPD250K 0x00000100 // 250K samples/second
-#define SYSCTL_SCGC0_ADCSPD500K 0x00000200 // 500K samples/second
-#define SYSCTL_SCGC0_ADCSPD1M 0x00000300 // 1M samples/second
-#define SYSCTL_SCGC0_HIB 0x00000040 // HIB Clock Gating Control.
-#define SYSCTL_SCGC0_WDT 0x00000008 // WDT Clock Gating Control.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_SCGC1 register.
-//
-//*****************************************************************************
-#define SYSCTL_SCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock
- // Gating.
-#define SYSCTL_SCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock
- // Gating.
-#define SYSCTL_SCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock
- // Gating.
-#define SYSCTL_SCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control.
-#define SYSCTL_SCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control.
-#define SYSCTL_SCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control.
-#define SYSCTL_SCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control.
-#define SYSCTL_SCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control.
-#define SYSCTL_SCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control.
-#define SYSCTL_SCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control.
-#define SYSCTL_SCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control.
-#define SYSCTL_SCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control.
-#define SYSCTL_SCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control.
-#define SYSCTL_SCGC1_UART2 0x00000004 // UART2 Clock Gating Control.
-#define SYSCTL_SCGC1_UART1 0x00000002 // UART1 Clock Gating Control.
-#define SYSCTL_SCGC1_UART0 0x00000001 // UART0 Clock Gating Control.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_SCGC2 register.
-//
-//*****************************************************************************
-#define SYSCTL_SCGC2_EPHY0 0x40000000 // PHY0 Clock Gating Control.
-#define SYSCTL_SCGC2_EMAC0 0x10000000 // MAC0 Clock Gating Control.
-#define SYSCTL_SCGC2_USB0 0x00010000 // USB0 Clock Gating Control.
-#define SYSCTL_SCGC2_UDMA 0x00002000 // UDMA Clock Gating Control.
-#define SYSCTL_SCGC2_GPIOH 0x00000080 // Port H Clock Gating Control.
-#define SYSCTL_SCGC2_GPIOG 0x00000040 // Port G Clock Gating Control.
-#define SYSCTL_SCGC2_GPIOF 0x00000020 // Port F Clock Gating Control.
-#define SYSCTL_SCGC2_GPIOE 0x00000010 // Port E Clock Gating Control.
-#define SYSCTL_SCGC2_GPIOD 0x00000008 // Port D Clock Gating Control.
-#define SYSCTL_SCGC2_GPIOC 0x00000004 // Port C Clock Gating Control.
-#define SYSCTL_SCGC2_GPIOB 0x00000002 // Port B Clock Gating Control.
-#define SYSCTL_SCGC2_GPIOA 0x00000001 // Port A Clock Gating Control.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_DCGC0 register.
-//
-//*****************************************************************************
-#define SYSCTL_DCGC0_CAN2 0x04000000 // CAN2 Clock Gating Control.
-#define SYSCTL_DCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control.
-#define SYSCTL_DCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control.
-#define SYSCTL_DCGC0_PWM 0x00100000 // PWM Clock Gating Control.
-#define SYSCTL_DCGC0_ADC 0x00010000 // ADC0 Clock Gating Control.
-#define SYSCTL_DCGC0_ADCSPD_M 0x00000F00 // ADC Sample Speed.
-#define SYSCTL_DCGC0_ADCSPD125K 0x00000000 // 125K samples/second
-#define SYSCTL_DCGC0_ADCSPD250K 0x00000100 // 250K samples/second
-#define SYSCTL_DCGC0_ADCSPD500K 0x00000200 // 500K samples/second
-#define SYSCTL_DCGC0_ADCSPD1M 0x00000300 // 1M samples/second
-#define SYSCTL_DCGC0_HIB 0x00000040 // HIB Clock Gating Control.
-#define SYSCTL_DCGC0_WDT 0x00000008 // WDT Clock Gating Control.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_DCGC1 register.
-//
-//*****************************************************************************
-#define SYSCTL_DCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock
- // Gating.
-#define SYSCTL_DCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock
- // Gating.
-#define SYSCTL_DCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock
- // Gating.
-#define SYSCTL_DCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control.
-#define SYSCTL_DCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control.
-#define SYSCTL_DCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control.
-#define SYSCTL_DCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control.
-#define SYSCTL_DCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control.
-#define SYSCTL_DCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control.
-#define SYSCTL_DCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control.
-#define SYSCTL_DCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control.
-#define SYSCTL_DCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control.
-#define SYSCTL_DCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control.
-#define SYSCTL_DCGC1_UART2 0x00000004 // UART2 Clock Gating Control.
-#define SYSCTL_DCGC1_UART1 0x00000002 // UART1 Clock Gating Control.
-#define SYSCTL_DCGC1_UART0 0x00000001 // UART0 Clock Gating Control.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_DCGC2 register.
-//
-//*****************************************************************************
-#define SYSCTL_DCGC2_EPHY0 0x40000000 // PHY0 Clock Gating Control.
-#define SYSCTL_DCGC2_EMAC0 0x10000000 // MAC0 Clock Gating Control.
-#define SYSCTL_DCGC2_USB0 0x00010000 // USB0 Clock Gating Control.
-#define SYSCTL_DCGC2_UDMA 0x00002000 // UDMA Clock Gating Control.
-#define SYSCTL_DCGC2_GPIOH 0x00000080 // Port H Clock Gating Control.
-#define SYSCTL_DCGC2_GPIOG 0x00000040 // Port G Clock Gating Control.
-#define SYSCTL_DCGC2_GPIOF 0x00000020 // Port F Clock Gating Control.
-#define SYSCTL_DCGC2_GPIOE 0x00000010 // Port E Clock Gating Control.
-#define SYSCTL_DCGC2_GPIOD 0x00000008 // Port D Clock Gating Control.
-#define SYSCTL_DCGC2_GPIOC 0x00000004 // Port C Clock Gating Control.
-#define SYSCTL_DCGC2_GPIOB 0x00000002 // Port B Clock Gating Control.
-#define SYSCTL_DCGC2_GPIOA 0x00000001 // Port A Clock Gating Control.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_DC5 register.
-//
-//*****************************************************************************
-#define SYSCTL_DC5_PWMFAULT3 0x08000000 // PWM Fault 3 Pin Present.
-#define SYSCTL_DC5_PWMFAULT2 0x04000000 // PWM Fault 2 Pin Present.
-#define SYSCTL_DC5_PWMFAULT1 0x02000000 // PWM Fault 1 Pin Present.
-#define SYSCTL_DC5_PWMFAULT0 0x01000000 // PWM Fault 0 Pin Present.
-#define SYSCTL_DC5_PWMEFLT 0x00200000 // PWM Extended Fault feature is
- // active.
-#define SYSCTL_DC5_PWMESYNC 0x00100000 // PWM Extended SYNC feature is
- // active.
-#define SYSCTL_DC5_PWM7 0x00000080 // PWM7 Pin Present.
-#define SYSCTL_DC5_PWM6 0x00000040 // PWM6 Pin Present.
-#define SYSCTL_DC5_PWM5 0x00000020 // PWM5 Pin Present.
-#define SYSCTL_DC5_PWM4 0x00000010 // PWM4 Pin Present.
-#define SYSCTL_DC5_PWM3 0x00000008 // PWM3 Pin Present.
-#define SYSCTL_DC5_PWM2 0x00000004 // PWM2 Pin Present.
-#define SYSCTL_DC5_PWM1 0x00000002 // PWM1 Pin Present.
-#define SYSCTL_DC5_PWM0 0x00000001 // PWM0 Pin Present.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_DC6 register.
-//
-//*****************************************************************************
-#define SYSCTL_DC6_USB0_M 0x00000003 // This specifies that USB0 is
- // present and its capability.
-#define SYSCTL_DC6_USB0_HOSTDEV 0x00000002 // USB is DEVICE or HOST
-#define SYSCTL_DC6_USB0_OTG 0x00000003 // USB is OTG
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_GPIOHSCTL
-// register.
-//
-//*****************************************************************************
-#define SYSCTL_GPIOHSCTL_PORTH 0x00000080 // Port H High-Speed.
-#define SYSCTL_GPIOHSCTL_PORTG 0x00000040 // Port G High-Speed.
-#define SYSCTL_GPIOHSCTL_PORTF 0x00000020 // Port F High-Speed.
-#define SYSCTL_GPIOHSCTL_PORTE 0x00000010 // Port E High-Speed.
-#define SYSCTL_GPIOHSCTL_PORTD 0x00000008 // Port D High-Speed.
-#define SYSCTL_GPIOHSCTL_PORTC 0x00000004 // Port C High-Speed.
-#define SYSCTL_GPIOHSCTL_PORTB 0x00000002 // Port B High-Speed.
-#define SYSCTL_GPIOHSCTL_PORTA 0x00000001 // Port A High-Speed.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_MOSCCTL register.
-//
-//*****************************************************************************
-#define SYSCTL_MOSCCTL_CVAL 0x00000001 // Clock Validation for MOSC.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_DC7 register.
-//
-//*****************************************************************************
-#define SYSCTL_DC7_SSI1_TX 0x02000000 // SSI1 TX on uDMA Ch25.
-#define SYSCTL_DC7_SSI1_RX 0x01000000 // SSI1 RX on uDMA Ch24.
-#define SYSCTL_DC7_UART1_TX 0x00800000 // UART1 TX on uDMA Ch23.
-#define SYSCTL_DC7_UART1_RX 0x00400000 // UART1 RX on uDMA Ch22.
-#define SYSCTL_DC7_SSI0_TX 0x00000800 // SSI0 TX on uDMA Ch11.
-#define SYSCTL_DC7_SSI0_RX 0x00000400 // SSI0 RX on uDMA Ch10.
-#define SYSCTL_DC7_UART0_TX 0x00000200 // UART0 TX on uDMA Ch9.
-#define SYSCTL_DC7_UART0_RX 0x00000100 // UART0 RX on uDMA Ch8.
-#define SYSCTL_DC7_USB_EP3_TX 0x00000020 // USB EP3 TX on uDMA Ch5.
-#define SYSCTL_DC7_USB_EP3_RX 0x00000010 // USB EP3 RX on uDMA Ch4.
-#define SYSCTL_DC7_USB_EP2_TX 0x00000008 // USB EP2 TX on uDMA Ch3.
-#define SYSCTL_DC7_USB_EP2_RX 0x00000004 // USB EP2 RX on uDMA Ch2.
-#define SYSCTL_DC7_USB_EP1_TX 0x00000002 // USB EP1 TX on uDMA Ch1.
-#define SYSCTL_DC7_USB_EP1_RX 0x00000001 // USB EP1 RX on uDMA Ch0.
-
-//*****************************************************************************
-//
-// The following definitions are deprecated.
-//
-//*****************************************************************************
-#ifndef DEPRECATED
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the system control register
-// addresses.
-//
-//*****************************************************************************
-#define SYSCTL_USER0 0x400FE1E0 // NV User Register 0
-#define SYSCTL_USER1 0x400FE1E4 // NV User Register 1
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the SYSCTL_DID0
-// register.
-//
-//*****************************************************************************
-#define SYSCTL_DID0_VER_MASK 0x70000000 // DID0 version mask
-#define SYSCTL_DID0_CLASS_MASK 0x00FF0000 // Device Class
-#define SYSCTL_DID0_MAJ_MASK 0x0000FF00 // Major revision mask
-#define SYSCTL_DID0_MAJ_A 0x00000000 // Major revision A
-#define SYSCTL_DID0_MAJ_B 0x00000100 // Major revision B
-#define SYSCTL_DID0_MAJ_C 0x00000200 // Major revision C
-#define SYSCTL_DID0_MIN_MASK 0x000000FF // Minor revision mask
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the SYSCTL_DID1
-// register.
-//
-//*****************************************************************************
-#define SYSCTL_DID1_VER_MASK 0xF0000000 // Register version mask
-#define SYSCTL_DID1_FAM_MASK 0x0F000000 // Family mask
-#define SYSCTL_DID1_FAM_S 0x00000000 // Stellaris family
-#define SYSCTL_DID1_PRTNO_MASK 0x00FF0000 // Part number mask
-#define SYSCTL_DID1_PINCNT_MASK 0x0000E000 // Pin count
-#define SYSCTL_DID1_TEMP_MASK 0x000000E0 // Temperature range mask
-#define SYSCTL_DID1_PKG_MASK 0x00000018 // Package mask
-#define SYSCTL_DID1_QUAL_MASK 0x00000003 // Qualification status mask
-#define SYSCTL_DID1_PRTNO_SHIFT 16
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the SYSCTL_DC0
-// register.
-//
-//*****************************************************************************
-#define SYSCTL_DC0_SRAMSZ_MASK 0xFFFF0000 // SRAM size mask
-#define SYSCTL_DC0_FLASHSZ_MASK 0x0000FFFF // Flash size mask
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the SYSCTL_DC1
-// register.
-//
-//*****************************************************************************
-#define SYSCTL_DC1_SYSDIV_MASK 0x0000F000 // Minimum system divider mask
-#define SYSCTL_DC1_ADCSPD_MASK 0x00000F00 // ADC speed mask
-#define SYSCTL_DC1_WDOG 0x00000008 // Watchdog present
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the SYSCTL_DC2
-// register.
-//
-//*****************************************************************************
-#define SYSCTL_DC2_I2C 0x00001000 // I2C present
-#define SYSCTL_DC2_QEI 0x00000100 // QEI present
-#define SYSCTL_DC2_SSI 0x00000010 // SSI present
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the SYSCTL_DC3
-// register.
-//
-//*****************************************************************************
-#define SYSCTL_DC3_MC_FAULT0 0x00008000 // MC0 fault pin present
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the
-// SYSCTL_PBORCTL register.
-//
-//*****************************************************************************
-#define SYSCTL_PBORCTL_BOR_MASK 0x0000FFFC // BOR wait timer
-#define SYSCTL_PBORCTL_BOR_SH 2
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the
-// SYSCTL_LDOPCTL register.
-//
-//*****************************************************************************
-#define SYSCTL_LDOPCTL_MASK 0x0000003F // Voltage adjust mask
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the SYSCTL_SRCR0,
-// SYSCTL_RCGC0, SYSCTL_SCGC0, and SYSCTL_DCGC0 registers.
-//
-//*****************************************************************************
-#define SYSCTL_SET0_CAN2 0x04000000 // CAN 2 module
-#define SYSCTL_SET0_CAN1 0x02000000 // CAN 1 module
-#define SYSCTL_SET0_CAN0 0x01000000 // CAN 0 module
-#define SYSCTL_SET0_PWM 0x00100000 // PWM module
-#define SYSCTL_SET0_ADC 0x00010000 // ADC module
-#define SYSCTL_SET0_ADCSPD_MASK 0x00000F00 // ADC speed mask
-#define SYSCTL_SET0_ADCSPD_125K 0x00000000 // 125Ksps ADC
-#define SYSCTL_SET0_ADCSPD_250K 0x00000100 // 250Ksps ADC
-#define SYSCTL_SET0_ADCSPD_500K 0x00000200 // 500Ksps ADC
-#define SYSCTL_SET0_ADCSPD_1M 0x00000300 // 1Msps ADC
-#define SYSCTL_SET0_HIB 0x00000040 // Hibernation module
-#define SYSCTL_SET0_WDOG 0x00000008 // Watchdog module
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the SYSCTL_SRCR1,
-// SYSCTL_RCGC1, SYSCTL_SCGC1, and SYSCTL_DCGC1 registers.
-//
-//*****************************************************************************
-#define SYSCTL_SET1_COMP2 0x04000000 // Analog comparator module 2
-#define SYSCTL_SET1_COMP1 0x02000000 // Analog comparator module 1
-#define SYSCTL_SET1_COMP0 0x01000000 // Analog comparator module 0
-#define SYSCTL_SET1_TIMER3 0x00080000 // Timer module 3
-#define SYSCTL_SET1_TIMER2 0x00040000 // Timer module 2
-#define SYSCTL_SET1_TIMER1 0x00020000 // Timer module 1
-#define SYSCTL_SET1_TIMER0 0x00010000 // Timer module 0
-#define SYSCTL_SET1_I2C1 0x00002000 // I2C module 1
-#define SYSCTL_SET1_I2C0 0x00001000 // I2C module 0
-#define SYSCTL_SET1_I2C 0x00001000 // I2C module
-#define SYSCTL_SET1_QEI1 0x00000200 // QEI module 1
-#define SYSCTL_SET1_QEI 0x00000100 // QEI module
-#define SYSCTL_SET1_QEI0 0x00000100 // QEI module 0
-#define SYSCTL_SET1_SSI1 0x00000020 // SSI module 1
-#define SYSCTL_SET1_SSI0 0x00000010 // SSI module 0
-#define SYSCTL_SET1_SSI 0x00000010 // SSI module
-#define SYSCTL_SET1_UART2 0x00000004 // UART module 2
-#define SYSCTL_SET1_UART1 0x00000002 // UART module 1
-#define SYSCTL_SET1_UART0 0x00000001 // UART module 0
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the SYSCTL_SRCR2,
-// SYSCTL_RCGC2, SYSCTL_SCGC2, and SYSCTL_DCGC2 registers.
-//
-//*****************************************************************************
-#define SYSCTL_SET2_ETH 0x50000000 // ETH module
-#define SYSCTL_SET2_GPIOH 0x00000080 // GPIO H module
-#define SYSCTL_SET2_GPIOG 0x00000040 // GPIO G module
-#define SYSCTL_SET2_GPIOF 0x00000020 // GPIO F module
-#define SYSCTL_SET2_GPIOE 0x00000010 // GPIO E module
-#define SYSCTL_SET2_GPIOD 0x00000008 // GPIO D module
-#define SYSCTL_SET2_GPIOC 0x00000004 // GPIO C module
-#define SYSCTL_SET2_GPIOB 0x00000002 // GPIO B module
-#define SYSCTL_SET2_GPIOA 0x00000001 // GIPO A module
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the SYSCTL_RIS,
-// SYSCTL_IMC, and SYSCTL_IMS registers.
-//
-//*****************************************************************************
-#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt
-#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt
-#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int
-#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int
-#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt
-#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt
-#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the SYSCTL_RESC
-// register.
-//
-//*****************************************************************************
-#define SYSCTL_RESC_WDOG 0x00000008 // Watchdog reset
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the SYSCTL_RCC
-// register.
-//
-//*****************************************************************************
-#define SYSCTL_RCC_SYSDIV_MASK 0x07800000 // System clock divider
-#define SYSCTL_RCC_USE_SYSDIV 0x00400000 // Use sytem clock divider
-#define SYSCTL_RCC_USE_PWMDIV 0x00100000 // Use PWM clock divider
-#define SYSCTL_RCC_PWMDIV_MASK 0x000E0000 // PWM clock divider
-#define SYSCTL_RCC_OE 0x00001000 // PLL output enable
-#define SYSCTL_RCC_XTAL_3_68MHz 0x00000140 // Using a 3.6864 MHz crystal
-#define SYSCTL_RCC_XTAL_4MHz 0x00000180 // Using a 4 MHz crystal
-#define SYSCTL_RCC_XTAL_MASK 0x000003C0 // Crystal attached to main osc
-#define SYSCTL_RCC_OSCSRC_MASK 0x00000030 // Oscillator input select
-#define SYSCTL_RCC_SYSDIV_SHIFT 23 // Shift to the SYSDIV field
-#define SYSCTL_RCC_PWMDIV_SHIFT 17 // Shift to the PWMDIV field
-#define SYSCTL_RCC_XTAL_SHIFT 6 // Shift to the XTAL field
-#define SYSCTL_RCC_OSCSRC_SHIFT 4 // Shift to the OSCSRC field
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the SYSCTL_PLLCFG
-// register.
-//
-//*****************************************************************************
-#define SYSCTL_PLLCFG_OD_MASK 0x0000C000 // Output divider
-#define SYSCTL_PLLCFG_F_MASK 0x00003FE0 // PLL multiplier
-#define SYSCTL_PLLCFG_R_MASK 0x0000001F // Input predivider
-#define SYSCTL_PLLCFG_F_SHIFT 5
-#define SYSCTL_PLLCFG_R_SHIFT 0
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the SYSCTL_RCC2
-// register.
-//
-//*****************************************************************************
-#define SYSCTL_RCC2_SYSDIV2_MSK 0x1F800000 // System clock divider
-#define SYSCTL_RCC2_OSCSRC2_MSK 0x00000070 // Oscillator input select
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the
-// SYSCTL_DSLPCLKCFG register.
-//
-//*****************************************************************************
-#define SYSCTL_DSLPCLKCFG_D_MSK 0x1F800000 // Deep sleep system clock override
-#define SYSCTL_DSLPCLKCFG_O_MSK 0x00000070 // Deep sleep oscillator override
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the
-// SYSCTL_CLKVCLR register.
-//
-//*****************************************************************************
-#define SYSCTL_CLKVCLR_CLR 0x00000001 // Clear clock verification fault
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the
-// SYSCTL_LDOARST register.
-//
-//*****************************************************************************
-#define SYSCTL_LDOARST_ARST 0x00000001 // Allow LDO to reset device
-
-#endif
-
-#endif // __HW_SYSCTL_H__
+//*****************************************************************************
+//
+// hw_sysctl.h - Macros used when accessing the system control hardware.
+//
+// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4781 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_SYSCTL_H__
+#define __HW_SYSCTL_H__
+
+//*****************************************************************************
+//
+// The following are defines for the system control register addresses.
+//
+//*****************************************************************************
+#define SYSCTL_DID0 0x400FE000 // Device identification register 0
+#define SYSCTL_DID1 0x400FE004 // Device identification register 1
+#define SYSCTL_DC0 0x400FE008 // Device capabilities register 0
+#define SYSCTL_DC1 0x400FE010 // Device capabilities register 1
+#define SYSCTL_DC2 0x400FE014 // Device capabilities register 2
+#define SYSCTL_DC3 0x400FE018 // Device capabilities register 3
+#define SYSCTL_DC4 0x400FE01C // Device capabilities register 4
+#define SYSCTL_DC5 0x400FE020 // Device capabilities register 5
+#define SYSCTL_DC6 0x400FE024 // Device capabilities register 6
+#define SYSCTL_DC7 0x400FE028 // Device capabilities register 7
+#define SYSCTL_DC8 0x400FE02C // Device capabilities register 8
+#define SYSCTL_PBORCTL 0x400FE030 // POR/BOR reset control register
+#define SYSCTL_LDOPCTL 0x400FE034 // LDO power control register
+#define SYSCTL_SRCR0 0x400FE040 // Software reset control reg 0
+#define SYSCTL_SRCR1 0x400FE044 // Software reset control reg 1
+#define SYSCTL_SRCR2 0x400FE048 // Software reset control reg 2
+#define SYSCTL_RIS 0x400FE050 // Raw interrupt status register
+#define SYSCTL_IMC 0x400FE054 // Interrupt mask/control register
+#define SYSCTL_MISC 0x400FE058 // Interrupt status register
+#define SYSCTL_RESC 0x400FE05C // Reset cause register
+#define SYSCTL_RCC 0x400FE060 // Run-mode clock config register
+#define SYSCTL_PLLCFG 0x400FE064 // PLL configuration register
+#define SYSCTL_GPIOHSCTL 0x400FE06C // GPIO High Speed Control
+#define SYSCTL_GPIOHBCTL 0x400FE06C // GPIO Host-Bus Control
+#define SYSCTL_RCC2 0x400FE070 // Run-mode clock config register 2
+#define SYSCTL_MOSCCTL 0x400FE07C // Main Oscillator Control
+#define SYSCTL_PIOSCCTL 0x400FE088 // Precision internal oscillator
+ // control register
+#define SYSCTL_RCGC0 0x400FE100 // Run-mode clock gating register 0
+#define SYSCTL_RCGC1 0x400FE104 // Run-mode clock gating register 1
+#define SYSCTL_RCGC2 0x400FE108 // Run-mode clock gating register 2
+#define SYSCTL_SCGC0 0x400FE110 // Sleep-mode clock gating reg 0
+#define SYSCTL_SCGC1 0x400FE114 // Sleep-mode clock gating reg 1
+#define SYSCTL_SCGC2 0x400FE118 // Sleep-mode clock gating reg 2
+#define SYSCTL_DCGC0 0x400FE120 // Deep Sleep-mode clock gate reg 0
+#define SYSCTL_DCGC1 0x400FE124 // Deep Sleep-mode clock gate reg 1
+#define SYSCTL_DCGC2 0x400FE128 // Deep Sleep-mode clock gate reg 2
+#define SYSCTL_DSLPCLKCFG 0x400FE144 // Deep Sleep-mode clock config reg
+#define SYSCTL_DSFLASHCFG 0x400FE14C // Deep Sleep Flash Configuration
+#define SYSCTL_CLKVCLR 0x400FE150 // Clock verifcation clear register
+#define SYSCTL_PIOSCCAL 0x400FE150 // Precision Internal Oscillator
+ // Calibration
+#define SYSCTL_PIOSCSTAT 0x400FE154 // Precision Internal Oscillator
+ // Statistics
+#define SYSCTL_LDOARST 0x400FE160 // LDO reset control register
+#define SYSCTL_I2SMCLKCFG 0x400FE170 // I2S MCLK Configuration
+#define SYSCTL_DC9 0x400FE190 // Device capabilities register 9
+#define SYSCTL_NVMSTAT 0x400FE1A0 // Non-Volitile Memory Information
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DID0 register.
+//
+//*****************************************************************************
+#define SYSCTL_DID0_VER_M 0x70000000 // DID0 version mask
+#define SYSCTL_DID0_VER_0 0x00000000 // DID0 version 0
+#define SYSCTL_DID0_VER_1 0x10000000 // DID0 version 1
+#define SYSCTL_DID0_CLASS_M 0x00FF0000 // Device Class
+#define SYSCTL_DID0_CLASS_SANDSTORM \
+ 0x00000000 // Sandstorm-class Device
+#define SYSCTL_DID0_CLASS_FURY 0x00010000 // Fury-class Device
+#define SYSCTL_DID0_CLASS_DUSTDEVIL \
+ 0x00030000 // DustDevil-class Device
+#define SYSCTL_DID0_CLASS_TEMPEST \
+ 0x00040000 // Tempest-class Device
+#define SYSCTL_DID0_MAJ_M 0x0000FF00 // Major revision mask
+#define SYSCTL_DID0_MAJ_REVA 0x00000000 // Revision A (initial device)
+#define SYSCTL_DID0_MAJ_REVB 0x00000100 // Revision B (first base layer
+ // revision)
+#define SYSCTL_DID0_MAJ_REVC 0x00000200 // Revision C (second base layer
+ // revision)
+#define SYSCTL_DID0_MIN_M 0x000000FF // Minor revision mask
+#define SYSCTL_DID0_MIN_0 0x00000000 // Minor revision 0
+#define SYSCTL_DID0_MIN_1 0x00000001 // Minor revision 1
+#define SYSCTL_DID0_MIN_2 0x00000002 // Minor revision 2
+#define SYSCTL_DID0_MIN_3 0x00000003 // Minor revision 3
+#define SYSCTL_DID0_MIN_4 0x00000004 // Minor revision 4
+#define SYSCTL_DID0_MIN_5 0x00000005 // Minor revision 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DID1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DID1_VER_M 0xF0000000 // DID1 Version.
+#define SYSCTL_DID1_VER_0 0x00000000 // Initial DID1 register format
+ // definition, indicating a
+ // Stellaris LM3Snnn device.
+#define SYSCTL_DID1_VER_1 0x10000000 // First revision of the DID1
+ // register format, indicating a
+ // Stellaris Fury-class device.
+#define SYSCTL_DID1_FAM_M 0x0F000000 // Family.
+#define SYSCTL_DID1_FAM_STELLARIS \
+ 0x00000000 // Stellaris family of
+ // microcontollers, that is, all
+ // devices with external part
+ // numbers starting with LM3S.
+#define SYSCTL_DID1_PRTNO_M 0x00FF0000 // Part number mask
+#define SYSCTL_DID1_PRTNO_2B93 0x006C0000 // LM3S2B93
+#define SYSCTL_DID1_PRTNO_5B91 0x00680000 // LM3S5B91
+#define SYSCTL_DID1_PRTNO_9B95 0x006E0000 // LM3S9B95
+#define SYSCTL_DID1_PRTNO_9B92 0x006A0000 // LM3S9B92
+#define SYSCTL_DID1_PRTNO_9B96 0x006F0000 // LM3S9B96
+#define SYSCTL_DID1_PRTNO_9B90 0x00660000 // LM3S9B90
+#define SYSCTL_DID1_PRTNO_101 0x00010000 // LM3S101
+#define SYSCTL_DID1_PRTNO_102 0x00020000 // LM3S102
+#define SYSCTL_DID1_PRTNO_300 0x00190000 // LM3S300
+#define SYSCTL_DID1_PRTNO_301 0x00110000 // LM3S301
+#define SYSCTL_DID1_PRTNO_308 0x001A0000 // LM3S308
+#define SYSCTL_DID1_PRTNO_310 0x00120000 // LM3S310
+#define SYSCTL_DID1_PRTNO_315 0x00130000 // LM3S315
+#define SYSCTL_DID1_PRTNO_316 0x00140000 // LM3S316
+#define SYSCTL_DID1_PRTNO_317 0x00170000 // LM3S317
+#define SYSCTL_DID1_PRTNO_328 0x00150000 // LM3S328
+#define SYSCTL_DID1_PRTNO_600 0x002A0000 // LM3S600
+#define SYSCTL_DID1_PRTNO_601 0x00210000 // LM3S601
+#define SYSCTL_DID1_PRTNO_608 0x002B0000 // LM3S608
+#define SYSCTL_DID1_PRTNO_610 0x00220000 // LM3S610
+#define SYSCTL_DID1_PRTNO_611 0x00230000 // LM3S611
+#define SYSCTL_DID1_PRTNO_612 0x00240000 // LM3S612
+#define SYSCTL_DID1_PRTNO_613 0x00250000 // LM3S613
+#define SYSCTL_DID1_PRTNO_615 0x00260000 // LM3S615
+#define SYSCTL_DID1_PRTNO_617 0x00280000 // LM3S617
+#define SYSCTL_DID1_PRTNO_618 0x00290000 // LM3S618
+#define SYSCTL_DID1_PRTNO_628 0x00270000 // LM3S628
+#define SYSCTL_DID1_PRTNO_800 0x00380000 // LM3S800
+#define SYSCTL_DID1_PRTNO_801 0x00310000 // LM3S801
+#define SYSCTL_DID1_PRTNO_808 0x00390000 // LM3S808
+#define SYSCTL_DID1_PRTNO_811 0x00320000 // LM3S811
+#define SYSCTL_DID1_PRTNO_812 0x00330000 // LM3S812
+#define SYSCTL_DID1_PRTNO_815 0x00340000 // LM3S815
+#define SYSCTL_DID1_PRTNO_817 0x00360000 // LM3S817
+#define SYSCTL_DID1_PRTNO_818 0x00370000 // LM3S818
+#define SYSCTL_DID1_PRTNO_828 0x00350000 // LM3S828
+#define SYSCTL_DID1_PRTNO_1110 0x00BF0000 // LM3S1110
+#define SYSCTL_DID1_PRTNO_1133 0x00C30000 // LM3S1133
+#define SYSCTL_DID1_PRTNO_1138 0x00C50000 // LM3S1138
+#define SYSCTL_DID1_PRTNO_1150 0x00C10000 // LM3S1150
+#define SYSCTL_DID1_PRTNO_1162 0x00C40000 // LM3S1162
+#define SYSCTL_DID1_PRTNO_1165 0x00C20000 // LM3S1165
+#define SYSCTL_DID1_PRTNO_1332 0x00C60000 // LM3S1332
+#define SYSCTL_DID1_PRTNO_1435 0x00BC0000 // LM3S1435
+#define SYSCTL_DID1_PRTNO_1439 0x00BA0000 // LM3S1439
+#define SYSCTL_DID1_PRTNO_1512 0x00BB0000 // LM3S1512
+#define SYSCTL_DID1_PRTNO_1538 0x00C70000 // LM3S1538
+#define SYSCTL_DID1_PRTNO_1601 0x00DB0000 // LM3S1601
+#define SYSCTL_DID1_PRTNO_1607 0x00060000 // LM3S1607
+#define SYSCTL_DID1_PRTNO_1608 0x00DA0000 // LM3S1608
+#define SYSCTL_DID1_PRTNO_1620 0x00C00000 // LM3S1620
+#define SYSCTL_DID1_PRTNO_1625 0x00030000 // LM3S1625
+#define SYSCTL_DID1_PRTNO_1626 0x00040000 // LM3S1626
+#define SYSCTL_DID1_PRTNO_1627 0x00050000 // LM3S1627
+#define SYSCTL_DID1_PRTNO_1635 0x00B30000 // LM3S1635
+#define SYSCTL_DID1_PRTNO_1637 0x00BD0000 // LM3S1637
+#define SYSCTL_DID1_PRTNO_1751 0x00B90000 // LM3S1751
+#define SYSCTL_DID1_PRTNO_1776 0x00100000 // LM3S1776
+#define SYSCTL_DID1_PRTNO_1850 0x00B40000 // LM3S1850
+#define SYSCTL_DID1_PRTNO_1911 0x00DD0000 // LM3S1911
+#define SYSCTL_DID1_PRTNO_1918 0x00DC0000 // LM3S1918
+#define SYSCTL_DID1_PRTNO_1937 0x00B70000 // LM3S1937
+#define SYSCTL_DID1_PRTNO_1958 0x00BE0000 // LM3S1958
+#define SYSCTL_DID1_PRTNO_1960 0x00B50000 // LM3S1960
+#define SYSCTL_DID1_PRTNO_1968 0x00B80000 // LM3S1968
+#define SYSCTL_DID1_PRTNO_2110 0x00510000 // LM3S2110
+#define SYSCTL_DID1_PRTNO_2139 0x00840000 // LM3S2139
+#define SYSCTL_DID1_PRTNO_2276 0x00390000 // LM3S2276
+#define SYSCTL_DID1_PRTNO_2410 0x00A20000 // LM3S2410
+#define SYSCTL_DID1_PRTNO_2412 0x00590000 // LM3S2412
+#define SYSCTL_DID1_PRTNO_2432 0x00560000 // LM3S2432
+#define SYSCTL_DID1_PRTNO_2533 0x005A0000 // LM3S2533
+#define SYSCTL_DID1_PRTNO_2601 0x00E10000 // LM3S2601
+#define SYSCTL_DID1_PRTNO_2608 0x00E00000 // LM3S2608
+#define SYSCTL_DID1_PRTNO_2616 0x00330000 // LM3S2616
+#define SYSCTL_DID1_PRTNO_2620 0x00570000 // LM3S2620
+#define SYSCTL_DID1_PRTNO_2637 0x00850000 // LM3S2637
+#define SYSCTL_DID1_PRTNO_2651 0x00530000 // LM3S2651
+#define SYSCTL_DID1_PRTNO_2671 0x00800000 // LM3S2671
+#define SYSCTL_DID1_PRTNO_2678 0x00500000 // LM3S2678
+#define SYSCTL_DID1_PRTNO_2730 0x00A40000 // LM3S2730
+#define SYSCTL_DID1_PRTNO_2739 0x00520000 // LM3S2739
+#define SYSCTL_DID1_PRTNO_2776 0x003A0000 // LM3S2776
+#define SYSCTL_DID1_PRTNO_2793 0x006D0000 // LM3S2793
+#define SYSCTL_DID1_PRTNO_2911 0x00E30000 // LM3S2911
+#define SYSCTL_DID1_PRTNO_2918 0x00E20000 // LM3S2918
+#define SYSCTL_DID1_PRTNO_2939 0x00540000 // LM3S2939
+#define SYSCTL_DID1_PRTNO_2948 0x008F0000 // LM3S2948
+#define SYSCTL_DID1_PRTNO_2950 0x00580000 // LM3S2950
+#define SYSCTL_DID1_PRTNO_2965 0x00550000 // LM3S2965
+#define SYSCTL_DID1_PRTNO_3651 0x00430000 // LM3S3651
+#define SYSCTL_DID1_PRTNO_3739 0x00440000 // LM3S3739
+#define SYSCTL_DID1_PRTNO_3748 0x00490000 // LM3S3748
+#define SYSCTL_DID1_PRTNO_3749 0x00450000 // LM3S3749
+#define SYSCTL_DID1_PRTNO_5632 0x00810000 // LM3S5632
+#define SYSCTL_DID1_PRTNO_5652 0x008A0000 // LM3S5652
+#define SYSCTL_DID1_PRTNO_5662 0x00910000 // LM3S5662
+#define SYSCTL_DID1_PRTNO_5732 0x00960000 // LM3S5732
+#define SYSCTL_DID1_PRTNO_5737 0x00970000 // LM3S5737
+#define SYSCTL_DID1_PRTNO_5739 0x00A00000 // LM3S5739
+#define SYSCTL_DID1_PRTNO_5747 0x00990000 // LM3S5747
+#define SYSCTL_DID1_PRTNO_5749 0x00A70000 // LM3S5749
+#define SYSCTL_DID1_PRTNO_5752 0x009A0000 // LM3S5752
+#define SYSCTL_DID1_PRTNO_5762 0x009C0000 // LM3S5762
+#define SYSCTL_DID1_PRTNO_5791 0x00690000 // LM3S5791
+#define SYSCTL_DID1_PRTNO_6100 0x00A10000 // LM3S6100
+#define SYSCTL_DID1_PRTNO_6110 0x00740000 // LM3S6110
+#define SYSCTL_DID1_PRTNO_6420 0x00A50000 // LM3S6420
+#define SYSCTL_DID1_PRTNO_6422 0x00820000 // LM3S6422
+#define SYSCTL_DID1_PRTNO_6432 0x00750000 // LM3S6432
+#define SYSCTL_DID1_PRTNO_6537 0x00760000 // LM3S6537
+#define SYSCTL_DID1_PRTNO_6610 0x00710000 // LM3S6610
+#define SYSCTL_DID1_PRTNO_6611 0x00E70000 // LM3S6611
+#define SYSCTL_DID1_PRTNO_6618 0x00E60000 // LM3S6618
+#define SYSCTL_DID1_PRTNO_6633 0x00830000 // LM3S6633
+#define SYSCTL_DID1_PRTNO_6637 0x008B0000 // LM3S6637
+#define SYSCTL_DID1_PRTNO_6730 0x00A30000 // LM3S6730
+#define SYSCTL_DID1_PRTNO_6753 0x00770000 // LM3S6753
+#define SYSCTL_DID1_PRTNO_6911 0x00E90000 // LM3S6911
+#define SYSCTL_DID1_PRTNO_6918 0x00E80000 // LM3S6918
+#define SYSCTL_DID1_PRTNO_6938 0x00890000 // LM3S6938
+#define SYSCTL_DID1_PRTNO_6950 0x00720000 // LM3S6950
+#define SYSCTL_DID1_PRTNO_6952 0x00780000 // LM3S6952
+#define SYSCTL_DID1_PRTNO_6965 0x00730000 // LM3S6965
+#define SYSCTL_DID1_PRTNO_8530 0x00640000 // LM3S8530
+#define SYSCTL_DID1_PRTNO_8538 0x008E0000 // LM3S8538
+#define SYSCTL_DID1_PRTNO_8630 0x00610000 // LM3S8630
+#define SYSCTL_DID1_PRTNO_8730 0x00630000 // LM3S8730
+#define SYSCTL_DID1_PRTNO_8733 0x008D0000 // LM3S8733
+#define SYSCTL_DID1_PRTNO_8738 0x00860000 // LM3S8738
+#define SYSCTL_DID1_PRTNO_8930 0x00650000 // LM3S8930
+#define SYSCTL_DID1_PRTNO_8933 0x008C0000 // LM3S8933
+#define SYSCTL_DID1_PRTNO_8938 0x00880000 // LM3S8938
+#define SYSCTL_DID1_PRTNO_8962 0x00A60000 // LM3S8962
+#define SYSCTL_DID1_PRTNO_8970 0x00620000 // LM3S8970
+#define SYSCTL_DID1_PRTNO_8971 0x00D70000 // LM3S8971
+#define SYSCTL_DID1_PRTNO_9790 0x00670000 // LM3S9790
+#define SYSCTL_DID1_PRTNO_9792 0x006B0000 // LM3S9792
+#define SYSCTL_DID1_PINCNT_M 0x0000E000 // Package Pin Count.
+#define SYSCTL_DID1_PINCNT_28 0x00000000 // 28 pin package
+#define SYSCTL_DID1_PINCNT_48 0x00002000 // 48 pin package
+#define SYSCTL_DID1_PINCNT_100 0x00004000 // 100 pin package
+#define SYSCTL_DID1_PINCNT_64 0x00006000 // 64 pin package
+#define SYSCTL_DID1_TEMP_M 0x000000E0 // Temperature range mask
+#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temp range (0..70C)
+#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temp range (-40..85C)
+#define SYSCTL_DID1_TEMP_E 0x00000040 // Extended temperature range (-40C
+ // to 105C)
+#define SYSCTL_DID1_PKG_M 0x00000018 // Package Type.
+#define SYSCTL_DID1_PKG_28SOIC 0x00000000 // 28-pin SOIC
+#define SYSCTL_DID1_PKG_48QFP 0x00000008 // 48-pin QFP
+#define SYSCTL_DID1_PKG_BGA 0x00000010 // BGA package
+#define SYSCTL_DID1_ROHS 0x00000004 // Part is RoHS compliant
+#define SYSCTL_DID1_QUAL_M 0x00000003 // Qualification status mask
+#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering sample (unqualified)
+#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot production (unqualified)
+#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully qualified
+#define SYSCTL_DID1_PRTNO_S 16 // Part number shift
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC0_SRAMSZ_M 0xFFFF0000 // SRAM size mask
+#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 // 4 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_8KB 0x001F0000 // 8 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_16KB 0x003F0000 // 16 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_32KB 0x007F0000 // 32 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_64KB 0x00FF0000 // 64 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_96KB 0x017F0000 // 96 KB of SRAM
+#define SYSCTL_DC0_FLASHSZ_M 0x0000FFFF // Flash size mask
+#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8 KB of flash
+#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 // 16 KB of flash
+#define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F // 32 KB of flash
+#define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F // 64 KB of flash
+#define SYSCTL_DC0_FLASHSZ_96KB 0x0000002F // 96 KB of flash
+#define SYSCTL_DC0_FLASHSZ_128K 0x0000003F // 128 KB of flash
+#define SYSCTL_DC0_FLASHSZ_256K 0x0000007F // 256 KB of flash
+#define SYSCTL_DC0_SRAMSZ_S 16 // SRAM size shift
+#define SYSCTL_DC0_FLASHSZ_S 0 // Flash size shift
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC1_WDT1 0x10000000 // Watchdog Timer1 Present.
+#define SYSCTL_DC1_CAN2 0x04000000 // CAN2 module present
+#define SYSCTL_DC1_CAN1 0x02000000 // CAN1 module present
+#define SYSCTL_DC1_CAN0 0x01000000 // CAN0 module present
+#define SYSCTL_DC1_PWM 0x00100000 // PWM module present
+#define SYSCTL_DC1_ADC1 0x00020000 // ADC Module 1 Present.
+#define SYSCTL_DC1_ADC0 0x00010000 // ADC Module 0 Present.
+#define SYSCTL_DC1_MINSYSDIV_M 0x0000F000 // System Clock Divider.
+#define SYSCTL_DC1_MINSYSDIV_100 \
+ 0x00001000 // Specifies a 100-MHz clock with a
+ // PLL divider of 2.
+#define SYSCTL_DC1_MINSYSDIV_66 0x00002000 // Specifies a 66-MHz clock with a
+ // PLL divider of 3.
+#define SYSCTL_DC1_MINSYSDIV_50 0x00003000 // Specifies a 50-MHz clock with a
+ // PLL divider of 4.
+#define SYSCTL_DC1_MINSYSDIV_25 0x00007000 // Specifies a 25-MHz clock with a
+ // PLL divider of 8.
+#define SYSCTL_DC1_MINSYSDIV_20 0x00009000 // Specifies a 20-MHz clock with a
+ // PLL divider of 10.
+#define SYSCTL_DC1_ADCSPD_M 0x00000F00 // ADC speed mask
+#define SYSCTL_DC1_ADCSPD_125K 0x00000000 // 125Ksps ADC
+#define SYSCTL_DC1_ADCSPD_250K 0x00000100 // 250Ksps ADC
+#define SYSCTL_DC1_ADCSPD_500K 0x00000200 // 500Ksps ADC
+#define SYSCTL_DC1_ADCSPD_1M 0x00000300 // 1Msps ADC
+#define SYSCTL_DC1_ADC1SPD_M 0x00000C00 // Max ADC1 Speed.
+#define SYSCTL_DC1_ADC1SPD_1M 0x00000C00 // 1M samples/second
+#define SYSCTL_DC1_ADC0SPD_M 0x00000300 // Max ADC0 Speed.
+#define SYSCTL_DC1_ADC0SPD_1M 0x00000300 // 1M samples/second
+#define SYSCTL_DC1_MPU 0x00000080 // Cortex M3 MPU present
+#define SYSCTL_DC1_HIB 0x00000040 // Hibernation module present
+#define SYSCTL_DC1_TEMP 0x00000020 // Temperature sensor present
+#define SYSCTL_DC1_PLL 0x00000010 // PLL present
+#define SYSCTL_DC1_WDT0 0x00000008 // Watchdog Timer 0 Present.
+#define SYSCTL_DC1_SWO 0x00000004 // Serial wire output present
+#define SYSCTL_DC1_SWD 0x00000002 // Serial wire debug present
+#define SYSCTL_DC1_JTAG 0x00000001 // JTAG debug present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC2_EPI0 0x40000000 // EPI0 Present.
+#define SYSCTL_DC2_I2S0 0x10000000 // I2S 0 Present.
+#define SYSCTL_DC2_COMP2 0x04000000 // Analog comparator 2 present
+#define SYSCTL_DC2_COMP1 0x02000000 // Analog comparator 1 present
+#define SYSCTL_DC2_COMP0 0x01000000 // Analog comparator 0 present
+#define SYSCTL_DC2_TIMER3 0x00080000 // Timer 3 present
+#define SYSCTL_DC2_TIMER2 0x00040000 // Timer 2 present
+#define SYSCTL_DC2_TIMER1 0x00020000 // Timer 1 present
+#define SYSCTL_DC2_TIMER0 0x00010000 // Timer 0 present
+#define SYSCTL_DC2_I2C1 0x00004000 // I2C 1 present
+#define SYSCTL_DC2_I2C0 0x00001000 // I2C 0 present
+#define SYSCTL_DC2_QEI1 0x00000200 // QEI 1 present
+#define SYSCTL_DC2_QEI0 0x00000100 // QEI 0 present
+#define SYSCTL_DC2_SSI1 0x00000020 // SSI 1 present
+#define SYSCTL_DC2_SSI0 0x00000010 // SSI 0 present
+#define SYSCTL_DC2_UART2 0x00000004 // UART 2 present
+#define SYSCTL_DC2_UART1 0x00000002 // UART 1 present
+#define SYSCTL_DC2_UART0 0x00000001 // UART 0 present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC3 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC3_32KHZ 0x80000000 // 32KHz Pin Present.
+#define SYSCTL_DC3_CCP5 0x20000000 // CCP5 pin present
+#define SYSCTL_DC3_CCP4 0x10000000 // CCP4 pin present
+#define SYSCTL_DC3_CCP3 0x08000000 // CCP3 pin present
+#define SYSCTL_DC3_CCP2 0x04000000 // CCP2 pin present
+#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 pin present
+#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 pin present
+#define SYSCTL_DC3_ADC0AIN7 0x00800000 // AIN7 Pin Present.
+#define SYSCTL_DC3_ADC0AIN6 0x00400000 // AIN6 Pin Present.
+#define SYSCTL_DC3_ADC0AIN5 0x00200000 // AIN5 Pin Present.
+#define SYSCTL_DC3_ADC0AIN4 0x00100000 // AIN4 Pin Present.
+#define SYSCTL_DC3_ADC0AIN3 0x00080000 // AIN3 Pin Present.
+#define SYSCTL_DC3_ADC0AIN2 0x00040000 // AIN2 Pin Present.
+#define SYSCTL_DC3_ADC0AIN1 0x00020000 // AIN1 Pin Present.
+#define SYSCTL_DC3_ADC0AIN0 0x00010000 // AIN0 Pin Present.
+#define SYSCTL_DC3_PWMFAULT 0x00008000 // PWM Fault Pin Present.
+#define SYSCTL_DC3_C2O 0x00004000 // C2o pin present
+#define SYSCTL_DC3_C2PLUS 0x00002000 // C2+ pin present
+#define SYSCTL_DC3_C2MINUS 0x00001000 // C2- pin present
+#define SYSCTL_DC3_C1O 0x00000800 // C1o pin present
+#define SYSCTL_DC3_C1PLUS 0x00000400 // C1+ pin present
+#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- pin present
+#define SYSCTL_DC3_C0O 0x00000100 // C0o pin present
+#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ pin present
+#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- pin present
+#define SYSCTL_DC3_PWM5 0x00000020 // PWM5 pin present
+#define SYSCTL_DC3_PWM4 0x00000010 // PWM4 pin present
+#define SYSCTL_DC3_PWM3 0x00000008 // PWM3 pin present
+#define SYSCTL_DC3_PWM2 0x00000004 // PWM2 pin present
+#define SYSCTL_DC3_PWM1 0x00000002 // PWM1 pin present
+#define SYSCTL_DC3_PWM0 0x00000001 // PWM0 pin present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC4 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC4_ETH 0x50000000 // Ethernet present
+#define SYSCTL_DC4_EPHY0 0x40000000 // Ethernet PHY0 Present.
+#define SYSCTL_DC4_EMAC0 0x10000000 // Ethernet MAC0 Present.
+#define SYSCTL_DC4_E1588 0x01000000 // 1588 Capable.
+#define SYSCTL_DC4_PICAL 0x00040000 // When set, indicates that the
+ // USER can calibrate the PIOSC
+#define SYSCTL_DC4_CCP7 0x00008000 // CCP7 Pin Present.
+#define SYSCTL_DC4_CCP6 0x00004000 // CCP6 Pin Present.
+#define SYSCTL_DC4_UDMA 0x00002000 // Micro-DMA is present.
+#define SYSCTL_DC4_ROM 0x00001000 // Internal Code ROM is present.
+#define SYSCTL_DC4_GPIOJ 0x00000100 // GPIO Port J Present.
+#define SYSCTL_DC4_GPIOH 0x00000080 // GPIO port H present
+#define SYSCTL_DC4_GPIOG 0x00000040 // GPIO port G present
+#define SYSCTL_DC4_GPIOF 0x00000020 // GPIO port F present
+#define SYSCTL_DC4_GPIOE 0x00000010 // GPIO port E present
+#define SYSCTL_DC4_GPIOD 0x00000008 // GPIO port D present
+#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO port C present
+#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO port B present
+#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO port A present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PBORCTL register.
+//
+//*****************************************************************************
+#define SYSCTL_PBORCTL_BORTIM_M 0x0000FFFC // BOR Time Delay.
+#define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR interrupt or reset
+#define SYSCTL_PBORCTL_BORWT 0x00000001 // BOR wait and check for noise
+#define SYSCTL_PBORCTL_BORTIM_S 2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_LDOPCTL register.
+//
+//*****************************************************************************
+#define SYSCTL_LDOPCTL_M 0x0000003F // LDO Output Voltage.
+#define SYSCTL_LDOPCTL_2_55V 0x0000001F // LDO output of 2.55V
+#define SYSCTL_LDOPCTL_2_60V 0x0000001E // LDO output of 2.60V
+#define SYSCTL_LDOPCTL_2_65V 0x0000001D // LDO output of 2.65V
+#define SYSCTL_LDOPCTL_2_70V 0x0000001C // LDO output of 2.70V
+#define SYSCTL_LDOPCTL_2_75V 0x0000001B // LDO output of 2.75V
+#define SYSCTL_LDOPCTL_2_25V 0x00000005 // LDO output of 2.25V
+#define SYSCTL_LDOPCTL_2_30V 0x00000004 // LDO output of 2.30V
+#define SYSCTL_LDOPCTL_2_35V 0x00000003 // LDO output of 2.35V
+#define SYSCTL_LDOPCTL_2_40V 0x00000002 // LDO output of 2.40V
+#define SYSCTL_LDOPCTL_2_45V 0x00000001 // LDO output of 2.45V
+#define SYSCTL_LDOPCTL_2_50V 0x00000000 // LDO output of 2.50V
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RESC register.
+//
+//*****************************************************************************
+#define SYSCTL_RESC_MOSCFAIL 0x00010000 // MOSC Failure Reset.
+#define SYSCTL_RESC_LDO 0x00000020 // LDO power OK lost reset
+#define SYSCTL_RESC_WDT1 0x00000020 // Watchdog Timer 1 Reset.
+#define SYSCTL_RESC_SW 0x00000010 // Software reset
+#define SYSCTL_RESC_WDT0 0x00000008 // Watchdog Timer 0 Reset.
+#define SYSCTL_RESC_BOR 0x00000004 // Brown-out reset
+#define SYSCTL_RESC_POR 0x00000002 // Power on reset
+#define SYSCTL_RESC_EXT 0x00000001 // External reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCC register.
+//
+//*****************************************************************************
+#define SYSCTL_RCC_ACG 0x08000000 // Automatic clock gating
+#define SYSCTL_RCC_SYSDIV_M 0x07800000 // System Clock Divisor.
+#define SYSCTL_RCC_SYSDIV_2 0x00800000 // System clock /2
+#define SYSCTL_RCC_SYSDIV_3 0x01000000 // System clock /3
+#define SYSCTL_RCC_SYSDIV_4 0x01800000 // System clock /4
+#define SYSCTL_RCC_SYSDIV_5 0x02000000 // System clock /5
+#define SYSCTL_RCC_SYSDIV_6 0x02800000 // System clock /6
+#define SYSCTL_RCC_SYSDIV_7 0x03000000 // System clock /7
+#define SYSCTL_RCC_SYSDIV_8 0x03800000 // System clock /8
+#define SYSCTL_RCC_SYSDIV_9 0x04000000 // System clock /9
+#define SYSCTL_RCC_SYSDIV_10 0x04800000 // System clock /10
+#define SYSCTL_RCC_SYSDIV_11 0x05000000 // System clock /11
+#define SYSCTL_RCC_SYSDIV_12 0x05800000 // System clock /12
+#define SYSCTL_RCC_SYSDIV_13 0x06000000 // System clock /13
+#define SYSCTL_RCC_SYSDIV_14 0x06800000 // System clock /14
+#define SYSCTL_RCC_SYSDIV_15 0x07000000 // System clock /15
+#define SYSCTL_RCC_SYSDIV_16 0x07800000 // System clock /16
+#define SYSCTL_RCC_USESYSDIV 0x00400000 // Enable System Clock Divider.
+#define SYSCTL_RCC_USEPWMDIV 0x00100000 // Enable PWM Clock Divisor.
+#define SYSCTL_RCC_PWMDIV_M 0x000E0000 // PWM clock divider
+#define SYSCTL_RCC_PWMDIV_2 0x00000000 // PWM clock /2
+#define SYSCTL_RCC_PWMDIV_4 0x00020000 // PWM clock /4
+#define SYSCTL_RCC_PWMDIV_8 0x00040000 // PWM clock /8
+#define SYSCTL_RCC_PWMDIV_16 0x00060000 // PWM clock /16
+#define SYSCTL_RCC_PWMDIV_32 0x00080000 // PWM clock /32
+#define SYSCTL_RCC_PWMDIV_64 0x000A0000 // PWM clock /64
+#define SYSCTL_RCC_PWRDN 0x00002000 // PLL power down
+#define SYSCTL_RCC_OEN 0x00001000 // PLL Output Enable.
+#define SYSCTL_RCC_BYPASS 0x00000800 // PLL bypass
+#define SYSCTL_RCC_XTAL_M 0x000007C0 // Crystal attached to main osc
+#define SYSCTL_RCC_XTAL_1MHZ 0x00000000 // Using a 1MHz crystal
+#define SYSCTL_RCC_XTAL_1_84MHZ 0x00000040 // Using a 1.8432MHz crystal
+#define SYSCTL_RCC_XTAL_2MHZ 0x00000080 // Using a 2MHz crystal
+#define SYSCTL_RCC_XTAL_2_45MHZ 0x000000C0 // Using a 2.4576MHz crystal
+#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100 // Using a 3.579545MHz crystal
+#define SYSCTL_RCC_XTAL_3_68MHZ 0x00000140 // Using a 3.6864MHz crystal
+#define SYSCTL_RCC_XTAL_4MHZ 0x00000180 // Using a 4MHz crystal
+#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // Using a 4.096MHz crystal
+#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // Using a 4.9152MHz crystal
+#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // Using a 5MHz crystal
+#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // Using a 5.12MHz crystal
+#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // Using a 6MHz crystal
+#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // Using a 6.144MHz crystal
+#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // Using a 7.3728MHz crystal
+#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // Using a 8MHz crystal
+#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // Using a 8.192MHz crystal
+#define SYSCTL_RCC_XTAL_10MHZ 0x00000400 // 10.0 MHz (USB)
+#define SYSCTL_RCC_XTAL_12MHZ 0x00000440 // 12.0 MHz (USB)
+#define SYSCTL_RCC_XTAL_12_2MHZ 0x00000480 // 12.288 MHz
+#define SYSCTL_RCC_XTAL_13_5MHZ 0x000004C0 // 13.56 MHz
+#define SYSCTL_RCC_XTAL_14_3MHZ 0x00000500 // 14.31818 MHz
+#define SYSCTL_RCC_XTAL_16MHZ 0x00000540 // 16.0 MHz (USB)
+#define SYSCTL_RCC_XTAL_16_3MHZ 0x00000580 // 16.384 MHz
+#define SYSCTL_RCC_PLLVER 0x00000400 // PLL verification timer enable
+#define SYSCTL_RCC_OSCSRC_M 0x00000030 // Oscillator input select
+#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // Use the main oscillator
+#define SYSCTL_RCC_OSCSRC_INT 0x00000010 // Use the internal oscillator
+#define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // Use the internal oscillator / 4
+#define SYSCTL_RCC_OSCSRC_30 0x00000030 // 30 KHz internal oscillator
+#define SYSCTL_RCC_IOSCVER 0x00000008 // Int. osc. verification timer en
+#define SYSCTL_RCC_MOSCVER 0x00000004 // Main osc. verification timer en
+#define SYSCTL_RCC_IOSCDIS 0x00000002 // Internal oscillator disable
+#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main oscillator disable
+#define SYSCTL_RCC_SYSDIV_S 23 // Shift to the SYSDIV field
+#define SYSCTL_RCC_PWMDIV_S 17 // Shift to the PWMDIV field
+#define SYSCTL_RCC_XTAL_S 6 // Shift to the XTAL field
+#define SYSCTL_RCC_OSCSRC_S 4 // Shift to the OSCSRC field
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PLLCFG register.
+//
+//*****************************************************************************
+#define SYSCTL_PLLCFG_OD_M 0x0000C000 // Output divider
+#define SYSCTL_PLLCFG_OD_1 0x00000000 // Output divider is 1
+#define SYSCTL_PLLCFG_OD_2 0x00004000 // Output divider is 2
+#define SYSCTL_PLLCFG_OD_4 0x00008000 // Output divider is 4
+#define SYSCTL_PLLCFG_F_M 0x00003FE0 // PLL F Value.
+#define SYSCTL_PLLCFG_R_M 0x0000001F // PLL R Value.
+#define SYSCTL_PLLCFG_F_S 5
+#define SYSCTL_PLLCFG_R_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCC2_USERCC2 0x80000000 // Use RCC2
+#define SYSCTL_RCC2_USEFRACT 0x40000000 // Use fractional divider
+#define SYSCTL_RCC2_SYSDIV2_M 0x1F800000 // System clock divider
+#define SYSCTL_RCC2_SYSDIV2_2 0x00800000 // System clock /2
+#define SYSCTL_RCC2_SYSDIV2_3 0x01000000 // System clock /3
+#define SYSCTL_RCC2_SYSDIV2_4 0x01800000 // System clock /4
+#define SYSCTL_RCC2_SYSDIV2_5 0x02000000 // System clock /5
+#define SYSCTL_RCC2_SYSDIV2_6 0x02800000 // System clock /6
+#define SYSCTL_RCC2_SYSDIV2_7 0x03000000 // System clock /7
+#define SYSCTL_RCC2_SYSDIV2_8 0x03800000 // System clock /8
+#define SYSCTL_RCC2_SYSDIV2_9 0x04000000 // System clock /9
+#define SYSCTL_RCC2_SYSDIV2_10 0x04800000 // System clock /10
+#define SYSCTL_RCC2_SYSDIV2_11 0x05000000 // System clock /11
+#define SYSCTL_RCC2_SYSDIV2_12 0x05800000 // System clock /12
+#define SYSCTL_RCC2_SYSDIV2_13 0x06000000 // System clock /13
+#define SYSCTL_RCC2_SYSDIV2_14 0x06800000 // System clock /14
+#define SYSCTL_RCC2_SYSDIV2_15 0x07000000 // System clock /15
+#define SYSCTL_RCC2_SYSDIV2_16 0x07800000 // System clock /16
+#define SYSCTL_RCC2_SYSDIV2_17 0x08000000 // System clock /17
+#define SYSCTL_RCC2_SYSDIV2_18 0x08800000 // System clock /18
+#define SYSCTL_RCC2_SYSDIV2_19 0x09000000 // System clock /19
+#define SYSCTL_RCC2_SYSDIV2_20 0x09800000 // System clock /20
+#define SYSCTL_RCC2_SYSDIV2_21 0x0A000000 // System clock /21
+#define SYSCTL_RCC2_SYSDIV2_22 0x0A800000 // System clock /22
+#define SYSCTL_RCC2_SYSDIV2_23 0x0B000000 // System clock /23
+#define SYSCTL_RCC2_SYSDIV2_24 0x0B800000 // System clock /24
+#define SYSCTL_RCC2_SYSDIV2_25 0x0C000000 // System clock /25
+#define SYSCTL_RCC2_SYSDIV2_26 0x0C800000 // System clock /26
+#define SYSCTL_RCC2_SYSDIV2_27 0x0D000000 // System clock /27
+#define SYSCTL_RCC2_SYSDIV2_28 0x0D800000 // System clock /28
+#define SYSCTL_RCC2_SYSDIV2_29 0x0E000000 // System clock /29
+#define SYSCTL_RCC2_SYSDIV2_30 0x0E800000 // System clock /30
+#define SYSCTL_RCC2_SYSDIV2_31 0x0F000000 // System clock /31
+#define SYSCTL_RCC2_SYSDIV2_32 0x0F800000 // System clock /32
+#define SYSCTL_RCC2_SYSDIV2_33 0x10000000 // System clock /33
+#define SYSCTL_RCC2_SYSDIV2_34 0x10800000 // System clock /34
+#define SYSCTL_RCC2_SYSDIV2_35 0x11000000 // System clock /35
+#define SYSCTL_RCC2_SYSDIV2_36 0x11800000 // System clock /36
+#define SYSCTL_RCC2_SYSDIV2_37 0x12000000 // System clock /37
+#define SYSCTL_RCC2_SYSDIV2_38 0x12800000 // System clock /38
+#define SYSCTL_RCC2_SYSDIV2_39 0x13000000 // System clock /39
+#define SYSCTL_RCC2_SYSDIV2_40 0x13800000 // System clock /40
+#define SYSCTL_RCC2_SYSDIV2_41 0x14000000 // System clock /41
+#define SYSCTL_RCC2_SYSDIV2_42 0x14800000 // System clock /42
+#define SYSCTL_RCC2_SYSDIV2_43 0x15000000 // System clock /43
+#define SYSCTL_RCC2_SYSDIV2_44 0x15800000 // System clock /44
+#define SYSCTL_RCC2_SYSDIV2_45 0x16000000 // System clock /45
+#define SYSCTL_RCC2_SYSDIV2_46 0x16800000 // System clock /46
+#define SYSCTL_RCC2_SYSDIV2_47 0x17000000 // System clock /47
+#define SYSCTL_RCC2_SYSDIV2_48 0x17800000 // System clock /48
+#define SYSCTL_RCC2_SYSDIV2_49 0x18000000 // System clock /49
+#define SYSCTL_RCC2_SYSDIV2_50 0x18800000 // System clock /50
+#define SYSCTL_RCC2_SYSDIV2_51 0x19000000 // System clock /51
+#define SYSCTL_RCC2_SYSDIV2_52 0x19800000 // System clock /52
+#define SYSCTL_RCC2_SYSDIV2_53 0x1A000000 // System clock /53
+#define SYSCTL_RCC2_SYSDIV2_54 0x1A800000 // System clock /54
+#define SYSCTL_RCC2_SYSDIV2_55 0x1B000000 // System clock /55
+#define SYSCTL_RCC2_SYSDIV2_56 0x1B800000 // System clock /56
+#define SYSCTL_RCC2_SYSDIV2_57 0x1C000000 // System clock /57
+#define SYSCTL_RCC2_SYSDIV2_58 0x1C800000 // System clock /58
+#define SYSCTL_RCC2_SYSDIV2_59 0x1D000000 // System clock /59
+#define SYSCTL_RCC2_SYSDIV2_60 0x1D800000 // System clock /60
+#define SYSCTL_RCC2_SYSDIV2_61 0x1E000000 // System clock /61
+#define SYSCTL_RCC2_SYSDIV2_62 0x1E800000 // System clock /62
+#define SYSCTL_RCC2_SYSDIV2_63 0x1F000000 // System clock /63
+#define SYSCTL_RCC2_SYSDIV2_64 0x1F800000 // System clock /64
+#define SYSCTL_RCC2_FRACT 0x00400000 // Fractional divide
+#define SYSCTL_RCC2_USBPWRDN 0x00004000 // Power-Down USB PLL.
+#define SYSCTL_RCC2_PWRDN2 0x00002000 // PLL power down
+#define SYSCTL_RCC2_BYPASS2 0x00000800 // PLL bypass
+#define SYSCTL_RCC2_OSCSRC2_M 0x00000070 // System Clock Source.
+#define SYSCTL_RCC2_OSCSRC2_MO 0x00000000 // Use the main oscillator
+#define SYSCTL_RCC2_OSCSRC2_IO 0x00000010 // Use the internal oscillator
+#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020 // Use the internal oscillator / 4
+#define SYSCTL_RCC2_OSCSRC2_30 0x00000030 // Use the 30 KHz internal osc.
+#define SYSCTL_RCC2_OSCSRC2_419 0x00000060 // Use the 4.19 MHz external osc.
+#define SYSCTL_RCC2_OSCSRC2_32 0x00000070 // Use the 32 KHz external osc.
+#define SYSCTL_RCC2_SYSDIV2_S 23 // Shift to the SYSDIV2 field
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DSLPCLKCFG
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DSLPCLKCFG_D_M 0x1F800000 // Divider Field Override.
+#define SYSCTL_DSLPCLKCFG_D_2 0x00800000 // System clock /2
+#define SYSCTL_DSLPCLKCFG_D_3 0x01000000 // System clock /3
+#define SYSCTL_DSLPCLKCFG_D_4 0x01800000 // System clock /4
+#define SYSCTL_DSLPCLKCFG_D_5 0x02000000 // System clock /5
+#define SYSCTL_DSLPCLKCFG_D_6 0x02800000 // System clock /6
+#define SYSCTL_DSLPCLKCFG_D_7 0x03000000 // System clock /7
+#define SYSCTL_DSLPCLKCFG_D_8 0x03800000 // System clock /8
+#define SYSCTL_DSLPCLKCFG_D_9 0x04000000 // System clock /9
+#define SYSCTL_DSLPCLKCFG_D_10 0x04800000 // System clock /10
+#define SYSCTL_DSLPCLKCFG_D_11 0x05000000 // System clock /11
+#define SYSCTL_DSLPCLKCFG_D_12 0x05800000 // System clock /12
+#define SYSCTL_DSLPCLKCFG_D_13 0x06000000 // System clock /13
+#define SYSCTL_DSLPCLKCFG_D_14 0x06800000 // System clock /14
+#define SYSCTL_DSLPCLKCFG_D_15 0x07000000 // System clock /15
+#define SYSCTL_DSLPCLKCFG_D_16 0x07800000 // System clock /16
+#define SYSCTL_DSLPCLKCFG_D_17 0x08000000 // System clock /17
+#define SYSCTL_DSLPCLKCFG_D_18 0x08800000 // System clock /18
+#define SYSCTL_DSLPCLKCFG_D_19 0x09000000 // System clock /19
+#define SYSCTL_DSLPCLKCFG_D_20 0x09800000 // System clock /20
+#define SYSCTL_DSLPCLKCFG_D_21 0x0A000000 // System clock /21
+#define SYSCTL_DSLPCLKCFG_D_22 0x0A800000 // System clock /22
+#define SYSCTL_DSLPCLKCFG_D_23 0x0B000000 // System clock /23
+#define SYSCTL_DSLPCLKCFG_D_24 0x0B800000 // System clock /24
+#define SYSCTL_DSLPCLKCFG_D_25 0x0C000000 // System clock /25
+#define SYSCTL_DSLPCLKCFG_D_26 0x0C800000 // System clock /26
+#define SYSCTL_DSLPCLKCFG_D_27 0x0D000000 // System clock /27
+#define SYSCTL_DSLPCLKCFG_D_28 0x0D800000 // System clock /28
+#define SYSCTL_DSLPCLKCFG_D_29 0x0E000000 // System clock /29
+#define SYSCTL_DSLPCLKCFG_D_30 0x0E800000 // System clock /30
+#define SYSCTL_DSLPCLKCFG_D_31 0x0F000000 // System clock /31
+#define SYSCTL_DSLPCLKCFG_D_32 0x0F800000 // System clock /32
+#define SYSCTL_DSLPCLKCFG_D_33 0x10000000 // System clock /33
+#define SYSCTL_DSLPCLKCFG_D_34 0x10800000 // System clock /34
+#define SYSCTL_DSLPCLKCFG_D_35 0x11000000 // System clock /35
+#define SYSCTL_DSLPCLKCFG_D_36 0x11800000 // System clock /36
+#define SYSCTL_DSLPCLKCFG_D_37 0x12000000 // System clock /37
+#define SYSCTL_DSLPCLKCFG_D_38 0x12800000 // System clock /38
+#define SYSCTL_DSLPCLKCFG_D_39 0x13000000 // System clock /39
+#define SYSCTL_DSLPCLKCFG_D_40 0x13800000 // System clock /40
+#define SYSCTL_DSLPCLKCFG_D_41 0x14000000 // System clock /41
+#define SYSCTL_DSLPCLKCFG_D_42 0x14800000 // System clock /42
+#define SYSCTL_DSLPCLKCFG_D_43 0x15000000 // System clock /43
+#define SYSCTL_DSLPCLKCFG_D_44 0x15800000 // System clock /44
+#define SYSCTL_DSLPCLKCFG_D_45 0x16000000 // System clock /45
+#define SYSCTL_DSLPCLKCFG_D_46 0x16800000 // System clock /46
+#define SYSCTL_DSLPCLKCFG_D_47 0x17000000 // System clock /47
+#define SYSCTL_DSLPCLKCFG_D_48 0x17800000 // System clock /48
+#define SYSCTL_DSLPCLKCFG_D_49 0x18000000 // System clock /49
+#define SYSCTL_DSLPCLKCFG_D_50 0x18800000 // System clock /50
+#define SYSCTL_DSLPCLKCFG_D_51 0x19000000 // System clock /51
+#define SYSCTL_DSLPCLKCFG_D_52 0x19800000 // System clock /52
+#define SYSCTL_DSLPCLKCFG_D_53 0x1A000000 // System clock /53
+#define SYSCTL_DSLPCLKCFG_D_54 0x1A800000 // System clock /54
+#define SYSCTL_DSLPCLKCFG_D_55 0x1B000000 // System clock /55
+#define SYSCTL_DSLPCLKCFG_D_56 0x1B800000 // System clock /56
+#define SYSCTL_DSLPCLKCFG_D_57 0x1C000000 // System clock /57
+#define SYSCTL_DSLPCLKCFG_D_58 0x1C800000 // System clock /58
+#define SYSCTL_DSLPCLKCFG_D_59 0x1D000000 // System clock /59
+#define SYSCTL_DSLPCLKCFG_D_60 0x1D800000 // System clock /60
+#define SYSCTL_DSLPCLKCFG_D_61 0x1E000000 // System clock /61
+#define SYSCTL_DSLPCLKCFG_D_62 0x1E800000 // System clock /62
+#define SYSCTL_DSLPCLKCFG_D_63 0x1F000000 // System clock /63
+#define SYSCTL_DSLPCLKCFG_D_64 0x1F800000 // System clock /64
+#define SYSCTL_DSLPCLKCFG_O_M 0x00000070 // Clock Source.
+#define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000 // Do not override
+#define SYSCTL_DSLPCLKCFG_O_IO 0x00000010 // Use the internal oscillator
+#define SYSCTL_DSLPCLKCFG_O_30 0x00000030 // Use the 30 KHz internal osc.
+#define SYSCTL_DSLPCLKCFG_O_32 0x00000070 // Use the 32 KHz external osc.
+#define SYSCTL_DSLPCLKCFG_IOSC 0x00000001 // IOSC Clock Source.
+#define SYSCTL_DSLPCLKCFG_D_S 23
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_CLKVCLR register.
+//
+//*****************************************************************************
+#define SYSCTL_CLKVCLR_VERCLR 0x00000001 // Clock Verification Clear.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_LDOARST register.
+//
+//*****************************************************************************
+#define SYSCTL_LDOARST_LDOARST 0x00000001 // LDO Reset.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCR0 register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCR0_WDT1 0x10000000 // WDT1 Reset Control.
+#define SYSCTL_SRCR0_CAN2 0x04000000 // CAN2 Reset Control.
+#define SYSCTL_SRCR0_CAN1 0x02000000 // CAN1 Reset Control.
+#define SYSCTL_SRCR0_CAN0 0x01000000 // CAN0 Reset Control.
+#define SYSCTL_SRCR0_PWM 0x00100000 // PWM Reset Control.
+#define SYSCTL_SRCR0_ADC1 0x00020000 // ADC1 Reset Control.
+#define SYSCTL_SRCR0_ADC0 0x00010000 // ADC0 Reset Control.
+#define SYSCTL_SRCR0_HIB 0x00000040 // HIB Reset Control.
+#define SYSCTL_SRCR0_WDT0 0x00000008 // WDT0 Reset Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCR1 register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCR1_EPI0 0x40000000 // EPI0 Reset Control.
+#define SYSCTL_SRCR1_I2S0 0x10000000 // I2S 0 Reset Control.
+#define SYSCTL_SRCR1_COMP2 0x04000000 // Analog Comp 2 Reset Control.
+#define SYSCTL_SRCR1_COMP1 0x02000000 // Analog Comp 1 Reset Control.
+#define SYSCTL_SRCR1_COMP0 0x01000000 // Analog Comp 0 Reset Control.
+#define SYSCTL_SRCR1_TIMER3 0x00080000 // Timer 3 Reset Control.
+#define SYSCTL_SRCR1_TIMER2 0x00040000 // Timer 2 Reset Control.
+#define SYSCTL_SRCR1_TIMER1 0x00020000 // Timer 1 Reset Control.
+#define SYSCTL_SRCR1_TIMER0 0x00010000 // Timer 0 Reset Control.
+#define SYSCTL_SRCR1_I2C1 0x00004000 // I2C1 Reset Control.
+#define SYSCTL_SRCR1_I2C0 0x00001000 // I2C0 Reset Control.
+#define SYSCTL_SRCR1_QEI1 0x00000200 // QEI1 Reset Control.
+#define SYSCTL_SRCR1_QEI0 0x00000100 // QEI0 Reset Control.
+#define SYSCTL_SRCR1_SSI1 0x00000020 // SSI1 Reset Control.
+#define SYSCTL_SRCR1_SSI0 0x00000010 // SSI0 Reset Control.
+#define SYSCTL_SRCR1_UART2 0x00000004 // UART2 Reset Control.
+#define SYSCTL_SRCR1_UART1 0x00000002 // UART1 Reset Control.
+#define SYSCTL_SRCR1_UART0 0x00000001 // UART0 Reset Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCR2 register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCR2_EPHY0 0x40000000 // PHY0 Reset Control.
+#define SYSCTL_SRCR2_EMAC0 0x10000000 // MAC0 Reset Control.
+#define SYSCTL_SRCR2_USB0 0x00010000 // USB0 Reset Control.
+#define SYSCTL_SRCR2_UDMA 0x00002000 // UDMA Reset Control.
+#define SYSCTL_SRCR2_GPIOJ 0x00000100 // Port J Reset Control.
+#define SYSCTL_SRCR2_GPIOH 0x00000080 // Port H Reset Control.
+#define SYSCTL_SRCR2_GPIOG 0x00000040 // Port G Reset Control.
+#define SYSCTL_SRCR2_GPIOF 0x00000020 // Port F Reset Control.
+#define SYSCTL_SRCR2_GPIOE 0x00000010 // Port E Reset Control.
+#define SYSCTL_SRCR2_GPIOD 0x00000008 // Port D Reset Control.
+#define SYSCTL_SRCR2_GPIOC 0x00000004 // Port C Reset Control.
+#define SYSCTL_SRCR2_GPIOB 0x00000002 // Port B Reset Control.
+#define SYSCTL_SRCR2_GPIOA 0x00000001 // Port A Reset Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RIS register.
+//
+//*****************************************************************************
+#define SYSCTL_RIS_MOSCPUPRIS 0x00000100 // MOSC Power Up Raw Interrupt
+ // Status.
+#define SYSCTL_RIS_USBPLLLRIS 0x00000080 // USB PLL Lock Raw Interrupt
+ // Status.
+#define SYSCTL_RIS_PLLLRIS 0x00000040 // PLL Lock Raw Interrupt Status.
+#define SYSCTL_RIS_CLRIS 0x00000020 // Current Limit Raw Interrupt
+ // Status.
+#define SYSCTL_RIS_IOFRIS 0x00000010 // Internal Oscillator Fault Raw
+ // Interrupt Status.
+#define SYSCTL_RIS_MOFRIS 0x00000008 // Main Oscillator Fault Raw
+ // Interrupt Status.
+#define SYSCTL_RIS_LDORIS 0x00000004 // LDO Power Unregulated Raw
+ // Interrupt Status.
+#define SYSCTL_RIS_BORRIS 0x00000002 // Brown-Out Reset Raw Interrupt
+ // Status.
+#define SYSCTL_RIS_PLLFRIS 0x00000001 // PLL Fault Raw Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_IMC register.
+//
+//*****************************************************************************
+#define SYSCTL_IMC_MOSCPUPIM 0x00000100 // MOSC Power Up Interrupt Mask.
+#define SYSCTL_IMC_USBPLLLIM 0x00000080 // USB PLL Lock Interrupt Mask.
+#define SYSCTL_IMC_PLLLIM 0x00000040 // PLL Lock Interrupt Mask.
+#define SYSCTL_IMC_CLIM 0x00000020 // Current Limit Interrupt Mask.
+#define SYSCTL_IMC_IOFIM 0x00000010 // Internal Oscillator Fault
+ // Interrupt Mask.
+#define SYSCTL_IMC_MOFIM 0x00000008 // Main Oscillator Fault Interrupt
+ // Mask.
+#define SYSCTL_IMC_LDOIM 0x00000004 // LDO Power Unregulated Interrupt
+ // Mask.
+#define SYSCTL_IMC_BORIM 0x00000002 // Brown-Out Reset Interrupt Mask.
+#define SYSCTL_IMC_PLLFIM 0x00000001 // PLL Fault Interrupt Mask.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_MISC register.
+//
+//*****************************************************************************
+#define SYSCTL_MISC_MOSCPUPMIS 0x00000100 // MOSC Power Up Masked Interrupt
+ // Status.
+#define SYSCTL_MISC_USBPLLLMIS 0x00000080 // USB PLL Lock Masked Interrupt
+ // Status.
+#define SYSCTL_MISC_PLLLMIS 0x00000040 // PLL Lock Masked Interrupt
+ // Status.
+#define SYSCTL_MISC_CLMIS 0x00000020 // Current Limit Masked Interrupt
+ // Status.
+#define SYSCTL_MISC_IOFMIS 0x00000010 // Internal Oscillator Fault Masked
+ // Interrupt Status.
+#define SYSCTL_MISC_MOFMIS 0x00000008 // Main Oscillator Fault Masked
+ // Interrupt Status.
+#define SYSCTL_MISC_LDOMIS 0x00000004 // LDO Power Unregulated Masked
+ // Interrupt Status.
+#define SYSCTL_MISC_BORMIS 0x00000002 // BOR Masked Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control.
+#define SYSCTL_RCGC0_CAN2 0x04000000 // CAN2 Clock Gating Control.
+#define SYSCTL_RCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control.
+#define SYSCTL_RCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control.
+#define SYSCTL_RCGC0_PWM 0x00100000 // PWM Clock Gating Control.
+#define SYSCTL_RCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control.
+#define SYSCTL_RCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control.
+#define SYSCTL_RCGC0_ADCSPD_M 0x00000F00 // ADC Sample Speed.
+#define SYSCTL_RCGC0_ADCSPD125K 0x00000000 // 125K samples/second
+#define SYSCTL_RCGC0_ADCSPD250K 0x00000100 // 250K samples/second
+#define SYSCTL_RCGC0_ADCSPD500K 0x00000200 // 500K samples/second
+#define SYSCTL_RCGC0_ADCSPD1M 0x00000300 // 1M samples/second
+#define SYSCTL_RCGC0_ADC1SPD_M 0x00000C00 // ADC1 Sample Speed.
+#define SYSCTL_RCGC0_ADC1SPD_1M 0x00000C00 // 1M samples/second
+#define SYSCTL_RCGC0_ADC0SPD_M 0x00000300 // ADC0 Sample Speed.
+#define SYSCTL_RCGC0_ADC0SPD_1M 0x00000300 // 1M samples/second
+#define SYSCTL_RCGC0_HIB 0x00000040 // HIB Clock Gating Control.
+#define SYSCTL_RCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGC1_EPI0 0x40000000 // EPI0 Clock Gating.
+#define SYSCTL_RCGC1_I2S0 0x10000000 // I2S0 Clock Gating Control.
+#define SYSCTL_RCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock
+ // Gating.
+#define SYSCTL_RCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock
+ // Gating.
+#define SYSCTL_RCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock
+ // Gating.
+#define SYSCTL_RCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control.
+#define SYSCTL_RCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control.
+#define SYSCTL_RCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control.
+#define SYSCTL_RCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control.
+#define SYSCTL_RCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control.
+#define SYSCTL_RCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control.
+#define SYSCTL_RCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control.
+#define SYSCTL_RCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control.
+#define SYSCTL_RCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control.
+#define SYSCTL_RCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control.
+#define SYSCTL_RCGC1_UART2 0x00000004 // UART2 Clock Gating Control.
+#define SYSCTL_RCGC1_UART1 0x00000002 // UART1 Clock Gating Control.
+#define SYSCTL_RCGC1_UART0 0x00000001 // UART0 Clock Gating Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGC2_EPHY0 0x40000000 // PHY0 Clock Gating Control.
+#define SYSCTL_RCGC2_EMAC0 0x10000000 // MAC0 Clock Gating Control.
+#define SYSCTL_RCGC2_USB0 0x00010000 // USB0 Clock Gating Control.
+#define SYSCTL_RCGC2_UDMA 0x00002000 // UDMA Clock Gating Control.
+#define SYSCTL_RCGC2_GPIOJ 0x00000100 // Port J Clock Gating Control.
+#define SYSCTL_RCGC2_GPIOH 0x00000080 // Port H Clock Gating Control.
+#define SYSCTL_RCGC2_GPIOG 0x00000040 // Port G Clock Gating Control.
+#define SYSCTL_RCGC2_GPIOF 0x00000020 // Port F Clock Gating Control.
+#define SYSCTL_RCGC2_GPIOE 0x00000010 // Port E Clock Gating Control.
+#define SYSCTL_RCGC2_GPIOD 0x00000008 // Port D Clock Gating Control.
+#define SYSCTL_RCGC2_GPIOC 0x00000004 // Port C Clock Gating Control.
+#define SYSCTL_RCGC2_GPIOB 0x00000002 // Port B Clock Gating Control.
+#define SYSCTL_RCGC2_GPIOA 0x00000001 // Port A Clock Gating Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control.
+#define SYSCTL_SCGC0_CAN2 0x04000000 // CAN2 Clock Gating Control.
+#define SYSCTL_SCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control.
+#define SYSCTL_SCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control.
+#define SYSCTL_SCGC0_PWM 0x00100000 // PWM Clock Gating Control.
+#define SYSCTL_SCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control.
+#define SYSCTL_SCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control.
+#define SYSCTL_SCGC0_ADCSPD_M 0x00000F00 // ADC Sample Speed.
+#define SYSCTL_SCGC0_ADCSPD125K 0x00000000 // 125K samples/second
+#define SYSCTL_SCGC0_ADCSPD250K 0x00000100 // 250K samples/second
+#define SYSCTL_SCGC0_ADCSPD500K 0x00000200 // 500K samples/second
+#define SYSCTL_SCGC0_ADCSPD1M 0x00000300 // 1M samples/second
+#define SYSCTL_SCGC0_ADC1SPD_M 0x00000C00 // ADC1 Sample Speed.
+#define SYSCTL_SCGC0_ADC1SPD_1M 0x00000C00 // 1M samples/second
+#define SYSCTL_SCGC0_ADC0SPD_M 0x00000300 // ADC0 Sample Speed.
+#define SYSCTL_SCGC0_ADC0SPD_1M 0x00000300 // 1M samples/second
+#define SYSCTL_SCGC0_HIB 0x00000040 // HIB Clock Gating Control.
+#define SYSCTL_SCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGC1_EPI0 0x40000000 // EPI0 Clock Gating.
+#define SYSCTL_SCGC1_I2S0 0x10000000 // I2S 0 Clock Gating.
+#define SYSCTL_SCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock
+ // Gating.
+#define SYSCTL_SCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock
+ // Gating.
+#define SYSCTL_SCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock
+ // Gating.
+#define SYSCTL_SCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control.
+#define SYSCTL_SCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control.
+#define SYSCTL_SCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control.
+#define SYSCTL_SCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control.
+#define SYSCTL_SCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control.
+#define SYSCTL_SCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control.
+#define SYSCTL_SCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control.
+#define SYSCTL_SCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control.
+#define SYSCTL_SCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control.
+#define SYSCTL_SCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control.
+#define SYSCTL_SCGC1_UART2 0x00000004 // UART2 Clock Gating Control.
+#define SYSCTL_SCGC1_UART1 0x00000002 // UART1 Clock Gating Control.
+#define SYSCTL_SCGC1_UART0 0x00000001 // UART0 Clock Gating Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGC2_EPHY0 0x40000000 // PHY0 Clock Gating Control.
+#define SYSCTL_SCGC2_EMAC0 0x10000000 // MAC0 Clock Gating Control.
+#define SYSCTL_SCGC2_USB0 0x00010000 // USB0 Clock Gating Control.
+#define SYSCTL_SCGC2_UDMA 0x00002000 // UDMA Clock Gating Control.
+#define SYSCTL_SCGC2_GPIOJ 0x00000100 // GPIO Port J Present.
+#define SYSCTL_SCGC2_GPIOH 0x00000080 // Port H Clock Gating Control.
+#define SYSCTL_SCGC2_GPIOG 0x00000040 // Port G Clock Gating Control.
+#define SYSCTL_SCGC2_GPIOF 0x00000020 // Port F Clock Gating Control.
+#define SYSCTL_SCGC2_GPIOE 0x00000010 // Port E Clock Gating Control.
+#define SYSCTL_SCGC2_GPIOD 0x00000008 // Port D Clock Gating Control.
+#define SYSCTL_SCGC2_GPIOC 0x00000004 // Port C Clock Gating Control.
+#define SYSCTL_SCGC2_GPIOB 0x00000002 // Port B Clock Gating Control.
+#define SYSCTL_SCGC2_GPIOA 0x00000001 // Port A Clock Gating Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control.
+#define SYSCTL_DCGC0_CAN2 0x04000000 // CAN2 Clock Gating Control.
+#define SYSCTL_DCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control.
+#define SYSCTL_DCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control.
+#define SYSCTL_DCGC0_PWM 0x00100000 // PWM Clock Gating Control.
+#define SYSCTL_DCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control.
+#define SYSCTL_DCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control.
+#define SYSCTL_DCGC0_ADCSPD_M 0x00000F00 // ADC Sample Speed.
+#define SYSCTL_DCGC0_ADCSPD125K 0x00000000 // 125K samples/second
+#define SYSCTL_DCGC0_ADCSPD250K 0x00000100 // 250K samples/second
+#define SYSCTL_DCGC0_ADCSPD500K 0x00000200 // 500K samples/second
+#define SYSCTL_DCGC0_ADCSPD1M 0x00000300 // 1M samples/second
+#define SYSCTL_DCGC0_ADC1SPD_M 0x00000C00 // ADC1 Sample Speed.
+#define SYSCTL_DCGC0_ADC1SPD_1M 0x00000C00 // 1M samples/second
+#define SYSCTL_DCGC0_ADC0SPD_M 0x00000300 // ADC0 Sample Speed.
+#define SYSCTL_DCGC0_ADC0SPD_1M 0x00000300 // 1M samples/second
+#define SYSCTL_DCGC0_HIB 0x00000040 // HIB Clock Gating Control.
+#define SYSCTL_DCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGC1_EPI0 0x40000000 // EPI0 Clock Gating.
+#define SYSCTL_DCGC1_I2S0 0x10000000 // I2S 0 Clock Gating.
+#define SYSCTL_DCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock
+ // Gating.
+#define SYSCTL_DCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock
+ // Gating.
+#define SYSCTL_DCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock
+ // Gating.
+#define SYSCTL_DCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control.
+#define SYSCTL_DCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control.
+#define SYSCTL_DCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control.
+#define SYSCTL_DCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control.
+#define SYSCTL_DCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control.
+#define SYSCTL_DCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control.
+#define SYSCTL_DCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control.
+#define SYSCTL_DCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control.
+#define SYSCTL_DCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control.
+#define SYSCTL_DCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control.
+#define SYSCTL_DCGC1_UART2 0x00000004 // UART2 Clock Gating Control.
+#define SYSCTL_DCGC1_UART1 0x00000002 // UART1 Clock Gating Control.
+#define SYSCTL_DCGC1_UART0 0x00000001 // UART0 Clock Gating Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGC2_EPHY0 0x40000000 // PHY0 Clock Gating Control.
+#define SYSCTL_DCGC2_EMAC0 0x10000000 // MAC0 Clock Gating Control.
+#define SYSCTL_DCGC2_USB0 0x00010000 // USB0 Clock Gating Control.
+#define SYSCTL_DCGC2_UDMA 0x00002000 // UDMA Clock Gating Control.
+#define SYSCTL_DCGC2_GPIOJ 0x00000100 // GPIO Port J Present.
+#define SYSCTL_DCGC2_GPIOH 0x00000080 // Port H Clock Gating Control.
+#define SYSCTL_DCGC2_GPIOG 0x00000040 // Port G Clock Gating Control.
+#define SYSCTL_DCGC2_GPIOF 0x00000020 // Port F Clock Gating Control.
+#define SYSCTL_DCGC2_GPIOE 0x00000010 // Port E Clock Gating Control.
+#define SYSCTL_DCGC2_GPIOD 0x00000008 // Port D Clock Gating Control.
+#define SYSCTL_DCGC2_GPIOC 0x00000004 // Port C Clock Gating Control.
+#define SYSCTL_DCGC2_GPIOB 0x00000002 // Port B Clock Gating Control.
+#define SYSCTL_DCGC2_GPIOA 0x00000001 // Port A Clock Gating Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC5 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC5_PWMFAULT3 0x08000000 // PWM Fault 3 Pin Present.
+#define SYSCTL_DC5_PWMFAULT2 0x04000000 // PWM Fault 2 Pin Present.
+#define SYSCTL_DC5_PWMFAULT1 0x02000000 // PWM Fault 1 Pin Present.
+#define SYSCTL_DC5_PWMFAULT0 0x01000000 // PWM Fault 0 Pin Present.
+#define SYSCTL_DC5_PWMEFLT 0x00200000 // PWM Extended Fault feature is
+ // active.
+#define SYSCTL_DC5_PWMESYNC 0x00100000 // PWM Extended SYNC feature is
+ // active.
+#define SYSCTL_DC5_PWM7 0x00000080 // PWM7 Pin Present.
+#define SYSCTL_DC5_PWM6 0x00000040 // PWM6 Pin Present.
+#define SYSCTL_DC5_PWM5 0x00000020 // PWM5 Pin Present.
+#define SYSCTL_DC5_PWM4 0x00000010 // PWM4 Pin Present.
+#define SYSCTL_DC5_PWM3 0x00000008 // PWM3 Pin Present.
+#define SYSCTL_DC5_PWM2 0x00000004 // PWM2 Pin Present.
+#define SYSCTL_DC5_PWM1 0x00000002 // PWM1 Pin Present.
+#define SYSCTL_DC5_PWM0 0x00000001 // PWM0 Pin Present.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC6 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC6_USB0PHY 0x00000010 // This specifies that USB0 PHY is
+ // present.
+#define SYSCTL_DC6_USB0_M 0x00000003 // This specifies that USB0 is
+ // present and its capability.
+#define SYSCTL_DC6_USB0_HOSTDEV 0x00000002 // USB is DEVICE or HOST
+#define SYSCTL_DC6_USB0_OTG 0x00000003 // USB is OTG
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_GPIOHSCTL
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_GPIOHSCTL_PORTH 0x00000080 // Port H High-Speed.
+#define SYSCTL_GPIOHSCTL_PORTG 0x00000040 // Port G High-Speed.
+#define SYSCTL_GPIOHSCTL_PORTF 0x00000020 // Port F High-Speed.
+#define SYSCTL_GPIOHSCTL_PORTE 0x00000010 // Port E High-Speed.
+#define SYSCTL_GPIOHSCTL_PORTD 0x00000008 // Port D High-Speed.
+#define SYSCTL_GPIOHSCTL_PORTC 0x00000004 // Port C High-Speed.
+#define SYSCTL_GPIOHSCTL_PORTB 0x00000002 // Port B High-Speed.
+#define SYSCTL_GPIOHSCTL_PORTA 0x00000001 // Port A High-Speed.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_MOSCCTL register.
+//
+//*****************************************************************************
+#define SYSCTL_MOSCCTL_CVAL 0x00000001 // Clock Validation for MOSC.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC7 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC7_DMACH30 0x40000000 // SW.
+#define SYSCTL_DC7_DMACH29 0x20000000 // I2S0_TX.
+#define SYSCTL_DC7_DMACH28 0x10000000 // I2S0_RX.
+#define SYSCTL_DC7_DMACH27 0x08000000 // ADC1_SS3.
+#define SYSCTL_DC7_DMACH26 0x04000000 // ADC1_SS2.
+#define SYSCTL_DC7_DMACH25 0x02000000 // SSI1_TX / ADC1_SS1.
+#define SYSCTL_DC7_SSI1_TX 0x02000000 // SSI1 TX on uDMA Ch25.
+#define SYSCTL_DC7_SSI1_RX 0x01000000 // SSI1 RX on uDMA Ch24.
+#define SYSCTL_DC7_DMACH24 0x01000000 // SSI1_RX / ADC1_SS0.
+#define SYSCTL_DC7_UART1_TX 0x00800000 // UART1 TX on uDMA Ch23.
+#define SYSCTL_DC7_DMACH23 0x00800000 // UART1_TX.
+#define SYSCTL_DC7_DMACH22 0x00400000 // UART1_RX.
+#define SYSCTL_DC7_UART1_RX 0x00400000 // UART1 RX on uDMA Ch22.
+#define SYSCTL_DC7_DMACH21 0x00200000 // Timer1B / EPI0_TX.
+#define SYSCTL_DC7_DMACH20 0x00100000 // Timer1A / EPI0_RX.
+#define SYSCTL_DC7_DMACH19 0x00080000 // Timer0B / Timer1B.
+#define SYSCTL_DC7_DMACH18 0x00040000 // Timer0A / Timer1A.
+#define SYSCTL_DC7_DMACH17 0x00020000 // ADC0_SS3.
+#define SYSCTL_DC7_DMACH16 0x00010000 // ADC0_SS2.
+#define SYSCTL_DC7_DMACH15 0x00008000 // ADC0_SS1 / Timer2B.
+#define SYSCTL_DC7_DMACH14 0x00004000 // ADC0_SS0 / Timer2A.
+#define SYSCTL_DC7_DMACH13 0x00002000 // UART2_TX.
+#define SYSCTL_DC7_DMACH12 0x00001000 // UART2_RX.
+#define SYSCTL_DC7_SSI0_TX 0x00000800 // SSI0 TX on uDMA Ch11.
+#define SYSCTL_DC7_DMACH11 0x00000800 // SSI0_TX / UART1_TX.
+#define SYSCTL_DC7_SSI0_RX 0x00000400 // SSI0 RX on uDMA Ch10.
+#define SYSCTL_DC7_DMACH10 0x00000400 // SSI0_RX / UART1_RX.
+#define SYSCTL_DC7_UART0_TX 0x00000200 // UART0 TX on uDMA Ch9.
+#define SYSCTL_DC7_DMACH9 0x00000200 // UART0_TX / SSI1_TX.
+#define SYSCTL_DC7_DMACH8 0x00000100 // UART0_RX / SSI1_RX.
+#define SYSCTL_DC7_UART0_RX 0x00000100 // UART0 RX on uDMA Ch8.
+#define SYSCTL_DC7_DMACH7 0x00000080 // ETH_TX / Timer2B.
+#define SYSCTL_DC7_DMACH6 0x00000040 // ETH_RX / Timer2A.
+#define SYSCTL_DC7_DMACH5 0x00000020 // USB_EP3_TX / Timer2B.
+#define SYSCTL_DC7_USB_EP3_TX 0x00000020 // USB EP3 TX on uDMA Ch5.
+#define SYSCTL_DC7_USB_EP3_RX 0x00000010 // USB EP3 RX on uDMA Ch4.
+#define SYSCTL_DC7_DMACH4 0x00000010 // USB_EP3_RX / Timer2A.
+#define SYSCTL_DC7_USB_EP2_TX 0x00000008 // USB EP2 TX on uDMA Ch3.
+#define SYSCTL_DC7_DMACH3 0x00000008 // USB_EP2_TX / Timer3B.
+#define SYSCTL_DC7_USB_EP2_RX 0x00000004 // USB EP2 RX on uDMA Ch2.
+#define SYSCTL_DC7_DMACH2 0x00000004 // USB_EP2_RX / Timer3A.
+#define SYSCTL_DC7_USB_EP1_TX 0x00000002 // USB EP1 TX on uDMA Ch1.
+#define SYSCTL_DC7_DMACH1 0x00000002 // USB_EP1_TX / UART2_TX.
+#define SYSCTL_DC7_DMACH0 0x00000001 // USB_EP1_RX / UART2_RX.
+#define SYSCTL_DC7_USB_EP1_RX 0x00000001 // USB EP1 RX on uDMA Ch0.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC8 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC8_ADC1AIN15 0x80000000 // ADC Module 1 AIN15 Pin Present.
+#define SYSCTL_DC8_ADC1AIN14 0x40000000 // ADC Module 1 AIN14 Pin Present.
+#define SYSCTL_DC8_ADC1AIN13 0x20000000 // ADC Module 1 AIN13 Pin Present.
+#define SYSCTL_DC8_ADC1AIN12 0x10000000 // ADC Module 1 AIN12 Pin Present.
+#define SYSCTL_DC8_ADC1AIN11 0x08000000 // ADC1 11 Pin Present.
+#define SYSCTL_DC8_ADC1AIN10 0x04000000 // ADC1 10 Pin Present.
+#define SYSCTL_DC8_ADC1AIN9 0x02000000 // ADC1 9 Pin Present.
+#define SYSCTL_DC8_ADC1AIN8 0x01000000 // ADC1 8 Pin Present.
+#define SYSCTL_DC8_ADC1AIN7 0x00800000 // ADC1 7 Pin Present.
+#define SYSCTL_DC8_ADC1AIN6 0x00400000 // ADC1 6 Pin Present.
+#define SYSCTL_DC8_ADC1AIN5 0x00200000 // ADC1 5 Pin Present.
+#define SYSCTL_DC8_ADC1AIN4 0x00100000 // ADC1 4 Pin Present.
+#define SYSCTL_DC8_ADC1AIN3 0x00080000 // ADC1 3 Pin Present.
+#define SYSCTL_DC8_ADC1AIN2 0x00040000 // ADC1 2 Pin Present.
+#define SYSCTL_DC8_ADC1AIN1 0x00020000 // ADC1 1 Pin Present.
+#define SYSCTL_DC8_ADC1AIN0 0x00010000 // ADC1 0 Pin Present.
+#define SYSCTL_DC8_ADC0AIN15 0x00008000 // ADC Module 0 AIN15 Pin Present.
+#define SYSCTL_DC8_ADC0AIN14 0x00004000 // ADC Module 0 AIN14 Pin Present.
+#define SYSCTL_DC8_ADC0AIN13 0x00002000 // ADC Module 0 AIN13 Pin Present.
+#define SYSCTL_DC8_ADC0AIN12 0x00001000 // ADC Module 0 AIN12 Pin Present.
+#define SYSCTL_DC8_ADC0AIN11 0x00000800 // ADC0 11 Pin Present.
+#define SYSCTL_DC8_ADC0AIN10 0x00000400 // ADC0 10 Pin Present.
+#define SYSCTL_DC8_ADC0AIN9 0x00000200 // ADC0 9 Pin Present.
+#define SYSCTL_DC8_ADC0AIN8 0x00000100 // ADC0 8 Pin Present.
+#define SYSCTL_DC8_ADC0AIN7 0x00000080 // ADC0 7 Pin Present.
+#define SYSCTL_DC8_ADC0AIN6 0x00000040 // ADC0 6 Pin Present.
+#define SYSCTL_DC8_ADC0AIN5 0x00000020 // ADC0 5 Pin Present.
+#define SYSCTL_DC8_ADC0AIN4 0x00000010 // ADC0 4 Pin Present.
+#define SYSCTL_DC8_ADC0AIN3 0x00000008 // ADC0 3 Pin Present.
+#define SYSCTL_DC8_ADC0AIN2 0x00000004 // ADC0 2 Pin Present.
+#define SYSCTL_DC8_ADC0AIN1 0x00000002 // ADC0 1 Pin Present.
+#define SYSCTL_DC8_ADC0AIN0 0x00000001 // ADC0 0 Pin Present.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PIOSCCAL
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PIOSCCAL_UTEN 0x80000000 // Use User Trim Value.
+#define SYSCTL_PIOSCCAL_CAL 0x00000200 // Start Calibration.
+#define SYSCTL_PIOSCCAL_UPDATE 0x00000100 // Update Trim.
+#define SYSCTL_PIOSCCAL_UT_M 0x0000007F // User Trim Value.
+#define SYSCTL_PIOSCCAL_UT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PIOSCSTAT
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PIOSCSTAT_DT_M 0x007F0000 // Default Trim Value.
+#define SYSCTL_PIOSCSTAT_CR_M 0x00000300 // Calibration Result.
+#define SYSCTL_PIOSCSTAT_CRNONE 0x00000000 // Calibration has not been
+ // attempted.
+#define SYSCTL_PIOSCSTAT_CRPASS 0x00000100 // The last calibration operation
+ // completed to meet 1% accuracy.
+#define SYSCTL_PIOSCSTAT_CRFAIL 0x00000200 // The last calibration operation
+ // failed to meet 1% accuracy.
+#define SYSCTL_PIOSCSTAT_CT_M 0x0000007F // Calibration Trim Value.
+#define SYSCTL_PIOSCSTAT_DT_S 16
+#define SYSCTL_PIOSCSTAT_CT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_I2SMCLKCFG
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_I2SMCLKCFG_RXEN 0x80000000 // RX Clock Enable.
+#define SYSCTL_I2SMCLKCFG_RXI_M 0x0FF00000 // RX Clock Integer Input.
+#define SYSCTL_I2SMCLKCFG_RXF_M 0x000F0000 // RX Clock Fractional Input.
+#define SYSCTL_I2SMCLKCFG_TXEN 0x00008000 // TX Clock Enable.
+#define SYSCTL_I2SMCLKCFG_TXI_M 0x00000FF0 // TX Clock Integer Input.
+#define SYSCTL_I2SMCLKCFG_TXF_M 0x0000000F // TX Clock Fractional Input.
+#define SYSCTL_I2SMCLKCFG_RXI_S 20
+#define SYSCTL_I2SMCLKCFG_RXF_S 16
+#define SYSCTL_I2SMCLKCFG_TXI_S 4
+#define SYSCTL_I2SMCLKCFG_TXF_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC9 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC9_ADC1DC7 0x00800000 // ADC1 7 Dig Cmp Present.
+#define SYSCTL_DC9_ADC1DC6 0x00400000 // ADC1 6 Dig Cmp Present.
+#define SYSCTL_DC9_ADC1DC5 0x00200000 // ADC1 5 Dig Cmp Present.
+#define SYSCTL_DC9_ADC1DC4 0x00100000 // ADC1 4 Dig Cmp Present.
+#define SYSCTL_DC9_ADC1DC3 0x00080000 // ADC1 3 Dig Cmp Present.
+#define SYSCTL_DC9_ADC1DC2 0x00040000 // ADC1 2 Dig Cmp Present.
+#define SYSCTL_DC9_ADC1DC1 0x00020000 // ADC1 1 Dig Cmp Present.
+#define SYSCTL_DC9_ADC1DC0 0x00010000 // ADC1 0 Dig Cmp Present.
+#define SYSCTL_DC9_ADC0DC7 0x00000080 // ADC0 7 Dig Cmp Present.
+#define SYSCTL_DC9_ADC0DC6 0x00000040 // ADC0 6 Dig Cmp Present.
+#define SYSCTL_DC9_ADC0DC5 0x00000020 // ADC0 5 Dig Cmp Present.
+#define SYSCTL_DC9_ADC0DC4 0x00000010 // ADC0 4 Dig Cmp Present.
+#define SYSCTL_DC9_ADC0DC3 0x00000008 // ADC0 3 Dig Cmp Present.
+#define SYSCTL_DC9_ADC0DC2 0x00000004 // ADC0 2 Dig Cmp Present.
+#define SYSCTL_DC9_ADC0DC1 0x00000002 // ADC0 1 Dig Cmp Present.
+#define SYSCTL_DC9_ADC0DC0 0x00000001 // ADC0 0 Dig Cmp Present.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_NVMSTAT register.
+//
+//*****************************************************************************
+#define SYSCTL_NVMSTAT_TPSW 0x00000010 // 1: Indicates 3rd party software
+ // in ROM.
+#define SYSCTL_NVMSTAT_FWB 0x00000001 // 32 Word flash write buffer
+ // function available.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DSFLASHCFG
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DSFLASHCFG_SHDWN 0x00000001 // Flash Shutdown.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_GPIOHBCTL
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_GPIOHBCTL_PORTJ 0x00000100 // Port J Advanced Host Bus.
+#define SYSCTL_GPIOHBCTL_PORTH 0x00000080 // Port H Advanced Host Bus.
+#define SYSCTL_GPIOHBCTL_PORTG 0x00000040 // Port G Advanced Host Bus.
+#define SYSCTL_GPIOHBCTL_PORTF 0x00000020 // Port F Advanced Host Bus.
+#define SYSCTL_GPIOHBCTL_PORTE 0x00000010 // Port E Advanced Host Bus.
+#define SYSCTL_GPIOHBCTL_PORTD 0x00000008 // Port D Advanced Host Bus.
+#define SYSCTL_GPIOHBCTL_PORTC 0x00000004 // Port C Advanced Host Bus.
+#define SYSCTL_GPIOHBCTL_PORTB 0x00000002 // Port B Advanced Host Bus.
+#define SYSCTL_GPIOHBCTL_PORTA 0x00000001 // Port A Advanced Host Bus.
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the system control register
+// addresses.
+//
+//*****************************************************************************
+#define SYSCTL_USER0 0x400FE1E0 // NV User Register 0
+#define SYSCTL_USER1 0x400FE1E4 // NV User Register 1
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_DID0
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DID0_VER_MASK 0x70000000 // DID0 version mask
+#define SYSCTL_DID0_CLASS_MASK 0x00FF0000 // Device Class
+#define SYSCTL_DID0_MAJ_MASK 0x0000FF00 // Major revision mask
+#define SYSCTL_DID0_MAJ_A 0x00000000 // Major revision A
+#define SYSCTL_DID0_MAJ_B 0x00000100 // Major revision B
+#define SYSCTL_DID0_MAJ_C 0x00000200 // Major revision C
+#define SYSCTL_DID0_MIN_MASK 0x000000FF // Minor revision mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_DID1
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DID1_VER_MASK 0xF0000000 // Register version mask
+#define SYSCTL_DID1_FAM_MASK 0x0F000000 // Family mask
+#define SYSCTL_DID1_FAM_S 0x00000000 // Stellaris family
+#define SYSCTL_DID1_PRTNO_MASK 0x00FF0000 // Part number mask
+#define SYSCTL_DID1_PINCNT_MASK 0x0000E000 // Pin count
+#define SYSCTL_DID1_TEMP_MASK 0x000000E0 // Temperature range mask
+#define SYSCTL_DID1_PKG_MASK 0x00000018 // Package mask
+#define SYSCTL_DID1_QUAL_MASK 0x00000003 // Qualification status mask
+#define SYSCTL_DID1_PRTNO_SHIFT 16
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_DC0
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DC0_SRAMSZ_MASK 0xFFFF0000 // SRAM size mask
+#define SYSCTL_DC0_FLASHSZ_MASK 0x0000FFFF // Flash size mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_DC1
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DC1_ADC 0x00010000 // ADC module present
+#define SYSCTL_DC1_SYSDIV_MASK 0x0000F000 // Minimum system divider mask
+#define SYSCTL_DC1_ADCSPD_MASK 0x00000F00 // ADC speed mask
+#define SYSCTL_DC1_WDOG 0x00000008 // Watchdog present
+#define SYSCTL_DC1_WDT 0x00000008 // Watchdog Timer Present.
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_DC2
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DC2_I2C 0x00001000 // I2C present
+#define SYSCTL_DC2_QEI 0x00000100 // QEI present
+#define SYSCTL_DC2_SSI 0x00000010 // SSI present
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_DC3
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DC3_ADC7 0x00800000 // ADC7 pin present
+#define SYSCTL_DC3_ADC6 0x00400000 // ADC6 pin present
+#define SYSCTL_DC3_ADC5 0x00200000 // ADC5 pin present
+#define SYSCTL_DC3_ADC4 0x00100000 // ADC4 pin present
+#define SYSCTL_DC3_ADC3 0x00080000 // ADC3 pin present
+#define SYSCTL_DC3_ADC2 0x00040000 // ADC2 pin present
+#define SYSCTL_DC3_ADC1 0x00020000 // ADC1 pin present
+#define SYSCTL_DC3_ADC0 0x00010000 // ADC0 pin present
+#define SYSCTL_DC3_MC_FAULT0 0x00008000 // MC0 fault pin present
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the
+// SYSCTL_PBORCTL register.
+//
+//*****************************************************************************
+#define SYSCTL_PBORCTL_BOR_MASK 0x0000FFFC // BOR wait timer
+#define SYSCTL_PBORCTL_BOR_SH 2
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the
+// SYSCTL_LDOPCTL register.
+//
+//*****************************************************************************
+#define SYSCTL_LDOPCTL_MASK 0x0000003F // Voltage adjust mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_SRCR0,
+// SYSCTL_RCGC0, SYSCTL_SCGC0, and SYSCTL_DCGC0 registers.
+//
+//*****************************************************************************
+#define SYSCTL_SET0_CAN2 0x04000000 // CAN 2 module
+#define SYSCTL_SET0_CAN1 0x02000000 // CAN 1 module
+#define SYSCTL_SET0_CAN0 0x01000000 // CAN 0 module
+#define SYSCTL_SET0_PWM 0x00100000 // PWM module
+#define SYSCTL_SET0_ADC 0x00010000 // ADC module
+#define SYSCTL_SET0_ADCSPD_MASK 0x00000F00 // ADC speed mask
+#define SYSCTL_SET0_ADCSPD_125K 0x00000000 // 125Ksps ADC
+#define SYSCTL_SET0_ADCSPD_250K 0x00000100 // 250Ksps ADC
+#define SYSCTL_SET0_ADCSPD_500K 0x00000200 // 500Ksps ADC
+#define SYSCTL_SET0_ADCSPD_1M 0x00000300 // 1Msps ADC
+#define SYSCTL_SET0_HIB 0x00000040 // Hibernation module
+#define SYSCTL_SET0_WDOG 0x00000008 // Watchdog module
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_SRCR1,
+// SYSCTL_RCGC1, SYSCTL_SCGC1, and SYSCTL_DCGC1 registers.
+//
+//*****************************************************************************
+#define SYSCTL_SET1_COMP2 0x04000000 // Analog comparator module 2
+#define SYSCTL_SET1_COMP1 0x02000000 // Analog comparator module 1
+#define SYSCTL_SET1_COMP0 0x01000000 // Analog comparator module 0
+#define SYSCTL_SET1_TIMER3 0x00080000 // Timer module 3
+#define SYSCTL_SET1_TIMER2 0x00040000 // Timer module 2
+#define SYSCTL_SET1_TIMER1 0x00020000 // Timer module 1
+#define SYSCTL_SET1_TIMER0 0x00010000 // Timer module 0
+#define SYSCTL_SET1_I2C1 0x00002000 // I2C module 1
+#define SYSCTL_SET1_I2C0 0x00001000 // I2C module 0
+#define SYSCTL_SET1_I2C 0x00001000 // I2C module
+#define SYSCTL_SET1_QEI1 0x00000200 // QEI module 1
+#define SYSCTL_SET1_QEI 0x00000100 // QEI module
+#define SYSCTL_SET1_QEI0 0x00000100 // QEI module 0
+#define SYSCTL_SET1_SSI1 0x00000020 // SSI module 1
+#define SYSCTL_SET1_SSI0 0x00000010 // SSI module 0
+#define SYSCTL_SET1_SSI 0x00000010 // SSI module
+#define SYSCTL_SET1_UART2 0x00000004 // UART module 2
+#define SYSCTL_SET1_UART1 0x00000002 // UART module 1
+#define SYSCTL_SET1_UART0 0x00000001 // UART module 0
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_SRCR2,
+// SYSCTL_RCGC2, SYSCTL_SCGC2, and SYSCTL_DCGC2 registers.
+//
+//*****************************************************************************
+#define SYSCTL_SET2_ETH 0x50000000 // ETH module
+#define SYSCTL_SET2_GPIOH 0x00000080 // GPIO H module
+#define SYSCTL_SET2_GPIOG 0x00000040 // GPIO G module
+#define SYSCTL_SET2_GPIOF 0x00000020 // GPIO F module
+#define SYSCTL_SET2_GPIOE 0x00000010 // GPIO E module
+#define SYSCTL_SET2_GPIOD 0x00000008 // GPIO D module
+#define SYSCTL_SET2_GPIOC 0x00000004 // GPIO C module
+#define SYSCTL_SET2_GPIOB 0x00000002 // GPIO B module
+#define SYSCTL_SET2_GPIOA 0x00000001 // GIPO A module
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_RIS,
+// SYSCTL_IMC, and SYSCTL_IMS registers.
+//
+//*****************************************************************************
+#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt
+#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt
+#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int
+#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int
+#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt
+#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt
+#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_RESC
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RESC_WDOG 0x00000008 // Watchdog reset
+#define SYSCTL_RESC_WDT 0x00000008 // Watchdog Timer Reset.
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_RCC
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCC_SYSDIV_MASK 0x07800000 // System clock divider
+#define SYSCTL_RCC_USE_SYSDIV 0x00400000 // Use sytem clock divider
+#define SYSCTL_RCC_USE_PWMDIV 0x00100000 // Use PWM clock divider
+#define SYSCTL_RCC_PWMDIV_MASK 0x000E0000 // PWM clock divider
+#define SYSCTL_RCC_OE 0x00001000 // PLL output enable
+#define SYSCTL_RCC_XTAL_3_68MHz 0x00000140 // Using a 3.6864 MHz crystal
+#define SYSCTL_RCC_XTAL_4MHz 0x00000180 // Using a 4 MHz crystal
+#define SYSCTL_RCC_XTAL_MASK 0x000003C0 // Crystal attached to main osc
+#define SYSCTL_RCC_OSCSRC_MASK 0x00000030 // Oscillator input select
+#define SYSCTL_RCC_SYSDIV_SHIFT 23 // Shift to the SYSDIV field
+#define SYSCTL_RCC_PWMDIV_SHIFT 17 // Shift to the PWMDIV field
+#define SYSCTL_RCC_XTAL_SHIFT 6 // Shift to the XTAL field
+#define SYSCTL_RCC_OSCSRC_SHIFT 4 // Shift to the OSCSRC field
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_PLLCFG
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PLLCFG_OD_MASK 0x0000C000 // Output divider
+#define SYSCTL_PLLCFG_F_MASK 0x00003FE0 // PLL multiplier
+#define SYSCTL_PLLCFG_R_MASK 0x0000001F // Input predivider
+#define SYSCTL_PLLCFG_F_SHIFT 5
+#define SYSCTL_PLLCFG_R_SHIFT 0
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_RCC2
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCC2_SYSDIV2_MSK 0x1F800000 // System clock divider
+#define SYSCTL_RCC2_OSCSRC2_MSK 0x00000070 // Oscillator input select
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the
+// SYSCTL_DSLPCLKCFG register.
+//
+//*****************************************************************************
+#define SYSCTL_DSLPCLKCFG_D_MSK 0x1F800000 // Deep sleep system clock override
+#define SYSCTL_DSLPCLKCFG_O_MSK 0x00000070 // Deep sleep oscillator override
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the
+// SYSCTL_CLKVCLR register.
+//
+//*****************************************************************************
+#define SYSCTL_CLKVCLR_CLR 0x00000001 // Clear clock verification fault
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the
+// SYSCTL_LDOARST register.
+//
+//*****************************************************************************
+#define SYSCTL_LDOARST_ARST 0x00000001 // Allow LDO to reset device
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_SRCR0
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCR0_ADC 0x00010000 // ADC0 Reset Control.
+#define SYSCTL_SRCR0_WDT 0x00000008 // WDT Reset Control.
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_RCGC0
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGC0_ADC 0x00010000 // ADC0 Clock Gating Control.
+#define SYSCTL_RCGC0_WDT 0x00000008 // WDT Clock Gating Control.
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_SCGC0
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGC0_ADC 0x00010000 // ADC0 Clock Gating Control.
+#define SYSCTL_SCGC0_WDT 0x00000008 // WDT Clock Gating Control.
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_DCGC0
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGC0_ADC 0x00010000 // ADC0 Clock Gating Control.
+#define SYSCTL_DCGC0_WDT 0x00000008 // WDT Clock Gating Control.
+
+#endif
+
+#endif // __HW_SYSCTL_H__
Property changes on: branches/eagle_mmc/src/platform/lm3s/hw_sysctl.h
___________________________________________________________________
Name: svn:executable
+ *
Modified: branches/eagle_mmc/src/platform/lm3s/hw_timer.h
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/hw_timer.h 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lm3s/hw_timer.h 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,406 +1,452 @@
-//*****************************************************************************
-//
-// hw_timer.h - Defines and macros used when accessing the timer.
-//
-// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
-// Software License Agreement
-//
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
-//
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws. All rights are reserved. You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program. Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
-//
-// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-//
-// This is part of revision 3740 of the Stellaris Firmware Development Package.
-//
-//*****************************************************************************
-
-#ifndef __HW_TIMER_H__
-#define __HW_TIMER_H__
-
-//*****************************************************************************
-//
-// The following are defines for the timer register offsets.
-//
-//*****************************************************************************
-#define TIMER_O_CFG 0x00000000 // Configuration register
-#define TIMER_O_TAMR 0x00000004 // TimerA mode register
-#define TIMER_O_TBMR 0x00000008 // TimerB mode register
-#define TIMER_O_CTL 0x0000000C // Control register
-#define TIMER_O_IMR 0x00000018 // Interrupt mask register
-#define TIMER_O_RIS 0x0000001C // Interrupt status register
-#define TIMER_O_MIS 0x00000020 // Masked interrupt status reg.
-#define TIMER_O_ICR 0x00000024 // Interrupt clear register
-#define TIMER_O_TAILR 0x00000028 // TimerA interval load register
-#define TIMER_O_TBILR 0x0000002C // TimerB interval load register
-#define TIMER_O_TAMATCHR 0x00000030 // TimerA match register
-#define TIMER_O_TBMATCHR 0x00000034 // TimerB match register
-#define TIMER_O_TAPR 0x00000038 // TimerA prescale register
-#define TIMER_O_TBPR 0x0000003C // TimerB prescale register
-#define TIMER_O_TAPMR 0x00000040 // TimerA prescale match register
-#define TIMER_O_TBPMR 0x00000044 // TimerB prescale match register
-#define TIMER_O_TAR 0x00000048 // TimerA register
-#define TIMER_O_TBR 0x0000004C // TimerB register
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_CFG register.
-//
-//*****************************************************************************
-#define TIMER_CFG_M 0x00000007 // GPTM Configuration.
-#define TIMER_CFG_16_BIT 0x00000004 // Two 16 bit timers
-#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32 bit RTC
-#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32 bit timer
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_CTL register.
-//
-//*****************************************************************************
-#define TIMER_CTL_TBPWML 0x00004000 // TimerB PWM output level invert
-#define TIMER_CTL_TBOTE 0x00002000 // TimerB output trigger enable
-#define TIMER_CTL_TBEVENT_POS 0x00000000 // TimerB event mode - pos edge
-#define TIMER_CTL_TBEVENT_NEG 0x00000400 // TimerB event mode - neg edge
-#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // TimerB event mode - both edges
-#define TIMER_CTL_TBEVENT_M 0x00000C00 // GPTM TimerB Event Mode.
-#define TIMER_CTL_TBSTALL 0x00000200 // TimerB stall enable
-#define TIMER_CTL_TBEN 0x00000100 // TimerB enable
-#define TIMER_CTL_TAPWML 0x00000040 // TimerA PWM output level invert
-#define TIMER_CTL_TAOTE 0x00000020 // TimerA output trigger enable
-#define TIMER_CTL_RTCEN 0x00000010 // RTC counter enable
-#define TIMER_CTL_TAEVENT_M 0x0000000C // GPTM TimerA Event Mode.
-#define TIMER_CTL_TAEVENT_POS 0x00000000 // TimerA event mode - pos edge
-#define TIMER_CTL_TAEVENT_NEG 0x00000004 // TimerA event mode - neg edge
-#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // TimerA event mode - both edges
-#define TIMER_CTL_TASTALL 0x00000002 // TimerA stall enable
-#define TIMER_CTL_TAEN 0x00000001 // TimerA enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_IMR register.
-//
-//*****************************************************************************
-#define TIMER_IMR_CBEIM 0x00000400 // CaptureB event interrupt mask
-#define TIMER_IMR_CBMIM 0x00000200 // CaptureB match interrupt mask
-#define TIMER_IMR_TBTOIM 0x00000100 // TimerB time out interrupt mask
-#define TIMER_IMR_RTCIM 0x00000008 // RTC interrupt mask
-#define TIMER_IMR_CAEIM 0x00000004 // CaptureA event interrupt mask
-#define TIMER_IMR_CAMIM 0x00000002 // CaptureA match interrupt mask
-#define TIMER_IMR_TATOIM 0x00000001 // TimerA time out interrupt mask
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_RIS register.
-//
-//*****************************************************************************
-#define TIMER_RIS_CBERIS 0x00000400 // CaptureB event raw int status
-#define TIMER_RIS_CBMRIS 0x00000200 // CaptureB match raw int status
-#define TIMER_RIS_TBTORIS 0x00000100 // TimerB time out raw int status
-#define TIMER_RIS_RTCRIS 0x00000008 // RTC raw int status
-#define TIMER_RIS_CAERIS 0x00000004 // CaptureA event raw int status
-#define TIMER_RIS_CAMRIS 0x00000002 // CaptureA match raw int status
-#define TIMER_RIS_TATORIS 0x00000001 // TimerA time out raw int status
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_ICR register.
-//
-//*****************************************************************************
-#define TIMER_ICR_CBECINT 0x00000400 // CaptureB event interrupt clear
-#define TIMER_ICR_CBMCINT 0x00000200 // CaptureB match interrupt clear
-#define TIMER_ICR_TBTOCINT 0x00000100 // TimerB time out interrupt clear
-#define TIMER_ICR_RTCCINT 0x00000008 // RTC interrupt clear
-#define TIMER_ICR_CAECINT 0x00000004 // CaptureA event interrupt clear
-#define TIMER_ICR_CAMCINT 0x00000002 // CaptureA match interrupt clear
-#define TIMER_ICR_TATOCINT 0x00000001 // TimerA time out interrupt clear
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_TAILR register.
-//
-//*****************************************************************************
-#define TIMER_TAILR_TAILRH_M 0xFFFF0000 // GPTM TimerA Interval Load
- // Register High.
-#define TIMER_TAILR_TAILRL_M 0x0000FFFF // GPTM TimerA Interval Load
- // Register Low.
-#define TIMER_TAILR_TAILRH_S 16
-#define TIMER_TAILR_TAILRL_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_TBILR register.
-//
-//*****************************************************************************
-#define TIMER_TBILR_TBILRL_M 0x0000FFFF // GPTM TimerB Interval Load
- // Register.
-#define TIMER_TBILR_TBILRL_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_TAMATCHR register.
-//
-//*****************************************************************************
-#define TIMER_TAMATCHR_TAMRH_M 0xFFFF0000 // GPTM TimerA Match Register High.
-#define TIMER_TAMATCHR_TAMRL_M 0x0000FFFF // GPTM TimerA Match Register Low.
-#define TIMER_TAMATCHR_TAMRH_S 16
-#define TIMER_TAMATCHR_TAMRL_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_TBMATCHR register.
-//
-//*****************************************************************************
-#define TIMER_TBMATCHR_TBMRL_M 0x0000FFFF // GPTM TimerB Match Register Low.
-#define TIMER_TBMATCHR_TBMRL_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_TAR register.
-//
-//*****************************************************************************
-#define TIMER_TAR_TARH_M 0xFFFF0000 // GPTM TimerA Register High.
-#define TIMER_TAR_TARL_M 0x0000FFFF // GPTM TimerA Register Low.
-#define TIMER_TAR_TARH_S 16
-#define TIMER_TAR_TARL_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_TBR register.
-//
-//*****************************************************************************
-#define TIMER_TBR_TBRL_M 0x0000FFFF // GPTM TimerB.
-#define TIMER_TBR_TBRL_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_O_TAMR register.
-//
-//*****************************************************************************
-#define TIMER_TAMR_TAAMS 0x00000008 // GPTM TimerA Alternate Mode
- // Select.
-#define TIMER_TAMR_TACMR 0x00000004 // GPTM TimerA Capture Mode.
-#define TIMER_TAMR_TAMR_M 0x00000003 // GPTM TimerA Mode.
-#define TIMER_TAMR_TAMR_1_SHOT 0x00000001 // One-Shot Timer mode.
-#define TIMER_TAMR_TAMR_PERIOD 0x00000002 // Periodic Timer mode.
-#define TIMER_TAMR_TAMR_CAP 0x00000003 // Capture mode.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_O_TBMR register.
-//
-//*****************************************************************************
-#define TIMER_TBMR_TBAMS 0x00000008 // GPTM TimerB Alternate Mode
- // Select.
-#define TIMER_TBMR_TBCMR 0x00000004 // GPTM TimerB Capture Mode.
-#define TIMER_TBMR_TBMR_M 0x00000003 // GPTM TimerB Mode.
-#define TIMER_TBMR_TBMR_1_SHOT 0x00000001 // One-Shot Timer mode.
-#define TIMER_TBMR_TBMR_PERIOD 0x00000002 // Periodic Timer mode.
-#define TIMER_TBMR_TBMR_CAP 0x00000003 // Capture mode.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_O_MIS register.
-//
-//*****************************************************************************
-#define TIMER_MIS_CBEMIS 0x00000400 // GPTM CaptureB Event Masked
- // Interrupt.
-#define TIMER_MIS_CBMMIS 0x00000200 // GPTM CaptureB Match Masked
- // Interrupt.
-#define TIMER_MIS_TBTOMIS 0x00000100 // GPTM TimerB Time-Out Masked
- // Interrupt.
-#define TIMER_MIS_RTCMIS 0x00000008 // GPTM RTC Masked Interrupt.
-#define TIMER_MIS_CAEMIS 0x00000004 // GPTM CaptureA Event Masked
- // Interrupt.
-#define TIMER_MIS_CAMMIS 0x00000002 // GPTM CaptureA Match Masked
- // Interrupt.
-#define TIMER_MIS_TATOMIS 0x00000001 // GPTM TimerA Time-Out Masked
- // Interrupt.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_O_TAPR register.
-//
-//*****************************************************************************
-#define TIMER_TAPR_TAPSR_M 0x000000FF // GPTM TimerA Prescale.
-#define TIMER_TAPR_TAPSR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_O_TBPR register.
-//
-//*****************************************************************************
-#define TIMER_TBPR_TBPSR_M 0x000000FF // GPTM TimerB Prescale.
-#define TIMER_TBPR_TBPSR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_O_TAPMR register.
-//
-//*****************************************************************************
-#define TIMER_TAPMR_TAPSMR_M 0x000000FF // GPTM TimerA Prescale Match.
-#define TIMER_TAPMR_TAPSMR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_O_TBPMR register.
-//
-//*****************************************************************************
-#define TIMER_TBPMR_TBPSMR_M 0x000000FF // GPTM TimerB Prescale Match.
-#define TIMER_TBPMR_TBPSMR_S 0
-
-//*****************************************************************************
-//
-// The following definitions are deprecated.
-//
-//*****************************************************************************
-#ifndef DEPRECATED
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the reset values of the timer
-// registers.
-//
-//*****************************************************************************
-#define TIMER_RV_TAILR 0xFFFFFFFF // TimerA interval load reg RV
-#define TIMER_RV_TAR 0xFFFFFFFF // TimerA register RV
-#define TIMER_RV_TAMATCHR 0xFFFFFFFF // TimerA match register RV
-#define TIMER_RV_TBILR 0x0000FFFF // TimerB interval load reg RV
-#define TIMER_RV_TBMATCHR 0x0000FFFF // TimerB match register RV
-#define TIMER_RV_TBR 0x0000FFFF // TimerB register RV
-#define TIMER_RV_TAPR 0x00000000 // TimerA prescale register RV
-#define TIMER_RV_CFG 0x00000000 // Configuration register RV
-#define TIMER_RV_TBPMR 0x00000000 // TimerB prescale match regi RV
-#define TIMER_RV_TAPMR 0x00000000 // TimerA prescale match reg RV
-#define TIMER_RV_CTL 0x00000000 // Control register RV
-#define TIMER_RV_ICR 0x00000000 // Interrupt clear register RV
-#define TIMER_RV_TBMR 0x00000000 // TimerB mode register RV
-#define TIMER_RV_MIS 0x00000000 // Masked interrupt status reg RV
-#define TIMER_RV_RIS 0x00000000 // Interrupt status register RV
-#define TIMER_RV_TBPR 0x00000000 // TimerB prescale register RV
-#define TIMER_RV_IMR 0x00000000 // Interrupt mask register RV
-#define TIMER_RV_TAMR 0x00000000 // TimerA mode register RV
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the TIMER_CFG
-// register.
-//
-//*****************************************************************************
-#define TIMER_CFG_CFG_MSK 0x00000007 // Configuration options mask
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the TIMER_TnMR
-// register.
-//
-//*****************************************************************************
-#define TIMER_TNMR_TNAMS 0x00000008 // Alternate mode select
-#define TIMER_TNMR_TNCMR 0x00000004 // Capture mode - count or time
-#define TIMER_TNMR_TNTMR_MSK 0x00000003 // Timer mode mask
-#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001 // Mode - one shot
-#define TIMER_TNMR_TNTMR_PERIOD 0x00000002 // Mode - periodic
-#define TIMER_TNMR_TNTMR_CAP 0x00000003 // Mode - capture
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the TIMER_CTL
-// register.
-//
-//*****************************************************************************
-#define TIMER_CTL_TBEVENT_MSK 0x00000C00 // TimerB event mode mask
-#define TIMER_CTL_TAEVENT_MSK 0x0000000C // TimerA event mode mask
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the TIMER_MIS
-// register.
-//
-//*****************************************************************************
-#define TIMER_RIS_CBEMIS 0x00000400 // CaptureB event masked int status
-#define TIMER_RIS_CBMMIS 0x00000200 // CaptureB match masked int status
-#define TIMER_RIS_TBTOMIS 0x00000100 // TimerB time out masked int stat
-#define TIMER_RIS_RTCMIS 0x00000008 // RTC masked int status
-#define TIMER_RIS_CAEMIS 0x00000004 // CaptureA event masked int status
-#define TIMER_RIS_CAMMIS 0x00000002 // CaptureA match masked int status
-#define TIMER_RIS_TATOMIS 0x00000001 // TimerA time out masked int stat
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the TIMER_TAILR
-// register.
-//
-//*****************************************************************************
-#define TIMER_TAILR_TAILRH 0xFFFF0000 // TimerB load val in 32 bit mode
-#define TIMER_TAILR_TAILRL 0x0000FFFF // TimerA interval load value
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the TIMER_TBILR
-// register.
-//
-//*****************************************************************************
-#define TIMER_TBILR_TBILRL 0x0000FFFF // TimerB interval load value
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the
-// TIMER_TAMATCHR register.
-//
-//*****************************************************************************
-#define TIMER_TAMATCHR_TAMRH 0xFFFF0000 // TimerB match val in 32 bit mode
-#define TIMER_TAMATCHR_TAMRL 0x0000FFFF // TimerA match value
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the
-// TIMER_TBMATCHR register.
-//
-//*****************************************************************************
-#define TIMER_TBMATCHR_TBMRL 0x0000FFFF // TimerB match load value
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the TIMER_TnPR
-// register.
-//
-//*****************************************************************************
-#define TIMER_TNPR_TNPSR 0x000000FF // TimerN prescale value
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the TIMER_TnPMR
-// register.
-//
-//*****************************************************************************
-#define TIMER_TNPMR_TNPSMR 0x000000FF // TimerN prescale match value
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the TIMER_TAR
-// register.
-//
-//*****************************************************************************
-#define TIMER_TAR_TARH 0xFFFF0000 // TimerB val in 32 bit mode
-#define TIMER_TAR_TARL 0x0000FFFF // TimerA value
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the TIMER_TBR
-// register.
-//
-//*****************************************************************************
-#define TIMER_TBR_TBRL 0x0000FFFF // TimerB value
-
-#endif
-
-#endif // __HW_TIMER_H__
+//*****************************************************************************
+//
+// hw_timer.h - Defines and macros used when accessing the timer.
+//
+// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4781 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_TIMER_H__
+#define __HW_TIMER_H__
+
+//*****************************************************************************
+//
+// The following are defines for the timer register offsets.
+//
+//*****************************************************************************
+#define TIMER_O_CFG 0x00000000 // Configuration register
+#define TIMER_O_TAMR 0x00000004 // TimerA mode register
+#define TIMER_O_TBMR 0x00000008 // TimerB mode register
+#define TIMER_O_CTL 0x0000000C // Control register
+#define TIMER_O_IMR 0x00000018 // Interrupt mask register
+#define TIMER_O_RIS 0x0000001C // Interrupt status register
+#define TIMER_O_MIS 0x00000020 // Masked interrupt status reg.
+#define TIMER_O_ICR 0x00000024 // Interrupt clear register
+#define TIMER_O_TAILR 0x00000028 // TimerA interval load register
+#define TIMER_O_TBILR 0x0000002C // TimerB interval load register
+#define TIMER_O_TAMATCHR 0x00000030 // TimerA match register
+#define TIMER_O_TBMATCHR 0x00000034 // TimerB match register
+#define TIMER_O_TAPR 0x00000038 // TimerA prescale register
+#define TIMER_O_TBPR 0x0000003C // TimerB prescale register
+#define TIMER_O_TAPMR 0x00000040 // TimerA prescale match register
+#define TIMER_O_TBPMR 0x00000044 // TimerB prescale match register
+#define TIMER_O_TAR 0x00000048 // TimerA register
+#define TIMER_O_TBR 0x0000004C // TimerB register
+#define TIMER_O_TAV 0x00000050 // GPTM Timer A Value
+#define TIMER_O_TBV 0x00000054 // GPTM Timer B Value
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_CFG register.
+//
+//*****************************************************************************
+#define TIMER_CFG_M 0x00000007 // GPTM Configuration.
+#define TIMER_CFG_16_BIT 0x00000004 // Two 16 bit timers
+#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32 bit RTC
+#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32 bit timer
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_CTL register.
+//
+//*****************************************************************************
+#define TIMER_CTL_TBPWML 0x00004000 // TimerB PWM output level invert
+#define TIMER_CTL_TBOTE 0x00002000 // TimerB output trigger enable
+#define TIMER_CTL_TBEVENT_POS 0x00000000 // TimerB event mode - pos edge
+#define TIMER_CTL_TBEVENT_NEG 0x00000400 // TimerB event mode - neg edge
+#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // TimerB event mode - both edges
+#define TIMER_CTL_TBEVENT_M 0x00000C00 // GPTM TimerB Event Mode.
+#define TIMER_CTL_TBSTALL 0x00000200 // TimerB stall enable
+#define TIMER_CTL_TBEN 0x00000100 // TimerB enable
+#define TIMER_CTL_TAPWML 0x00000040 // TimerA PWM output level invert
+#define TIMER_CTL_TAOTE 0x00000020 // TimerA output trigger enable
+#define TIMER_CTL_RTCEN 0x00000010 // RTC counter enable
+#define TIMER_CTL_TAEVENT_M 0x0000000C // GPTM TimerA Event Mode.
+#define TIMER_CTL_TAEVENT_POS 0x00000000 // TimerA event mode - pos edge
+#define TIMER_CTL_TAEVENT_NEG 0x00000004 // TimerA event mode - neg edge
+#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // TimerA event mode - both edges
+#define TIMER_CTL_TASTALL 0x00000002 // TimerA stall enable
+#define TIMER_CTL_TAEN 0x00000001 // TimerA enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_IMR register.
+//
+//*****************************************************************************
+#define TIMER_IMR_TBMIM 0x00000800 // GPTM Timer B Mode Match
+ // Interrupt Mask.
+#define TIMER_IMR_CBEIM 0x00000400 // CaptureB event interrupt mask
+#define TIMER_IMR_CBMIM 0x00000200 // CaptureB match interrupt mask
+#define TIMER_IMR_TBTOIM 0x00000100 // TimerB time out interrupt mask
+#define TIMER_IMR_TAMIM 0x00000010 // GPTM Timer A Mode Match
+ // Interrupt Mask.
+#define TIMER_IMR_RTCIM 0x00000008 // RTC interrupt mask
+#define TIMER_IMR_CAEIM 0x00000004 // CaptureA event interrupt mask
+#define TIMER_IMR_CAMIM 0x00000002 // CaptureA match interrupt mask
+#define TIMER_IMR_TATOIM 0x00000001 // TimerA time out interrupt mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_RIS register.
+//
+//*****************************************************************************
+#define TIMER_RIS_TBMRIS 0x00000800 // GPTM Timer B Mode Match Raw
+ // Interrupt.
+#define TIMER_RIS_CBERIS 0x00000400 // CaptureB event raw int status
+#define TIMER_RIS_CBMRIS 0x00000200 // CaptureB match raw int status
+#define TIMER_RIS_TBTORIS 0x00000100 // TimerB time out raw int status
+#define TIMER_RIS_TAMRIS 0x00000010 // GPTM Timer A Mode Match Raw
+ // Interrupt.
+#define TIMER_RIS_RTCRIS 0x00000008 // RTC raw int status
+#define TIMER_RIS_CAERIS 0x00000004 // CaptureA event raw int status
+#define TIMER_RIS_CAMRIS 0x00000002 // CaptureA match raw int status
+#define TIMER_RIS_TATORIS 0x00000001 // TimerA time out raw int status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_ICR register.
+//
+//*****************************************************************************
+#define TIMER_ICR_TBMCINT 0x00000800 // GPTM Timer B Mode Match
+ // Interrupt Clear.
+#define TIMER_ICR_CBECINT 0x00000400 // CaptureB event interrupt clear
+#define TIMER_ICR_CBMCINT 0x00000200 // CaptureB match interrupt clear
+#define TIMER_ICR_TBTOCINT 0x00000100 // TimerB time out interrupt clear
+#define TIMER_ICR_TAMCINT 0x00000010 // GPTM Timer A Mode Match
+ // Interrupt Clear.
+#define TIMER_ICR_RTCCINT 0x00000008 // RTC interrupt clear
+#define TIMER_ICR_CAECINT 0x00000004 // CaptureA event interrupt clear
+#define TIMER_ICR_CAMCINT 0x00000002 // CaptureA match interrupt clear
+#define TIMER_ICR_TATOCINT 0x00000001 // TimerA time out interrupt clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_TAILR register.
+//
+//*****************************************************************************
+#define TIMER_TAILR_TAILRH_M 0xFFFF0000 // GPTM TimerA Interval Load
+ // Register High.
+#define TIMER_TAILR_TAILRL_M 0x0000FFFF // GPTM TimerA Interval Load
+ // Register Low.
+#define TIMER_TAILR_TAILRH_S 16
+#define TIMER_TAILR_TAILRL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_TBILR register.
+//
+//*****************************************************************************
+#define TIMER_TBILR_TBILRL_M 0x0000FFFF // GPTM TimerB Interval Load
+ // Register.
+#define TIMER_TBILR_TBILRL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_TAMATCHR register.
+//
+//*****************************************************************************
+#define TIMER_TAMATCHR_TAMRH_M 0xFFFF0000 // GPTM TimerA Match Register High.
+#define TIMER_TAMATCHR_TAMRL_M 0x0000FFFF // GPTM TimerA Match Register Low.
+#define TIMER_TAMATCHR_TAMRH_S 16
+#define TIMER_TAMATCHR_TAMRL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_TBMATCHR register.
+//
+//*****************************************************************************
+#define TIMER_TBMATCHR_TBMRL_M 0x0000FFFF // GPTM TimerB Match Register Low.
+#define TIMER_TBMATCHR_TBMRL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_TAR register.
+//
+//*****************************************************************************
+#define TIMER_TAR_TARH_M 0xFFFF0000 // GPTM TimerA Register High.
+#define TIMER_TAR_TARL_M 0x0000FFFF // GPTM TimerA Register Low.
+#define TIMER_TAR_TARH_S 16
+#define TIMER_TAR_TARL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_TBR register.
+//
+//*****************************************************************************
+#define TIMER_TBR_TBRL_M 0x0000FFFF // GPTM TimerB.
+#define TIMER_TBR_TBRL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAMR register.
+//
+//*****************************************************************************
+#define TIMER_TAMR_TASNAPS 0x00000080 // GPTM Timer A Snap-Shot Mode.
+#define TIMER_TAMR_TAWOT 0x00000040 // GPTM Timer A Wait-on-Trigger.
+#define TIMER_TAMR_TAMIE 0x00000020 // GPTM Timer A Match Interrupt
+ // Enable.
+#define TIMER_TAMR_TACDIR 0x00000010 // GPTM Timer A Count Direction.
+#define TIMER_TAMR_TAAMS 0x00000008 // GPTM TimerA Alternate Mode
+ // Select.
+#define TIMER_TAMR_TACMR 0x00000004 // GPTM TimerA Capture Mode.
+#define TIMER_TAMR_TAMR_M 0x00000003 // GPTM TimerA Mode.
+#define TIMER_TAMR_TAMR_1_SHOT 0x00000001 // One-Shot Timer mode.
+#define TIMER_TAMR_TAMR_PERIOD 0x00000002 // Periodic Timer mode.
+#define TIMER_TAMR_TAMR_CAP 0x00000003 // Capture mode.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBMR register.
+//
+//*****************************************************************************
+#define TIMER_TBMR_TBSNAPS 0x00000080 // GPTM Timer B Snap-Shot Mode.
+#define TIMER_TBMR_TBWOT 0x00000040 // GPTM Timer B Wait-on-Trigger.
+#define TIMER_TBMR_TBMIE 0x00000020 // GPTM Timer B Match Interrupt
+ // Enable.
+#define TIMER_TBMR_TBCDIR 0x00000010 // GPTM Timer B Count Direction.
+#define TIMER_TBMR_TBAMS 0x00000008 // GPTM TimerB Alternate Mode
+ // Select.
+#define TIMER_TBMR_TBCMR 0x00000004 // GPTM TimerB Capture Mode.
+#define TIMER_TBMR_TBMR_M 0x00000003 // GPTM TimerB Mode.
+#define TIMER_TBMR_TBMR_1_SHOT 0x00000001 // One-Shot Timer mode.
+#define TIMER_TBMR_TBMR_PERIOD 0x00000002 // Periodic Timer mode.
+#define TIMER_TBMR_TBMR_CAP 0x00000003 // Capture mode.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_MIS register.
+//
+//*****************************************************************************
+#define TIMER_MIS_TBMMIS 0x00000800 // GPTM Timer B Mode Match Masked
+ // Interrupt.
+#define TIMER_MIS_CBEMIS 0x00000400 // GPTM CaptureB Event Masked
+ // Interrupt.
+#define TIMER_MIS_CBMMIS 0x00000200 // GPTM CaptureB Match Masked
+ // Interrupt.
+#define TIMER_MIS_TBTOMIS 0x00000100 // GPTM TimerB Time-Out Masked
+ // Interrupt.
+#define TIMER_MIS_TAMMIS 0x00000010 // GPTM Timer A Mode Match Masked
+ // Interrupt.
+#define TIMER_MIS_RTCMIS 0x00000008 // GPTM RTC Masked Interrupt.
+#define TIMER_MIS_CAEMIS 0x00000004 // GPTM CaptureA Event Masked
+ // Interrupt.
+#define TIMER_MIS_CAMMIS 0x00000002 // GPTM CaptureA Match Masked
+ // Interrupt.
+#define TIMER_MIS_TATOMIS 0x00000001 // GPTM TimerA Time-Out Masked
+ // Interrupt.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAPR register.
+//
+//*****************************************************************************
+#define TIMER_TAPR_TAPSR_M 0x000000FF // GPTM TimerA Prescale.
+#define TIMER_TAPR_TAPSR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBPR register.
+//
+//*****************************************************************************
+#define TIMER_TBPR_TBPSR_M 0x000000FF // GPTM TimerB Prescale.
+#define TIMER_TBPR_TBPSR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAPMR register.
+//
+//*****************************************************************************
+#define TIMER_TAPMR_TAPSMR_M 0x000000FF // GPTM TimerA Prescale Match.
+#define TIMER_TAPMR_TAPSMR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBPMR register.
+//
+//*****************************************************************************
+#define TIMER_TBPMR_TBPSMR_M 0x000000FF // GPTM TimerB Prescale Match.
+#define TIMER_TBPMR_TBPSMR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAV register.
+//
+//*****************************************************************************
+#define TIMER_TAV_TAVH_M 0xFFFF0000 // GPTM Timer A Value High.
+#define TIMER_TAV_TAVL_M 0x0000FFFF // GPTM Timer A Register Low.
+#define TIMER_TAV_TAVH_S 16
+#define TIMER_TAV_TAVL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBV register.
+//
+//*****************************************************************************
+#define TIMER_TBV_TBVL_M 0x0000FFFF // GPTM Timer B Register.
+#define TIMER_TBV_TBVL_S 0
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the reset values of the timer
+// registers.
+//
+//*****************************************************************************
+#define TIMER_RV_TAILR 0xFFFFFFFF // TimerA interval load reg RV
+#define TIMER_RV_TAR 0xFFFFFFFF // TimerA register RV
+#define TIMER_RV_TAMATCHR 0xFFFFFFFF // TimerA match register RV
+#define TIMER_RV_TBILR 0x0000FFFF // TimerB interval load reg RV
+#define TIMER_RV_TBMATCHR 0x0000FFFF // TimerB match register RV
+#define TIMER_RV_TBR 0x0000FFFF // TimerB register RV
+#define TIMER_RV_TAPR 0x00000000 // TimerA prescale register RV
+#define TIMER_RV_CFG 0x00000000 // Configuration register RV
+#define TIMER_RV_TBPMR 0x00000000 // TimerB prescale match regi RV
+#define TIMER_RV_TAPMR 0x00000000 // TimerA prescale match reg RV
+#define TIMER_RV_CTL 0x00000000 // Control register RV
+#define TIMER_RV_ICR 0x00000000 // Interrupt clear register RV
+#define TIMER_RV_TBMR 0x00000000 // TimerB mode register RV
+#define TIMER_RV_MIS 0x00000000 // Masked interrupt status reg RV
+#define TIMER_RV_RIS 0x00000000 // Interrupt status register RV
+#define TIMER_RV_TBPR 0x00000000 // TimerB prescale register RV
+#define TIMER_RV_IMR 0x00000000 // Interrupt mask register RV
+#define TIMER_RV_TAMR 0x00000000 // TimerA mode register RV
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the TIMER_CFG
+// register.
+//
+//*****************************************************************************
+#define TIMER_CFG_CFG_MSK 0x00000007 // Configuration options mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the TIMER_TnMR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TNMR_TNAMS 0x00000008 // Alternate mode select
+#define TIMER_TNMR_TNCMR 0x00000004 // Capture mode - count or time
+#define TIMER_TNMR_TNTMR_MSK 0x00000003 // Timer mode mask
+#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001 // Mode - one shot
+#define TIMER_TNMR_TNTMR_PERIOD 0x00000002 // Mode - periodic
+#define TIMER_TNMR_TNTMR_CAP 0x00000003 // Mode - capture
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the TIMER_CTL
+// register.
+//
+//*****************************************************************************
+#define TIMER_CTL_TBEVENT_MSK 0x00000C00 // TimerB event mode mask
+#define TIMER_CTL_TAEVENT_MSK 0x0000000C // TimerA event mode mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the TIMER_MIS
+// register.
+//
+//*****************************************************************************
+#define TIMER_RIS_CBEMIS 0x00000400 // CaptureB event masked int status
+#define TIMER_RIS_CBMMIS 0x00000200 // CaptureB match masked int status
+#define TIMER_RIS_TBTOMIS 0x00000100 // TimerB time out masked int stat
+#define TIMER_RIS_RTCMIS 0x00000008 // RTC masked int status
+#define TIMER_RIS_CAEMIS 0x00000004 // CaptureA event masked int status
+#define TIMER_RIS_CAMMIS 0x00000002 // CaptureA match masked int status
+#define TIMER_RIS_TATOMIS 0x00000001 // TimerA time out masked int stat
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the TIMER_TAILR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TAILR_TAILRH 0xFFFF0000 // TimerB load val in 32 bit mode
+#define TIMER_TAILR_TAILRL 0x0000FFFF // TimerA interval load value
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the TIMER_TBILR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TBILR_TBILRL 0x0000FFFF // TimerB interval load value
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the
+// TIMER_TAMATCHR register.
+//
+//*****************************************************************************
+#define TIMER_TAMATCHR_TAMRH 0xFFFF0000 // TimerB match val in 32 bit mode
+#define TIMER_TAMATCHR_TAMRL 0x0000FFFF // TimerA match value
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the
+// TIMER_TBMATCHR register.
+//
+//*****************************************************************************
+#define TIMER_TBMATCHR_TBMRL 0x0000FFFF // TimerB match load value
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the TIMER_TnPR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TNPR_TNPSR 0x000000FF // TimerN prescale value
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the TIMER_TnPMR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TNPMR_TNPSMR 0x000000FF // TimerN prescale match value
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the TIMER_TAR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TAR_TARH 0xFFFF0000 // TimerB val in 32 bit mode
+#define TIMER_TAR_TARL 0x0000FFFF // TimerA value
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the TIMER_TBR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TBR_TBRL 0x0000FFFF // TimerB value
+
+#endif
+
+#endif // __HW_TIMER_H__
Property changes on: branches/eagle_mmc/src/platform/lm3s/hw_timer.h
___________________________________________________________________
Name: svn:executable
+ *
Modified: branches/eagle_mmc/src/platform/lm3s/hw_types.h
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/hw_types.h 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lm3s/hw_types.h 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,158 +1,176 @@
-//*****************************************************************************
-//
-// hw_types.h - Common types and macros.
-//
-// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
-// Software License Agreement
-//
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
-//
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws. All rights are reserved. You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program. Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
-//
-// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-//
-// This is part of revision 3740 of the Stellaris Firmware Development Package.
-//
-//*****************************************************************************
-
-#ifndef __HW_TYPES_H__
-#define __HW_TYPES_H__
-
-//*****************************************************************************
-//
-// Define a boolean type, and values for true and false.
-//
-//*****************************************************************************
-typedef unsigned char tBoolean;
-
-#ifndef true
-#define true 1
-#endif
-
-#ifndef false
-#define false 0
-#endif
-
-//*****************************************************************************
-//
-// Macros for hardware access, both direct and via the bit-band region.
-//
-//*****************************************************************************
-#define HWREG(x) \
- (*((volatile unsigned long *)(x)))
-#define HWREGH(x) \
- (*((volatile unsigned short *)(x)))
-#define HWREGB(x) \
- (*((volatile unsigned char *)(x)))
-#define HWREGBITW(x, b) \
- HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \
- (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
-#define HWREGBITH(x, b) \
- HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \
- (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
-#define HWREGBITB(x, b) \
- HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \
- (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
-
-//*****************************************************************************
-//
-// Helper Macros for determining silicon revisions, etc.
-//
-// These macros will be used by Driverlib at "run-time" to create necessary
-// conditional code blocks that will allow a single version of the Driverlib
-// "binary" code to support multiple(all) Stellaris silicon revisions.
-//
-// It is expected that these macros will be used inside of a standard 'C'
-// conditional block of code, e.g.
-//
-// if(CLASS_IS_SANDSTORM)
-// {
-// do some Sandstorm-class specific code here.
-// }
-//
-// By default, these macros will be defined as run-time checks of the
-// appropriate register(s) to allow creation of run-time conditional code
-// blocks for a common DriverLib across the entire Stellaris family.
-//
-// However, if code-space optimization is required, these macros can be "hard-
-// coded" for a specific version of Stellaris silicon. Many compilers will
-// then detect the "hard-coded" conditionals, and appropriately optimize the
-// code blocks, eliminating any "unreachable" code. This would result in
-// a smaller Driverlib, thus producing a smaller final application size, but
-// at the cost of limiting the Driverlib binary to a specific Stellaris
-// silicon revision.
-//
-//*****************************************************************************
-#ifndef CLASS_IS_SANDSTORM
-#define CLASS_IS_SANDSTORM \
- (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_VER_M) == SYSCTL_DID0_VER_0) || \
- ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
- (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_SANDSTORM)))
-#endif
-
-#ifndef CLASS_IS_FURY
-#define CLASS_IS_FURY \
- ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
- (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_FURY))
-#endif
-
-#ifndef CLASS_IS_DUSTDEVIL
-#define CLASS_IS_DUSTDEVIL \
- ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
- (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_DUSTDEVIL))
-#endif
-
-#ifndef REVISION_IS_A0
-#define REVISION_IS_A0 \
- ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
- (SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_0))
-#endif
-
-#ifndef REVISION_IS_A1
-#define REVISION_IS_A1 \
- ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
- (SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_0))
-#endif
-
-#ifndef REVISION_IS_A2
-#define REVISION_IS_A2 \
- ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
- (SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_2))
-#endif
-
-#ifndef REVISION_IS_C1
-#define REVISION_IS_C1 \
- ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
- (SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_1))
-#endif
-
-#ifndef REVISION_IS_C2
-#define REVISION_IS_C2 \
- ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
- (SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_2))
-#endif
-
-//*****************************************************************************
-//
-// Deprecated silicon class and revision detection macros.
-//
-//*****************************************************************************
-#ifndef DEPRECATED
-#define DEVICE_IS_SANDSTORM CLASS_IS_SANDSTORM
-#define DEVICE_IS_FURY CLASS_IS_FURY
-#define DEVICE_IS_REVA2 REVISION_IS_A2
-#define DEVICE_IS_REVC1 REVISION_IS_C1
-#define DEVICE_IS_REVC2 REVISION_IS_C2
-#endif
-
-#endif // __HW_TYPES_H__
+//*****************************************************************************
+//
+// hw_types.h - Common types and macros.
+//
+// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4781 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_TYPES_H__
+#define __HW_TYPES_H__
+
+//*****************************************************************************
+//
+// Define a boolean type, and values for true and false.
+//
+//*****************************************************************************
+typedef unsigned char tBoolean;
+
+#ifndef true
+#define true 1
+#endif
+
+#ifndef false
+#define false 0
+#endif
+
+//*****************************************************************************
+//
+// Macros for hardware access, both direct and via the bit-band region.
+//
+//*****************************************************************************
+#define HWREG(x) \
+ (*((volatile unsigned long *)(x)))
+#define HWREGH(x) \
+ (*((volatile unsigned short *)(x)))
+#define HWREGB(x) \
+ (*((volatile unsigned char *)(x)))
+#define HWREGBITW(x, b) \
+ HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \
+ (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
+#define HWREGBITH(x, b) \
+ HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \
+ (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
+#define HWREGBITB(x, b) \
+ HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \
+ (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
+
+//*****************************************************************************
+//
+// Helper Macros for determining silicon revisions, etc.
+//
+// These macros will be used by Driverlib at "run-time" to create necessary
+// conditional code blocks that will allow a single version of the Driverlib
+// "binary" code to support multiple(all) Stellaris silicon revisions.
+//
+// It is expected that these macros will be used inside of a standard 'C'
+// conditional block of code, e.g.
+//
+// if(CLASS_IS_SANDSTORM)
+// {
+// do some Sandstorm-class specific code here.
+// }
+//
+// By default, these macros will be defined as run-time checks of the
+// appropriate register(s) to allow creation of run-time conditional code
+// blocks for a common DriverLib across the entire Stellaris family.
+//
+// However, if code-space optimization is required, these macros can be "hard-
+// coded" for a specific version of Stellaris silicon. Many compilers will
+// then detect the "hard-coded" conditionals, and appropriately optimize the
+// code blocks, eliminating any "unreachable" code. This would result in
+// a smaller Driverlib, thus producing a smaller final application size, but
+// at the cost of limiting the Driverlib binary to a specific Stellaris
+// silicon revision.
+//
+//*****************************************************************************
+#ifndef CLASS_IS_SANDSTORM
+#define CLASS_IS_SANDSTORM \
+ (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_VER_M) == SYSCTL_DID0_VER_0) || \
+ ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
+ (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_SANDSTORM)))
+#endif
+
+#ifndef CLASS_IS_FURY
+#define CLASS_IS_FURY \
+ ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
+ (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_FURY))
+#endif
+
+#ifndef CLASS_IS_DUSTDEVIL
+#define CLASS_IS_DUSTDEVIL \
+ ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
+ (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_DUSTDEVIL))
+#endif
+
+#ifndef CLASS_IS_TEMPEST
+#define CLASS_IS_TEMPEST \
+ ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
+ (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_TEMPEST))
+#endif
+
+#ifndef REVISION_IS_A0
+#define REVISION_IS_A0 \
+ ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
+ (SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_0))
+#endif
+
+#ifndef REVISION_IS_A1
+#define REVISION_IS_A1 \
+ ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
+ (SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_0))
+#endif
+
+#ifndef REVISION_IS_A2
+#define REVISION_IS_A2 \
+ ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
+ (SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_2))
+#endif
+
+#ifndef REVISION_IS_B0
+#define REVISION_IS_B0 \
+ ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
+ (SYSCTL_DID0_MAJ_REVB | SYSCTL_DID0_MIN_0))
+#endif
+
+#ifndef REVISION_IS_B1
+#define REVISION_IS_B1 \
+ ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
+ (SYSCTL_DID0_MAJ_REVB | SYSCTL_DID0_MIN_1))
+#endif
+
+#ifndef REVISION_IS_C1
+#define REVISION_IS_C1 \
+ ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
+ (SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_1))
+#endif
+
+#ifndef REVISION_IS_C2
+#define REVISION_IS_C2 \
+ ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
+ (SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_2))
+#endif
+
+//*****************************************************************************
+//
+// Deprecated silicon class and revision detection macros.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+#define DEVICE_IS_SANDSTORM CLASS_IS_SANDSTORM
+#define DEVICE_IS_FURY CLASS_IS_FURY
+#define DEVICE_IS_REVA2 REVISION_IS_A2
+#define DEVICE_IS_REVC1 REVISION_IS_C1
+#define DEVICE_IS_REVC2 REVISION_IS_C2
+#endif
+
+#endif // __HW_TYPES_H__
Property changes on: branches/eagle_mmc/src/platform/lm3s/hw_types.h
___________________________________________________________________
Name: svn:executable
+ *
Modified: branches/eagle_mmc/src/platform/lm3s/hw_uart.h
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/hw_uart.h 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lm3s/hw_uart.h 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,340 +1,436 @@
-//*****************************************************************************
-//
-// hw_uart.h - Macros and defines used when accessing the UART hardware
-//
-// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
-// Software License Agreement
-//
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
-//
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws. All rights are reserved. You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program. Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
-//
-// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-//
-// This is part of revision 3740 of the Stellaris Firmware Development Package.
-//
-//*****************************************************************************
-
-#ifndef __HW_UART_H__
-#define __HW_UART_H__
-
-//*****************************************************************************
-//
-// The following are defines for the UART Register offsets.
-//
-//*****************************************************************************
-#define UART_O_DR 0x00000000 // Data Register
-#define UART_O_RSR 0x00000004 // Receive Status Register (read)
-#define UART_O_ECR 0x00000004 // Error Clear Register (write)
-#define UART_O_FR 0x00000018 // Flag Register (read only)
-#define UART_O_ILPR 0x00000020 // UART IrDA Low-Power Register
-#define UART_O_IBRD 0x00000024 // Integer Baud Rate Divisor Reg
-#define UART_O_FBRD 0x00000028 // Fractional Baud Rate Divisor Reg
-#define UART_O_LCRH 0x0000002C // UART Line Control
-#define UART_O_CTL 0x00000030 // Control Register
-#define UART_O_IFLS 0x00000034 // Interrupt FIFO Level Select Reg
-#define UART_O_IM 0x00000038 // Interrupt Mask Set/Clear Reg
-#define UART_O_RIS 0x0000003C // Raw Interrupt Status Register
-#define UART_O_MIS 0x00000040 // Masked Interrupt Status Register
-#define UART_O_ICR 0x00000044 // Interrupt Clear Register
-#define UART_O_DMACTL 0x00000048 // UART DMA Control
-
-//*****************************************************************************
-//
-// The following are defines for the Data Register bits
-//
-//*****************************************************************************
-#define UART_DR_OE 0x00000800 // Overrun Error
-#define UART_DR_BE 0x00000400 // Break Error
-#define UART_DR_PE 0x00000200 // Parity Error
-#define UART_DR_FE 0x00000100 // Framing Error
-#define UART_DR_DATA_M 0x000000FF // Data Transmitted or Received.
-#define UART_DR_DATA_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the Receive Status Register bits
-//
-//*****************************************************************************
-#define UART_RSR_OE 0x00000008 // Overrun Error
-#define UART_RSR_BE 0x00000004 // Break Error
-#define UART_RSR_PE 0x00000002 // Parity Error
-#define UART_RSR_FE 0x00000001 // Framing Error
-
-//*****************************************************************************
-//
-// The following are defines for the Flag Register bits
-//
-//*****************************************************************************
-#define UART_FR_TXFE 0x00000080 // TX FIFO Empty
-#define UART_FR_RXFF 0x00000040 // RX FIFO Full
-#define UART_FR_TXFF 0x00000020 // TX FIFO Full
-#define UART_FR_RXFE 0x00000010 // RX FIFO Empty
-#define UART_FR_BUSY 0x00000008 // UART Busy
-
-//*****************************************************************************
-//
-// The following are defines for the Integer baud-rate divisor
-//
-//*****************************************************************************
-#define UART_IBRD_DIVINT_M 0x0000FFFF // Integer Baud-Rate Divisor.
-#define UART_IBRD_DIVINT_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the Fractional baud-rate divisor
-//
-//*****************************************************************************
-#define UART_FBRD_DIVFRAC_M 0x0000003F // Fractional Baud-Rate Divisor.
-#define UART_FBRD_DIVFRAC_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the Control Register bits
-//
-//*****************************************************************************
-#define UART_CTL_RXE 0x00000200 // Receive Enable
-#define UART_CTL_TXE 0x00000100 // Transmit Enable
-#define UART_CTL_LBE 0x00000080 // Loopback Enable
-#define UART_CTL_SIRLP 0x00000004 // SIR (IrDA) Low Power Enable
-#define UART_CTL_SIREN 0x00000002 // SIR (IrDA) Enable
-#define UART_CTL_UARTEN 0x00000001 // UART Enable
-
-//*****************************************************************************
-//
-// The following are defines for the Interrupt FIFO Level Select Register bits
-//
-//*****************************************************************************
-#define UART_IFLS_RX_M 0x00000038 // RX FIFO Level Interrupt Mask
-#define UART_IFLS_RX1_8 0x00000000 // 1/8 Full
-#define UART_IFLS_RX2_8 0x00000008 // 1/4 Full
-#define UART_IFLS_RX4_8 0x00000010 // 1/2 Full
-#define UART_IFLS_RX6_8 0x00000018 // 3/4 Full
-#define UART_IFLS_RX7_8 0x00000020 // 7/8 Full
-#define UART_IFLS_TX_M 0x00000007 // TX FIFO Level Interrupt Mask
-#define UART_IFLS_TX1_8 0x00000000 // 1/8 Full
-#define UART_IFLS_TX2_8 0x00000001 // 1/4 Full
-#define UART_IFLS_TX4_8 0x00000002 // 1/2 Full
-#define UART_IFLS_TX6_8 0x00000003 // 3/4 Full
-#define UART_IFLS_TX7_8 0x00000004 // 7/8 Full
-
-//*****************************************************************************
-//
-// The following are defines for the Interrupt Mask Set/Clear Register bits
-//
-//*****************************************************************************
-#define UART_IM_OEIM 0x00000400 // Overrun Error Interrupt Mask
-#define UART_IM_BEIM 0x00000200 // Break Error Interrupt Mask
-#define UART_IM_PEIM 0x00000100 // Parity Error Interrupt Mask
-#define UART_IM_FEIM 0x00000080 // Framing Error Interrupt Mask
-#define UART_IM_RTIM 0x00000040 // Receive Timeout Interrupt Mask
-#define UART_IM_TXIM 0x00000020 // Transmit Interrupt Mask
-#define UART_IM_RXIM 0x00000010 // Receive Interrupt Mask
-
-//*****************************************************************************
-//
-// The following are defines for the Raw Interrupt Status Register
-//
-//*****************************************************************************
-#define UART_RIS_OERIS 0x00000400 // Overrun Error Interrupt Status
-#define UART_RIS_BERIS 0x00000200 // Break Error Interrupt Status
-#define UART_RIS_PERIS 0x00000100 // Parity Error Interrupt Status
-#define UART_RIS_FERIS 0x00000080 // Framing Error Interrupt Status
-#define UART_RIS_RTRIS 0x00000040 // Receive Timeout Interrupt Status
-#define UART_RIS_TXRIS 0x00000020 // Transmit Interrupt Status
-#define UART_RIS_RXRIS 0x00000010 // Receive Interrupt Status
-
-//*****************************************************************************
-//
-// The following are defines for the Masked Interrupt Status Register
-//
-//*****************************************************************************
-#define UART_MIS_OEMIS 0x00000400 // Overrun Error Interrupt Status
-#define UART_MIS_BEMIS 0x00000200 // Break Error Interrupt Status
-#define UART_MIS_PEMIS 0x00000100 // Parity Error Interrupt Status
-#define UART_MIS_FEMIS 0x00000080 // Framing Error Interrupt Status
-#define UART_MIS_RTMIS 0x00000040 // Receive Timeout Interrupt Status
-#define UART_MIS_TXMIS 0x00000020 // Transmit Interrupt Status
-#define UART_MIS_RXMIS 0x00000010 // Receive Interrupt Status
-
-//*****************************************************************************
-//
-// The following are defines for the Interrupt Clear Register bits
-//
-//*****************************************************************************
-#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear
-#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear
-#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear
-#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear
-#define UART_ICR_RTIC 0x00000040 // Receive Timeout Interrupt Clear
-#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear
-#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UART_O_ECR register.
-//
-//*****************************************************************************
-#define UART_ECR_DATA_M 0x000000FF // Error Clear.
-#define UART_ECR_DATA_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UART_O_LCRH register.
-//
-//*****************************************************************************
-#define UART_LCRH_SPS 0x00000080 // UART Stick Parity Select.
-#define UART_LCRH_WLEN_M 0x00000060 // UART Word Length.
-#define UART_LCRH_WLEN_5 0x00000000 // 5 bits (default)
-#define UART_LCRH_WLEN_6 0x00000020 // 6 bits
-#define UART_LCRH_WLEN_7 0x00000040 // 7 bits
-#define UART_LCRH_WLEN_8 0x00000060 // 8 bits
-#define UART_LCRH_FEN 0x00000010 // UART Enable FIFOs.
-#define UART_LCRH_STP2 0x00000008 // UART Two Stop Bits Select.
-#define UART_LCRH_EPS 0x00000004 // UART Even Parity Select.
-#define UART_LCRH_PEN 0x00000002 // UART Parity Enable.
-#define UART_LCRH_BRK 0x00000001 // UART Send Break.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UART_O_ILPR register.
-//
-//*****************************************************************************
-#define UART_ILPR_ILPDVSR_M 0x000000FF // IrDA Low-Power Divisor.
-#define UART_ILPR_ILPDVSR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UART_O_DMACTL register.
-//
-//*****************************************************************************
-#define UART_DMACTL_DMAERR 0x00000004 // DMA on Error.
-#define UART_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable.
-#define UART_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable.
-
-//*****************************************************************************
-//
-// The following definitions are deprecated.
-//
-//*****************************************************************************
-#ifndef DEPRECATED
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the UART Register offsets.
-//
-//*****************************************************************************
-#define UART_O_LCR_H 0x0000002C // Line Control Register, HIGH byte
-#define UART_O_PeriphID4 0x00000FD0
-#define UART_O_PeriphID5 0x00000FD4
-#define UART_O_PeriphID6 0x00000FD8
-#define UART_O_PeriphID7 0x00000FDC
-#define UART_O_PeriphID0 0x00000FE0
-#define UART_O_PeriphID1 0x00000FE4
-#define UART_O_PeriphID2 0x00000FE8
-#define UART_O_PeriphID3 0x00000FEC
-#define UART_O_PCellID0 0x00000FF0
-#define UART_O_PCellID1 0x00000FF4
-#define UART_O_PCellID2 0x00000FF8
-#define UART_O_PCellID3 0x00000FFC
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the Data Register bits
-//
-//*****************************************************************************
-#define UART_DR_DATA_MASK 0x000000FF // UART data
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the Integer baud-rate divisor
-//
-//*****************************************************************************
-#define UART_IBRD_DIVINT_MASK 0x0000FFFF // Integer baud-rate divisor
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the Fractional baud-rate divisor
-//
-//*****************************************************************************
-#define UART_FBRD_DIVFRAC_MASK 0x0000003F // Fractional baud-rate divisor
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the Line Control Register High bits
-//
-//*****************************************************************************
-#define UART_LCR_H_SPS 0x00000080 // Stick Parity Select
-#define UART_LCR_H_WLEN 0x00000060 // Word length
-#define UART_LCR_H_WLEN_5 0x00000000 // 5 bit data
-#define UART_LCR_H_WLEN_6 0x00000020 // 6 bit data
-#define UART_LCR_H_WLEN_7 0x00000040 // 7 bit data
-#define UART_LCR_H_WLEN_8 0x00000060 // 8 bit data
-#define UART_LCR_H_FEN 0x00000010 // Enable FIFO
-#define UART_LCR_H_STP2 0x00000008 // Two Stop Bits Select
-#define UART_LCR_H_EPS 0x00000004 // Even Parity Select
-#define UART_LCR_H_PEN 0x00000002 // Parity Enable
-#define UART_LCR_H_BRK 0x00000001 // Send Break
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the Interrupt FIFO Level Select
-// Register bits
-//
-//*****************************************************************************
-#define UART_IFLS_RX_MASK 0x00000038 // RX FIFO level mask
-#define UART_IFLS_TX_MASK 0x00000007 // TX FIFO level mask
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the Interrupt Clear Register bits
-//
-//*****************************************************************************
-#define UART_RSR_ANY (UART_RSR_OE | UART_RSR_BE | UART_RSR_PE | \
- UART_RSR_FE)
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the Reset Values for UART
-// Registers.
-//
-//*****************************************************************************
-#define UART_RV_CTL 0x00000300
-#define UART_RV_PCellID1 0x000000F0
-#define UART_RV_PCellID3 0x000000B1
-#define UART_RV_FR 0x00000090
-#define UART_RV_PeriphID2 0x00000018
-#define UART_RV_IFLS 0x00000012
-#define UART_RV_PeriphID0 0x00000011
-#define UART_RV_PCellID0 0x0000000D
-#define UART_RV_PCellID2 0x00000005
-#define UART_RV_PeriphID3 0x00000001
-#define UART_RV_PeriphID4 0x00000000
-#define UART_RV_LCR_H 0x00000000
-#define UART_RV_PeriphID6 0x00000000
-#define UART_RV_DR 0x00000000
-#define UART_RV_RSR 0x00000000
-#define UART_RV_ECR 0x00000000
-#define UART_RV_PeriphID5 0x00000000
-#define UART_RV_RIS 0x00000000
-#define UART_RV_FBRD 0x00000000
-#define UART_RV_IM 0x00000000
-#define UART_RV_MIS 0x00000000
-#define UART_RV_ICR 0x00000000
-#define UART_RV_PeriphID1 0x00000000
-#define UART_RV_PeriphID7 0x00000000
-#define UART_RV_IBRD 0x00000000
-
-#endif
-
-#endif // __HW_UART_H__
+//*****************************************************************************
+//
+// hw_uart.h - Macros and defines used when accessing the UART hardware
+//
+// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4781 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_UART_H__
+#define __HW_UART_H__
+
+//*****************************************************************************
+//
+// The following are defines for the UART Register offsets.
+//
+//*****************************************************************************
+#define UART_O_DR 0x00000000 // Data Register
+#define UART_O_RSR 0x00000004 // Receive Status Register (read)
+#define UART_O_ECR 0x00000004 // Error Clear Register (write)
+#define UART_O_FR 0x00000018 // Flag Register (read only)
+#define UART_O_ILPR 0x00000020 // UART IrDA Low-Power Register
+#define UART_O_IBRD 0x00000024 // Integer Baud Rate Divisor Reg
+#define UART_O_FBRD 0x00000028 // Fractional Baud Rate Divisor Reg
+#define UART_O_LCRH 0x0000002C // UART Line Control
+#define UART_O_CTL 0x00000030 // Control Register
+#define UART_O_IFLS 0x00000034 // Interrupt FIFO Level Select Reg
+#define UART_O_IM 0x00000038 // Interrupt Mask Set/Clear Reg
+#define UART_O_RIS 0x0000003C // Raw Interrupt Status Register
+#define UART_O_MIS 0x00000040 // Masked Interrupt Status Register
+#define UART_O_ICR 0x00000044 // Interrupt Clear Register
+#define UART_O_DMACTL 0x00000048 // UART DMA Control
+#define UART_O_LCTL 0x00000090 // UART LIN Control
+#define UART_O_LSS 0x00000094 // UART LIN Snap Shot
+#define UART_O_LTIM 0x00000098 // UART LIN Timer
+
+//*****************************************************************************
+//
+// The following are defines for the Data Register bits
+//
+//*****************************************************************************
+#define UART_DR_OE 0x00000800 // Overrun Error
+#define UART_DR_BE 0x00000400 // Break Error
+#define UART_DR_PE 0x00000200 // Parity Error
+#define UART_DR_FE 0x00000100 // Framing Error
+#define UART_DR_DATA_M 0x000000FF // Data Transmitted or Received.
+#define UART_DR_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the Receive Status Register bits
+//
+//*****************************************************************************
+#define UART_RSR_OE 0x00000008 // Overrun Error
+#define UART_RSR_BE 0x00000004 // Break Error
+#define UART_RSR_PE 0x00000002 // Parity Error
+#define UART_RSR_FE 0x00000001 // Framing Error
+
+//*****************************************************************************
+//
+// The following are defines for the Flag Register bits
+//
+//*****************************************************************************
+#define UART_FR_RI 0x00000100 // Ring Indicator.
+#define UART_FR_TXFE 0x00000080 // TX FIFO Empty
+#define UART_FR_RXFF 0x00000040 // RX FIFO Full
+#define UART_FR_TXFF 0x00000020 // TX FIFO Full
+#define UART_FR_RXFE 0x00000010 // RX FIFO Empty
+#define UART_FR_BUSY 0x00000008 // UART Busy
+#define UART_FR_DCD 0x00000004 // Data Carrier Detect.
+#define UART_FR_DSR 0x00000002 // Data Set Ready.
+#define UART_FR_CTS 0x00000001 // Clear To Send.
+
+//*****************************************************************************
+//
+// The following are defines for the Integer baud-rate divisor
+//
+//*****************************************************************************
+#define UART_IBRD_DIVINT_M 0x0000FFFF // Integer Baud-Rate Divisor.
+#define UART_IBRD_DIVINT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the Fractional baud-rate divisor
+//
+//*****************************************************************************
+#define UART_FBRD_DIVFRAC_M 0x0000003F // Fractional Baud-Rate Divisor.
+#define UART_FBRD_DIVFRAC_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the Control Register bits
+//
+//*****************************************************************************
+#define UART_CTL_CTSEN 0x00008000 // Enable Clear To Send.
+#define UART_CTL_RTSEN 0x00004000 // Enable Request to Send.
+#define UART_CTL_RTS 0x00000800 // Request to Send.
+#define UART_CTL_DTR 0x00000400 // Data Terminal Ready.
+#define UART_CTL_RXE 0x00000200 // Receive Enable
+#define UART_CTL_TXE 0x00000100 // Transmit Enable
+#define UART_CTL_LBE 0x00000080 // Loopback Enable
+#define UART_CTL_LIN 0x00000040 // LIN Mode Enable.
+#define UART_CTL_HSE 0x00000020 // High-Speed Enable.
+#define UART_CTL_EOT 0x00000010 // End of Transmission.
+#define UART_CTL_SMART 0x00000008 // ISO 7816 Smart Card Support.
+#define UART_CTL_SIRLP 0x00000004 // SIR (IrDA) Low Power Enable
+#define UART_CTL_SIREN 0x00000002 // SIR (IrDA) Enable
+#define UART_CTL_UARTEN 0x00000001 // UART Enable
+
+//*****************************************************************************
+//
+// The following are defines for the Interrupt FIFO Level Select Register bits
+//
+//*****************************************************************************
+#define UART_IFLS_RX_M 0x00000038 // RX FIFO Level Interrupt Mask
+#define UART_IFLS_RX1_8 0x00000000 // 1/8 Full
+#define UART_IFLS_RX2_8 0x00000008 // 1/4 Full
+#define UART_IFLS_RX4_8 0x00000010 // 1/2 Full
+#define UART_IFLS_RX6_8 0x00000018 // 3/4 Full
+#define UART_IFLS_RX7_8 0x00000020 // 7/8 Full
+#define UART_IFLS_TX_M 0x00000007 // TX FIFO Level Interrupt Mask
+#define UART_IFLS_TX1_8 0x00000000 // 1/8 Full
+#define UART_IFLS_TX2_8 0x00000001 // 1/4 Full
+#define UART_IFLS_TX4_8 0x00000002 // 1/2 Full
+#define UART_IFLS_TX6_8 0x00000003 // 3/4 Full
+#define UART_IFLS_TX7_8 0x00000004 // 7/8 Full
+
+//*****************************************************************************
+//
+// The following are defines for the Interrupt Mask Set/Clear Register bits
+//
+//*****************************************************************************
+#define UART_IM_LME5IM 0x00008000 // LIN Mode Edge 5 Interrupt Mask.
+#define UART_IM_LME1IM 0x00004000 // LIN Mode Edge 1 Interrupt Mask.
+#define UART_IM_LMSBIM 0x00002000 // LIN Mode Sync Break Interrupt
+ // Mask.
+#define UART_IM_OEIM 0x00000400 // Overrun Error Interrupt Mask
+#define UART_IM_BEIM 0x00000200 // Break Error Interrupt Mask
+#define UART_IM_PEIM 0x00000100 // Parity Error Interrupt Mask
+#define UART_IM_FEIM 0x00000080 // Framing Error Interrupt Mask
+#define UART_IM_RTIM 0x00000040 // Receive Timeout Interrupt Mask
+#define UART_IM_TXIM 0x00000020 // Transmit Interrupt Mask
+#define UART_IM_RXIM 0x00000010 // Receive Interrupt Mask
+#define UART_IM_DSRMIM 0x00000008 // UART Data Set Ready Modem
+ // Interrupt Mask.
+#define UART_IM_DCDMIM 0x00000004 // UART Data Carrier Detect Modem
+ // Interrupt Mask.
+#define UART_IM_CTSMIM 0x00000002 // UART Clear to Send Modem
+ // Interrupt Mask.
+#define UART_IM_RIMIM 0x00000001 // UART Ring Indicator Modem
+ // Interrupt Mask.
+
+//*****************************************************************************
+//
+// The following are defines for the Raw Interrupt Status Register
+//
+//*****************************************************************************
+#define UART_RIS_LME5RIS 0x00008000 // LIN Mode Edge 5 Raw Interrupt
+ // Status.
+#define UART_RIS_LME1RIS 0x00004000 // LIN Mode Edge 1 Raw Interrupt
+ // Status.
+#define UART_RIS_LMSBRIS 0x00002000 // LIN Mode Sync Break Raw
+ // Interrupt Status.
+#define UART_RIS_OERIS 0x00000400 // Overrun Error Interrupt Status
+#define UART_RIS_BERIS 0x00000200 // Break Error Interrupt Status
+#define UART_RIS_PERIS 0x00000100 // Parity Error Interrupt Status
+#define UART_RIS_FERIS 0x00000080 // Framing Error Interrupt Status
+#define UART_RIS_RTRIS 0x00000040 // Receive Timeout Interrupt Status
+#define UART_RIS_TXRIS 0x00000020 // Transmit Interrupt Status
+#define UART_RIS_RXRIS 0x00000010 // Receive Interrupt Status
+#define UART_RIS_DSRRIS 0x00000008 // UART Data Set Ready Modem Raw
+ // Interrupt Status.
+#define UART_RIS_DCDRIS 0x00000004 // UART Data Carrier Detect odem
+ // Raw Interrupt Status.
+#define UART_RIS_CTSRIS 0x00000002 // UART Clear to Send Modem Raw
+ // Interrupt Status.
+#define UART_RIS_RIRIS 0x00000001 // UART Ring Indicator Modem Raw
+ // Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the Masked Interrupt Status Register
+//
+//*****************************************************************************
+#define UART_MIS_LME5MIS 0x00008000 // LIN Mode Edge 5 Masked Interrupt
+ // Status.
+#define UART_MIS_LME1MIS 0x00004000 // LIN Mode Edge 1 Masked Interrupt
+ // Status.
+#define UART_MIS_LMSBMIS 0x00002000 // LIN Mode Sync Break Masked
+ // Interrupt Status.
+#define UART_MIS_OEMIS 0x00000400 // Overrun Error Interrupt Status
+#define UART_MIS_BEMIS 0x00000200 // Break Error Interrupt Status
+#define UART_MIS_PEMIS 0x00000100 // Parity Error Interrupt Status
+#define UART_MIS_FEMIS 0x00000080 // Framing Error Interrupt Status
+#define UART_MIS_RTMIS 0x00000040 // Receive Timeout Interrupt Status
+#define UART_MIS_TXMIS 0x00000020 // Transmit Interrupt Status
+#define UART_MIS_RXMIS 0x00000010 // Receive Interrupt Status
+#define UART_MIS_DSRMIS 0x00000008 // UART Data Set Ready Modem Masked
+ // Interrupt Status.
+#define UART_MIS_DCDMIS 0x00000004 // UART Data Carrier Detect odem
+ // Masked Interrupt Status.
+#define UART_MIS_CTSMIS 0x00000002 // UART Clear to Send Modem Masked
+ // Interrupt Status.
+#define UART_MIS_RIMIS 0x00000001 // UART Ring Indicator Modem Masked
+ // Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the Interrupt Clear Register bits
+//
+//*****************************************************************************
+#define UART_ICR_LME5MIC 0x00008000 // LIN Mode Edge 5 Interrupt Clear.
+#define UART_ICR_LME1MIC 0x00004000 // LIN Mode Edge 1 Interrupt Clear.
+#define UART_ICR_LMSBMIC 0x00002000 // LIN Mode Sync Break Interrupt
+ // Clear.
+#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear
+#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear
+#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear
+#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear
+#define UART_ICR_RTIC 0x00000040 // Receive Timeout Interrupt Clear
+#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear
+#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear
+#define UART_ICR_DSRMIC 0x00000008 // UART Data Set Ready Modem
+ // Interrupt Clear.
+#define UART_ICR_DCDMIC 0x00000004 // UART Data Carrier Detect odem
+ // Interrupt Clear.
+#define UART_ICR_CTSMIC 0x00000002 // UART Clear to Send Modem
+ // Interrupt Clear.
+#define UART_ICR_RIMIC 0x00000001 // UART Ring Indicator Modem
+ // Interrupt Clear.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_ECR register.
+//
+//*****************************************************************************
+#define UART_ECR_DATA_M 0x000000FF // Error Clear.
+#define UART_ECR_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_LCRH register.
+//
+//*****************************************************************************
+#define UART_LCRH_SPS 0x00000080 // UART Stick Parity Select.
+#define UART_LCRH_WLEN_M 0x00000060 // UART Word Length.
+#define UART_LCRH_WLEN_5 0x00000000 // 5 bits (default)
+#define UART_LCRH_WLEN_6 0x00000020 // 6 bits
+#define UART_LCRH_WLEN_7 0x00000040 // 7 bits
+#define UART_LCRH_WLEN_8 0x00000060 // 8 bits
+#define UART_LCRH_FEN 0x00000010 // UART Enable FIFOs.
+#define UART_LCRH_STP2 0x00000008 // UART Two Stop Bits Select.
+#define UART_LCRH_EPS 0x00000004 // UART Even Parity Select.
+#define UART_LCRH_PEN 0x00000002 // UART Parity Enable.
+#define UART_LCRH_BRK 0x00000001 // UART Send Break.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_ILPR register.
+//
+//*****************************************************************************
+#define UART_ILPR_ILPDVSR_M 0x000000FF // IrDA Low-Power Divisor.
+#define UART_ILPR_ILPDVSR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_DMACTL register.
+//
+//*****************************************************************************
+#define UART_DMACTL_DMAERR 0x00000004 // DMA on Error.
+#define UART_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable.
+#define UART_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_LCTL register.
+//
+//*****************************************************************************
+#define UART_LCTL_BLEN_M 0x00000030 // Sync Break Length.
+#define UART_LCTL_BLEN_13T 0x00000000 // Sync break length is 13T bits
+ // (default)
+#define UART_LCTL_BLEN_14T 0x00000010 // Sync break length is 14T bits
+#define UART_LCTL_BLEN_15T 0x00000020 // Sync break length is 15T bits
+#define UART_LCTL_BLEN_16T 0x00000030 // Sync break length is 16T bits
+#define UART_LCTL_MASTER 0x00000001 // LIN Master Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_LSS register.
+//
+//*****************************************************************************
+#define UART_LSS_TSS_M 0x0000FFFF // Timer Snap Shot.
+#define UART_LSS_TSS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_LTIM register.
+//
+//*****************************************************************************
+#define UART_LTIM_TIMER_M 0x0000FFFF // Timer Value.
+#define UART_LTIM_TIMER_S 0
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the UART Register offsets.
+//
+//*****************************************************************************
+#define UART_O_LCR_H 0x0000002C // Line Control Register, HIGH byte
+#define UART_O_PeriphID4 0x00000FD0
+#define UART_O_PeriphID5 0x00000FD4
+#define UART_O_PeriphID6 0x00000FD8
+#define UART_O_PeriphID7 0x00000FDC
+#define UART_O_PeriphID0 0x00000FE0
+#define UART_O_PeriphID1 0x00000FE4
+#define UART_O_PeriphID2 0x00000FE8
+#define UART_O_PeriphID3 0x00000FEC
+#define UART_O_PCellID0 0x00000FF0
+#define UART_O_PCellID1 0x00000FF4
+#define UART_O_PCellID2 0x00000FF8
+#define UART_O_PCellID3 0x00000FFC
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the Data Register bits
+//
+//*****************************************************************************
+#define UART_DR_DATA_MASK 0x000000FF // UART data
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the Integer baud-rate divisor
+//
+//*****************************************************************************
+#define UART_IBRD_DIVINT_MASK 0x0000FFFF // Integer baud-rate divisor
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the Fractional baud-rate divisor
+//
+//*****************************************************************************
+#define UART_FBRD_DIVFRAC_MASK 0x0000003F // Fractional baud-rate divisor
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the Line Control Register High bits
+//
+//*****************************************************************************
+#define UART_LCR_H_SPS 0x00000080 // Stick Parity Select
+#define UART_LCR_H_WLEN 0x00000060 // Word length
+#define UART_LCR_H_WLEN_5 0x00000000 // 5 bit data
+#define UART_LCR_H_WLEN_6 0x00000020 // 6 bit data
+#define UART_LCR_H_WLEN_7 0x00000040 // 7 bit data
+#define UART_LCR_H_WLEN_8 0x00000060 // 8 bit data
+#define UART_LCR_H_FEN 0x00000010 // Enable FIFO
+#define UART_LCR_H_STP2 0x00000008 // Two Stop Bits Select
+#define UART_LCR_H_EPS 0x00000004 // Even Parity Select
+#define UART_LCR_H_PEN 0x00000002 // Parity Enable
+#define UART_LCR_H_BRK 0x00000001 // Send Break
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the Interrupt FIFO Level Select
+// Register bits
+//
+//*****************************************************************************
+#define UART_IFLS_RX_MASK 0x00000038 // RX FIFO level mask
+#define UART_IFLS_TX_MASK 0x00000007 // TX FIFO level mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the Interrupt Clear Register bits
+//
+//*****************************************************************************
+#define UART_RSR_ANY (UART_RSR_OE | UART_RSR_BE | UART_RSR_PE | \
+ UART_RSR_FE)
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the Reset Values for UART
+// Registers.
+//
+//*****************************************************************************
+#define UART_RV_CTL 0x00000300
+#define UART_RV_PCellID1 0x000000F0
+#define UART_RV_PCellID3 0x000000B1
+#define UART_RV_FR 0x00000090
+#define UART_RV_PeriphID2 0x00000018
+#define UART_RV_IFLS 0x00000012
+#define UART_RV_PeriphID0 0x00000011
+#define UART_RV_PCellID0 0x0000000D
+#define UART_RV_PCellID2 0x00000005
+#define UART_RV_PeriphID3 0x00000001
+#define UART_RV_PeriphID4 0x00000000
+#define UART_RV_LCR_H 0x00000000
+#define UART_RV_PeriphID6 0x00000000
+#define UART_RV_DR 0x00000000
+#define UART_RV_RSR 0x00000000
+#define UART_RV_ECR 0x00000000
+#define UART_RV_PeriphID5 0x00000000
+#define UART_RV_RIS 0x00000000
+#define UART_RV_FBRD 0x00000000
+#define UART_RV_IM 0x00000000
+#define UART_RV_MIS 0x00000000
+#define UART_RV_ICR 0x00000000
+#define UART_RV_PeriphID1 0x00000000
+#define UART_RV_PeriphID7 0x00000000
+#define UART_RV_IBRD 0x00000000
+
+#endif
+
+#endif // __HW_UART_H__
Property changes on: branches/eagle_mmc/src/platform/lm3s/hw_uart.h
___________________________________________________________________
Name: svn:executable
+ *
Added: branches/eagle_mmc/src/platform/lm3s/hw_udma.h
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/hw_udma.h 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lm3s/hw_udma.h 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,320 @@
+//*****************************************************************************
+//
+// hw_udma.h - Macros for use in accessing the UDMA registers.
+//
+// Copyright (c) 2007-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4781 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_UDMA_H__
+#define __HW_UDMA_H__
+
+//*****************************************************************************
+//
+// The following are defines for the Micro Direct Memory Access (uDMA) offsets.
+//
+//*****************************************************************************
+#define UDMA_STAT 0x400FF000 // DMA Status
+#define UDMA_CFG 0x400FF004 // DMA Configuration
+#define UDMA_CTLBASE 0x400FF008 // DMA Channel Control Base Pointer
+#define UDMA_ALTBASE 0x400FF00C // DMA Alternate Channel Control
+ // Base Pointer
+#define UDMA_WAITSTAT 0x400FF010 // DMA Channel Wait on Request
+ // Status
+#define UDMA_SWREQ 0x400FF014 // DMA Channel Software Request
+#define UDMA_USEBURSTSET 0x400FF018 // DMA Channel Useburst Set
+#define UDMA_USEBURSTCLR 0x400FF01C // DMA Channel Useburst Clear
+#define UDMA_REQMASKSET 0x400FF020 // DMA Channel Request Mask Set
+#define UDMA_REQMASKCLR 0x400FF024 // DMA Channel Request Mask Clear
+#define UDMA_ENASET 0x400FF028 // DMA Channel Enable Set
+#define UDMA_ENACLR 0x400FF02C // DMA Channel Enable Clear
+#define UDMA_ALTSET 0x400FF030 // DMA Channel Primary Alternate
+ // Set
+#define UDMA_ALTCLR 0x400FF034 // DMA Channel Primary Alternate
+ // Clear
+#define UDMA_PRIOSET 0x400FF038 // DMA Channel Priority Set
+#define UDMA_PRIOCLR 0x400FF03C // DMA Channel Priority Clear
+#define UDMA_ERRCLR 0x400FF04C // DMA Bus Error Clear
+#define UDMA_CHALT 0x400FF500 // DMA Channel Alternate Select
+#define UDMA_CHIS 0x400FF504 // DMA Channel Interrupt Status
+
+//*****************************************************************************
+//
+// Micro Direct Memory Access (uDMA) offsets.
+//
+//*****************************************************************************
+#define UDMA_O_SRCENDP 0x00000000 // DMA Channel Source Address End
+ // Pointer
+#define UDMA_O_DSTENDP 0x00000004 // DMA Channel Destination Address
+ // End Pointer
+#define UDMA_O_CHCTL 0x00000008 // DMA Channel Control Word
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_SRCENDP register.
+//
+//*****************************************************************************
+#define UDMA_SRCENDP_ADDR_M 0xFFFFFFFF // Source Address End Pointer.
+#define UDMA_SRCENDP_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_STAT register.
+//
+//*****************************************************************************
+#define UDMA_STAT_DMACHANS_M 0x001F0000 // Available DMA Channels Minus 1.
+#define UDMA_STAT_STATE_M 0x000000F0 // Control State Machine State.
+#define UDMA_STAT_STATE_IDLE 0x00000000 // Idle
+#define UDMA_STAT_STATE_RD_CTRL 0x00000010 // Reading channel controller data
+#define UDMA_STAT_STATE_RD_SRCENDP \
+ 0x00000020 // Reading source end pointer
+#define UDMA_STAT_STATE_RD_DSTENDP \
+ 0x00000030 // Reading destination end pointer
+#define UDMA_STAT_STATE_RD_SRCDAT \
+ 0x00000040 // Reading source data
+#define UDMA_STAT_STATE_WR_DSTDAT \
+ 0x00000050 // Writing destination data
+#define UDMA_STAT_STATE_WAIT 0x00000060 // Waiting for DMA request to clear
+#define UDMA_STAT_STATE_WR_CTRL 0x00000070 // Writing channel controller data
+#define UDMA_STAT_STATE_STALL 0x00000080 // Stalled
+#define UDMA_STAT_STATE_DONE 0x00000090 // Done
+#define UDMA_STAT_STATE_UNDEF 0x000000A0 // Undefined
+#define UDMA_STAT_MASTEN 0x00000001 // Master Enable.
+#define UDMA_STAT_DMACHANS_S 16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_DSTENDP register.
+//
+//*****************************************************************************
+#define UDMA_DSTENDP_ADDR_M 0xFFFFFFFF // Destination Address End Pointer.
+#define UDMA_DSTENDP_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CFG register.
+//
+//*****************************************************************************
+#define UDMA_CFG_MASTEN 0x00000001 // Controller Master Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CTLBASE register.
+//
+//*****************************************************************************
+#define UDMA_CTLBASE_ADDR_M 0xFFFFFC00 // Channel Control Base Address.
+#define UDMA_CTLBASE_ADDR_S 10
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_CHCTL register.
+//
+//*****************************************************************************
+#define UDMA_CHCTL_DSTINC_M 0xC0000000 // Destination Address Increment.
+#define UDMA_CHCTL_DSTINC_8 0x00000000 // Byte
+#define UDMA_CHCTL_DSTINC_16 0x40000000 // Half-word
+#define UDMA_CHCTL_DSTINC_32 0x80000000 // Word
+#define UDMA_CHCTL_DSTINC_NONE 0xC0000000 // No increment
+#define UDMA_CHCTL_DSTSIZE_M 0x30000000 // Destination Data Size.
+#define UDMA_CHCTL_DSTSIZE_8 0x00000000 // Byte
+#define UDMA_CHCTL_DSTSIZE_16 0x10000000 // Half-word
+#define UDMA_CHCTL_DSTSIZE_32 0x20000000 // Word
+#define UDMA_CHCTL_SRCINC_M 0x0C000000 // Source Address Increment.
+#define UDMA_CHCTL_SRCINC_8 0x00000000 // Byte
+#define UDMA_CHCTL_SRCINC_16 0x04000000 // Half-word
+#define UDMA_CHCTL_SRCINC_32 0x08000000 // Word
+#define UDMA_CHCTL_SRCINC_NONE 0x0C000000 // No increment
+#define UDMA_CHCTL_SRCSIZE_M 0x03000000 // Source Data Size.
+#define UDMA_CHCTL_SRCSIZE_8 0x00000000 // Byte
+#define UDMA_CHCTL_SRCSIZE_16 0x01000000 // Half-word
+#define UDMA_CHCTL_SRCSIZE_32 0x02000000 // Word
+#define UDMA_CHCTL_ARBSIZE_M 0x0003C000 // Arbitration Size.
+#define UDMA_CHCTL_ARBSIZE_1 0x00000000 // 1 Transfer
+#define UDMA_CHCTL_ARBSIZE_2 0x00004000 // 2 Transfers
+#define UDMA_CHCTL_ARBSIZE_4 0x00008000 // 4 Transfers
+#define UDMA_CHCTL_ARBSIZE_8 0x0000C000 // 8 Transfers
+#define UDMA_CHCTL_ARBSIZE_16 0x00010000 // 16 Transfers
+#define UDMA_CHCTL_ARBSIZE_32 0x00014000 // 32 Transfers
+#define UDMA_CHCTL_ARBSIZE_64 0x00018000 // 64 Transfers
+#define UDMA_CHCTL_ARBSIZE_128 0x0001C000 // 128 Transfers
+#define UDMA_CHCTL_ARBSIZE_256 0x00020000 // 256 Transfers
+#define UDMA_CHCTL_ARBSIZE_512 0x00024000 // 512 Transfers
+#define UDMA_CHCTL_ARBSIZE_1024 0x00028000 // 1024 Transfers
+#define UDMA_CHCTL_XFERSIZE_M 0x00003FF0 // Transfer Size (minus 1).
+#define UDMA_CHCTL_NXTUSEBURST 0x00000008 // Next Useburst.
+#define UDMA_CHCTL_XFERMODE_M 0x00000007 // DMA Transfer Mode.
+#define UDMA_CHCTL_XFERMODE_STOP \
+ 0x00000000 // Stop
+#define UDMA_CHCTL_XFERMODE_BASIC \
+ 0x00000001 // Basic
+#define UDMA_CHCTL_XFERMODE_AUTO \
+ 0x00000002 // Auto-Request
+#define UDMA_CHCTL_XFERMODE_PINGPONG \
+ 0x00000003 // Ping-Pong
+#define UDMA_CHCTL_XFERMODE_MEM_SG \
+ 0x00000004 // Memory Scatter-Gather
+#define UDMA_CHCTL_XFERMODE_MEM_SGA \
+ 0x00000005 // Alternate Memory Scatter-Gather
+#define UDMA_CHCTL_XFERMODE_PER_SG \
+ 0x00000006 // Peripheral Scatter-Gather
+#define UDMA_CHCTL_XFERMODE_PER_SGA \
+ 0x00000007 // Alternate Peripheral
+ // Scatter-Gather
+#define UDMA_CHCTL_XFERSIZE_S 4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ALTBASE register.
+//
+//*****************************************************************************
+#define UDMA_ALTBASE_ADDR_M 0xFFFFFFFF // Alternate Channel Address
+ // Pointer.
+#define UDMA_ALTBASE_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_WAITSTAT register.
+//
+//*****************************************************************************
+#define UDMA_WAITSTAT_WAITREQ_M 0xFFFFFFFF // Channel [n] Wait Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_SWREQ register.
+//
+//*****************************************************************************
+#define UDMA_SWREQ_M 0xFFFFFFFF // Channel [n] Software Request.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_USEBURSTSET
+// register.
+//
+//*****************************************************************************
+#define UDMA_USEBURSTSET_SET_M 0xFFFFFFFF // Channel [n] Useburst Set.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_USEBURSTCLR
+// register.
+//
+//*****************************************************************************
+#define UDMA_USEBURSTCLR_CLR_M 0xFFFFFFFF // Channel [n] Useburst Clear.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_REQMASKSET
+// register.
+//
+//*****************************************************************************
+#define UDMA_REQMASKSET_SET_M 0xFFFFFFFF // Channel [n] Request Mask Set.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_REQMASKCLR
+// register.
+//
+//*****************************************************************************
+#define UDMA_REQMASKCLR_CLR_M 0xFFFFFFFF // Channel [n] Request Mask Clear.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ENASET register.
+//
+//*****************************************************************************
+#define UDMA_ENASET_SET_M 0xFFFFFFFF // Channel [n] Enable Set.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ENACLR register.
+//
+//*****************************************************************************
+#define UDMA_ENACLR_CLR_M 0xFFFFFFFF // Clear Channel [n] Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ALTSET register.
+//
+//*****************************************************************************
+#define UDMA_ALTSET_SET_M 0xFFFFFFFF // Channel [n] Alternate Set.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ALTCLR register.
+//
+//*****************************************************************************
+#define UDMA_ALTCLR_CLR_M 0xFFFFFFFF // Channel [n] Alternate Clear.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_PRIOSET register.
+//
+//*****************************************************************************
+#define UDMA_PRIOSET_SET_M 0xFFFFFFFF // Channel [n] Priority Set.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_PRIOCLR register.
+//
+//*****************************************************************************
+#define UDMA_PRIOCLR_CLR_M 0xFFFFFFFF // Channel [n] Priority Clear.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ERRCLR register.
+//
+//*****************************************************************************
+#define UDMA_ERRCLR_ERRCLR 0x00000001 // DMA Bus Error Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CHALT register.
+//
+//*****************************************************************************
+#define UDMA_CHALT_M 0xFFFFFFFF // Channel [n] Alternate Assignment
+ // Select.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CHIS register.
+//
+//*****************************************************************************
+#define UDMA_CHIS_M 0xFFFFFFFF // Channel [n] Interrupt Status.
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the UDMA_ENASET
+// register.
+//
+//*****************************************************************************
+#define UDMA_ENASET_CHENSET_M 0xFFFFFFFF // Channel [n] Enable Set.
+
+#endif
+
+#endif // __HW_UDMA_H__
Property changes on: branches/eagle_mmc/src/platform/lm3s/hw_udma.h
___________________________________________________________________
Name: svn:executable
+ *
Added: branches/eagle_mmc/src/platform/lm3s/hw_usb.h
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/hw_usb.h 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lm3s/hw_usb.h 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,4638 @@
+//*****************************************************************************
+//
+// hw_usb.h - Macros for use in accessing the USB registers.
+//
+// Copyright (c) 2007-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4781 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_USB_H__
+#define __HW_USB_H__
+
+//*****************************************************************************
+//
+// The following are defines for the Univeral Serial Bus (USB) Controller
+// offsets.
+//
+//*****************************************************************************
+#define USB_O_FADDR 0x00000000 // USB Device Functional Address
+#define USB_O_POWER 0x00000001 // USB Power
+#define USB_O_TXIS 0x00000002 // USB Transmit Interrupt Status
+#define USB_O_RXIS 0x00000004 // USB Receive Interrupt Status
+#define USB_O_TXIE 0x00000006 // USB Transmit Interrupt Enable
+#define USB_O_RXIE 0x00000008 // USB Receive Interrupt Enable
+#define USB_O_IS 0x0000000A // USB General Interrupt Status
+#define USB_O_IE 0x0000000B // USB Interrupt Enable
+#define USB_O_FRAME 0x0000000C // USB Frame Value
+#define USB_O_EPIDX 0x0000000E // USB Endpoint Index
+#define USB_O_TEST 0x0000000F // USB Test Mode
+#define USB_O_FIFO0 0x00000020 // USB FIFO Endpoint 0
+#define USB_O_FIFO1 0x00000024 // USB FIFO Endpoint 1
+#define USB_O_FIFO2 0x00000028 // USB FIFO Endpoint 2
+#define USB_O_FIFO3 0x0000002C // USB FIFO Endpoint 3
+#define USB_O_FIFO4 0x00000030 // USB FIFO Endpoint 4
+#define USB_O_FIFO5 0x00000034 // USB FIFO Endpoint 5
+#define USB_O_FIFO6 0x00000038 // USB FIFO Endpoint 6
+#define USB_O_FIFO7 0x0000003C // USB FIFO Endpoint 7
+#define USB_O_FIFO8 0x00000040 // USB FIFO Endpoint 8
+#define USB_O_FIFO9 0x00000044 // USB FIFO Endpoint 9
+#define USB_O_FIFO10 0x00000048 // USB FIFO Endpoint 10
+#define USB_O_FIFO11 0x0000004C // USB FIFO Endpoint 11
+#define USB_O_FIFO12 0x00000050 // USB FIFO Endpoint 12
+#define USB_O_FIFO13 0x00000054 // USB FIFO Endpoint 13
+#define USB_O_FIFO14 0x00000058 // USB FIFO Endpoint 14
+#define USB_O_FIFO15 0x0000005C // USB FIFO Endpoint 15
+#define USB_O_DEVCTL 0x00000060 // USB Device Control
+#define USB_O_TXFIFOSZ 0x00000062 // USB Transmit Dynamic FIFO Sizing
+#define USB_O_RXFIFOSZ 0x00000063 // USB Receive Dynamic FIFO Sizing
+#define USB_O_TXFIFOADD 0x00000064 // USB Transmit FIFO Start Address
+#define USB_O_RXFIFOADD 0x00000066 // USB Receive FIFO Start Address
+#define USB_O_CONTIM 0x0000007A // USB Connect Timing
+#define USB_O_VPLEN 0x0000007B // USB OTG VBus Pulse Timing
+#define USB_O_FSEOF 0x0000007D // USB Full-Speed Last Transaction
+ // to End of Frame Timing
+#define USB_O_LSEOF 0x0000007E // USB Low-Speed Last Transaction
+ // to End of Frame Timing
+#define USB_O_TXFUNCADDR0 0x00000080 // USB Transmit Functional Address
+ // Endpoint 0
+#define USB_O_TXHUBADDR0 0x00000082 // USB Transmit Hub Address
+ // Endpoint 0
+#define USB_O_TXHUBPORT0 0x00000083 // USB Transmit Hub Port Endpoint 0
+#define USB_O_TXFUNCADDR1 0x00000088 // USB Transmit Functional Address
+ // Endpoint 1
+#define USB_O_TXHUBADDR1 0x0000008A // USB Transmit Hub Address
+ // Endpoint 1
+#define USB_O_TXHUBPORT1 0x0000008B // USB Transmit Hub Port Endpoint 1
+#define USB_O_RXFUNCADDR1 0x0000008C // USB Receive Functional Address
+ // Endpoint 1
+#define USB_O_RXHUBADDR1 0x0000008E // USB Receive Hub Address Endpoint
+ // 1
+#define USB_O_RXHUBPORT1 0x0000008F // USB Receive Hub Port Endpoint 1
+#define USB_O_TXFUNCADDR2 0x00000090 // USB Transmit Functional Address
+ // Endpoint 2
+#define USB_O_TXHUBADDR2 0x00000092 // USB Transmit Hub Address
+ // Endpoint 2
+#define USB_O_TXHUBPORT2 0x00000093 // USB Transmit Hub Port Endpoint 2
+#define USB_O_RXFUNCADDR2 0x00000094 // USB Receive Functional Address
+ // Endpoint 2
+#define USB_O_RXHUBADDR2 0x00000096 // USB Receive Hub Address Endpoint
+ // 2
+#define USB_O_RXHUBPORT2 0x00000097 // USB Receive Hub Port Endpoint 2
+#define USB_O_TXFUNCADDR3 0x00000098 // USB Transmit Functional Address
+ // Endpoint 3
+#define USB_O_TXHUBADDR3 0x0000009A // USB Transmit Hub Address
+ // Endpoint 3
+#define USB_O_TXHUBPORT3 0x0000009B // USB Transmit Hub Port Endpoint 3
+#define USB_O_RXFUNCADDR3 0x0000009C // USB Receive Functional Address
+ // Endpoint 3
+#define USB_O_RXHUBADDR3 0x0000009E // USB Receive Hub Address Endpoint
+ // 3
+#define USB_O_RXHUBPORT3 0x0000009F // USB Receive Hub Port Endpoint 3
+#define USB_O_TXFUNCADDR4 0x000000A0 // USB Transmit Functional Address
+ // Endpoint 4
+#define USB_O_TXHUBADDR4 0x000000A2 // USB Transmit Hub Address
+ // Endpoint 4
+#define USB_O_TXHUBPORT4 0x000000A3 // USB Transmit Hub Port Endpoint 4
+#define USB_O_RXFUNCADDR4 0x000000A4 // USB Receive Functional Address
+ // Endpoint 4
+#define USB_O_RXHUBADDR4 0x000000A6 // USB Receive Hub Address Endpoint
+ // 4
+#define USB_O_RXHUBPORT4 0x000000A7 // USB Receive Hub Port Endpoint 4
+#define USB_O_TXFUNCADDR5 0x000000A8 // USB Transmit Functional Address
+ // Endpoint 5
+#define USB_O_TXHUBADDR5 0x000000AA // USB Transmit Hub Address
+ // Endpoint 5
+#define USB_O_TXHUBPORT5 0x000000AB // USB Transmit Hub Port Endpoint 5
+#define USB_O_RXFUNCADDR5 0x000000AC // USB Receive Functional Address
+ // Endpoint 5
+#define USB_O_RXHUBADDR5 0x000000AE // USB Receive Hub Address Endpoint
+ // 5
+#define USB_O_RXHUBPORT5 0x000000AF // USB Receive Hub Port Endpoint 5
+#define USB_O_TXFUNCADDR6 0x000000B0 // USB Transmit Functional Address
+ // Endpoint 6
+#define USB_O_TXHUBADDR6 0x000000B2 // USB Transmit Hub Address
+ // Endpoint 6
+#define USB_O_TXHUBPORT6 0x000000B3 // USB Transmit Hub Port Endpoint 6
+#define USB_O_RXFUNCADDR6 0x000000B4 // USB Receive Functional Address
+ // Endpoint 6
+#define USB_O_RXHUBADDR6 0x000000B6 // USB Receive Hub Address Endpoint
+ // 6
+#define USB_O_RXHUBPORT6 0x000000B7 // USB Receive Hub Port Endpoint 6
+#define USB_O_TXFUNCADDR7 0x000000B8 // USB Transmit Functional Address
+ // Endpoint 7
+#define USB_O_TXHUBADDR7 0x000000BA // USB Transmit Hub Address
+ // Endpoint 7
+#define USB_O_TXHUBPORT7 0x000000BB // USB Transmit Hub Port Endpoint 7
+#define USB_O_RXFUNCADDR7 0x000000BC // USB Receive Functional Address
+ // Endpoint 7
+#define USB_O_RXHUBADDR7 0x000000BE // USB Receive Hub Address Endpoint
+ // 7
+#define USB_O_RXHUBPORT7 0x000000BF // USB Receive Hub Port Endpoint 7
+#define USB_O_TXFUNCADDR8 0x000000C0 // USB Transmit Functional Address
+ // Endpoint 8
+#define USB_O_TXHUBADDR8 0x000000C2 // USB Transmit Hub Address
+ // Endpoint 8
+#define USB_O_TXHUBPORT8 0x000000C3 // USB Transmit Hub Port Endpoint 8
+#define USB_O_RXFUNCADDR8 0x000000C4 // USB Receive Functional Address
+ // Endpoint 8
+#define USB_O_RXHUBADDR8 0x000000C6 // USB Receive Hub Address Endpoint
+ // 8
+#define USB_O_RXHUBPORT8 0x000000C7 // USB Receive Hub Port Endpoint 8
+#define USB_O_TXFUNCADDR9 0x000000C8 // USB Transmit Functional Address
+ // Endpoint 9
+#define USB_O_TXHUBADDR9 0x000000CA // USB Transmit Hub Address
+ // Endpoint 9
+#define USB_O_TXHUBPORT9 0x000000CB // USB Transmit Hub Port Endpoint 9
+#define USB_O_RXFUNCADDR9 0x000000CC // USB Receive Functional Address
+ // Endpoint 9
+#define USB_O_RXHUBADDR9 0x000000CE // USB Receive Hub Address Endpoint
+ // 9
+#define USB_O_RXHUBPORT9 0x000000CF // USB Receive Hub Port Endpoint 9
+#define USB_O_TXFUNCADDR10 0x000000D0 // USB Transmit Functional Address
+ // Endpoint 10
+#define USB_O_TXHUBADDR10 0x000000D2 // USB Transmit Hub Address
+ // Endpoint 10
+#define USB_O_TXHUBPORT10 0x000000D3 // USB Transmit Hub Port Endpoint
+ // 10
+#define USB_O_RXFUNCADDR10 0x000000D4 // USB Receive Functional Address
+ // Endpoint 10
+#define USB_O_RXHUBADDR10 0x000000D6 // USB Receive Hub Address Endpoint
+ // 10
+#define USB_O_RXHUBPORT10 0x000000D7 // USB Receive Hub Port Endpoint 10
+#define USB_O_TXFUNCADDR11 0x000000D8 // USB Transmit Functional Address
+ // Endpoint 11
+#define USB_O_TXHUBADDR11 0x000000DA // USB Transmit Hub Address
+ // Endpoint 11
+#define USB_O_TXHUBPORT11 0x000000DB // USB Transmit Hub Port Endpoint
+ // 11
+#define USB_O_RXFUNCADDR11 0x000000DC // USB Receive Functional Address
+ // Endpoint 11
+#define USB_O_RXHUBADDR11 0x000000DE // USB Receive Hub Address Endpoint
+ // 11
+#define USB_O_RXHUBPORT11 0x000000DF // USB Receive Hub Port Endpoint 11
+#define USB_O_TXFUNCADDR12 0x000000E0 // USB Transmit Functional Address
+ // Endpoint 12
+#define USB_O_TXHUBADDR12 0x000000E2 // USB Transmit Hub Address
+ // Endpoint 12
+#define USB_O_TXHUBPORT12 0x000000E3 // USB Transmit Hub Port Endpoint
+ // 12
+#define USB_O_RXFUNCADDR12 0x000000E4 // USB Receive Functional Address
+ // Endpoint 12
+#define USB_O_RXHUBADDR12 0x000000E6 // USB Receive Hub Address Endpoint
+ // 12
+#define USB_O_RXHUBPORT12 0x000000E7 // USB Receive Hub Port Endpoint 12
+#define USB_O_TXFUNCADDR13 0x000000E8 // USB Transmit Functional Address
+ // Endpoint 13
+#define USB_O_TXHUBADDR13 0x000000EA // USB Transmit Hub Address
+ // Endpoint 13
+#define USB_O_TXHUBPORT13 0x000000EB // USB Transmit Hub Port Endpoint
+ // 13
+#define USB_O_RXFUNCADDR13 0x000000EC // USB Receive Functional Address
+ // Endpoint 13
+#define USB_O_RXHUBADDR13 0x000000EE // USB Receive Hub Address Endpoint
+ // 13
+#define USB_O_RXHUBPORT13 0x000000EF // USB Receive Hub Port Endpoint 13
+#define USB_O_TXFUNCADDR14 0x000000F0 // USB Transmit Functional Address
+ // Endpoint 14
+#define USB_O_TXHUBADDR14 0x000000F2 // USB Transmit Hub Address
+ // Endpoint 14
+#define USB_O_TXHUBPORT14 0x000000F3 // USB Transmit Hub Port Endpoint
+ // 14
+#define USB_O_RXFUNCADDR14 0x000000F4 // USB Receive Functional Address
+ // Endpoint 14
+#define USB_O_RXHUBADDR14 0x000000F6 // USB Receive Hub Address Endpoint
+ // 14
+#define USB_O_RXHUBPORT14 0x000000F7 // USB Receive Hub Port Endpoint 14
+#define USB_O_TXFUNCADDR15 0x000000F8 // USB Transmit Functional Address
+ // Endpoint 15
+#define USB_O_TXHUBADDR15 0x000000FA // USB Transmit Hub Address
+ // Endpoint 15
+#define USB_O_TXHUBPORT15 0x000000FB // USB Transmit Hub Port Endpoint
+ // 15
+#define USB_O_RXFUNCADDR15 0x000000FC // USB Receive Functional Address
+ // Endpoint 15
+#define USB_O_RXHUBADDR15 0x000000FE // USB Receive Hub Address Endpoint
+ // 15
+#define USB_O_RXHUBPORT15 0x000000FF // USB Receive Hub Port Endpoint 15
+#define USB_O_CSRL0 0x00000102 // USB Control and Status Endpoint
+ // 0 Low
+#define USB_O_CSRH0 0x00000103 // USB Control and Status Endpoint
+ // 0 High
+#define USB_O_COUNT0 0x00000108 // USB Receive Byte Count Endpoint
+ // 0
+#define USB_O_TYPE0 0x0000010A // USB Type Endpoint 0
+#define USB_O_NAKLMT 0x0000010B // USB NAK Limit
+#define USB_O_TXMAXP1 0x00000110 // USB Maximum Transmit Data
+ // Endpoint 1
+#define USB_O_TXCSRL1 0x00000112 // USB Transmit Control and Status
+ // Endpoint 1 Low
+#define USB_O_TXCSRH1 0x00000113 // USB Transmit Control and Status
+ // Endpoint 1 High
+#define USB_O_RXMAXP1 0x00000114 // USB Maximum Receive Data
+ // Endpoint 1
+#define USB_O_RXCSRL1 0x00000116 // USB Receive Control and Status
+ // Endpoint 1 Low
+#define USB_O_RXCSRH1 0x00000117 // USB Receive Control and Status
+ // Endpoint 1 High
+#define USB_O_RXCOUNT1 0x00000118 // USB Receive Byte Count Endpoint
+ // 1
+#define USB_O_TXTYPE1 0x0000011A // USB Host Transmit Configure Type
+ // Endpoint 1
+#define USB_O_TXINTERVAL1 0x0000011B // USB Host Transmit Interval
+ // Endpoint 1
+#define USB_O_RXTYPE1 0x0000011C // USB Host Configure Receive Type
+ // Endpoint 1
+#define USB_O_RXINTERVAL1 0x0000011D // USB Host Receive Polling
+ // Interval Endpoint 1
+#define USB_O_TXMAXP2 0x00000120 // USB Maximum Transmit Data
+ // Endpoint 2
+#define USB_O_TXCSRL2 0x00000122 // USB Transmit Control and Status
+ // Endpoint 2 Low
+#define USB_O_TXCSRH2 0x00000123 // USB Transmit Control and Status
+ // Endpoint 2 High
+#define USB_O_RXMAXP2 0x00000124 // USB Maximum Receive Data
+ // Endpoint 2
+#define USB_O_RXCSRL2 0x00000126 // USB Receive Control and Status
+ // Endpoint 2 Low
+#define USB_O_RXCSRH2 0x00000127 // USB Receive Control and Status
+ // Endpoint 2 High
+#define USB_O_RXCOUNT2 0x00000128 // USB Receive Byte Count Endpoint
+ // 2
+#define USB_O_TXTYPE2 0x0000012A // USB Host Transmit Configure Type
+ // Endpoint 2
+#define USB_O_TXINTERVAL2 0x0000012B // USB Host Transmit Interval
+ // Endpoint 2
+#define USB_O_RXTYPE2 0x0000012C // USB Host Configure Receive Type
+ // Endpoint 2
+#define USB_O_RXINTERVAL2 0x0000012D // USB Host Receive Polling
+ // Interval Endpoint 2
+#define USB_O_TXMAXP3 0x00000130 // USB Maximum Transmit Data
+ // Endpoint 3
+#define USB_O_TXCSRL3 0x00000132 // USB Transmit Control and Status
+ // Endpoint 3 Low
+#define USB_O_TXCSRH3 0x00000133 // USB Transmit Control and Status
+ // Endpoint 3 High
+#define USB_O_RXMAXP3 0x00000134 // USB Maximum Receive Data
+ // Endpoint 3
+#define USB_O_RXCSRL3 0x00000136 // USB Receive Control and Status
+ // Endpoint 3 Low
+#define USB_O_RXCSRH3 0x00000137 // USB Receive Control and Status
+ // Endpoint 3 High
+#define USB_O_RXCOUNT3 0x00000138 // USB Receive Byte Count Endpoint
+ // 3
+#define USB_O_TXTYPE3 0x0000013A // USB Host Transmit Configure Type
+ // Endpoint 3
+#define USB_O_TXINTERVAL3 0x0000013B // USB Host Transmit Interval
+ // Endpoint 3
+#define USB_O_RXTYPE3 0x0000013C // USB Host Configure Receive Type
+ // Endpoint 3
+#define USB_O_RXINTERVAL3 0x0000013D // USB Host Receive Polling
+ // Interval Endpoint 3
+#define USB_O_TXMAXP4 0x00000140 // USB Maximum Transmit Data
+ // Endpoint 4
+#define USB_O_TXCSRL4 0x00000142 // USB Transmit Control and Status
+ // Endpoint 4 Low
+#define USB_O_TXCSRH4 0x00000143 // USB Transmit Control and Status
+ // Endpoint 4 High
+#define USB_O_RXMAXP4 0x00000144 // USB Maximum Receive Data
+ // Endpoint 4
+#define USB_O_RXCSRL4 0x00000146 // USB Receive Control and Status
+ // Endpoint 4 Low
+#define USB_O_RXCSRH4 0x00000147 // USB Receive Control and Status
+ // Endpoint 4 High
+#define USB_O_RXCOUNT4 0x00000148 // USB Receive Byte Count Endpoint
+ // 4
+#define USB_O_TXTYPE4 0x0000014A // USB Host Transmit Configure Type
+ // Endpoint 4
+#define USB_O_TXINTERVAL4 0x0000014B // USB Host Transmit Interval
+ // Endpoint 4
+#define USB_O_RXTYPE4 0x0000014C // USB Host Configure Receive Type
+ // Endpoint 4
+#define USB_O_RXINTERVAL4 0x0000014D // USB Host Receive Polling
+ // Interval Endpoint 4
+#define USB_O_TXMAXP5 0x00000150 // USB Maximum Transmit Data
+ // Endpoint 5
+#define USB_O_TXCSRL5 0x00000152 // USB Transmit Control and Status
+ // Endpoint 5 Low
+#define USB_O_TXCSRH5 0x00000153 // USB Transmit Control and Status
+ // Endpoint 5 High
+#define USB_O_RXMAXP5 0x00000154 // USB Maximum Receive Data
+ // Endpoint 5
+#define USB_O_RXCSRL5 0x00000156 // USB Receive Control and Status
+ // Endpoint 5 Low
+#define USB_O_RXCSRH5 0x00000157 // USB Receive Control and Status
+ // Endpoint 5 High
+#define USB_O_RXCOUNT5 0x00000158 // USB Receive Byte Count Endpoint
+ // 5
+#define USB_O_TXTYPE5 0x0000015A // USB Host Transmit Configure Type
+ // Endpoint 5
+#define USB_O_TXINTERVAL5 0x0000015B // USB Host Transmit Interval
+ // Endpoint 5
+#define USB_O_RXTYPE5 0x0000015C // USB Host Configure Receive Type
+ // Endpoint 5
+#define USB_O_RXINTERVAL5 0x0000015D // USB Host Receive Polling
+ // Interval Endpoint 5
+#define USB_O_TXMAXP6 0x00000160 // USB Maximum Transmit Data
+ // Endpoint 6
+#define USB_O_TXCSRL6 0x00000162 // USB Transmit Control and Status
+ // Endpoint 6 Low
+#define USB_O_TXCSRH6 0x00000163 // USB Transmit Control and Status
+ // Endpoint 6 High
+#define USB_O_RXMAXP6 0x00000164 // USB Maximum Receive Data
+ // Endpoint 6
+#define USB_O_RXCSRL6 0x00000166 // USB Receive Control and Status
+ // Endpoint 6 Low
+#define USB_O_RXCSRH6 0x00000167 // USB Receive Control and Status
+ // Endpoint 6 High
+#define USB_O_RXCOUNT6 0x00000168 // USB Receive Byte Count Endpoint
+ // 6
+#define USB_O_TXTYPE6 0x0000016A // USB Host Transmit Configure Type
+ // Endpoint 6
+#define USB_O_TXINTERVAL6 0x0000016B // USB Host Transmit Interval
+ // Endpoint 6
+#define USB_O_RXTYPE6 0x0000016C // USB Host Configure Receive Type
+ // Endpoint 6
+#define USB_O_RXINTERVAL6 0x0000016D // USB Host Receive Polling
+ // Interval Endpoint 6
+#define USB_O_TXMAXP7 0x00000170 // USB Maximum Transmit Data
+ // Endpoint 7
+#define USB_O_TXCSRL7 0x00000172 // USB Transmit Control and Status
+ // Endpoint 7 Low
+#define USB_O_TXCSRH7 0x00000173 // USB Transmit Control and Status
+ // Endpoint 7 High
+#define USB_O_RXMAXP7 0x00000174 // USB Maximum Receive Data
+ // Endpoint 7
+#define USB_O_RXCSRL7 0x00000176 // USB Receive Control and Status
+ // Endpoint 7 Low
+#define USB_O_RXCSRH7 0x00000177 // USB Receive Control and Status
+ // Endpoint 7 High
+#define USB_O_RXCOUNT7 0x00000178 // USB Receive Byte Count Endpoint
+ // 7
+#define USB_O_TXTYPE7 0x0000017A // USB Host Transmit Configure Type
+ // Endpoint 7
+#define USB_O_TXINTERVAL7 0x0000017B // USB Host Transmit Interval
+ // Endpoint 7
+#define USB_O_RXTYPE7 0x0000017C // USB Host Configure Receive Type
+ // Endpoint 7
+#define USB_O_RXINTERVAL7 0x0000017D // USB Host Receive Polling
+ // Interval Endpoint 7
+#define USB_O_TXMAXP8 0x00000180 // USB Maximum Transmit Data
+ // Endpoint 8
+#define USB_O_TXCSRL8 0x00000182 // USB Transmit Control and Status
+ // Endpoint 8 Low
+#define USB_O_TXCSRH8 0x00000183 // USB Transmit Control and Status
+ // Endpoint 8 High
+#define USB_O_RXMAXP8 0x00000184 // USB Maximum Receive Data
+ // Endpoint 8
+#define USB_O_RXCSRL8 0x00000186 // USB Receive Control and Status
+ // Endpoint 8 Low
+#define USB_O_RXCSRH8 0x00000187 // USB Receive Control and Status
+ // Endpoint 8 High
+#define USB_O_RXCOUNT8 0x00000188 // USB Receive Byte Count Endpoint
+ // 8
+#define USB_O_TXTYPE8 0x0000018A // USB Host Transmit Configure Type
+ // Endpoint 8
+#define USB_O_TXINTERVAL8 0x0000018B // USB Host Transmit Interval
+ // Endpoint 8
+#define USB_O_RXTYPE8 0x0000018C // USB Host Configure Receive Type
+ // Endpoint 8
+#define USB_O_RXINTERVAL8 0x0000018D // USB Host Receive Polling
+ // Interval Endpoint 8
+#define USB_O_TXMAXP9 0x00000190 // USB Maximum Transmit Data
+ // Endpoint 9
+#define USB_O_TXCSRL9 0x00000192 // USB Transmit Control and Status
+ // Endpoint 9 Low
+#define USB_O_TXCSRH9 0x00000193 // USB Transmit Control and Status
+ // Endpoint 9 High
+#define USB_O_RXMAXP9 0x00000194 // USB Maximum Receive Data
+ // Endpoint 9
+#define USB_O_RXCSRL9 0x00000196 // USB Receive Control and Status
+ // Endpoint 9 Low
+#define USB_O_RXCSRH9 0x00000197 // USB Receive Control and Status
+ // Endpoint 9 High
+#define USB_O_RXCOUNT9 0x00000198 // USB Receive Byte Count Endpoint
+ // 9
+#define USB_O_TXTYPE9 0x0000019A // USB Host Transmit Configure Type
+ // Endpoint 9
+#define USB_O_TXINTERVAL9 0x0000019B // USB Host Transmit Interval
+ // Endpoint 9
+#define USB_O_RXTYPE9 0x0000019C // USB Host Configure Receive Type
+ // Endpoint 9
+#define USB_O_RXINTERVAL9 0x0000019D // USB Host Receive Polling
+ // Interval Endpoint 9
+#define USB_O_TXMAXP10 0x000001A0 // USB Maximum Transmit Data
+ // Endpoint 10
+#define USB_O_TXCSRL10 0x000001A2 // USB Transmit Control and Status
+ // Endpoint 10 Low
+#define USB_O_TXCSRH10 0x000001A3 // USB Transmit Control and Status
+ // Endpoint 10 High
+#define USB_O_RXMAXP10 0x000001A4 // USB Maximum Receive Data
+ // Endpoint 10
+#define USB_O_RXCSRL10 0x000001A6 // USB Receive Control and Status
+ // Endpoint 10 Low
+#define USB_O_RXCSRH10 0x000001A7 // USB Receive Control and Status
+ // Endpoint 10 High
+#define USB_O_RXCOUNT10 0x000001A8 // USB Receive Byte Count Endpoint
+ // 10
+#define USB_O_TXTYPE10 0x000001AA // USB Host Transmit Configure Type
+ // Endpoint 10
+#define USB_O_TXINTERVAL10 0x000001AB // USB Host Transmit Interval
+ // Endpoint 10
+#define USB_O_RXTYPE10 0x000001AC // USB Host Configure Receive Type
+ // Endpoint 10
+#define USB_O_RXINTERVAL10 0x000001AD // USB Host Receive Polling
+ // Interval Endpoint 10
+#define USB_O_TXMAXP11 0x000001B0 // USB Maximum Transmit Data
+ // Endpoint 11
+#define USB_O_TXCSRL11 0x000001B2 // USB Transmit Control and Status
+ // Endpoint 11 Low
+#define USB_O_TXCSRH11 0x000001B3 // USB Transmit Control and Status
+ // Endpoint 11 High
+#define USB_O_RXMAXP11 0x000001B4 // USB Maximum Receive Data
+ // Endpoint 11
+#define USB_O_RXCSRL11 0x000001B6 // USB Receive Control and Status
+ // Endpoint 11 Low
+#define USB_O_RXCSRH11 0x000001B7 // USB Receive Control and Status
+ // Endpoint 11 High
+#define USB_O_RXCOUNT11 0x000001B8 // USB Receive Byte Count Endpoint
+ // 11
+#define USB_O_TXTYPE11 0x000001BA // USB Host Transmit Configure Type
+ // Endpoint 11
+#define USB_O_TXINTERVAL11 0x000001BB // USB Host Transmit Interval
+ // Endpoint 11
+#define USB_O_RXTYPE11 0x000001BC // USB Host Configure Receive Type
+ // Endpoint 11
+#define USB_O_RXINTERVAL11 0x000001BD // USB Host Receive Polling
+ // Interval Endpoint 11
+#define USB_O_TXMAXP12 0x000001C0 // USB Maximum Transmit Data
+ // Endpoint 12
+#define USB_O_TXCSRL12 0x000001C2 // USB Transmit Control and Status
+ // Endpoint 12 Low
+#define USB_O_TXCSRH12 0x000001C3 // USB Transmit Control and Status
+ // Endpoint 12 High
+#define USB_O_RXMAXP12 0x000001C4 // USB Maximum Receive Data
+ // Endpoint 12
+#define USB_O_RXCSRL12 0x000001C6 // USB Receive Control and Status
+ // Endpoint 12 Low
+#define USB_O_RXCSRH12 0x000001C7 // USB Receive Control and Status
+ // Endpoint 12 High
+#define USB_O_RXCOUNT12 0x000001C8 // USB Receive Byte Count Endpoint
+ // 12
+#define USB_O_TXTYPE12 0x000001CA // USB Host Transmit Configure Type
+ // Endpoint 12
+#define USB_O_TXINTERVAL12 0x000001CB // USB Host Transmit Interval
+ // Endpoint 12
+#define USB_O_RXTYPE12 0x000001CC // USB Host Configure Receive Type
+ // Endpoint 12
+#define USB_O_RXINTERVAL12 0x000001CD // USB Host Receive Polling
+ // Interval Endpoint 12
+#define USB_O_TXMAXP13 0x000001D0 // USB Maximum Transmit Data
+ // Endpoint 13
+#define USB_O_TXCSRL13 0x000001D2 // USB Transmit Control and Status
+ // Endpoint 13 Low
+#define USB_O_TXCSRH13 0x000001D3 // USB Transmit Control and Status
+ // Endpoint 13 High
+#define USB_O_RXMAXP13 0x000001D4 // USB Maximum Receive Data
+ // Endpoint 13
+#define USB_O_RXCSRL13 0x000001D6 // USB Receive Control and Status
+ // Endpoint 13 Low
+#define USB_O_RXCSRH13 0x000001D7 // USB Receive Control and Status
+ // Endpoint 13 High
+#define USB_O_RXCOUNT13 0x000001D8 // USB Receive Byte Count Endpoint
+ // 13
+#define USB_O_TXTYPE13 0x000001DA // USB Host Transmit Configure Type
+ // Endpoint 13
+#define USB_O_TXINTERVAL13 0x000001DB // USB Host Transmit Interval
+ // Endpoint 13
+#define USB_O_RXTYPE13 0x000001DC // USB Host Configure Receive Type
+ // Endpoint 13
+#define USB_O_RXINTERVAL13 0x000001DD // USB Host Receive Polling
+ // Interval Endpoint 13
+#define USB_O_TXMAXP14 0x000001E0 // USB Maximum Transmit Data
+ // Endpoint 14
+#define USB_O_TXCSRL14 0x000001E2 // USB Transmit Control and Status
+ // Endpoint 14 Low
+#define USB_O_TXCSRH14 0x000001E3 // USB Transmit Control and Status
+ // Endpoint 14 High
+#define USB_O_RXMAXP14 0x000001E4 // USB Maximum Receive Data
+ // Endpoint 14
+#define USB_O_RXCSRL14 0x000001E6 // USB Receive Control and Status
+ // Endpoint 14 Low
+#define USB_O_RXCSRH14 0x000001E7 // USB Receive Control and Status
+ // Endpoint 14 High
+#define USB_O_RXCOUNT14 0x000001E8 // USB Receive Byte Count Endpoint
+ // 14
+#define USB_O_TXTYPE14 0x000001EA // USB Host Transmit Configure Type
+ // Endpoint 14
+#define USB_O_TXINTERVAL14 0x000001EB // USB Host Transmit Interval
+ // Endpoint 14
+#define USB_O_RXTYPE14 0x000001EC // USB Host Configure Receive Type
+ // Endpoint 14
+#define USB_O_RXINTERVAL14 0x000001ED // USB Host Receive Polling
+ // Interval Endpoint 14
+#define USB_O_TXMAXP15 0x000001F0 // USB Maximum Transmit Data
+ // Endpoint 15
+#define USB_O_TXCSRL15 0x000001F2 // USB Transmit Control and Status
+ // Endpoint 15 Low
+#define USB_O_TXCSRH15 0x000001F3 // USB Transmit Control and Status
+ // Endpoint 15 High
+#define USB_O_RXMAXP15 0x000001F4 // USB Maximum Receive Data
+ // Endpoint 15
+#define USB_O_RXCSRL15 0x000001F6 // USB Receive Control and Status
+ // Endpoint 15 Low
+#define USB_O_RXCSRH15 0x000001F7 // USB Receive Control and Status
+ // Endpoint 15 High
+#define USB_O_RXCOUNT15 0x000001F8 // USB Receive Byte Count Endpoint
+ // 15
+#define USB_O_TXTYPE15 0x000001FA // USB Host Transmit Configure Type
+ // Endpoint 15
+#define USB_O_TXINTERVAL15 0x000001FB // USB Host Transmit Interval
+ // Endpoint 15
+#define USB_O_RXTYPE15 0x000001FC // USB Host Configure Receive Type
+ // Endpoint 15
+#define USB_O_RXINTERVAL15 0x000001FD // USB Host Receive Polling
+ // Interval Endpoint 15
+#define USB_O_RQPKTCOUNT1 0x00000304 // USB Request Packet Count in
+ // Block Transfer Endpoint 1
+#define USB_O_RQPKTCOUNT2 0x00000308 // USB Request Packet Count in
+ // Block Transfer Endpoint 2
+#define USB_O_RQPKTCOUNT3 0x0000030C // USB Request Packet Count in
+ // Block Transfer Endpoint 3
+#define USB_O_RQPKTCOUNT4 0x00000310 // USB Request Packet Count in
+ // Block Transfer Endpoint 4
+#define USB_O_RQPKTCOUNT5 0x00000314 // USB Request Packet Count in
+ // Block Transfer Endpoint 5
+#define USB_O_RQPKTCOUNT6 0x00000318 // USB Request Packet Count in
+ // Block Transfer Endpoint 6
+#define USB_O_RQPKTCOUNT7 0x0000031C // USB Request Packet Count in
+ // Block Transfer Endpoint 7
+#define USB_O_RQPKTCOUNT8 0x00000320 // USB Request Packet Count in
+ // Block Transfer Endpoint 8
+#define USB_O_RQPKTCOUNT9 0x00000324 // USB Request Packet Count in
+ // Block Transfer Endpoint 9
+#define USB_O_RQPKTCOUNT10 0x00000328 // USB Request Packet Count in
+ // Block Transfer Endpoint 10
+#define USB_O_RQPKTCOUNT11 0x0000032C // USB Request Packet Count in
+ // Block Transfer Endpoint 11
+#define USB_O_RQPKTCOUNT12 0x00000330 // USB Request Packet Count in
+ // Block Transfer Endpoint 12
+#define USB_O_RQPKTCOUNT13 0x00000334 // USB Request Packet Count in
+ // Block Transfer Endpoint 13
+#define USB_O_RQPKTCOUNT14 0x00000338 // USB Request Packet Count in
+ // Block Transfer Endpoint 14
+#define USB_O_RQPKTCOUNT15 0x0000033C // USB Request Packet Count in
+ // Block Transfer Endpoint 15
+#define USB_O_RXDPKTBUFDIS 0x00000340 // USB Receive Double Packet Buffer
+ // Disable
+#define USB_O_TXDPKTBUFDIS 0x00000342 // USB Transmit Double Packet
+ // Buffer Disable
+#define USB_O_EPC 0x00000400 // USB External Power Control
+#define USB_O_EPCRIS 0x00000404 // USB External Power Control Raw
+ // Interrupt Status
+#define USB_O_EPCIM 0x00000408 // USB External Power Control
+ // Interrupt Mask
+#define USB_O_EPCISC 0x0000040C // USB External Power Control
+ // Interrupt Status and Clear
+#define USB_O_DRRIS 0x00000410 // USB Device Resume Raw Interrupt
+ // Status
+#define USB_O_DRIM 0x00000414 // USB Device Resume Interrupt Mask
+#define USB_O_DRISC 0x00000418 // USB Device Resume Interrupt
+ // Status and Clear
+#define USB_O_GPCS 0x0000041C // USB General-Purpose Control and
+ // Status
+#define USB_O_VDC 0x00000430 // USB VBUS Droop Control
+#define USB_O_VDCRIS 0x00000434 // USB VBUS Droop Control Raw
+ // Interrupt Status
+#define USB_O_VDCIM 0x00000438 // USB VBUS Droop Control Interrupt
+ // Mask
+#define USB_O_VDCISC 0x0000043C // USB VBUS Droop Control Interrupt
+ // Status and Clear
+#define USB_O_IDVRIS 0x00000444 // USB ID Valid Detect Raw
+ // Interrupt Status
+#define USB_O_IDVIM 0x00000448 // USB ID Valid Detect Interrupt
+ // Mask
+#define USB_O_IDVISC 0x0000044C // USB ID Valid Detect Interrupt
+ // Status and Clear
+#define USB_O_EPS 0x00000450 // USB End-Point Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FADDR register.
+//
+//*****************************************************************************
+#define USB_FADDR_M 0x0000007F // Function Address.
+#define USB_FADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_POWER register.
+//
+//*****************************************************************************
+#define USB_POWER_ISOUP 0x00000080 // ISO Update.
+#define USB_POWER_SOFTCONN 0x00000040 // Soft Connect/Disconnect.
+#define USB_POWER_RESET 0x00000008 // Reset.
+#define USB_POWER_RESUME 0x00000004 // Resume Signaling.
+#define USB_POWER_SUSPEND 0x00000002 // Suspend Mode.
+#define USB_POWER_PWRDNPHY 0x00000001 // Power Down PHY.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXIS register.
+//
+//*****************************************************************************
+#define USB_TXIS_EP15 0x00008000 // TX Endpoint 15 Interrupt.
+#define USB_TXIS_EP14 0x00004000 // TX Endpoint 14 Interrupt.
+#define USB_TXIS_EP13 0x00002000 // TX Endpoint 13 Interrupt.
+#define USB_TXIS_EP12 0x00001000 // TX Endpoint 12 Interrupt.
+#define USB_TXIS_EP11 0x00000800 // TX Endpoint 11 Interrupt.
+#define USB_TXIS_EP10 0x00000400 // TX Endpoint 10 Interrupt.
+#define USB_TXIS_EP9 0x00000200 // TX Endpoint 9 Interrupt.
+#define USB_TXIS_EP8 0x00000100 // TX Endpoint 8 Interrupt.
+#define USB_TXIS_EP7 0x00000080 // TX Endpoint 7 Interrupt.
+#define USB_TXIS_EP6 0x00000040 // TX Endpoint 6 Interrupt.
+#define USB_TXIS_EP5 0x00000020 // TX Endpoint 5 Interrupt.
+#define USB_TXIS_EP4 0x00000010 // TX Endpoint 4 Interrupt.
+#define USB_TXIS_EP3 0x00000008 // TX Endpoint 3 Interrupt.
+#define USB_TXIS_EP2 0x00000004 // TX Endpoint 2 Interrupt.
+#define USB_TXIS_EP1 0x00000002 // TX Endpoint 1 Interrupt.
+#define USB_TXIS_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXIS register.
+//
+//*****************************************************************************
+#define USB_RXIS_EP15 0x00008000 // RX Endpoint 15 Interrupt.
+#define USB_RXIS_EP14 0x00004000 // RX Endpoint 14 Interrupt.
+#define USB_RXIS_EP13 0x00002000 // RX Endpoint 13 Interrupt.
+#define USB_RXIS_EP12 0x00001000 // RX Endpoint 12 Interrupt.
+#define USB_RXIS_EP11 0x00000800 // RX Endpoint 11 Interrupt.
+#define USB_RXIS_EP10 0x00000400 // RX Endpoint 10 Interrupt.
+#define USB_RXIS_EP9 0x00000200 // RX Endpoint 9 Interrupt.
+#define USB_RXIS_EP8 0x00000100 // RX Endpoint 8 Interrupt.
+#define USB_RXIS_EP7 0x00000080 // RX Endpoint 7 Interrupt.
+#define USB_RXIS_EP6 0x00000040 // RX Endpoint 6 Interrupt.
+#define USB_RXIS_EP5 0x00000020 // RX Endpoint 5 Interrupt.
+#define USB_RXIS_EP4 0x00000010 // RX Endpoint 4 Interrupt.
+#define USB_RXIS_EP3 0x00000008 // RX Endpoint 3 Interrupt.
+#define USB_RXIS_EP2 0x00000004 // RX Endpoint 2 Interrupt.
+#define USB_RXIS_EP1 0x00000002 // RX Endpoint 1 Interrupt.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXIE register.
+//
+//*****************************************************************************
+#define USB_TXIE_EP15 0x00008000 // TX Endpoint 15 Interrupt Enable.
+#define USB_TXIE_EP14 0x00004000 // TX Endpoint 14 Interrupt Enable.
+#define USB_TXIE_EP13 0x00002000 // TX Endpoint 13 Interrupt Enable.
+#define USB_TXIE_EP12 0x00001000 // TX Endpoint 12 Interrupt Enable.
+#define USB_TXIE_EP11 0x00000800 // TX Endpoint 11 Interrupt Enable.
+#define USB_TXIE_EP10 0x00000400 // TX Endpoint 10 Interrupt Enable.
+#define USB_TXIE_EP9 0x00000200 // TX Endpoint 9 Interrupt Enable.
+#define USB_TXIE_EP8 0x00000100 // TX Endpoint 8 Interrupt Enable.
+#define USB_TXIE_EP7 0x00000080 // TX Endpoint 7 Interrupt Enable.
+#define USB_TXIE_EP6 0x00000040 // TX Endpoint 6 Interrupt Enable.
+#define USB_TXIE_EP5 0x00000020 // TX Endpoint 5 Interrupt Enable.
+#define USB_TXIE_EP4 0x00000010 // TX Endpoint 4 Interrupt Enable.
+#define USB_TXIE_EP3 0x00000008 // TX Endpoint 3 Interrupt Enable.
+#define USB_TXIE_EP2 0x00000004 // TX Endpoint 2 Interrupt Enable.
+#define USB_TXIE_EP1 0x00000002 // TX Endpoint 1 Interrupt Enable.
+#define USB_TXIE_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt
+ // Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXIE register.
+//
+//*****************************************************************************
+#define USB_RXIE_EP15 0x00008000 // RX Endpoint 15 Interrupt Enable.
+#define USB_RXIE_EP14 0x00004000 // RX Endpoint 14 Interrupt Enable.
+#define USB_RXIE_EP13 0x00002000 // RX Endpoint 13 Interrupt Enable.
+#define USB_RXIE_EP12 0x00001000 // RX Endpoint 12 Interrupt Enable.
+#define USB_RXIE_EP11 0x00000800 // RX Endpoint 11 Interrupt Enable.
+#define USB_RXIE_EP10 0x00000400 // RX Endpoint 10 Interrupt Enable.
+#define USB_RXIE_EP9 0x00000200 // RX Endpoint 9 Interrupt Enable.
+#define USB_RXIE_EP8 0x00000100 // RX Endpoint 8 Interrupt Enable.
+#define USB_RXIE_EP7 0x00000080 // RX Endpoint 7 Interrupt Enable.
+#define USB_RXIE_EP6 0x00000040 // RX Endpoint 6 Interrupt Enable.
+#define USB_RXIE_EP5 0x00000020 // RX Endpoint 5 Interrupt Enable.
+#define USB_RXIE_EP4 0x00000010 // RX Endpoint 4 Interrupt Enable.
+#define USB_RXIE_EP3 0x00000008 // RX Endpoint 3 Interrupt Enable.
+#define USB_RXIE_EP2 0x00000004 // RX Endpoint 2 Interrupt Enable.
+#define USB_RXIE_EP1 0x00000002 // RX Endpoint 1 Interrupt Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IS register.
+//
+//*****************************************************************************
+#define USB_IS_VBUSERR 0x00000080 // VBus Error.
+#define USB_IS_SESREQ 0x00000040 // Session Request.
+#define USB_IS_DISCON 0x00000020 // Session Disconnect.
+#define USB_IS_CONN 0x00000010 // Session Connect.
+#define USB_IS_SOF 0x00000008 // Start of Frame.
+#define USB_IS_BABBLE 0x00000004 // Babble Detected.
+#define USB_IS_RESET 0x00000004 // Reset Signal Detected.
+#define USB_IS_RESUME 0x00000002 // Resume Signal Detected.
+#define USB_IS_SUSPEND 0x00000001 // Suspend Signal Detected.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IE register.
+//
+//*****************************************************************************
+#define USB_IE_VBUSERR 0x00000080 // Enable VBUS Error Interrupt.
+#define USB_IE_SESREQ 0x00000040 // Enable Session Request
+ // Interrupt.
+#define USB_IE_DISCON 0x00000020 // Enable Disconnect Interrupt.
+#define USB_IE_CONN 0x00000010 // Enable Connect Interrupt.
+#define USB_IE_SOF 0x00000008 // Enable Start-of-Frame Interrupt.
+#define USB_IE_BABBLE 0x00000004 // Enable Babble Interrupt.
+#define USB_IE_RESET 0x00000004 // Enable Reset Interrupt.
+#define USB_IE_RESUME 0x00000002 // Enable Resume Interrupt.
+#define USB_IE_SUSPND 0x00000001 // Enable Suspend Interrupt.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FRAME register.
+//
+//*****************************************************************************
+#define USB_FRAME_M 0x000007FF // Frame Number.
+#define USB_FRAME_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPIDX register.
+//
+//*****************************************************************************
+#define USB_EPIDX_EPIDX_M 0x0000000F // Endpoint Index.
+#define USB_EPIDX_EPIDX_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TEST register.
+//
+//*****************************************************************************
+#define USB_TEST_FORCEH 0x00000080 // Force Host Mode.
+#define USB_TEST_FIFOACC 0x00000040 // FIFO Access.
+#define USB_TEST_FORCEFS 0x00000020 // Force Full Speed.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO0 register.
+//
+//*****************************************************************************
+#define USB_FIFO0_EPDATA_M 0xFFFFFFFF // Endpoint Data.
+#define USB_FIFO0_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO1 register.
+//
+//*****************************************************************************
+#define USB_FIFO1_EPDATA_M 0xFFFFFFFF // Endpoint Data.
+#define USB_FIFO1_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO2 register.
+//
+//*****************************************************************************
+#define USB_FIFO2_EPDATA_M 0xFFFFFFFF // Endpoint Data.
+#define USB_FIFO2_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO3 register.
+//
+//*****************************************************************************
+#define USB_FIFO3_EPDATA_M 0xFFFFFFFF // Endpoint Data.
+#define USB_FIFO3_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DEVCTL register.
+//
+//*****************************************************************************
+#define USB_DEVCTL_DEV 0x00000080 // Device Mode.
+#define USB_DEVCTL_FSDEV 0x00000040 // Full-Speed Device Detected.
+#define USB_DEVCTL_LSDEV 0x00000020 // Low-Speed Device Detected.
+#define USB_DEVCTL_VBUS_M 0x00000018 // VBus Level.
+#define USB_DEVCTL_VBUS_NONE 0x00000000 // Below SessionEnd
+#define USB_DEVCTL_VBUS_SEND 0x00000008 // Above SessionEnd, below AValid
+#define USB_DEVCTL_VBUS_AVALID 0x00000010 // Above AValid, below VBusValid
+#define USB_DEVCTL_VBUS_VALID 0x00000018 // Above VBusValid
+#define USB_DEVCTL_HOST 0x00000004 // Host Mode.
+#define USB_DEVCTL_HOSTREQ 0x00000002 // Host Request.
+#define USB_DEVCTL_SESSION 0x00000001 // Session Start/End.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFIFOSZ register.
+//
+//*****************************************************************************
+#define USB_TXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support.
+#define USB_TXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size.
+#define USB_TXFIFOSZ_SIZE_8 0x00000000 // 8
+#define USB_TXFIFOSZ_SIZE_16 0x00000001 // 16
+#define USB_TXFIFOSZ_SIZE_32 0x00000002 // 32
+#define USB_TXFIFOSZ_SIZE_64 0x00000003 // 64
+#define USB_TXFIFOSZ_SIZE_128 0x00000004 // 128
+#define USB_TXFIFOSZ_SIZE_256 0x00000005 // 256
+#define USB_TXFIFOSZ_SIZE_512 0x00000006 // 512
+#define USB_TXFIFOSZ_SIZE_1024 0x00000007 // 1024
+#define USB_TXFIFOSZ_SIZE_2048 0x00000008 // 2048
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFIFOSZ register.
+//
+//*****************************************************************************
+#define USB_RXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support.
+#define USB_RXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size.
+#define USB_RXFIFOSZ_SIZE_8 0x00000000 // 8
+#define USB_RXFIFOSZ_SIZE_16 0x00000001 // 16
+#define USB_RXFIFOSZ_SIZE_32 0x00000002 // 32
+#define USB_RXFIFOSZ_SIZE_64 0x00000003 // 64
+#define USB_RXFIFOSZ_SIZE_128 0x00000004 // 128
+#define USB_RXFIFOSZ_SIZE_256 0x00000005 // 256
+#define USB_RXFIFOSZ_SIZE_512 0x00000006 // 512
+#define USB_RXFIFOSZ_SIZE_1024 0x00000007 // 1024
+#define USB_RXFIFOSZ_SIZE_2048 0x00000008 // 2048
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFIFOADD
+// register.
+//
+//*****************************************************************************
+#define USB_TXFIFOADD_ADDR_M 0x00001FFF // Transmit/Receive Start Address.
+#define USB_TXFIFOADD_ADDR_0 0x00000000 // 0
+#define USB_TXFIFOADD_ADDR_8 0x00000001 // 8
+#define USB_TXFIFOADD_ADDR_16 0x00000002 // 16
+#define USB_TXFIFOADD_ADDR_32 0x00000003 // 32
+#define USB_TXFIFOADD_ADDR_64 0x00000004 // 64
+#define USB_TXFIFOADD_ADDR_128 0x00000005 // 128
+#define USB_TXFIFOADD_ADDR_256 0x00000006 // 256
+#define USB_TXFIFOADD_ADDR_512 0x00000007 // 512
+#define USB_TXFIFOADD_ADDR_1024 0x00000008 // 1024
+#define USB_TXFIFOADD_ADDR_2048 0x00000009 // 2048
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFIFOADD
+// register.
+//
+//*****************************************************************************
+#define USB_RXFIFOADD_ADDR_M 0x00001FFF // Transmit/Receive Start Address.
+#define USB_RXFIFOADD_ADDR_0 0x00000000 // 0
+#define USB_RXFIFOADD_ADDR_8 0x00000001 // 8
+#define USB_RXFIFOADD_ADDR_16 0x00000002 // 16
+#define USB_RXFIFOADD_ADDR_32 0x00000003 // 32
+#define USB_RXFIFOADD_ADDR_64 0x00000004 // 64
+#define USB_RXFIFOADD_ADDR_128 0x00000005 // 128
+#define USB_RXFIFOADD_ADDR_256 0x00000006 // 256
+#define USB_RXFIFOADD_ADDR_512 0x00000007 // 512
+#define USB_RXFIFOADD_ADDR_1024 0x00000008 // 1024
+#define USB_RXFIFOADD_ADDR_2048 0x00000009 // 2048
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_CONTIM register.
+//
+//*****************************************************************************
+#define USB_CONTIM_WTCON_M 0x000000F0 // Connect Wait.
+#define USB_CONTIM_WTID_M 0x0000000F // Wait ID.
+#define USB_CONTIM_WTCON_S 4
+#define USB_CONTIM_WTID_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FSEOF register.
+//
+//*****************************************************************************
+#define USB_FSEOF_FSEOFG_M 0x000000FF // Full-Speed End-of-Frame Gap.
+#define USB_FSEOF_FSEOFG_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_LSEOF register.
+//
+//*****************************************************************************
+#define USB_LSEOF_LSEOFG_M 0x000000FF // Low-Speed End-of-Frame Gap.
+#define USB_LSEOF_LSEOFG_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR0
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR0_ADDR_M 0x0000007F // Device Address.
+#define USB_TXFUNCADDR0_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR0
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR0_MULTTRAN 0x00000080 // Multiple Translators.
+#define USB_TXHUBADDR0_ADDR_M 0x0000007F // Hub Address.
+#define USB_TXHUBADDR0_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT0
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT0_PORT_M 0x0000007F // Hub Port.
+#define USB_TXHUBPORT0_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR1
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR1_ADDR_M 0x0000007F // Device Address.
+#define USB_TXFUNCADDR1_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR1
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR1_MULTTRAN 0x00000080 // Multiple Translators.
+#define USB_TXHUBADDR1_ADDR_M 0x0000007F // Hub Address.
+#define USB_TXHUBADDR1_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT1
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT1_PORT_M 0x0000007F // Hub Port.
+#define USB_TXHUBPORT1_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR1
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR1_ADDR_M 0x0000007F // Device Address.
+#define USB_RXFUNCADDR1_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR1
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR1_MULTTRAN 0x00000080 // Multiple Translators.
+#define USB_RXHUBADDR1_ADDR_M 0x0000007F // Hub Address.
+#define USB_RXHUBADDR1_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT1
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT1_PORT_M 0x0000007F // Hub Port.
+#define USB_RXHUBPORT1_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR2
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR2_ADDR_M 0x0000007F // Device Address.
+#define USB_TXFUNCADDR2_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR2
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR2_MULTTRAN 0x00000080 // Multiple Translators.
+#define USB_TXHUBADDR2_ADDR_M 0x0000007F // Hub Address.
+#define USB_TXHUBADDR2_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT2
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT2_PORT_M 0x0000007F // Hub Port.
+#define USB_TXHUBPORT2_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR2
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR2_ADDR_M 0x0000007F // Device Address.
+#define USB_RXFUNCADDR2_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR2
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR2_MULTTRAN 0x00000080 // Multiple Translators.
+#define USB_RXHUBADDR2_ADDR_M 0x0000007F // Hub Address.
+#define USB_RXHUBADDR2_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT2
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT2_PORT_M 0x0000007F // Hub Port.
+#define USB_RXHUBPORT2_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR3
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR3_ADDR_M 0x0000007F // Device Address.
+#define USB_TXFUNCADDR3_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR3
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR3_MULTTRAN 0x00000080 // Multiple Translators.
+#define USB_TXHUBADDR3_ADDR_M 0x0000007F // Hub Address.
+#define USB_TXHUBADDR3_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT3
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT3_PORT_M 0x0000007F // Hub Port.
+#define USB_TXHUBPORT3_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR3
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR3_ADDR_M 0x0000007F // Device Address.
+#define USB_RXFUNCADDR3_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR3
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR3_MULTTRAN 0x00000080 // Multiple Translators.
+#define USB_RXHUBADDR3_ADDR_M 0x0000007F // Hub Address.
+#define USB_RXHUBADDR3_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT3
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT3_PORT_M 0x0000007F // Hub Port.
+#define USB_RXHUBPORT3_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_CSRL0 register.
+//
+//*****************************************************************************
+#define USB_CSRL0_NAKTO 0x00000080 // NAK Timeout.
+#define USB_CSRL0_SETENDC 0x00000080 // Setup End Clear.
+#define USB_CSRL0_STATUS 0x00000040 // Status Packet.
+#define USB_CSRL0_RXRDYC 0x00000040 // RXRDY Clear.
+#define USB_CSRL0_REQPKT 0x00000020 // Request Packet.
+#define USB_CSRL0_STALL 0x00000020 // Send Stall.
+#define USB_CSRL0_SETEND 0x00000010 // Setup End.
+#define USB_CSRL0_ERROR 0x00000010 // Error.
+#define USB_CSRL0_DATAEND 0x00000008 // Data End.
+#define USB_CSRL0_SETUP 0x00000008 // Setup Packet.
+#define USB_CSRL0_STALLED 0x00000004 // Endpoint Stalled.
+#define USB_CSRL0_TXRDY 0x00000002 // Transmit Packet Ready.
+#define USB_CSRL0_RXRDY 0x00000001 // Receive Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_CSRH0 register.
+//
+//*****************************************************************************
+#define USB_CSRH0_DTWE 0x00000004 // Data Toggle Write Enable.
+#define USB_CSRH0_DT 0x00000002 // Data Toggle.
+#define USB_CSRH0_FLUSH 0x00000001 // Flush FIFO.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_COUNT0 register.
+//
+//*****************************************************************************
+#define USB_COUNT0_COUNT_M 0x0000007F // Count.
+#define USB_COUNT0_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TYPE0 register.
+//
+//*****************************************************************************
+#define USB_TYPE0_SPEED_M 0x000000C0 // Operating Speed.
+#define USB_TYPE0_SPEED_FULL 0x00000080 // Full
+#define USB_TYPE0_SPEED_LOW 0x000000C0 // Low
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_NAKLMT register.
+//
+//*****************************************************************************
+#define USB_NAKLMT_NAKLMT_M 0x0000001F // EP0 NAK Limit.
+#define USB_NAKLMT_NAKLMT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP1 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP1_MULT_M 0x0000F800 // Multiplier.
+#define USB_TXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload.
+#define USB_TXMAXP1_MULT_S 11
+#define USB_TXMAXP1_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL1 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL1_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL1_INCTX 0x00000080 // Incomplete Transmit.
+#define USB_TXCSRL1_CLRDT 0x00000040 // Clear Data Toggle.
+#define USB_TXCSRL1_STALLED 0x00000020 // Endpoint Stalled.
+#define USB_TXCSRL1_STALL 0x00000010 // Send Stall.
+#define USB_TXCSRL1_SETUP 0x00000010 // Setup Packet.
+#define USB_TXCSRL1_FLUSH 0x00000008 // Flush FIFO.
+#define USB_TXCSRL1_ERROR 0x00000004 // Error.
+#define USB_TXCSRL1_UNDRN 0x00000004 // Underrun.
+#define USB_TXCSRL1_FIFONE 0x00000002 // FIFO Not Empty.
+#define USB_TXCSRL1_TXRDY 0x00000001 // Transmit Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH1 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH1_AUTOSET 0x00000080 // Auto Set.
+#define USB_TXCSRH1_ISO 0x00000040 // ISO.
+#define USB_TXCSRH1_MODE 0x00000020 // Mode.
+#define USB_TXCSRH1_DMAEN 0x00000010 // DMA Request Enable.
+#define USB_TXCSRH1_FDT 0x00000008 // Force Data Toggle.
+#define USB_TXCSRH1_DMAMOD 0x00000004 // DMA Request Mode.
+#define USB_TXCSRH1_DTWE 0x00000002 // Data Toggle Write Enable.
+#define USB_TXCSRH1_DT 0x00000001 // Data Toggle.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP1 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP1_MULT_M 0x0000F800 // Multiplier.
+#define USB_RXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload.
+#define USB_RXMAXP1_MULT_S 11
+#define USB_RXMAXP1_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL1 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL1_CLRDT 0x00000080 // Clear Data Toggle.
+#define USB_RXCSRL1_STALLED 0x00000040 // Endpoint Stalled.
+#define USB_RXCSRL1_STALL 0x00000020 // Send Stall.
+#define USB_RXCSRL1_REQPKT 0x00000020 // Request Packet.
+#define USB_RXCSRL1_FLUSH 0x00000010 // Flush FIFO.
+#define USB_RXCSRL1_DATAERR 0x00000008 // Data Error.
+#define USB_RXCSRL1_NAKTO 0x00000008 // NAK Timeout.
+#define USB_RXCSRL1_OVER 0x00000004 // Overrun.
+#define USB_RXCSRL1_ERROR 0x00000004 // Error.
+#define USB_RXCSRL1_FULL 0x00000002 // FIFO Full.
+#define USB_RXCSRL1_RXRDY 0x00000001 // Receive Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH1 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH1_AUTOCL 0x00000080 // Auto Clear.
+#define USB_RXCSRH1_AUTORQ 0x00000040 // Auto Request.
+#define USB_RXCSRH1_ISO 0x00000040 // ISO.
+#define USB_RXCSRH1_DMAEN 0x00000020 // DMA Request Enable.
+#define USB_RXCSRH1_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH1_PIDERR 0x00000010 // PID Error.
+#define USB_RXCSRH1_DMAMOD 0x00000008 // DMA Request Mode.
+#define USB_RXCSRH1_DTWE 0x00000004 // Data Toggle Write Enable.
+#define USB_RXCSRH1_DT 0x00000002 // Data Toggle.
+#define USB_RXCSRH1_INCRX 0x00000001 // Incomplete Receive.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT1 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT1_COUNT_M 0x00001FFF // Receive Packet Count.
+#define USB_RXCOUNT1_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE1 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE1_SPEED_M 0x000000C0 // Operating Speed.
+#define USB_TXTYPE1_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE1_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE1_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE1_PROTO_M 0x00000030 // Protocol.
+#define USB_TXTYPE1_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE1_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE1_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE1_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE1_TEP_M 0x0000000F // Target Endpoint Number.
+#define USB_TXTYPE1_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL1
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL1_NAKLMT_M \
+ 0x000000FF // NAK Limit.
+#define USB_TXINTERVAL1_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL1_TXPOLL_S \
+ 0
+#define USB_TXINTERVAL1_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE1 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE1_SPEED_M 0x000000C0 // Operating Speed.
+#define USB_RXTYPE1_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE1_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE1_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE1_PROTO_M 0x00000030 // Protocol.
+#define USB_RXTYPE1_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE1_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE1_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE1_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE1_TEP_M 0x0000000F // Target Endpoint Number.
+#define USB_RXTYPE1_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL1
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL1_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL1_NAKLMT_M \
+ 0x000000FF // NAK Limit.
+#define USB_RXINTERVAL1_TXPOLL_S \
+ 0
+#define USB_RXINTERVAL1_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP2 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP2_MULT_M 0x0000F800 // Multiplier.
+#define USB_TXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload.
+#define USB_TXMAXP2_MULT_S 11
+#define USB_TXMAXP2_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL2 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL2_INCTX 0x00000080 // Incomplete Transmit.
+#define USB_TXCSRL2_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL2_CLRDT 0x00000040 // Clear Data Toggle.
+#define USB_TXCSRL2_STALLED 0x00000020 // Endpoint Stalled.
+#define USB_TXCSRL2_SETUP 0x00000010 // Setup Packet.
+#define USB_TXCSRL2_STALL 0x00000010 // Send Stall.
+#define USB_TXCSRL2_FLUSH 0x00000008 // Flush FIFO.
+#define USB_TXCSRL2_ERROR 0x00000004 // Error.
+#define USB_TXCSRL2_UNDRN 0x00000004 // Underrun.
+#define USB_TXCSRL2_FIFONE 0x00000002 // FIFO Not Empty.
+#define USB_TXCSRL2_TXRDY 0x00000001 // Transmit Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH2 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH2_AUTOSET 0x00000080 // Auto Set.
+#define USB_TXCSRH2_ISO 0x00000040 // ISO.
+#define USB_TXCSRH2_MODE 0x00000020 // Mode.
+#define USB_TXCSRH2_DMAEN 0x00000010 // DMA Request Enable.
+#define USB_TXCSRH2_FDT 0x00000008 // Force Data Toggle.
+#define USB_TXCSRH2_DMAMOD 0x00000004 // DMA Request Mode.
+#define USB_TXCSRH2_DTWE 0x00000002 // Data Toggle Write Enable.
+#define USB_TXCSRH2_DT 0x00000001 // Data Toggle.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP2 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP2_MULT_M 0x0000F800 // Multiplier.
+#define USB_RXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload.
+#define USB_RXMAXP2_MULT_S 11
+#define USB_RXMAXP2_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL2 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL2_CLRDT 0x00000080 // Clear Data Toggle.
+#define USB_RXCSRL2_STALLED 0x00000040 // Endpoint Stalled.
+#define USB_RXCSRL2_REQPKT 0x00000020 // Request Packet.
+#define USB_RXCSRL2_STALL 0x00000020 // Send Stall.
+#define USB_RXCSRL2_FLUSH 0x00000010 // Flush FIFO.
+#define USB_RXCSRL2_DATAERR 0x00000008 // Data Error.
+#define USB_RXCSRL2_NAKTO 0x00000008 // NAK Timeout.
+#define USB_RXCSRL2_ERROR 0x00000004 // Error.
+#define USB_RXCSRL2_OVER 0x00000004 // Overrun.
+#define USB_RXCSRL2_FULL 0x00000002 // FIFO Full.
+#define USB_RXCSRL2_RXRDY 0x00000001 // Receive Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH2 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH2_AUTOCL 0x00000080 // Auto Clear.
+#define USB_RXCSRH2_AUTORQ 0x00000040 // Auto Request.
+#define USB_RXCSRH2_ISO 0x00000040 // ISO.
+#define USB_RXCSRH2_DMAEN 0x00000020 // DMA Request Enable.
+#define USB_RXCSRH2_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH2_PIDERR 0x00000010 // PID Error.
+#define USB_RXCSRH2_DMAMOD 0x00000008 // DMA Request Mode.
+#define USB_RXCSRH2_DTWE 0x00000004 // Data Toggle Write Enable.
+#define USB_RXCSRH2_DT 0x00000002 // Data Toggle.
+#define USB_RXCSRH2_INCRX 0x00000001 // Incomplete Receive.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT2 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT2_COUNT_M 0x00001FFF // Receive Packet Count.
+#define USB_RXCOUNT2_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE2 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE2_SPEED_M 0x000000C0 // Operating Speed.
+#define USB_TXTYPE2_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE2_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE2_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE2_PROTO_M 0x00000030 // Protocol.
+#define USB_TXTYPE2_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE2_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE2_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE2_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE2_TEP_M 0x0000000F // Target Endpoint Number.
+#define USB_TXTYPE2_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL2
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL2_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL2_NAKLMT_M \
+ 0x000000FF // NAK Limit.
+#define USB_TXINTERVAL2_NAKLMT_S \
+ 0
+#define USB_TXINTERVAL2_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE2 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE2_SPEED_M 0x000000C0 // Operating Speed.
+#define USB_RXTYPE2_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE2_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE2_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE2_PROTO_M 0x00000030 // Protocol.
+#define USB_RXTYPE2_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE2_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE2_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE2_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE2_TEP_M 0x0000000F // Target Endpoint Number.
+#define USB_RXTYPE2_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL2
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL2_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL2_NAKLMT_M \
+ 0x000000FF // NAK Limit.
+#define USB_RXINTERVAL2_TXPOLL_S \
+ 0
+#define USB_RXINTERVAL2_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP3 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP3_MULT_M 0x0000F800 // Multiplier.
+#define USB_TXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload.
+#define USB_TXMAXP3_MULT_S 11
+#define USB_TXMAXP3_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL3 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL3_INCTX 0x00000080 // Incomplete Transmit.
+#define USB_TXCSRL3_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL3_CLRDT 0x00000040 // Clear Data Toggle.
+#define USB_TXCSRL3_STALLED 0x00000020 // Endpoint Stalled.
+#define USB_TXCSRL3_SETUP 0x00000010 // Setup Packet.
+#define USB_TXCSRL3_STALL 0x00000010 // Send Stall.
+#define USB_TXCSRL3_FLUSH 0x00000008 // Flush FIFO.
+#define USB_TXCSRL3_ERROR 0x00000004 // Error.
+#define USB_TXCSRL3_UNDRN 0x00000004 // Underrun.
+#define USB_TXCSRL3_FIFONE 0x00000002 // FIFO Not Empty.
+#define USB_TXCSRL3_TXRDY 0x00000001 // Transmit Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH3 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH3_AUTOSET 0x00000080 // Auto Set.
+#define USB_TXCSRH3_ISO 0x00000040 // ISO.
+#define USB_TXCSRH3_MODE 0x00000020 // Mode.
+#define USB_TXCSRH3_DMAEN 0x00000010 // DMA Request Enable.
+#define USB_TXCSRH3_FDT 0x00000008 // Force Data Toggle.
+#define USB_TXCSRH3_DMAMOD 0x00000004 // DMA Request Mode.
+#define USB_TXCSRH3_DTWE 0x00000002 // Data Toggle Write Enable.
+#define USB_TXCSRH3_DT 0x00000001 // Data Toggle.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP3 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP3_MULT_M 0x0000F800 // Multiplier.
+#define USB_RXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload.
+#define USB_RXMAXP3_MULT_S 11
+#define USB_RXMAXP3_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL3 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL3_CLRDT 0x00000080 // Clear Data Toggle.
+#define USB_RXCSRL3_STALLED 0x00000040 // Endpoint Stalled.
+#define USB_RXCSRL3_STALL 0x00000020 // Send Stall.
+#define USB_RXCSRL3_REQPKT 0x00000020 // Request Packet.
+#define USB_RXCSRL3_FLUSH 0x00000010 // Flush FIFO.
+#define USB_RXCSRL3_DATAERR 0x00000008 // Data Error.
+#define USB_RXCSRL3_NAKTO 0x00000008 // NAK Timeout.
+#define USB_RXCSRL3_ERROR 0x00000004 // Error.
+#define USB_RXCSRL3_OVER 0x00000004 // Overrun.
+#define USB_RXCSRL3_FULL 0x00000002 // FIFO Full.
+#define USB_RXCSRL3_RXRDY 0x00000001 // Receive Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH3 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH3_AUTOCL 0x00000080 // Auto Clear.
+#define USB_RXCSRH3_AUTORQ 0x00000040 // Auto Request.
+#define USB_RXCSRH3_ISO 0x00000040 // ISO.
+#define USB_RXCSRH3_DMAEN 0x00000020 // DMA Request Enable.
+#define USB_RXCSRH3_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH3_PIDERR 0x00000010 // PID Error.
+#define USB_RXCSRH3_DMAMOD 0x00000008 // DMA Request Mode.
+#define USB_RXCSRH3_DTWE 0x00000004 // Data Toggle Write Enable.
+#define USB_RXCSRH3_DT 0x00000002 // Data Toggle.
+#define USB_RXCSRH3_INCRX 0x00000001 // Incomplete Receive.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT3 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT3_COUNT_M 0x00001FFF // Receive Packet Count.
+#define USB_RXCOUNT3_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE3 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE3_SPEED_M 0x000000C0 // Operating Speed.
+#define USB_TXTYPE3_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE3_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE3_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE3_PROTO_M 0x00000030 // Protocol.
+#define USB_TXTYPE3_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE3_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE3_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE3_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE3_TEP_M 0x0000000F // Target Endpoint Number.
+#define USB_TXTYPE3_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL3
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL3_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL3_NAKLMT_M \
+ 0x000000FF // NAK Limit.
+#define USB_TXINTERVAL3_TXPOLL_S \
+ 0
+#define USB_TXINTERVAL3_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE3 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE3_SPEED_M 0x000000C0 // Operating Speed.
+#define USB_RXTYPE3_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE3_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE3_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE3_PROTO_M 0x00000030 // Protocol.
+#define USB_RXTYPE3_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE3_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE3_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE3_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE3_TEP_M 0x0000000F // Target Endpoint Number.
+#define USB_RXTYPE3_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL3
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL3_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL3_NAKLMT_M \
+ 0x000000FF // NAK Limit.
+#define USB_RXINTERVAL3_TXPOLL_S \
+ 0
+#define USB_RXINTERVAL3_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT1
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT1_M 0x0000FFFF // Block Transfer Packet Count.
+#define USB_RQPKTCOUNT1_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT2
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT2_M 0x0000FFFF // Block Transfer Packet Count.
+#define USB_RQPKTCOUNT2_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT3
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT3_M 0x0000FFFF // Block Transfer Packet Count.
+#define USB_RQPKTCOUNT3_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXDPKTBUFDIS
+// register.
+//
+//*****************************************************************************
+#define USB_RXDPKTBUFDIS_EP15 0x00008000 // EP15 RX Double-Packet Buffer
+ // Disable.
+#define USB_RXDPKTBUFDIS_EP14 0x00004000 // EP14 RX Double-Packet Buffer
+ // Disable.
+#define USB_RXDPKTBUFDIS_EP13 0x00002000 // EP13 RX Double-Packet Buffer
+ // Disable.
+#define USB_RXDPKTBUFDIS_EP12 0x00001000 // EP12 RX Double-Packet Buffer
+ // Disable.
+#define USB_RXDPKTBUFDIS_EP11 0x00000800 // EP11 RX Double-Packet Buffer
+ // Disable.
+#define USB_RXDPKTBUFDIS_EP10 0x00000400 // EP10 RX Double-Packet Buffer
+ // Disable.
+#define USB_RXDPKTBUFDIS_EP9 0x00000200 // EP9 RX Double-Packet Buffer
+ // Disable.
+#define USB_RXDPKTBUFDIS_EP8 0x00000100 // EP8 RX Double-Packet Buffer
+ // Disable.
+#define USB_RXDPKTBUFDIS_EP7 0x00000080 // EP7 RX Double-Packet Buffer
+ // Disable.
+#define USB_RXDPKTBUFDIS_EP6 0x00000040 // EP6 RX Double-Packet Buffer
+ // Disable.
+#define USB_RXDPKTBUFDIS_EP5 0x00000020 // EP5 RX Double-Packet Buffer
+ // Disable.
+#define USB_RXDPKTBUFDIS_EP4 0x00000010 // EP4 RX Double-Packet Buffer
+ // Disable.
+#define USB_RXDPKTBUFDIS_EP3 0x00000008 // EP3 RX Double-Packet Buffer
+ // Disable.
+#define USB_RXDPKTBUFDIS_EP2 0x00000004 // EP2 RX Double-Packet Buffer
+ // Disable.
+#define USB_RXDPKTBUFDIS_EP1 0x00000002 // EP1 RX Double-Packet Buffer
+ // Disable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXDPKTBUFDIS
+// register.
+//
+//*****************************************************************************
+#define USB_TXDPKTBUFDIS_EP15 0x00008000 // EP15 TX Double-Packet Buffer
+ // Disable.
+#define USB_TXDPKTBUFDIS_EP14 0x00004000 // EP14 TX Double-Packet Buffer
+ // Disable.
+#define USB_TXDPKTBUFDIS_EP13 0x00002000 // EP13 TX Double-Packet Buffer
+ // Disable.
+#define USB_TXDPKTBUFDIS_EP12 0x00001000 // EP12 TX Double-Packet Buffer
+ // Disable.
+#define USB_TXDPKTBUFDIS_EP11 0x00000800 // EP11 TX Double-Packet Buffer
+ // Disable.
+#define USB_TXDPKTBUFDIS_EP10 0x00000400 // EP10 TX Double-Packet Buffer
+ // Disable.
+#define USB_TXDPKTBUFDIS_EP9 0x00000200 // EP9 TX Double-Packet Buffer
+ // Disable.
+#define USB_TXDPKTBUFDIS_EP8 0x00000100 // EP8 TX Double-Packet Buffer
+ // Disable.
+#define USB_TXDPKTBUFDIS_EP7 0x00000080 // EP7 TX Double-Packet Buffer
+ // Disable.
+#define USB_TXDPKTBUFDIS_EP6 0x00000040 // EP6 TX Double-Packet Buffer
+ // Disable.
+#define USB_TXDPKTBUFDIS_EP5 0x00000020 // EP5 TX Double-Packet Buffer
+ // Disable.
+#define USB_TXDPKTBUFDIS_EP4 0x00000010 // EP4 TX Double-Packet Buffer
+ // Disable.
+#define USB_TXDPKTBUFDIS_EP3 0x00000008 // EP3 TX Double-Packet Buffer
+ // Disable.
+#define USB_TXDPKTBUFDIS_EP2 0x00000004 // EP2 TX Double-Packet Buffer
+ // Disable.
+#define USB_TXDPKTBUFDIS_EP1 0x00000002 // EP1 TX Double-Packet Buffer
+ // Disable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPC register.
+//
+//*****************************************************************************
+#define USB_EPC_PFLTACT_M 0x00000300 // Power Fault Action.
+#define USB_EPC_PFLTACT_UNCHG 0x00000000 // Unchanged
+#define USB_EPC_PFLTACT_TRIS 0x00000100 // Tristate
+#define USB_EPC_PFLTACT_LOW 0x00000200 // Low
+#define USB_EPC_PFLTACT_HIGH 0x00000300 // High
+#define USB_EPC_PFLTAEN 0x00000040 // Power Fault Action Enable.
+#define USB_EPC_PFLTSEN_HIGH 0x00000020 // Power Fault Sense.
+#define USB_EPC_PFLTEN 0x00000010 // Power Fault Input Enable.
+#define USB_EPC_EPENDE 0x00000004 // EPEN Drive Enable.
+#define USB_EPC_EPEN_M 0x00000003 // External Power Supply Enable
+ // Configuration.
+#define USB_EPC_EPEN_LOW 0x00000000 // Power Enable Active Low
+#define USB_EPC_EPEN_HIGH 0x00000001 // Power Enable Active High
+#define USB_EPC_EPEN_VBLOW 0x00000002 // Power Enable High if VBUS Low
+#define USB_EPC_EPEN_VBHIGH 0x00000003 // Power Enable High if VBUS High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPCRIS register.
+//
+//*****************************************************************************
+#define USB_EPCRIS_PF 0x00000001 // USB Power Fault Interrupt
+ // Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPCIM register.
+//
+//*****************************************************************************
+#define USB_EPCIM_PF 0x00000001 // USB Power Fault Interrupt Mask.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPCISC register.
+//
+//*****************************************************************************
+#define USB_EPCISC_PF 0x00000001 // USB Power Fault Interrupt Status
+ // and Clear.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DRRIS register.
+//
+//*****************************************************************************
+#define USB_DRRIS_RESUME 0x00000001 // Resume Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DRIM register.
+//
+//*****************************************************************************
+#define USB_DRIM_RESUME 0x00000001 // Resume Interrupt Mask.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DRISC register.
+//
+//*****************************************************************************
+#define USB_DRISC_RESUME 0x00000001 // Resume Interrupt Status and
+ // Clear.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_GPCS register.
+//
+//*****************************************************************************
+#define USB_GPCS_DEVMOD 0x00000001 // Device Mode.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VPLEN register.
+//
+//*****************************************************************************
+#define USB_VPLEN_VPLEN_M 0x000000FF // VBus Pulse Length.
+#define USB_VPLEN_VPLEN_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VDC register.
+//
+//*****************************************************************************
+#define USB_VDC_VBDEN 0x00000001 // VBUS Droop Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VDCRIS register.
+//
+//*****************************************************************************
+#define USB_VDCRIS_VD 0x00000001 // VBUS Droop Raw Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VDCIM register.
+//
+//*****************************************************************************
+#define USB_VDCIM_VD 0x00000001 // VBUS Droop Interrupt Mask.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VDCISC register.
+//
+//*****************************************************************************
+#define USB_VDCISC_VD 0x00000001 // VBUS Droop Interrupt Status and
+ // Clear.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IDVRIS register.
+//
+//*****************************************************************************
+#define USB_IDVRIS_ID 0x00000001 // ID Valid Detect Raw Interrupt
+ // Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IDVIM register.
+//
+//*****************************************************************************
+#define USB_IDVIM_ID 0x00000001 // ID Valid Detect Interrupt Mask.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IDVISC register.
+//
+//*****************************************************************************
+#define USB_IDVISC_ID 0x00000001 // ID Valid Detect Interrupt Status
+ // and Clear.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO4 register.
+//
+//*****************************************************************************
+#define USB_FIFO4_EPDATA_M 0xFFFFFFFF // Endpoint Data.
+#define USB_FIFO4_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO5 register.
+//
+//*****************************************************************************
+#define USB_FIFO5_EPDATA_M 0xFFFFFFFF // Endpoint Data.
+#define USB_FIFO5_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO6 register.
+//
+//*****************************************************************************
+#define USB_FIFO6_EPDATA_M 0xFFFFFFFF // Endpoint Data.
+#define USB_FIFO6_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO7 register.
+//
+//*****************************************************************************
+#define USB_FIFO7_EPDATA_M 0xFFFFFFFF // Endpoint Data.
+#define USB_FIFO7_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO8 register.
+//
+//*****************************************************************************
+#define USB_FIFO8_EPDATA_M 0xFFFFFFFF // Endpoint Data.
+#define USB_FIFO8_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO9 register.
+//
+//*****************************************************************************
+#define USB_FIFO9_EPDATA_M 0xFFFFFFFF // Endpoint Data.
+#define USB_FIFO9_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO10 register.
+//
+//*****************************************************************************
+#define USB_FIFO10_EPDATA_M 0xFFFFFFFF // Endpoint Data.
+#define USB_FIFO10_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO11 register.
+//
+//*****************************************************************************
+#define USB_FIFO11_EPDATA_M 0xFFFFFFFF // Endpoint Data.
+#define USB_FIFO11_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO12 register.
+//
+//*****************************************************************************
+#define USB_FIFO12_EPDATA_M 0xFFFFFFFF // Endpoint Data.
+#define USB_FIFO12_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO13 register.
+//
+//*****************************************************************************
+#define USB_FIFO13_EPDATA_M 0xFFFFFFFF // Endpoint Data.
+#define USB_FIFO13_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO14 register.
+//
+//*****************************************************************************
+#define USB_FIFO14_EPDATA_M 0xFFFFFFFF // Endpoint Data.
+#define USB_FIFO14_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO15 register.
+//
+//*****************************************************************************
+#define USB_FIFO15_EPDATA_M 0xFFFFFFFF // Endpoint Data.
+#define USB_FIFO15_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR4
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR4_ADDR_M 0x0000007F // Device Address.
+#define USB_TXFUNCADDR4_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR4
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR4_MULTTRAN 0x00000080 // Multiple Translators.
+#define USB_TXHUBADDR4_ADDR_M 0x0000007F // Hub Address.
+#define USB_TXHUBADDR4_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT4
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT4_PORT_M 0x0000007F // Hub Port.
+#define USB_TXHUBPORT4_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR4
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR4_ADDR_M 0x0000007F // Device Address.
+#define USB_RXFUNCADDR4_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR4
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR4_MULTTRAN 0x00000080 // Multiple Translators.
+#define USB_RXHUBADDR4_ADDR_M 0x0000007F // Hub Address.
+#define USB_RXHUBADDR4_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT4
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT4_PORT_M 0x0000007F // Hub Port.
+#define USB_RXHUBPORT4_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR5
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR5_ADDR_M 0x0000007F // Device Address.
+#define USB_TXFUNCADDR5_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR5
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR5_MULTTRAN 0x00000080 // Multiple Translators.
+#define USB_TXHUBADDR5_ADDR_M 0x0000007F // Hub Address.
+#define USB_TXHUBADDR5_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT5
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT5_PORT_M 0x0000007F // Hub Port.
+#define USB_TXHUBPORT5_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR5
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR5_ADDR_M 0x0000007F // Device Address.
+#define USB_RXFUNCADDR5_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR5
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR5_MULTTRAN 0x00000080 // Multiple Translators.
+#define USB_RXHUBADDR5_ADDR_M 0x0000007F // Hub Address.
+#define USB_RXHUBADDR5_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT5
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT5_PORT_M 0x0000007F // Hub Port.
+#define USB_RXHUBPORT5_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR6
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR6_ADDR_M 0x0000007F // Device Address.
+#define USB_TXFUNCADDR6_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR6
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR6_MULTTRAN 0x00000080 // Multiple Translators.
+#define USB_TXHUBADDR6_ADDR_M 0x0000007F // Hub Address.
+#define USB_TXHUBADDR6_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT6
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT6_PORT_M 0x0000007F // Hub Port.
+#define USB_TXHUBPORT6_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR6
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR6_ADDR_M 0x0000007F // Device Address.
+#define USB_RXFUNCADDR6_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR6
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR6_MULTTRAN 0x00000080 // Multiple Translators.
+#define USB_RXHUBADDR6_ADDR_M 0x0000007F // Hub Address.
+#define USB_RXHUBADDR6_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT6
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT6_PORT_M 0x0000007F // Hub Port.
+#define USB_RXHUBPORT6_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR7
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR7_ADDR_M 0x0000007F // Device Address.
+#define USB_TXFUNCADDR7_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR7
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR7_MULTTRAN 0x00000080 // Multiple Translators.
+#define USB_TXHUBADDR7_ADDR_M 0x0000007F // Hub Address.
+#define USB_TXHUBADDR7_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT7
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT7_PORT_M 0x0000007F // Hub Port.
+#define USB_TXHUBPORT7_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR7
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR7_ADDR_M 0x0000007F // Device Address.
+#define USB_RXFUNCADDR7_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR7
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR7_MULTTRAN 0x00000080 // Multiple Translators.
+#define USB_RXHUBADDR7_ADDR_M 0x0000007F // Hub Address.
+#define USB_RXHUBADDR7_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT7
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT7_PORT_M 0x0000007F // Hub Port.
+#define USB_RXHUBPORT7_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR8
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR8_ADDR_M 0x0000007F // Device Address.
+#define USB_TXFUNCADDR8_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR8
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR8_MULTTRAN 0x00000080 // Multiple Translators.
+#define USB_TXHUBADDR8_ADDR_M 0x0000007F // Hub Address.
+#define USB_TXHUBADDR8_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT8
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT8_PORT_M 0x0000007F // Hub Port.
+#define USB_TXHUBPORT8_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR8
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR8_ADDR_M 0x0000007F // Device Address.
+#define USB_RXFUNCADDR8_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR8
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR8_MULTTRAN 0x00000080 // Multiple Translators.
+#define USB_RXHUBADDR8_ADDR_M 0x0000007F // Hub Address.
+#define USB_RXHUBADDR8_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT8
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT8_PORT_M 0x0000007F // Hub Port.
+#define USB_RXHUBPORT8_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR9
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR9_ADDR_M 0x0000007F // Device Address.
+#define USB_TXFUNCADDR9_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR9
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR9_MULTTRAN 0x00000080 // Multiple Translators.
+#define USB_TXHUBADDR9_ADDR_M 0x0000007F // Hub Address.
+#define USB_TXHUBADDR9_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT9
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT9_PORT_M 0x0000007F // Hub Port.
+#define USB_TXHUBPORT9_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR9
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR9_ADDR_M 0x0000007F // Device Address.
+#define USB_RXFUNCADDR9_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR9
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR9_MULTTRAN 0x00000080 // Multiple Translators.
+#define USB_RXHUBADDR9_ADDR_M 0x0000007F // Hub Address.
+#define USB_RXHUBADDR9_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT9
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT9_PORT_M 0x0000007F // Hub Port.
+#define USB_RXHUBPORT9_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR10
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR10_ADDR_M 0x0000007F // Device Address.
+#define USB_TXFUNCADDR10_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR10
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR10_MULTTRAN \
+ 0x00000080 // Multiple Translators.
+#define USB_TXHUBADDR10_ADDR_M 0x0000007F // Hub Address.
+#define USB_TXHUBADDR10_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT10
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT10_PORT_M 0x0000007F // Hub Port.
+#define USB_TXHUBPORT10_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR10
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR10_ADDR_M 0x0000007F // Device Address.
+#define USB_RXFUNCADDR10_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR10
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR10_MULTTRAN \
+ 0x00000080 // Multiple Translators.
+#define USB_RXHUBADDR10_ADDR_M 0x0000007F // Hub Address.
+#define USB_RXHUBADDR10_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT10
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT10_PORT_M 0x0000007F // Hub Port.
+#define USB_RXHUBPORT10_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR11
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR11_ADDR_M 0x0000007F // Device Address.
+#define USB_TXFUNCADDR11_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR11
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR11_MULTTRAN \
+ 0x00000080 // Multiple Translators.
+#define USB_TXHUBADDR11_ADDR_M 0x0000007F // Hub Address.
+#define USB_TXHUBADDR11_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT11
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT11_PORT_M 0x0000007F // Hub Port.
+#define USB_TXHUBPORT11_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR11
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR11_ADDR_M 0x0000007F // Device Address.
+#define USB_RXFUNCADDR11_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR11
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR11_MULTTRAN \
+ 0x00000080 // Multiple Translators.
+#define USB_RXHUBADDR11_ADDR_M 0x0000007F // Hub Address.
+#define USB_RXHUBADDR11_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT11
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT11_PORT_M 0x0000007F // Hub Port.
+#define USB_RXHUBPORT11_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR12
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR12_ADDR_M 0x0000007F // Device Address.
+#define USB_TXFUNCADDR12_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR12
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR12_MULTTRAN \
+ 0x00000080 // Multiple Translators.
+#define USB_TXHUBADDR12_ADDR_M 0x0000007F // Hub Address.
+#define USB_TXHUBADDR12_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT12
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT12_PORT_M 0x0000007F // Hub Port.
+#define USB_TXHUBPORT12_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR12
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR12_ADDR_M 0x0000007F // Device Address.
+#define USB_RXFUNCADDR12_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR12
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR12_MULTTRAN \
+ 0x00000080 // Multiple Translators.
+#define USB_RXHUBADDR12_ADDR_M 0x0000007F // Hub Address.
+#define USB_RXHUBADDR12_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT12
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT12_PORT_M 0x0000007F // Hub Port.
+#define USB_RXHUBPORT12_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR13
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR13_ADDR_M 0x0000007F // Device Address.
+#define USB_TXFUNCADDR13_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR13
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR13_MULTTRAN \
+ 0x00000080 // Multiple Translators.
+#define USB_TXHUBADDR13_ADDR_M 0x0000007F // Hub Address.
+#define USB_TXHUBADDR13_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT13
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT13_PORT_M 0x0000007F // Hub Port.
+#define USB_TXHUBPORT13_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR13
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR13_ADDR_M 0x0000007F // Device Address.
+#define USB_RXFUNCADDR13_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR13
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR13_MULTTRAN \
+ 0x00000080 // Multiple Translators.
+#define USB_RXHUBADDR13_ADDR_M 0x0000007F // Hub Address.
+#define USB_RXHUBADDR13_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT13
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT13_PORT_M 0x0000007F // Hub Port.
+#define USB_RXHUBPORT13_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR14
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR14_ADDR_M 0x0000007F // Device Address.
+#define USB_TXFUNCADDR14_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR14
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR14_MULTTRAN \
+ 0x00000080 // Multiple Translators.
+#define USB_TXHUBADDR14_ADDR_M 0x0000007F // Hub Address.
+#define USB_TXHUBADDR14_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT14
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT14_PORT_M 0x0000007F // Hub Port.
+#define USB_TXHUBPORT14_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR14
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR14_ADDR_M 0x0000007F // Device Address.
+#define USB_RXFUNCADDR14_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR14
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR14_MULTTRAN \
+ 0x00000080 // Multiple Translators.
+#define USB_RXHUBADDR14_ADDR_M 0x0000007F // Hub Address.
+#define USB_RXHUBADDR14_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT14
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT14_PORT_M 0x0000007F // Hub Port.
+#define USB_RXHUBPORT14_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR15
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR15_ADDR_M 0x0000007F // Device Address.
+#define USB_TXFUNCADDR15_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR15
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR15_MULTTRAN \
+ 0x00000080 // Multiple Translators.
+#define USB_TXHUBADDR15_ADDR_M 0x0000007F // Hub Address.
+#define USB_TXHUBADDR15_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT15
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT15_PORT_M 0x0000007F // Hub Port.
+#define USB_TXHUBPORT15_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR15
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR15_ADDR_M 0x0000007F // Device Address.
+#define USB_RXFUNCADDR15_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR15
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR15_MULTTRAN \
+ 0x00000080 // Multiple Translators.
+#define USB_RXHUBADDR15_ADDR_M 0x0000007F // Hub Address.
+#define USB_RXHUBADDR15_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT15
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT15_PORT_M 0x0000007F // Hub Port.
+#define USB_RXHUBPORT15_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP4 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload.
+#define USB_TXMAXP4_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL4 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL4_INCTX 0x00000080 // Incomplete Transmit.
+#define USB_TXCSRL4_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL4_CLRDT 0x00000040 // Clear Data Toggle.
+#define USB_TXCSRL4_STALLED 0x00000020 // Endpoint Stalled.
+#define USB_TXCSRL4_SETUP 0x00000010 // Setup Packet.
+#define USB_TXCSRL4_STALL 0x00000010 // Send Stall.
+#define USB_TXCSRL4_FLUSH 0x00000008 // Flush FIFO.
+#define USB_TXCSRL4_ERROR 0x00000004 // Error.
+#define USB_TXCSRL4_UNDRN 0x00000004 // Underrun.
+#define USB_TXCSRL4_FIFONE 0x00000002 // FIFO Not Empty.
+#define USB_TXCSRL4_TXRDY 0x00000001 // Transmit Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH4 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH4_AUTOSET 0x00000080 // Auto Set.
+#define USB_TXCSRH4_ISO 0x00000040 // ISO.
+#define USB_TXCSRH4_MODE 0x00000020 // Mode.
+#define USB_TXCSRH4_DMAEN 0x00000010 // DMA Request Enable.
+#define USB_TXCSRH4_FDT 0x00000008 // Force Data Toggle.
+#define USB_TXCSRH4_DMAMOD 0x00000004 // DMA Request Mode.
+#define USB_TXCSRH4_DTWE 0x00000002 // Data Toggle Write Enable.
+#define USB_TXCSRH4_DT 0x00000001 // Data Toggle.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP4 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload.
+#define USB_RXMAXP4_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL4 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL4_CLRDT 0x00000080 // Clear Data Toggle.
+#define USB_RXCSRL4_STALLED 0x00000040 // Endpoint Stalled.
+#define USB_RXCSRL4_STALL 0x00000020 // Send Stall.
+#define USB_RXCSRL4_REQPKT 0x00000020 // Request Packet.
+#define USB_RXCSRL4_FLUSH 0x00000010 // Flush FIFO.
+#define USB_RXCSRL4_NAKTO 0x00000008 // NAK Timeout.
+#define USB_RXCSRL4_DATAERR 0x00000008 // Data Error.
+#define USB_RXCSRL4_OVER 0x00000004 // Overrun.
+#define USB_RXCSRL4_ERROR 0x00000004 // Error.
+#define USB_RXCSRL4_FULL 0x00000002 // FIFO Full.
+#define USB_RXCSRL4_RXRDY 0x00000001 // Receive Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH4 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH4_AUTOCL 0x00000080 // Auto Clear.
+#define USB_RXCSRH4_AUTORQ 0x00000040 // Auto Request.
+#define USB_RXCSRH4_ISO 0x00000040 // ISO.
+#define USB_RXCSRH4_DMAEN 0x00000020 // DMA Request Enable.
+#define USB_RXCSRH4_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH4_PIDERR 0x00000010 // PID Error.
+#define USB_RXCSRH4_DMAMOD 0x00000008 // DMA Request Mode.
+#define USB_RXCSRH4_DTWE 0x00000004 // Data Toggle Write Enable.
+#define USB_RXCSRH4_DT 0x00000002 // Data Toggle.
+#define USB_RXCSRH4_INCRX 0x00000001 // Incomplete Receive.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT4 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT4_COUNT_M 0x00001FFF // Receive Packet Count.
+#define USB_RXCOUNT4_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE4 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE4_SPEED_M 0x000000C0 // Operating Speed.
+#define USB_TXTYPE4_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE4_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE4_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE4_PROTO_M 0x00000030 // Protocol.
+#define USB_TXTYPE4_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE4_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE4_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE4_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE4_TEP_M 0x0000000F // Target Endpoint Number.
+#define USB_TXTYPE4_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL4
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL4_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL4_NAKLMT_M \
+ 0x000000FF // NAK Limit.
+#define USB_TXINTERVAL4_NAKLMT_S \
+ 0
+#define USB_TXINTERVAL4_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE4 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE4_SPEED_M 0x000000C0 // Operating Speed.
+#define USB_RXTYPE4_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE4_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE4_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE4_PROTO_M 0x00000030 // Protocol.
+#define USB_RXTYPE4_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE4_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE4_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE4_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE4_TEP_M 0x0000000F // Target Endpoint Number.
+#define USB_RXTYPE4_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL4
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL4_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL4_NAKLMT_M \
+ 0x000000FF // NAK Limit.
+#define USB_RXINTERVAL4_NAKLMT_S \
+ 0
+#define USB_RXINTERVAL4_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP5 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload.
+#define USB_TXMAXP5_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL5 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL5_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL5_INCTX 0x00000080 // Incomplete Transmit.
+#define USB_TXCSRL5_CLRDT 0x00000040 // Clear Data Toggle.
+#define USB_TXCSRL5_STALLED 0x00000020 // Endpoint Stalled.
+#define USB_TXCSRL5_SETUP 0x00000010 // Setup Packet.
+#define USB_TXCSRL5_STALL 0x00000010 // Send Stall.
+#define USB_TXCSRL5_FLUSH 0x00000008 // Flush FIFO.
+#define USB_TXCSRL5_ERROR 0x00000004 // Error.
+#define USB_TXCSRL5_UNDRN 0x00000004 // Underrun.
+#define USB_TXCSRL5_FIFONE 0x00000002 // FIFO Not Empty.
+#define USB_TXCSRL5_TXRDY 0x00000001 // Transmit Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH5 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH5_AUTOSET 0x00000080 // Auto Set.
+#define USB_TXCSRH5_ISO 0x00000040 // ISO.
+#define USB_TXCSRH5_MODE 0x00000020 // Mode.
+#define USB_TXCSRH5_DMAEN 0x00000010 // DMA Request Enable.
+#define USB_TXCSRH5_FDT 0x00000008 // Force Data Toggle.
+#define USB_TXCSRH5_DMAMOD 0x00000004 // DMA Request Mode.
+#define USB_TXCSRH5_DTWE 0x00000002 // Data Toggle Write Enable.
+#define USB_TXCSRH5_DT 0x00000001 // Data Toggle.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP5 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload.
+#define USB_RXMAXP5_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL5 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL5_CLRDT 0x00000080 // Clear Data Toggle.
+#define USB_RXCSRL5_STALLED 0x00000040 // Endpoint Stalled.
+#define USB_RXCSRL5_STALL 0x00000020 // Send Stall.
+#define USB_RXCSRL5_REQPKT 0x00000020 // Request Packet.
+#define USB_RXCSRL5_FLUSH 0x00000010 // Flush FIFO.
+#define USB_RXCSRL5_NAKTO 0x00000008 // NAK Timeout.
+#define USB_RXCSRL5_DATAERR 0x00000008 // Data Error.
+#define USB_RXCSRL5_ERROR 0x00000004 // Error.
+#define USB_RXCSRL5_OVER 0x00000004 // Overrun.
+#define USB_RXCSRL5_FULL 0x00000002 // FIFO Full.
+#define USB_RXCSRL5_RXRDY 0x00000001 // Receive Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH5 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH5_AUTOCL 0x00000080 // Auto Clear.
+#define USB_RXCSRH5_AUTORQ 0x00000040 // Auto Request.
+#define USB_RXCSRH5_ISO 0x00000040 // ISO.
+#define USB_RXCSRH5_DMAEN 0x00000020 // DMA Request Enable.
+#define USB_RXCSRH5_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH5_PIDERR 0x00000010 // PID Error.
+#define USB_RXCSRH5_DMAMOD 0x00000008 // DMA Request Mode.
+#define USB_RXCSRH5_DTWE 0x00000004 // Data Toggle Write Enable.
+#define USB_RXCSRH5_DT 0x00000002 // Data Toggle.
+#define USB_RXCSRH5_INCRX 0x00000001 // Incomplete Receive.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT5 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT5_COUNT_M 0x00001FFF // Receive Packet Count.
+#define USB_RXCOUNT5_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE5 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE5_SPEED_M 0x000000C0 // Operating Speed.
+#define USB_TXTYPE5_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE5_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE5_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE5_PROTO_M 0x00000030 // Protocol.
+#define USB_TXTYPE5_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE5_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE5_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE5_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE5_TEP_M 0x0000000F // Target Endpoint Number.
+#define USB_TXTYPE5_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL5
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL5_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL5_NAKLMT_M \
+ 0x000000FF // NAK Limit.
+#define USB_TXINTERVAL5_NAKLMT_S \
+ 0
+#define USB_TXINTERVAL5_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE5 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE5_SPEED_M 0x000000C0 // Operating Speed.
+#define USB_RXTYPE5_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE5_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE5_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE5_PROTO_M 0x00000030 // Protocol.
+#define USB_RXTYPE5_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE5_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE5_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE5_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE5_TEP_M 0x0000000F // Target Endpoint Number.
+#define USB_RXTYPE5_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL5
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL5_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL5_NAKLMT_M \
+ 0x000000FF // NAK Limit.
+#define USB_RXINTERVAL5_TXPOLL_S \
+ 0
+#define USB_RXINTERVAL5_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP6 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload.
+#define USB_TXMAXP6_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL6 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL6_INCTX 0x00000080 // Incomplete Transmit.
+#define USB_TXCSRL6_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL6_CLRDT 0x00000040 // Clear Data Toggle.
+#define USB_TXCSRL6_STALLED 0x00000020 // Endpoint Stalled.
+#define USB_TXCSRL6_STALL 0x00000010 // Send Stall.
+#define USB_TXCSRL6_SETUP 0x00000010 // Setup Packet.
+#define USB_TXCSRL6_FLUSH 0x00000008 // Flush FIFO.
+#define USB_TXCSRL6_ERROR 0x00000004 // Error.
+#define USB_TXCSRL6_UNDRN 0x00000004 // Underrun.
+#define USB_TXCSRL6_FIFONE 0x00000002 // FIFO Not Empty.
+#define USB_TXCSRL6_TXRDY 0x00000001 // Transmit Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH6 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH6_AUTOSET 0x00000080 // Auto Set.
+#define USB_TXCSRH6_ISO 0x00000040 // ISO.
+#define USB_TXCSRH6_MODE 0x00000020 // Mode.
+#define USB_TXCSRH6_DMAEN 0x00000010 // DMA Request Enable.
+#define USB_TXCSRH6_FDT 0x00000008 // Force Data Toggle.
+#define USB_TXCSRH6_DMAMOD 0x00000004 // DMA Request Mode.
+#define USB_TXCSRH6_DTWE 0x00000002 // Data Toggle Write Enable.
+#define USB_TXCSRH6_DT 0x00000001 // Data Toggle.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP6 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload.
+#define USB_RXMAXP6_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL6 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL6_CLRDT 0x00000080 // Clear Data Toggle.
+#define USB_RXCSRL6_STALLED 0x00000040 // Endpoint Stalled.
+#define USB_RXCSRL6_REQPKT 0x00000020 // Request Packet.
+#define USB_RXCSRL6_STALL 0x00000020 // Send Stall.
+#define USB_RXCSRL6_FLUSH 0x00000010 // Flush FIFO.
+#define USB_RXCSRL6_NAKTO 0x00000008 // NAK Timeout.
+#define USB_RXCSRL6_DATAERR 0x00000008 // Data Error.
+#define USB_RXCSRL6_ERROR 0x00000004 // Error.
+#define USB_RXCSRL6_OVER 0x00000004 // Overrun.
+#define USB_RXCSRL6_FULL 0x00000002 // FIFO Full.
+#define USB_RXCSRL6_RXRDY 0x00000001 // Receive Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH6 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH6_AUTOCL 0x00000080 // Auto Clear.
+#define USB_RXCSRH6_AUTORQ 0x00000040 // Auto Request.
+#define USB_RXCSRH6_ISO 0x00000040 // ISO.
+#define USB_RXCSRH6_DMAEN 0x00000020 // DMA Request Enable.
+#define USB_RXCSRH6_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH6_PIDERR 0x00000010 // PID Error.
+#define USB_RXCSRH6_DMAMOD 0x00000008 // DMA Request Mode.
+#define USB_RXCSRH6_DTWE 0x00000004 // Data Toggle Write Enable.
+#define USB_RXCSRH6_DT 0x00000002 // Data Toggle.
+#define USB_RXCSRH6_INCRX 0x00000001 // Incomplete Receive.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT6 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT6_COUNT_M 0x00001FFF // Receive Packet Count.
+#define USB_RXCOUNT6_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE6 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE6_SPEED_M 0x000000C0 // Operating Speed.
+#define USB_TXTYPE6_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE6_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE6_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE6_PROTO_M 0x00000030 // Protocol.
+#define USB_TXTYPE6_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE6_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE6_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE6_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE6_TEP_M 0x0000000F // Target Endpoint Number.
+#define USB_TXTYPE6_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL6
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL6_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL6_NAKLMT_M \
+ 0x000000FF // NAK Limit.
+#define USB_TXINTERVAL6_TXPOLL_S \
+ 0
+#define USB_TXINTERVAL6_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE6 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE6_SPEED_M 0x000000C0 // Operating Speed.
+#define USB_RXTYPE6_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE6_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE6_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE6_PROTO_M 0x00000030 // Protocol.
+#define USB_RXTYPE6_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE6_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE6_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE6_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE6_TEP_M 0x0000000F // Target Endpoint Number.
+#define USB_RXTYPE6_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL6
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL6_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL6_NAKLMT_M \
+ 0x000000FF // NAK Limit.
+#define USB_RXINTERVAL6_NAKLMT_S \
+ 0
+#define USB_RXINTERVAL6_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP7 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload.
+#define USB_TXMAXP7_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL7 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL7_INCTX 0x00000080 // Incomplete Transmit.
+#define USB_TXCSRL7_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL7_CLRDT 0x00000040 // Clear Data Toggle.
+#define USB_TXCSRL7_STALLED 0x00000020 // Endpoint Stalled.
+#define USB_TXCSRL7_STALL 0x00000010 // Send Stall.
+#define USB_TXCSRL7_SETUP 0x00000010 // Setup Packet.
+#define USB_TXCSRL7_FLUSH 0x00000008 // Flush FIFO.
+#define USB_TXCSRL7_ERROR 0x00000004 // Error.
+#define USB_TXCSRL7_UNDRN 0x00000004 // Underrun.
+#define USB_TXCSRL7_FIFONE 0x00000002 // FIFO Not Empty.
+#define USB_TXCSRL7_TXRDY 0x00000001 // Transmit Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH7 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH7_AUTOSET 0x00000080 // Auto Set.
+#define USB_TXCSRH7_ISO 0x00000040 // ISO.
+#define USB_TXCSRH7_MODE 0x00000020 // Mode.
+#define USB_TXCSRH7_DMAEN 0x00000010 // DMA Request Enable.
+#define USB_TXCSRH7_FDT 0x00000008 // Force Data Toggle.
+#define USB_TXCSRH7_DMAMOD 0x00000004 // DMA Request Mode.
+#define USB_TXCSRH7_DTWE 0x00000002 // Data Toggle Write Enable.
+#define USB_TXCSRH7_DT 0x00000001 // Data Toggle.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP7 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload.
+#define USB_RXMAXP7_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL7 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL7_CLRDT 0x00000080 // Clear Data Toggle.
+#define USB_RXCSRL7_STALLED 0x00000040 // Endpoint Stalled.
+#define USB_RXCSRL7_REQPKT 0x00000020 // Request Packet.
+#define USB_RXCSRL7_STALL 0x00000020 // Send Stall.
+#define USB_RXCSRL7_FLUSH 0x00000010 // Flush FIFO.
+#define USB_RXCSRL7_DATAERR 0x00000008 // Data Error.
+#define USB_RXCSRL7_NAKTO 0x00000008 // NAK Timeout.
+#define USB_RXCSRL7_ERROR 0x00000004 // Error.
+#define USB_RXCSRL7_OVER 0x00000004 // Overrun.
+#define USB_RXCSRL7_FULL 0x00000002 // FIFO Full.
+#define USB_RXCSRL7_RXRDY 0x00000001 // Receive Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH7 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH7_AUTOCL 0x00000080 // Auto Clear.
+#define USB_RXCSRH7_ISO 0x00000040 // ISO.
+#define USB_RXCSRH7_AUTORQ 0x00000040 // Auto Request.
+#define USB_RXCSRH7_DMAEN 0x00000020 // DMA Request Enable.
+#define USB_RXCSRH7_PIDERR 0x00000010 // PID Error.
+#define USB_RXCSRH7_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH7_DMAMOD 0x00000008 // DMA Request Mode.
+#define USB_RXCSRH7_DTWE 0x00000004 // Data Toggle Write Enable.
+#define USB_RXCSRH7_DT 0x00000002 // Data Toggle.
+#define USB_RXCSRH7_INCRX 0x00000001 // Incomplete Receive.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT7 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT7_COUNT_M 0x00001FFF // Receive Packet Count.
+#define USB_RXCOUNT7_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE7 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE7_SPEED_M 0x000000C0 // Operating Speed.
+#define USB_TXTYPE7_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE7_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE7_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE7_PROTO_M 0x00000030 // Protocol.
+#define USB_TXTYPE7_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE7_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE7_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE7_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE7_TEP_M 0x0000000F // Target Endpoint Number.
+#define USB_TXTYPE7_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL7
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL7_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL7_NAKLMT_M \
+ 0x000000FF // NAK Limit.
+#define USB_TXINTERVAL7_NAKLMT_S \
+ 0
+#define USB_TXINTERVAL7_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE7 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE7_SPEED_M 0x000000C0 // Operating Speed.
+#define USB_RXTYPE7_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE7_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE7_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE7_PROTO_M 0x00000030 // Protocol.
+#define USB_RXTYPE7_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE7_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE7_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE7_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE7_TEP_M 0x0000000F // Target Endpoint Number.
+#define USB_RXTYPE7_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL7
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL7_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL7_NAKLMT_M \
+ 0x000000FF // NAK Limit.
+#define USB_RXINTERVAL7_NAKLMT_S \
+ 0
+#define USB_RXINTERVAL7_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP8 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP8_MAXLOAD_M 0x000007FF // Maximum Payload.
+#define USB_TXMAXP8_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL8 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL8_INCTX 0x00000080 // Incomplete Transmit.
+#define USB_TXCSRL8_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL8_CLRDT 0x00000040 // Clear Data Toggle.
+#define USB_TXCSRL8_STALLED 0x00000020 // Endpoint Stalled.
+#define USB_TXCSRL8_STALL 0x00000010 // Send Stall.
+#define USB_TXCSRL8_SETUP 0x00000010 // Setup Packet.
+#define USB_TXCSRL8_FLUSH 0x00000008 // Flush FIFO.
+#define USB_TXCSRL8_ERROR 0x00000004 // Error.
+#define USB_TXCSRL8_UNDRN 0x00000004 // Underrun.
+#define USB_TXCSRL8_FIFONE 0x00000002 // FIFO Not Empty.
+#define USB_TXCSRL8_TXRDY 0x00000001 // Transmit Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH8 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH8_AUTOSET 0x00000080 // Auto Set.
+#define USB_TXCSRH8_ISO 0x00000040 // ISO.
+#define USB_TXCSRH8_MODE 0x00000020 // Mode.
+#define USB_TXCSRH8_DMAEN 0x00000010 // DMA Request Enable.
+#define USB_TXCSRH8_FDT 0x00000008 // Force Data Toggle.
+#define USB_TXCSRH8_DMAMOD 0x00000004 // DMA Request Mode.
+#define USB_TXCSRH8_DTWE 0x00000002 // Data Toggle Write Enable.
+#define USB_TXCSRH8_DT 0x00000001 // Data Toggle.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP8 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP8_MAXLOAD_M 0x000007FF // Maximum Payload.
+#define USB_RXMAXP8_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL8 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL8_CLRDT 0x00000080 // Clear Data Toggle.
+#define USB_RXCSRL8_STALLED 0x00000040 // Endpoint Stalled.
+#define USB_RXCSRL8_STALL 0x00000020 // Send Stall.
+#define USB_RXCSRL8_REQPKT 0x00000020 // Request Packet.
+#define USB_RXCSRL8_FLUSH 0x00000010 // Flush FIFO.
+#define USB_RXCSRL8_NAKTO 0x00000008 // NAK Timeout.
+#define USB_RXCSRL8_DATAERR 0x00000008 // Data Error.
+#define USB_RXCSRL8_OVER 0x00000004 // Overrun.
+#define USB_RXCSRL8_ERROR 0x00000004 // Error.
+#define USB_RXCSRL8_FULL 0x00000002 // FIFO Full.
+#define USB_RXCSRL8_RXRDY 0x00000001 // Receive Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH8 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH8_AUTOCL 0x00000080 // Auto Clear.
+#define USB_RXCSRH8_AUTORQ 0x00000040 // Auto Request.
+#define USB_RXCSRH8_ISO 0x00000040 // ISO.
+#define USB_RXCSRH8_DMAEN 0x00000020 // DMA Request Enable.
+#define USB_RXCSRH8_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH8_PIDERR 0x00000010 // PID Error.
+#define USB_RXCSRH8_DMAMOD 0x00000008 // DMA Request Mode.
+#define USB_RXCSRH8_DTWE 0x00000004 // Data Toggle Write Enable.
+#define USB_RXCSRH8_DT 0x00000002 // Data Toggle.
+#define USB_RXCSRH8_INCRX 0x00000001 // Incomplete Receive.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT8 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT8_COUNT_M 0x00001FFF // Receive Packet Count.
+#define USB_RXCOUNT8_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE8 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE8_SPEED_M 0x000000C0 // Operating Speed.
+#define USB_TXTYPE8_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE8_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE8_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE8_PROTO_M 0x00000030 // Protocol.
+#define USB_TXTYPE8_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE8_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE8_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE8_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE8_TEP_M 0x0000000F // Target Endpoint Number.
+#define USB_TXTYPE8_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL8
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL8_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL8_NAKLMT_M \
+ 0x000000FF // NAK Limit.
+#define USB_TXINTERVAL8_NAKLMT_S \
+ 0
+#define USB_TXINTERVAL8_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE8 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE8_SPEED_M 0x000000C0 // Operating Speed.
+#define USB_RXTYPE8_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE8_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE8_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE8_PROTO_M 0x00000030 // Protocol.
+#define USB_RXTYPE8_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE8_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE8_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE8_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE8_TEP_M 0x0000000F // Target Endpoint Number.
+#define USB_RXTYPE8_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL8
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL8_NAKLMT_M \
+ 0x000000FF // NAK Limit.
+#define USB_RXINTERVAL8_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL8_NAKLMT_S \
+ 0
+#define USB_RXINTERVAL8_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP9 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP9_MAXLOAD_M 0x000007FF // Maximum Payload.
+#define USB_TXMAXP9_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL9 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL9_INCTX 0x00000080 // Incomplete Transmit.
+#define USB_TXCSRL9_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL9_CLRDT 0x00000040 // Clear Data Toggle.
+#define USB_TXCSRL9_STALLED 0x00000020 // Endpoint Stalled.
+#define USB_TXCSRL9_SETUP 0x00000010 // Setup Packet.
+#define USB_TXCSRL9_STALL 0x00000010 // Send Stall.
+#define USB_TXCSRL9_FLUSH 0x00000008 // Flush FIFO.
+#define USB_TXCSRL9_ERROR 0x00000004 // Error.
+#define USB_TXCSRL9_UNDRN 0x00000004 // Underrun.
+#define USB_TXCSRL9_FIFONE 0x00000002 // FIFO Not Empty.
+#define USB_TXCSRL9_TXRDY 0x00000001 // Transmit Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH9 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH9_AUTOSET 0x00000080 // Auto Set.
+#define USB_TXCSRH9_ISO 0x00000040 // ISO.
+#define USB_TXCSRH9_MODE 0x00000020 // Mode.
+#define USB_TXCSRH9_DMAEN 0x00000010 // DMA Request Enable.
+#define USB_TXCSRH9_FDT 0x00000008 // Force Data Toggle.
+#define USB_TXCSRH9_DMAMOD 0x00000004 // DMA Request Mode.
+#define USB_TXCSRH9_DTWE 0x00000002 // Data Toggle Write Enable.
+#define USB_TXCSRH9_DT 0x00000001 // Data Toggle.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP9 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP9_MAXLOAD_M 0x000007FF // Maximum Payload.
+#define USB_RXMAXP9_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL9 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL9_CLRDT 0x00000080 // Clear Data Toggle.
+#define USB_RXCSRL9_STALLED 0x00000040 // Endpoint Stalled.
+#define USB_RXCSRL9_STALL 0x00000020 // Send Stall.
+#define USB_RXCSRL9_REQPKT 0x00000020 // Request Packet.
+#define USB_RXCSRL9_FLUSH 0x00000010 // Flush FIFO.
+#define USB_RXCSRL9_DATAERR 0x00000008 // Data Error.
+#define USB_RXCSRL9_NAKTO 0x00000008 // NAK Timeout.
+#define USB_RXCSRL9_ERROR 0x00000004 // Error.
+#define USB_RXCSRL9_OVER 0x00000004 // Overrun.
+#define USB_RXCSRL9_FULL 0x00000002 // FIFO Full.
+#define USB_RXCSRL9_RXRDY 0x00000001 // Receive Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH9 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH9_AUTOCL 0x00000080 // Auto Clear.
+#define USB_RXCSRH9_ISO 0x00000040 // ISO.
+#define USB_RXCSRH9_AUTORQ 0x00000040 // Auto Request.
+#define USB_RXCSRH9_DMAEN 0x00000020 // DMA Request Enable.
+#define USB_RXCSRH9_PIDERR 0x00000010 // PID Error.
+#define USB_RXCSRH9_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH9_DMAMOD 0x00000008 // DMA Request Mode.
+#define USB_RXCSRH9_DTWE 0x00000004 // Data Toggle Write Enable.
+#define USB_RXCSRH9_DT 0x00000002 // Data Toggle.
+#define USB_RXCSRH9_INCRX 0x00000001 // Incomplete Receive.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT9 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT9_COUNT_M 0x00001FFF // Receive Packet Count.
+#define USB_RXCOUNT9_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE9 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE9_SPEED_M 0x000000C0 // Operating Speed.
+#define USB_TXTYPE9_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE9_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE9_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE9_PROTO_M 0x00000030 // Protocol.
+#define USB_TXTYPE9_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE9_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE9_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE9_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE9_TEP_M 0x0000000F // Target Endpoint Number.
+#define USB_TXTYPE9_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL9
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL9_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL9_NAKLMT_M \
+ 0x000000FF // NAK Limit.
+#define USB_TXINTERVAL9_TXPOLL_S \
+ 0
+#define USB_TXINTERVAL9_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE9 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE9_SPEED_M 0x000000C0 // Operating Speed.
+#define USB_RXTYPE9_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE9_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE9_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE9_PROTO_M 0x00000030 // Protocol.
+#define USB_RXTYPE9_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE9_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE9_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE9_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE9_TEP_M 0x0000000F // Target Endpoint Number.
+#define USB_RXTYPE9_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL9
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL9_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL9_NAKLMT_M \
+ 0x000000FF // NAK Limit.
+#define USB_RXINTERVAL9_NAKLMT_S \
+ 0
+#define USB_RXINTERVAL9_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP10 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP10_MAXLOAD_M 0x000007FF // Maximum Payload.
+#define USB_TXMAXP10_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL10 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL10_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL10_INCTX 0x00000080 // Incomplete Transmit.
+#define USB_TXCSRL10_CLRDT 0x00000040 // Clear Data Toggle.
+#define USB_TXCSRL10_STALLED 0x00000020 // Endpoint Stalled.
+#define USB_TXCSRL10_SETUP 0x00000010 // Setup Packet.
+#define USB_TXCSRL10_STALL 0x00000010 // Send Stall.
+#define USB_TXCSRL10_FLUSH 0x00000008 // Flush FIFO.
+#define USB_TXCSRL10_UNDRN 0x00000004 // Underrun.
+#define USB_TXCSRL10_ERROR 0x00000004 // Error.
+#define USB_TXCSRL10_FIFONE 0x00000002 // FIFO Not Empty.
+#define USB_TXCSRL10_TXRDY 0x00000001 // Transmit Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH10 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH10_AUTOSET 0x00000080 // Auto Set.
+#define USB_TXCSRH10_ISO 0x00000040 // ISO.
+#define USB_TXCSRH10_MODE 0x00000020 // Mode.
+#define USB_TXCSRH10_DMAEN 0x00000010 // DMA Request Enable.
+#define USB_TXCSRH10_FDT 0x00000008 // Force Data Toggle.
+#define USB_TXCSRH10_DMAMOD 0x00000004 // DMA Request Mode.
+#define USB_TXCSRH10_DTWE 0x00000002 // Data Toggle Write Enable.
+#define USB_TXCSRH10_DT 0x00000001 // Data Toggle.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP10 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP10_MAXLOAD_M 0x000007FF // Maximum Payload.
+#define USB_RXMAXP10_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL10 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL10_CLRDT 0x00000080 // Clear Data Toggle.
+#define USB_RXCSRL10_STALLED 0x00000040 // Endpoint Stalled.
+#define USB_RXCSRL10_STALL 0x00000020 // Send Stall.
+#define USB_RXCSRL10_REQPKT 0x00000020 // Request Packet.
+#define USB_RXCSRL10_FLUSH 0x00000010 // Flush FIFO.
+#define USB_RXCSRL10_NAKTO 0x00000008 // NAK Timeout.
+#define USB_RXCSRL10_DATAERR 0x00000008 // Data Error.
+#define USB_RXCSRL10_OVER 0x00000004 // Overrun.
+#define USB_RXCSRL10_ERROR 0x00000004 // Error.
+#define USB_RXCSRL10_FULL 0x00000002 // FIFO Full.
+#define USB_RXCSRL10_RXRDY 0x00000001 // Receive Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH10 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH10_AUTOCL 0x00000080 // Auto Clear.
+#define USB_RXCSRH10_AUTORQ 0x00000040 // Auto Request.
+#define USB_RXCSRH10_ISO 0x00000040 // ISO.
+#define USB_RXCSRH10_DMAEN 0x00000020 // DMA Request Enable.
+#define USB_RXCSRH10_PIDERR 0x00000010 // PID Error.
+#define USB_RXCSRH10_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH10_DMAMOD 0x00000008 // DMA Request Mode.
+#define USB_RXCSRH10_DTWE 0x00000004 // Data Toggle Write Enable.
+#define USB_RXCSRH10_DT 0x00000002 // Data Toggle.
+#define USB_RXCSRH10_INCRX 0x00000001 // Incomplete Receive.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT10
+// register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT10_COUNT_M 0x00001FFF // Receive Packet Count.
+#define USB_RXCOUNT10_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE10 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE10_SPEED_M 0x000000C0 // Operating Speed.
+#define USB_TXTYPE10_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE10_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE10_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE10_PROTO_M 0x00000030 // Protocol.
+#define USB_TXTYPE10_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE10_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE10_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE10_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE10_TEP_M 0x0000000F // Target Endpoint Number.
+#define USB_TXTYPE10_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL10
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL10_NAKLMT_M \
+ 0x000000FF // NAK Limit.
+#define USB_TXINTERVAL10_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL10_TXPOLL_S \
+ 0
+#define USB_TXINTERVAL10_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE10 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE10_SPEED_M 0x000000C0 // Operating Speed.
+#define USB_RXTYPE10_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE10_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE10_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE10_PROTO_M 0x00000030 // Protocol.
+#define USB_RXTYPE10_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE10_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE10_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE10_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE10_TEP_M 0x0000000F // Target Endpoint Number.
+#define USB_RXTYPE10_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL10
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL10_NAKLMT_M \
+ 0x000000FF // NAK Limit.
+#define USB_RXINTERVAL10_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL10_TXPOLL_S \
+ 0
+#define USB_RXINTERVAL10_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP11 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP11_MAXLOAD_M 0x000007FF // Maximum Payload.
+#define USB_TXMAXP11_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL11 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL11_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL11_INCTX 0x00000080 // Incomplete Transmit.
+#define USB_TXCSRL11_CLRDT 0x00000040 // Clear Data Toggle.
+#define USB_TXCSRL11_STALLED 0x00000020 // Endpoint Stalled.
+#define USB_TXCSRL11_STALL 0x00000010 // Send Stall.
+#define USB_TXCSRL11_SETUP 0x00000010 // Setup Packet.
+#define USB_TXCSRL11_FLUSH 0x00000008 // Flush FIFO.
+#define USB_TXCSRL11_ERROR 0x00000004 // Error.
+#define USB_TXCSRL11_UNDRN 0x00000004 // Underrun.
+#define USB_TXCSRL11_FIFONE 0x00000002 // FIFO Not Empty.
+#define USB_TXCSRL11_TXRDY 0x00000001 // Transmit Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH11 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH11_AUTOSET 0x00000080 // Auto Set.
+#define USB_TXCSRH11_ISO 0x00000040 // ISO.
+#define USB_TXCSRH11_MODE 0x00000020 // Mode.
+#define USB_TXCSRH11_DMAEN 0x00000010 // DMA Request Enable.
+#define USB_TXCSRH11_FDT 0x00000008 // Force Data Toggle.
+#define USB_TXCSRH11_DMAMOD 0x00000004 // DMA Request Mode.
+#define USB_TXCSRH11_DTWE 0x00000002 // Data Toggle Write Enable.
+#define USB_TXCSRH11_DT 0x00000001 // Data Toggle.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP11 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP11_MAXLOAD_M 0x000007FF // Maximum Payload.
+#define USB_RXMAXP11_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL11 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL11_CLRDT 0x00000080 // Clear Data Toggle.
+#define USB_RXCSRL11_STALLED 0x00000040 // Endpoint Stalled.
+#define USB_RXCSRL11_STALL 0x00000020 // Send Stall.
+#define USB_RXCSRL11_REQPKT 0x00000020 // Request Packet.
+#define USB_RXCSRL11_FLUSH 0x00000010 // Flush FIFO.
+#define USB_RXCSRL11_DATAERR 0x00000008 // Data Error.
+#define USB_RXCSRL11_NAKTO 0x00000008 // NAK Timeout.
+#define USB_RXCSRL11_OVER 0x00000004 // Overrun.
+#define USB_RXCSRL11_ERROR 0x00000004 // Error.
+#define USB_RXCSRL11_FULL 0x00000002 // FIFO Full.
+#define USB_RXCSRL11_RXRDY 0x00000001 // Receive Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH11 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH11_AUTOCL 0x00000080 // Auto Clear.
+#define USB_RXCSRH11_ISO 0x00000040 // ISO.
+#define USB_RXCSRH11_AUTORQ 0x00000040 // Auto Request.
+#define USB_RXCSRH11_DMAEN 0x00000020 // DMA Request Enable.
+#define USB_RXCSRH11_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH11_PIDERR 0x00000010 // PID Error.
+#define USB_RXCSRH11_DMAMOD 0x00000008 // DMA Request Mode.
+#define USB_RXCSRH11_DTWE 0x00000004 // Data Toggle Write Enable.
+#define USB_RXCSRH11_DT 0x00000002 // Data Toggle.
+#define USB_RXCSRH11_INCRX 0x00000001 // Incomplete Receive.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT11
+// register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT11_COUNT_M 0x00001FFF // Receive Packet Count.
+#define USB_RXCOUNT11_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE11 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE11_SPEED_M 0x000000C0 // Operating Speed.
+#define USB_TXTYPE11_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE11_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE11_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE11_PROTO_M 0x00000030 // Protocol.
+#define USB_TXTYPE11_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE11_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE11_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE11_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE11_TEP_M 0x0000000F // Target Endpoint Number.
+#define USB_TXTYPE11_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL11
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL11_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL11_NAKLMT_M \
+ 0x000000FF // NAK Limit.
+#define USB_TXINTERVAL11_NAKLMT_S \
+ 0
+#define USB_TXINTERVAL11_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE11 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE11_SPEED_M 0x000000C0 // Operating Speed.
+#define USB_RXTYPE11_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE11_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE11_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE11_PROTO_M 0x00000030 // Protocol.
+#define USB_RXTYPE11_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE11_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE11_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE11_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE11_TEP_M 0x0000000F // Target Endpoint Number.
+#define USB_RXTYPE11_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL11
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL11_NAKLMT_M \
+ 0x000000FF // NAK Limit.
+#define USB_RXINTERVAL11_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL11_TXPOLL_S \
+ 0
+#define USB_RXINTERVAL11_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP12 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP12_MAXLOAD_M 0x000007FF // Maximum Payload.
+#define USB_TXMAXP12_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL12 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL12_INCTX 0x00000080 // Incomplete Transmit.
+#define USB_TXCSRL12_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL12_CLRDT 0x00000040 // Clear Data Toggle.
+#define USB_TXCSRL12_STALLED 0x00000020 // Endpoint Stalled.
+#define USB_TXCSRL12_SETUP 0x00000010 // Setup Packet.
+#define USB_TXCSRL12_STALL 0x00000010 // Send Stall.
+#define USB_TXCSRL12_FLUSH 0x00000008 // Flush FIFO.
+#define USB_TXCSRL12_UNDRN 0x00000004 // Underrun.
+#define USB_TXCSRL12_ERROR 0x00000004 // Error.
+#define USB_TXCSRL12_FIFONE 0x00000002 // FIFO Not Empty.
+#define USB_TXCSRL12_TXRDY 0x00000001 // Transmit Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH12 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH12_AUTOSET 0x00000080 // Auto Set.
+#define USB_TXCSRH12_ISO 0x00000040 // ISO.
+#define USB_TXCSRH12_MODE 0x00000020 // Mode.
+#define USB_TXCSRH12_DMAEN 0x00000010 // DMA Request Enable.
+#define USB_TXCSRH12_FDT 0x00000008 // Force Data Toggle.
+#define USB_TXCSRH12_DMAMOD 0x00000004 // DMA Request Mode.
+#define USB_TXCSRH12_DTWE 0x00000002 // Data Toggle Write Enable.
+#define USB_TXCSRH12_DT 0x00000001 // Data Toggle.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP12 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP12_MAXLOAD_M 0x000007FF // Maximum Payload.
+#define USB_RXMAXP12_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL12 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL12_CLRDT 0x00000080 // Clear Data Toggle.
+#define USB_RXCSRL12_STALLED 0x00000040 // Endpoint Stalled.
+#define USB_RXCSRL12_STALL 0x00000020 // Send Stall.
+#define USB_RXCSRL12_REQPKT 0x00000020 // Request Packet.
+#define USB_RXCSRL12_FLUSH 0x00000010 // Flush FIFO.
+#define USB_RXCSRL12_NAKTO 0x00000008 // NAK Timeout.
+#define USB_RXCSRL12_DATAERR 0x00000008 // Data Error.
+#define USB_RXCSRL12_ERROR 0x00000004 // Error.
+#define USB_RXCSRL12_OVER 0x00000004 // Overrun.
+#define USB_RXCSRL12_FULL 0x00000002 // FIFO Full.
+#define USB_RXCSRL12_RXRDY 0x00000001 // Receive Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH12 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH12_AUTOCL 0x00000080 // Auto Clear.
+#define USB_RXCSRH12_ISO 0x00000040 // ISO.
+#define USB_RXCSRH12_AUTORQ 0x00000040 // Auto Request.
+#define USB_RXCSRH12_DMAEN 0x00000020 // DMA Request Enable.
+#define USB_RXCSRH12_PIDERR 0x00000010 // PID Error.
+#define USB_RXCSRH12_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH12_DMAMOD 0x00000008 // DMA Request Mode.
+#define USB_RXCSRH12_DTWE 0x00000004 // Data Toggle Write Enable.
+#define USB_RXCSRH12_DT 0x00000002 // Data Toggle.
+#define USB_RXCSRH12_INCRX 0x00000001 // Incomplete Receive.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT12
+// register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT12_COUNT_M 0x00001FFF // Receive Packet Count.
+#define USB_RXCOUNT12_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE12 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE12_SPEED_M 0x000000C0 // Operating Speed.
+#define USB_TXTYPE12_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE12_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE12_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE12_PROTO_M 0x00000030 // Protocol.
+#define USB_TXTYPE12_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE12_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE12_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE12_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE12_TEP_M 0x0000000F // Target Endpoint Number.
+#define USB_TXTYPE12_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL12
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL12_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL12_NAKLMT_M \
+ 0x000000FF // NAK Limit.
+#define USB_TXINTERVAL12_TXPOLL_S \
+ 0
+#define USB_TXINTERVAL12_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE12 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE12_SPEED_M 0x000000C0 // Operating Speed.
+#define USB_RXTYPE12_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE12_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE12_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE12_PROTO_M 0x00000030 // Protocol.
+#define USB_RXTYPE12_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE12_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE12_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE12_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE12_TEP_M 0x0000000F // Target Endpoint Number.
+#define USB_RXTYPE12_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL12
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL12_NAKLMT_M \
+ 0x000000FF // NAK Limit.
+#define USB_RXINTERVAL12_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL12_NAKLMT_S \
+ 0
+#define USB_RXINTERVAL12_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP13 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP13_MAXLOAD_M 0x000007FF // Maximum Payload.
+#define USB_TXMAXP13_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL13 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL13_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL13_INCTX 0x00000080 // Incomplete Transmit.
+#define USB_TXCSRL13_CLRDT 0x00000040 // Clear Data Toggle.
+#define USB_TXCSRL13_STALLED 0x00000020 // Endpoint Stalled.
+#define USB_TXCSRL13_SETUP 0x00000010 // Setup Packet.
+#define USB_TXCSRL13_STALL 0x00000010 // Send Stall.
+#define USB_TXCSRL13_FLUSH 0x00000008 // Flush FIFO.
+#define USB_TXCSRL13_UNDRN 0x00000004 // Underrun.
+#define USB_TXCSRL13_ERROR 0x00000004 // Error.
+#define USB_TXCSRL13_FIFONE 0x00000002 // FIFO Not Empty.
+#define USB_TXCSRL13_TXRDY 0x00000001 // Transmit Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH13 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH13_AUTOSET 0x00000080 // Auto Set.
+#define USB_TXCSRH13_ISO 0x00000040 // ISO.
+#define USB_TXCSRH13_MODE 0x00000020 // Mode.
+#define USB_TXCSRH13_DMAEN 0x00000010 // DMA Request Enable.
+#define USB_TXCSRH13_FDT 0x00000008 // Force Data Toggle.
+#define USB_TXCSRH13_DMAMOD 0x00000004 // DMA Request Mode.
+#define USB_TXCSRH13_DTWE 0x00000002 // Data Toggle Write Enable.
+#define USB_TXCSRH13_DT 0x00000001 // Data Toggle.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP13 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP13_MAXLOAD_M 0x000007FF // Maximum Payload.
+#define USB_RXMAXP13_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL13 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL13_CLRDT 0x00000080 // Clear Data Toggle.
+#define USB_RXCSRL13_STALLED 0x00000040 // Endpoint Stalled.
+#define USB_RXCSRL13_REQPKT 0x00000020 // Request Packet.
+#define USB_RXCSRL13_STALL 0x00000020 // Send Stall.
+#define USB_RXCSRL13_FLUSH 0x00000010 // Flush FIFO.
+#define USB_RXCSRL13_NAKTO 0x00000008 // NAK Timeout.
+#define USB_RXCSRL13_DATAERR 0x00000008 // Data Error.
+#define USB_RXCSRL13_OVER 0x00000004 // Overrun.
+#define USB_RXCSRL13_ERROR 0x00000004 // Error.
+#define USB_RXCSRL13_FULL 0x00000002 // FIFO Full.
+#define USB_RXCSRL13_RXRDY 0x00000001 // Receive Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH13 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH13_AUTOCL 0x00000080 // Auto Clear.
+#define USB_RXCSRH13_ISO 0x00000040 // ISO.
+#define USB_RXCSRH13_AUTORQ 0x00000040 // Auto Request.
+#define USB_RXCSRH13_DMAEN 0x00000020 // DMA Request Enable.
+#define USB_RXCSRH13_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH13_PIDERR 0x00000010 // PID Error.
+#define USB_RXCSRH13_DMAMOD 0x00000008 // DMA Request Mode.
+#define USB_RXCSRH13_DTWE 0x00000004 // Data Toggle Write Enable.
+#define USB_RXCSRH13_DT 0x00000002 // Data Toggle.
+#define USB_RXCSRH13_INCRX 0x00000001 // Incomplete Receive.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT13
+// register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT13_COUNT_M 0x00001FFF // Receive Packet Count.
+#define USB_RXCOUNT13_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE13 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE13_SPEED_M 0x000000C0 // Operating Speed.
+#define USB_TXTYPE13_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE13_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE13_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE13_PROTO_M 0x00000030 // Protocol.
+#define USB_TXTYPE13_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE13_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE13_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE13_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE13_TEP_M 0x0000000F // Target Endpoint Number.
+#define USB_TXTYPE13_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL13
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL13_NAKLMT_M \
+ 0x000000FF // NAK Limit.
+#define USB_TXINTERVAL13_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL13_TXPOLL_S \
+ 0
+#define USB_TXINTERVAL13_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE13 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE13_SPEED_M 0x000000C0 // Operating Speed.
+#define USB_RXTYPE13_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE13_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE13_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE13_PROTO_M 0x00000030 // Protocol.
+#define USB_RXTYPE13_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE13_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE13_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE13_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE13_TEP_M 0x0000000F // Target Endpoint Number.
+#define USB_RXTYPE13_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL13
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL13_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL13_NAKLMT_M \
+ 0x000000FF // NAK Limit.
+#define USB_RXINTERVAL13_TXPOLL_S \
+ 0
+#define USB_RXINTERVAL13_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP14 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP14_MAXLOAD_M 0x000007FF // Maximum Payload.
+#define USB_TXMAXP14_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL14 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL14_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL14_INCTX 0x00000080 // Incomplete Transmit.
+#define USB_TXCSRL14_CLRDT 0x00000040 // Clear Data Toggle.
+#define USB_TXCSRL14_STALLED 0x00000020 // Endpoint Stalled.
+#define USB_TXCSRL14_STALL 0x00000010 // Send Stall.
+#define USB_TXCSRL14_SETUP 0x00000010 // Setup Packet.
+#define USB_TXCSRL14_FLUSH 0x00000008 // Flush FIFO.
+#define USB_TXCSRL14_ERROR 0x00000004 // Error.
+#define USB_TXCSRL14_UNDRN 0x00000004 // Underrun.
+#define USB_TXCSRL14_FIFONE 0x00000002 // FIFO Not Empty.
+#define USB_TXCSRL14_TXRDY 0x00000001 // Transmit Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH14 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH14_AUTOSET 0x00000080 // Auto Set.
+#define USB_TXCSRH14_ISO 0x00000040 // ISO.
+#define USB_TXCSRH14_MODE 0x00000020 // Mode.
+#define USB_TXCSRH14_DMAEN 0x00000010 // DMA Request Enable.
+#define USB_TXCSRH14_FDT 0x00000008 // Force Data Toggle.
+#define USB_TXCSRH14_DMAMOD 0x00000004 // DMA Request Mode.
+#define USB_TXCSRH14_DTWE 0x00000002 // Data Toggle Write Enable.
+#define USB_TXCSRH14_DT 0x00000001 // Data Toggle.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP14 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP14_MAXLOAD_M 0x000007FF // Maximum Payload.
+#define USB_RXMAXP14_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL14 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL14_CLRDT 0x00000080 // Clear Data Toggle.
+#define USB_RXCSRL14_STALLED 0x00000040 // Endpoint Stalled.
+#define USB_RXCSRL14_REQPKT 0x00000020 // Request Packet.
+#define USB_RXCSRL14_STALL 0x00000020 // Send Stall.
+#define USB_RXCSRL14_FLUSH 0x00000010 // Flush FIFO.
+#define USB_RXCSRL14_DATAERR 0x00000008 // Data Error.
+#define USB_RXCSRL14_NAKTO 0x00000008 // NAK Timeout.
+#define USB_RXCSRL14_OVER 0x00000004 // Overrun.
+#define USB_RXCSRL14_ERROR 0x00000004 // Error.
+#define USB_RXCSRL14_FULL 0x00000002 // FIFO Full.
+#define USB_RXCSRL14_RXRDY 0x00000001 // Receive Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH14 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH14_AUTOCL 0x00000080 // Auto Clear.
+#define USB_RXCSRH14_AUTORQ 0x00000040 // Auto Request.
+#define USB_RXCSRH14_ISO 0x00000040 // ISO.
+#define USB_RXCSRH14_DMAEN 0x00000020 // DMA Request Enable.
+#define USB_RXCSRH14_PIDERR 0x00000010 // PID Error.
+#define USB_RXCSRH14_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH14_DMAMOD 0x00000008 // DMA Request Mode.
+#define USB_RXCSRH14_DTWE 0x00000004 // Data Toggle Write Enable.
+#define USB_RXCSRH14_DT 0x00000002 // Data Toggle.
+#define USB_RXCSRH14_INCRX 0x00000001 // Incomplete Receive.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT14
+// register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT14_COUNT_M 0x00001FFF // Receive Packet Count.
+#define USB_RXCOUNT14_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE14 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE14_SPEED_M 0x000000C0 // Operating Speed.
+#define USB_TXTYPE14_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE14_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE14_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE14_PROTO_M 0x00000030 // Protocol.
+#define USB_TXTYPE14_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE14_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE14_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE14_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE14_TEP_M 0x0000000F // Target Endpoint Number.
+#define USB_TXTYPE14_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL14
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL14_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL14_NAKLMT_M \
+ 0x000000FF // NAK Limit.
+#define USB_TXINTERVAL14_TXPOLL_S \
+ 0
+#define USB_TXINTERVAL14_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE14 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE14_SPEED_M 0x000000C0 // Operating Speed.
+#define USB_RXTYPE14_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE14_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE14_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE14_PROTO_M 0x00000030 // Protocol.
+#define USB_RXTYPE14_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE14_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE14_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE14_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE14_TEP_M 0x0000000F // Target Endpoint Number.
+#define USB_RXTYPE14_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL14
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL14_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL14_NAKLMT_M \
+ 0x000000FF // NAK Limit.
+#define USB_RXINTERVAL14_TXPOLL_S \
+ 0
+#define USB_RXINTERVAL14_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP15 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP15_MAXLOAD_M 0x000007FF // Maximum Payload.
+#define USB_TXMAXP15_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL15 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL15_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL15_INCTX 0x00000080 // Incomplete Transmit.
+#define USB_TXCSRL15_CLRDT 0x00000040 // Clear Data Toggle.
+#define USB_TXCSRL15_STALLED 0x00000020 // Endpoint Stalled.
+#define USB_TXCSRL15_SETUP 0x00000010 // Setup Packet.
+#define USB_TXCSRL15_STALL 0x00000010 // Send Stall.
+#define USB_TXCSRL15_FLUSH 0x00000008 // Flush FIFO.
+#define USB_TXCSRL15_UNDRN 0x00000004 // Underrun.
+#define USB_TXCSRL15_ERROR 0x00000004 // Error.
+#define USB_TXCSRL15_FIFONE 0x00000002 // FIFO Not Empty.
+#define USB_TXCSRL15_TXRDY 0x00000001 // Transmit Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH15 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH15_AUTOSET 0x00000080 // Auto Set.
+#define USB_TXCSRH15_ISO 0x00000040 // ISO.
+#define USB_TXCSRH15_MODE 0x00000020 // Mode.
+#define USB_TXCSRH15_DMAEN 0x00000010 // DMA Request Enable.
+#define USB_TXCSRH15_FDT 0x00000008 // Force Data Toggle.
+#define USB_TXCSRH15_DMAMOD 0x00000004 // DMA Request Mode.
+#define USB_TXCSRH15_DTWE 0x00000002 // Data Toggle Write Enable.
+#define USB_TXCSRH15_DT 0x00000001 // Data Toggle.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP15 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP15_MAXLOAD_M 0x000007FF // Maximum Payload.
+#define USB_RXMAXP15_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL15 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL15_CLRDT 0x00000080 // Clear Data Toggle.
+#define USB_RXCSRL15_STALLED 0x00000040 // Endpoint Stalled.
+#define USB_RXCSRL15_STALL 0x00000020 // Send Stall.
+#define USB_RXCSRL15_REQPKT 0x00000020 // Request Packet.
+#define USB_RXCSRL15_FLUSH 0x00000010 // Flush FIFO.
+#define USB_RXCSRL15_DATAERR 0x00000008 // Data Error.
+#define USB_RXCSRL15_NAKTO 0x00000008 // NAK Timeout.
+#define USB_RXCSRL15_ERROR 0x00000004 // Error.
+#define USB_RXCSRL15_OVER 0x00000004 // Overrun.
+#define USB_RXCSRL15_FULL 0x00000002 // FIFO Full.
+#define USB_RXCSRL15_RXRDY 0x00000001 // Receive Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH15 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH15_AUTOCL 0x00000080 // Auto Clear.
+#define USB_RXCSRH15_AUTORQ 0x00000040 // Auto Request.
+#define USB_RXCSRH15_ISO 0x00000040 // ISO.
+#define USB_RXCSRH15_DMAEN 0x00000020 // DMA Request Enable.
+#define USB_RXCSRH15_PIDERR 0x00000010 // PID Error.
+#define USB_RXCSRH15_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH15_DMAMOD 0x00000008 // DMA Request Mode.
+#define USB_RXCSRH15_DTWE 0x00000004 // Data Toggle Write Enable.
+#define USB_RXCSRH15_DT 0x00000002 // Data Toggle.
+#define USB_RXCSRH15_INCRX 0x00000001 // Incomplete Receive.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT15
+// register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT15_COUNT_M 0x00001FFF // Receive Packet Count.
+#define USB_RXCOUNT15_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE15 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE15_SPEED_M 0x000000C0 // Operating Speed.
+#define USB_TXTYPE15_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE15_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE15_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE15_PROTO_M 0x00000030 // Protocol.
+#define USB_TXTYPE15_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE15_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE15_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE15_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE15_TEP_M 0x0000000F // Target Endpoint Number.
+#define USB_TXTYPE15_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL15
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL15_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL15_NAKLMT_M \
+ 0x000000FF // NAK Limit.
+#define USB_TXINTERVAL15_NAKLMT_S \
+ 0
+#define USB_TXINTERVAL15_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE15 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE15_SPEED_M 0x000000C0 // Operating Speed.
+#define USB_RXTYPE15_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE15_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE15_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE15_PROTO_M 0x00000030 // Protocol.
+#define USB_RXTYPE15_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE15_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE15_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE15_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE15_TEP_M 0x0000000F // Target Endpoint Number.
+#define USB_RXTYPE15_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL15
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL15_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL15_NAKLMT_M \
+ 0x000000FF // NAK Limit.
+#define USB_RXINTERVAL15_TXPOLL_S \
+ 0
+#define USB_RXINTERVAL15_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT4
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT4_COUNT_M 0x0000FFFF // Block Transfer Packet Count.
+#define USB_RQPKTCOUNT4_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT5
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT5_COUNT_M 0x0000FFFF // Block Transfer Packet Count.
+#define USB_RQPKTCOUNT5_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT6
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT6_COUNT_M 0x0000FFFF // Block Transfer Packet Count.
+#define USB_RQPKTCOUNT6_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT7
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT7_COUNT_M 0x0000FFFF // Block Transfer Packet Count.
+#define USB_RQPKTCOUNT7_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT8
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT8_COUNT_M 0x0000FFFF // Block Transfer Packet Count.
+#define USB_RQPKTCOUNT8_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT9
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT9_COUNT_M 0x0000FFFF // Block Transfer Packet Count.
+#define USB_RQPKTCOUNT9_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT10
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT10_COUNT_M \
+ 0x0000FFFF // Block Transfer Packet Count.
+#define USB_RQPKTCOUNT10_COUNT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT11
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT11_COUNT_M \
+ 0x0000FFFF // Block Transfer Packet Count.
+#define USB_RQPKTCOUNT11_COUNT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT12
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT12_COUNT_M \
+ 0x0000FFFF // Block Transfer Packet Count.
+#define USB_RQPKTCOUNT12_COUNT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT13
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT13_COUNT_M \
+ 0x0000FFFF // Block Transfer Packet Count.
+#define USB_RQPKTCOUNT13_COUNT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT14
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT14_COUNT_M \
+ 0x0000FFFF // Block Transfer Packet Count.
+#define USB_RQPKTCOUNT14_COUNT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT15
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT15_COUNT_M \
+ 0x0000FFFF // Block Transfer Packet Count.
+#define USB_RQPKTCOUNT15_COUNT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPS register.
+//
+//*****************************************************************************
+#define USB_EPS_DMAC_M 0x00000F00 // DMA C Select.
+#define USB_EPS_DMAB_M 0x000000F0 // DMA B Select.
+#define USB_EPS_DMAA_M 0x0000000F // DMA A Select.
+#define USB_EPS_DMAC_S 8
+#define USB_EPS_DMAB_S 4
+#define USB_EPS_DMAA_S 0
+
+#endif // __HW_USB_H__
Property changes on: branches/eagle_mmc/src/platform/lm3s/hw_usb.h
___________________________________________________________________
Name: svn:executable
+ *
Added: branches/eagle_mmc/src/platform/lm3s/hw_watchdog.h
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/hw_watchdog.h 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lm3s/hw_watchdog.h 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,178 @@
+//*****************************************************************************
+//
+// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware.
+//
+// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4781 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_WATCHDOG_H__
+#define __HW_WATCHDOG_H__
+
+//*****************************************************************************
+//
+// The following are defines for the Watchdog Timer register offsets.
+//
+//*****************************************************************************
+#define WDT_O_LOAD 0x00000000 // Load register
+#define WDT_O_VALUE 0x00000004 // Current value register
+#define WDT_O_CTL 0x00000008 // Control register
+#define WDT_O_ICR 0x0000000C // Interrupt clear register
+#define WDT_O_RIS 0x00000010 // Raw interrupt status register
+#define WDT_O_MIS 0x00000014 // Masked interrupt status register
+#define WDT_O_TEST 0x00000418 // Test register
+#define WDT_O_LOCK 0x00000C00 // Lock register
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_CTL register.
+//
+//*****************************************************************************
+#define WDT_CTL_RESEN 0x00000002 // Enable reset output
+#define WDT_CTL_INTEN 0x00000001 // Enable the WDT counter and int
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_ISR, WDT_RIS, and
+// WDT_MIS registers.
+//
+//*****************************************************************************
+#define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_TEST register.
+//
+//*****************************************************************************
+#define WDT_TEST_STALL 0x00000100 // Watchdog stall enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_LOCK register.
+//
+//*****************************************************************************
+#define WDT_LOCK_M 0xFFFFFFFF // Watchdog Lock.
+#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer
+#define WDT_LOCK_LOCKED 0x00000001 // Watchdog timer is locked
+#define WDT_LOCK_UNLOCKED 0x00000000 // Watchdog timer is unlocked
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_LOAD register.
+//
+//*****************************************************************************
+#define WDT_LOAD_M 0xFFFFFFFF // Watchdog Load Value.
+#define WDT_LOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_VALUE register.
+//
+//*****************************************************************************
+#define WDT_VALUE_M 0xFFFFFFFF // Watchdog Value.
+#define WDT_VALUE_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_ICR register.
+//
+//*****************************************************************************
+#define WDT_ICR_M 0xFFFFFFFF // Watchdog Interrupt Clear.
+#define WDT_ICR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_RIS register.
+//
+//*****************************************************************************
+#define WDT_RIS_WDTRIS 0x00000001 // Watchdog Raw Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_MIS register.
+//
+//*****************************************************************************
+#define WDT_MIS_WDTMIS 0x00000001 // Watchdog Masked Interrupt
+ // Status.
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the Watchdog Timer register
+// offsets.
+//
+//*****************************************************************************
+#define WDT_O_PeriphID4 0x00000FD0
+#define WDT_O_PeriphID5 0x00000FD4
+#define WDT_O_PeriphID6 0x00000FD8
+#define WDT_O_PeriphID7 0x00000FDC
+#define WDT_O_PeriphID0 0x00000FE0
+#define WDT_O_PeriphID1 0x00000FE4
+#define WDT_O_PeriphID2 0x00000FE8
+#define WDT_O_PeriphID3 0x00000FEC
+#define WDT_O_PCellID0 0x00000FF0
+#define WDT_O_PCellID1 0x00000FF4
+#define WDT_O_PCellID2 0x00000FF8
+#define WDT_O_PCellID3 0x00000FFC
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the WDT_TEST
+// register.
+//
+//*****************************************************************************
+#define WDT_TEST_STALL_EN 0x00000100 // Watchdog stall enable
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the reset values for the WDT
+// registers.
+//
+//*****************************************************************************
+#define WDT_RV_VALUE 0xFFFFFFFF // Current value register
+#define WDT_RV_LOAD 0xFFFFFFFF // Load register
+#define WDT_RV_PCellID1 0x000000F0
+#define WDT_RV_PCellID3 0x000000B1
+#define WDT_RV_PeriphID1 0x00000018
+#define WDT_RV_PeriphID2 0x00000018
+#define WDT_RV_PCellID0 0x0000000D
+#define WDT_RV_PCellID2 0x00000005
+#define WDT_RV_PeriphID0 0x00000005
+#define WDT_RV_PeriphID3 0x00000001
+#define WDT_RV_PeriphID5 0x00000000
+#define WDT_RV_RIS 0x00000000 // Raw interrupt status register
+#define WDT_RV_CTL 0x00000000 // Control register
+#define WDT_RV_PeriphID4 0x00000000
+#define WDT_RV_PeriphID6 0x00000000
+#define WDT_RV_PeriphID7 0x00000000
+#define WDT_RV_LOCK 0x00000000 // Lock register
+#define WDT_RV_MIS 0x00000000 // Masked interrupt status register
+
+#endif
+
+#endif // __HW_WATCHDOG_H__
Property changes on: branches/eagle_mmc/src/platform/lm3s/hw_watchdog.h
___________________________________________________________________
Name: svn:executable
+ *
Modified: branches/eagle_mmc/src/platform/lm3s/interrupt.c
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/interrupt.c 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lm3s/interrupt.c 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,550 +1,550 @@
-//*****************************************************************************
-//
-// interrupt.c - Driver for the NVIC Interrupt Controller.
-//
-// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
-// Software License Agreement
-//
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
-//
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws. All rights are reserved. You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program. Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
-//
-// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-//
-// This is part of revision 3740 of the Stellaris Peripheral Driver Library.
-//
-//*****************************************************************************
-
-//*****************************************************************************
-//
-//! \addtogroup interrupt_api
-//! @{
-//
-//*****************************************************************************
-
-#include "hw_ints.h"
-#include "hw_nvic.h"
-#include "hw_types.h"
-#include "cpu.h"
-#include "debug.h"
-#include "interrupt.h"
-
-//*****************************************************************************
-//
-// This is a mapping between priority grouping encodings and the number of
-// preemption priority bits.
-//
-//*****************************************************************************
-static const unsigned long g_pulPriority[] =
-{
- NVIC_APINT_PRIGROUP_0_8, NVIC_APINT_PRIGROUP_1_7, NVIC_APINT_PRIGROUP_2_6,
- NVIC_APINT_PRIGROUP_3_5, NVIC_APINT_PRIGROUP_4_4, NVIC_APINT_PRIGROUP_5_3,
- NVIC_APINT_PRIGROUP_6_2, NVIC_APINT_PRIGROUP_7_1
-};
-
-//*****************************************************************************
-//
-// This is a mapping between interrupt number and the register that contains
-// the priority encoding for that interrupt.
-//
-//*****************************************************************************
-static const unsigned long g_pulRegs[] =
-{
- 0, NVIC_SYS_PRI1, NVIC_SYS_PRI2, NVIC_SYS_PRI3, NVIC_PRI0, NVIC_PRI1,
- NVIC_PRI2, NVIC_PRI3, NVIC_PRI4, NVIC_PRI5, NVIC_PRI6, NVIC_PRI7,
- NVIC_PRI8, NVIC_PRI9, NVIC_PRI10, NVIC_PRI11
-};
-
-//*****************************************************************************
-//
-//! \internal
-//! The default interrupt handler.
-//!
-//! This is the default interrupt handler for all interrupts. It simply loops
-//! forever so that the system state is preserved for observation by a
-//! debugger. Since interrupts should be disabled before unregistering the
-//! corresponding handler, this should never be called.
-//!
-//! \return None.
-//
-//*****************************************************************************
-static void
-IntDefaultHandler(void)
-{
- //
- // Go into an infinite loop.
- //
- while(1)
- {
- }
-}
-
-//*****************************************************************************
-//
-// The processor vector table.
-//
-// This contains a list of the handlers for the various interrupt sources in
-// the system. The layout of this list is defined by the hardware; assertion
-// of an interrupt causes the processor to start executing directly at the
-// address given in the corresponding location in this list.
-//
-//*****************************************************************************
-#if defined(ewarm)
-static __no_init void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) @ "VTABLE";
-#elif defined(sourcerygxx)
-static __attribute__((section(".cs3.region-head.ram")))
-void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void);
-#else
-static __attribute__((section("vtable")))
-void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void);
-#endif
-
-//*****************************************************************************
-//
-//! Enables the processor interrupt.
-//!
-//! Allows the processor to respond to interrupts. This does not affect the
-//! set of interrupts enabled in the interrupt controller; it just gates the
-//! single interrupt from the controller to the processor.
-//!
-//! \note Previously, this function had no return value. As such, it was
-//! possible to include <tt>interrupt.h</tt> and call this function without
-//! having included <tt>hw_types.h</tt>. Now that the return is a
-//! <tt>tBoolean</tt>, a compiler error will occur in this case. The solution
-//! is to include <tt>hw_types.h</tt> before including <tt>interrupt.h</tt>.
-//!
-//! \return Returns \b true if interrupts were disabled when the function was
-//! called or \b false if they were initially enabled.
-//
-//*****************************************************************************
-tBoolean
-IntMasterEnable(void)
-{
- //
- // Enable processor interrupts.
- //
- return(CPUcpsie());
-}
-
-//*****************************************************************************
-//
-//! Disables the processor interrupt.
-//!
-//! Prevents the processor from receiving interrupts. This does not affect the
-//! set of interrupts enabled in the interrupt controller; it just gates the
-//! single interrupt from the controller to the processor.
-//!
-//! \note Previously, this function had no return value. As such, it was
-//! possible to include <tt>interrupt.h</tt> and call this function without
-//! having included <tt>hw_types.h</tt>. Now that the return is a
-//! <tt>tBoolean</tt>, a compiler error will occur in this case. The solution
-//! is to include <tt>hw_types.h</tt> before including <tt>interrupt.h</tt>.
-//!
-//! \return Returns \b true if interrupts were already disabled when the
-//! function was called or \b false if they were initially enabled.
-//
-//*****************************************************************************
-tBoolean
-IntMasterDisable(void)
-{
- //
- // Disable processor interrupts.
- //
- return(CPUcpsid());
-}
-
-//*****************************************************************************
-//
-//! Registers a function to be called when an interrupt occurs.
-//!
-//! \param ulInterrupt specifies the interrupt in question.
-//! \param pfnHandler is a pointer to the function to be called.
-//!
-//! This function is used to specify the handler function to be called when the
-//! given interrupt is asserted to the processor. When the interrupt occurs,
-//! if it is enabled (via IntEnable()), the handler function will be called in
-//! interrupt context. Since the handler function can preempt other code, care
-//! must be taken to protect memory or peripherals that are accessed by the
-//! handler and other non-handler code.
-//!
-//! \note The use of this function (directly or indirectly via a peripheral
-//! driver interrupt register function) moves the interrupt vector table from
-//! flash to SRAM. Therefore, care must be taken when linking the application
-//! to ensure that the SRAM vector table is located at the beginning of SRAM;
-//! otherwise NVIC will not look in the correct portion of memory for the
-//! vector table (it requires the vector table be on a 1 kB memory alignment).
-//! Normally, the SRAM vector table is so placed via the use of linker scripts;
-//! some tool chains, such as the evaluation version of RV-MDK, do not support
-//! linker scripts and therefore will not produce a valid executable. See the
-//! discussion of compile-time versus run-time interrupt handler registration
-//! in the introduction to this chapter.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void))
-{
- unsigned long ulIdx, ulValue;
-
- //
- // Check the arguments.
- //
- ASSERT(ulInterrupt < NUM_INTERRUPTS);
-
- //
- // Make sure that the RAM vector table is correctly aligned.
- //
- ASSERT(((unsigned long)g_pfnRAMVectors & 0x000003ff) == 0);
-
- //
- // See if the RAM vector table has been initialized.
- //
- if(HWREG(NVIC_VTABLE) != (unsigned long)g_pfnRAMVectors)
- {
- //
- // Copy the vector table from the beginning of FLASH to the RAM vector
- // table.
- //
- ulValue = HWREG(NVIC_VTABLE);
- for(ulIdx = 0; ulIdx < NUM_INTERRUPTS; ulIdx++)
- {
- g_pfnRAMVectors[ulIdx] = (void (*)(void))HWREG((ulIdx * 4) +
- ulValue);
- }
-
- //
- // Point NVIC at the RAM vector table.
- //
- HWREG(NVIC_VTABLE) = (unsigned long)g_pfnRAMVectors;
- }
-
- //
- // Save the interrupt handler.
- //
- g_pfnRAMVectors[ulInterrupt] = pfnHandler;
-}
-
-//*****************************************************************************
-//
-//! Unregisters the function to be called when an interrupt occurs.
-//!
-//! \param ulInterrupt specifies the interrupt in question.
-//!
-//! This function is used to indicate that no handler should be called when the
-//! given interrupt is asserted to the processor. The interrupt source will be
-//! automatically disabled (via IntDisable()) if necessary.
-//!
-//! \sa IntRegister() for important information about registering interrupt
-//! handlers.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-IntUnregister(unsigned long ulInterrupt)
-{
- //
- // Check the arguments.
- //
- ASSERT(ulInterrupt < NUM_INTERRUPTS);
-
- //
- // Reset the interrupt handler.
- //
- g_pfnRAMVectors[ulInterrupt] = IntDefaultHandler;
-}
-
-//*****************************************************************************
-//
-//! Sets the priority grouping of the interrupt controller.
-//!
-//! \param ulBits specifies the number of bits of preemptable priority.
-//!
-//! This function specifies the split between preemptable priority levels and
-//! subpriority levels in the interrupt priority specification. The range of
-//! the grouping values are dependent upon the hardware implementation; on
-//! the Stellaris family, three bits are available for hardware interrupt
-//! prioritization and therefore priority grouping values of three through
-//! seven have the same effect.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-IntPriorityGroupingSet(unsigned long ulBits)
-{
- //
- // Check the arguments.
- //
- ASSERT(ulBits < NUM_PRIORITY);
-
- //
- // Set the priority grouping.
- //
- HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | g_pulPriority[ulBits];
-}
-
-//*****************************************************************************
-//
-//! Gets the priority grouping of the interrupt controller.
-//!
-//! This function returns the split between preemptable priority levels and
-//! subpriority levels in the interrupt priority specification.
-//!
-//! \return The number of bits of preemptable priority.
-//
-//*****************************************************************************
-unsigned long
-IntPriorityGroupingGet(void)
-{
- unsigned long ulLoop, ulValue;
-
- //
- // Read the priority grouping.
- //
- ulValue = HWREG(NVIC_APINT) & NVIC_APINT_PRIGROUP_M;
-
- //
- // Loop through the priority grouping values.
- //
- for(ulLoop = 0; ulLoop < NUM_PRIORITY; ulLoop++)
- {
- //
- // Stop looping if this value matches.
- //
- if(ulValue == g_pulPriority[ulLoop])
- {
- break;
- }
- }
-
- //
- // Return the number of priority bits.
- //
- return(ulLoop);
-}
-
-//*****************************************************************************
-//
-//! Sets the priority of an interrupt.
-//!
-//! \param ulInterrupt specifies the interrupt in question.
-//! \param ucPriority specifies the priority of the interrupt.
-//!
-//! This function is used to set the priority of an interrupt. When multiple
-//! interrupts are asserted simultaneously, the ones with the highest priority
-//! are processed before the lower priority interrupts. Smaller numbers
-//! correspond to higher interrupt priorities; priority 0 is the highest
-//! interrupt priority.
-//!
-//! The hardware priority mechanism will only look at the upper N bits of the
-//! priority level (where N is 3 for the Stellaris family), so any
-//! prioritization must be performed in those bits. The remaining bits can be
-//! used to sub-prioritize the interrupt sources, and may be used by the
-//! hardware priority mechanism on a future part. This arrangement allows
-//! priorities to migrate to different NVIC implementations without changing
-//! the gross prioritization of the interrupts.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-IntPrioritySet(unsigned long ulInterrupt, unsigned char ucPriority)
-{
- unsigned long ulTemp;
-
- //
- // Check the arguments.
- //
- ASSERT((ulInterrupt >= 4) && (ulInterrupt < NUM_INTERRUPTS));
-
- //
- // Set the interrupt priority.
- //
- ulTemp = HWREG(g_pulRegs[ulInterrupt >> 2]);
- ulTemp &= ~(0xFF << (8 * (ulInterrupt & 3)));
- ulTemp |= ucPriority << (8 * (ulInterrupt & 3));
- HWREG(g_pulRegs[ulInterrupt >> 2]) = ulTemp;
-}
-
-//*****************************************************************************
-//
-//! Gets the priority of an interrupt.
-//!
-//! \param ulInterrupt specifies the interrupt in question.
-//!
-//! This function gets the priority of an interrupt. See IntPrioritySet() for
-//! a definition of the priority value.
-//!
-//! \return Returns the interrupt priority, or -1 if an invalid interrupt was
-//! specified.
-//
-//*****************************************************************************
-long
-IntPriorityGet(unsigned long ulInterrupt)
-{
- //
- // Check the arguments.
- //
- ASSERT((ulInterrupt >= 4) && (ulInterrupt < NUM_INTERRUPTS));
-
- //
- // Return the interrupt priority.
- //
- return((HWREG(g_pulRegs[ulInterrupt >> 2]) >> (8 * (ulInterrupt & 3))) &
- 0xFF);
-}
-
-//*****************************************************************************
-//
-//! Enables an interrupt.
-//!
-//! \param ulInterrupt specifies the interrupt to be enabled.
-//!
-//! The specified interrupt is enabled in the interrupt controller. Other
-//! enables for the interrupt (such as at the peripheral level) are unaffected
-//! by this function.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-IntEnable(unsigned long ulInterrupt)
-{
- //
- // Check the arguments.
- //
- ASSERT(ulInterrupt < NUM_INTERRUPTS);
-
- //
- // Determine the interrupt to enable.
- //
- if(ulInterrupt == FAULT_MPU)
- {
- //
- // Enable the MemManage interrupt.
- //
- HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_MEM;
- }
- else if(ulInterrupt == FAULT_BUS)
- {
- //
- // Enable the bus fault interrupt.
- //
- HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_BUS;
- }
- else if(ulInterrupt == FAULT_USAGE)
- {
- //
- // Enable the usage fault interrupt.
- //
- HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_USAGE;
- }
- else if(ulInterrupt == FAULT_SYSTICK)
- {
- //
- // Enable the System Tick interrupt.
- //
- HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN;
- }
- else if((ulInterrupt >= 16) && (ulInterrupt <= 47))
- {
- //
- // Enable the general interrupt.
- //
- HWREG(NVIC_EN0) = 1 << (ulInterrupt - 16);
- }
- else if(ulInterrupt >= 48)
- {
- //
- // Enable the general interrupt.
- //
- HWREG(NVIC_EN1) = 1 << (ulInterrupt - 48);
- }
-}
-
-//*****************************************************************************
-//
-//! Disables an interrupt.
-//!
-//! \param ulInterrupt specifies the interrupt to be disabled.
-//!
-//! The specified interrupt is disabled in the interrupt controller. Other
-//! enables for the interrupt (such as at the peripheral level) are unaffected
-//! by this function.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-IntDisable(unsigned long ulInterrupt)
-{
- //
- // Check the arguments.
- //
- ASSERT(ulInterrupt < NUM_INTERRUPTS);
-
- //
- // Determine the interrupt to disable.
- //
- if(ulInterrupt == FAULT_MPU)
- {
- //
- // Disable the MemManage interrupt.
- //
- HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_MEM);
- }
- else if(ulInterrupt == FAULT_BUS)
- {
- //
- // Disable the bus fault interrupt.
- //
- HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_BUS);
- }
- else if(ulInterrupt == FAULT_USAGE)
- {
- //
- // Disable the usage fault interrupt.
- //
- HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_USAGE);
- }
- else if(ulInterrupt == FAULT_SYSTICK)
- {
- //
- // Disable the System Tick interrupt.
- //
- HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN);
- }
- else if((ulInterrupt >= 16) && (ulInterrupt <= 47))
- {
- //
- // Disable the general interrupt.
- //
- HWREG(NVIC_DIS0) = 1 << (ulInterrupt - 16);
- }
- else if(ulInterrupt >= 48)
- {
- //
- // Disable the general interrupt.
- //
- HWREG(NVIC_DIS1) = 1 << (ulInterrupt - 48);
- }
-}
-
-//*****************************************************************************
-//
-// Close the Doxygen group.
-//! @}
-//
-//*****************************************************************************
+//*****************************************************************************
+//
+// interrupt.c - Driver for the NVIC Interrupt Controller.
+//
+// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup interrupt_api
+//! @{
+//
+//*****************************************************************************
+
+#include "hw_ints.h"
+#include "hw_nvic.h"
+#include "hw_types.h"
+#include "cpu.h"
+#include "debug.h"
+#include "interrupt.h"
+
+//*****************************************************************************
+//
+// This is a mapping between priority grouping encodings and the number of
+// preemption priority bits.
+//
+//*****************************************************************************
+static const unsigned long g_pulPriority[] =
+{
+ NVIC_APINT_PRIGROUP_0_8, NVIC_APINT_PRIGROUP_1_7, NVIC_APINT_PRIGROUP_2_6,
+ NVIC_APINT_PRIGROUP_3_5, NVIC_APINT_PRIGROUP_4_4, NVIC_APINT_PRIGROUP_5_3,
+ NVIC_APINT_PRIGROUP_6_2, NVIC_APINT_PRIGROUP_7_1
+};
+
+//*****************************************************************************
+//
+// This is a mapping between interrupt number and the register that contains
+// the priority encoding for that interrupt.
+//
+//*****************************************************************************
+static const unsigned long g_pulRegs[] =
+{
+ 0, NVIC_SYS_PRI1, NVIC_SYS_PRI2, NVIC_SYS_PRI3, NVIC_PRI0, NVIC_PRI1,
+ NVIC_PRI2, NVIC_PRI3, NVIC_PRI4, NVIC_PRI5, NVIC_PRI6, NVIC_PRI7,
+ NVIC_PRI8, NVIC_PRI9, NVIC_PRI10, NVIC_PRI11, NVIC_PRI12, NVIC_PRI13
+};
+
+//*****************************************************************************
+//
+//! \internal
+//! The default interrupt handler.
+//!
+//! This is the default interrupt handler for all interrupts. It simply loops
+//! forever so that the system state is preserved for observation by a
+//! debugger. Since interrupts should be disabled before unregistering the
+//! corresponding handler, this should never be called.
+//!
+//! \return None.
+//
+//*****************************************************************************
+static void
+IntDefaultHandler(void)
+{
+ //
+ // Go into an infinite loop.
+ //
+ while(1)
+ {
+ }
+}
+
+//*****************************************************************************
+//
+// The processor vector table.
+//
+// This contains a list of the handlers for the various interrupt sources in
+// the system. The layout of this list is defined by the hardware; assertion
+// of an interrupt causes the processor to start executing directly at the
+// address given in the corresponding location in this list.
+//
+//*****************************************************************************
+#if defined(ewarm)
+static __no_init void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) @ "VTABLE";
+#elif defined(sourcerygxx)
+static __attribute__((section(".cs3.region-head.ram")))
+void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void);
+#else
+static __attribute__((section("vtable")))
+void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void);
+#endif
+
+//*****************************************************************************
+//
+//! Enables the processor interrupt.
+//!
+//! Allows the processor to respond to interrupts. This does not affect the
+//! set of interrupts enabled in the interrupt controller; it just gates the
+//! single interrupt from the controller to the processor.
+//!
+//! \note Previously, this function had no return value. As such, it was
+//! possible to include <tt>interrupt.h</tt> and call this function without
+//! having included <tt>hw_types.h</tt>. Now that the return is a
+//! <tt>tBoolean</tt>, a compiler error will occur in this case. The solution
+//! is to include <tt>hw_types.h</tt> before including <tt>interrupt.h</tt>.
+//!
+//! \return Returns \b true if interrupts were disabled when the function was
+//! called or \b false if they were initially enabled.
+//
+//*****************************************************************************
+tBoolean
+IntMasterEnable(void)
+{
+ //
+ // Enable processor interrupts.
+ //
+ return(CPUcpsie());
+}
+
+//*****************************************************************************
+//
+//! Disables the processor interrupt.
+//!
+//! Prevents the processor from receiving interrupts. This does not affect the
+//! set of interrupts enabled in the interrupt controller; it just gates the
+//! single interrupt from the controller to the processor.
+//!
+//! \note Previously, this function had no return value. As such, it was
+//! possible to include <tt>interrupt.h</tt> and call this function without
+//! having included <tt>hw_types.h</tt>. Now that the return is a
+//! <tt>tBoolean</tt>, a compiler error will occur in this case. The solution
+//! is to include <tt>hw_types.h</tt> before including <tt>interrupt.h</tt>.
+//!
+//! \return Returns \b true if interrupts were already disabled when the
+//! function was called or \b false if they were initially enabled.
+//
+//*****************************************************************************
+tBoolean
+IntMasterDisable(void)
+{
+ //
+ // Disable processor interrupts.
+ //
+ return(CPUcpsid());
+}
+
+//*****************************************************************************
+//
+//! Registers a function to be called when an interrupt occurs.
+//!
+//! \param ulInterrupt specifies the interrupt in question.
+//! \param pfnHandler is a pointer to the function to be called.
+//!
+//! This function is used to specify the handler function to be called when the
+//! given interrupt is asserted to the processor. When the interrupt occurs,
+//! if it is enabled (via IntEnable()), the handler function will be called in
+//! interrupt context. Since the handler function can preempt other code, care
+//! must be taken to protect memory or peripherals that are accessed by the
+//! handler and other non-handler code.
+//!
+//! \note The use of this function (directly or indirectly via a peripheral
+//! driver interrupt register function) moves the interrupt vector table from
+//! flash to SRAM. Therefore, care must be taken when linking the application
+//! to ensure that the SRAM vector table is located at the beginning of SRAM;
+//! otherwise NVIC will not look in the correct portion of memory for the
+//! vector table (it requires the vector table be on a 1 kB memory alignment).
+//! Normally, the SRAM vector table is so placed via the use of linker scripts;
+//! some tool chains, such as the evaluation version of RV-MDK, do not support
+//! linker scripts and therefore will not produce a valid executable. See the
+//! discussion of compile-time versus run-time interrupt handler registration
+//! in the introduction to this chapter.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void))
+{
+ unsigned long ulIdx, ulValue;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulInterrupt < NUM_INTERRUPTS);
+
+ //
+ // Make sure that the RAM vector table is correctly aligned.
+ //
+ ASSERT(((unsigned long)g_pfnRAMVectors & 0x000003ff) == 0);
+
+ //
+ // See if the RAM vector table has been initialized.
+ //
+ if(HWREG(NVIC_VTABLE) != (unsigned long)g_pfnRAMVectors)
+ {
+ //
+ // Copy the vector table from the beginning of FLASH to the RAM vector
+ // table.
+ //
+ ulValue = HWREG(NVIC_VTABLE);
+ for(ulIdx = 0; ulIdx < NUM_INTERRUPTS; ulIdx++)
+ {
+ g_pfnRAMVectors[ulIdx] = (void (*)(void))HWREG((ulIdx * 4) +
+ ulValue);
+ }
+
+ //
+ // Point NVIC at the RAM vector table.
+ //
+ HWREG(NVIC_VTABLE) = (unsigned long)g_pfnRAMVectors;
+ }
+
+ //
+ // Save the interrupt handler.
+ //
+ g_pfnRAMVectors[ulInterrupt] = pfnHandler;
+}
+
+//*****************************************************************************
+//
+//! Unregisters the function to be called when an interrupt occurs.
+//!
+//! \param ulInterrupt specifies the interrupt in question.
+//!
+//! This function is used to indicate that no handler should be called when the
+//! given interrupt is asserted to the processor. The interrupt source will be
+//! automatically disabled (via IntDisable()) if necessary.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+IntUnregister(unsigned long ulInterrupt)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulInterrupt < NUM_INTERRUPTS);
+
+ //
+ // Reset the interrupt handler.
+ //
+ g_pfnRAMVectors[ulInterrupt] = IntDefaultHandler;
+}
+
+//*****************************************************************************
+//
+//! Sets the priority grouping of the interrupt controller.
+//!
+//! \param ulBits specifies the number of bits of preemptable priority.
+//!
+//! This function specifies the split between preemptable priority levels and
+//! subpriority levels in the interrupt priority specification. The range of
+//! the grouping values are dependent upon the hardware implementation; on
+//! the Stellaris family, three bits are available for hardware interrupt
+//! prioritization and therefore priority grouping values of three through
+//! seven have the same effect.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+IntPriorityGroupingSet(unsigned long ulBits)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBits < NUM_PRIORITY);
+
+ //
+ // Set the priority grouping.
+ //
+ HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | g_pulPriority[ulBits];
+}
+
+//*****************************************************************************
+//
+//! Gets the priority grouping of the interrupt controller.
+//!
+//! This function returns the split between preemptable priority levels and
+//! subpriority levels in the interrupt priority specification.
+//!
+//! \return The number of bits of preemptable priority.
+//
+//*****************************************************************************
+unsigned long
+IntPriorityGroupingGet(void)
+{
+ unsigned long ulLoop, ulValue;
+
+ //
+ // Read the priority grouping.
+ //
+ ulValue = HWREG(NVIC_APINT) & NVIC_APINT_PRIGROUP_M;
+
+ //
+ // Loop through the priority grouping values.
+ //
+ for(ulLoop = 0; ulLoop < NUM_PRIORITY; ulLoop++)
+ {
+ //
+ // Stop looping if this value matches.
+ //
+ if(ulValue == g_pulPriority[ulLoop])
+ {
+ break;
+ }
+ }
+
+ //
+ // Return the number of priority bits.
+ //
+ return(ulLoop);
+}
+
+//*****************************************************************************
+//
+//! Sets the priority of an interrupt.
+//!
+//! \param ulInterrupt specifies the interrupt in question.
+//! \param ucPriority specifies the priority of the interrupt.
+//!
+//! This function is used to set the priority of an interrupt. When multiple
+//! interrupts are asserted simultaneously, the ones with the highest priority
+//! are processed before the lower priority interrupts. Smaller numbers
+//! correspond to higher interrupt priorities; priority 0 is the highest
+//! interrupt priority.
+//!
+//! The hardware priority mechanism will only look at the upper N bits of the
+//! priority level (where N is 3 for the Stellaris family), so any
+//! prioritization must be performed in those bits. The remaining bits can be
+//! used to sub-prioritize the interrupt sources, and may be used by the
+//! hardware priority mechanism on a future part. This arrangement allows
+//! priorities to migrate to different NVIC implementations without changing
+//! the gross prioritization of the interrupts.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+IntPrioritySet(unsigned long ulInterrupt, unsigned char ucPriority)
+{
+ unsigned long ulTemp;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulInterrupt >= 4) && (ulInterrupt < NUM_INTERRUPTS));
+
+ //
+ // Set the interrupt priority.
+ //
+ ulTemp = HWREG(g_pulRegs[ulInterrupt >> 2]);
+ ulTemp &= ~(0xFF << (8 * (ulInterrupt & 3)));
+ ulTemp |= ucPriority << (8 * (ulInterrupt & 3));
+ HWREG(g_pulRegs[ulInterrupt >> 2]) = ulTemp;
+}
+
+//*****************************************************************************
+//
+//! Gets the priority of an interrupt.
+//!
+//! \param ulInterrupt specifies the interrupt in question.
+//!
+//! This function gets the priority of an interrupt. See IntPrioritySet() for
+//! a definition of the priority value.
+//!
+//! \return Returns the interrupt priority, or -1 if an invalid interrupt was
+//! specified.
+//
+//*****************************************************************************
+long
+IntPriorityGet(unsigned long ulInterrupt)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulInterrupt >= 4) && (ulInterrupt < NUM_INTERRUPTS));
+
+ //
+ // Return the interrupt priority.
+ //
+ return((HWREG(g_pulRegs[ulInterrupt >> 2]) >> (8 * (ulInterrupt & 3))) &
+ 0xFF);
+}
+
+//*****************************************************************************
+//
+//! Enables an interrupt.
+//!
+//! \param ulInterrupt specifies the interrupt to be enabled.
+//!
+//! The specified interrupt is enabled in the interrupt controller. Other
+//! enables for the interrupt (such as at the peripheral level) are unaffected
+//! by this function.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+IntEnable(unsigned long ulInterrupt)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulInterrupt < NUM_INTERRUPTS);
+
+ //
+ // Determine the interrupt to enable.
+ //
+ if(ulInterrupt == FAULT_MPU)
+ {
+ //
+ // Enable the MemManage interrupt.
+ //
+ HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_MEM;
+ }
+ else if(ulInterrupt == FAULT_BUS)
+ {
+ //
+ // Enable the bus fault interrupt.
+ //
+ HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_BUS;
+ }
+ else if(ulInterrupt == FAULT_USAGE)
+ {
+ //
+ // Enable the usage fault interrupt.
+ //
+ HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_USAGE;
+ }
+ else if(ulInterrupt == FAULT_SYSTICK)
+ {
+ //
+ // Enable the System Tick interrupt.
+ //
+ HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN;
+ }
+ else if((ulInterrupt >= 16) && (ulInterrupt <= 47))
+ {
+ //
+ // Enable the general interrupt.
+ //
+ HWREG(NVIC_EN0) = 1 << (ulInterrupt - 16);
+ }
+ else if(ulInterrupt >= 48)
+ {
+ //
+ // Enable the general interrupt.
+ //
+ HWREG(NVIC_EN1) = 1 << (ulInterrupt - 48);
+ }
+}
+
+//*****************************************************************************
+//
+//! Disables an interrupt.
+//!
+//! \param ulInterrupt specifies the interrupt to be disabled.
+//!
+//! The specified interrupt is disabled in the interrupt controller. Other
+//! enables for the interrupt (such as at the peripheral level) are unaffected
+//! by this function.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+IntDisable(unsigned long ulInterrupt)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulInterrupt < NUM_INTERRUPTS);
+
+ //
+ // Determine the interrupt to disable.
+ //
+ if(ulInterrupt == FAULT_MPU)
+ {
+ //
+ // Disable the MemManage interrupt.
+ //
+ HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_MEM);
+ }
+ else if(ulInterrupt == FAULT_BUS)
+ {
+ //
+ // Disable the bus fault interrupt.
+ //
+ HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_BUS);
+ }
+ else if(ulInterrupt == FAULT_USAGE)
+ {
+ //
+ // Disable the usage fault interrupt.
+ //
+ HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_USAGE);
+ }
+ else if(ulInterrupt == FAULT_SYSTICK)
+ {
+ //
+ // Disable the System Tick interrupt.
+ //
+ HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN);
+ }
+ else if((ulInterrupt >= 16) && (ulInterrupt <= 47))
+ {
+ //
+ // Disable the general interrupt.
+ //
+ HWREG(NVIC_DIS0) = 1 << (ulInterrupt - 16);
+ }
+ else if(ulInterrupt >= 48)
+ {
+ //
+ // Disable the general interrupt.
+ //
+ HWREG(NVIC_DIS1) = 1 << (ulInterrupt - 48);
+ }
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
Property changes on: branches/eagle_mmc/src/platform/lm3s/interrupt.c
___________________________________________________________________
Name: svn:executable
+ *
Modified: branches/eagle_mmc/src/platform/lm3s/interrupt.h
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/interrupt.h 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lm3s/interrupt.h 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,76 +1,76 @@
-//*****************************************************************************
-//
-// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver.
-//
-// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
-// Software License Agreement
-//
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
-//
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws. All rights are reserved. You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program. Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
-//
-// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-//
-// This is part of revision 3740 of the Stellaris Peripheral Driver Library.
-//
-//*****************************************************************************
-
-#ifndef __INTERRUPT_H__
-#define __INTERRUPT_H__
-
-//*****************************************************************************
-//
-// If building with a C++ compiler, make all of the definitions in this header
-// have a C binding.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-//*****************************************************************************
-//
-// Macro to generate an interrupt priority mask based on the number of bits
-// of priority supported by the hardware.
-//
-//*****************************************************************************
-#define INT_PRIORITY_MASK ((0xFF << (8 - NUM_PRIORITY_BITS)) & 0xFF)
-
-//*****************************************************************************
-//
-// Prototypes for the APIs.
-//
-//*****************************************************************************
-extern tBoolean IntMasterEnable(void);
-extern tBoolean IntMasterDisable(void);
-extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void));
-extern void IntUnregister(unsigned long ulInterrupt);
-extern void IntPriorityGroupingSet(unsigned long ulBits);
-extern unsigned long IntPriorityGroupingGet(void);
-extern void IntPrioritySet(unsigned long ulInterrupt,
- unsigned char ucPriority);
-extern long IntPriorityGet(unsigned long ulInterrupt);
-extern void IntEnable(unsigned long ulInterrupt);
-extern void IntDisable(unsigned long ulInterrupt);
-
-//*****************************************************************************
-//
-// Mark the end of the C bindings section for C++ compilers.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-}
-#endif
-
-#endif // __INTERRUPT_H__
+//*****************************************************************************
+//
+// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver.
+//
+// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __INTERRUPT_H__
+#define __INTERRUPT_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Macro to generate an interrupt priority mask based on the number of bits
+// of priority supported by the hardware.
+//
+//*****************************************************************************
+#define INT_PRIORITY_MASK ((0xFF << (8 - NUM_PRIORITY_BITS)) & 0xFF)
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern tBoolean IntMasterEnable(void);
+extern tBoolean IntMasterDisable(void);
+extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void));
+extern void IntUnregister(unsigned long ulInterrupt);
+extern void IntPriorityGroupingSet(unsigned long ulBits);
+extern unsigned long IntPriorityGroupingGet(void);
+extern void IntPrioritySet(unsigned long ulInterrupt,
+ unsigned char ucPriority);
+extern long IntPriorityGet(unsigned long ulInterrupt);
+extern void IntEnable(unsigned long ulInterrupt);
+extern void IntDisable(unsigned long ulInterrupt);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __INTERRUPT_H__
Property changes on: branches/eagle_mmc/src/platform/lm3s/interrupt.h
___________________________________________________________________
Name: svn:executable
+ *
Added: branches/eagle_mmc/src/platform/lm3s/lm3s-9b92.ld
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/lm3s-9b92.ld 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lm3s/lm3s-9b92.ld 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,64 @@
+MEMORY
+{
+ sram (W!RX) : ORIGIN = 0x20000000, LENGTH = 0x00018000
+ flash (RX) : ORIGIN = 0x00000000, LENGTH = 0x00040000
+}
+
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ _text = .;
+ PROVIDE(stext = .);
+ KEEP(*(.isr_vector))
+ KEEP(*(.init))
+ *(.text .text.*)
+ *(.rodata .rodata.*)
+ *(.gnu.linkonce.t.*)
+ *(.glue_7)
+ *(.glue_7t)
+ *(.gcc_except_table)
+ *(.gnu.linkonce.r.*)
+ . = ALIGN(4);
+ _etext = .;
+ PROVIDE(etext = .);
+ _fini = . ;
+ *(.fini)
+
+ } >flash
+
+ .data : AT (_etext)
+ {
+ . = ALIGN(4);
+ _data = .;
+ *(.ramfunc .ramfunc.* .fastrun .fastrun.*)
+ *(.data .data.*)
+ *(.gnu.linkonce.d.*)
+ . = ALIGN(4);
+ _edata = .;
+ } >sram
+
+ .ARM.extab :
+ {
+ *(.ARM.extab*)
+ } >sram
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx*)
+ } >sram
+ __exidx_end = .;
+
+ .bss (NOLOAD) : {
+ _bss = .;
+ *(.bss .bss.*)
+ *(.gnu.linkonce.b.*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = .;
+ } >sram
+
+ end = .;
+}
Added: branches/eagle_mmc/src/platform/lm3s/lm3s6918.h
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/lm3s6918.h 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lm3s/lm3s6918.h 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,4036 @@
+//*****************************************************************************
+//
+// lm3s6918.h - LM3S6918 Register Definitions
+//
+// Copyright (c) 2007-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4781 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __LM3S6918_H__
+#define __LM3S6918_H__
+
+//*****************************************************************************
+//
+// Watchdog Timer (WATCHDOG)
+//
+//*****************************************************************************
+#define WATCHDOG_LOAD_R (*((volatile unsigned long *)0x40000000))
+#define WATCHDOG_VALUE_R (*((volatile unsigned long *)0x40000004))
+#define WATCHDOG_CTL_R (*((volatile unsigned long *)0x40000008))
+#define WATCHDOG_ICR_R (*((volatile unsigned long *)0x4000000C))
+#define WATCHDOG_RIS_R (*((volatile unsigned long *)0x40000010))
+#define WATCHDOG_MIS_R (*((volatile unsigned long *)0x40000014))
+#define WATCHDOG_TEST_R (*((volatile unsigned long *)0x40000418))
+#define WATCHDOG_LOCK_R (*((volatile unsigned long *)0x40000C00))
+
+//*****************************************************************************
+//
+// General-Purpose Input/Outputs (PORTA)
+//
+//*****************************************************************************
+#define GPIO_PORTA_DATA_BITS_R ((volatile unsigned long *)0x40004000)
+#define GPIO_PORTA_DATA_R (*((volatile unsigned long *)0x400043FC))
+#define GPIO_PORTA_DIR_R (*((volatile unsigned long *)0x40004400))
+#define GPIO_PORTA_IS_R (*((volatile unsigned long *)0x40004404))
+#define GPIO_PORTA_IBE_R (*((volatile unsigned long *)0x40004408))
+#define GPIO_PORTA_IEV_R (*((volatile unsigned long *)0x4000440C))
+#define GPIO_PORTA_IM_R (*((volatile unsigned long *)0x40004410))
+#define GPIO_PORTA_RIS_R (*((volatile unsigned long *)0x40004414))
+#define GPIO_PORTA_MIS_R (*((volatile unsigned long *)0x40004418))
+#define GPIO_PORTA_ICR_R (*((volatile unsigned long *)0x4000441C))
+#define GPIO_PORTA_AFSEL_R (*((volatile unsigned long *)0x40004420))
+#define GPIO_PORTA_DR2R_R (*((volatile unsigned long *)0x40004500))
+#define GPIO_PORTA_DR4R_R (*((volatile unsigned long *)0x40004504))
+#define GPIO_PORTA_DR8R_R (*((volatile unsigned long *)0x40004508))
+#define GPIO_PORTA_ODR_R (*((volatile unsigned long *)0x4000450C))
+#define GPIO_PORTA_PUR_R (*((volatile unsigned long *)0x40004510))
+#define GPIO_PORTA_PDR_R (*((volatile unsigned long *)0x40004514))
+#define GPIO_PORTA_SLR_R (*((volatile unsigned long *)0x40004518))
+#define GPIO_PORTA_DEN_R (*((volatile unsigned long *)0x4000451C))
+#define GPIO_PORTA_LOCK_R (*((volatile unsigned long *)0x40004520))
+#define GPIO_PORTA_CR_R (*((volatile unsigned long *)0x40004524))
+
+//*****************************************************************************
+//
+// General-Purpose Input/Outputs (PORTB)
+//
+//*****************************************************************************
+#define GPIO_PORTB_DATA_BITS_R ((volatile unsigned long *)0x40005000)
+#define GPIO_PORTB_DATA_R (*((volatile unsigned long *)0x400053FC))
+#define GPIO_PORTB_DIR_R (*((volatile unsigned long *)0x40005400))
+#define GPIO_PORTB_IS_R (*((volatile unsigned long *)0x40005404))
+#define GPIO_PORTB_IBE_R (*((volatile unsigned long *)0x40005408))
+#define GPIO_PORTB_IEV_R (*((volatile unsigned long *)0x4000540C))
+#define GPIO_PORTB_IM_R (*((volatile unsigned long *)0x40005410))
+#define GPIO_PORTB_RIS_R (*((volatile unsigned long *)0x40005414))
+#define GPIO_PORTB_MIS_R (*((volatile unsigned long *)0x40005418))
+#define GPIO_PORTB_ICR_R (*((volatile unsigned long *)0x4000541C))
+#define GPIO_PORTB_AFSEL_R (*((volatile unsigned long *)0x40005420))
+#define GPIO_PORTB_DR2R_R (*((volatile unsigned long *)0x40005500))
+#define GPIO_PORTB_DR4R_R (*((volatile unsigned long *)0x40005504))
+#define GPIO_PORTB_DR8R_R (*((volatile unsigned long *)0x40005508))
+#define GPIO_PORTB_ODR_R (*((volatile unsigned long *)0x4000550C))
+#define GPIO_PORTB_PUR_R (*((volatile unsigned long *)0x40005510))
+#define GPIO_PORTB_PDR_R (*((volatile unsigned long *)0x40005514))
+#define GPIO_PORTB_SLR_R (*((volatile unsigned long *)0x40005518))
+#define GPIO_PORTB_DEN_R (*((volatile unsigned long *)0x4000551C))
+#define GPIO_PORTB_LOCK_R (*((volatile unsigned long *)0x40005520))
+#define GPIO_PORTB_CR_R (*((volatile unsigned long *)0x40005524))
+
+//*****************************************************************************
+//
+// General-Purpose Input/Outputs (PORTC)
+//
+//*****************************************************************************
+#define GPIO_PORTC_DATA_BITS_R ((volatile unsigned long *)0x40006000)
+#define GPIO_PORTC_DATA_R (*((volatile unsigned long *)0x400063FC))
+#define GPIO_PORTC_DIR_R (*((volatile unsigned long *)0x40006400))
+#define GPIO_PORTC_IS_R (*((volatile unsigned long *)0x40006404))
+#define GPIO_PORTC_IBE_R (*((volatile unsigned long *)0x40006408))
+#define GPIO_PORTC_IEV_R (*((volatile unsigned long *)0x4000640C))
+#define GPIO_PORTC_IM_R (*((volatile unsigned long *)0x40006410))
+#define GPIO_PORTC_RIS_R (*((volatile unsigned long *)0x40006414))
+#define GPIO_PORTC_MIS_R (*((volatile unsigned long *)0x40006418))
+#define GPIO_PORTC_ICR_R (*((volatile unsigned long *)0x4000641C))
+#define GPIO_PORTC_AFSEL_R (*((volatile unsigned long *)0x40006420))
+#define GPIO_PORTC_DR2R_R (*((volatile unsigned long *)0x40006500))
+#define GPIO_PORTC_DR4R_R (*((volatile unsigned long *)0x40006504))
+#define GPIO_PORTC_DR8R_R (*((volatile unsigned long *)0x40006508))
+#define GPIO_PORTC_ODR_R (*((volatile unsigned long *)0x4000650C))
+#define GPIO_PORTC_PUR_R (*((volatile unsigned long *)0x40006510))
+#define GPIO_PORTC_PDR_R (*((volatile unsigned long *)0x40006514))
+#define GPIO_PORTC_SLR_R (*((volatile unsigned long *)0x40006518))
+#define GPIO_PORTC_DEN_R (*((volatile unsigned long *)0x4000651C))
+#define GPIO_PORTC_LOCK_R (*((volatile unsigned long *)0x40006520))
+#define GPIO_PORTC_CR_R (*((volatile unsigned long *)0x40006524))
+
+//*****************************************************************************
+//
+// General-Purpose Input/Outputs (PORTD)
+//
+//*****************************************************************************
+#define GPIO_PORTD_DATA_BITS_R ((volatile unsigned long *)0x40007000)
+#define GPIO_PORTD_DATA_R (*((volatile unsigned long *)0x400073FC))
+#define GPIO_PORTD_DIR_R (*((volatile unsigned long *)0x40007400))
+#define GPIO_PORTD_IS_R (*((volatile unsigned long *)0x40007404))
+#define GPIO_PORTD_IBE_R (*((volatile unsigned long *)0x40007408))
+#define GPIO_PORTD_IEV_R (*((volatile unsigned long *)0x4000740C))
+#define GPIO_PORTD_IM_R (*((volatile unsigned long *)0x40007410))
+#define GPIO_PORTD_RIS_R (*((volatile unsigned long *)0x40007414))
+#define GPIO_PORTD_MIS_R (*((volatile unsigned long *)0x40007418))
+#define GPIO_PORTD_ICR_R (*((volatile unsigned long *)0x4000741C))
+#define GPIO_PORTD_AFSEL_R (*((volatile unsigned long *)0x40007420))
+#define GPIO_PORTD_DR2R_R (*((volatile unsigned long *)0x40007500))
+#define GPIO_PORTD_DR4R_R (*((volatile unsigned long *)0x40007504))
+#define GPIO_PORTD_DR8R_R (*((volatile unsigned long *)0x40007508))
+#define GPIO_PORTD_ODR_R (*((volatile unsigned long *)0x4000750C))
+#define GPIO_PORTD_PUR_R (*((volatile unsigned long *)0x40007510))
+#define GPIO_PORTD_PDR_R (*((volatile unsigned long *)0x40007514))
+#define GPIO_PORTD_SLR_R (*((volatile unsigned long *)0x40007518))
+#define GPIO_PORTD_DEN_R (*((volatile unsigned long *)0x4000751C))
+#define GPIO_PORTD_LOCK_R (*((volatile unsigned long *)0x40007520))
+#define GPIO_PORTD_CR_R (*((volatile unsigned long *)0x40007524))
+
+//*****************************************************************************
+//
+// Synchronous Serial Interface (SSI0)
+//
+//*****************************************************************************
+#define SSI0_CR0_R (*((volatile unsigned long *)0x40008000))
+#define SSI0_CR1_R (*((volatile unsigned long *)0x40008004))
+#define SSI0_DR_R (*((volatile unsigned long *)0x40008008))
+#define SSI0_SR_R (*((volatile unsigned long *)0x4000800C))
+#define SSI0_CPSR_R (*((volatile unsigned long *)0x40008010))
+#define SSI0_IM_R (*((volatile unsigned long *)0x40008014))
+#define SSI0_RIS_R (*((volatile unsigned long *)0x40008018))
+#define SSI0_MIS_R (*((volatile unsigned long *)0x4000801C))
+#define SSI0_ICR_R (*((volatile unsigned long *)0x40008020))
+
+//*****************************************************************************
+//
+// Synchronous Serial Interface (SSI1)
+//
+//*****************************************************************************
+#define SSI1_CR0_R (*((volatile unsigned long *)0x40009000))
+#define SSI1_CR1_R (*((volatile unsigned long *)0x40009004))
+#define SSI1_DR_R (*((volatile unsigned long *)0x40009008))
+#define SSI1_SR_R (*((volatile unsigned long *)0x4000900C))
+#define SSI1_CPSR_R (*((volatile unsigned long *)0x40009010))
+#define SSI1_IM_R (*((volatile unsigned long *)0x40009014))
+#define SSI1_RIS_R (*((volatile unsigned long *)0x40009018))
+#define SSI1_MIS_R (*((volatile unsigned long *)0x4000901C))
+#define SSI1_ICR_R (*((volatile unsigned long *)0x40009020))
+
+//*****************************************************************************
+//
+// Universal Asynchronous Receivers/Transmitters (UART0)
+//
+//*****************************************************************************
+#define UART0_DR_R (*((volatile unsigned long *)0x4000C000))
+#define UART0_RSR_R (*((volatile unsigned long *)0x4000C004))
+#define UART0_ECR_R (*((volatile unsigned long *)0x4000C004))
+#define UART0_FR_R (*((volatile unsigned long *)0x4000C018))
+#define UART0_ILPR_R (*((volatile unsigned long *)0x4000C020))
+#define UART0_IBRD_R (*((volatile unsigned long *)0x4000C024))
+#define UART0_FBRD_R (*((volatile unsigned long *)0x4000C028))
+#define UART0_LCRH_R (*((volatile unsigned long *)0x4000C02C))
+#define UART0_CTL_R (*((volatile unsigned long *)0x4000C030))
+#define UART0_IFLS_R (*((volatile unsigned long *)0x4000C034))
+#define UART0_IM_R (*((volatile unsigned long *)0x4000C038))
+#define UART0_RIS_R (*((volatile unsigned long *)0x4000C03C))
+#define UART0_MIS_R (*((volatile unsigned long *)0x4000C040))
+#define UART0_ICR_R (*((volatile unsigned long *)0x4000C044))
+
+//*****************************************************************************
+//
+// Universal Asynchronous Receivers/Transmitters (UART1)
+//
+//*****************************************************************************
+#define UART1_DR_R (*((volatile unsigned long *)0x4000D000))
+#define UART1_RSR_R (*((volatile unsigned long *)0x4000D004))
+#define UART1_ECR_R (*((volatile unsigned long *)0x4000D004))
+#define UART1_FR_R (*((volatile unsigned long *)0x4000D018))
+#define UART1_ILPR_R (*((volatile unsigned long *)0x4000D020))
+#define UART1_IBRD_R (*((volatile unsigned long *)0x4000D024))
+#define UART1_FBRD_R (*((volatile unsigned long *)0x4000D028))
+#define UART1_LCRH_R (*((volatile unsigned long *)0x4000D02C))
+#define UART1_CTL_R (*((volatile unsigned long *)0x4000D030))
+#define UART1_IFLS_R (*((volatile unsigned long *)0x4000D034))
+#define UART1_IM_R (*((volatile unsigned long *)0x4000D038))
+#define UART1_RIS_R (*((volatile unsigned long *)0x4000D03C))
+#define UART1_MIS_R (*((volatile unsigned long *)0x4000D040))
+#define UART1_ICR_R (*((volatile unsigned long *)0x4000D044))
+
+//*****************************************************************************
+//
+// Inter-Integrated Circuit (MASTER) Interface
+//
+//*****************************************************************************
+#define I2C0_MASTER_MSA_R (*((volatile unsigned long *)0x40020000))
+#define I2C0_MASTER_SOAR_R (*((volatile unsigned long *)0x40020000))
+#define I2C0_MASTER_SCSR_R (*((volatile unsigned long *)0x40020004))
+#define I2C0_MASTER_MCS_R (*((volatile unsigned long *)0x40020004))
+#define I2C0_MASTER_SDR_R (*((volatile unsigned long *)0x40020008))
+#define I2C0_MASTER_MDR_R (*((volatile unsigned long *)0x40020008))
+#define I2C0_MASTER_MTPR_R (*((volatile unsigned long *)0x4002000C))
+#define I2C0_MASTER_SIMR_R (*((volatile unsigned long *)0x4002000C))
+#define I2C0_MASTER_SRIS_R (*((volatile unsigned long *)0x40020010))
+#define I2C0_MASTER_MIMR_R (*((volatile unsigned long *)0x40020010))
+#define I2C0_MASTER_MRIS_R (*((volatile unsigned long *)0x40020014))
+#define I2C0_MASTER_SMIS_R (*((volatile unsigned long *)0x40020014))
+#define I2C0_MASTER_SICR_R (*((volatile unsigned long *)0x40020018))
+#define I2C0_MASTER_MMIS_R (*((volatile unsigned long *)0x40020018))
+#define I2C0_MASTER_MICR_R (*((volatile unsigned long *)0x4002001C))
+#define I2C0_MASTER_MCR_R (*((volatile unsigned long *)0x40020020))
+
+//*****************************************************************************
+//
+// Inter-Integrated Circuit (SLAVE) Interface
+//
+//*****************************************************************************
+#define I2C0_SLAVE_MSA_R (*((volatile unsigned long *)0x40020800))
+#define I2C0_SLAVE_SOAR_R (*((volatile unsigned long *)0x40020800))
+#define I2C0_SLAVE_SCSR_R (*((volatile unsigned long *)0x40020804))
+#define I2C0_SLAVE_MCS_R (*((volatile unsigned long *)0x40020804))
+#define I2C0_SLAVE_SDR_R (*((volatile unsigned long *)0x40020808))
+#define I2C0_SLAVE_MDR_R (*((volatile unsigned long *)0x40020808))
+#define I2C0_SLAVE_MTPR_R (*((volatile unsigned long *)0x4002080C))
+#define I2C0_SLAVE_SIMR_R (*((volatile unsigned long *)0x4002080C))
+#define I2C0_SLAVE_SRIS_R (*((volatile unsigned long *)0x40020810))
+#define I2C0_SLAVE_MIMR_R (*((volatile unsigned long *)0x40020810))
+#define I2C0_SLAVE_MRIS_R (*((volatile unsigned long *)0x40020814))
+#define I2C0_SLAVE_SMIS_R (*((volatile unsigned long *)0x40020814))
+#define I2C0_SLAVE_SICR_R (*((volatile unsigned long *)0x40020818))
+#define I2C0_SLAVE_MMIS_R (*((volatile unsigned long *)0x40020818))
+#define I2C0_SLAVE_MICR_R (*((volatile unsigned long *)0x4002081C))
+#define I2C0_SLAVE_MCR_R (*((volatile unsigned long *)0x40020820))
+
+//*****************************************************************************
+//
+// Inter-Integrated Circuit (MASTER) Interface
+//
+//*****************************************************************************
+#define I2C1_MASTER_MSA_R (*((volatile unsigned long *)0x40021000))
+#define I2C1_MASTER_SOAR_R (*((volatile unsigned long *)0x40021000))
+#define I2C1_MASTER_SCSR_R (*((volatile unsigned long *)0x40021004))
+#define I2C1_MASTER_MCS_R (*((volatile unsigned long *)0x40021004))
+#define I2C1_MASTER_SDR_R (*((volatile unsigned long *)0x40021008))
+#define I2C1_MASTER_MDR_R (*((volatile unsigned long *)0x40021008))
+#define I2C1_MASTER_MTPR_R (*((volatile unsigned long *)0x4002100C))
+#define I2C1_MASTER_SIMR_R (*((volatile unsigned long *)0x4002100C))
+#define I2C1_MASTER_SRIS_R (*((volatile unsigned long *)0x40021010))
+#define I2C1_MASTER_MIMR_R (*((volatile unsigned long *)0x40021010))
+#define I2C1_MASTER_MRIS_R (*((volatile unsigned long *)0x40021014))
+#define I2C1_MASTER_SMIS_R (*((volatile unsigned long *)0x40021014))
+#define I2C1_MASTER_SICR_R (*((volatile unsigned long *)0x40021018))
+#define I2C1_MASTER_MMIS_R (*((volatile unsigned long *)0x40021018))
+#define I2C1_MASTER_MICR_R (*((volatile unsigned long *)0x4002101C))
+#define I2C1_MASTER_MCR_R (*((volatile unsigned long *)0x40021020))
+
+//*****************************************************************************
+//
+// Inter-Integrated Circuit (SLAVE) Interface
+//
+//*****************************************************************************
+#define I2C1_SLAVE_MSA_R (*((volatile unsigned long *)0x40021800))
+#define I2C1_SLAVE_SOAR_R (*((volatile unsigned long *)0x40021800))
+#define I2C1_SLAVE_SCSR_R (*((volatile unsigned long *)0x40021804))
+#define I2C1_SLAVE_MCS_R (*((volatile unsigned long *)0x40021804))
+#define I2C1_SLAVE_SDR_R (*((volatile unsigned long *)0x40021808))
+#define I2C1_SLAVE_MDR_R (*((volatile unsigned long *)0x40021808))
+#define I2C1_SLAVE_MTPR_R (*((volatile unsigned long *)0x4002180C))
+#define I2C1_SLAVE_SIMR_R (*((volatile unsigned long *)0x4002180C))
+#define I2C1_SLAVE_SRIS_R (*((volatile unsigned long *)0x40021810))
+#define I2C1_SLAVE_MIMR_R (*((volatile unsigned long *)0x40021810))
+#define I2C1_SLAVE_MRIS_R (*((volatile unsigned long *)0x40021814))
+#define I2C1_SLAVE_SMIS_R (*((volatile unsigned long *)0x40021814))
+#define I2C1_SLAVE_SICR_R (*((volatile unsigned long *)0x40021818))
+#define I2C1_SLAVE_MMIS_R (*((volatile unsigned long *)0x40021818))
+#define I2C1_SLAVE_MICR_R (*((volatile unsigned long *)0x4002181C))
+#define I2C1_SLAVE_MCR_R (*((volatile unsigned long *)0x40021820))
+
+//*****************************************************************************
+//
+// General-Purpose Input/Outputs (PORTE)
+//
+//*****************************************************************************
+#define GPIO_PORTE_DATA_BITS_R ((volatile unsigned long *)0x40024000)
+#define GPIO_PORTE_DATA_R (*((volatile unsigned long *)0x400243FC))
+#define GPIO_PORTE_DIR_R (*((volatile unsigned long *)0x40024400))
+#define GPIO_PORTE_IS_R (*((volatile unsigned long *)0x40024404))
+#define GPIO_PORTE_IBE_R (*((volatile unsigned long *)0x40024408))
+#define GPIO_PORTE_IEV_R (*((volatile unsigned long *)0x4002440C))
+#define GPIO_PORTE_IM_R (*((volatile unsigned long *)0x40024410))
+#define GPIO_PORTE_RIS_R (*((volatile unsigned long *)0x40024414))
+#define GPIO_PORTE_MIS_R (*((volatile unsigned long *)0x40024418))
+#define GPIO_PORTE_ICR_R (*((volatile unsigned long *)0x4002441C))
+#define GPIO_PORTE_AFSEL_R (*((volatile unsigned long *)0x40024420))
+#define GPIO_PORTE_DR2R_R (*((volatile unsigned long *)0x40024500))
+#define GPIO_PORTE_DR4R_R (*((volatile unsigned long *)0x40024504))
+#define GPIO_PORTE_DR8R_R (*((volatile unsigned long *)0x40024508))
+#define GPIO_PORTE_ODR_R (*((volatile unsigned long *)0x4002450C))
+#define GPIO_PORTE_PUR_R (*((volatile unsigned long *)0x40024510))
+#define GPIO_PORTE_PDR_R (*((volatile unsigned long *)0x40024514))
+#define GPIO_PORTE_SLR_R (*((volatile unsigned long *)0x40024518))
+#define GPIO_PORTE_DEN_R (*((volatile unsigned long *)0x4002451C))
+#define GPIO_PORTE_LOCK_R (*((volatile unsigned long *)0x40024520))
+#define GPIO_PORTE_CR_R (*((volatile unsigned long *)0x40024524))
+
+//*****************************************************************************
+//
+// General-Purpose Input/Outputs (PORTF)
+//
+//*****************************************************************************
+#define GPIO_PORTF_DATA_BITS_R ((volatile unsigned long *)0x40025000)
+#define GPIO_PORTF_DATA_R (*((volatile unsigned long *)0x400253FC))
+#define GPIO_PORTF_DIR_R (*((volatile unsigned long *)0x40025400))
+#define GPIO_PORTF_IS_R (*((volatile unsigned long *)0x40025404))
+#define GPIO_PORTF_IBE_R (*((volatile unsigned long *)0x40025408))
+#define GPIO_PORTF_IEV_R (*((volatile unsigned long *)0x4002540C))
+#define GPIO_PORTF_IM_R (*((volatile unsigned long *)0x40025410))
+#define GPIO_PORTF_RIS_R (*((volatile unsigned long *)0x40025414))
+#define GPIO_PORTF_MIS_R (*((volatile unsigned long *)0x40025418))
+#define GPIO_PORTF_ICR_R (*((volatile unsigned long *)0x4002541C))
+#define GPIO_PORTF_AFSEL_R (*((volatile unsigned long *)0x40025420))
+#define GPIO_PORTF_DR2R_R (*((volatile unsigned long *)0x40025500))
+#define GPIO_PORTF_DR4R_R (*((volatile unsigned long *)0x40025504))
+#define GPIO_PORTF_DR8R_R (*((volatile unsigned long *)0x40025508))
+#define GPIO_PORTF_ODR_R (*((volatile unsigned long *)0x4002550C))
+#define GPIO_PORTF_PUR_R (*((volatile unsigned long *)0x40025510))
+#define GPIO_PORTF_PDR_R (*((volatile unsigned long *)0x40025514))
+#define GPIO_PORTF_SLR_R (*((volatile unsigned long *)0x40025518))
+#define GPIO_PORTF_DEN_R (*((volatile unsigned long *)0x4002551C))
+#define GPIO_PORTF_LOCK_R (*((volatile unsigned long *)0x40025520))
+#define GPIO_PORTF_CR_R (*((volatile unsigned long *)0x40025524))
+
+//*****************************************************************************
+//
+// General-Purpose Input/Outputs (PORTG)
+//
+//*****************************************************************************
+#define GPIO_PORTG_DATA_BITS_R ((volatile unsigned long *)0x40026000)
+#define GPIO_PORTG_DATA_R (*((volatile unsigned long *)0x400263FC))
+#define GPIO_PORTG_DIR_R (*((volatile unsigned long *)0x40026400))
+#define GPIO_PORTG_IS_R (*((volatile unsigned long *)0x40026404))
+#define GPIO_PORTG_IBE_R (*((volatile unsigned long *)0x40026408))
+#define GPIO_PORTG_IEV_R (*((volatile unsigned long *)0x4002640C))
+#define GPIO_PORTG_IM_R (*((volatile unsigned long *)0x40026410))
+#define GPIO_PORTG_RIS_R (*((volatile unsigned long *)0x40026414))
+#define GPIO_PORTG_MIS_R (*((volatile unsigned long *)0x40026418))
+#define GPIO_PORTG_ICR_R (*((volatile unsigned long *)0x4002641C))
+#define GPIO_PORTG_AFSEL_R (*((volatile unsigned long *)0x40026420))
+#define GPIO_PORTG_DR2R_R (*((volatile unsigned long *)0x40026500))
+#define GPIO_PORTG_DR4R_R (*((volatile unsigned long *)0x40026504))
+#define GPIO_PORTG_DR8R_R (*((volatile unsigned long *)0x40026508))
+#define GPIO_PORTG_ODR_R (*((volatile unsigned long *)0x4002650C))
+#define GPIO_PORTG_PUR_R (*((volatile unsigned long *)0x40026510))
+#define GPIO_PORTG_PDR_R (*((volatile unsigned long *)0x40026514))
+#define GPIO_PORTG_SLR_R (*((volatile unsigned long *)0x40026518))
+#define GPIO_PORTG_DEN_R (*((volatile unsigned long *)0x4002651C))
+#define GPIO_PORTG_LOCK_R (*((volatile unsigned long *)0x40026520))
+#define GPIO_PORTG_CR_R (*((volatile unsigned long *)0x40026524))
+
+//*****************************************************************************
+//
+// General-Purpose Input/Outputs (PORTH)
+//
+//*****************************************************************************
+#define GPIO_PORTH_DATA_BITS_R ((volatile unsigned long *)0x40027000)
+#define GPIO_PORTH_DATA_R (*((volatile unsigned long *)0x400273FC))
+#define GPIO_PORTH_DIR_R (*((volatile unsigned long *)0x40027400))
+#define GPIO_PORTH_IS_R (*((volatile unsigned long *)0x40027404))
+#define GPIO_PORTH_IBE_R (*((volatile unsigned long *)0x40027408))
+#define GPIO_PORTH_IEV_R (*((volatile unsigned long *)0x4002740C))
+#define GPIO_PORTH_IM_R (*((volatile unsigned long *)0x40027410))
+#define GPIO_PORTH_RIS_R (*((volatile unsigned long *)0x40027414))
+#define GPIO_PORTH_MIS_R (*((volatile unsigned long *)0x40027418))
+#define GPIO_PORTH_ICR_R (*((volatile unsigned long *)0x4002741C))
+#define GPIO_PORTH_AFSEL_R (*((volatile unsigned long *)0x40027420))
+#define GPIO_PORTH_DR2R_R (*((volatile unsigned long *)0x40027500))
+#define GPIO_PORTH_DR4R_R (*((volatile unsigned long *)0x40027504))
+#define GPIO_PORTH_DR8R_R (*((volatile unsigned long *)0x40027508))
+#define GPIO_PORTH_ODR_R (*((volatile unsigned long *)0x4002750C))
+#define GPIO_PORTH_PUR_R (*((volatile unsigned long *)0x40027510))
+#define GPIO_PORTH_PDR_R (*((volatile unsigned long *)0x40027514))
+#define GPIO_PORTH_SLR_R (*((volatile unsigned long *)0x40027518))
+#define GPIO_PORTH_DEN_R (*((volatile unsigned long *)0x4002751C))
+#define GPIO_PORTH_LOCK_R (*((volatile unsigned long *)0x40027520))
+#define GPIO_PORTH_CR_R (*((volatile unsigned long *)0x40027524))
+
+//*****************************************************************************
+//
+// General-Purpose Timers (TIMER0)
+//
+//*****************************************************************************
+#define TIMER0_CFG_R (*((volatile unsigned long *)0x40030000))
+#define TIMER0_TAMR_R (*((volatile unsigned long *)0x40030004))
+#define TIMER0_TBMR_R (*((volatile unsigned long *)0x40030008))
+#define TIMER0_CTL_R (*((volatile unsigned long *)0x4003000C))
+#define TIMER0_IMR_R (*((volatile unsigned long *)0x40030018))
+#define TIMER0_RIS_R (*((volatile unsigned long *)0x4003001C))
+#define TIMER0_MIS_R (*((volatile unsigned long *)0x40030020))
+#define TIMER0_ICR_R (*((volatile unsigned long *)0x40030024))
+#define TIMER0_TAILR_R (*((volatile unsigned long *)0x40030028))
+#define TIMER0_TBILR_R (*((volatile unsigned long *)0x4003002C))
+#define TIMER0_TAMATCHR_R (*((volatile unsigned long *)0x40030030))
+#define TIMER0_TBMATCHR_R (*((volatile unsigned long *)0x40030034))
+#define TIMER0_TAPR_R (*((volatile unsigned long *)0x40030038))
+#define TIMER0_TBPR_R (*((volatile unsigned long *)0x4003003C))
+#define TIMER0_TAPMR_R (*((volatile unsigned long *)0x40030040))
+#define TIMER0_TBPMR_R (*((volatile unsigned long *)0x40030044))
+#define TIMER0_TAR_R (*((volatile unsigned long *)0x40030048))
+#define TIMER0_TBR_R (*((volatile unsigned long *)0x4003004C))
+
+//*****************************************************************************
+//
+// General-Purpose Timers (TIMER1)
+//
+//*****************************************************************************
+#define TIMER1_CFG_R (*((volatile unsigned long *)0x40031000))
+#define TIMER1_TAMR_R (*((volatile unsigned long *)0x40031004))
+#define TIMER1_TBMR_R (*((volatile unsigned long *)0x40031008))
+#define TIMER1_CTL_R (*((volatile unsigned long *)0x4003100C))
+#define TIMER1_IMR_R (*((volatile unsigned long *)0x40031018))
+#define TIMER1_RIS_R (*((volatile unsigned long *)0x4003101C))
+#define TIMER1_MIS_R (*((volatile unsigned long *)0x40031020))
+#define TIMER1_ICR_R (*((volatile unsigned long *)0x40031024))
+#define TIMER1_TAILR_R (*((volatile unsigned long *)0x40031028))
+#define TIMER1_TBILR_R (*((volatile unsigned long *)0x4003102C))
+#define TIMER1_TAMATCHR_R (*((volatile unsigned long *)0x40031030))
+#define TIMER1_TBMATCHR_R (*((volatile unsigned long *)0x40031034))
+#define TIMER1_TAPR_R (*((volatile unsigned long *)0x40031038))
+#define TIMER1_TBPR_R (*((volatile unsigned long *)0x4003103C))
+#define TIMER1_TAPMR_R (*((volatile unsigned long *)0x40031040))
+#define TIMER1_TBPMR_R (*((volatile unsigned long *)0x40031044))
+#define TIMER1_TAR_R (*((volatile unsigned long *)0x40031048))
+#define TIMER1_TBR_R (*((volatile unsigned long *)0x4003104C))
+
+//*****************************************************************************
+//
+// General-Purpose Timers (TIMER2)
+//
+//*****************************************************************************
+#define TIMER2_CFG_R (*((volatile unsigned long *)0x40032000))
+#define TIMER2_TAMR_R (*((volatile unsigned long *)0x40032004))
+#define TIMER2_TBMR_R (*((volatile unsigned long *)0x40032008))
+#define TIMER2_CTL_R (*((volatile unsigned long *)0x4003200C))
+#define TIMER2_IMR_R (*((volatile unsigned long *)0x40032018))
+#define TIMER2_RIS_R (*((volatile unsigned long *)0x4003201C))
+#define TIMER2_MIS_R (*((volatile unsigned long *)0x40032020))
+#define TIMER2_ICR_R (*((volatile unsigned long *)0x40032024))
+#define TIMER2_TAILR_R (*((volatile unsigned long *)0x40032028))
+#define TIMER2_TBILR_R (*((volatile unsigned long *)0x4003202C))
+#define TIMER2_TAMATCHR_R (*((volatile unsigned long *)0x40032030))
+#define TIMER2_TBMATCHR_R (*((volatile unsigned long *)0x40032034))
+#define TIMER2_TAPR_R (*((volatile unsigned long *)0x40032038))
+#define TIMER2_TBPR_R (*((volatile unsigned long *)0x4003203C))
+#define TIMER2_TAPMR_R (*((volatile unsigned long *)0x40032040))
+#define TIMER2_TBPMR_R (*((volatile unsigned long *)0x40032044))
+#define TIMER2_TAR_R (*((volatile unsigned long *)0x40032048))
+#define TIMER2_TBR_R (*((volatile unsigned long *)0x4003204C))
+
+//*****************************************************************************
+//
+// General-Purpose Timers (TIMER3)
+//
+//*****************************************************************************
+#define TIMER3_CFG_R (*((volatile unsigned long *)0x40033000))
+#define TIMER3_TAMR_R (*((volatile unsigned long *)0x40033004))
+#define TIMER3_TBMR_R (*((volatile unsigned long *)0x40033008))
+#define TIMER3_CTL_R (*((volatile unsigned long *)0x4003300C))
+#define TIMER3_IMR_R (*((volatile unsigned long *)0x40033018))
+#define TIMER3_RIS_R (*((volatile unsigned long *)0x4003301C))
+#define TIMER3_MIS_R (*((volatile unsigned long *)0x40033020))
+#define TIMER3_ICR_R (*((volatile unsigned long *)0x40033024))
+#define TIMER3_TAILR_R (*((volatile unsigned long *)0x40033028))
+#define TIMER3_TBILR_R (*((volatile unsigned long *)0x4003302C))
+#define TIMER3_TAMATCHR_R (*((volatile unsigned long *)0x40033030))
+#define TIMER3_TBMATCHR_R (*((volatile unsigned long *)0x40033034))
+#define TIMER3_TAPR_R (*((volatile unsigned long *)0x40033038))
+#define TIMER3_TBPR_R (*((volatile unsigned long *)0x4003303C))
+#define TIMER3_TAPMR_R (*((volatile unsigned long *)0x40033040))
+#define TIMER3_TBPMR_R (*((volatile unsigned long *)0x40033044))
+#define TIMER3_TAR_R (*((volatile unsigned long *)0x40033048))
+#define TIMER3_TBR_R (*((volatile unsigned long *)0x4003304C))
+
+//*****************************************************************************
+//
+// Analog-to-Digital Converter (ADC)
+//
+//*****************************************************************************
+#define ADC_ACTSS_R (*((volatile unsigned long *)0x40038000))
+#define ADC_RIS_R (*((volatile unsigned long *)0x40038004))
+#define ADC_IM_R (*((volatile unsigned long *)0x40038008))
+#define ADC_ISC_R (*((volatile unsigned long *)0x4003800C))
+#define ADC_OSTAT_R (*((volatile unsigned long *)0x40038010))
+#define ADC_EMUX_R (*((volatile unsigned long *)0x40038014))
+#define ADC_USTAT_R (*((volatile unsigned long *)0x40038018))
+#define ADC_SSPRI_R (*((volatile unsigned long *)0x40038020))
+#define ADC_PSSI_R (*((volatile unsigned long *)0x40038028))
+#define ADC_SAC_R (*((volatile unsigned long *)0x40038030))
+#define ADC_SSMUX0_R (*((volatile unsigned long *)0x40038040))
+#define ADC_SSCTL0_R (*((volatile unsigned long *)0x40038044))
+#define ADC_SSFIFO0_R (*((volatile unsigned long *)0x40038048))
+#define ADC_SSFSTAT0_R (*((volatile unsigned long *)0x4003804C))
+#define ADC_SSMUX1_R (*((volatile unsigned long *)0x40038060))
+#define ADC_SSCTL1_R (*((volatile unsigned long *)0x40038064))
+#define ADC_SSFIFO1_R (*((volatile unsigned long *)0x40038068))
+#define ADC_SSFSTAT1_R (*((volatile unsigned long *)0x4003806C))
+#define ADC_SSMUX2_R (*((volatile unsigned long *)0x40038080))
+#define ADC_SSCTL2_R (*((volatile unsigned long *)0x40038084))
+#define ADC_SSFIFO2_R (*((volatile unsigned long *)0x40038088))
+#define ADC_SSFSTAT2_R (*((volatile unsigned long *)0x4003808C))
+#define ADC_SSMUX3_R (*((volatile unsigned long *)0x400380A0))
+#define ADC_SSCTL3_R (*((volatile unsigned long *)0x400380A4))
+#define ADC_SSFIFO3_R (*((volatile unsigned long *)0x400380A8))
+#define ADC_SSFSTAT3_R (*((volatile unsigned long *)0x400380AC))
+#define ADC_TMLB_R (*((volatile unsigned long *)0x40038100))
+
+//*****************************************************************************
+//
+// Analog Comparators (COMP)
+//
+//*****************************************************************************
+#define COMP_ACMIS_R (*((volatile unsigned long *)0x4003C000))
+#define COMP_ACRIS_R (*((volatile unsigned long *)0x4003C004))
+#define COMP_ACINTEN_R (*((volatile unsigned long *)0x4003C008))
+#define COMP_ACREFCTL_R (*((volatile unsigned long *)0x4003C010))
+#define COMP_ACSTAT0_R (*((volatile unsigned long *)0x4003C020))
+#define COMP_ACCTL0_R (*((volatile unsigned long *)0x4003C024))
+#define COMP_ACSTAT1_R (*((volatile unsigned long *)0x4003C040))
+#define COMP_ACCTL1_R (*((volatile unsigned long *)0x4003C044))
+
+//*****************************************************************************
+//
+// Ethernet Controller (MAC)
+//
+//*****************************************************************************
+#define MAC_MR0_R (*((volatile unsigned long *)0x40048000))
+#define MAC_RIS_R (*((volatile unsigned long *)0x40048000))
+#define MAC_IACK_R (*((volatile unsigned long *)0x40048000))
+#define MAC_MR1_R (*((volatile unsigned long *)0x40048001))
+#define MAC_MR2_R (*((volatile unsigned long *)0x40048002))
+#define MAC_MR3_R (*((volatile unsigned long *)0x40048003))
+#define MAC_IM_R (*((volatile unsigned long *)0x40048004))
+#define MAC_MR4_R (*((volatile unsigned long *)0x40048004))
+#define MAC_MR5_R (*((volatile unsigned long *)0x40048005))
+#define MAC_MR6_R (*((volatile unsigned long *)0x40048006))
+#define MAC_RCTL_R (*((volatile unsigned long *)0x40048008))
+#define MAC_TCTL_R (*((volatile unsigned long *)0x4004800C))
+#define MAC_DATA_R (*((volatile unsigned long *)0x40048010))
+#define MAC_MR16_R (*((volatile unsigned long *)0x40048010))
+#define MAC_MR17_R (*((volatile unsigned long *)0x40048011))
+#define MAC_MR18_R (*((volatile unsigned long *)0x40048012))
+#define MAC_MR19_R (*((volatile unsigned long *)0x40048013))
+#define MAC_IA0_R (*((volatile unsigned long *)0x40048014))
+#define MAC_MR23_R (*((volatile unsigned long *)0x40048017))
+#define MAC_IA1_R (*((volatile unsigned long *)0x40048018))
+#define MAC_MR24_R (*((volatile unsigned long *)0x40048018))
+#define MAC_THR_R (*((volatile unsigned long *)0x4004801C))
+#define MAC_MCTL_R (*((volatile unsigned long *)0x40048020))
+#define MAC_MDV_R (*((volatile unsigned long *)0x40048024))
+#define MAC_MTXD_R (*((volatile unsigned long *)0x4004802C))
+#define MAC_MRXD_R (*((volatile unsigned long *)0x40048030))
+#define MAC_NP_R (*((volatile unsigned long *)0x40048034))
+#define MAC_TR_R (*((volatile unsigned long *)0x40048038))
+
+//*****************************************************************************
+//
+// Hibernation Module (HIB)
+//
+//*****************************************************************************
+#define HIB_RTCC_R (*((volatile unsigned long *)0x400FC000))
+#define HIB_RTCM0_R (*((volatile unsigned long *)0x400FC004))
+#define HIB_RTCM1_R (*((volatile unsigned long *)0x400FC008))
+#define HIB_RTCLD_R (*((volatile unsigned long *)0x400FC00C))
+#define HIB_CTL_R (*((volatile unsigned long *)0x400FC010))
+#define HIB_IM_R (*((volatile unsigned long *)0x400FC014))
+#define HIB_RIS_R (*((volatile unsigned long *)0x400FC018))
+#define HIB_MIS_R (*((volatile unsigned long *)0x400FC01C))
+#define HIB_IC_R (*((volatile unsigned long *)0x400FC020))
+#define HIB_RTCT_R (*((volatile unsigned long *)0x400FC024))
+#define HIB_DATA_R (*((volatile unsigned long *)0x400FC030))
+
+//*****************************************************************************
+//
+// Internal Memory (FLASH)
+//
+//*****************************************************************************
+#define FLASH_FMA_R (*((volatile unsigned long *)0x400FD000))
+#define FLASH_FMD_R (*((volatile unsigned long *)0x400FD004))
+#define FLASH_FMC_R (*((volatile unsigned long *)0x400FD008))
+#define FLASH_FCRIS_R (*((volatile unsigned long *)0x400FD00C))
+#define FLASH_FCIM_R (*((volatile unsigned long *)0x400FD010))
+#define FLASH_FCMISC_R (*((volatile unsigned long *)0x400FD014))
+#define FLASH_USECRL_R (*((volatile unsigned long *)0x400FE140))
+#define FLASH_USERDBG_R (*((volatile unsigned long *)0x400FE1D0))
+#define FLASH_USERREG0_R (*((volatile unsigned long *)0x400FE1E0))
+#define FLASH_USERREG1_R (*((volatile unsigned long *)0x400FE1E4))
+#define FLASH_FMPRE0_R (*((volatile unsigned long *)0x400FE200))
+#define FLASH_FMPRE1_R (*((volatile unsigned long *)0x400FE204))
+#define FLASH_FMPRE2_R (*((volatile unsigned long *)0x400FE208))
+#define FLASH_FMPRE3_R (*((volatile unsigned long *)0x400FE20C))
+#define FLASH_FMPPE0_R (*((volatile unsigned long *)0x400FE400))
+#define FLASH_FMPPE1_R (*((volatile unsigned long *)0x400FE404))
+#define FLASH_FMPPE2_R (*((volatile unsigned long *)0x400FE408))
+#define FLASH_FMPPE3_R (*((volatile unsigned long *)0x400FE40C))
+
+//*****************************************************************************
+//
+// System Control (SYSCTL)
+//
+//*****************************************************************************
+#define SYSCTL_DID0_R (*((volatile unsigned long *)0x400FE000))
+#define SYSCTL_DID1_R (*((volatile unsigned long *)0x400FE004))
+#define SYSCTL_DC0_R (*((volatile unsigned long *)0x400FE008))
+#define SYSCTL_DC1_R (*((volatile unsigned long *)0x400FE010))
+#define SYSCTL_DC2_R (*((volatile unsigned long *)0x400FE014))
+#define SYSCTL_DC3_R (*((volatile unsigned long *)0x400FE018))
+#define SYSCTL_DC4_R (*((volatile unsigned long *)0x400FE01C))
+#define SYSCTL_PBORCTL_R (*((volatile unsigned long *)0x400FE030))
+#define SYSCTL_LDOPCTL_R (*((volatile unsigned long *)0x400FE034))
+#define SYSCTL_SRCR0_R (*((volatile unsigned long *)0x400FE040))
+#define SYSCTL_SRCR1_R (*((volatile unsigned long *)0x400FE044))
+#define SYSCTL_SRCR2_R (*((volatile unsigned long *)0x400FE048))
+#define SYSCTL_RIS_R (*((volatile unsigned long *)0x400FE050))
+#define SYSCTL_IMC_R (*((volatile unsigned long *)0x400FE054))
+#define SYSCTL_MISC_R (*((volatile unsigned long *)0x400FE058))
+#define SYSCTL_RESC_R (*((volatile unsigned long *)0x400FE05C))
+#define SYSCTL_RCC_R (*((volatile unsigned long *)0x400FE060))
+#define SYSCTL_PLLCFG_R (*((volatile unsigned long *)0x400FE064))
+#define SYSCTL_RCC2_R (*((volatile unsigned long *)0x400FE070))
+#define SYSCTL_RCGC0_R (*((volatile unsigned long *)0x400FE100))
+#define SYSCTL_RCGC1_R (*((volatile unsigned long *)0x400FE104))
+#define SYSCTL_RCGC2_R (*((volatile unsigned long *)0x400FE108))
+#define SYSCTL_SCGC0_R (*((volatile unsigned long *)0x400FE110))
+#define SYSCTL_SCGC1_R (*((volatile unsigned long *)0x400FE114))
+#define SYSCTL_SCGC2_R (*((volatile unsigned long *)0x400FE118))
+#define SYSCTL_DCGC0_R (*((volatile unsigned long *)0x400FE120))
+#define SYSCTL_DCGC1_R (*((volatile unsigned long *)0x400FE124))
+#define SYSCTL_DCGC2_R (*((volatile unsigned long *)0x400FE128))
+#define SYSCTL_DSLPCLKCFG_R (*((volatile unsigned long *)0x400FE144))
+
+//*****************************************************************************
+//
+// Nested Vectored Interrupt Ctrl (NVIC)
+//
+//*****************************************************************************
+#define NVIC_INT_TYPE_R (*((volatile unsigned long *)0xE000E004))
+#define NVIC_ST_CTRL_R (*((volatile unsigned long *)0xE000E010))
+#define NVIC_ST_RELOAD_R (*((volatile unsigned long *)0xE000E014))
+#define NVIC_ST_CURRENT_R (*((volatile unsigned long *)0xE000E018))
+#define NVIC_ST_CAL_R (*((volatile unsigned long *)0xE000E01C))
+#define NVIC_EN0_R (*((volatile unsigned long *)0xE000E100))
+#define NVIC_EN1_R (*((volatile unsigned long *)0xE000E104))
+#define NVIC_DIS0_R (*((volatile unsigned long *)0xE000E180))
+#define NVIC_DIS1_R (*((volatile unsigned long *)0xE000E184))
+#define NVIC_PEND0_R (*((volatile unsigned long *)0xE000E200))
+#define NVIC_PEND1_R (*((volatile unsigned long *)0xE000E204))
+#define NVIC_UNPEND0_R (*((volatile unsigned long *)0xE000E280))
+#define NVIC_UNPEND1_R (*((volatile unsigned long *)0xE000E284))
+#define NVIC_ACTIVE0_R (*((volatile unsigned long *)0xE000E300))
+#define NVIC_ACTIVE1_R (*((volatile unsigned long *)0xE000E304))
+#define NVIC_PRI0_R (*((volatile unsigned long *)0xE000E400))
+#define NVIC_PRI1_R (*((volatile unsigned long *)0xE000E404))
+#define NVIC_PRI2_R (*((volatile unsigned long *)0xE000E408))
+#define NVIC_PRI3_R (*((volatile unsigned long *)0xE000E40C))
+#define NVIC_PRI4_R (*((volatile unsigned long *)0xE000E410))
+#define NVIC_PRI5_R (*((volatile unsigned long *)0xE000E414))
+#define NVIC_PRI6_R (*((volatile unsigned long *)0xE000E418))
+#define NVIC_PRI7_R (*((volatile unsigned long *)0xE000E41C))
+#define NVIC_PRI8_R (*((volatile unsigned long *)0xE000E420))
+#define NVIC_PRI9_R (*((volatile unsigned long *)0xE000E424))
+#define NVIC_PRI10_R (*((volatile unsigned long *)0xE000E428))
+#define NVIC_CPUID_R (*((volatile unsigned long *)0xE000ED00))
+#define NVIC_INT_CTRL_R (*((volatile unsigned long *)0xE000ED04))
+#define NVIC_VTABLE_R (*((volatile unsigned long *)0xE000ED08))
+#define NVIC_APINT_R (*((volatile unsigned long *)0xE000ED0C))
+#define NVIC_SYS_CTRL_R (*((volatile unsigned long *)0xE000ED10))
+#define NVIC_CFG_CTRL_R (*((volatile unsigned long *)0xE000ED14))
+#define NVIC_SYS_PRI1_R (*((volatile unsigned long *)0xE000ED18))
+#define NVIC_SYS_PRI2_R (*((volatile unsigned long *)0xE000ED1C))
+#define NVIC_SYS_PRI3_R (*((volatile unsigned long *)0xE000ED20))
+#define NVIC_SYS_HND_CTRL_R (*((volatile unsigned long *)0xE000ED24))
+#define NVIC_FAULT_STAT_R (*((volatile unsigned long *)0xE000ED28))
+#define NVIC_HFAULT_STAT_R (*((volatile unsigned long *)0xE000ED2C))
+#define NVIC_DEBUG_STAT_R (*((volatile unsigned long *)0xE000ED30))
+#define NVIC_MM_ADDR_R (*((volatile unsigned long *)0xE000ED34))
+#define NVIC_FAULT_ADDR_R (*((volatile unsigned long *)0xE000ED38))
+#define NVIC_MPU_TYPE_R (*((volatile unsigned long *)0xE000ED90))
+#define NVIC_MPU_CTRL_R (*((volatile unsigned long *)0xE000ED94))
+#define NVIC_MPU_NUMBER_R (*((volatile unsigned long *)0xE000ED98))
+#define NVIC_MPU_R (*((volatile unsigned long *)0xE000ED9C))
+#define NVIC_MPU_ATTR_R (*((volatile unsigned long *)0xE000EDA0))
+#define NVIC_DBG_CTRL_R (*((volatile unsigned long *)0xE000EDF0))
+#define NVIC_DBG_XFER_R (*((volatile unsigned long *)0xE000EDF4))
+#define NVIC_DBG_DATA_R (*((volatile unsigned long *)0xE000EDF8))
+#define NVIC_DBG_INT_R (*((volatile unsigned long *)0xE000EDFC))
+#define NVIC_SW_TRIG_R (*((volatile unsigned long *)0xE000EF00))
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_LOAD register.
+//
+//*****************************************************************************
+#define WDT_LOAD_M 0xFFFFFFFF // Watchdog Load Value.
+#define WDT_LOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_VALUE register.
+//
+//*****************************************************************************
+#define WDT_VALUE_M 0xFFFFFFFF // Watchdog Value.
+#define WDT_VALUE_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_CTL register.
+//
+//*****************************************************************************
+#define WDT_CTL_RESEN 0x00000002 // Watchdog Reset Enable.
+#define WDT_CTL_INTEN 0x00000001 // Watchdog Interrupt Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_ICR register.
+//
+//*****************************************************************************
+#define WDT_ICR_M 0xFFFFFFFF // Watchdog Interrupt Clear.
+#define WDT_ICR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_RIS register.
+//
+//*****************************************************************************
+#define WDT_RIS_WDTRIS 0x00000001 // Watchdog Raw Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_MIS register.
+//
+//*****************************************************************************
+#define WDT_MIS_WDTMIS 0x00000001 // Watchdog Masked Interrupt
+ // Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_TEST register.
+//
+//*****************************************************************************
+#define WDT_TEST_STALL 0x00000100 // Watchdog Stall Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_LOCK register.
+//
+//*****************************************************************************
+#define WDT_LOCK_M 0xFFFFFFFF // Watchdog Lock.
+#define WDT_LOCK_UNLOCKED 0x00000000 // Unlocked
+#define WDT_LOCK_LOCKED 0x00000001 // Locked
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_LOCK register.
+//
+//*****************************************************************************
+#define GPIO_LOCK_M 0xFFFFFFFF // GPIO Lock.
+#define GPIO_LOCK_UNLOCKED 0x00000000 // unlocked
+#define GPIO_LOCK_LOCKED 0x00000001 // locked
+#define GPIO_LOCK_KEY 0x1ACCE551 // Unlocks the GPIO_CR register
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_CR0 register.
+//
+//*****************************************************************************
+#define SSI_CR0_SCR_M 0x0000FF00 // SSI Serial Clock Rate.
+#define SSI_CR0_SPH 0x00000080 // SSI Serial Clock Phase.
+#define SSI_CR0_SPO 0x00000040 // SSI Serial Clock Polarity.
+#define SSI_CR0_FRF_M 0x00000030 // SSI Frame Format Select.
+#define SSI_CR0_FRF_MOTO 0x00000000 // Freescale SPI Frame Format
+#define SSI_CR0_FRF_TI 0x00000010 // Texas Instruments Synchronous
+ // Serial Frame Format
+#define SSI_CR0_FRF_NMW 0x00000020 // MICROWIRE Frame Format
+#define SSI_CR0_DSS_M 0x0000000F // SSI Data Size Select.
+#define SSI_CR0_DSS_4 0x00000003 // 4-bit data
+#define SSI_CR0_DSS_5 0x00000004 // 5-bit data
+#define SSI_CR0_DSS_6 0x00000005 // 6-bit data
+#define SSI_CR0_DSS_7 0x00000006 // 7-bit data
+#define SSI_CR0_DSS_8 0x00000007 // 8-bit data
+#define SSI_CR0_DSS_9 0x00000008 // 9-bit data
+#define SSI_CR0_DSS_10 0x00000009 // 10-bit data
+#define SSI_CR0_DSS_11 0x0000000A // 11-bit data
+#define SSI_CR0_DSS_12 0x0000000B // 12-bit data
+#define SSI_CR0_DSS_13 0x0000000C // 13-bit data
+#define SSI_CR0_DSS_14 0x0000000D // 14-bit data
+#define SSI_CR0_DSS_15 0x0000000E // 15-bit data
+#define SSI_CR0_DSS_16 0x0000000F // 16-bit data
+#define SSI_CR0_SCR_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_CR1 register.
+//
+//*****************************************************************************
+#define SSI_CR1_SOD 0x00000008 // SSI Slave Mode Output Disable.
+#define SSI_CR1_MS 0x00000004 // SSI Master/Slave Select.
+#define SSI_CR1_SSE 0x00000002 // SSI Synchronous Serial Port
+ // Enable.
+#define SSI_CR1_LBM 0x00000001 // SSI Loopback Mode.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_DR register.
+//
+//*****************************************************************************
+#define SSI_DR_DATA_M 0x0000FFFF // SSI Receive/Transmit Data.
+#define SSI_DR_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_SR register.
+//
+//*****************************************************************************
+#define SSI_SR_BSY 0x00000010 // SSI Busy Bit.
+#define SSI_SR_RFF 0x00000008 // SSI Receive FIFO Full.
+#define SSI_SR_RNE 0x00000004 // SSI Receive FIFO Not Empty.
+#define SSI_SR_TNF 0x00000002 // SSI Transmit FIFO Not Full.
+#define SSI_SR_TFE 0x00000001 // SSI Transmit FIFO Empty.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_CPSR register.
+//
+//*****************************************************************************
+#define SSI_CPSR_CPSDVSR_M 0x000000FF // SSI Clock Prescale Divisor.
+#define SSI_CPSR_CPSDVSR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_IM register.
+//
+//*****************************************************************************
+#define SSI_IM_TXIM 0x00000008 // SSI Transmit FIFO Interrupt
+ // Mask.
+#define SSI_IM_RXIM 0x00000004 // SSI Receive FIFO Interrupt Mask.
+#define SSI_IM_RTIM 0x00000002 // SSI Receive Time-Out Interrupt
+ // Mask.
+#define SSI_IM_RORIM 0x00000001 // SSI Receive Overrun Interrupt
+ // Mask.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_RIS register.
+//
+//*****************************************************************************
+#define SSI_RIS_TXRIS 0x00000008 // SSI Transmit FIFO Raw Interrupt
+ // Status.
+#define SSI_RIS_RXRIS 0x00000004 // SSI Receive FIFO Raw Interrupt
+ // Status.
+#define SSI_RIS_RTRIS 0x00000002 // SSI Receive Time-Out Raw
+ // Interrupt Status.
+#define SSI_RIS_RORRIS 0x00000001 // SSI Receive Overrun Raw
+ // Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_MIS register.
+//
+//*****************************************************************************
+#define SSI_MIS_TXMIS 0x00000008 // SSI Transmit FIFO Masked
+ // Interrupt Status.
+#define SSI_MIS_RXMIS 0x00000004 // SSI Receive FIFO Masked
+ // Interrupt Status.
+#define SSI_MIS_RTMIS 0x00000002 // SSI Receive Time-Out Masked
+ // Interrupt Status.
+#define SSI_MIS_RORMIS 0x00000001 // SSI Receive Overrun Masked
+ // Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_ICR register.
+//
+//*****************************************************************************
+#define SSI_ICR_RTIC 0x00000002 // SSI Receive Time-Out Interrupt
+ // Clear.
+#define SSI_ICR_RORIC 0x00000001 // SSI Receive Overrun Interrupt
+ // Clear.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_DR register.
+//
+//*****************************************************************************
+#define UART_DR_OE 0x00000800 // UART Overrun Error.
+#define UART_DR_BE 0x00000400 // UART Break Error.
+#define UART_DR_PE 0x00000200 // UART Parity Error.
+#define UART_DR_FE 0x00000100 // UART Framing Error.
+#define UART_DR_DATA_M 0x000000FF // Data Transmitted or Received.
+#define UART_DR_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_RSR register.
+//
+//*****************************************************************************
+#define UART_RSR_OE 0x00000008 // UART Overrun Error.
+#define UART_RSR_BE 0x00000004 // UART Break Error.
+#define UART_RSR_PE 0x00000002 // UART Parity Error.
+#define UART_RSR_FE 0x00000001 // UART Framing Error.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_ECR register.
+//
+//*****************************************************************************
+#define UART_ECR_DATA_M 0x000000FF // Error Clear.
+#define UART_ECR_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_FR register.
+//
+//*****************************************************************************
+#define UART_FR_TXFE 0x00000080 // UART Transmit FIFO Empty.
+#define UART_FR_RXFF 0x00000040 // UART Receive FIFO Full.
+#define UART_FR_TXFF 0x00000020 // UART Transmit FIFO Full.
+#define UART_FR_RXFE 0x00000010 // UART Receive FIFO Empty.
+#define UART_FR_BUSY 0x00000008 // UART Busy.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_ILPR register.
+//
+//*****************************************************************************
+#define UART_ILPR_ILPDVSR_M 0x000000FF // IrDA Low-Power Divisor.
+#define UART_ILPR_ILPDVSR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_IBRD register.
+//
+//*****************************************************************************
+#define UART_IBRD_DIVINT_M 0x0000FFFF // Integer Baud-Rate Divisor.
+#define UART_IBRD_DIVINT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_FBRD register.
+//
+//*****************************************************************************
+#define UART_FBRD_DIVFRAC_M 0x0000003F // Fractional Baud-Rate Divisor.
+#define UART_FBRD_DIVFRAC_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_LCRH register.
+//
+//*****************************************************************************
+#define UART_LCRH_SPS 0x00000080 // UART Stick Parity Select.
+#define UART_LCRH_WLEN_M 0x00000060 // UART Word Length.
+#define UART_LCRH_WLEN_5 0x00000000 // 5 bits (default)
+#define UART_LCRH_WLEN_6 0x00000020 // 6 bits
+#define UART_LCRH_WLEN_7 0x00000040 // 7 bits
+#define UART_LCRH_WLEN_8 0x00000060 // 8 bits
+#define UART_LCRH_FEN 0x00000010 // UART Enable FIFOs.
+#define UART_LCRH_STP2 0x00000008 // UART Two Stop Bits Select.
+#define UART_LCRH_EPS 0x00000004 // UART Even Parity Select.
+#define UART_LCRH_PEN 0x00000002 // UART Parity Enable.
+#define UART_LCRH_BRK 0x00000001 // UART Send Break.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_CTL register.
+//
+//*****************************************************************************
+#define UART_CTL_RXE 0x00000200 // UART Receive Enable.
+#define UART_CTL_TXE 0x00000100 // UART Transmit Enable.
+#define UART_CTL_LBE 0x00000080 // UART Loop Back Enable.
+#define UART_CTL_SIRLP 0x00000004 // UART SIR Low Power Mode.
+#define UART_CTL_SIREN 0x00000002 // UART SIR Enable.
+#define UART_CTL_UARTEN 0x00000001 // UART Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_IFLS register.
+//
+//*****************************************************************************
+#define UART_IFLS_RX_M 0x00000038 // UART Receive Interrupt FIFO
+ // Level Select.
+#define UART_IFLS_RX1_8 0x00000000 // RX FIFO <= 1/8 full
+#define UART_IFLS_RX2_8 0x00000008 // RX FIFO <= 1/4 full
+#define UART_IFLS_RX4_8 0x00000010 // RX FIFO <= 1/2 full (default)
+#define UART_IFLS_RX6_8 0x00000018 // RX FIFO <= 3/4 full
+#define UART_IFLS_RX7_8 0x00000020 // RX FIFO <= 7/8 full
+#define UART_IFLS_TX_M 0x00000007 // UART Transmit Interrupt FIFO
+ // Level Select.
+#define UART_IFLS_TX1_8 0x00000000 // TX FIFO >= 1/8 full
+#define UART_IFLS_TX2_8 0x00000001 // TX FIFO >= 1/4 full
+#define UART_IFLS_TX4_8 0x00000002 // TX FIFO >= 1/2 full (default)
+#define UART_IFLS_TX6_8 0x00000003 // TX FIFO >= 3/4 full
+#define UART_IFLS_TX7_8 0x00000004 // TX FIFO >= 7/8 full
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_IM register.
+//
+//*****************************************************************************
+#define UART_IM_OEIM 0x00000400 // UART Overrun Error Interrupt
+ // Mask.
+#define UART_IM_BEIM 0x00000200 // UART Break Error Interrupt Mask.
+#define UART_IM_PEIM 0x00000100 // UART Parity Error Interrupt
+ // Mask.
+#define UART_IM_FEIM 0x00000080 // UART Framing Error Interrupt
+ // Mask.
+#define UART_IM_RTIM 0x00000040 // UART Receive Time-Out Interrupt
+ // Mask.
+#define UART_IM_TXIM 0x00000020 // UART Transmit Interrupt Mask.
+#define UART_IM_RXIM 0x00000010 // UART Receive Interrupt Mask.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_RIS register.
+//
+//*****************************************************************************
+#define UART_RIS_OERIS 0x00000400 // UART Overrun Error Raw Interrupt
+ // Status.
+#define UART_RIS_BERIS 0x00000200 // UART Break Error Raw Interrupt
+ // Status.
+#define UART_RIS_PERIS 0x00000100 // UART Parity Error Raw Interrupt
+ // Status.
+#define UART_RIS_FERIS 0x00000080 // UART Framing Error Raw Interrupt
+ // Status.
+#define UART_RIS_RTRIS 0x00000040 // UART Receive Time-Out Raw
+ // Interrupt Status.
+#define UART_RIS_TXRIS 0x00000020 // UART Transmit Raw Interrupt
+ // Status.
+#define UART_RIS_RXRIS 0x00000010 // UART Receive Raw Interrupt
+ // Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_MIS register.
+//
+//*****************************************************************************
+#define UART_MIS_OEMIS 0x00000400 // UART Overrun Error Masked
+ // Interrupt Status.
+#define UART_MIS_BEMIS 0x00000200 // UART Break Error Masked
+ // Interrupt Status.
+#define UART_MIS_PEMIS 0x00000100 // UART Parity Error Masked
+ // Interrupt Status.
+#define UART_MIS_FEMIS 0x00000080 // UART Framing Error Masked
+ // Interrupt Status.
+#define UART_MIS_RTMIS 0x00000040 // UART Receive Time-Out Masked
+ // Interrupt Status.
+#define UART_MIS_TXMIS 0x00000020 // UART Transmit Masked Interrupt
+ // Status.
+#define UART_MIS_RXMIS 0x00000010 // UART Receive Masked Interrupt
+ // Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_ICR register.
+//
+//*****************************************************************************
+#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear.
+#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear.
+#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear.
+#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear.
+#define UART_ICR_RTIC 0x00000040 // Receive Time-Out Interrupt
+ // Clear.
+#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear.
+#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MSA register.
+//
+//*****************************************************************************
+#define I2C_MSA_SA_M 0x000000FE // I2C Slave Address.
+#define I2C_MSA_RS 0x00000001 // Receive not send.
+#define I2C_MSA_SA_S 1
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SOAR register.
+//
+//*****************************************************************************
+#define I2C_SOAR_OAR_M 0x0000007F // I2C Slave Own Address.
+#define I2C_SOAR_OAR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SCSR register.
+//
+//*****************************************************************************
+#define I2C_SCSR_FBR 0x00000004 // First Byte Received.
+#define I2C_SCSR_TREQ 0x00000002 // Transmit Request.
+#define I2C_SCSR_DA 0x00000001 // Device Active.
+#define I2C_SCSR_RREQ 0x00000001 // Receive Request.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MCS register.
+//
+//*****************************************************************************
+#define I2C_MCS_BUSBSY 0x00000040 // Bus Busy.
+#define I2C_MCS_IDLE 0x00000020 // I2C Idle.
+#define I2C_MCS_ARBLST 0x00000010 // Arbitration Lost.
+#define I2C_MCS_ACK 0x00000008 // Data Acknowledge Enable.
+#define I2C_MCS_DATACK 0x00000008 // Acknowledge Data.
+#define I2C_MCS_ADRACK 0x00000004 // Acknowledge Address.
+#define I2C_MCS_STOP 0x00000004 // Generate STOP.
+#define I2C_MCS_START 0x00000002 // Generate START.
+#define I2C_MCS_ERROR 0x00000002 // Error.
+#define I2C_MCS_RUN 0x00000001 // I2C Master Enable.
+#define I2C_MCS_BUSY 0x00000001 // I2C Busy.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SDR register.
+//
+//*****************************************************************************
+#define I2C_SDR_DATA_M 0x000000FF // Data for Transfer.
+#define I2C_SDR_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MDR register.
+//
+//*****************************************************************************
+#define I2C_MDR_DATA_M 0x000000FF // Data Transferred.
+#define I2C_MDR_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MTPR register.
+//
+//*****************************************************************************
+#define I2C_MTPR_TPR_M 0x000000FF // SCL Clock Period.
+#define I2C_MTPR_TPR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SIMR register.
+//
+//*****************************************************************************
+#define I2C_SIMR_IM 0x00000001 // Data Interrupt Mask.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SRIS register.
+//
+//*****************************************************************************
+#define I2C_SRIS_RIS 0x00000001 // Data Raw Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MIMR register.
+//
+//*****************************************************************************
+#define I2C_MIMR_IM 0x00000001 // Interrupt Mask.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MRIS register.
+//
+//*****************************************************************************
+#define I2C_MRIS_RIS 0x00000001 // Raw Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SMIS register.
+//
+//*****************************************************************************
+#define I2C_SMIS_MIS 0x00000001 // Data Masked Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SICR register.
+//
+//*****************************************************************************
+#define I2C_SICR_IC 0x00000001 // Data Interrupt Clear.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MMIS register.
+//
+//*****************************************************************************
+#define I2C_MMIS_MIS 0x00000001 // Masked Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MICR register.
+//
+//*****************************************************************************
+#define I2C_MICR_IC 0x00000001 // Interrupt Clear.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MCR register.
+//
+//*****************************************************************************
+#define I2C_MCR_SFE 0x00000020 // I2C Slave Function Enable.
+#define I2C_MCR_MFE 0x00000010 // I2C Master Function Enable.
+#define I2C_MCR_LPBK 0x00000001 // I2C Loopback.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_CFG register.
+//
+//*****************************************************************************
+#define TIMER_CFG_M 0x00000007 // GPTM Configuration.
+#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32-bit timer configuration.
+#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32-bit real-time clock (RTC)
+ // counter configuration.
+#define TIMER_CFG_16_BIT 0x00000004 // 16-bit timer configuration,
+ // function is controlled by bits
+ // 1:0 of GPTMTAMR and GPTMTBMR.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAMR register.
+//
+//*****************************************************************************
+#define TIMER_TAMR_TAAMS 0x00000008 // GPTM TimerA Alternate Mode
+ // Select.
+#define TIMER_TAMR_TACMR 0x00000004 // GPTM TimerA Capture Mode.
+#define TIMER_TAMR_TAMR_M 0x00000003 // GPTM TimerA Mode.
+#define TIMER_TAMR_TAMR_1_SHOT 0x00000001 // One-Shot Timer mode
+#define TIMER_TAMR_TAMR_PERIOD 0x00000002 // Periodic Timer mode
+#define TIMER_TAMR_TAMR_CAP 0x00000003 // Capture mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBMR register.
+//
+//*****************************************************************************
+#define TIMER_TBMR_TBAMS 0x00000008 // GPTM TimerB Alternate Mode
+ // Select.
+#define TIMER_TBMR_TBCMR 0x00000004 // GPTM TimerB Capture Mode.
+#define TIMER_TBMR_TBMR_M 0x00000003 // GPTM TimerB Mode.
+#define TIMER_TBMR_TBMR_1_SHOT 0x00000001 // One-Shot Timer mode
+#define TIMER_TBMR_TBMR_PERIOD 0x00000002 // Periodic Timer mode
+#define TIMER_TBMR_TBMR_CAP 0x00000003 // Capture mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_CTL register.
+//
+//*****************************************************************************
+#define TIMER_CTL_TBPWML 0x00004000 // GPTM TimerB PWM Output Level.
+#define TIMER_CTL_TBOTE 0x00002000 // GPTM TimerB Output Trigger
+ // Enable.
+#define TIMER_CTL_TBEVENT_M 0x00000C00 // GPTM TimerB Event Mode.
+#define TIMER_CTL_TBEVENT_POS 0x00000000 // Positive edge
+#define TIMER_CTL_TBEVENT_NEG 0x00000400 // Negative edge
+#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // Both edges
+#define TIMER_CTL_TBSTALL 0x00000200 // GPTM TimerB Stall Enable.
+#define TIMER_CTL_TBEN 0x00000100 // GPTM TimerB Enable.
+#define TIMER_CTL_TAPWML 0x00000040 // GPTM TimerA PWM Output Level.
+#define TIMER_CTL_TAOTE 0x00000020 // GPTM TimerA Output Trigger
+ // Enable.
+#define TIMER_CTL_RTCEN 0x00000010 // GPTM RTC Enable.
+#define TIMER_CTL_TAEVENT_M 0x0000000C // GPTM TimerA Event Mode.
+#define TIMER_CTL_TAEVENT_POS 0x00000000 // Positive edge
+#define TIMER_CTL_TAEVENT_NEG 0x00000004 // Negative edge
+#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // Both edges
+#define TIMER_CTL_TASTALL 0x00000002 // GPTM TimerA Stall Enable.
+#define TIMER_CTL_TAEN 0x00000001 // GPTM TimerA Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_IMR register.
+//
+//*****************************************************************************
+#define TIMER_IMR_CBEIM 0x00000400 // GPTM CaptureB Event Interrupt
+ // Mask.
+#define TIMER_IMR_CBMIM 0x00000200 // GPTM CaptureB Match Interrupt
+ // Mask.
+#define TIMER_IMR_TBTOIM 0x00000100 // GPTM TimerB Time-Out Interrupt
+ // Mask.
+#define TIMER_IMR_RTCIM 0x00000008 // GPTM RTC Interrupt Mask.
+#define TIMER_IMR_CAEIM 0x00000004 // GPTM CaptureA Event Interrupt
+ // Mask.
+#define TIMER_IMR_CAMIM 0x00000002 // GPTM CaptureA Match Interrupt
+ // Mask.
+#define TIMER_IMR_TATOIM 0x00000001 // GPTM TimerA Time-Out Interrupt
+ // Mask.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_RIS register.
+//
+//*****************************************************************************
+#define TIMER_RIS_CBERIS 0x00000400 // GPTM CaptureB Event Raw
+ // Interrupt.
+#define TIMER_RIS_CBMRIS 0x00000200 // GPTM CaptureB Match Raw
+ // Interrupt.
+#define TIMER_RIS_TBTORIS 0x00000100 // GPTM TimerB Time-Out Raw
+ // Interrupt.
+#define TIMER_RIS_RTCRIS 0x00000008 // GPTM RTC Raw Interrupt.
+#define TIMER_RIS_CAERIS 0x00000004 // GPTM CaptureA Event Raw
+ // Interrupt.
+#define TIMER_RIS_CAMRIS 0x00000002 // GPTM CaptureA Match Raw
+ // Interrupt.
+#define TIMER_RIS_TATORIS 0x00000001 // GPTM TimerA Time-Out Raw
+ // Interrupt.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_MIS register.
+//
+//*****************************************************************************
+#define TIMER_MIS_CBEMIS 0x00000400 // GPTM CaptureB Event Masked
+ // Interrupt.
+#define TIMER_MIS_CBMMIS 0x00000200 // GPTM CaptureB Match Masked
+ // Interrupt.
+#define TIMER_MIS_TBTOMIS 0x00000100 // GPTM TimerB Time-Out Masked
+ // Interrupt.
+#define TIMER_MIS_RTCMIS 0x00000008 // GPTM RTC Masked Interrupt.
+#define TIMER_MIS_CAEMIS 0x00000004 // GPTM CaptureA Event Masked
+ // Interrupt.
+#define TIMER_MIS_CAMMIS 0x00000002 // GPTM CaptureA Match Masked
+ // Interrupt.
+#define TIMER_MIS_TATOMIS 0x00000001 // GPTM TimerA Time-Out Masked
+ // Interrupt.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_ICR register.
+//
+//*****************************************************************************
+#define TIMER_ICR_CBECINT 0x00000400 // GPTM CaptureB Event Interrupt
+ // Clear.
+#define TIMER_ICR_CBMCINT 0x00000200 // GPTM CaptureB Match Interrupt
+ // Clear.
+#define TIMER_ICR_TBTOCINT 0x00000100 // GPTM TimerB Time-Out Interrupt
+ // Clear.
+#define TIMER_ICR_RTCCINT 0x00000008 // GPTM RTC Interrupt Clear.
+#define TIMER_ICR_CAECINT 0x00000004 // GPTM CaptureA Event Interrupt
+ // Clear.
+#define TIMER_ICR_CAMCINT 0x00000002 // GPTM CaptureA Match Raw
+ // Interrupt.
+#define TIMER_ICR_TATOCINT 0x00000001 // GPTM TimerA Time-Out Raw
+ // Interrupt.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAILR register.
+//
+//*****************************************************************************
+#define TIMER_TAILR_TAILRH_M 0xFFFF0000 // GPTM TimerA Interval Load
+ // Register High.
+#define TIMER_TAILR_TAILRL_M 0x0000FFFF // GPTM TimerA Interval Load
+ // Register Low.
+#define TIMER_TAILR_TAILRH_S 16
+#define TIMER_TAILR_TAILRL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBILR register.
+//
+//*****************************************************************************
+#define TIMER_TBILR_TBILRL_M 0x0000FFFF // GPTM TimerB Interval Load
+ // Register.
+#define TIMER_TBILR_TBILRL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAMATCHR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TAMATCHR_TAMRH_M 0xFFFF0000 // GPTM TimerA Match Register High.
+#define TIMER_TAMATCHR_TAMRL_M 0x0000FFFF // GPTM TimerA Match Register Low.
+#define TIMER_TAMATCHR_TAMRH_S 16
+#define TIMER_TAMATCHR_TAMRL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBMATCHR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TBMATCHR_TBMRL_M 0x0000FFFF // GPTM TimerB Match Register Low.
+#define TIMER_TBMATCHR_TBMRL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAPR register.
+//
+//*****************************************************************************
+#define TIMER_TAPR_TAPSR_M 0x000000FF // GPTM TimerA Prescale.
+#define TIMER_TAPR_TAPSR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBPR register.
+//
+//*****************************************************************************
+#define TIMER_TBPR_TBPSR_M 0x000000FF // GPTM TimerB Prescale.
+#define TIMER_TBPR_TBPSR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAPMR register.
+//
+//*****************************************************************************
+#define TIMER_TAPMR_TAPSMR_M 0x000000FF // GPTM TimerA Prescale Match.
+#define TIMER_TAPMR_TAPSMR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBPMR register.
+//
+//*****************************************************************************
+#define TIMER_TBPMR_TBPSMR_M 0x000000FF // GPTM TimerB Prescale Match.
+#define TIMER_TBPMR_TBPSMR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAR register.
+//
+//*****************************************************************************
+#define TIMER_TAR_TARH_M 0xFFFF0000 // GPTM TimerA Register High.
+#define TIMER_TAR_TARL_M 0x0000FFFF // GPTM TimerA Register Low.
+#define TIMER_TAR_TARH_S 16
+#define TIMER_TAR_TARL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBR register.
+//
+//*****************************************************************************
+#define TIMER_TBR_TBRL_M 0x0000FFFF // GPTM TimerB.
+#define TIMER_TBR_TBRL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_ACTSS register.
+//
+//*****************************************************************************
+#define ADC_ACTSS_ASEN3 0x00000008 // ADC SS3 Enable.
+#define ADC_ACTSS_ASEN2 0x00000004 // ADC SS2 Enable.
+#define ADC_ACTSS_ASEN1 0x00000002 // ADC SS1 Enable.
+#define ADC_ACTSS_ASEN0 0x00000001 // ADC SS0 Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_RIS register.
+//
+//*****************************************************************************
+#define ADC_RIS_INR3 0x00000008 // SS3 Raw Interrupt Status.
+#define ADC_RIS_INR2 0x00000004 // SS2 Raw Interrupt Status.
+#define ADC_RIS_INR1 0x00000002 // SS1 Raw Interrupt Status.
+#define ADC_RIS_INR0 0x00000001 // SS0 Raw Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_IM register.
+//
+//*****************************************************************************
+#define ADC_IM_MASK3 0x00000008 // SS3 Interrupt Mask.
+#define ADC_IM_MASK2 0x00000004 // SS2 Interrupt Mask.
+#define ADC_IM_MASK1 0x00000002 // SS1 Interrupt Mask.
+#define ADC_IM_MASK0 0x00000001 // SS0 Interrupt Mask.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_ISC register.
+//
+//*****************************************************************************
+#define ADC_ISC_IN3 0x00000008 // SS3 Interrupt Status and Clear.
+#define ADC_ISC_IN2 0x00000004 // SS2 Interrupt Status and Clear.
+#define ADC_ISC_IN1 0x00000002 // SS1 Interrupt Status and Clear.
+#define ADC_ISC_IN0 0x00000001 // SS0 Interrupt Status and Clear.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_OSTAT register.
+//
+//*****************************************************************************
+#define ADC_OSTAT_OV3 0x00000008 // SS3 FIFO Overflow.
+#define ADC_OSTAT_OV2 0x00000004 // SS2 FIFO Overflow.
+#define ADC_OSTAT_OV1 0x00000002 // SS1 FIFO Overflow.
+#define ADC_OSTAT_OV0 0x00000001 // SS0 FIFO Overflow.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_EMUX register.
+//
+//*****************************************************************************
+#define ADC_EMUX_EM3_M 0x0000F000 // SS3 Trigger Select.
+#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Controller (default)
+#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog Comparator 0
+#define ADC_EMUX_EM3_COMP1 0x00002000 // Analog Comparator 1
+#define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External (GPIO PB4)
+#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer
+#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always (continuously sample)
+#define ADC_EMUX_EM2_M 0x00000F00 // SS2 Trigger Select.
+#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Controller (default)
+#define ADC_EMUX_EM2_COMP0 0x00000100 // Analog Comparator 0
+#define ADC_EMUX_EM2_COMP1 0x00000200 // Analog Comparator 1
+#define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External (GPIO PB4)
+#define ADC_EMUX_EM2_TIMER 0x00000500 // Timer
+#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always (continuously sample)
+#define ADC_EMUX_EM1_M 0x000000F0 // SS1 Trigger Select.
+#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Controller (default)
+#define ADC_EMUX_EM1_COMP0 0x00000010 // Analog Comparator 0
+#define ADC_EMUX_EM1_COMP1 0x00000020 // Analog Comparator 1
+#define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External (GPIO PB4)
+#define ADC_EMUX_EM1_TIMER 0x00000050 // Timer
+#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always (continuously sample)
+#define ADC_EMUX_EM0_M 0x0000000F // SS0 Trigger Select.
+#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Controller (default)
+#define ADC_EMUX_EM0_COMP0 0x00000001 // Analog Comparator 0
+#define ADC_EMUX_EM0_COMP1 0x00000002 // Analog Comparator 1
+#define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External (GPIO PB4)
+#define ADC_EMUX_EM0_TIMER 0x00000005 // Timer
+#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always (continuously sample)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_USTAT register.
+//
+//*****************************************************************************
+#define ADC_USTAT_UV3 0x00000008 // SS3 FIFO Underflow.
+#define ADC_USTAT_UV2 0x00000004 // SS2 FIFO Underflow.
+#define ADC_USTAT_UV1 0x00000002 // SS1 FIFO Underflow.
+#define ADC_USTAT_UV0 0x00000001 // SS0 FIFO Underflow.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSPRI register.
+//
+//*****************************************************************************
+#define ADC_SSPRI_SS3_M 0x00003000 // SS3 Priority.
+#define ADC_SSPRI_SS3_1ST 0x00000000 // First priority
+#define ADC_SSPRI_SS3_2ND 0x00001000 // Second priority
+#define ADC_SSPRI_SS3_3RD 0x00002000 // Third priority
+#define ADC_SSPRI_SS3_4TH 0x00003000 // Fourth priority
+#define ADC_SSPRI_SS2_M 0x00000300 // SS2 Priority.
+#define ADC_SSPRI_SS2_1ST 0x00000000 // First priority
+#define ADC_SSPRI_SS2_2ND 0x00000100 // Second priority
+#define ADC_SSPRI_SS2_3RD 0x00000200 // Third priority
+#define ADC_SSPRI_SS2_4TH 0x00000300 // Fourth priority
+#define ADC_SSPRI_SS1_M 0x00000030 // SS1 Priority.
+#define ADC_SSPRI_SS1_1ST 0x00000000 // First priority
+#define ADC_SSPRI_SS1_2ND 0x00000010 // Second priority
+#define ADC_SSPRI_SS1_3RD 0x00000020 // Third priority
+#define ADC_SSPRI_SS1_4TH 0x00000030 // Fourth priority
+#define ADC_SSPRI_SS0_M 0x00000003 // SS0 Priority.
+#define ADC_SSPRI_SS0_1ST 0x00000000 // First priority
+#define ADC_SSPRI_SS0_2ND 0x00000001 // Second priority
+#define ADC_SSPRI_SS0_3RD 0x00000002 // Third priority
+#define ADC_SSPRI_SS0_4TH 0x00000003 // Fourth priority
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_PSSI register.
+//
+//*****************************************************************************
+#define ADC_PSSI_SS3 0x00000008 // SS3 Initiate.
+#define ADC_PSSI_SS2 0x00000004 // SS2 Initiate.
+#define ADC_PSSI_SS1 0x00000002 // SS1 Initiate.
+#define ADC_PSSI_SS0 0x00000001 // SS0 Initiate.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SAC register.
+//
+//*****************************************************************************
+#define ADC_SAC_AVG_M 0x00000007 // Hardware Averaging Control.
+#define ADC_SAC_AVG_OFF 0x00000000 // No hardware oversampling
+#define ADC_SAC_AVG_2X 0x00000001 // 2x hardware oversampling
+#define ADC_SAC_AVG_4X 0x00000002 // 4x hardware oversampling
+#define ADC_SAC_AVG_8X 0x00000003 // 8x hardware oversampling
+#define ADC_SAC_AVG_16X 0x00000004 // 16x hardware oversampling
+#define ADC_SAC_AVG_32X 0x00000005 // 32x hardware oversampling
+#define ADC_SAC_AVG_64X 0x00000006 // 64x hardware oversampling
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX0 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX0_MUX7_M 0x70000000 // 8th Sample Input Select.
+#define ADC_SSMUX0_MUX6_M 0x07000000 // 7th Sample Input Select.
+#define ADC_SSMUX0_MUX5_M 0x00700000 // 6th Sample Input Select.
+#define ADC_SSMUX0_MUX4_M 0x00070000 // 5th Sample Input Select.
+#define ADC_SSMUX0_MUX3_M 0x00007000 // 4th Sample Input Select.
+#define ADC_SSMUX0_MUX2_M 0x00000700 // 3rd Sample Input Select.
+#define ADC_SSMUX0_MUX1_M 0x00000070 // 2nd Sample Input Select.
+#define ADC_SSMUX0_MUX0_M 0x00000007 // 1st Sample Input Select.
+#define ADC_SSMUX0_MUX7_S 28
+#define ADC_SSMUX0_MUX6_S 24
+#define ADC_SSMUX0_MUX5_S 20
+#define ADC_SSMUX0_MUX4_S 16
+#define ADC_SSMUX0_MUX3_S 12
+#define ADC_SSMUX0_MUX2_S 8
+#define ADC_SSMUX0_MUX1_S 4
+#define ADC_SSMUX0_MUX0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL0 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL0_TS7 0x80000000 // 8th Sample Temp Sensor Select.
+#define ADC_SSCTL0_IE7 0x40000000 // 8th Sample Interrupt Enable.
+#define ADC_SSCTL0_END7 0x20000000 // 8th Sample is End of Sequence.
+#define ADC_SSCTL0_D7 0x10000000 // 8th Sample Diff Input Select.
+#define ADC_SSCTL0_TS6 0x08000000 // 7th Sample Temp Sensor Select.
+#define ADC_SSCTL0_IE6 0x04000000 // 7th Sample Interrupt Enable.
+#define ADC_SSCTL0_END6 0x02000000 // 7th Sample is End of Sequence.
+#define ADC_SSCTL0_D6 0x01000000 // 7th Sample Diff Input Select.
+#define ADC_SSCTL0_TS5 0x00800000 // 6th Sample Temp Sensor Select.
+#define ADC_SSCTL0_IE5 0x00400000 // 6th Sample Interrupt Enable.
+#define ADC_SSCTL0_END5 0x00200000 // 6th Sample is End of Sequence.
+#define ADC_SSCTL0_D5 0x00100000 // 6th Sample Diff Input Select.
+#define ADC_SSCTL0_TS4 0x00080000 // 5th Sample Temp Sensor Select.
+#define ADC_SSCTL0_IE4 0x00040000 // 5th Sample Interrupt Enable.
+#define ADC_SSCTL0_END4 0x00020000 // 5th Sample is End of Sequence.
+#define ADC_SSCTL0_D4 0x00010000 // 5th Sample Diff Input Select.
+#define ADC_SSCTL0_TS3 0x00008000 // 4th Sample Temp Sensor Select.
+#define ADC_SSCTL0_IE3 0x00004000 // 4th Sample Interrupt Enable.
+#define ADC_SSCTL0_END3 0x00002000 // 4th Sample is End of Sequence.
+#define ADC_SSCTL0_D3 0x00001000 // 4th Sample Diff Input Select.
+#define ADC_SSCTL0_TS2 0x00000800 // 3rd Sample Temp Sensor Select.
+#define ADC_SSCTL0_IE2 0x00000400 // 3rd Sample Interrupt Enable.
+#define ADC_SSCTL0_END2 0x00000200 // 3rd Sample is End of Sequence.
+#define ADC_SSCTL0_D2 0x00000100 // 3rd Sample Diff Input Select.
+#define ADC_SSCTL0_TS1 0x00000080 // 2nd Sample Temp Sensor Select.
+#define ADC_SSCTL0_IE1 0x00000040 // 2nd Sample Interrupt Enable.
+#define ADC_SSCTL0_END1 0x00000020 // 2nd Sample is End of Sequence.
+#define ADC_SSCTL0_D1 0x00000010 // 2nd Sample Diff Input Select.
+#define ADC_SSCTL0_TS0 0x00000008 // 1st Sample Temp Sensor Select.
+#define ADC_SSCTL0_IE0 0x00000004 // 1st Sample Interrupt Enable.
+#define ADC_SSCTL0_END0 0x00000002 // 1st Sample is End of Sequence.
+#define ADC_SSCTL0_D0 0x00000001 // 1st Sample Diff Input Select.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO0 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO0_DATA_M 0x000003FF // Conversion Result Data.
+#define ADC_SSFIFO0_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT0 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT0_FULL 0x00001000 // FIFO Full.
+#define ADC_SSFSTAT0_EMPTY 0x00000100 // FIFO Empty.
+#define ADC_SSFSTAT0_HPTR_M 0x000000F0 // FIFO Head Pointer.
+#define ADC_SSFSTAT0_TPTR_M 0x0000000F // FIFO Tail Pointer.
+#define ADC_SSFSTAT0_HPTR_S 4
+#define ADC_SSFSTAT0_TPTR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX1 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX1_MUX3_M 0x00007000 // 4th Sample Input Select.
+#define ADC_SSMUX1_MUX2_M 0x00000700 // 3rd Sample Input Select.
+#define ADC_SSMUX1_MUX1_M 0x00000070 // 2nd Sample Input Select.
+#define ADC_SSMUX1_MUX0_M 0x00000007 // 1st Sample Input Select.
+#define ADC_SSMUX1_MUX3_S 12
+#define ADC_SSMUX1_MUX2_S 8
+#define ADC_SSMUX1_MUX1_S 4
+#define ADC_SSMUX1_MUX0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL1 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL1_TS3 0x00008000 // 4th Sample Temp Sensor Select.
+#define ADC_SSCTL1_IE3 0x00004000 // 4th Sample Interrupt Enable.
+#define ADC_SSCTL1_END3 0x00002000 // 4th Sample is End of Sequence.
+#define ADC_SSCTL1_D3 0x00001000 // 4th Sample Diff Input Select.
+#define ADC_SSCTL1_TS2 0x00000800 // 3rd Sample Temp Sensor Select.
+#define ADC_SSCTL1_IE2 0x00000400 // 3rd Sample Interrupt Enable.
+#define ADC_SSCTL1_END2 0x00000200 // 3rd Sample is End of Sequence.
+#define ADC_SSCTL1_D2 0x00000100 // 3rd Sample Diff Input Select.
+#define ADC_SSCTL1_TS1 0x00000080 // 2nd Sample Temp Sensor Select.
+#define ADC_SSCTL1_IE1 0x00000040 // 2nd Sample Interrupt Enable.
+#define ADC_SSCTL1_END1 0x00000020 // 2nd Sample is End of Sequence.
+#define ADC_SSCTL1_D1 0x00000010 // 2nd Sample Diff Input Select.
+#define ADC_SSCTL1_TS0 0x00000008 // 1st Sample Temp Sensor Select.
+#define ADC_SSCTL1_IE0 0x00000004 // 1st Sample Interrupt Enable.
+#define ADC_SSCTL1_END0 0x00000002 // 1st Sample is End of Sequence.
+#define ADC_SSCTL1_D0 0x00000001 // 1st Sample Diff Input Select.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO1 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO1_DATA_M 0x000003FF // Conversion Result Data.
+#define ADC_SSFIFO1_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT1 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT1_FULL 0x00001000 // FIFO Full.
+#define ADC_SSFSTAT1_EMPTY 0x00000100 // FIFO Empty.
+#define ADC_SSFSTAT1_HPTR_M 0x000000F0 // FIFO Head Pointer.
+#define ADC_SSFSTAT1_TPTR_M 0x0000000F // FIFO Tail Pointer.
+#define ADC_SSFSTAT1_HPTR_S 4
+#define ADC_SSFSTAT1_TPTR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX2 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX2_MUX3_M 0x00007000 // 4th Sample Input Select.
+#define ADC_SSMUX2_MUX2_M 0x00000700 // 3rd Sample Input Select.
+#define ADC_SSMUX2_MUX1_M 0x00000070 // 2nd Sample Input Select.
+#define ADC_SSMUX2_MUX0_M 0x00000007 // 1st Sample Input Select.
+#define ADC_SSMUX2_MUX3_S 12
+#define ADC_SSMUX2_MUX2_S 8
+#define ADC_SSMUX2_MUX1_S 4
+#define ADC_SSMUX2_MUX0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL2 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL2_TS3 0x00008000 // 4th Sample Temp Sensor Select.
+#define ADC_SSCTL2_IE3 0x00004000 // 4th Sample Interrupt Enable.
+#define ADC_SSCTL2_END3 0x00002000 // 4th Sample is End of Sequence.
+#define ADC_SSCTL2_D3 0x00001000 // 4th Sample Diff Input Select.
+#define ADC_SSCTL2_TS2 0x00000800 // 3rd Sample Temp Sensor Select.
+#define ADC_SSCTL2_IE2 0x00000400 // 3rd Sample Interrupt Enable.
+#define ADC_SSCTL2_END2 0x00000200 // 3rd Sample is End of Sequence.
+#define ADC_SSCTL2_D2 0x00000100 // 3rd Sample Diff Input Select.
+#define ADC_SSCTL2_TS1 0x00000080 // 2nd Sample Temp Sensor Select.
+#define ADC_SSCTL2_IE1 0x00000040 // 2nd Sample Interrupt Enable.
+#define ADC_SSCTL2_END1 0x00000020 // 2nd Sample is End of Sequence.
+#define ADC_SSCTL2_D1 0x00000010 // 2nd Sample Diff Input Select.
+#define ADC_SSCTL2_TS0 0x00000008 // 1st Sample Temp Sensor Select.
+#define ADC_SSCTL2_IE0 0x00000004 // 1st Sample Interrupt Enable.
+#define ADC_SSCTL2_END0 0x00000002 // 1st Sample is End of Sequence.
+#define ADC_SSCTL2_D0 0x00000001 // 1st Sample Diff Input Select.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO2 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO2_DATA_M 0x000003FF // Conversion Result Data.
+#define ADC_SSFIFO2_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT2 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT2_FULL 0x00001000 // FIFO Full.
+#define ADC_SSFSTAT2_EMPTY 0x00000100 // FIFO Empty.
+#define ADC_SSFSTAT2_HPTR_M 0x000000F0 // FIFO Head Pointer.
+#define ADC_SSFSTAT2_TPTR_M 0x0000000F // FIFO Tail Pointer.
+#define ADC_SSFSTAT2_HPTR_S 4
+#define ADC_SSFSTAT2_TPTR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX3 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX3_MUX0_M 0x00000007 // 1st Sample Input Select.
+#define ADC_SSMUX3_MUX0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL3 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL3_TS0 0x00000008 // 1st Sample Temp Sensor Select.
+#define ADC_SSCTL3_IE0 0x00000004 // 1st Sample Interrupt Enable.
+#define ADC_SSCTL3_END0 0x00000002 // 1st Sample is End of Sequence.
+#define ADC_SSCTL3_D0 0x00000001 // 1st Sample Diff Input Select.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO3 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO3_DATA_M 0x000003FF // Conversion Result Data.
+#define ADC_SSFIFO3_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT3 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT3_FULL 0x00001000 // FIFO Full.
+#define ADC_SSFSTAT3_EMPTY 0x00000100 // FIFO Empty.
+#define ADC_SSFSTAT3_HPTR_M 0x000000F0 // FIFO Head Pointer.
+#define ADC_SSFSTAT3_TPTR_M 0x0000000F // FIFO Tail Pointer.
+#define ADC_SSFSTAT3_HPTR_S 4
+#define ADC_SSFSTAT3_TPTR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_TMLB register.
+//
+//*****************************************************************************
+#define ADC_TMLB_LB 0x00000001 // Loopback Mode Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the the interpretation of the data in the
+// SSFIFOx when the ADC TMLB is enabled.
+//
+//*****************************************************************************
+#define ADC_SSFIFO_TMLB_CNT_M 0x000003C0 // Continuous Sample Counter.
+#define ADC_SSFIFO_TMLB_CONT 0x00000020 // Continuation Sample Indicator.
+#define ADC_SSFIFO_TMLB_DIFF 0x00000010 // Differential Sample Indicator.
+#define ADC_SSFIFO_TMLB_TS 0x00000008 // Temp Sensor Sample Indicator.
+#define ADC_SSFIFO_TMLB_MUX_M 0x00000007 // Analog Input Indicator.
+#define ADC_SSFIFO_TMLB_CNT_S 6 // Sample counter shift
+#define ADC_SSFIFO_TMLB_MUX_S 0 // Input channel number shift
+
+//*****************************************************************************
+//
+// The following are defines for the the interpretation of the data in the
+// SSFIFOx when the ADC TMLB is enabled.
+//
+//*****************************************************************************
+#define ADC_TMLB_CNT_M 0x000003C0 // Continuous Sample Counter.
+#define ADC_TMLB_CONT 0x00000020 // Continuation Sample Indicator.
+#define ADC_TMLB_DIFF 0x00000010 // Differential Sample Indicator.
+#define ADC_TMLB_TS 0x00000008 // Temp Sensor Sample Indicator.
+#define ADC_TMLB_MUX_M 0x00000007 // Analog Input Indicator.
+#define ADC_TMLB_CNT_S 6 // Sample counter shift
+#define ADC_TMLB_MUX_S 0 // Input channel number shift
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACMIS register.
+//
+//*****************************************************************************
+#define COMP_ACMIS_IN1 0x00000002 // Comparator 1 Masked Interrupt
+ // Status.
+#define COMP_ACMIS_IN0 0x00000001 // Comparator 0 Masked Interrupt
+ // Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACRIS register.
+//
+//*****************************************************************************
+#define COMP_ACRIS_IN1 0x00000002 // Comparator 1 Interrupt Status.
+#define COMP_ACRIS_IN0 0x00000001 // Comparator 0 Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACINTEN register.
+//
+//*****************************************************************************
+#define COMP_ACINTEN_IN1 0x00000002 // Comparator 1 Interrupt Enable.
+#define COMP_ACINTEN_IN0 0x00000001 // Comparator 0 Interrupt Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACREFCTL
+// register.
+//
+//*****************************************************************************
+#define COMP_ACREFCTL_EN 0x00000200 // Resistor Ladder Enable.
+#define COMP_ACREFCTL_RNG 0x00000100 // Resistor Ladder Range.
+#define COMP_ACREFCTL_VREF_M 0x0000000F // Resistor Ladder Voltage Ref.
+#define COMP_ACREFCTL_VREF_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACSTAT0 register.
+//
+//*****************************************************************************
+#define COMP_ACSTAT0_OVAL 0x00000002 // Comparator Output Value.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACCTL0 register.
+//
+//*****************************************************************************
+#define COMP_ACCTL0_TOEN 0x00000800 // Trigger Output Enable.
+#define COMP_ACCTL0_ASRCP_M 0x00000600 // Analog Source Positive.
+#define COMP_ACCTL0_ASRCP_PIN 0x00000000 // Pin value
+#define COMP_ACCTL0_ASRCP_PIN0 0x00000200 // Pin value of C0+
+#define COMP_ACCTL0_ASRCP_REF 0x00000400 // Internal voltage reference
+#define COMP_ACCTL0_TSLVAL 0x00000080 // Trigger Sense Level Value.
+#define COMP_ACCTL0_TSEN_M 0x00000060 // Trigger Sense.
+#define COMP_ACCTL0_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL
+#define COMP_ACCTL0_TSEN_FALL 0x00000020 // Falling edge
+#define COMP_ACCTL0_TSEN_RISE 0x00000040 // Rising edge
+#define COMP_ACCTL0_TSEN_BOTH 0x00000060 // Either edge
+#define COMP_ACCTL0_ISLVAL 0x00000010 // Interrupt Sense Level Value.
+#define COMP_ACCTL0_ISEN_M 0x0000000C // Interrupt Sense.
+#define COMP_ACCTL0_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL
+#define COMP_ACCTL0_ISEN_FALL 0x00000004 // Falling edge
+#define COMP_ACCTL0_ISEN_RISE 0x00000008 // Rising edge
+#define COMP_ACCTL0_ISEN_BOTH 0x0000000C // Either edge
+#define COMP_ACCTL0_CINV 0x00000002 // Comparator Output Invert.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACSTAT1 register.
+//
+//*****************************************************************************
+#define COMP_ACSTAT1_OVAL 0x00000002 // Comparator Output Value.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACCTL1 register.
+//
+//*****************************************************************************
+#define COMP_ACCTL1_TOEN 0x00000800 // Trigger Output Enable.
+#define COMP_ACCTL1_ASRCP_M 0x00000600 // Analog Source Positive.
+#define COMP_ACCTL1_ASRCP_PIN 0x00000000 // Pin value
+#define COMP_ACCTL1_ASRCP_PIN0 0x00000200 // Pin value of C0+
+#define COMP_ACCTL1_ASRCP_REF 0x00000400 // Internal voltage reference
+#define COMP_ACCTL1_TSLVAL 0x00000080 // Trigger Sense Level Value.
+#define COMP_ACCTL1_TSEN_M 0x00000060 // Trigger Sense.
+#define COMP_ACCTL1_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL
+#define COMP_ACCTL1_TSEN_FALL 0x00000020 // Falling edge
+#define COMP_ACCTL1_TSEN_RISE 0x00000040 // Rising edge
+#define COMP_ACCTL1_TSEN_BOTH 0x00000060 // Either edge
+#define COMP_ACCTL1_ISLVAL 0x00000010 // Interrupt Sense Level Value.
+#define COMP_ACCTL1_ISEN_M 0x0000000C // Interrupt Sense.
+#define COMP_ACCTL1_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL
+#define COMP_ACCTL1_ISEN_FALL 0x00000004 // Falling edge
+#define COMP_ACCTL1_ISEN_RISE 0x00000008 // Rising edge
+#define COMP_ACCTL1_ISEN_BOTH 0x0000000C // Either edge
+#define COMP_ACCTL1_CINV 0x00000002 // Comparator Output Invert.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MR0 register.
+//
+//*****************************************************************************
+#define PHY_MR0_RESET 0x00008000 // Reset Registers.
+#define PHY_MR0_LOOPBK 0x00004000 // Loopback Mode.
+#define PHY_MR0_SPEEDSL 0x00002000 // Speed Select.
+#define PHY_MR0_ANEGEN 0x00001000 // Auto-Negotiation Enable.
+#define PHY_MR0_PWRDN 0x00000800 // Power Down.
+#define PHY_MR0_ISO 0x00000400 // Isolate.
+#define PHY_MR0_RANEG 0x00000200 // Restart Auto-Negotiation.
+#define PHY_MR0_DUPLEX 0x00000100 // Set Duplex Mode.
+#define PHY_MR0_COLT 0x00000080 // Collision Test.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_RIS register.
+//
+//*****************************************************************************
+#define MAC_RIS_PHYINT 0x00000040 // PHY Interrupt.
+#define MAC_RIS_MDINT 0x00000020 // MII Transaction Complete.
+#define MAC_RIS_RXER 0x00000010 // Receive Error.
+#define MAC_RIS_FOV 0x00000008 // FIFO Overrun.
+#define MAC_RIS_TXEMP 0x00000004 // Transmit FIFO Empty.
+#define MAC_RIS_TXER 0x00000002 // Transmit Error.
+#define MAC_RIS_RXINT 0x00000001 // Packet Received.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_IACK register.
+//
+//*****************************************************************************
+#define MAC_IACK_PHYINT 0x00000040 // Clear PHY Interrupt.
+#define MAC_IACK_MDINT 0x00000020 // Clear MII Transaction Complete.
+#define MAC_IACK_RXER 0x00000010 // Clear Receive Error.
+#define MAC_IACK_FOV 0x00000008 // Clear FIFO Overrun.
+#define MAC_IACK_TXEMP 0x00000004 // Clear Transmit FIFO Empty.
+#define MAC_IACK_TXER 0x00000002 // Clear Transmit Error.
+#define MAC_IACK_RXINT 0x00000001 // Clear Packet Received.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MR1 register.
+//
+//*****************************************************************************
+#define PHY_MR1_100X_F 0x00004000 // 100BASE-TX Full-Duplex Mode.
+#define PHY_MR1_100X_H 0x00002000 // 100BASE-TX Half-Duplex Mode.
+#define PHY_MR1_10T_F 0x00001000 // 10BASE-T Full-Duplex Mode.
+#define PHY_MR1_10T_H 0x00000800 // 10BASE-T Half-Duplex Mode.
+#define PHY_MR1_MFPS 0x00000040 // Management Frames with Preamble
+ // Suppressed.
+#define PHY_MR1_ANEGC 0x00000020 // Auto-Negotiation Complete.
+#define PHY_MR1_RFAULT 0x00000010 // Remote Fault.
+#define PHY_MR1_ANEGA 0x00000008 // Auto-Negotiation.
+#define PHY_MR1_LINK 0x00000004 // Link Made.
+#define PHY_MR1_JAB 0x00000002 // Jabber Condition.
+#define PHY_MR1_EXTD 0x00000001 // Extended Capabilities.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MR2 register.
+//
+//*****************************************************************************
+#define PHY_MR2_OUI_M 0x0000FFFF // Organizationally Unique
+ // Identifier[21:6].
+#define PHY_MR2_OUI_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MR3 register.
+//
+//*****************************************************************************
+#define PHY_MR3_OUI_M 0x0000FC00 // Organizationally Unique
+ // Identifier[5:0].
+#define PHY_MR3_MN_M 0x000003F0 // Model Number.
+#define PHY_MR3_RN_M 0x0000000F // Revision Number.
+#define PHY_MR3_OUI_S 10
+#define PHY_MR3_MN_S 4
+#define PHY_MR3_RN_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_IM register.
+//
+//*****************************************************************************
+#define MAC_IM_PHYINTM 0x00000040 // Mask PHY Interrupt.
+#define MAC_IM_MDINTM 0x00000020 // Mask MII Transaction Complete.
+#define MAC_IM_RXERM 0x00000010 // Mask Receive Error.
+#define MAC_IM_FOVM 0x00000008 // Mask FIFO Overrun.
+#define MAC_IM_TXEMPM 0x00000004 // Mask Transmit FIFO Empty.
+#define MAC_IM_TXERM 0x00000002 // Mask Transmit Error.
+#define MAC_IM_RXINTM 0x00000001 // Mask Packet Received.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MR4 register.
+//
+//*****************************************************************************
+#define PHY_MR4_NP 0x00008000 // Next Page.
+#define PHY_MR4_RF 0x00002000 // Remote Fault.
+#define PHY_MR4_A3 0x00000100 // Technology Ability Field[3].
+#define PHY_MR4_A2 0x00000080 // Technology Ability Field[2].
+#define PHY_MR4_A1 0x00000040 // Technology Ability Field[1].
+#define PHY_MR4_A0 0x00000020 // Technology Ability Field[0].
+#define PHY_MR4_S_M 0x0000001F // Selector Field.
+#define PHY_MR4_S_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MR5 register.
+//
+//*****************************************************************************
+#define PHY_MR5_NP 0x00008000 // Next Page.
+#define PHY_MR5_ACK 0x00004000 // Acknowledge.
+#define PHY_MR5_RF 0x00002000 // Remote Fault.
+#define PHY_MR5_A_M 0x00001FE0 // Technology Ability Field.
+#define PHY_MR5_S_M 0x0000001F // Selector Field.
+#define PHY_MR5_S_8023 0x00000001 // IEEE Std 802.3
+#define PHY_MR5_S_8029 0x00000002 // IEEE Std 802.9 ISLAN-16T
+#define PHY_MR5_S_8025 0x00000003 // IEEE Std 802.5
+#define PHY_MR5_S_1394 0x00000004 // IEEE Std 1394
+#define PHY_MR5_A_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MR6 register.
+//
+//*****************************************************************************
+#define PHY_MR6_PDF 0x00000010 // Parallel Detection Fault.
+#define PHY_MR6_LPNPA 0x00000008 // Link Partner is Next Page Able.
+#define PHY_MR6_PRX 0x00000002 // New Page Received.
+#define PHY_MR6_LPANEGA 0x00000001 // Link Partner is Auto-Negotiation
+ // Able.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_RCTL register.
+//
+//*****************************************************************************
+#define MAC_RCTL_RSTFIFO 0x00000010 // Clear Receive FIFO.
+#define MAC_RCTL_BADCRC 0x00000008 // Enable Reject Bad CRC.
+#define MAC_RCTL_PRMS 0x00000004 // Enable Promiscuous Mode.
+#define MAC_RCTL_AMUL 0x00000002 // Enable Multicast Frames.
+#define MAC_RCTL_RXEN 0x00000001 // Enable Receiver.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_TCTL register.
+//
+//*****************************************************************************
+#define MAC_TCTL_DUPLEX 0x00000010 // Enable Duplex Mode.
+#define MAC_TCTL_CRC 0x00000004 // Enable CRC Generation.
+#define MAC_TCTL_PADEN 0x00000002 // Enable Packet Padding.
+#define MAC_TCTL_TXEN 0x00000001 // Enable Transmitter.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_DATA register.
+//
+//*****************************************************************************
+#define MAC_DATA_TXDATA_M 0xFFFFFFFF // Transmit FIFO Data.
+#define MAC_DATA_RXDATA_M 0xFFFFFFFF // Receive FIFO Data.
+#define MAC_DATA_RXDATA_S 0
+#define MAC_DATA_TXDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MR16 register.
+//
+//*****************************************************************************
+#define PHY_MR16_RPTR 0x00008000 // Repeater Mode.
+#define PHY_MR16_INPOL 0x00004000 // Interrupt Polarity.
+#define PHY_MR16_TXHIM 0x00001000 // Transmit High Impedance Mode.
+#define PHY_MR16_SQEI 0x00000800 // SQE Inhibit Testing.
+#define PHY_MR16_NL10 0x00000400 // Natural Loopback Mode.
+#define PHY_MR16_APOL 0x00000020 // Auto-Polarity Disable.
+#define PHY_MR16_RVSPOL 0x00000010 // Receive Data Polarity.
+#define PHY_MR16_PCSBP 0x00000002 // PCS Bypass.
+#define PHY_MR16_RXCC 0x00000001 // Receive Clock Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MR17 register.
+//
+//*****************************************************************************
+#define PHY_MR17_JABBER_IE 0x00008000 // Jabber Interrupt Enable.
+#define PHY_MR17_RXER_IE 0x00004000 // Receive Error Interrupt Enable.
+#define PHY_MR17_PRX_IE 0x00002000 // Page Received Interrupt Enable.
+#define PHY_MR17_PDF_IE 0x00001000 // Parallel Detection Fault
+ // Interrupt Enable.
+#define PHY_MR17_LPACK_IE 0x00000800 // LP Acknowledge Interrupt Enable.
+#define PHY_MR17_LSCHG_IE 0x00000400 // Link Status Change Interrupt
+ // Enable.
+#define PHY_MR17_RFAULT_IE 0x00000200 // Remote Fault Interrupt Enable.
+#define PHY_MR17_ANEGCOMP_IE 0x00000100 // Auto-Negotiation Complete
+ // Interrupt Enable.
+#define PHY_MR17_JABBER_INT 0x00000080 // Jabber Event Interrupt.
+#define PHY_MR17_RXER_INT 0x00000040 // Receive Error Interrupt.
+#define PHY_MR17_PRX_INT 0x00000020 // Page Receive Interrupt.
+#define PHY_MR17_PDF_INT 0x00000010 // Parallel Detection Fault
+ // Interrupt.
+#define PHY_MR17_LPACK_INT 0x00000008 // LP Acknowledge Interrupt.
+#define PHY_MR17_LSCHG_INT 0x00000004 // Link Status Change Interrupt.
+#define PHY_MR17_RFAULT_INT 0x00000002 // Remote Fault Interrupt.
+#define PHY_MR17_ANEGCOMP_INT 0x00000001 // Auto-Negotiation Complete
+ // Interrupt.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MR18 register.
+//
+//*****************************************************************************
+#define PHY_MR18_ANEGF 0x00001000 // Auto-Negotiation Failure.
+#define PHY_MR18_DPLX 0x00000800 // Duplex Mode.
+#define PHY_MR18_RATE 0x00000400 // Rate.
+#define PHY_MR18_RXSD 0x00000200 // Receive Detection.
+#define PHY_MR18_RX_LOCK 0x00000100 // Receive PLL Lock.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MR19 register.
+//
+//*****************************************************************************
+#define PHY_MR19_TXO_M 0x0000C000 // Transmit Amplitude Selection.
+#define PHY_MR19_TXO_00DB 0x00000000 // Gain set for 0.0dB of insertion
+ // loss
+#define PHY_MR19_TXO_04DB 0x00004000 // Gain set for 0.4dB of insertion
+ // loss
+#define PHY_MR19_TXO_08DB 0x00008000 // Gain set for 0.8dB of insertion
+ // loss
+#define PHY_MR19_TXO_12DB 0x0000C000 // Gain set for 1.2dB of insertion
+ // loss
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_IA0 register.
+//
+//*****************************************************************************
+#define MAC_IA0_MACOCT4_M 0xFF000000 // MAC Address Octet 4.
+#define MAC_IA0_MACOCT3_M 0x00FF0000 // MAC Address Octet 3.
+#define MAC_IA0_MACOCT2_M 0x0000FF00 // MAC Address Octet 2.
+#define MAC_IA0_MACOCT1_M 0x000000FF // MAC Address Octet 1.
+#define MAC_IA0_MACOCT4_S 24
+#define MAC_IA0_MACOCT3_S 16
+#define MAC_IA0_MACOCT2_S 8
+#define MAC_IA0_MACOCT1_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MR23 register.
+//
+//*****************************************************************************
+#define PHY_MR23_LED1_M 0x000000F0 // LED1 Source.
+#define PHY_MR23_LED1_LINK 0x00000000 // Link OK
+#define PHY_MR23_LED1_RXTX 0x00000010 // RX or TX Activity (Default LED1)
+#define PHY_MR23_LED1_100 0x00000050 // 100BASE-TX mode
+#define PHY_MR23_LED1_10 0x00000060 // 10BASE-T mode
+#define PHY_MR23_LED1_DUPLEX 0x00000070 // Full-Duplex
+#define PHY_MR23_LED1_LINKACT 0x00000080 // Link OK & Blink=RX or TX
+ // Activity
+#define PHY_MR23_LED0_M 0x0000000F // LED0 Source.
+#define PHY_MR23_LED0_LINK 0x00000000 // Link OK (Default LED0)
+#define PHY_MR23_LED0_RXTX 0x00000001 // RX or TX Activity
+#define PHY_MR23_LED0_100 0x00000005 // 100BASE-TX mode
+#define PHY_MR23_LED0_10 0x00000006 // 10BASE-T mode
+#define PHY_MR23_LED0_DUPLEX 0x00000007 // Full-Duplex
+#define PHY_MR23_LED0_LINKACT 0x00000008 // Link OK & Blink=RX or TX
+ // Activity
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_IA1 register.
+//
+//*****************************************************************************
+#define MAC_IA1_MACOCT6_M 0x0000FF00 // MAC Address Octet 6.
+#define MAC_IA1_MACOCT5_M 0x000000FF // MAC Address Octet 5.
+#define MAC_IA1_MACOCT6_S 8
+#define MAC_IA1_MACOCT5_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MR24 register.
+//
+//*****************************************************************************
+#define PHY_MR24_PD_MODE 0x00000080 // Parallel Detection Mode.
+#define PHY_MR24_AUTO_SW 0x00000040 // Auto-Switching Enable.
+#define PHY_MR24_MDIX 0x00000020 // Auto-Switching Configuration.
+#define PHY_MR24_MDIX_CM 0x00000010 // Auto-Switching Complete.
+#define PHY_MR24_MDIX_SD_M 0x0000000F // Auto-Switching Seed.
+#define PHY_MR24_MDIX_SD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_THR register.
+//
+//*****************************************************************************
+#define MAC_THR_THRESH_M 0x0000003F // Threshold Value.
+#define MAC_THR_THRESH_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MCTL register.
+//
+//*****************************************************************************
+#define MAC_MCTL_REGADR_M 0x000000F8 // MII Register Address.
+#define MAC_MCTL_WRITE 0x00000002 // MII Register Transaction Type.
+#define MAC_MCTL_START 0x00000001 // MII Register Transaction Enable.
+#define MAC_MCTL_REGADR_S 3
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MDV register.
+//
+//*****************************************************************************
+#define MAC_MDV_DIV_M 0x000000FF // Clock Divider.
+#define MAC_MDV_DIV_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MTXD register.
+//
+//*****************************************************************************
+#define MAC_MTXD_MDTX_M 0x0000FFFF // MII Register Transmit Data.
+#define MAC_MTXD_MDTX_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MRXD register.
+//
+//*****************************************************************************
+#define MAC_MRXD_MDRX_M 0x0000FFFF // MII Register Receive Data.
+#define MAC_MRXD_MDRX_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_NP register.
+//
+//*****************************************************************************
+#define MAC_NP_NPR_M 0x0000003F // Number of Packets in Receive
+ // FIFO.
+#define MAC_NP_NPR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_TR register.
+//
+//*****************************************************************************
+#define MAC_TR_NEWTX 0x00000001 // New Transmission.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCC register.
+//
+//*****************************************************************************
+#define HIB_RTCC_M 0xFFFFFFFF // RTC Counter.
+#define HIB_RTCC_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCM0 register.
+//
+//*****************************************************************************
+#define HIB_RTCM0_M 0xFFFFFFFF // RTC Match 0.
+#define HIB_RTCM0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCM1 register.
+//
+//*****************************************************************************
+#define HIB_RTCM1_M 0xFFFFFFFF // RTC Match 1.
+#define HIB_RTCM1_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCLD register.
+//
+//*****************************************************************************
+#define HIB_RTCLD_M 0xFFFFFFFF // RTC Load.
+#define HIB_RTCLD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_CTL register.
+//
+//*****************************************************************************
+#define HIB_CTL_VABORT 0x00000080 // Power Cut Abort Enable.
+#define HIB_CTL_CLK32EN 0x00000040 // Clocking Enable.
+#define HIB_CTL_LOWBATEN 0x00000020 // Low Battery Monitoring Enable.
+#define HIB_CTL_PINWEN 0x00000010 // External WAKE Pin Enable.
+#define HIB_CTL_RTCWEN 0x00000008 // RTC Wake-up Enable.
+#define HIB_CTL_CLKSEL 0x00000004 // Hibernation Module Clock Select.
+#define HIB_CTL_HIBREQ 0x00000002 // Hibernation Request.
+#define HIB_CTL_RTCEN 0x00000001 // RTC Timer Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_IM register.
+//
+//*****************************************************************************
+#define HIB_IM_EXTW 0x00000008 // External Wake-Up Interrupt Mask.
+#define HIB_IM_LOWBAT 0x00000004 // Low Battery Voltage Interrupt
+ // Mask.
+#define HIB_IM_RTCALT1 0x00000002 // RTC Alert1 Interrupt Mask.
+#define HIB_IM_RTCALT0 0x00000001 // RTC Alert0 Interrupt Mask.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RIS register.
+//
+//*****************************************************************************
+#define HIB_RIS_EXTW 0x00000008 // External Wake-Up Raw Interrupt
+ // Status.
+#define HIB_RIS_LOWBAT 0x00000004 // Low Battery Voltage Raw
+ // Interrupt Status.
+#define HIB_RIS_RTCALT1 0x00000002 // RTC Alert1 Raw Interrupt Status.
+#define HIB_RIS_RTCALT0 0x00000001 // RTC Alert0 Raw Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_MIS register.
+//
+//*****************************************************************************
+#define HIB_MIS_EXTW 0x00000008 // External Wake-Up Masked
+ // Interrupt Status.
+#define HIB_MIS_LOWBAT 0x00000004 // Low Battery Voltage Masked
+ // Interrupt Status.
+#define HIB_MIS_RTCALT1 0x00000002 // RTC Alert1 Masked Interrupt
+ // Status.
+#define HIB_MIS_RTCALT0 0x00000001 // RTC Alert0 Masked Interrupt
+ // Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_IC register.
+//
+//*****************************************************************************
+#define HIB_IC_EXTW 0x00000008 // External Wake-Up Masked
+ // Interrupt Clear.
+#define HIB_IC_LOWBAT 0x00000004 // Low Battery Voltage Masked
+ // Interrupt Clear.
+#define HIB_IC_RTCALT1 0x00000002 // RTC Alert1 Masked Interrupt
+ // Clear.
+#define HIB_IC_RTCALT0 0x00000001 // RTC Alert0 Masked Interrupt
+ // Clear.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCT register.
+//
+//*****************************************************************************
+#define HIB_RTCT_TRIM_M 0x0000FFFF // RTC Trim Value.
+#define HIB_RTCT_TRIM_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_DATA register.
+//
+//*****************************************************************************
+#define HIB_DATA_RTD_M 0xFFFFFFFF // Hibernation Module NV
+ // Registers[63:0].
+#define HIB_DATA_RTD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMA register.
+//
+//*****************************************************************************
+#define FLASH_FMA_OFFSET_M 0x0003FFFF // Address Offset.
+#define FLASH_FMA_OFFSET_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMD register.
+//
+//*****************************************************************************
+#define FLASH_FMD_DATA_M 0xFFFFFFFF // Data Value.
+#define FLASH_FMD_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMC register.
+//
+//*****************************************************************************
+#define FLASH_FMC_WRKEY_M 0xFFFF0000 // Flash Write Key.
+#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key
+#define FLASH_FMC_COMT 0x00000008 // Commit Register Value.
+#define FLASH_FMC_MERASE 0x00000004 // Mass Erase Flash Memory.
+#define FLASH_FMC_ERASE 0x00000002 // Erase a Page of Flash Memory.
+#define FLASH_FMC_WRITE 0x00000001 // Write a Word into Flash Memory.
+#define FLASH_FMC_WRKEY_S 16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FCRIS register.
+//
+//*****************************************************************************
+#define FLASH_FCRIS_PRIS 0x00000002 // Programming Raw Interrupt
+ // Status.
+#define FLASH_FCRIS_ARIS 0x00000001 // Access Raw Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FCIM register.
+//
+//*****************************************************************************
+#define FLASH_FCIM_PMASK 0x00000002 // Programming Interrupt Mask.
+#define FLASH_FCIM_AMASK 0x00000001 // Access Interrupt Mask.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FCMISC register.
+//
+//*****************************************************************************
+#define FLASH_FCMISC_PMISC 0x00000002 // Programming Masked Interrupt
+ // Status and Clear.
+#define FLASH_FCMISC_AMISC 0x00000001 // Access Masked Interrupt Status
+ // and Clear.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USECRL register.
+//
+//*****************************************************************************
+#define FLASH_USECRL_M 0x000000FF // Microsecond Reload Value.
+#define FLASH_USECRL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERDBG register.
+//
+//*****************************************************************************
+#define FLASH_USERDBG_NW 0x80000000 // User Debug Not Written.
+#define FLASH_USERDBG_DATA_M 0x7FFFFFFC // User Data.
+#define FLASH_USERDBG_DBG1 0x00000002 // Debug Control 1.
+#define FLASH_USERDBG_DBG0 0x00000001 // Debug Control 0.
+#define FLASH_USERDBG_DATA_S 2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG0 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG0_NW 0x80000000 // Not Written.
+#define FLASH_USERREG0_DATA_M 0x7FFFFFFF // User Data.
+#define FLASH_USERREG0_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG1 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG1_NW 0x80000000 // Not Written.
+#define FLASH_USERREG1_DATA_M 0x7FFFFFFF // User Data.
+#define FLASH_USERREG1_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the erase size of the FLASH block that is
+// erased by an erase operation, and the protect size is the size of the FLASH
+// block that is protected by each protection register.
+//
+//*****************************************************************************
+#define FLASH_PROTECT_SIZE 0x00000800
+#define FLASH_ERASE_SIZE 0x00000400
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DID0 register.
+//
+//*****************************************************************************
+#define SYSCTL_DID0_VER_M 0x70000000 // DID0 Version.
+#define SYSCTL_DID0_VER_1 0x10000000 // Second version of the DID0
+ // register format.
+#define SYSCTL_DID0_CLASS_M 0x00FF0000 // Device Class.
+#define SYSCTL_DID0_CLASS_FURY 0x00010000 // Stellaris(r) Fury-class devices.
+#define SYSCTL_DID0_MAJ_M 0x0000FF00 // Major Revision.
+#define SYSCTL_DID0_MAJ_REVA 0x00000000 // Revision A (initial device)
+#define SYSCTL_DID0_MAJ_REVB 0x00000100 // Revision B (first base layer
+ // revision)
+#define SYSCTL_DID0_MAJ_REVC 0x00000200 // Revision C (second base layer
+ // revision)
+#define SYSCTL_DID0_MIN_M 0x000000FF // Minor Revision.
+#define SYSCTL_DID0_MIN_0 0x00000000 // Initial device, or a major
+ // revision update.
+#define SYSCTL_DID0_MIN_1 0x00000001 // First metal layer change.
+#define SYSCTL_DID0_MIN_2 0x00000002 // Second metal layer change.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DID1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DID1_VER_M 0xF0000000 // DID1 Version.
+#define SYSCTL_DID1_VER_1 0x10000000 // Second version of the DID1
+ // register format.
+#define SYSCTL_DID1_FAM_M 0x0F000000 // Family.
+#define SYSCTL_DID1_FAM_STELLARIS \
+ 0x00000000 // Stellaris family of
+ // microcontollers, that is, all
+ // devices with external part
+ // numbers starting with LM3S.
+#define SYSCTL_DID1_PRTNO_M 0x00FF0000 // Part Number.
+#define SYSCTL_DID1_PRTNO_6918 0x00E80000 // LM3S6918
+#define SYSCTL_DID1_PINCNT_M 0x0000E000 // Package Pin Count.
+#define SYSCTL_DID1_PINCNT_100 0x00004000 // 100-pin or 108-ball package
+#define SYSCTL_DID1_TEMP_M 0x000000E0 // Temperature Range.
+#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temperature range (0C
+ // to 70C)
+#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temperature range
+ // (-40C to 85C)
+#define SYSCTL_DID1_TEMP_E 0x00000040 // Extended temperature range (-40C
+ // to 105C)
+#define SYSCTL_DID1_PKG_M 0x00000018 // Package Type.
+#define SYSCTL_DID1_PKG_28SOIC 0x00000000 // SOIC package
+#define SYSCTL_DID1_PKG_48QFP 0x00000008 // LQFP package
+#define SYSCTL_DID1_PKG_BGA 0x00000010 // BGA package
+#define SYSCTL_DID1_ROHS 0x00000004 // RoHS-Compliance.
+#define SYSCTL_DID1_QUAL_M 0x00000003 // Qualification Status.
+#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering Sample (unqualified)
+#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot Production (unqualified)
+#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully Qualified
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC0_SRAMSZ_M 0xFFFF0000 // SRAM Size.
+#define SYSCTL_DC0_SRAMSZ_64KB 0x00FF0000 // 64 KB of SRAM
+#define SYSCTL_DC0_FLASHSZ_M 0x0000FFFF // Flash Size.
+#define SYSCTL_DC0_FLASHSZ_256K 0x0000007F // 256 KB of Flash
+#define SYSCTL_DC0_SRAMSZ_S 16 // SRAM size shift
+#define SYSCTL_DC0_FLASHSZ_S 0 // Flash size shift
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC1_ADC 0x00010000 // ADC Module Present.
+#define SYSCTL_DC1_MINSYSDIV_M 0x0000F000 // System Clock Divider.
+#define SYSCTL_DC1_MINSYSDIV_50 0x00003000 // Specifies a 50-MHz CPU clock
+ // with a PLL divider of 4.
+#define SYSCTL_DC1_ADCSPD_M 0x00000300 // Max ADC Speed.
+#define SYSCTL_DC1_ADCSPD_500K 0x00000200 // 500K samples/second
+#define SYSCTL_DC1_MPU 0x00000080 // MPU Present.
+#define SYSCTL_DC1_HIB 0x00000040 // Hibernation Module Present.
+#define SYSCTL_DC1_TEMP 0x00000020 // Temp Sensor Present.
+#define SYSCTL_DC1_PLL 0x00000010 // PLL Present.
+#define SYSCTL_DC1_WDT 0x00000008 // Watchdog Timer Present.
+#define SYSCTL_DC1_SWO 0x00000004 // SWO Trace Port Present.
+#define SYSCTL_DC1_SWD 0x00000002 // SWD Present.
+#define SYSCTL_DC1_JTAG 0x00000001 // JTAG Present.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC2_COMP1 0x02000000 // Analog Comparator 1 Present.
+#define SYSCTL_DC2_COMP0 0x01000000 // Analog Comparator 0 Present.
+#define SYSCTL_DC2_TIMER3 0x00080000 // Timer 3 Present.
+#define SYSCTL_DC2_TIMER2 0x00040000 // Timer 2 Present.
+#define SYSCTL_DC2_TIMER1 0x00020000 // Timer 1 Present.
+#define SYSCTL_DC2_TIMER0 0x00010000 // Timer 0 Present.
+#define SYSCTL_DC2_I2C1 0x00004000 // I2C Module 1 Present.
+#define SYSCTL_DC2_I2C0 0x00001000 // I2C Module 0 Present.
+#define SYSCTL_DC2_SSI1 0x00000020 // SSI1 Present.
+#define SYSCTL_DC2_SSI0 0x00000010 // SSI0 Present.
+#define SYSCTL_DC2_UART1 0x00000002 // UART1 Present.
+#define SYSCTL_DC2_UART0 0x00000001 // UART0 Present.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC3 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC3_32KHZ 0x80000000 // 32KHz Input Clock Available.
+#define SYSCTL_DC3_CCP5 0x20000000 // CCP5 Pin Present.
+#define SYSCTL_DC3_CCP4 0x10000000 // CCP4 Pin Present.
+#define SYSCTL_DC3_CCP3 0x08000000 // CCP3 Pin Present.
+#define SYSCTL_DC3_CCP2 0x04000000 // CCP2 Pin Present.
+#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 Pin Present.
+#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 Pin Present.
+#define SYSCTL_DC3_ADC7 0x00800000 // ADC7 Pin Present.
+#define SYSCTL_DC3_ADC6 0x00400000 // ADC6 Pin Present.
+#define SYSCTL_DC3_ADC5 0x00200000 // ADC5 Pin Present.
+#define SYSCTL_DC3_ADC4 0x00100000 // ADC4 Pin Present.
+#define SYSCTL_DC3_ADC3 0x00080000 // ADC3 Pin Present.
+#define SYSCTL_DC3_ADC2 0x00040000 // ADC2 Pin Present.
+#define SYSCTL_DC3_ADC1 0x00020000 // ADC1 Pin Present.
+#define SYSCTL_DC3_ADC0 0x00010000 // ADC0 Pin Present.
+#define SYSCTL_DC3_C1PLUS 0x00000400 // C1+ Pin Present.
+#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- Pin Present.
+#define SYSCTL_DC3_C0O 0x00000100 // C0o Pin Present.
+#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ Pin Present.
+#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- Pin Present.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC4 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC4_EPHY0 0x40000000 // Ethernet PHY0 Present.
+#define SYSCTL_DC4_EMAC0 0x10000000 // Ethernet MAC0 Present.
+#define SYSCTL_DC4_GPIOH 0x00000080 // GPIO Port H Present.
+#define SYSCTL_DC4_GPIOG 0x00000040 // GPIO Port G Present.
+#define SYSCTL_DC4_GPIOF 0x00000020 // GPIO Port F Present.
+#define SYSCTL_DC4_GPIOE 0x00000010 // GPIO Port E Present.
+#define SYSCTL_DC4_GPIOD 0x00000008 // GPIO Port D Present.
+#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO Port C Present.
+#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO Port B Present.
+#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO Port A Present.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PBORCTL register.
+//
+//*****************************************************************************
+#define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR Interrupt or Reset.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_LDOPCTL register.
+//
+//*****************************************************************************
+#define SYSCTL_LDOPCTL_M 0x0000003F // LDO Output Voltage.
+#define SYSCTL_LDOPCTL_2_50V 0x00000000 // 2.50
+#define SYSCTL_LDOPCTL_2_45V 0x00000001 // 2.45
+#define SYSCTL_LDOPCTL_2_40V 0x00000002 // 2.40
+#define SYSCTL_LDOPCTL_2_35V 0x00000003 // 2.35
+#define SYSCTL_LDOPCTL_2_30V 0x00000004 // 2.30
+#define SYSCTL_LDOPCTL_2_25V 0x00000005 // 2.25
+#define SYSCTL_LDOPCTL_2_75V 0x0000001B // 2.75
+#define SYSCTL_LDOPCTL_2_70V 0x0000001C // 2.70
+#define SYSCTL_LDOPCTL_2_65V 0x0000001D // 2.65
+#define SYSCTL_LDOPCTL_2_60V 0x0000001E // 2.60
+#define SYSCTL_LDOPCTL_2_55V 0x0000001F // 2.55
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCR0 register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCR0_ADC 0x00010000 // ADC0 Reset Control.
+#define SYSCTL_SRCR0_HIB 0x00000040 // HIB Reset Control.
+#define SYSCTL_SRCR0_WDT 0x00000008 // WDT Reset Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCR1 register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCR1_COMP1 0x02000000 // Analog Comp 1 Reset Control.
+#define SYSCTL_SRCR1_COMP0 0x01000000 // Analog Comp 0 Reset Control.
+#define SYSCTL_SRCR1_TIMER3 0x00080000 // Timer 3 Reset Control.
+#define SYSCTL_SRCR1_TIMER2 0x00040000 // Timer 2 Reset Control.
+#define SYSCTL_SRCR1_TIMER1 0x00020000 // Timer 1 Reset Control.
+#define SYSCTL_SRCR1_TIMER0 0x00010000 // Timer 0 Reset Control.
+#define SYSCTL_SRCR1_I2C1 0x00004000 // I2C1 Reset Control.
+#define SYSCTL_SRCR1_I2C0 0x00001000 // I2C0 Reset Control.
+#define SYSCTL_SRCR1_SSI1 0x00000020 // SSI1 Reset Control.
+#define SYSCTL_SRCR1_SSI0 0x00000010 // SSI0 Reset Control.
+#define SYSCTL_SRCR1_UART1 0x00000002 // UART1 Reset Control.
+#define SYSCTL_SRCR1_UART0 0x00000001 // UART0 Reset Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCR2 register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCR2_EPHY0 0x40000000 // PHY0 Reset Control.
+#define SYSCTL_SRCR2_EMAC0 0x10000000 // MAC0 Reset Control.
+#define SYSCTL_SRCR2_GPIOH 0x00000080 // Port H Reset Control.
+#define SYSCTL_SRCR2_GPIOG 0x00000040 // Port G Reset Control.
+#define SYSCTL_SRCR2_GPIOF 0x00000020 // Port F Reset Control.
+#define SYSCTL_SRCR2_GPIOE 0x00000010 // Port E Reset Control.
+#define SYSCTL_SRCR2_GPIOD 0x00000008 // Port D Reset Control.
+#define SYSCTL_SRCR2_GPIOC 0x00000004 // Port C Reset Control.
+#define SYSCTL_SRCR2_GPIOB 0x00000002 // Port B Reset Control.
+#define SYSCTL_SRCR2_GPIOA 0x00000001 // Port A Reset Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RIS register.
+//
+//*****************************************************************************
+#define SYSCTL_RIS_PLLLRIS 0x00000040 // PLL Lock Raw Interrupt Status.
+#define SYSCTL_RIS_BORRIS 0x00000002 // Brown-Out Reset Raw Interrupt
+ // Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_IMC register.
+//
+//*****************************************************************************
+#define SYSCTL_IMC_PLLLIM 0x00000040 // PLL Lock Interrupt Mask.
+#define SYSCTL_IMC_BORIM 0x00000002 // Brown-Out Reset Interrupt Mask.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_MISC register.
+//
+//*****************************************************************************
+#define SYSCTL_MISC_PLLLMIS 0x00000040 // PLL Lock Masked Interrupt
+ // Status.
+#define SYSCTL_MISC_BORMIS 0x00000002 // BOR Masked Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RESC register.
+//
+//*****************************************************************************
+#define SYSCTL_RESC_LDO 0x00000020 // LDO Reset.
+#define SYSCTL_RESC_SW 0x00000010 // Software Reset.
+#define SYSCTL_RESC_WDT 0x00000008 // Watchdog Timer Reset.
+#define SYSCTL_RESC_BOR 0x00000004 // Brown-Out Reset.
+#define SYSCTL_RESC_POR 0x00000002 // Power-On Reset.
+#define SYSCTL_RESC_EXT 0x00000001 // External Reset.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCC register.
+//
+//*****************************************************************************
+#define SYSCTL_RCC_ACG 0x08000000 // Auto Clock Gating.
+#define SYSCTL_RCC_SYSDIV_M 0x07800000 // System Clock Divisor.
+#define SYSCTL_RCC_SYSDIV_2 0x00800000 // /2
+#define SYSCTL_RCC_SYSDIV_3 0x01000000 // /3
+#define SYSCTL_RCC_SYSDIV_4 0x01800000 // /4
+#define SYSCTL_RCC_SYSDIV_5 0x02000000 // /5
+#define SYSCTL_RCC_SYSDIV_6 0x02800000 // /6
+#define SYSCTL_RCC_SYSDIV_7 0x03000000 // /7
+#define SYSCTL_RCC_SYSDIV_8 0x03800000 // /8
+#define SYSCTL_RCC_SYSDIV_9 0x04000000 // /9
+#define SYSCTL_RCC_SYSDIV_10 0x04800000 // /10
+#define SYSCTL_RCC_SYSDIV_11 0x05000000 // /11
+#define SYSCTL_RCC_SYSDIV_12 0x05800000 // /12
+#define SYSCTL_RCC_SYSDIV_13 0x06000000 // /13
+#define SYSCTL_RCC_SYSDIV_14 0x06800000 // /14
+#define SYSCTL_RCC_SYSDIV_15 0x07000000 // /15
+#define SYSCTL_RCC_SYSDIV_16 0x07800000 // /16
+#define SYSCTL_RCC_USESYSDIV 0x00400000 // Enable System Clock Divider.
+#define SYSCTL_RCC_PWRDN 0x00002000 // PLL Power Down.
+#define SYSCTL_RCC_BYPASS 0x00000800 // PLL Bypass.
+#define SYSCTL_RCC_XTAL_M 0x000003C0 // Crystal Value.
+#define SYSCTL_RCC_XTAL_1MHZ 0x00000000 // 1.000
+#define SYSCTL_RCC_XTAL_1_84MHZ 0x00000040 // 1.8432
+#define SYSCTL_RCC_XTAL_2MHZ 0x00000080 // 2.000
+#define SYSCTL_RCC_XTAL_2_45MHZ 0x000000C0 // 2.4576
+#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100 // 3.579545 MHz
+#define SYSCTL_RCC_XTAL_3_68MHZ 0x00000140 // 3.6864 MHz
+#define SYSCTL_RCC_XTAL_4MHZ 0x00000180 // 4 MHz
+#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // 4.096 MHz
+#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // 4.9152 MHz
+#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // 5 MHz
+#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // 5.12 MHz
+#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // 6 MHz (reset value)
+#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // 6.144 MHz
+#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // 7.3728 MHz
+#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // 8 MHz
+#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // 8.192 MHz
+#define SYSCTL_RCC_OSCSRC_M 0x00000030 // Oscillator Source.
+#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // MOSC
+#define SYSCTL_RCC_OSCSRC_INT 0x00000010 // IOSC
+#define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // IOSC/4
+#define SYSCTL_RCC_OSCSRC_30 0x00000030 // 30 kHz
+#define SYSCTL_RCC_IOSCDIS 0x00000002 // Internal Oscillator Disable.
+#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main Oscillator Disable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PLLCFG register.
+//
+//*****************************************************************************
+#define SYSCTL_PLLCFG_F_M 0x00003FE0 // PLL F Value.
+#define SYSCTL_PLLCFG_R_M 0x0000001F // PLL R Value.
+#define SYSCTL_PLLCFG_F_S 5
+#define SYSCTL_PLLCFG_R_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCC2_USERCC2 0x80000000 // Use RCC2.
+#define SYSCTL_RCC2_SYSDIV2_M 0x1F800000 // System Clock Divisor.
+#define SYSCTL_RCC2_SYSDIV2_2 0x00800000 // System clock /2
+#define SYSCTL_RCC2_SYSDIV2_3 0x01000000 // System clock /3
+#define SYSCTL_RCC2_SYSDIV2_4 0x01800000 // System clock /4
+#define SYSCTL_RCC2_SYSDIV2_5 0x02000000 // System clock /5
+#define SYSCTL_RCC2_SYSDIV2_6 0x02800000 // System clock /6
+#define SYSCTL_RCC2_SYSDIV2_7 0x03000000 // System clock /7
+#define SYSCTL_RCC2_SYSDIV2_8 0x03800000 // System clock /8
+#define SYSCTL_RCC2_SYSDIV2_9 0x04000000 // System clock /9
+#define SYSCTL_RCC2_SYSDIV2_10 0x04800000 // System clock /10
+#define SYSCTL_RCC2_SYSDIV2_11 0x05000000 // System clock /11
+#define SYSCTL_RCC2_SYSDIV2_12 0x05800000 // System clock /12
+#define SYSCTL_RCC2_SYSDIV2_13 0x06000000 // System clock /13
+#define SYSCTL_RCC2_SYSDIV2_14 0x06800000 // System clock /14
+#define SYSCTL_RCC2_SYSDIV2_15 0x07000000 // System clock /15
+#define SYSCTL_RCC2_SYSDIV2_16 0x07800000 // System clock /16
+#define SYSCTL_RCC2_SYSDIV2_17 0x08000000 // System clock /17
+#define SYSCTL_RCC2_SYSDIV2_18 0x08800000 // System clock /18
+#define SYSCTL_RCC2_SYSDIV2_19 0x09000000 // System clock /19
+#define SYSCTL_RCC2_SYSDIV2_20 0x09800000 // System clock /20
+#define SYSCTL_RCC2_SYSDIV2_21 0x0A000000 // System clock /21
+#define SYSCTL_RCC2_SYSDIV2_22 0x0A800000 // System clock /22
+#define SYSCTL_RCC2_SYSDIV2_23 0x0B000000 // System clock /23
+#define SYSCTL_RCC2_SYSDIV2_24 0x0B800000 // System clock /24
+#define SYSCTL_RCC2_SYSDIV2_25 0x0C000000 // System clock /25
+#define SYSCTL_RCC2_SYSDIV2_26 0x0C800000 // System clock /26
+#define SYSCTL_RCC2_SYSDIV2_27 0x0D000000 // System clock /27
+#define SYSCTL_RCC2_SYSDIV2_28 0x0D800000 // System clock /28
+#define SYSCTL_RCC2_SYSDIV2_29 0x0E000000 // System clock /29
+#define SYSCTL_RCC2_SYSDIV2_30 0x0E800000 // System clock /30
+#define SYSCTL_RCC2_SYSDIV2_31 0x0F000000 // System clock /31
+#define SYSCTL_RCC2_SYSDIV2_32 0x0F800000 // System clock /32
+#define SYSCTL_RCC2_SYSDIV2_33 0x10000000 // System clock /33
+#define SYSCTL_RCC2_SYSDIV2_34 0x10800000 // System clock /34
+#define SYSCTL_RCC2_SYSDIV2_35 0x11000000 // System clock /35
+#define SYSCTL_RCC2_SYSDIV2_36 0x11800000 // System clock /36
+#define SYSCTL_RCC2_SYSDIV2_37 0x12000000 // System clock /37
+#define SYSCTL_RCC2_SYSDIV2_38 0x12800000 // System clock /38
+#define SYSCTL_RCC2_SYSDIV2_39 0x13000000 // System clock /39
+#define SYSCTL_RCC2_SYSDIV2_40 0x13800000 // System clock /40
+#define SYSCTL_RCC2_SYSDIV2_41 0x14000000 // System clock /41
+#define SYSCTL_RCC2_SYSDIV2_42 0x14800000 // System clock /42
+#define SYSCTL_RCC2_SYSDIV2_43 0x15000000 // System clock /43
+#define SYSCTL_RCC2_SYSDIV2_44 0x15800000 // System clock /44
+#define SYSCTL_RCC2_SYSDIV2_45 0x16000000 // System clock /45
+#define SYSCTL_RCC2_SYSDIV2_46 0x16800000 // System clock /46
+#define SYSCTL_RCC2_SYSDIV2_47 0x17000000 // System clock /47
+#define SYSCTL_RCC2_SYSDIV2_48 0x17800000 // System clock /48
+#define SYSCTL_RCC2_SYSDIV2_49 0x18000000 // System clock /49
+#define SYSCTL_RCC2_SYSDIV2_50 0x18800000 // System clock /50
+#define SYSCTL_RCC2_SYSDIV2_51 0x19000000 // System clock /51
+#define SYSCTL_RCC2_SYSDIV2_52 0x19800000 // System clock /52
+#define SYSCTL_RCC2_SYSDIV2_53 0x1A000000 // System clock /53
+#define SYSCTL_RCC2_SYSDIV2_54 0x1A800000 // System clock /54
+#define SYSCTL_RCC2_SYSDIV2_55 0x1B000000 // System clock /55
+#define SYSCTL_RCC2_SYSDIV2_56 0x1B800000 // System clock /56
+#define SYSCTL_RCC2_SYSDIV2_57 0x1C000000 // System clock /57
+#define SYSCTL_RCC2_SYSDIV2_58 0x1C800000 // System clock /58
+#define SYSCTL_RCC2_SYSDIV2_59 0x1D000000 // System clock /59
+#define SYSCTL_RCC2_SYSDIV2_60 0x1D800000 // System clock /60
+#define SYSCTL_RCC2_SYSDIV2_61 0x1E000000 // System clock /61
+#define SYSCTL_RCC2_SYSDIV2_62 0x1E800000 // System clock /62
+#define SYSCTL_RCC2_SYSDIV2_63 0x1F000000 // System clock /63
+#define SYSCTL_RCC2_SYSDIV2_64 0x1F800000 // System clock /64
+#define SYSCTL_RCC2_PWRDN2 0x00002000 // Power-Down PLL.
+#define SYSCTL_RCC2_BYPASS2 0x00000800 // Bypass PLL.
+#define SYSCTL_RCC2_OSCSRC2_M 0x00000070 // Oscillator Source.
+#define SYSCTL_RCC2_OSCSRC2_MO 0x00000000 // MOSC
+#define SYSCTL_RCC2_OSCSRC2_IO 0x00000010 // IOSC
+#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020 // IOSC/4
+#define SYSCTL_RCC2_OSCSRC2_30 0x00000030 // 30 kHz
+#define SYSCTL_RCC2_OSCSRC2_32 0x00000070 // 32 kHz
+#define SYSCTL_RCC2_SYSDIV2_S 23
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGC0_ADC 0x00010000 // ADC0 Clock Gating Control.
+#define SYSCTL_RCGC0_ADCSPD_M 0x00000300 // ADC Sample Speed.
+#define SYSCTL_RCGC0_ADCSPD125K 0x00000000 // 125K samples/second
+#define SYSCTL_RCGC0_ADCSPD250K 0x00000100 // 250K samples/second
+#define SYSCTL_RCGC0_ADCSPD500K 0x00000200 // 500K samples/second
+#define SYSCTL_RCGC0_HIB 0x00000040 // HIB Clock Gating Control.
+#define SYSCTL_RCGC0_WDT 0x00000008 // WDT Clock Gating Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock
+ // Gating.
+#define SYSCTL_RCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock
+ // Gating.
+#define SYSCTL_RCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control.
+#define SYSCTL_RCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control.
+#define SYSCTL_RCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control.
+#define SYSCTL_RCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control.
+#define SYSCTL_RCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control.
+#define SYSCTL_RCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control.
+#define SYSCTL_RCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control.
+#define SYSCTL_RCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control.
+#define SYSCTL_RCGC1_UART1 0x00000002 // UART1 Clock Gating Control.
+#define SYSCTL_RCGC1_UART0 0x00000001 // UART0 Clock Gating Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGC2_EPHY0 0x40000000 // PHY0 Clock Gating Control.
+#define SYSCTL_RCGC2_EMAC0 0x10000000 // MAC0 Clock Gating Control.
+#define SYSCTL_RCGC2_GPIOH 0x00000080 // Port H Clock Gating Control.
+#define SYSCTL_RCGC2_GPIOG 0x00000040 // Port G Clock Gating Control.
+#define SYSCTL_RCGC2_GPIOF 0x00000020 // Port F Clock Gating Control.
+#define SYSCTL_RCGC2_GPIOE 0x00000010 // Port E Clock Gating Control.
+#define SYSCTL_RCGC2_GPIOD 0x00000008 // Port D Clock Gating Control.
+#define SYSCTL_RCGC2_GPIOC 0x00000004 // Port C Clock Gating Control.
+#define SYSCTL_RCGC2_GPIOB 0x00000002 // Port B Clock Gating Control.
+#define SYSCTL_RCGC2_GPIOA 0x00000001 // Port A Clock Gating Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGC0_ADC 0x00010000 // ADC0 Clock Gating Control.
+#define SYSCTL_SCGC0_ADCSPD_M 0x00000300 // ADC Sample Speed.
+#define SYSCTL_SCGC0_ADCSPD125K 0x00000000 // 125K samples/second
+#define SYSCTL_SCGC0_ADCSPD250K 0x00000100 // 250K samples/second
+#define SYSCTL_SCGC0_ADCSPD500K 0x00000200 // 500K samples/second
+#define SYSCTL_SCGC0_HIB 0x00000040 // HIB Clock Gating Control.
+#define SYSCTL_SCGC0_WDT 0x00000008 // WDT Clock Gating Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock
+ // Gating.
+#define SYSCTL_SCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock
+ // Gating.
+#define SYSCTL_SCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control.
+#define SYSCTL_SCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control.
+#define SYSCTL_SCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control.
+#define SYSCTL_SCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control.
+#define SYSCTL_SCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control.
+#define SYSCTL_SCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control.
+#define SYSCTL_SCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control.
+#define SYSCTL_SCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control.
+#define SYSCTL_SCGC1_UART1 0x00000002 // UART1 Clock Gating Control.
+#define SYSCTL_SCGC1_UART0 0x00000001 // UART0 Clock Gating Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGC2_EPHY0 0x40000000 // PHY0 Clock Gating Control.
+#define SYSCTL_SCGC2_EMAC0 0x10000000 // MAC0 Clock Gating Control.
+#define SYSCTL_SCGC2_GPIOH 0x00000080 // Port H Clock Gating Control.
+#define SYSCTL_SCGC2_GPIOG 0x00000040 // Port G Clock Gating Control.
+#define SYSCTL_SCGC2_GPIOF 0x00000020 // Port F Clock Gating Control.
+#define SYSCTL_SCGC2_GPIOE 0x00000010 // Port E Clock Gating Control.
+#define SYSCTL_SCGC2_GPIOD 0x00000008 // Port D Clock Gating Control.
+#define SYSCTL_SCGC2_GPIOC 0x00000004 // Port C Clock Gating Control.
+#define SYSCTL_SCGC2_GPIOB 0x00000002 // Port B Clock Gating Control.
+#define SYSCTL_SCGC2_GPIOA 0x00000001 // Port A Clock Gating Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGC0_ADC 0x00010000 // ADC0 Clock Gating Control.
+#define SYSCTL_DCGC0_ADCSPD_M 0x00000300 // ADC Sample Speed.
+#define SYSCTL_DCGC0_ADCSPD125K 0x00000000 // 125K samples/second
+#define SYSCTL_DCGC0_ADCSPD250K 0x00000100 // 250K samples/second
+#define SYSCTL_DCGC0_ADCSPD500K 0x00000200 // 500K samples/second
+#define SYSCTL_DCGC0_HIB 0x00000040 // HIB Clock Gating Control.
+#define SYSCTL_DCGC0_WDT 0x00000008 // WDT Clock Gating Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock
+ // Gating.
+#define SYSCTL_DCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock
+ // Gating.
+#define SYSCTL_DCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control.
+#define SYSCTL_DCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control.
+#define SYSCTL_DCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control.
+#define SYSCTL_DCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control.
+#define SYSCTL_DCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control.
+#define SYSCTL_DCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control.
+#define SYSCTL_DCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control.
+#define SYSCTL_DCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control.
+#define SYSCTL_DCGC1_UART1 0x00000002 // UART1 Clock Gating Control.
+#define SYSCTL_DCGC1_UART0 0x00000001 // UART0 Clock Gating Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGC2_EPHY0 0x40000000 // PHY0 Clock Gating Control.
+#define SYSCTL_DCGC2_EMAC0 0x10000000 // MAC0 Clock Gating Control.
+#define SYSCTL_DCGC2_GPIOH 0x00000080 // Port H Clock Gating Control.
+#define SYSCTL_DCGC2_GPIOG 0x00000040 // Port G Clock Gating Control.
+#define SYSCTL_DCGC2_GPIOF 0x00000020 // Port F Clock Gating Control.
+#define SYSCTL_DCGC2_GPIOE 0x00000010 // Port E Clock Gating Control.
+#define SYSCTL_DCGC2_GPIOD 0x00000008 // Port D Clock Gating Control.
+#define SYSCTL_DCGC2_GPIOC 0x00000004 // Port C Clock Gating Control.
+#define SYSCTL_DCGC2_GPIOB 0x00000002 // Port B Clock Gating Control.
+#define SYSCTL_DCGC2_GPIOA 0x00000001 // Port A Clock Gating Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DSLPCLKCFG
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DSLPCLKCFG_D_M 0x1F800000 // Divider Field Override.
+#define SYSCTL_DSLPCLKCFG_O_M 0x00000070 // Clock Source.
+#define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000 // MOSC
+#define SYSCTL_DSLPCLKCFG_O_IO 0x00000010 // IOSC
+#define SYSCTL_DSLPCLKCFG_O_30 0x00000030 // 30 kHz
+#define SYSCTL_DSLPCLKCFG_O_32 0x00000070 // 32 kHz
+#define SYSCTL_DSLPCLKCFG_D_S 23
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_INT_TYPE register.
+//
+//*****************************************************************************
+#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32)
+#define NVIC_INT_TYPE_LINES_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_ST_CTRL_COUNT 0x00010000 // Count flag
+#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source
+#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt enable
+#define NVIC_ST_CTRL_ENABLE 0x00000001 // Counter mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_RELOAD register.
+//
+//*****************************************************************************
+#define NVIC_ST_RELOAD_M 0x00FFFFFF // Counter load value
+#define NVIC_ST_RELOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_CURRENT
+// register.
+//
+//*****************************************************************************
+#define NVIC_ST_CURRENT_M 0x00FFFFFF // Counter current value
+#define NVIC_ST_CURRENT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_CAL register.
+//
+//*****************************************************************************
+#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock
+#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew
+#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value
+#define NVIC_ST_CAL_ONEMS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN0 register.
+//
+//*****************************************************************************
+#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable
+#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable
+#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable
+#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable
+#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable
+#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable
+#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable
+#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable
+#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable
+#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable
+#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable
+#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable
+#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable
+#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable
+#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable
+#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable
+#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable
+#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable
+#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable
+#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable
+#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable
+#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable
+#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable
+#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable
+#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable
+#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable
+#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable
+#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable
+#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable
+#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable
+#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable
+#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN1 register.
+//
+//*****************************************************************************
+#define NVIC_EN1_INT59 0x08000000 // Interrupt 59 enable
+#define NVIC_EN1_INT58 0x04000000 // Interrupt 58 enable
+#define NVIC_EN1_INT57 0x02000000 // Interrupt 57 enable
+#define NVIC_EN1_INT56 0x01000000 // Interrupt 56 enable
+#define NVIC_EN1_INT55 0x00800000 // Interrupt 55 enable
+#define NVIC_EN1_INT54 0x00400000 // Interrupt 54 enable
+#define NVIC_EN1_INT53 0x00200000 // Interrupt 53 enable
+#define NVIC_EN1_INT52 0x00100000 // Interrupt 52 enable
+#define NVIC_EN1_INT51 0x00080000 // Interrupt 51 enable
+#define NVIC_EN1_INT50 0x00040000 // Interrupt 50 enable
+#define NVIC_EN1_INT49 0x00020000 // Interrupt 49 enable
+#define NVIC_EN1_INT48 0x00010000 // Interrupt 48 enable
+#define NVIC_EN1_INT47 0x00008000 // Interrupt 47 enable
+#define NVIC_EN1_INT46 0x00004000 // Interrupt 46 enable
+#define NVIC_EN1_INT45 0x00002000 // Interrupt 45 enable
+#define NVIC_EN1_INT44 0x00001000 // Interrupt 44 enable
+#define NVIC_EN1_INT43 0x00000800 // Interrupt 43 enable
+#define NVIC_EN1_INT42 0x00000400 // Interrupt 42 enable
+#define NVIC_EN1_INT41 0x00000200 // Interrupt 41 enable
+#define NVIC_EN1_INT40 0x00000100 // Interrupt 40 enable
+#define NVIC_EN1_INT39 0x00000080 // Interrupt 39 enable
+#define NVIC_EN1_INT38 0x00000040 // Interrupt 38 enable
+#define NVIC_EN1_INT37 0x00000020 // Interrupt 37 enable
+#define NVIC_EN1_INT36 0x00000010 // Interrupt 36 enable
+#define NVIC_EN1_INT35 0x00000008 // Interrupt 35 enable
+#define NVIC_EN1_INT34 0x00000004 // Interrupt 34 enable
+#define NVIC_EN1_INT33 0x00000002 // Interrupt 33 enable
+#define NVIC_EN1_INT32 0x00000001 // Interrupt 32 enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS0 register.
+//
+//*****************************************************************************
+#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable
+#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable
+#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable
+#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable
+#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable
+#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable
+#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable
+#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable
+#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable
+#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable
+#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable
+#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable
+#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable
+#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable
+#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable
+#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable
+#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable
+#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable
+#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable
+#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable
+#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable
+#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable
+#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable
+#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable
+#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable
+#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable
+#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable
+#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable
+#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable
+#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable
+#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable
+#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS1 register.
+//
+//*****************************************************************************
+#define NVIC_DIS1_INT59 0x08000000 // Interrupt 59 disable
+#define NVIC_DIS1_INT58 0x04000000 // Interrupt 58 disable
+#define NVIC_DIS1_INT57 0x02000000 // Interrupt 57 disable
+#define NVIC_DIS1_INT56 0x01000000 // Interrupt 56 disable
+#define NVIC_DIS1_INT55 0x00800000 // Interrupt 55 disable
+#define NVIC_DIS1_INT54 0x00400000 // Interrupt 54 disable
+#define NVIC_DIS1_INT53 0x00200000 // Interrupt 53 disable
+#define NVIC_DIS1_INT52 0x00100000 // Interrupt 52 disable
+#define NVIC_DIS1_INT51 0x00080000 // Interrupt 51 disable
+#define NVIC_DIS1_INT50 0x00040000 // Interrupt 50 disable
+#define NVIC_DIS1_INT49 0x00020000 // Interrupt 49 disable
+#define NVIC_DIS1_INT48 0x00010000 // Interrupt 48 disable
+#define NVIC_DIS1_INT47 0x00008000 // Interrupt 47 disable
+#define NVIC_DIS1_INT46 0x00004000 // Interrupt 46 disable
+#define NVIC_DIS1_INT45 0x00002000 // Interrupt 45 disable
+#define NVIC_DIS1_INT44 0x00001000 // Interrupt 44 disable
+#define NVIC_DIS1_INT43 0x00000800 // Interrupt 43 disable
+#define NVIC_DIS1_INT42 0x00000400 // Interrupt 42 disable
+#define NVIC_DIS1_INT41 0x00000200 // Interrupt 41 disable
+#define NVIC_DIS1_INT40 0x00000100 // Interrupt 40 disable
+#define NVIC_DIS1_INT39 0x00000080 // Interrupt 39 disable
+#define NVIC_DIS1_INT38 0x00000040 // Interrupt 38 disable
+#define NVIC_DIS1_INT37 0x00000020 // Interrupt 37 disable
+#define NVIC_DIS1_INT36 0x00000010 // Interrupt 36 disable
+#define NVIC_DIS1_INT35 0x00000008 // Interrupt 35 disable
+#define NVIC_DIS1_INT34 0x00000004 // Interrupt 34 disable
+#define NVIC_DIS1_INT33 0x00000002 // Interrupt 33 disable
+#define NVIC_DIS1_INT32 0x00000001 // Interrupt 32 disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND0 register.
+//
+//*****************************************************************************
+#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend
+#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend
+#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend
+#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend
+#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend
+#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend
+#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend
+#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend
+#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend
+#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend
+#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend
+#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend
+#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend
+#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend
+#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend
+#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend
+#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend
+#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend
+#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend
+#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend
+#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend
+#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend
+#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend
+#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend
+#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend
+#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend
+#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend
+#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend
+#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend
+#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend
+#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend
+#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND1 register.
+//
+//*****************************************************************************
+#define NVIC_PEND1_INT59 0x08000000 // Interrupt 59 pend
+#define NVIC_PEND1_INT58 0x04000000 // Interrupt 58 pend
+#define NVIC_PEND1_INT57 0x02000000 // Interrupt 57 pend
+#define NVIC_PEND1_INT56 0x01000000 // Interrupt 56 pend
+#define NVIC_PEND1_INT55 0x00800000 // Interrupt 55 pend
+#define NVIC_PEND1_INT54 0x00400000 // Interrupt 54 pend
+#define NVIC_PEND1_INT53 0x00200000 // Interrupt 53 pend
+#define NVIC_PEND1_INT52 0x00100000 // Interrupt 52 pend
+#define NVIC_PEND1_INT51 0x00080000 // Interrupt 51 pend
+#define NVIC_PEND1_INT50 0x00040000 // Interrupt 50 pend
+#define NVIC_PEND1_INT49 0x00020000 // Interrupt 49 pend
+#define NVIC_PEND1_INT48 0x00010000 // Interrupt 48 pend
+#define NVIC_PEND1_INT47 0x00008000 // Interrupt 47 pend
+#define NVIC_PEND1_INT46 0x00004000 // Interrupt 46 pend
+#define NVIC_PEND1_INT45 0x00002000 // Interrupt 45 pend
+#define NVIC_PEND1_INT44 0x00001000 // Interrupt 44 pend
+#define NVIC_PEND1_INT43 0x00000800 // Interrupt 43 pend
+#define NVIC_PEND1_INT42 0x00000400 // Interrupt 42 pend
+#define NVIC_PEND1_INT41 0x00000200 // Interrupt 41 pend
+#define NVIC_PEND1_INT40 0x00000100 // Interrupt 40 pend
+#define NVIC_PEND1_INT39 0x00000080 // Interrupt 39 pend
+#define NVIC_PEND1_INT38 0x00000040 // Interrupt 38 pend
+#define NVIC_PEND1_INT37 0x00000020 // Interrupt 37 pend
+#define NVIC_PEND1_INT36 0x00000010 // Interrupt 36 pend
+#define NVIC_PEND1_INT35 0x00000008 // Interrupt 35 pend
+#define NVIC_PEND1_INT34 0x00000004 // Interrupt 34 pend
+#define NVIC_PEND1_INT33 0x00000002 // Interrupt 33 pend
+#define NVIC_PEND1_INT32 0x00000001 // Interrupt 32 pend
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND0 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend
+#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend
+#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend
+#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend
+#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend
+#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend
+#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend
+#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend
+#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend
+#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend
+#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend
+#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend
+#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend
+#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend
+#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend
+#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend
+#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend
+#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend
+#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend
+#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend
+#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend
+#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend
+#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend
+#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend
+#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend
+#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend
+#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend
+#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend
+#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend
+#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend
+#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend
+#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND1 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND1_INT59 0x08000000 // Interrupt 59 unpend
+#define NVIC_UNPEND1_INT58 0x04000000 // Interrupt 58 unpend
+#define NVIC_UNPEND1_INT57 0x02000000 // Interrupt 57 unpend
+#define NVIC_UNPEND1_INT56 0x01000000 // Interrupt 56 unpend
+#define NVIC_UNPEND1_INT55 0x00800000 // Interrupt 55 unpend
+#define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend
+#define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend
+#define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend
+#define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend
+#define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend
+#define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend
+#define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend
+#define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend
+#define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend
+#define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend
+#define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend
+#define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend
+#define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend
+#define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend
+#define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend
+#define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend
+#define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend
+#define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend
+#define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend
+#define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend
+#define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend
+#define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend
+#define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE0 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active
+#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active
+#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active
+#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active
+#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active
+#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active
+#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active
+#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active
+#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active
+#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active
+#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active
+#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active
+#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active
+#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active
+#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active
+#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active
+#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active
+#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active
+#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active
+#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active
+#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active
+#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active
+#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active
+#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active
+#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active
+#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active
+#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active
+#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active
+#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active
+#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active
+#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active
+#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE1 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE1_INT59 0x08000000 // Interrupt 59 active
+#define NVIC_ACTIVE1_INT58 0x04000000 // Interrupt 58 active
+#define NVIC_ACTIVE1_INT57 0x02000000 // Interrupt 57 active
+#define NVIC_ACTIVE1_INT56 0x01000000 // Interrupt 56 active
+#define NVIC_ACTIVE1_INT55 0x00800000 // Interrupt 55 active
+#define NVIC_ACTIVE1_INT54 0x00400000 // Interrupt 54 active
+#define NVIC_ACTIVE1_INT53 0x00200000 // Interrupt 53 active
+#define NVIC_ACTIVE1_INT52 0x00100000 // Interrupt 52 active
+#define NVIC_ACTIVE1_INT51 0x00080000 // Interrupt 51 active
+#define NVIC_ACTIVE1_INT50 0x00040000 // Interrupt 50 active
+#define NVIC_ACTIVE1_INT49 0x00020000 // Interrupt 49 active
+#define NVIC_ACTIVE1_INT48 0x00010000 // Interrupt 48 active
+#define NVIC_ACTIVE1_INT47 0x00008000 // Interrupt 47 active
+#define NVIC_ACTIVE1_INT46 0x00004000 // Interrupt 46 active
+#define NVIC_ACTIVE1_INT45 0x00002000 // Interrupt 45 active
+#define NVIC_ACTIVE1_INT44 0x00001000 // Interrupt 44 active
+#define NVIC_ACTIVE1_INT43 0x00000800 // Interrupt 43 active
+#define NVIC_ACTIVE1_INT42 0x00000400 // Interrupt 42 active
+#define NVIC_ACTIVE1_INT41 0x00000200 // Interrupt 41 active
+#define NVIC_ACTIVE1_INT40 0x00000100 // Interrupt 40 active
+#define NVIC_ACTIVE1_INT39 0x00000080 // Interrupt 39 active
+#define NVIC_ACTIVE1_INT38 0x00000040 // Interrupt 38 active
+#define NVIC_ACTIVE1_INT37 0x00000020 // Interrupt 37 active
+#define NVIC_ACTIVE1_INT36 0x00000010 // Interrupt 36 active
+#define NVIC_ACTIVE1_INT35 0x00000008 // Interrupt 35 active
+#define NVIC_ACTIVE1_INT34 0x00000004 // Interrupt 34 active
+#define NVIC_ACTIVE1_INT33 0x00000002 // Interrupt 33 active
+#define NVIC_ACTIVE1_INT32 0x00000001 // Interrupt 32 active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI0 register.
+//
+//*****************************************************************************
+#define NVIC_PRI0_INT3_M 0xFF000000 // Interrupt 3 priority mask
+#define NVIC_PRI0_INT2_M 0x00FF0000 // Interrupt 2 priority mask
+#define NVIC_PRI0_INT1_M 0x0000FF00 // Interrupt 1 priority mask
+#define NVIC_PRI0_INT0_M 0x000000FF // Interrupt 0 priority mask
+#define NVIC_PRI0_INT3_S 24
+#define NVIC_PRI0_INT2_S 16
+#define NVIC_PRI0_INT1_S 8
+#define NVIC_PRI0_INT0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI1 register.
+//
+//*****************************************************************************
+#define NVIC_PRI1_INT7_M 0xFF000000 // Interrupt 7 priority mask
+#define NVIC_PRI1_INT6_M 0x00FF0000 // Interrupt 6 priority mask
+#define NVIC_PRI1_INT5_M 0x0000FF00 // Interrupt 5 priority mask
+#define NVIC_PRI1_INT4_M 0x000000FF // Interrupt 4 priority mask
+#define NVIC_PRI1_INT7_S 24
+#define NVIC_PRI1_INT6_S 16
+#define NVIC_PRI1_INT5_S 8
+#define NVIC_PRI1_INT4_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI2 register.
+//
+//*****************************************************************************
+#define NVIC_PRI2_INT11_M 0xFF000000 // Interrupt 11 priority mask
+#define NVIC_PRI2_INT10_M 0x00FF0000 // Interrupt 10 priority mask
+#define NVIC_PRI2_INT9_M 0x0000FF00 // Interrupt 9 priority mask
+#define NVIC_PRI2_INT8_M 0x000000FF // Interrupt 8 priority mask
+#define NVIC_PRI2_INT11_S 24
+#define NVIC_PRI2_INT10_S 16
+#define NVIC_PRI2_INT9_S 8
+#define NVIC_PRI2_INT8_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI3 register.
+//
+//*****************************************************************************
+#define NVIC_PRI3_INT15_M 0xFF000000 // Interrupt 15 priority mask
+#define NVIC_PRI3_INT14_M 0x00FF0000 // Interrupt 14 priority mask
+#define NVIC_PRI3_INT13_M 0x0000FF00 // Interrupt 13 priority mask
+#define NVIC_PRI3_INT12_M 0x000000FF // Interrupt 12 priority mask
+#define NVIC_PRI3_INT15_S 24
+#define NVIC_PRI3_INT14_S 16
+#define NVIC_PRI3_INT13_S 8
+#define NVIC_PRI3_INT12_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI4 register.
+//
+//*****************************************************************************
+#define NVIC_PRI4_INT19_M 0xFF000000 // Interrupt 19 priority mask
+#define NVIC_PRI4_INT18_M 0x00FF0000 // Interrupt 18 priority mask
+#define NVIC_PRI4_INT17_M 0x0000FF00 // Interrupt 17 priority mask
+#define NVIC_PRI4_INT16_M 0x000000FF // Interrupt 16 priority mask
+#define NVIC_PRI4_INT19_S 24
+#define NVIC_PRI4_INT18_S 16
+#define NVIC_PRI4_INT17_S 8
+#define NVIC_PRI4_INT16_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI5 register.
+//
+//*****************************************************************************
+#define NVIC_PRI5_INT23_M 0xFF000000 // Interrupt 23 priority mask
+#define NVIC_PRI5_INT22_M 0x00FF0000 // Interrupt 22 priority mask
+#define NVIC_PRI5_INT21_M 0x0000FF00 // Interrupt 21 priority mask
+#define NVIC_PRI5_INT20_M 0x000000FF // Interrupt 20 priority mask
+#define NVIC_PRI5_INT23_S 24
+#define NVIC_PRI5_INT22_S 16
+#define NVIC_PRI5_INT21_S 8
+#define NVIC_PRI5_INT20_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI6 register.
+//
+//*****************************************************************************
+#define NVIC_PRI6_INT27_M 0xFF000000 // Interrupt 27 priority mask
+#define NVIC_PRI6_INT26_M 0x00FF0000 // Interrupt 26 priority mask
+#define NVIC_PRI6_INT25_M 0x0000FF00 // Interrupt 25 priority mask
+#define NVIC_PRI6_INT24_M 0x000000FF // Interrupt 24 priority mask
+#define NVIC_PRI6_INT27_S 24
+#define NVIC_PRI6_INT26_S 16
+#define NVIC_PRI6_INT25_S 8
+#define NVIC_PRI6_INT24_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI7 register.
+//
+//*****************************************************************************
+#define NVIC_PRI7_INT31_M 0xFF000000 // Interrupt 31 priority mask
+#define NVIC_PRI7_INT30_M 0x00FF0000 // Interrupt 30 priority mask
+#define NVIC_PRI7_INT29_M 0x0000FF00 // Interrupt 29 priority mask
+#define NVIC_PRI7_INT28_M 0x000000FF // Interrupt 28 priority mask
+#define NVIC_PRI7_INT31_S 24
+#define NVIC_PRI7_INT30_S 16
+#define NVIC_PRI7_INT29_S 8
+#define NVIC_PRI7_INT28_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI8 register.
+//
+//*****************************************************************************
+#define NVIC_PRI8_INT35_M 0xFF000000 // Interrupt 35 priority mask
+#define NVIC_PRI8_INT34_M 0x00FF0000 // Interrupt 34 priority mask
+#define NVIC_PRI8_INT33_M 0x0000FF00 // Interrupt 33 priority mask
+#define NVIC_PRI8_INT32_M 0x000000FF // Interrupt 32 priority mask
+#define NVIC_PRI8_INT35_S 24
+#define NVIC_PRI8_INT34_S 16
+#define NVIC_PRI8_INT33_S 8
+#define NVIC_PRI8_INT32_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI9 register.
+//
+//*****************************************************************************
+#define NVIC_PRI9_INT39_M 0xFF000000 // Interrupt 39 priority mask
+#define NVIC_PRI9_INT38_M 0x00FF0000 // Interrupt 38 priority mask
+#define NVIC_PRI9_INT37_M 0x0000FF00 // Interrupt 37 priority mask
+#define NVIC_PRI9_INT36_M 0x000000FF // Interrupt 36 priority mask
+#define NVIC_PRI9_INT39_S 24
+#define NVIC_PRI9_INT38_S 16
+#define NVIC_PRI9_INT37_S 8
+#define NVIC_PRI9_INT36_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI10 register.
+//
+//*****************************************************************************
+#define NVIC_PRI10_INT43_M 0xFF000000 // Interrupt 43 priority mask
+#define NVIC_PRI10_INT42_M 0x00FF0000 // Interrupt 42 priority mask
+#define NVIC_PRI10_INT41_M 0x0000FF00 // Interrupt 41 priority mask
+#define NVIC_PRI10_INT40_M 0x000000FF // Interrupt 40 priority mask
+#define NVIC_PRI10_INT43_S 24
+#define NVIC_PRI10_INT42_S 16
+#define NVIC_PRI10_INT41_S 8
+#define NVIC_PRI10_INT40_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_CPUID register.
+//
+//*****************************************************************************
+#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer
+#define NVIC_CPUID_VAR_M 0x00F00000 // Variant
+#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Processor part number
+#define NVIC_CPUID_REV_M 0x0000000F // Revision
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_INT_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_INT_CTRL_NMI_SET 0x80000000 // Pend a NMI
+#define NVIC_INT_CTRL_PEND_SV 0x10000000 // Pend a PendSV
+#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // Unpend a PendSV
+#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug interrupt handling
+#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Debug interrupt pending
+#define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000 // Highest pending exception
+#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to base
+#define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF // Current active exception
+#define NVIC_INT_CTRL_VEC_PEN_S 12
+#define NVIC_INT_CTRL_VEC_ACT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_VTABLE register.
+//
+//*****************************************************************************
+#define NVIC_VTABLE_BASE 0x20000000 // Vector table base
+#define NVIC_VTABLE_OFFSET_M 0x1FFFFF00 // Vector table offset
+#define NVIC_VTABLE_OFFSET_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_APINT register.
+//
+//*****************************************************************************
+#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Vector key mask
+#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key
+#define NVIC_APINT_ENDIANESS 0x00008000 // Data endianess
+#define NVIC_APINT_PRIGROUP_M 0x00000700 // Priority group
+#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split
+#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split
+#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split
+#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split
+#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split
+#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split
+#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split
+#define NVIC_APINT_SYSRESETREQ 0x00000004 // System reset request
+#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear active NMI/fault info
+#define NVIC_APINT_VECT_RESET 0x00000001 // System reset
+#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wakeup on pend
+#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep sleep enable
+#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR exit
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_CFG_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore bus fault in NMI/fault
+#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on divide by 0
+#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on unaligned access
+#define NVIC_CFG_CTRL_DEEP_PEND 0x00000004 // Allow deep interrupt trigger
+#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow main interrupt trigger
+#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread state control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_PRI1 register.
+//
+//*****************************************************************************
+#define NVIC_SYS_PRI1_RES_M 0xFF000000 // Priority of reserved handler
+#define NVIC_SYS_PRI1_USAGE_M 0x00FF0000 // Priority of usage fault handler
+#define NVIC_SYS_PRI1_BUS_M 0x0000FF00 // Priority of bus fault handler
+#define NVIC_SYS_PRI1_MEM_M 0x000000FF // Priority of mem manage handler
+#define NVIC_SYS_PRI1_USAGE_S 16
+#define NVIC_SYS_PRI1_BUS_S 8
+#define NVIC_SYS_PRI1_MEM_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_PRI2 register.
+//
+//*****************************************************************************
+#define NVIC_SYS_PRI2_SVC_M 0xFF000000 // Priority of SVCall handler
+#define NVIC_SYS_PRI2_RES_M 0x00FFFFFF // Priority of reserved handlers
+#define NVIC_SYS_PRI2_SVC_S 24
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_PRI3 register.
+//
+//*****************************************************************************
+#define NVIC_SYS_PRI3_TICK_M 0xFF000000 // Priority of Sys Tick handler
+#define NVIC_SYS_PRI3_PENDSV_M 0x00FF0000 // Priority of PendSV handler
+#define NVIC_SYS_PRI3_RES_M 0x0000FF00 // Priority of reserved handler
+#define NVIC_SYS_PRI3_DEBUG_M 0x000000FF // Priority of debug handler
+#define NVIC_SYS_PRI3_TICK_S 24
+#define NVIC_SYS_PRI3_PENDSV_S 16
+#define NVIC_SYS_PRI3_DEBUG_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_HND_CTRL
+// register.
+//
+//*****************************************************************************
+#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage fault enable
+#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus fault enable
+#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Mem manage fault enable
+#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVCall is pended
+#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus fault is pended
+#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // Sys tick is active
+#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV is active
+#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Monitor is active
+#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVCall is active
+#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage fault is active
+#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus fault is active
+#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Mem manage is active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FAULT_STAT
+// register.
+//
+//*****************************************************************************
+#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide by zero fault
+#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned access fault
+#define NVIC_FAULT_STAT_NOCP 0x00080000 // No coprocessor fault
+#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC fault
+#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid state fault
+#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined instruction fault
+#define NVIC_FAULT_STAT_BFARV 0x00008000 // BFAR is valid
+#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack bus fault
+#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack bus fault
+#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise data bus error
+#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise data bus error
+#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction bus fault
+#define NVIC_FAULT_STAT_MMARV 0x00000080 // MMAR is valid
+#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack access violation
+#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack access violation
+#define NVIC_FAULT_STAT_DERR 0x00000002 // Data access violation
+#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction access violation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_HFAULT_STAT
+// register.
+//
+//*****************************************************************************
+#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug event
+#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Cannot execute fault handler
+#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector table read fault
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DEBUG_STAT
+// register.
+//
+//*****************************************************************************
+#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted
+#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch
+#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match
+#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction
+#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MM_ADDR register.
+//
+//*****************************************************************************
+#define NVIC_MM_ADDR_M 0xFFFFFFFF // Data fault address
+#define NVIC_MM_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FAULT_ADDR
+// register.
+//
+//*****************************************************************************
+#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Data bus fault address
+#define NVIC_FAULT_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_TYPE register.
+//
+//*****************************************************************************
+#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I regions
+#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D regions
+#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or unified MPU
+#define NVIC_MPU_TYPE_IREGION_S 16
+#define NVIC_MPU_TYPE_DREGION_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004 // MPU default region in priv mode
+#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU enabled during faults
+#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_NUMBER
+// register.
+//
+//*****************************************************************************
+#define NVIC_MPU_NUMBER_M 0x000000FF // MPU region to access
+#define NVIC_MPU_NUMBER_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE_ADDR_M 0xFFFFFFE0 // Base address mask
+#define NVIC_MPU_BASE_VALID 0x00000010 // Region number valid
+#define NVIC_MPU_BASE_REGION_M 0x0000000F // Region number
+#define NVIC_MPU_BASE_ADDR_S 8
+#define NVIC_MPU_BASE_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR_M 0xFFFF0000 // Attributes
+#define NVIC_MPU_ATTR_AP_NO_NO 0x00000000 // prv: no access, usr: no access
+#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000 // Bufferable
+#define NVIC_MPU_ATTR_CACHEABLE 0x00020000 // Cacheable
+#define NVIC_MPU_ATTR_SHAREABLE 0x00040000 // Shareable
+#define NVIC_MPU_ATTR_TEX_M 0x00380000 // Type extension mask
+#define NVIC_MPU_ATTR_AP_RW_NO 0x01000000 // prv: rw, usr: none
+#define NVIC_MPU_ATTR_AP_RW_RO 0x02000000 // prv: rw, usr: read-only
+#define NVIC_MPU_ATTR_AP_RW_RW 0x03000000 // prv: rw, usr: rw
+#define NVIC_MPU_ATTR_AP_RO_NO 0x05000000 // prv: ro, usr: none
+#define NVIC_MPU_ATTR_AP_RO_RO 0x06000000 // prv: ro, usr: ro
+#define NVIC_MPU_ATTR_AP_M 0x07000000 // Access permissions mask
+#define NVIC_MPU_ATTR_XN 0x10000000 // Execute disable
+#define NVIC_MPU_ATTR_SRD_M 0x0000FF00 // Sub-region disable mask
+#define NVIC_MPU_ATTR_SRD_0 0x00000100 // Sub-region 0 disable
+#define NVIC_MPU_ATTR_SRD_1 0x00000200 // Sub-region 1 disable
+#define NVIC_MPU_ATTR_SRD_2 0x00000400 // Sub-region 2 disable
+#define NVIC_MPU_ATTR_SRD_3 0x00000800 // Sub-region 3 disable
+#define NVIC_MPU_ATTR_SRD_4 0x00001000 // Sub-region 4 disable
+#define NVIC_MPU_ATTR_SRD_5 0x00002000 // Sub-region 5 disable
+#define NVIC_MPU_ATTR_SRD_6 0x00004000 // Sub-region 6 disable
+#define NVIC_MPU_ATTR_SRD_7 0x00008000 // Sub-region 7 disable
+#define NVIC_MPU_ATTR_SIZE_M 0x0000003E // Region size mask
+#define NVIC_MPU_ATTR_SIZE_32B 0x00000008 // Region size 32 bytes
+#define NVIC_MPU_ATTR_SIZE_64B 0x0000000A // Region size 64 bytes
+#define NVIC_MPU_ATTR_SIZE_128B 0x0000000C // Region size 128 bytes
+#define NVIC_MPU_ATTR_SIZE_256B 0x0000000E // Region size 256 bytes
+#define NVIC_MPU_ATTR_SIZE_512B 0x00000010 // Region size 512 bytes
+#define NVIC_MPU_ATTR_SIZE_1K 0x00000012 // Region size 1 Kbytes
+#define NVIC_MPU_ATTR_SIZE_2K 0x00000014 // Region size 2 Kbytes
+#define NVIC_MPU_ATTR_SIZE_4K 0x00000016 // Region size 4 Kbytes
+#define NVIC_MPU_ATTR_SIZE_8K 0x00000018 // Region size 8 Kbytes
+#define NVIC_MPU_ATTR_SIZE_16K 0x0000001A // Region size 16 Kbytes
+#define NVIC_MPU_ATTR_SIZE_32K 0x0000001C // Region size 32 Kbytes
+#define NVIC_MPU_ATTR_SIZE_64K 0x0000001E // Region size 64 Kbytes
+#define NVIC_MPU_ATTR_SIZE_128K 0x00000020 // Region size 128 Kbytes
+#define NVIC_MPU_ATTR_SIZE_256K 0x00000022 // Region size 256 Kbytes
+#define NVIC_MPU_ATTR_SIZE_512K 0x00000024 // Region size 512 Kbytes
+#define NVIC_MPU_ATTR_SIZE_1M 0x00000026 // Region size 1 Mbytes
+#define NVIC_MPU_ATTR_SIZE_2M 0x00000028 // Region size 2 Mbytes
+#define NVIC_MPU_ATTR_SIZE_4M 0x0000002A // Region size 4 Mbytes
+#define NVIC_MPU_ATTR_SIZE_8M 0x0000002C // Region size 8 Mbytes
+#define NVIC_MPU_ATTR_SIZE_16M 0x0000002E // Region size 16 Mbytes
+#define NVIC_MPU_ATTR_SIZE_32M 0x00000030 // Region size 32 Mbytes
+#define NVIC_MPU_ATTR_SIZE_64M 0x00000032 // Region size 64 Mbytes
+#define NVIC_MPU_ATTR_SIZE_128M 0x00000034 // Region size 128 Mbytes
+#define NVIC_MPU_ATTR_SIZE_256M 0x00000036 // Region size 256 Mbytes
+#define NVIC_MPU_ATTR_SIZE_512M 0x00000038 // Region size 512 Mbytes
+#define NVIC_MPU_ATTR_SIZE_1G 0x0000003A // Region size 1 Gbytes
+#define NVIC_MPU_ATTR_SIZE_2G 0x0000003C // Region size 2 Gbytes
+#define NVIC_MPU_ATTR_SIZE_4G 0x0000003E // Region size 4 Gbytes
+#define NVIC_MPU_ATTR_ENABLE 0x00000001 // Region enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask
+#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key
+#define NVIC_DBG_CTRL_S_RESET_ST \
+ 0x02000000 // Core has reset since last read
+#define NVIC_DBG_CTRL_S_RETIRE_ST \
+ 0x01000000 // Core has executed insruction
+ // since last read
+#define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 // Core is locked up
+#define NVIC_DBG_CTRL_S_SLEEP 0x00040000 // Core is sleeping
+#define NVIC_DBG_CTRL_S_HALT 0x00020000 // Core status on halt
+#define NVIC_DBG_CTRL_S_REGRDY 0x00010000 // Register read/write available
+#define NVIC_DBG_CTRL_C_SNAPSTALL \
+ 0x00000020 // Breaks a stalled load/store
+#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping
+#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core
+#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core
+#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_XFER register.
+//
+//*****************************************************************************
+#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read
+#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register
+#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask
+#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP
+#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP
+#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP
+#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register
+#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15
+#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14
+#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13
+#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12
+#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11
+#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10
+#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9
+#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8
+#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7
+#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6
+#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5
+#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4
+#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3
+#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2
+#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1
+#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_DATA register.
+//
+//*****************************************************************************
+#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache
+#define NVIC_DBG_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_INT register.
+//
+//*****************************************************************************
+#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault
+#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors
+#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error
+#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state
+#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check
+#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error
+#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault
+#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status
+#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset
+#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending
+#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SW_TRIG register.
+//
+//*****************************************************************************
+#define NVIC_SW_TRIG_INTID_M 0x000003FF // Interrupt to trigger
+#define NVIC_SW_TRIG_INTID_S 0
+
+#endif // __LM3S6918_H__
Property changes on: branches/eagle_mmc/src/platform/lm3s/lm3s6918.h
___________________________________________________________________
Name: svn:executable
+ *
Added: branches/eagle_mmc/src/platform/lm3s/lm3s6965.h
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/lm3s6965.h 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lm3s/lm3s6965.h 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,4565 @@
+//*****************************************************************************
+//
+// lm3s6965.h - LM3S6965 Register Definitions
+//
+// Copyright (c) 2007-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4781 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __LM3S6965_H__
+#define __LM3S6965_H__
+
+//*****************************************************************************
+//
+// Watchdog Timer (WATCHDOG)
+//
+//*****************************************************************************
+#define WATCHDOG_LOAD_R (*((volatile unsigned long *)0x40000000))
+#define WATCHDOG_VALUE_R (*((volatile unsigned long *)0x40000004))
+#define WATCHDOG_CTL_R (*((volatile unsigned long *)0x40000008))
+#define WATCHDOG_ICR_R (*((volatile unsigned long *)0x4000000C))
+#define WATCHDOG_RIS_R (*((volatile unsigned long *)0x40000010))
+#define WATCHDOG_MIS_R (*((volatile unsigned long *)0x40000014))
+#define WATCHDOG_TEST_R (*((volatile unsigned long *)0x40000418))
+#define WATCHDOG_LOCK_R (*((volatile unsigned long *)0x40000C00))
+
+//*****************************************************************************
+//
+// General-Purpose Input/Outputs (PORTA)
+//
+//*****************************************************************************
+#define GPIO_PORTA_DATA_BITS_R ((volatile unsigned long *)0x40004000)
+#define GPIO_PORTA_DATA_R (*((volatile unsigned long *)0x400043FC))
+#define GPIO_PORTA_DIR_R (*((volatile unsigned long *)0x40004400))
+#define GPIO_PORTA_IS_R (*((volatile unsigned long *)0x40004404))
+#define GPIO_PORTA_IBE_R (*((volatile unsigned long *)0x40004408))
+#define GPIO_PORTA_IEV_R (*((volatile unsigned long *)0x4000440C))
+#define GPIO_PORTA_IM_R (*((volatile unsigned long *)0x40004410))
+#define GPIO_PORTA_RIS_R (*((volatile unsigned long *)0x40004414))
+#define GPIO_PORTA_MIS_R (*((volatile unsigned long *)0x40004418))
+#define GPIO_PORTA_ICR_R (*((volatile unsigned long *)0x4000441C))
+#define GPIO_PORTA_AFSEL_R (*((volatile unsigned long *)0x40004420))
+#define GPIO_PORTA_DR2R_R (*((volatile unsigned long *)0x40004500))
+#define GPIO_PORTA_DR4R_R (*((volatile unsigned long *)0x40004504))
+#define GPIO_PORTA_DR8R_R (*((volatile unsigned long *)0x40004508))
+#define GPIO_PORTA_ODR_R (*((volatile unsigned long *)0x4000450C))
+#define GPIO_PORTA_PUR_R (*((volatile unsigned long *)0x40004510))
+#define GPIO_PORTA_PDR_R (*((volatile unsigned long *)0x40004514))
+#define GPIO_PORTA_SLR_R (*((volatile unsigned long *)0x40004518))
+#define GPIO_PORTA_DEN_R (*((volatile unsigned long *)0x4000451C))
+#define GPIO_PORTA_LOCK_R (*((volatile unsigned long *)0x40004520))
+#define GPIO_PORTA_CR_R (*((volatile unsigned long *)0x40004524))
+
+//*****************************************************************************
+//
+// General-Purpose Input/Outputs (PORTB)
+//
+//*****************************************************************************
+#define GPIO_PORTB_DATA_BITS_R ((volatile unsigned long *)0x40005000)
+#define GPIO_PORTB_DATA_R (*((volatile unsigned long *)0x400053FC))
+#define GPIO_PORTB_DIR_R (*((volatile unsigned long *)0x40005400))
+#define GPIO_PORTB_IS_R (*((volatile unsigned long *)0x40005404))
+#define GPIO_PORTB_IBE_R (*((volatile unsigned long *)0x40005408))
+#define GPIO_PORTB_IEV_R (*((volatile unsigned long *)0x4000540C))
+#define GPIO_PORTB_IM_R (*((volatile unsigned long *)0x40005410))
+#define GPIO_PORTB_RIS_R (*((volatile unsigned long *)0x40005414))
+#define GPIO_PORTB_MIS_R (*((volatile unsigned long *)0x40005418))
+#define GPIO_PORTB_ICR_R (*((volatile unsigned long *)0x4000541C))
+#define GPIO_PORTB_AFSEL_R (*((volatile unsigned long *)0x40005420))
+#define GPIO_PORTB_DR2R_R (*((volatile unsigned long *)0x40005500))
+#define GPIO_PORTB_DR4R_R (*((volatile unsigned long *)0x40005504))
+#define GPIO_PORTB_DR8R_R (*((volatile unsigned long *)0x40005508))
+#define GPIO_PORTB_ODR_R (*((volatile unsigned long *)0x4000550C))
+#define GPIO_PORTB_PUR_R (*((volatile unsigned long *)0x40005510))
+#define GPIO_PORTB_PDR_R (*((volatile unsigned long *)0x40005514))
+#define GPIO_PORTB_SLR_R (*((volatile unsigned long *)0x40005518))
+#define GPIO_PORTB_DEN_R (*((volatile unsigned long *)0x4000551C))
+#define GPIO_PORTB_LOCK_R (*((volatile unsigned long *)0x40005520))
+#define GPIO_PORTB_CR_R (*((volatile unsigned long *)0x40005524))
+
+//*****************************************************************************
+//
+// General-Purpose Input/Outputs (PORTC)
+//
+//*****************************************************************************
+#define GPIO_PORTC_DATA_BITS_R ((volatile unsigned long *)0x40006000)
+#define GPIO_PORTC_DATA_R (*((volatile unsigned long *)0x400063FC))
+#define GPIO_PORTC_DIR_R (*((volatile unsigned long *)0x40006400))
+#define GPIO_PORTC_IS_R (*((volatile unsigned long *)0x40006404))
+#define GPIO_PORTC_IBE_R (*((volatile unsigned long *)0x40006408))
+#define GPIO_PORTC_IEV_R (*((volatile unsigned long *)0x4000640C))
+#define GPIO_PORTC_IM_R (*((volatile unsigned long *)0x40006410))
+#define GPIO_PORTC_RIS_R (*((volatile unsigned long *)0x40006414))
+#define GPIO_PORTC_MIS_R (*((volatile unsigned long *)0x40006418))
+#define GPIO_PORTC_ICR_R (*((volatile unsigned long *)0x4000641C))
+#define GPIO_PORTC_AFSEL_R (*((volatile unsigned long *)0x40006420))
+#define GPIO_PORTC_DR2R_R (*((volatile unsigned long *)0x40006500))
+#define GPIO_PORTC_DR4R_R (*((volatile unsigned long *)0x40006504))
+#define GPIO_PORTC_DR8R_R (*((volatile unsigned long *)0x40006508))
+#define GPIO_PORTC_ODR_R (*((volatile unsigned long *)0x4000650C))
+#define GPIO_PORTC_PUR_R (*((volatile unsigned long *)0x40006510))
+#define GPIO_PORTC_PDR_R (*((volatile unsigned long *)0x40006514))
+#define GPIO_PORTC_SLR_R (*((volatile unsigned long *)0x40006518))
+#define GPIO_PORTC_DEN_R (*((volatile unsigned long *)0x4000651C))
+#define GPIO_PORTC_LOCK_R (*((volatile unsigned long *)0x40006520))
+#define GPIO_PORTC_CR_R (*((volatile unsigned long *)0x40006524))
+
+//*****************************************************************************
+//
+// General-Purpose Input/Outputs (PORTD)
+//
+//*****************************************************************************
+#define GPIO_PORTD_DATA_BITS_R ((volatile unsigned long *)0x40007000)
+#define GPIO_PORTD_DATA_R (*((volatile unsigned long *)0x400073FC))
+#define GPIO_PORTD_DIR_R (*((volatile unsigned long *)0x40007400))
+#define GPIO_PORTD_IS_R (*((volatile unsigned long *)0x40007404))
+#define GPIO_PORTD_IBE_R (*((volatile unsigned long *)0x40007408))
+#define GPIO_PORTD_IEV_R (*((volatile unsigned long *)0x4000740C))
+#define GPIO_PORTD_IM_R (*((volatile unsigned long *)0x40007410))
+#define GPIO_PORTD_RIS_R (*((volatile unsigned long *)0x40007414))
+#define GPIO_PORTD_MIS_R (*((volatile unsigned long *)0x40007418))
+#define GPIO_PORTD_ICR_R (*((volatile unsigned long *)0x4000741C))
+#define GPIO_PORTD_AFSEL_R (*((volatile unsigned long *)0x40007420))
+#define GPIO_PORTD_DR2R_R (*((volatile unsigned long *)0x40007500))
+#define GPIO_PORTD_DR4R_R (*((volatile unsigned long *)0x40007504))
+#define GPIO_PORTD_DR8R_R (*((volatile unsigned long *)0x40007508))
+#define GPIO_PORTD_ODR_R (*((volatile unsigned long *)0x4000750C))
+#define GPIO_PORTD_PUR_R (*((volatile unsigned long *)0x40007510))
+#define GPIO_PORTD_PDR_R (*((volatile unsigned long *)0x40007514))
+#define GPIO_PORTD_SLR_R (*((volatile unsigned long *)0x40007518))
+#define GPIO_PORTD_DEN_R (*((volatile unsigned long *)0x4000751C))
+#define GPIO_PORTD_LOCK_R (*((volatile unsigned long *)0x40007520))
+#define GPIO_PORTD_CR_R (*((volatile unsigned long *)0x40007524))
+
+//*****************************************************************************
+//
+// Synchronous Serial Interface (SSI0)
+//
+//*****************************************************************************
+#define SSI0_CR0_R (*((volatile unsigned long *)0x40008000))
+#define SSI0_CR1_R (*((volatile unsigned long *)0x40008004))
+#define SSI0_DR_R (*((volatile unsigned long *)0x40008008))
+#define SSI0_SR_R (*((volatile unsigned long *)0x4000800C))
+#define SSI0_CPSR_R (*((volatile unsigned long *)0x40008010))
+#define SSI0_IM_R (*((volatile unsigned long *)0x40008014))
+#define SSI0_RIS_R (*((volatile unsigned long *)0x40008018))
+#define SSI0_MIS_R (*((volatile unsigned long *)0x4000801C))
+#define SSI0_ICR_R (*((volatile unsigned long *)0x40008020))
+
+//*****************************************************************************
+//
+// Universal Asynchronous Receivers/Transmitters (UART0)
+//
+//*****************************************************************************
+#define UART0_DR_R (*((volatile unsigned long *)0x4000C000))
+#define UART0_RSR_R (*((volatile unsigned long *)0x4000C004))
+#define UART0_ECR_R (*((volatile unsigned long *)0x4000C004))
+#define UART0_FR_R (*((volatile unsigned long *)0x4000C018))
+#define UART0_ILPR_R (*((volatile unsigned long *)0x4000C020))
+#define UART0_IBRD_R (*((volatile unsigned long *)0x4000C024))
+#define UART0_FBRD_R (*((volatile unsigned long *)0x4000C028))
+#define UART0_LCRH_R (*((volatile unsigned long *)0x4000C02C))
+#define UART0_CTL_R (*((volatile unsigned long *)0x4000C030))
+#define UART0_IFLS_R (*((volatile unsigned long *)0x4000C034))
+#define UART0_IM_R (*((volatile unsigned long *)0x4000C038))
+#define UART0_RIS_R (*((volatile unsigned long *)0x4000C03C))
+#define UART0_MIS_R (*((volatile unsigned long *)0x4000C040))
+#define UART0_ICR_R (*((volatile unsigned long *)0x4000C044))
+
+//*****************************************************************************
+//
+// Universal Asynchronous Receivers/Transmitters (UART1)
+//
+//*****************************************************************************
+#define UART1_DR_R (*((volatile unsigned long *)0x4000D000))
+#define UART1_RSR_R (*((volatile unsigned long *)0x4000D004))
+#define UART1_ECR_R (*((volatile unsigned long *)0x4000D004))
+#define UART1_FR_R (*((volatile unsigned long *)0x4000D018))
+#define UART1_ILPR_R (*((volatile unsigned long *)0x4000D020))
+#define UART1_IBRD_R (*((volatile unsigned long *)0x4000D024))
+#define UART1_FBRD_R (*((volatile unsigned long *)0x4000D028))
+#define UART1_LCRH_R (*((volatile unsigned long *)0x4000D02C))
+#define UART1_CTL_R (*((volatile unsigned long *)0x4000D030))
+#define UART1_IFLS_R (*((volatile unsigned long *)0x4000D034))
+#define UART1_IM_R (*((volatile unsigned long *)0x4000D038))
+#define UART1_RIS_R (*((volatile unsigned long *)0x4000D03C))
+#define UART1_MIS_R (*((volatile unsigned long *)0x4000D040))
+#define UART1_ICR_R (*((volatile unsigned long *)0x4000D044))
+
+//*****************************************************************************
+//
+// Universal Asynchronous Receivers/Transmitters (UART2)
+//
+//*****************************************************************************
+#define UART2_DR_R (*((volatile unsigned long *)0x4000E000))
+#define UART2_RSR_R (*((volatile unsigned long *)0x4000E004))
+#define UART2_ECR_R (*((volatile unsigned long *)0x4000E004))
+#define UART2_FR_R (*((volatile unsigned long *)0x4000E018))
+#define UART2_ILPR_R (*((volatile unsigned long *)0x4000E020))
+#define UART2_IBRD_R (*((volatile unsigned long *)0x4000E024))
+#define UART2_FBRD_R (*((volatile unsigned long *)0x4000E028))
+#define UART2_LCRH_R (*((volatile unsigned long *)0x4000E02C))
+#define UART2_CTL_R (*((volatile unsigned long *)0x4000E030))
+#define UART2_IFLS_R (*((volatile unsigned long *)0x4000E034))
+#define UART2_IM_R (*((volatile unsigned long *)0x4000E038))
+#define UART2_RIS_R (*((volatile unsigned long *)0x4000E03C))
+#define UART2_MIS_R (*((volatile unsigned long *)0x4000E040))
+#define UART2_ICR_R (*((volatile unsigned long *)0x4000E044))
+
+//*****************************************************************************
+//
+// Inter-Integrated Circuit (MASTER) Interface
+//
+//*****************************************************************************
+#define I2C0_MASTER_MSA_R (*((volatile unsigned long *)0x40020000))
+#define I2C0_MASTER_SOAR_R (*((volatile unsigned long *)0x40020000))
+#define I2C0_MASTER_SCSR_R (*((volatile unsigned long *)0x40020004))
+#define I2C0_MASTER_MCS_R (*((volatile unsigned long *)0x40020004))
+#define I2C0_MASTER_SDR_R (*((volatile unsigned long *)0x40020008))
+#define I2C0_MASTER_MDR_R (*((volatile unsigned long *)0x40020008))
+#define I2C0_MASTER_MTPR_R (*((volatile unsigned long *)0x4002000C))
+#define I2C0_MASTER_SIMR_R (*((volatile unsigned long *)0x4002000C))
+#define I2C0_MASTER_SRIS_R (*((volatile unsigned long *)0x40020010))
+#define I2C0_MASTER_MIMR_R (*((volatile unsigned long *)0x40020010))
+#define I2C0_MASTER_MRIS_R (*((volatile unsigned long *)0x40020014))
+#define I2C0_MASTER_SMIS_R (*((volatile unsigned long *)0x40020014))
+#define I2C0_MASTER_SICR_R (*((volatile unsigned long *)0x40020018))
+#define I2C0_MASTER_MMIS_R (*((volatile unsigned long *)0x40020018))
+#define I2C0_MASTER_MICR_R (*((volatile unsigned long *)0x4002001C))
+#define I2C0_MASTER_MCR_R (*((volatile unsigned long *)0x40020020))
+
+//*****************************************************************************
+//
+// Inter-Integrated Circuit (SLAVE) Interface
+//
+//*****************************************************************************
+#define I2C0_SLAVE_MSA_R (*((volatile unsigned long *)0x40020800))
+#define I2C0_SLAVE_SOAR_R (*((volatile unsigned long *)0x40020800))
+#define I2C0_SLAVE_SCSR_R (*((volatile unsigned long *)0x40020804))
+#define I2C0_SLAVE_MCS_R (*((volatile unsigned long *)0x40020804))
+#define I2C0_SLAVE_SDR_R (*((volatile unsigned long *)0x40020808))
+#define I2C0_SLAVE_MDR_R (*((volatile unsigned long *)0x40020808))
+#define I2C0_SLAVE_MTPR_R (*((volatile unsigned long *)0x4002080C))
+#define I2C0_SLAVE_SIMR_R (*((volatile unsigned long *)0x4002080C))
+#define I2C0_SLAVE_SRIS_R (*((volatile unsigned long *)0x40020810))
+#define I2C0_SLAVE_MIMR_R (*((volatile unsigned long *)0x40020810))
+#define I2C0_SLAVE_MRIS_R (*((volatile unsigned long *)0x40020814))
+#define I2C0_SLAVE_SMIS_R (*((volatile unsigned long *)0x40020814))
+#define I2C0_SLAVE_SICR_R (*((volatile unsigned long *)0x40020818))
+#define I2C0_SLAVE_MMIS_R (*((volatile unsigned long *)0x40020818))
+#define I2C0_SLAVE_MICR_R (*((volatile unsigned long *)0x4002081C))
+#define I2C0_SLAVE_MCR_R (*((volatile unsigned long *)0x40020820))
+
+//*****************************************************************************
+//
+// Inter-Integrated Circuit (MASTER) Interface
+//
+//*****************************************************************************
+#define I2C1_MASTER_MSA_R (*((volatile unsigned long *)0x40021000))
+#define I2C1_MASTER_SOAR_R (*((volatile unsigned long *)0x40021000))
+#define I2C1_MASTER_SCSR_R (*((volatile unsigned long *)0x40021004))
+#define I2C1_MASTER_MCS_R (*((volatile unsigned long *)0x40021004))
+#define I2C1_MASTER_SDR_R (*((volatile unsigned long *)0x40021008))
+#define I2C1_MASTER_MDR_R (*((volatile unsigned long *)0x40021008))
+#define I2C1_MASTER_MTPR_R (*((volatile unsigned long *)0x4002100C))
+#define I2C1_MASTER_SIMR_R (*((volatile unsigned long *)0x4002100C))
+#define I2C1_MASTER_SRIS_R (*((volatile unsigned long *)0x40021010))
+#define I2C1_MASTER_MIMR_R (*((volatile unsigned long *)0x40021010))
+#define I2C1_MASTER_MRIS_R (*((volatile unsigned long *)0x40021014))
+#define I2C1_MASTER_SMIS_R (*((volatile unsigned long *)0x40021014))
+#define I2C1_MASTER_SICR_R (*((volatile unsigned long *)0x40021018))
+#define I2C1_MASTER_MMIS_R (*((volatile unsigned long *)0x40021018))
+#define I2C1_MASTER_MICR_R (*((volatile unsigned long *)0x4002101C))
+#define I2C1_MASTER_MCR_R (*((volatile unsigned long *)0x40021020))
+
+//*****************************************************************************
+//
+// Inter-Integrated Circuit (SLAVE) Interface
+//
+//*****************************************************************************
+#define I2C1_SLAVE_MSA_R (*((volatile unsigned long *)0x40021800))
+#define I2C1_SLAVE_SOAR_R (*((volatile unsigned long *)0x40021800))
+#define I2C1_SLAVE_SCSR_R (*((volatile unsigned long *)0x40021804))
+#define I2C1_SLAVE_MCS_R (*((volatile unsigned long *)0x40021804))
+#define I2C1_SLAVE_SDR_R (*((volatile unsigned long *)0x40021808))
+#define I2C1_SLAVE_MDR_R (*((volatile unsigned long *)0x40021808))
+#define I2C1_SLAVE_MTPR_R (*((volatile unsigned long *)0x4002180C))
+#define I2C1_SLAVE_SIMR_R (*((volatile unsigned long *)0x4002180C))
+#define I2C1_SLAVE_SRIS_R (*((volatile unsigned long *)0x40021810))
+#define I2C1_SLAVE_MIMR_R (*((volatile unsigned long *)0x40021810))
+#define I2C1_SLAVE_MRIS_R (*((volatile unsigned long *)0x40021814))
+#define I2C1_SLAVE_SMIS_R (*((volatile unsigned long *)0x40021814))
+#define I2C1_SLAVE_SICR_R (*((volatile unsigned long *)0x40021818))
+#define I2C1_SLAVE_MMIS_R (*((volatile unsigned long *)0x40021818))
+#define I2C1_SLAVE_MICR_R (*((volatile unsigned long *)0x4002181C))
+#define I2C1_SLAVE_MCR_R (*((volatile unsigned long *)0x40021820))
+
+//*****************************************************************************
+//
+// General-Purpose Input/Outputs (PORTE)
+//
+//*****************************************************************************
+#define GPIO_PORTE_DATA_BITS_R ((volatile unsigned long *)0x40024000)
+#define GPIO_PORTE_DATA_R (*((volatile unsigned long *)0x400243FC))
+#define GPIO_PORTE_DIR_R (*((volatile unsigned long *)0x40024400))
+#define GPIO_PORTE_IS_R (*((volatile unsigned long *)0x40024404))
+#define GPIO_PORTE_IBE_R (*((volatile unsigned long *)0x40024408))
+#define GPIO_PORTE_IEV_R (*((volatile unsigned long *)0x4002440C))
+#define GPIO_PORTE_IM_R (*((volatile unsigned long *)0x40024410))
+#define GPIO_PORTE_RIS_R (*((volatile unsigned long *)0x40024414))
+#define GPIO_PORTE_MIS_R (*((volatile unsigned long *)0x40024418))
+#define GPIO_PORTE_ICR_R (*((volatile unsigned long *)0x4002441C))
+#define GPIO_PORTE_AFSEL_R (*((volatile unsigned long *)0x40024420))
+#define GPIO_PORTE_DR2R_R (*((volatile unsigned long *)0x40024500))
+#define GPIO_PORTE_DR4R_R (*((volatile unsigned long *)0x40024504))
+#define GPIO_PORTE_DR8R_R (*((volatile unsigned long *)0x40024508))
+#define GPIO_PORTE_ODR_R (*((volatile unsigned long *)0x4002450C))
+#define GPIO_PORTE_PUR_R (*((volatile unsigned long *)0x40024510))
+#define GPIO_PORTE_PDR_R (*((volatile unsigned long *)0x40024514))
+#define GPIO_PORTE_SLR_R (*((volatile unsigned long *)0x40024518))
+#define GPIO_PORTE_DEN_R (*((volatile unsigned long *)0x4002451C))
+#define GPIO_PORTE_LOCK_R (*((volatile unsigned long *)0x40024520))
+#define GPIO_PORTE_CR_R (*((volatile unsigned long *)0x40024524))
+
+//*****************************************************************************
+//
+// General-Purpose Input/Outputs (PORTF)
+//
+//*****************************************************************************
+#define GPIO_PORTF_DATA_BITS_R ((volatile unsigned long *)0x40025000)
+#define GPIO_PORTF_DATA_R (*((volatile unsigned long *)0x400253FC))
+#define GPIO_PORTF_DIR_R (*((volatile unsigned long *)0x40025400))
+#define GPIO_PORTF_IS_R (*((volatile unsigned long *)0x40025404))
+#define GPIO_PORTF_IBE_R (*((volatile unsigned long *)0x40025408))
+#define GPIO_PORTF_IEV_R (*((volatile unsigned long *)0x4002540C))
+#define GPIO_PORTF_IM_R (*((volatile unsigned long *)0x40025410))
+#define GPIO_PORTF_RIS_R (*((volatile unsigned long *)0x40025414))
+#define GPIO_PORTF_MIS_R (*((volatile unsigned long *)0x40025418))
+#define GPIO_PORTF_ICR_R (*((volatile unsigned long *)0x4002541C))
+#define GPIO_PORTF_AFSEL_R (*((volatile unsigned long *)0x40025420))
+#define GPIO_PORTF_DR2R_R (*((volatile unsigned long *)0x40025500))
+#define GPIO_PORTF_DR4R_R (*((volatile unsigned long *)0x40025504))
+#define GPIO_PORTF_DR8R_R (*((volatile unsigned long *)0x40025508))
+#define GPIO_PORTF_ODR_R (*((volatile unsigned long *)0x4002550C))
+#define GPIO_PORTF_PUR_R (*((volatile unsigned long *)0x40025510))
+#define GPIO_PORTF_PDR_R (*((volatile unsigned long *)0x40025514))
+#define GPIO_PORTF_SLR_R (*((volatile unsigned long *)0x40025518))
+#define GPIO_PORTF_DEN_R (*((volatile unsigned long *)0x4002551C))
+#define GPIO_PORTF_LOCK_R (*((volatile unsigned long *)0x40025520))
+#define GPIO_PORTF_CR_R (*((volatile unsigned long *)0x40025524))
+
+//*****************************************************************************
+//
+// General-Purpose Input/Outputs (PORTG)
+//
+//*****************************************************************************
+#define GPIO_PORTG_DATA_BITS_R ((volatile unsigned long *)0x40026000)
+#define GPIO_PORTG_DATA_R (*((volatile unsigned long *)0x400263FC))
+#define GPIO_PORTG_DIR_R (*((volatile unsigned long *)0x40026400))
+#define GPIO_PORTG_IS_R (*((volatile unsigned long *)0x40026404))
+#define GPIO_PORTG_IBE_R (*((volatile unsigned long *)0x40026408))
+#define GPIO_PORTG_IEV_R (*((volatile unsigned long *)0x4002640C))
+#define GPIO_PORTG_IM_R (*((volatile unsigned long *)0x40026410))
+#define GPIO_PORTG_RIS_R (*((volatile unsigned long *)0x40026414))
+#define GPIO_PORTG_MIS_R (*((volatile unsigned long *)0x40026418))
+#define GPIO_PORTG_ICR_R (*((volatile unsigned long *)0x4002641C))
+#define GPIO_PORTG_AFSEL_R (*((volatile unsigned long *)0x40026420))
+#define GPIO_PORTG_DR2R_R (*((volatile unsigned long *)0x40026500))
+#define GPIO_PORTG_DR4R_R (*((volatile unsigned long *)0x40026504))
+#define GPIO_PORTG_DR8R_R (*((volatile unsigned long *)0x40026508))
+#define GPIO_PORTG_ODR_R (*((volatile unsigned long *)0x4002650C))
+#define GPIO_PORTG_PUR_R (*((volatile unsigned long *)0x40026510))
+#define GPIO_PORTG_PDR_R (*((volatile unsigned long *)0x40026514))
+#define GPIO_PORTG_SLR_R (*((volatile unsigned long *)0x40026518))
+#define GPIO_PORTG_DEN_R (*((volatile unsigned long *)0x4002651C))
+#define GPIO_PORTG_LOCK_R (*((volatile unsigned long *)0x40026520))
+#define GPIO_PORTG_CR_R (*((volatile unsigned long *)0x40026524))
+
+//*****************************************************************************
+//
+// Pulse Width Modulator (PWM)
+//
+//*****************************************************************************
+#define PWM_CTL_R (*((volatile unsigned long *)0x40028000))
+#define PWM_SYNC_R (*((volatile unsigned long *)0x40028004))
+#define PWM_ENABLE_R (*((volatile unsigned long *)0x40028008))
+#define PWM_INVERT_R (*((volatile unsigned long *)0x4002800C))
+#define PWM_FAULT_R (*((volatile unsigned long *)0x40028010))
+#define PWM_INTEN_R (*((volatile unsigned long *)0x40028014))
+#define PWM_RIS_R (*((volatile unsigned long *)0x40028018))
+#define PWM_ISC_R (*((volatile unsigned long *)0x4002801C))
+#define PWM_STATUS_R (*((volatile unsigned long *)0x40028020))
+#define PWM_0_CTL_R (*((volatile unsigned long *)0x40028040))
+#define PWM_0_INTEN_R (*((volatile unsigned long *)0x40028044))
+#define PWM_0_RIS_R (*((volatile unsigned long *)0x40028048))
+#define PWM_0_ISC_R (*((volatile unsigned long *)0x4002804C))
+#define PWM_0_LOAD_R (*((volatile unsigned long *)0x40028050))
+#define PWM_0_COUNT_R (*((volatile unsigned long *)0x40028054))
+#define PWM_0_CMPA_R (*((volatile unsigned long *)0x40028058))
+#define PWM_0_CMPB_R (*((volatile unsigned long *)0x4002805C))
+#define PWM_0_GENA_R (*((volatile unsigned long *)0x40028060))
+#define PWM_0_GENB_R (*((volatile unsigned long *)0x40028064))
+#define PWM_0_DBCTL_R (*((volatile unsigned long *)0x40028068))
+#define PWM_0_DBRISE_R (*((volatile unsigned long *)0x4002806C))
+#define PWM_0_DBFALL_R (*((volatile unsigned long *)0x40028070))
+#define PWM_1_CTL_R (*((volatile unsigned long *)0x40028080))
+#define PWM_1_INTEN_R (*((volatile unsigned long *)0x40028084))
+#define PWM_1_RIS_R (*((volatile unsigned long *)0x40028088))
+#define PWM_1_ISC_R (*((volatile unsigned long *)0x4002808C))
+#define PWM_1_LOAD_R (*((volatile unsigned long *)0x40028090))
+#define PWM_1_COUNT_R (*((volatile unsigned long *)0x40028094))
+#define PWM_1_CMPA_R (*((volatile unsigned long *)0x40028098))
+#define PWM_1_CMPB_R (*((volatile unsigned long *)0x4002809C))
+#define PWM_1_GENA_R (*((volatile unsigned long *)0x400280A0))
+#define PWM_1_GENB_R (*((volatile unsigned long *)0x400280A4))
+#define PWM_1_DBCTL_R (*((volatile unsigned long *)0x400280A8))
+#define PWM_1_DBRISE_R (*((volatile unsigned long *)0x400280AC))
+#define PWM_1_DBFALL_R (*((volatile unsigned long *)0x400280B0))
+#define PWM_2_CTL_R (*((volatile unsigned long *)0x400280C0))
+#define PWM_2_INTEN_R (*((volatile unsigned long *)0x400280C4))
+#define PWM_2_RIS_R (*((volatile unsigned long *)0x400280C8))
+#define PWM_2_ISC_R (*((volatile unsigned long *)0x400280CC))
+#define PWM_2_LOAD_R (*((volatile unsigned long *)0x400280D0))
+#define PWM_2_COUNT_R (*((volatile unsigned long *)0x400280D4))
+#define PWM_2_CMPA_R (*((volatile unsigned long *)0x400280D8))
+#define PWM_2_CMPB_R (*((volatile unsigned long *)0x400280DC))
+#define PWM_2_GENA_R (*((volatile unsigned long *)0x400280E0))
+#define PWM_2_GENB_R (*((volatile unsigned long *)0x400280E4))
+#define PWM_2_DBCTL_R (*((volatile unsigned long *)0x400280E8))
+#define PWM_2_DBRISE_R (*((volatile unsigned long *)0x400280EC))
+#define PWM_2_DBFALL_R (*((volatile unsigned long *)0x400280F0))
+
+//*****************************************************************************
+//
+// Quadrature Encoder Interface (QEI0)
+//
+//*****************************************************************************
+#define QEI0_CTL_R (*((volatile unsigned long *)0x4002C000))
+#define QEI0_STAT_R (*((volatile unsigned long *)0x4002C004))
+#define QEI0_POS_R (*((volatile unsigned long *)0x4002C008))
+#define QEI0_MAXPOS_R (*((volatile unsigned long *)0x4002C00C))
+#define QEI0_LOAD_R (*((volatile unsigned long *)0x4002C010))
+#define QEI0_TIME_R (*((volatile unsigned long *)0x4002C014))
+#define QEI0_COUNT_R (*((volatile unsigned long *)0x4002C018))
+#define QEI0_SPEED_R (*((volatile unsigned long *)0x4002C01C))
+#define QEI0_INTEN_R (*((volatile unsigned long *)0x4002C020))
+#define QEI0_RIS_R (*((volatile unsigned long *)0x4002C024))
+#define QEI0_ISC_R (*((volatile unsigned long *)0x4002C028))
+
+//*****************************************************************************
+//
+// Quadrature Encoder Interface (QEI1)
+//
+//*****************************************************************************
+#define QEI1_CTL_R (*((volatile unsigned long *)0x4002D000))
+#define QEI1_STAT_R (*((volatile unsigned long *)0x4002D004))
+#define QEI1_POS_R (*((volatile unsigned long *)0x4002D008))
+#define QEI1_MAXPOS_R (*((volatile unsigned long *)0x4002D00C))
+#define QEI1_LOAD_R (*((volatile unsigned long *)0x4002D010))
+#define QEI1_TIME_R (*((volatile unsigned long *)0x4002D014))
+#define QEI1_COUNT_R (*((volatile unsigned long *)0x4002D018))
+#define QEI1_SPEED_R (*((volatile unsigned long *)0x4002D01C))
+#define QEI1_INTEN_R (*((volatile unsigned long *)0x4002D020))
+#define QEI1_RIS_R (*((volatile unsigned long *)0x4002D024))
+#define QEI1_ISC_R (*((volatile unsigned long *)0x4002D028))
+
+//*****************************************************************************
+//
+// General-Purpose Timers (TIMER0)
+//
+//*****************************************************************************
+#define TIMER0_CFG_R (*((volatile unsigned long *)0x40030000))
+#define TIMER0_TAMR_R (*((volatile unsigned long *)0x40030004))
+#define TIMER0_TBMR_R (*((volatile unsigned long *)0x40030008))
+#define TIMER0_CTL_R (*((volatile unsigned long *)0x4003000C))
+#define TIMER0_IMR_R (*((volatile unsigned long *)0x40030018))
+#define TIMER0_RIS_R (*((volatile unsigned long *)0x4003001C))
+#define TIMER0_MIS_R (*((volatile unsigned long *)0x40030020))
+#define TIMER0_ICR_R (*((volatile unsigned long *)0x40030024))
+#define TIMER0_TAILR_R (*((volatile unsigned long *)0x40030028))
+#define TIMER0_TBILR_R (*((volatile unsigned long *)0x4003002C))
+#define TIMER0_TAMATCHR_R (*((volatile unsigned long *)0x40030030))
+#define TIMER0_TBMATCHR_R (*((volatile unsigned long *)0x40030034))
+#define TIMER0_TAPR_R (*((volatile unsigned long *)0x40030038))
+#define TIMER0_TBPR_R (*((volatile unsigned long *)0x4003003C))
+#define TIMER0_TAPMR_R (*((volatile unsigned long *)0x40030040))
+#define TIMER0_TBPMR_R (*((volatile unsigned long *)0x40030044))
+#define TIMER0_TAR_R (*((volatile unsigned long *)0x40030048))
+#define TIMER0_TBR_R (*((volatile unsigned long *)0x4003004C))
+
+//*****************************************************************************
+//
+// General-Purpose Timers (TIMER1)
+//
+//*****************************************************************************
+#define TIMER1_CFG_R (*((volatile unsigned long *)0x40031000))
+#define TIMER1_TAMR_R (*((volatile unsigned long *)0x40031004))
+#define TIMER1_TBMR_R (*((volatile unsigned long *)0x40031008))
+#define TIMER1_CTL_R (*((volatile unsigned long *)0x4003100C))
+#define TIMER1_IMR_R (*((volatile unsigned long *)0x40031018))
+#define TIMER1_RIS_R (*((volatile unsigned long *)0x4003101C))
+#define TIMER1_MIS_R (*((volatile unsigned long *)0x40031020))
+#define TIMER1_ICR_R (*((volatile unsigned long *)0x40031024))
+#define TIMER1_TAILR_R (*((volatile unsigned long *)0x40031028))
+#define TIMER1_TBILR_R (*((volatile unsigned long *)0x4003102C))
+#define TIMER1_TAMATCHR_R (*((volatile unsigned long *)0x40031030))
+#define TIMER1_TBMATCHR_R (*((volatile unsigned long *)0x40031034))
+#define TIMER1_TAPR_R (*((volatile unsigned long *)0x40031038))
+#define TIMER1_TBPR_R (*((volatile unsigned long *)0x4003103C))
+#define TIMER1_TAPMR_R (*((volatile unsigned long *)0x40031040))
+#define TIMER1_TBPMR_R (*((volatile unsigned long *)0x40031044))
+#define TIMER1_TAR_R (*((volatile unsigned long *)0x40031048))
+#define TIMER1_TBR_R (*((volatile unsigned long *)0x4003104C))
+
+//*****************************************************************************
+//
+// General-Purpose Timers (TIMER2)
+//
+//*****************************************************************************
+#define TIMER2_CFG_R (*((volatile unsigned long *)0x40032000))
+#define TIMER2_TAMR_R (*((volatile unsigned long *)0x40032004))
+#define TIMER2_TBMR_R (*((volatile unsigned long *)0x40032008))
+#define TIMER2_CTL_R (*((volatile unsigned long *)0x4003200C))
+#define TIMER2_IMR_R (*((volatile unsigned long *)0x40032018))
+#define TIMER2_RIS_R (*((volatile unsigned long *)0x4003201C))
+#define TIMER2_MIS_R (*((volatile unsigned long *)0x40032020))
+#define TIMER2_ICR_R (*((volatile unsigned long *)0x40032024))
+#define TIMER2_TAILR_R (*((volatile unsigned long *)0x40032028))
+#define TIMER2_TBILR_R (*((volatile unsigned long *)0x4003202C))
+#define TIMER2_TAMATCHR_R (*((volatile unsigned long *)0x40032030))
+#define TIMER2_TBMATCHR_R (*((volatile unsigned long *)0x40032034))
+#define TIMER2_TAPR_R (*((volatile unsigned long *)0x40032038))
+#define TIMER2_TBPR_R (*((volatile unsigned long *)0x4003203C))
+#define TIMER2_TAPMR_R (*((volatile unsigned long *)0x40032040))
+#define TIMER2_TBPMR_R (*((volatile unsigned long *)0x40032044))
+#define TIMER2_TAR_R (*((volatile unsigned long *)0x40032048))
+#define TIMER2_TBR_R (*((volatile unsigned long *)0x4003204C))
+
+//*****************************************************************************
+//
+// General-Purpose Timers (TIMER3)
+//
+//*****************************************************************************
+#define TIMER3_CFG_R (*((volatile unsigned long *)0x40033000))
+#define TIMER3_TAMR_R (*((volatile unsigned long *)0x40033004))
+#define TIMER3_TBMR_R (*((volatile unsigned long *)0x40033008))
+#define TIMER3_CTL_R (*((volatile unsigned long *)0x4003300C))
+#define TIMER3_IMR_R (*((volatile unsigned long *)0x40033018))
+#define TIMER3_RIS_R (*((volatile unsigned long *)0x4003301C))
+#define TIMER3_MIS_R (*((volatile unsigned long *)0x40033020))
+#define TIMER3_ICR_R (*((volatile unsigned long *)0x40033024))
+#define TIMER3_TAILR_R (*((volatile unsigned long *)0x40033028))
+#define TIMER3_TBILR_R (*((volatile unsigned long *)0x4003302C))
+#define TIMER3_TAMATCHR_R (*((volatile unsigned long *)0x40033030))
+#define TIMER3_TBMATCHR_R (*((volatile unsigned long *)0x40033034))
+#define TIMER3_TAPR_R (*((volatile unsigned long *)0x40033038))
+#define TIMER3_TBPR_R (*((volatile unsigned long *)0x4003303C))
+#define TIMER3_TAPMR_R (*((volatile unsigned long *)0x40033040))
+#define TIMER3_TBPMR_R (*((volatile unsigned long *)0x40033044))
+#define TIMER3_TAR_R (*((volatile unsigned long *)0x40033048))
+#define TIMER3_TBR_R (*((volatile unsigned long *)0x4003304C))
+
+//*****************************************************************************
+//
+// Analog-to-Digital Converter (ADC)
+//
+//*****************************************************************************
+#define ADC_ACTSS_R (*((volatile unsigned long *)0x40038000))
+#define ADC_RIS_R (*((volatile unsigned long *)0x40038004))
+#define ADC_IM_R (*((volatile unsigned long *)0x40038008))
+#define ADC_ISC_R (*((volatile unsigned long *)0x4003800C))
+#define ADC_OSTAT_R (*((volatile unsigned long *)0x40038010))
+#define ADC_EMUX_R (*((volatile unsigned long *)0x40038014))
+#define ADC_USTAT_R (*((volatile unsigned long *)0x40038018))
+#define ADC_SSPRI_R (*((volatile unsigned long *)0x40038020))
+#define ADC_PSSI_R (*((volatile unsigned long *)0x40038028))
+#define ADC_SAC_R (*((volatile unsigned long *)0x40038030))
+#define ADC_SSMUX0_R (*((volatile unsigned long *)0x40038040))
+#define ADC_SSCTL0_R (*((volatile unsigned long *)0x40038044))
+#define ADC_SSFIFO0_R (*((volatile unsigned long *)0x40038048))
+#define ADC_SSFSTAT0_R (*((volatile unsigned long *)0x4003804C))
+#define ADC_SSMUX1_R (*((volatile unsigned long *)0x40038060))
+#define ADC_SSCTL1_R (*((volatile unsigned long *)0x40038064))
+#define ADC_SSFIFO1_R (*((volatile unsigned long *)0x40038068))
+#define ADC_SSFSTAT1_R (*((volatile unsigned long *)0x4003806C))
+#define ADC_SSMUX2_R (*((volatile unsigned long *)0x40038080))
+#define ADC_SSCTL2_R (*((volatile unsigned long *)0x40038084))
+#define ADC_SSFIFO2_R (*((volatile unsigned long *)0x40038088))
+#define ADC_SSFSTAT2_R (*((volatile unsigned long *)0x4003808C))
+#define ADC_SSMUX3_R (*((volatile unsigned long *)0x400380A0))
+#define ADC_SSCTL3_R (*((volatile unsigned long *)0x400380A4))
+#define ADC_SSFIFO3_R (*((volatile unsigned long *)0x400380A8))
+#define ADC_SSFSTAT3_R (*((volatile unsigned long *)0x400380AC))
+#define ADC_TMLB_R (*((volatile unsigned long *)0x40038100))
+
+//*****************************************************************************
+//
+// Analog Comparators (COMP)
+//
+//*****************************************************************************
+#define COMP_ACMIS_R (*((volatile unsigned long *)0x4003C000))
+#define COMP_ACRIS_R (*((volatile unsigned long *)0x4003C004))
+#define COMP_ACINTEN_R (*((volatile unsigned long *)0x4003C008))
+#define COMP_ACREFCTL_R (*((volatile unsigned long *)0x4003C010))
+#define COMP_ACSTAT0_R (*((volatile unsigned long *)0x4003C020))
+#define COMP_ACCTL0_R (*((volatile unsigned long *)0x4003C024))
+#define COMP_ACSTAT1_R (*((volatile unsigned long *)0x4003C040))
+#define COMP_ACCTL1_R (*((volatile unsigned long *)0x4003C044))
+
+//*****************************************************************************
+//
+// Ethernet Controller (MAC)
+//
+//*****************************************************************************
+#define MAC_MR0_R (*((volatile unsigned long *)0x40048000))
+#define MAC_RIS_R (*((volatile unsigned long *)0x40048000))
+#define MAC_IACK_R (*((volatile unsigned long *)0x40048000))
+#define MAC_MR1_R (*((volatile unsigned long *)0x40048001))
+#define MAC_MR2_R (*((volatile unsigned long *)0x40048002))
+#define MAC_MR3_R (*((volatile unsigned long *)0x40048003))
+#define MAC_IM_R (*((volatile unsigned long *)0x40048004))
+#define MAC_MR4_R (*((volatile unsigned long *)0x40048004))
+#define MAC_MR5_R (*((volatile unsigned long *)0x40048005))
+#define MAC_MR6_R (*((volatile unsigned long *)0x40048006))
+#define MAC_RCTL_R (*((volatile unsigned long *)0x40048008))
+#define MAC_TCTL_R (*((volatile unsigned long *)0x4004800C))
+#define MAC_DATA_R (*((volatile unsigned long *)0x40048010))
+#define MAC_MR16_R (*((volatile unsigned long *)0x40048010))
+#define MAC_MR17_R (*((volatile unsigned long *)0x40048011))
+#define MAC_MR18_R (*((volatile unsigned long *)0x40048012))
+#define MAC_MR19_R (*((volatile unsigned long *)0x40048013))
+#define MAC_IA0_R (*((volatile unsigned long *)0x40048014))
+#define MAC_MR23_R (*((volatile unsigned long *)0x40048017))
+#define MAC_IA1_R (*((volatile unsigned long *)0x40048018))
+#define MAC_MR24_R (*((volatile unsigned long *)0x40048018))
+#define MAC_THR_R (*((volatile unsigned long *)0x4004801C))
+#define MAC_MCTL_R (*((volatile unsigned long *)0x40048020))
+#define MAC_MDV_R (*((volatile unsigned long *)0x40048024))
+#define MAC_MTXD_R (*((volatile unsigned long *)0x4004802C))
+#define MAC_MRXD_R (*((volatile unsigned long *)0x40048030))
+#define MAC_NP_R (*((volatile unsigned long *)0x40048034))
+#define MAC_TR_R (*((volatile unsigned long *)0x40048038))
+
+//*****************************************************************************
+//
+// Hibernation Module (HIB)
+//
+//*****************************************************************************
+#define HIB_RTCC_R (*((volatile unsigned long *)0x400FC000))
+#define HIB_RTCM0_R (*((volatile unsigned long *)0x400FC004))
+#define HIB_RTCM1_R (*((volatile unsigned long *)0x400FC008))
+#define HIB_RTCLD_R (*((volatile unsigned long *)0x400FC00C))
+#define HIB_CTL_R (*((volatile unsigned long *)0x400FC010))
+#define HIB_IM_R (*((volatile unsigned long *)0x400FC014))
+#define HIB_RIS_R (*((volatile unsigned long *)0x400FC018))
+#define HIB_MIS_R (*((volatile unsigned long *)0x400FC01C))
+#define HIB_IC_R (*((volatile unsigned long *)0x400FC020))
+#define HIB_RTCT_R (*((volatile unsigned long *)0x400FC024))
+#define HIB_DATA_R (*((volatile unsigned long *)0x400FC030))
+
+//*****************************************************************************
+//
+// Internal Memory (FLASH)
+//
+//*****************************************************************************
+#define FLASH_FMA_R (*((volatile unsigned long *)0x400FD000))
+#define FLASH_FMD_R (*((volatile unsigned long *)0x400FD004))
+#define FLASH_FMC_R (*((volatile unsigned long *)0x400FD008))
+#define FLASH_FCRIS_R (*((volatile unsigned long *)0x400FD00C))
+#define FLASH_FCIM_R (*((volatile unsigned long *)0x400FD010))
+#define FLASH_FCMISC_R (*((volatile unsigned long *)0x400FD014))
+#define FLASH_USECRL_R (*((volatile unsigned long *)0x400FE140))
+#define FLASH_USERDBG_R (*((volatile unsigned long *)0x400FE1D0))
+#define FLASH_USERREG0_R (*((volatile unsigned long *)0x400FE1E0))
+#define FLASH_USERREG1_R (*((volatile unsigned long *)0x400FE1E4))
+#define FLASH_FMPRE0_R (*((volatile unsigned long *)0x400FE200))
+#define FLASH_FMPRE1_R (*((volatile unsigned long *)0x400FE204))
+#define FLASH_FMPRE2_R (*((volatile unsigned long *)0x400FE208))
+#define FLASH_FMPRE3_R (*((volatile unsigned long *)0x400FE20C))
+#define FLASH_FMPPE0_R (*((volatile unsigned long *)0x400FE400))
+#define FLASH_FMPPE1_R (*((volatile unsigned long *)0x400FE404))
+#define FLASH_FMPPE2_R (*((volatile unsigned long *)0x400FE408))
+#define FLASH_FMPPE3_R (*((volatile unsigned long *)0x400FE40C))
+
+//*****************************************************************************
+//
+// System Control (SYSCTL)
+//
+//*****************************************************************************
+#define SYSCTL_DID0_R (*((volatile unsigned long *)0x400FE000))
+#define SYSCTL_DID1_R (*((volatile unsigned long *)0x400FE004))
+#define SYSCTL_DC0_R (*((volatile unsigned long *)0x400FE008))
+#define SYSCTL_DC1_R (*((volatile unsigned long *)0x400FE010))
+#define SYSCTL_DC2_R (*((volatile unsigned long *)0x400FE014))
+#define SYSCTL_DC3_R (*((volatile unsigned long *)0x400FE018))
+#define SYSCTL_DC4_R (*((volatile unsigned long *)0x400FE01C))
+#define SYSCTL_PBORCTL_R (*((volatile unsigned long *)0x400FE030))
+#define SYSCTL_LDOPCTL_R (*((volatile unsigned long *)0x400FE034))
+#define SYSCTL_SRCR0_R (*((volatile unsigned long *)0x400FE040))
+#define SYSCTL_SRCR1_R (*((volatile unsigned long *)0x400FE044))
+#define SYSCTL_SRCR2_R (*((volatile unsigned long *)0x400FE048))
+#define SYSCTL_RIS_R (*((volatile unsigned long *)0x400FE050))
+#define SYSCTL_IMC_R (*((volatile unsigned long *)0x400FE054))
+#define SYSCTL_MISC_R (*((volatile unsigned long *)0x400FE058))
+#define SYSCTL_RESC_R (*((volatile unsigned long *)0x400FE05C))
+#define SYSCTL_RCC_R (*((volatile unsigned long *)0x400FE060))
+#define SYSCTL_PLLCFG_R (*((volatile unsigned long *)0x400FE064))
+#define SYSCTL_RCC2_R (*((volatile unsigned long *)0x400FE070))
+#define SYSCTL_RCGC0_R (*((volatile unsigned long *)0x400FE100))
+#define SYSCTL_RCGC1_R (*((volatile unsigned long *)0x400FE104))
+#define SYSCTL_RCGC2_R (*((volatile unsigned long *)0x400FE108))
+#define SYSCTL_SCGC0_R (*((volatile unsigned long *)0x400FE110))
+#define SYSCTL_SCGC1_R (*((volatile unsigned long *)0x400FE114))
+#define SYSCTL_SCGC2_R (*((volatile unsigned long *)0x400FE118))
+#define SYSCTL_DCGC0_R (*((volatile unsigned long *)0x400FE120))
+#define SYSCTL_DCGC1_R (*((volatile unsigned long *)0x400FE124))
+#define SYSCTL_DCGC2_R (*((volatile unsigned long *)0x400FE128))
+#define SYSCTL_DSLPCLKCFG_R (*((volatile unsigned long *)0x400FE144))
+
+//*****************************************************************************
+//
+// Nested Vectored Interrupt Ctrl (NVIC)
+//
+//*****************************************************************************
+#define NVIC_INT_TYPE_R (*((volatile unsigned long *)0xE000E004))
+#define NVIC_ST_CTRL_R (*((volatile unsigned long *)0xE000E010))
+#define NVIC_ST_RELOAD_R (*((volatile unsigned long *)0xE000E014))
+#define NVIC_ST_CURRENT_R (*((volatile unsigned long *)0xE000E018))
+#define NVIC_ST_CAL_R (*((volatile unsigned long *)0xE000E01C))
+#define NVIC_EN0_R (*((volatile unsigned long *)0xE000E100))
+#define NVIC_EN1_R (*((volatile unsigned long *)0xE000E104))
+#define NVIC_DIS0_R (*((volatile unsigned long *)0xE000E180))
+#define NVIC_DIS1_R (*((volatile unsigned long *)0xE000E184))
+#define NVIC_PEND0_R (*((volatile unsigned long *)0xE000E200))
+#define NVIC_PEND1_R (*((volatile unsigned long *)0xE000E204))
+#define NVIC_UNPEND0_R (*((volatile unsigned long *)0xE000E280))
+#define NVIC_UNPEND1_R (*((volatile unsigned long *)0xE000E284))
+#define NVIC_ACTIVE0_R (*((volatile unsigned long *)0xE000E300))
+#define NVIC_ACTIVE1_R (*((volatile unsigned long *)0xE000E304))
+#define NVIC_PRI0_R (*((volatile unsigned long *)0xE000E400))
+#define NVIC_PRI1_R (*((volatile unsigned long *)0xE000E404))
+#define NVIC_PRI2_R (*((volatile unsigned long *)0xE000E408))
+#define NVIC_PRI3_R (*((volatile unsigned long *)0xE000E40C))
+#define NVIC_PRI4_R (*((volatile unsigned long *)0xE000E410))
+#define NVIC_PRI5_R (*((volatile unsigned long *)0xE000E414))
+#define NVIC_PRI6_R (*((volatile unsigned long *)0xE000E418))
+#define NVIC_PRI7_R (*((volatile unsigned long *)0xE000E41C))
+#define NVIC_PRI8_R (*((volatile unsigned long *)0xE000E420))
+#define NVIC_PRI9_R (*((volatile unsigned long *)0xE000E424))
+#define NVIC_PRI10_R (*((volatile unsigned long *)0xE000E428))
+#define NVIC_CPUID_R (*((volatile unsigned long *)0xE000ED00))
+#define NVIC_INT_CTRL_R (*((volatile unsigned long *)0xE000ED04))
+#define NVIC_VTABLE_R (*((volatile unsigned long *)0xE000ED08))
+#define NVIC_APINT_R (*((volatile unsigned long *)0xE000ED0C))
+#define NVIC_SYS_CTRL_R (*((volatile unsigned long *)0xE000ED10))
+#define NVIC_CFG_CTRL_R (*((volatile unsigned long *)0xE000ED14))
+#define NVIC_SYS_PRI1_R (*((volatile unsigned long *)0xE000ED18))
+#define NVIC_SYS_PRI2_R (*((volatile unsigned long *)0xE000ED1C))
+#define NVIC_SYS_PRI3_R (*((volatile unsigned long *)0xE000ED20))
+#define NVIC_SYS_HND_CTRL_R (*((volatile unsigned long *)0xE000ED24))
+#define NVIC_FAULT_STAT_R (*((volatile unsigned long *)0xE000ED28))
+#define NVIC_HFAULT_STAT_R (*((volatile unsigned long *)0xE000ED2C))
+#define NVIC_DEBUG_STAT_R (*((volatile unsigned long *)0xE000ED30))
+#define NVIC_MM_ADDR_R (*((volatile unsigned long *)0xE000ED34))
+#define NVIC_FAULT_ADDR_R (*((volatile unsigned long *)0xE000ED38))
+#define NVIC_MPU_TYPE_R (*((volatile unsigned long *)0xE000ED90))
+#define NVIC_MPU_CTRL_R (*((volatile unsigned long *)0xE000ED94))
+#define NVIC_MPU_NUMBER_R (*((volatile unsigned long *)0xE000ED98))
+#define NVIC_MPU_R (*((volatile unsigned long *)0xE000ED9C))
+#define NVIC_MPU_ATTR_R (*((volatile unsigned long *)0xE000EDA0))
+#define NVIC_DBG_CTRL_R (*((volatile unsigned long *)0xE000EDF0))
+#define NVIC_DBG_XFER_R (*((volatile unsigned long *)0xE000EDF4))
+#define NVIC_DBG_DATA_R (*((volatile unsigned long *)0xE000EDF8))
+#define NVIC_DBG_INT_R (*((volatile unsigned long *)0xE000EDFC))
+#define NVIC_SW_TRIG_R (*((volatile unsigned long *)0xE000EF00))
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_LOAD register.
+//
+//*****************************************************************************
+#define WDT_LOAD_M 0xFFFFFFFF // Watchdog Load Value.
+#define WDT_LOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_VALUE register.
+//
+//*****************************************************************************
+#define WDT_VALUE_M 0xFFFFFFFF // Watchdog Value.
+#define WDT_VALUE_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_CTL register.
+//
+//*****************************************************************************
+#define WDT_CTL_RESEN 0x00000002 // Watchdog Reset Enable.
+#define WDT_CTL_INTEN 0x00000001 // Watchdog Interrupt Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_ICR register.
+//
+//*****************************************************************************
+#define WDT_ICR_M 0xFFFFFFFF // Watchdog Interrupt Clear.
+#define WDT_ICR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_RIS register.
+//
+//*****************************************************************************
+#define WDT_RIS_WDTRIS 0x00000001 // Watchdog Raw Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_MIS register.
+//
+//*****************************************************************************
+#define WDT_MIS_WDTMIS 0x00000001 // Watchdog Masked Interrupt
+ // Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_TEST register.
+//
+//*****************************************************************************
+#define WDT_TEST_STALL 0x00000100 // Watchdog Stall Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_LOCK register.
+//
+//*****************************************************************************
+#define WDT_LOCK_M 0xFFFFFFFF // Watchdog Lock.
+#define WDT_LOCK_UNLOCKED 0x00000000 // Unlocked
+#define WDT_LOCK_LOCKED 0x00000001 // Locked
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_LOCK register.
+//
+//*****************************************************************************
+#define GPIO_LOCK_M 0xFFFFFFFF // GPIO Lock.
+#define GPIO_LOCK_UNLOCKED 0x00000000 // unlocked
+#define GPIO_LOCK_LOCKED 0x00000001 // locked
+#define GPIO_LOCK_KEY 0x1ACCE551 // Unlocks the GPIO_CR register
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_CR0 register.
+//
+//*****************************************************************************
+#define SSI_CR0_SCR_M 0x0000FF00 // SSI Serial Clock Rate.
+#define SSI_CR0_SPH 0x00000080 // SSI Serial Clock Phase.
+#define SSI_CR0_SPO 0x00000040 // SSI Serial Clock Polarity.
+#define SSI_CR0_FRF_M 0x00000030 // SSI Frame Format Select.
+#define SSI_CR0_FRF_MOTO 0x00000000 // Freescale SPI Frame Format
+#define SSI_CR0_FRF_TI 0x00000010 // Texas Instruments Synchronous
+ // Serial Frame Format
+#define SSI_CR0_FRF_NMW 0x00000020 // MICROWIRE Frame Format
+#define SSI_CR0_DSS_M 0x0000000F // SSI Data Size Select.
+#define SSI_CR0_DSS_4 0x00000003 // 4-bit data
+#define SSI_CR0_DSS_5 0x00000004 // 5-bit data
+#define SSI_CR0_DSS_6 0x00000005 // 6-bit data
+#define SSI_CR0_DSS_7 0x00000006 // 7-bit data
+#define SSI_CR0_DSS_8 0x00000007 // 8-bit data
+#define SSI_CR0_DSS_9 0x00000008 // 9-bit data
+#define SSI_CR0_DSS_10 0x00000009 // 10-bit data
+#define SSI_CR0_DSS_11 0x0000000A // 11-bit data
+#define SSI_CR0_DSS_12 0x0000000B // 12-bit data
+#define SSI_CR0_DSS_13 0x0000000C // 13-bit data
+#define SSI_CR0_DSS_14 0x0000000D // 14-bit data
+#define SSI_CR0_DSS_15 0x0000000E // 15-bit data
+#define SSI_CR0_DSS_16 0x0000000F // 16-bit data
+#define SSI_CR0_SCR_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_CR1 register.
+//
+//*****************************************************************************
+#define SSI_CR1_SOD 0x00000008 // SSI Slave Mode Output Disable.
+#define SSI_CR1_MS 0x00000004 // SSI Master/Slave Select.
+#define SSI_CR1_SSE 0x00000002 // SSI Synchronous Serial Port
+ // Enable.
+#define SSI_CR1_LBM 0x00000001 // SSI Loopback Mode.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_DR register.
+//
+//*****************************************************************************
+#define SSI_DR_DATA_M 0x0000FFFF // SSI Receive/Transmit Data.
+#define SSI_DR_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_SR register.
+//
+//*****************************************************************************
+#define SSI_SR_BSY 0x00000010 // SSI Busy Bit.
+#define SSI_SR_RFF 0x00000008 // SSI Receive FIFO Full.
+#define SSI_SR_RNE 0x00000004 // SSI Receive FIFO Not Empty.
+#define SSI_SR_TNF 0x00000002 // SSI Transmit FIFO Not Full.
+#define SSI_SR_TFE 0x00000001 // SSI Transmit FIFO Empty.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_CPSR register.
+//
+//*****************************************************************************
+#define SSI_CPSR_CPSDVSR_M 0x000000FF // SSI Clock Prescale Divisor.
+#define SSI_CPSR_CPSDVSR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_IM register.
+//
+//*****************************************************************************
+#define SSI_IM_TXIM 0x00000008 // SSI Transmit FIFO Interrupt
+ // Mask.
+#define SSI_IM_RXIM 0x00000004 // SSI Receive FIFO Interrupt Mask.
+#define SSI_IM_RTIM 0x00000002 // SSI Receive Time-Out Interrupt
+ // Mask.
+#define SSI_IM_RORIM 0x00000001 // SSI Receive Overrun Interrupt
+ // Mask.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_RIS register.
+//
+//*****************************************************************************
+#define SSI_RIS_TXRIS 0x00000008 // SSI Transmit FIFO Raw Interrupt
+ // Status.
+#define SSI_RIS_RXRIS 0x00000004 // SSI Receive FIFO Raw Interrupt
+ // Status.
+#define SSI_RIS_RTRIS 0x00000002 // SSI Receive Time-Out Raw
+ // Interrupt Status.
+#define SSI_RIS_RORRIS 0x00000001 // SSI Receive Overrun Raw
+ // Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_MIS register.
+//
+//*****************************************************************************
+#define SSI_MIS_TXMIS 0x00000008 // SSI Transmit FIFO Masked
+ // Interrupt Status.
+#define SSI_MIS_RXMIS 0x00000004 // SSI Receive FIFO Masked
+ // Interrupt Status.
+#define SSI_MIS_RTMIS 0x00000002 // SSI Receive Time-Out Masked
+ // Interrupt Status.
+#define SSI_MIS_RORMIS 0x00000001 // SSI Receive Overrun Masked
+ // Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_ICR register.
+//
+//*****************************************************************************
+#define SSI_ICR_RTIC 0x00000002 // SSI Receive Time-Out Interrupt
+ // Clear.
+#define SSI_ICR_RORIC 0x00000001 // SSI Receive Overrun Interrupt
+ // Clear.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_DR register.
+//
+//*****************************************************************************
+#define UART_DR_OE 0x00000800 // UART Overrun Error.
+#define UART_DR_BE 0x00000400 // UART Break Error.
+#define UART_DR_PE 0x00000200 // UART Parity Error.
+#define UART_DR_FE 0x00000100 // UART Framing Error.
+#define UART_DR_DATA_M 0x000000FF // Data Transmitted or Received.
+#define UART_DR_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_RSR register.
+//
+//*****************************************************************************
+#define UART_RSR_OE 0x00000008 // UART Overrun Error.
+#define UART_RSR_BE 0x00000004 // UART Break Error.
+#define UART_RSR_PE 0x00000002 // UART Parity Error.
+#define UART_RSR_FE 0x00000001 // UART Framing Error.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_ECR register.
+//
+//*****************************************************************************
+#define UART_ECR_DATA_M 0x000000FF // Error Clear.
+#define UART_ECR_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_FR register.
+//
+//*****************************************************************************
+#define UART_FR_TXFE 0x00000080 // UART Transmit FIFO Empty.
+#define UART_FR_RXFF 0x00000040 // UART Receive FIFO Full.
+#define UART_FR_TXFF 0x00000020 // UART Transmit FIFO Full.
+#define UART_FR_RXFE 0x00000010 // UART Receive FIFO Empty.
+#define UART_FR_BUSY 0x00000008 // UART Busy.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_ILPR register.
+//
+//*****************************************************************************
+#define UART_ILPR_ILPDVSR_M 0x000000FF // IrDA Low-Power Divisor.
+#define UART_ILPR_ILPDVSR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_IBRD register.
+//
+//*****************************************************************************
+#define UART_IBRD_DIVINT_M 0x0000FFFF // Integer Baud-Rate Divisor.
+#define UART_IBRD_DIVINT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_FBRD register.
+//
+//*****************************************************************************
+#define UART_FBRD_DIVFRAC_M 0x0000003F // Fractional Baud-Rate Divisor.
+#define UART_FBRD_DIVFRAC_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_LCRH register.
+//
+//*****************************************************************************
+#define UART_LCRH_SPS 0x00000080 // UART Stick Parity Select.
+#define UART_LCRH_WLEN_M 0x00000060 // UART Word Length.
+#define UART_LCRH_WLEN_5 0x00000000 // 5 bits (default)
+#define UART_LCRH_WLEN_6 0x00000020 // 6 bits
+#define UART_LCRH_WLEN_7 0x00000040 // 7 bits
+#define UART_LCRH_WLEN_8 0x00000060 // 8 bits
+#define UART_LCRH_FEN 0x00000010 // UART Enable FIFOs.
+#define UART_LCRH_STP2 0x00000008 // UART Two Stop Bits Select.
+#define UART_LCRH_EPS 0x00000004 // UART Even Parity Select.
+#define UART_LCRH_PEN 0x00000002 // UART Parity Enable.
+#define UART_LCRH_BRK 0x00000001 // UART Send Break.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_CTL register.
+//
+//*****************************************************************************
+#define UART_CTL_RXE 0x00000200 // UART Receive Enable.
+#define UART_CTL_TXE 0x00000100 // UART Transmit Enable.
+#define UART_CTL_LBE 0x00000080 // UART Loop Back Enable.
+#define UART_CTL_SIRLP 0x00000004 // UART SIR Low Power Mode.
+#define UART_CTL_SIREN 0x00000002 // UART SIR Enable.
+#define UART_CTL_UARTEN 0x00000001 // UART Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_IFLS register.
+//
+//*****************************************************************************
+#define UART_IFLS_RX_M 0x00000038 // UART Receive Interrupt FIFO
+ // Level Select.
+#define UART_IFLS_RX1_8 0x00000000 // RX FIFO <= 1/8 full
+#define UART_IFLS_RX2_8 0x00000008 // RX FIFO <= 1/4 full
+#define UART_IFLS_RX4_8 0x00000010 // RX FIFO <= 1/2 full (default)
+#define UART_IFLS_RX6_8 0x00000018 // RX FIFO <= 3/4 full
+#define UART_IFLS_RX7_8 0x00000020 // RX FIFO <= 7/8 full
+#define UART_IFLS_TX_M 0x00000007 // UART Transmit Interrupt FIFO
+ // Level Select.
+#define UART_IFLS_TX1_8 0x00000000 // TX FIFO >= 1/8 full
+#define UART_IFLS_TX2_8 0x00000001 // TX FIFO >= 1/4 full
+#define UART_IFLS_TX4_8 0x00000002 // TX FIFO >= 1/2 full (default)
+#define UART_IFLS_TX6_8 0x00000003 // TX FIFO >= 3/4 full
+#define UART_IFLS_TX7_8 0x00000004 // TX FIFO >= 7/8 full
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_IM register.
+//
+//*****************************************************************************
+#define UART_IM_OEIM 0x00000400 // UART Overrun Error Interrupt
+ // Mask.
+#define UART_IM_BEIM 0x00000200 // UART Break Error Interrupt Mask.
+#define UART_IM_PEIM 0x00000100 // UART Parity Error Interrupt
+ // Mask.
+#define UART_IM_FEIM 0x00000080 // UART Framing Error Interrupt
+ // Mask.
+#define UART_IM_RTIM 0x00000040 // UART Receive Time-Out Interrupt
+ // Mask.
+#define UART_IM_TXIM 0x00000020 // UART Transmit Interrupt Mask.
+#define UART_IM_RXIM 0x00000010 // UART Receive Interrupt Mask.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_RIS register.
+//
+//*****************************************************************************
+#define UART_RIS_OERIS 0x00000400 // UART Overrun Error Raw Interrupt
+ // Status.
+#define UART_RIS_BERIS 0x00000200 // UART Break Error Raw Interrupt
+ // Status.
+#define UART_RIS_PERIS 0x00000100 // UART Parity Error Raw Interrupt
+ // Status.
+#define UART_RIS_FERIS 0x00000080 // UART Framing Error Raw Interrupt
+ // Status.
+#define UART_RIS_RTRIS 0x00000040 // UART Receive Time-Out Raw
+ // Interrupt Status.
+#define UART_RIS_TXRIS 0x00000020 // UART Transmit Raw Interrupt
+ // Status.
+#define UART_RIS_RXRIS 0x00000010 // UART Receive Raw Interrupt
+ // Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_MIS register.
+//
+//*****************************************************************************
+#define UART_MIS_OEMIS 0x00000400 // UART Overrun Error Masked
+ // Interrupt Status.
+#define UART_MIS_BEMIS 0x00000200 // UART Break Error Masked
+ // Interrupt Status.
+#define UART_MIS_PEMIS 0x00000100 // UART Parity Error Masked
+ // Interrupt Status.
+#define UART_MIS_FEMIS 0x00000080 // UART Framing Error Masked
+ // Interrupt Status.
+#define UART_MIS_RTMIS 0x00000040 // UART Receive Time-Out Masked
+ // Interrupt Status.
+#define UART_MIS_TXMIS 0x00000020 // UART Transmit Masked Interrupt
+ // Status.
+#define UART_MIS_RXMIS 0x00000010 // UART Receive Masked Interrupt
+ // Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_ICR register.
+//
+//*****************************************************************************
+#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear.
+#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear.
+#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear.
+#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear.
+#define UART_ICR_RTIC 0x00000040 // Receive Time-Out Interrupt
+ // Clear.
+#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear.
+#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MSA register.
+//
+//*****************************************************************************
+#define I2C_MSA_SA_M 0x000000FE // I2C Slave Address.
+#define I2C_MSA_RS 0x00000001 // Receive not send.
+#define I2C_MSA_SA_S 1
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SOAR register.
+//
+//*****************************************************************************
+#define I2C_SOAR_OAR_M 0x0000007F // I2C Slave Own Address.
+#define I2C_SOAR_OAR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SCSR register.
+//
+//*****************************************************************************
+#define I2C_SCSR_FBR 0x00000004 // First Byte Received.
+#define I2C_SCSR_TREQ 0x00000002 // Transmit Request.
+#define I2C_SCSR_DA 0x00000001 // Device Active.
+#define I2C_SCSR_RREQ 0x00000001 // Receive Request.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MCS register.
+//
+//*****************************************************************************
+#define I2C_MCS_BUSBSY 0x00000040 // Bus Busy.
+#define I2C_MCS_IDLE 0x00000020 // I2C Idle.
+#define I2C_MCS_ARBLST 0x00000010 // Arbitration Lost.
+#define I2C_MCS_ACK 0x00000008 // Data Acknowledge Enable.
+#define I2C_MCS_DATACK 0x00000008 // Acknowledge Data.
+#define I2C_MCS_ADRACK 0x00000004 // Acknowledge Address.
+#define I2C_MCS_STOP 0x00000004 // Generate STOP.
+#define I2C_MCS_START 0x00000002 // Generate START.
+#define I2C_MCS_ERROR 0x00000002 // Error.
+#define I2C_MCS_RUN 0x00000001 // I2C Master Enable.
+#define I2C_MCS_BUSY 0x00000001 // I2C Busy.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SDR register.
+//
+//*****************************************************************************
+#define I2C_SDR_DATA_M 0x000000FF // Data for Transfer.
+#define I2C_SDR_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MDR register.
+//
+//*****************************************************************************
+#define I2C_MDR_DATA_M 0x000000FF // Data Transferred.
+#define I2C_MDR_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MTPR register.
+//
+//*****************************************************************************
+#define I2C_MTPR_TPR_M 0x000000FF // SCL Clock Period.
+#define I2C_MTPR_TPR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SIMR register.
+//
+//*****************************************************************************
+#define I2C_SIMR_IM 0x00000001 // Data Interrupt Mask.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SRIS register.
+//
+//*****************************************************************************
+#define I2C_SRIS_RIS 0x00000001 // Data Raw Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MIMR register.
+//
+//*****************************************************************************
+#define I2C_MIMR_IM 0x00000001 // Interrupt Mask.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MRIS register.
+//
+//*****************************************************************************
+#define I2C_MRIS_RIS 0x00000001 // Raw Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SMIS register.
+//
+//*****************************************************************************
+#define I2C_SMIS_MIS 0x00000001 // Data Masked Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SICR register.
+//
+//*****************************************************************************
+#define I2C_SICR_IC 0x00000001 // Data Interrupt Clear.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MMIS register.
+//
+//*****************************************************************************
+#define I2C_MMIS_MIS 0x00000001 // Masked Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MICR register.
+//
+//*****************************************************************************
+#define I2C_MICR_IC 0x00000001 // Interrupt Clear.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MCR register.
+//
+//*****************************************************************************
+#define I2C_MCR_SFE 0x00000020 // I2C Slave Function Enable.
+#define I2C_MCR_MFE 0x00000010 // I2C Master Function Enable.
+#define I2C_MCR_LPBK 0x00000001 // I2C Loopback.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_CTL register.
+//
+//*****************************************************************************
+#define PWM_CTL_GLOBALSYNC2 0x00000004 // Update PWM Generator 2.
+#define PWM_CTL_GLOBALSYNC1 0x00000002 // Update PWM Generator 1.
+#define PWM_CTL_GLOBALSYNC0 0x00000001 // Update PWM Generator 0.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_SYNC register.
+//
+//*****************************************************************************
+#define PWM_SYNC_SYNC2 0x00000004 // Reset Generator 2 Counter.
+#define PWM_SYNC_SYNC1 0x00000002 // Reset Generator 1 Counter.
+#define PWM_SYNC_SYNC0 0x00000001 // Reset Generator 0 Counter.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_ENABLE register.
+//
+//*****************************************************************************
+#define PWM_ENABLE_PWM5EN 0x00000020 // PWM5 Output Enable.
+#define PWM_ENABLE_PWM4EN 0x00000010 // PWM4 Output Enable.
+#define PWM_ENABLE_PWM3EN 0x00000008 // PWM3 Output Enable.
+#define PWM_ENABLE_PWM2EN 0x00000004 // PWM2 Output Enable.
+#define PWM_ENABLE_PWM1EN 0x00000002 // PWM1 Output Enable.
+#define PWM_ENABLE_PWM0EN 0x00000001 // PWM0 Output Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_INVERT register.
+//
+//*****************************************************************************
+#define PWM_INVERT_PWM5INV 0x00000020 // Invert PWM5 Signal.
+#define PWM_INVERT_PWM4INV 0x00000010 // Invert PWM4 Signal.
+#define PWM_INVERT_PWM3INV 0x00000008 // Invert PWM3 Signal.
+#define PWM_INVERT_PWM2INV 0x00000004 // Invert PWM2 Signal.
+#define PWM_INVERT_PWM1INV 0x00000002 // Invert PWM1 Signal.
+#define PWM_INVERT_PWM0INV 0x00000001 // Invert PWM0 Signal.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_FAULT register.
+//
+//*****************************************************************************
+#define PWM_FAULT_FAULT5 0x00000020 // PWM5 Fault.
+#define PWM_FAULT_FAULT4 0x00000010 // PWM4 Fault.
+#define PWM_FAULT_FAULT3 0x00000008 // PWM3 Fault.
+#define PWM_FAULT_FAULT2 0x00000004 // PWM2 Fault.
+#define PWM_FAULT_FAULT1 0x00000002 // PWM1 Fault.
+#define PWM_FAULT_FAULT0 0x00000001 // PWM0 Fault.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_INTEN register.
+//
+//*****************************************************************************
+#define PWM_INTEN_INTFAULT 0x00010000 // Fault Interrupt Enable.
+#define PWM_INTEN_INTPWM2 0x00000004 // PWM2 Interrupt Enable.
+#define PWM_INTEN_INTPWM1 0x00000002 // PWM1 Interrupt Enable.
+#define PWM_INTEN_INTPWM0 0x00000001 // PWM0 Interrupt Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_RIS register.
+//
+//*****************************************************************************
+#define PWM_RIS_INTFAULT 0x00010000 // Fault Interrupt Asserted.
+#define PWM_RIS_INTPWM2 0x00000004 // PWM2 Interrupt Asserted.
+#define PWM_RIS_INTPWM1 0x00000002 // PWM1 Interrupt Asserted.
+#define PWM_RIS_INTPWM0 0x00000001 // PWM0 Interrupt Asserted.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_ISC register.
+//
+//*****************************************************************************
+#define PWM_ISC_INTFAULT 0x00010000 // Fault Interrupt Asserted.
+#define PWM_ISC_INTPWM2 0x00000004 // PWM2 Interrupt Status.
+#define PWM_ISC_INTPWM1 0x00000002 // PWM1 Interrupt Status.
+#define PWM_ISC_INTPWM0 0x00000001 // PWM0 Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_STATUS register.
+//
+//*****************************************************************************
+#define PWM_STATUS_FAULT 0x00000001 // Fault Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_CTL,
+// PWM_O_1_CTL, and PWM_O_2_CTL registers.
+//
+//*****************************************************************************
+#define PWM_X_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode.
+#define PWM_X_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode.
+#define PWM_X_CTL_LOADUPD 0x00000008 // Load Register Update Mode.
+#define PWM_X_CTL_DEBUG 0x00000004 // Debug Mode.
+#define PWM_X_CTL_MODE 0x00000002 // Counter Mode.
+#define PWM_X_CTL_ENABLE 0x00000001 // PWM Block Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_INTEN,
+// PWM_O_1_INTEN, and PWM_O_2_INTEN registers.
+//
+//*****************************************************************************
+#define PWM_X_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=Comparator B
+ // Down.
+#define PWM_X_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=Comparator B
+ // Up.
+#define PWM_X_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=Comparator A
+ // Down.
+#define PWM_X_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=Comparator A
+ // Up.
+#define PWM_X_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=Load.
+#define PWM_X_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0.
+#define PWM_X_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=Comparator
+ // B Down.
+#define PWM_X_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=Comparator
+ // B Up.
+#define PWM_X_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=Comparator
+ // A Down.
+#define PWM_X_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=Comparator
+ // A Up.
+#define PWM_X_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=Load.
+#define PWM_X_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_RIS,
+// PWM_O_1_RIS, and PWM_O_2_RIS registers.
+//
+//*****************************************************************************
+#define PWM_X_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt
+ // Status.
+#define PWM_X_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt
+ // Status.
+#define PWM_X_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt
+ // Status.
+#define PWM_X_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt
+ // Status.
+#define PWM_X_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status.
+#define PWM_X_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_ISC,
+// PWM_O_1_ISC, and PWM_O_2_ISC registers.
+//
+//*****************************************************************************
+#define PWM_X_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt.
+#define PWM_X_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt.
+#define PWM_X_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt.
+#define PWM_X_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt.
+#define PWM_X_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt.
+#define PWM_X_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_LOAD,
+// PWM_O_1_LOAD, and PWM_O_2_LOAD registers.
+//
+//*****************************************************************************
+#define PWM_X_LOAD_M 0x0000FFFF // Counter Load Value.
+#define PWM_X_LOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_COUNT,
+// PWM_O_1_COUNT, and PWM_O_2_COUNT registers.
+//
+//*****************************************************************************
+#define PWM_X_COUNT_M 0x0000FFFF // Counter Value.
+#define PWM_X_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_CMPA,
+// PWM_O_1_CMPA, and PWM_O_2_CMPA registers.
+//
+//*****************************************************************************
+#define PWM_X_CMPA_M 0x0000FFFF // Comparator A Value.
+#define PWM_X_CMPA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_CMPB,
+// PWM_O_1_CMPB, and PWM_O_2_CMPB registers.
+//
+//*****************************************************************************
+#define PWM_X_CMPB_M 0x0000FFFF // Comparator B Value.
+#define PWM_X_CMPB_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_GENA,
+// PWM_O_1_GENA, and PWM_O_2_GENA registers.
+//
+//*****************************************************************************
+#define PWM_X_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down.
+#define PWM_X_GENA_ACTCMPBD_NONE \
+ 0x00000000 // Do nothing.
+#define PWM_X_GENA_ACTCMPBD_INV 0x00000400 // Invert the output signal.
+#define PWM_X_GENA_ACTCMPBD_ZERO \
+ 0x00000800 // Set the output signal to 0.
+#define PWM_X_GENA_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1.
+#define PWM_X_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up.
+#define PWM_X_GENA_ACTCMPBU_NONE \
+ 0x00000000 // Do nothing.
+#define PWM_X_GENA_ACTCMPBU_INV 0x00000100 // Invert the output signal.
+#define PWM_X_GENA_ACTCMPBU_ZERO \
+ 0x00000200 // Set the output signal to 0.
+#define PWM_X_GENA_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1.
+#define PWM_X_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down.
+#define PWM_X_GENA_ACTCMPAD_NONE \
+ 0x00000000 // Do nothing.
+#define PWM_X_GENA_ACTCMPAD_INV 0x00000040 // Invert the output signal.
+#define PWM_X_GENA_ACTCMPAD_ZERO \
+ 0x00000080 // Set the output signal to 0.
+#define PWM_X_GENA_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1.
+#define PWM_X_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up.
+#define PWM_X_GENA_ACTCMPAU_NONE \
+ 0x00000000 // Do nothing.
+#define PWM_X_GENA_ACTCMPAU_INV 0x00000010 // Invert the output signal.
+#define PWM_X_GENA_ACTCMPAU_ZERO \
+ 0x00000020 // Set the output signal to 0.
+#define PWM_X_GENA_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1.
+#define PWM_X_GENA_ACTLOAD_M 0x0000000C // Action for Counter=Load.
+#define PWM_X_GENA_ACTLOAD_NONE 0x00000000 // Do nothing.
+#define PWM_X_GENA_ACTLOAD_INV 0x00000004 // Invert the output signal.
+#define PWM_X_GENA_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0.
+#define PWM_X_GENA_ACTLOAD_ONE 0x0000000C // Set the output signal to 1.
+#define PWM_X_GENA_ACTZERO_M 0x00000003 // Action for Counter=0.
+#define PWM_X_GENA_ACTZERO_NONE 0x00000000 // Do nothing.
+#define PWM_X_GENA_ACTZERO_INV 0x00000001 // Invert the output signal.
+#define PWM_X_GENA_ACTZERO_ZERO 0x00000002 // Set the output signal to 0.
+#define PWM_X_GENA_ACTZERO_ONE 0x00000003 // Set the output signal to 1.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_GENB,
+// PWM_O_1_GENB, and PWM_O_2_GENB registers.
+//
+//*****************************************************************************
+#define PWM_X_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down.
+#define PWM_X_GENB_ACTCMPBD_NONE \
+ 0x00000000 // Do nothing.
+#define PWM_X_GENB_ACTCMPBD_INV 0x00000400 // Invert the output signal.
+#define PWM_X_GENB_ACTCMPBD_ZERO \
+ 0x00000800 // Set the output signal to 0.
+#define PWM_X_GENB_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1.
+#define PWM_X_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up.
+#define PWM_X_GENB_ACTCMPBU_NONE \
+ 0x00000000 // Do nothing.
+#define PWM_X_GENB_ACTCMPBU_INV 0x00000100 // Invert the output signal.
+#define PWM_X_GENB_ACTCMPBU_ZERO \
+ 0x00000200 // Set the output signal to 0.
+#define PWM_X_GENB_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1.
+#define PWM_X_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down.
+#define PWM_X_GENB_ACTCMPAD_NONE \
+ 0x00000000 // Do nothing.
+#define PWM_X_GENB_ACTCMPAD_INV 0x00000040 // Invert the output signal.
+#define PWM_X_GENB_ACTCMPAD_ZERO \
+ 0x00000080 // Set the output signal to 0.
+#define PWM_X_GENB_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1.
+#define PWM_X_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up.
+#define PWM_X_GENB_ACTCMPAU_NONE \
+ 0x00000000 // Do nothing.
+#define PWM_X_GENB_ACTCMPAU_INV 0x00000010 // Invert the output signal.
+#define PWM_X_GENB_ACTCMPAU_ZERO \
+ 0x00000020 // Set the output signal to 0.
+#define PWM_X_GENB_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1.
+#define PWM_X_GENB_ACTLOAD_M 0x0000000C // Action for Counter=Load.
+#define PWM_X_GENB_ACTLOAD_NONE 0x00000000 // Do nothing.
+#define PWM_X_GENB_ACTLOAD_INV 0x00000004 // Invert the output signal.
+#define PWM_X_GENB_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0.
+#define PWM_X_GENB_ACTLOAD_ONE 0x0000000C // Set the output signal to 1.
+#define PWM_X_GENB_ACTZERO_M 0x00000003 // Action for Counter=0.
+#define PWM_X_GENB_ACTZERO_NONE 0x00000000 // Do nothing.
+#define PWM_X_GENB_ACTZERO_INV 0x00000001 // Invert the output signal.
+#define PWM_X_GENB_ACTZERO_ZERO 0x00000002 // Set the output signal to 0.
+#define PWM_X_GENB_ACTZERO_ONE 0x00000003 // Set the output signal to 1.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_DBCTL,
+// PWM_O_1_DBCTL, and PWM_O_2_DBCTL registers.
+//
+//*****************************************************************************
+#define PWM_X_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_DBRISE,
+// PWM_O_1_DBRISE, and PWM_O_2_DBRISE registers.
+//
+//*****************************************************************************
+#define PWM_X_DBRISE_DELAY_M 0x00000FFF // Dead-Band Rise Delay.
+#define PWM_X_DBRISE_DELAY_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_DBFALL,
+// PWM_O_1_DBFALL, and PWM_O_2_DBFALL registers.
+//
+//*****************************************************************************
+#define PWM_X_DBFALL_DELAY_M 0x00000FFF // Dead-Band Fall Delay.
+#define PWM_X_DBFALL_DELAY_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_CTL register.
+//
+//*****************************************************************************
+#define QEI_CTL_STALLEN 0x00001000 // Stall QEI.
+#define QEI_CTL_INVI 0x00000800 // Invert Index Pulse.
+#define QEI_CTL_INVB 0x00000400 // Invert PhB.
+#define QEI_CTL_INVA 0x00000200 // Invert PhA.
+#define QEI_CTL_VELDIV_M 0x000001C0 // Predivide Velocity.
+#define QEI_CTL_VELDIV_1 0x00000000 // /1
+#define QEI_CTL_VELDIV_2 0x00000040 // /2
+#define QEI_CTL_VELDIV_4 0x00000080 // /4
+#define QEI_CTL_VELDIV_8 0x000000C0 // /8
+#define QEI_CTL_VELDIV_16 0x00000100 // /16
+#define QEI_CTL_VELDIV_32 0x00000140 // /32
+#define QEI_CTL_VELDIV_64 0x00000180 // /64
+#define QEI_CTL_VELDIV_128 0x000001C0 // /128
+#define QEI_CTL_VELEN 0x00000020 // Capture Velocity.
+#define QEI_CTL_RESMODE 0x00000010 // Reset Mode.
+#define QEI_CTL_CAPMODE 0x00000008 // Capture Mode.
+#define QEI_CTL_SIGMODE 0x00000004 // Signal Mode.
+#define QEI_CTL_SWAP 0x00000002 // Swap Signals.
+#define QEI_CTL_ENABLE 0x00000001 // Enable QEI.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_STAT register.
+//
+//*****************************************************************************
+#define QEI_STAT_DIRECTION 0x00000002 // Direction of Rotation.
+#define QEI_STAT_ERROR 0x00000001 // Error Detected.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_POS register.
+//
+//*****************************************************************************
+#define QEI_POS_M 0xFFFFFFFF // Current Position Integrator
+ // Value.
+#define QEI_POS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_MAXPOS register.
+//
+//*****************************************************************************
+#define QEI_MAXPOS_M 0xFFFFFFFF // Maximum Position Integrator
+ // Value.
+#define QEI_MAXPOS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_LOAD register.
+//
+//*****************************************************************************
+#define QEI_LOAD_M 0xFFFFFFFF // Velocity Timer Load Value.
+#define QEI_LOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_TIME register.
+//
+//*****************************************************************************
+#define QEI_TIME_M 0xFFFFFFFF // Velocity Timer Current Value.
+#define QEI_TIME_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_COUNT register.
+//
+//*****************************************************************************
+#define QEI_COUNT_M 0xFFFFFFFF // Velocity Pulse Count.
+#define QEI_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_SPEED register.
+//
+//*****************************************************************************
+#define QEI_SPEED_M 0xFFFFFFFF // Velocity.
+#define QEI_SPEED_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_INTEN register.
+//
+//*****************************************************************************
+#define QEI_INTEN_ERROR 0x00000008 // Phase Error Interrupt Enable.
+#define QEI_INTEN_DIR 0x00000004 // Direction Change Interrupt
+ // Enable.
+#define QEI_INTEN_TIMER 0x00000002 // Timer Expires Interrupt Enable.
+#define QEI_INTEN_INDEX 0x00000001 // Index Pulse Detected Interrupt
+ // Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_RIS register.
+//
+//*****************************************************************************
+#define QEI_RIS_ERROR 0x00000008 // Phase Error Detected.
+#define QEI_RIS_DIR 0x00000004 // Direction Change Detected.
+#define QEI_RIS_TIMER 0x00000002 // Velocity Timer Expired.
+#define QEI_RIS_INDEX 0x00000001 // Index Pulse Asserted.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_ISC register.
+//
+//*****************************************************************************
+#define QEI_ISC_ERROR 0x00000008 // Phase Error Interrupt.
+#define QEI_ISC_DIR 0x00000004 // Direction Change Interrupt.
+#define QEI_ISC_TIMER 0x00000002 // Velocity Timer Expired
+ // Interrupt.
+#define QEI_ISC_INDEX 0x00000001 // Index Pulse Interrupt.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_CFG register.
+//
+//*****************************************************************************
+#define TIMER_CFG_M 0x00000007 // GPTM Configuration.
+#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32-bit timer configuration.
+#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32-bit real-time clock (RTC)
+ // counter configuration.
+#define TIMER_CFG_16_BIT 0x00000004 // 16-bit timer configuration,
+ // function is controlled by bits
+ // 1:0 of GPTMTAMR and GPTMTBMR.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAMR register.
+//
+//*****************************************************************************
+#define TIMER_TAMR_TAAMS 0x00000008 // GPTM TimerA Alternate Mode
+ // Select.
+#define TIMER_TAMR_TACMR 0x00000004 // GPTM TimerA Capture Mode.
+#define TIMER_TAMR_TAMR_M 0x00000003 // GPTM TimerA Mode.
+#define TIMER_TAMR_TAMR_1_SHOT 0x00000001 // One-Shot Timer mode
+#define TIMER_TAMR_TAMR_PERIOD 0x00000002 // Periodic Timer mode
+#define TIMER_TAMR_TAMR_CAP 0x00000003 // Capture mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBMR register.
+//
+//*****************************************************************************
+#define TIMER_TBMR_TBAMS 0x00000008 // GPTM TimerB Alternate Mode
+ // Select.
+#define TIMER_TBMR_TBCMR 0x00000004 // GPTM TimerB Capture Mode.
+#define TIMER_TBMR_TBMR_M 0x00000003 // GPTM TimerB Mode.
+#define TIMER_TBMR_TBMR_1_SHOT 0x00000001 // One-Shot Timer mode
+#define TIMER_TBMR_TBMR_PERIOD 0x00000002 // Periodic Timer mode
+#define TIMER_TBMR_TBMR_CAP 0x00000003 // Capture mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_CTL register.
+//
+//*****************************************************************************
+#define TIMER_CTL_TBPWML 0x00004000 // GPTM TimerB PWM Output Level.
+#define TIMER_CTL_TBOTE 0x00002000 // GPTM TimerB Output Trigger
+ // Enable.
+#define TIMER_CTL_TBEVENT_M 0x00000C00 // GPTM TimerB Event Mode.
+#define TIMER_CTL_TBEVENT_POS 0x00000000 // Positive edge
+#define TIMER_CTL_TBEVENT_NEG 0x00000400 // Negative edge
+#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // Both edges
+#define TIMER_CTL_TBSTALL 0x00000200 // GPTM TimerB Stall Enable.
+#define TIMER_CTL_TBEN 0x00000100 // GPTM TimerB Enable.
+#define TIMER_CTL_TAPWML 0x00000040 // GPTM TimerA PWM Output Level.
+#define TIMER_CTL_TAOTE 0x00000020 // GPTM TimerA Output Trigger
+ // Enable.
+#define TIMER_CTL_RTCEN 0x00000010 // GPTM RTC Enable.
+#define TIMER_CTL_TAEVENT_M 0x0000000C // GPTM TimerA Event Mode.
+#define TIMER_CTL_TAEVENT_POS 0x00000000 // Positive edge
+#define TIMER_CTL_TAEVENT_NEG 0x00000004 // Negative edge
+#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // Both edges
+#define TIMER_CTL_TASTALL 0x00000002 // GPTM TimerA Stall Enable.
+#define TIMER_CTL_TAEN 0x00000001 // GPTM TimerA Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_IMR register.
+//
+//*****************************************************************************
+#define TIMER_IMR_CBEIM 0x00000400 // GPTM CaptureB Event Interrupt
+ // Mask.
+#define TIMER_IMR_CBMIM 0x00000200 // GPTM CaptureB Match Interrupt
+ // Mask.
+#define TIMER_IMR_TBTOIM 0x00000100 // GPTM TimerB Time-Out Interrupt
+ // Mask.
+#define TIMER_IMR_RTCIM 0x00000008 // GPTM RTC Interrupt Mask.
+#define TIMER_IMR_CAEIM 0x00000004 // GPTM CaptureA Event Interrupt
+ // Mask.
+#define TIMER_IMR_CAMIM 0x00000002 // GPTM CaptureA Match Interrupt
+ // Mask.
+#define TIMER_IMR_TATOIM 0x00000001 // GPTM TimerA Time-Out Interrupt
+ // Mask.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_RIS register.
+//
+//*****************************************************************************
+#define TIMER_RIS_CBERIS 0x00000400 // GPTM CaptureB Event Raw
+ // Interrupt.
+#define TIMER_RIS_CBMRIS 0x00000200 // GPTM CaptureB Match Raw
+ // Interrupt.
+#define TIMER_RIS_TBTORIS 0x00000100 // GPTM TimerB Time-Out Raw
+ // Interrupt.
+#define TIMER_RIS_RTCRIS 0x00000008 // GPTM RTC Raw Interrupt.
+#define TIMER_RIS_CAERIS 0x00000004 // GPTM CaptureA Event Raw
+ // Interrupt.
+#define TIMER_RIS_CAMRIS 0x00000002 // GPTM CaptureA Match Raw
+ // Interrupt.
+#define TIMER_RIS_TATORIS 0x00000001 // GPTM TimerA Time-Out Raw
+ // Interrupt.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_MIS register.
+//
+//*****************************************************************************
+#define TIMER_MIS_CBEMIS 0x00000400 // GPTM CaptureB Event Masked
+ // Interrupt.
+#define TIMER_MIS_CBMMIS 0x00000200 // GPTM CaptureB Match Masked
+ // Interrupt.
+#define TIMER_MIS_TBTOMIS 0x00000100 // GPTM TimerB Time-Out Masked
+ // Interrupt.
+#define TIMER_MIS_RTCMIS 0x00000008 // GPTM RTC Masked Interrupt.
+#define TIMER_MIS_CAEMIS 0x00000004 // GPTM CaptureA Event Masked
+ // Interrupt.
+#define TIMER_MIS_CAMMIS 0x00000002 // GPTM CaptureA Match Masked
+ // Interrupt.
+#define TIMER_MIS_TATOMIS 0x00000001 // GPTM TimerA Time-Out Masked
+ // Interrupt.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_ICR register.
+//
+//*****************************************************************************
+#define TIMER_ICR_CBECINT 0x00000400 // GPTM CaptureB Event Interrupt
+ // Clear.
+#define TIMER_ICR_CBMCINT 0x00000200 // GPTM CaptureB Match Interrupt
+ // Clear.
+#define TIMER_ICR_TBTOCINT 0x00000100 // GPTM TimerB Time-Out Interrupt
+ // Clear.
+#define TIMER_ICR_RTCCINT 0x00000008 // GPTM RTC Interrupt Clear.
+#define TIMER_ICR_CAECINT 0x00000004 // GPTM CaptureA Event Interrupt
+ // Clear.
+#define TIMER_ICR_CAMCINT 0x00000002 // GPTM CaptureA Match Raw
+ // Interrupt.
+#define TIMER_ICR_TATOCINT 0x00000001 // GPTM TimerA Time-Out Raw
+ // Interrupt.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAILR register.
+//
+//*****************************************************************************
+#define TIMER_TAILR_TAILRH_M 0xFFFF0000 // GPTM TimerA Interval Load
+ // Register High.
+#define TIMER_TAILR_TAILRL_M 0x0000FFFF // GPTM TimerA Interval Load
+ // Register Low.
+#define TIMER_TAILR_TAILRH_S 16
+#define TIMER_TAILR_TAILRL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBILR register.
+//
+//*****************************************************************************
+#define TIMER_TBILR_TBILRL_M 0x0000FFFF // GPTM TimerB Interval Load
+ // Register.
+#define TIMER_TBILR_TBILRL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAMATCHR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TAMATCHR_TAMRH_M 0xFFFF0000 // GPTM TimerA Match Register High.
+#define TIMER_TAMATCHR_TAMRL_M 0x0000FFFF // GPTM TimerA Match Register Low.
+#define TIMER_TAMATCHR_TAMRH_S 16
+#define TIMER_TAMATCHR_TAMRL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBMATCHR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TBMATCHR_TBMRL_M 0x0000FFFF // GPTM TimerB Match Register Low.
+#define TIMER_TBMATCHR_TBMRL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAPR register.
+//
+//*****************************************************************************
+#define TIMER_TAPR_TAPSR_M 0x000000FF // GPTM TimerA Prescale.
+#define TIMER_TAPR_TAPSR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBPR register.
+//
+//*****************************************************************************
+#define TIMER_TBPR_TBPSR_M 0x000000FF // GPTM TimerB Prescale.
+#define TIMER_TBPR_TBPSR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAPMR register.
+//
+//*****************************************************************************
+#define TIMER_TAPMR_TAPSMR_M 0x000000FF // GPTM TimerA Prescale Match.
+#define TIMER_TAPMR_TAPSMR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBPMR register.
+//
+//*****************************************************************************
+#define TIMER_TBPMR_TBPSMR_M 0x000000FF // GPTM TimerB Prescale Match.
+#define TIMER_TBPMR_TBPSMR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAR register.
+//
+//*****************************************************************************
+#define TIMER_TAR_TARH_M 0xFFFF0000 // GPTM TimerA Register High.
+#define TIMER_TAR_TARL_M 0x0000FFFF // GPTM TimerA Register Low.
+#define TIMER_TAR_TARH_S 16
+#define TIMER_TAR_TARL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBR register.
+//
+//*****************************************************************************
+#define TIMER_TBR_TBRL_M 0x0000FFFF // GPTM TimerB.
+#define TIMER_TBR_TBRL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_ACTSS register.
+//
+//*****************************************************************************
+#define ADC_ACTSS_ASEN3 0x00000008 // ADC SS3 Enable.
+#define ADC_ACTSS_ASEN2 0x00000004 // ADC SS2 Enable.
+#define ADC_ACTSS_ASEN1 0x00000002 // ADC SS1 Enable.
+#define ADC_ACTSS_ASEN0 0x00000001 // ADC SS0 Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_RIS register.
+//
+//*****************************************************************************
+#define ADC_RIS_INR3 0x00000008 // SS3 Raw Interrupt Status.
+#define ADC_RIS_INR2 0x00000004 // SS2 Raw Interrupt Status.
+#define ADC_RIS_INR1 0x00000002 // SS1 Raw Interrupt Status.
+#define ADC_RIS_INR0 0x00000001 // SS0 Raw Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_IM register.
+//
+//*****************************************************************************
+#define ADC_IM_MASK3 0x00000008 // SS3 Interrupt Mask.
+#define ADC_IM_MASK2 0x00000004 // SS2 Interrupt Mask.
+#define ADC_IM_MASK1 0x00000002 // SS1 Interrupt Mask.
+#define ADC_IM_MASK0 0x00000001 // SS0 Interrupt Mask.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_ISC register.
+//
+//*****************************************************************************
+#define ADC_ISC_IN3 0x00000008 // SS3 Interrupt Status and Clear.
+#define ADC_ISC_IN2 0x00000004 // SS2 Interrupt Status and Clear.
+#define ADC_ISC_IN1 0x00000002 // SS1 Interrupt Status and Clear.
+#define ADC_ISC_IN0 0x00000001 // SS0 Interrupt Status and Clear.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_OSTAT register.
+//
+//*****************************************************************************
+#define ADC_OSTAT_OV3 0x00000008 // SS3 FIFO Overflow.
+#define ADC_OSTAT_OV2 0x00000004 // SS2 FIFO Overflow.
+#define ADC_OSTAT_OV1 0x00000002 // SS1 FIFO Overflow.
+#define ADC_OSTAT_OV0 0x00000001 // SS0 FIFO Overflow.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_EMUX register.
+//
+//*****************************************************************************
+#define ADC_EMUX_EM3_M 0x0000F000 // SS3 Trigger Select.
+#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Controller (default)
+#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog Comparator 0
+#define ADC_EMUX_EM3_COMP1 0x00002000 // Analog Comparator 1
+#define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External (GPIO PB4)
+#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer
+#define ADC_EMUX_EM3_PWM0 0x00006000 // PWM0
+#define ADC_EMUX_EM3_PWM1 0x00007000 // PWM1
+#define ADC_EMUX_EM3_PWM2 0x00008000 // PWM2
+#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always (continuously sample)
+#define ADC_EMUX_EM2_M 0x00000F00 // SS2 Trigger Select.
+#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Controller (default)
+#define ADC_EMUX_EM2_COMP0 0x00000100 // Analog Comparator 0
+#define ADC_EMUX_EM2_COMP1 0x00000200 // Analog Comparator 1
+#define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External (GPIO PB4)
+#define ADC_EMUX_EM2_TIMER 0x00000500 // Timer
+#define ADC_EMUX_EM2_PWM0 0x00000600 // PWM0
+#define ADC_EMUX_EM2_PWM1 0x00000700 // PWM1
+#define ADC_EMUX_EM2_PWM2 0x00000800 // PWM2
+#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always (continuously sample)
+#define ADC_EMUX_EM1_M 0x000000F0 // SS1 Trigger Select.
+#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Controller (default)
+#define ADC_EMUX_EM1_COMP0 0x00000010 // Analog Comparator 0
+#define ADC_EMUX_EM1_COMP1 0x00000020 // Analog Comparator 1
+#define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External (GPIO PB4)
+#define ADC_EMUX_EM1_TIMER 0x00000050 // Timer
+#define ADC_EMUX_EM1_PWM0 0x00000060 // PWM0
+#define ADC_EMUX_EM1_PWM1 0x00000070 // PWM1
+#define ADC_EMUX_EM1_PWM2 0x00000080 // PWM2
+#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always (continuously sample)
+#define ADC_EMUX_EM0_M 0x0000000F // SS0 Trigger Select.
+#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Controller (default)
+#define ADC_EMUX_EM0_COMP0 0x00000001 // Analog Comparator 0
+#define ADC_EMUX_EM0_COMP1 0x00000002 // Analog Comparator 1
+#define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External (GPIO PB4)
+#define ADC_EMUX_EM0_TIMER 0x00000005 // Timer
+#define ADC_EMUX_EM0_PWM0 0x00000006 // PWM0
+#define ADC_EMUX_EM0_PWM1 0x00000007 // PWM1
+#define ADC_EMUX_EM0_PWM2 0x00000008 // PWM2
+#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always (continuously sample)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_USTAT register.
+//
+//*****************************************************************************
+#define ADC_USTAT_UV3 0x00000008 // SS3 FIFO Underflow.
+#define ADC_USTAT_UV2 0x00000004 // SS2 FIFO Underflow.
+#define ADC_USTAT_UV1 0x00000002 // SS1 FIFO Underflow.
+#define ADC_USTAT_UV0 0x00000001 // SS0 FIFO Underflow.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSPRI register.
+//
+//*****************************************************************************
+#define ADC_SSPRI_SS3_M 0x00003000 // SS3 Priority.
+#define ADC_SSPRI_SS3_1ST 0x00000000 // First priority
+#define ADC_SSPRI_SS3_2ND 0x00001000 // Second priority
+#define ADC_SSPRI_SS3_3RD 0x00002000 // Third priority
+#define ADC_SSPRI_SS3_4TH 0x00003000 // Fourth priority
+#define ADC_SSPRI_SS2_M 0x00000300 // SS2 Priority.
+#define ADC_SSPRI_SS2_1ST 0x00000000 // First priority
+#define ADC_SSPRI_SS2_2ND 0x00000100 // Second priority
+#define ADC_SSPRI_SS2_3RD 0x00000200 // Third priority
+#define ADC_SSPRI_SS2_4TH 0x00000300 // Fourth priority
+#define ADC_SSPRI_SS1_M 0x00000030 // SS1 Priority.
+#define ADC_SSPRI_SS1_1ST 0x00000000 // First priority
+#define ADC_SSPRI_SS1_2ND 0x00000010 // Second priority
+#define ADC_SSPRI_SS1_3RD 0x00000020 // Third priority
+#define ADC_SSPRI_SS1_4TH 0x00000030 // Fourth priority
+#define ADC_SSPRI_SS0_M 0x00000003 // SS0 Priority.
+#define ADC_SSPRI_SS0_1ST 0x00000000 // First priority
+#define ADC_SSPRI_SS0_2ND 0x00000001 // Second priority
+#define ADC_SSPRI_SS0_3RD 0x00000002 // Third priority
+#define ADC_SSPRI_SS0_4TH 0x00000003 // Fourth priority
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_PSSI register.
+//
+//*****************************************************************************
+#define ADC_PSSI_SS3 0x00000008 // SS3 Initiate.
+#define ADC_PSSI_SS2 0x00000004 // SS2 Initiate.
+#define ADC_PSSI_SS1 0x00000002 // SS1 Initiate.
+#define ADC_PSSI_SS0 0x00000001 // SS0 Initiate.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SAC register.
+//
+//*****************************************************************************
+#define ADC_SAC_AVG_M 0x00000007 // Hardware Averaging Control.
+#define ADC_SAC_AVG_OFF 0x00000000 // No hardware oversampling
+#define ADC_SAC_AVG_2X 0x00000001 // 2x hardware oversampling
+#define ADC_SAC_AVG_4X 0x00000002 // 4x hardware oversampling
+#define ADC_SAC_AVG_8X 0x00000003 // 8x hardware oversampling
+#define ADC_SAC_AVG_16X 0x00000004 // 16x hardware oversampling
+#define ADC_SAC_AVG_32X 0x00000005 // 32x hardware oversampling
+#define ADC_SAC_AVG_64X 0x00000006 // 64x hardware oversampling
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX0 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX0_MUX7_M 0x30000000 // 8th Sample Input Select.
+#define ADC_SSMUX0_MUX6_M 0x03000000 // 7th Sample Input Select.
+#define ADC_SSMUX0_MUX5_M 0x00300000 // 6th Sample Input Select.
+#define ADC_SSMUX0_MUX4_M 0x00030000 // 5th Sample Input Select.
+#define ADC_SSMUX0_MUX3_M 0x00003000 // 4th Sample Input Select.
+#define ADC_SSMUX0_MUX2_M 0x00000300 // 3rd Sample Input Select.
+#define ADC_SSMUX0_MUX1_M 0x00000030 // 2nd Sample Input Select.
+#define ADC_SSMUX0_MUX0_M 0x00000003 // 1st Sample Input Select.
+#define ADC_SSMUX0_MUX7_S 28
+#define ADC_SSMUX0_MUX6_S 24
+#define ADC_SSMUX0_MUX5_S 20
+#define ADC_SSMUX0_MUX4_S 16
+#define ADC_SSMUX0_MUX3_S 12
+#define ADC_SSMUX0_MUX2_S 8
+#define ADC_SSMUX0_MUX1_S 4
+#define ADC_SSMUX0_MUX0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL0 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL0_TS7 0x80000000 // 8th Sample Temp Sensor Select.
+#define ADC_SSCTL0_IE7 0x40000000 // 8th Sample Interrupt Enable.
+#define ADC_SSCTL0_END7 0x20000000 // 8th Sample is End of Sequence.
+#define ADC_SSCTL0_D7 0x10000000 // 8th Sample Diff Input Select.
+#define ADC_SSCTL0_TS6 0x08000000 // 7th Sample Temp Sensor Select.
+#define ADC_SSCTL0_IE6 0x04000000 // 7th Sample Interrupt Enable.
+#define ADC_SSCTL0_END6 0x02000000 // 7th Sample is End of Sequence.
+#define ADC_SSCTL0_D6 0x01000000 // 7th Sample Diff Input Select.
+#define ADC_SSCTL0_TS5 0x00800000 // 6th Sample Temp Sensor Select.
+#define ADC_SSCTL0_IE5 0x00400000 // 6th Sample Interrupt Enable.
+#define ADC_SSCTL0_END5 0x00200000 // 6th Sample is End of Sequence.
+#define ADC_SSCTL0_D5 0x00100000 // 6th Sample Diff Input Select.
+#define ADC_SSCTL0_TS4 0x00080000 // 5th Sample Temp Sensor Select.
+#define ADC_SSCTL0_IE4 0x00040000 // 5th Sample Interrupt Enable.
+#define ADC_SSCTL0_END4 0x00020000 // 5th Sample is End of Sequence.
+#define ADC_SSCTL0_D4 0x00010000 // 5th Sample Diff Input Select.
+#define ADC_SSCTL0_TS3 0x00008000 // 4th Sample Temp Sensor Select.
+#define ADC_SSCTL0_IE3 0x00004000 // 4th Sample Interrupt Enable.
+#define ADC_SSCTL0_END3 0x00002000 // 4th Sample is End of Sequence.
+#define ADC_SSCTL0_D3 0x00001000 // 4th Sample Diff Input Select.
+#define ADC_SSCTL0_TS2 0x00000800 // 3rd Sample Temp Sensor Select.
+#define ADC_SSCTL0_IE2 0x00000400 // 3rd Sample Interrupt Enable.
+#define ADC_SSCTL0_END2 0x00000200 // 3rd Sample is End of Sequence.
+#define ADC_SSCTL0_D2 0x00000100 // 3rd Sample Diff Input Select.
+#define ADC_SSCTL0_TS1 0x00000080 // 2nd Sample Temp Sensor Select.
+#define ADC_SSCTL0_IE1 0x00000040 // 2nd Sample Interrupt Enable.
+#define ADC_SSCTL0_END1 0x00000020 // 2nd Sample is End of Sequence.
+#define ADC_SSCTL0_D1 0x00000010 // 2nd Sample Diff Input Select.
+#define ADC_SSCTL0_TS0 0x00000008 // 1st Sample Temp Sensor Select.
+#define ADC_SSCTL0_IE0 0x00000004 // 1st Sample Interrupt Enable.
+#define ADC_SSCTL0_END0 0x00000002 // 1st Sample is End of Sequence.
+#define ADC_SSCTL0_D0 0x00000001 // 1st Sample Diff Input Select.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO0 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO0_DATA_M 0x000003FF // Conversion Result Data.
+#define ADC_SSFIFO0_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT0 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT0_FULL 0x00001000 // FIFO Full.
+#define ADC_SSFSTAT0_EMPTY 0x00000100 // FIFO Empty.
+#define ADC_SSFSTAT0_HPTR_M 0x000000F0 // FIFO Head Pointer.
+#define ADC_SSFSTAT0_TPTR_M 0x0000000F // FIFO Tail Pointer.
+#define ADC_SSFSTAT0_HPTR_S 4
+#define ADC_SSFSTAT0_TPTR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX1 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX1_MUX3_M 0x00003000 // 4th Sample Input Select.
+#define ADC_SSMUX1_MUX2_M 0x00000300 // 3rd Sample Input Select.
+#define ADC_SSMUX1_MUX1_M 0x00000030 // 2nd Sample Input Select.
+#define ADC_SSMUX1_MUX0_M 0x00000003 // 1st Sample Input Select.
+#define ADC_SSMUX1_MUX3_S 12
+#define ADC_SSMUX1_MUX2_S 8
+#define ADC_SSMUX1_MUX1_S 4
+#define ADC_SSMUX1_MUX0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL1 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL1_TS3 0x00008000 // 4th Sample Temp Sensor Select.
+#define ADC_SSCTL1_IE3 0x00004000 // 4th Sample Interrupt Enable.
+#define ADC_SSCTL1_END3 0x00002000 // 4th Sample is End of Sequence.
+#define ADC_SSCTL1_D3 0x00001000 // 4th Sample Diff Input Select.
+#define ADC_SSCTL1_TS2 0x00000800 // 3rd Sample Temp Sensor Select.
+#define ADC_SSCTL1_IE2 0x00000400 // 3rd Sample Interrupt Enable.
+#define ADC_SSCTL1_END2 0x00000200 // 3rd Sample is End of Sequence.
+#define ADC_SSCTL1_D2 0x00000100 // 3rd Sample Diff Input Select.
+#define ADC_SSCTL1_TS1 0x00000080 // 2nd Sample Temp Sensor Select.
+#define ADC_SSCTL1_IE1 0x00000040 // 2nd Sample Interrupt Enable.
+#define ADC_SSCTL1_END1 0x00000020 // 2nd Sample is End of Sequence.
+#define ADC_SSCTL1_D1 0x00000010 // 2nd Sample Diff Input Select.
+#define ADC_SSCTL1_TS0 0x00000008 // 1st Sample Temp Sensor Select.
+#define ADC_SSCTL1_IE0 0x00000004 // 1st Sample Interrupt Enable.
+#define ADC_SSCTL1_END0 0x00000002 // 1st Sample is End of Sequence.
+#define ADC_SSCTL1_D0 0x00000001 // 1st Sample Diff Input Select.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO1 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO1_DATA_M 0x000003FF // Conversion Result Data.
+#define ADC_SSFIFO1_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT1 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT1_FULL 0x00001000 // FIFO Full.
+#define ADC_SSFSTAT1_EMPTY 0x00000100 // FIFO Empty.
+#define ADC_SSFSTAT1_HPTR_M 0x000000F0 // FIFO Head Pointer.
+#define ADC_SSFSTAT1_TPTR_M 0x0000000F // FIFO Tail Pointer.
+#define ADC_SSFSTAT1_HPTR_S 4
+#define ADC_SSFSTAT1_TPTR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX2 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX2_MUX3_M 0x00003000 // 4th Sample Input Select.
+#define ADC_SSMUX2_MUX2_M 0x00000300 // 3rd Sample Input Select.
+#define ADC_SSMUX2_MUX1_M 0x00000030 // 2nd Sample Input Select.
+#define ADC_SSMUX2_MUX0_M 0x00000003 // 1st Sample Input Select.
+#define ADC_SSMUX2_MUX3_S 12
+#define ADC_SSMUX2_MUX2_S 8
+#define ADC_SSMUX2_MUX1_S 4
+#define ADC_SSMUX2_MUX0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL2 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL2_TS3 0x00008000 // 4th Sample Temp Sensor Select.
+#define ADC_SSCTL2_IE3 0x00004000 // 4th Sample Interrupt Enable.
+#define ADC_SSCTL2_END3 0x00002000 // 4th Sample is End of Sequence.
+#define ADC_SSCTL2_D3 0x00001000 // 4th Sample Diff Input Select.
+#define ADC_SSCTL2_TS2 0x00000800 // 3rd Sample Temp Sensor Select.
+#define ADC_SSCTL2_IE2 0x00000400 // 3rd Sample Interrupt Enable.
+#define ADC_SSCTL2_END2 0x00000200 // 3rd Sample is End of Sequence.
+#define ADC_SSCTL2_D2 0x00000100 // 3rd Sample Diff Input Select.
+#define ADC_SSCTL2_TS1 0x00000080 // 2nd Sample Temp Sensor Select.
+#define ADC_SSCTL2_IE1 0x00000040 // 2nd Sample Interrupt Enable.
+#define ADC_SSCTL2_END1 0x00000020 // 2nd Sample is End of Sequence.
+#define ADC_SSCTL2_D1 0x00000010 // 2nd Sample Diff Input Select.
+#define ADC_SSCTL2_TS0 0x00000008 // 1st Sample Temp Sensor Select.
+#define ADC_SSCTL2_IE0 0x00000004 // 1st Sample Interrupt Enable.
+#define ADC_SSCTL2_END0 0x00000002 // 1st Sample is End of Sequence.
+#define ADC_SSCTL2_D0 0x00000001 // 1st Sample Diff Input Select.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO2 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO2_DATA_M 0x000003FF // Conversion Result Data.
+#define ADC_SSFIFO2_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT2 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT2_FULL 0x00001000 // FIFO Full.
+#define ADC_SSFSTAT2_EMPTY 0x00000100 // FIFO Empty.
+#define ADC_SSFSTAT2_HPTR_M 0x000000F0 // FIFO Head Pointer.
+#define ADC_SSFSTAT2_TPTR_M 0x0000000F // FIFO Tail Pointer.
+#define ADC_SSFSTAT2_HPTR_S 4
+#define ADC_SSFSTAT2_TPTR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX3 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX3_MUX0_M 0x00000003 // 1st Sample Input Select.
+#define ADC_SSMUX3_MUX0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL3 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL3_TS0 0x00000008 // 1st Sample Temp Sensor Select.
+#define ADC_SSCTL3_IE0 0x00000004 // 1st Sample Interrupt Enable.
+#define ADC_SSCTL3_END0 0x00000002 // 1st Sample is End of Sequence.
+#define ADC_SSCTL3_D0 0x00000001 // 1st Sample Diff Input Select.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO3 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO3_DATA_M 0x000003FF // Conversion Result Data.
+#define ADC_SSFIFO3_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT3 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT3_FULL 0x00001000 // FIFO Full.
+#define ADC_SSFSTAT3_EMPTY 0x00000100 // FIFO Empty.
+#define ADC_SSFSTAT3_HPTR_M 0x000000F0 // FIFO Head Pointer.
+#define ADC_SSFSTAT3_TPTR_M 0x0000000F // FIFO Tail Pointer.
+#define ADC_SSFSTAT3_HPTR_S 4
+#define ADC_SSFSTAT3_TPTR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_TMLB register.
+//
+//*****************************************************************************
+#define ADC_TMLB_LB 0x00000001 // Loopback Mode Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the the interpretation of the data in the
+// SSFIFOx when the ADC TMLB is enabled.
+//
+//*****************************************************************************
+#define ADC_SSFIFO_TMLB_CNT_M 0x000003C0 // Continuous Sample Counter.
+#define ADC_SSFIFO_TMLB_CONT 0x00000020 // Continuation Sample Indicator.
+#define ADC_SSFIFO_TMLB_DIFF 0x00000010 // Differential Sample Indicator.
+#define ADC_SSFIFO_TMLB_TS 0x00000008 // Temp Sensor Sample Indicator.
+#define ADC_SSFIFO_TMLB_MUX_M 0x00000007 // Analog Input Indicator.
+#define ADC_SSFIFO_TMLB_CNT_S 6 // Sample counter shift
+#define ADC_SSFIFO_TMLB_MUX_S 0 // Input channel number shift
+
+//*****************************************************************************
+//
+// The following are defines for the the interpretation of the data in the
+// SSFIFOx when the ADC TMLB is enabled.
+//
+//*****************************************************************************
+#define ADC_TMLB_CNT_M 0x000003C0 // Continuous Sample Counter.
+#define ADC_TMLB_CONT 0x00000020 // Continuation Sample Indicator.
+#define ADC_TMLB_DIFF 0x00000010 // Differential Sample Indicator.
+#define ADC_TMLB_TS 0x00000008 // Temp Sensor Sample Indicator.
+#define ADC_TMLB_MUX_M 0x00000007 // Analog Input Indicator.
+#define ADC_TMLB_CNT_S 6 // Sample counter shift
+#define ADC_TMLB_MUX_S 0 // Input channel number shift
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACMIS register.
+//
+//*****************************************************************************
+#define COMP_ACMIS_IN1 0x00000002 // Comparator 1 Masked Interrupt
+ // Status.
+#define COMP_ACMIS_IN0 0x00000001 // Comparator 0 Masked Interrupt
+ // Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACRIS register.
+//
+//*****************************************************************************
+#define COMP_ACRIS_IN1 0x00000002 // Comparator 1 Interrupt Status.
+#define COMP_ACRIS_IN0 0x00000001 // Comparator 0 Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACINTEN register.
+//
+//*****************************************************************************
+#define COMP_ACINTEN_IN1 0x00000002 // Comparator 1 Interrupt Enable.
+#define COMP_ACINTEN_IN0 0x00000001 // Comparator 0 Interrupt Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACREFCTL
+// register.
+//
+//*****************************************************************************
+#define COMP_ACREFCTL_EN 0x00000200 // Resistor Ladder Enable.
+#define COMP_ACREFCTL_RNG 0x00000100 // Resistor Ladder Range.
+#define COMP_ACREFCTL_VREF_M 0x0000000F // Resistor Ladder Voltage Ref.
+#define COMP_ACREFCTL_VREF_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACSTAT0 register.
+//
+//*****************************************************************************
+#define COMP_ACSTAT0_OVAL 0x00000002 // Comparator Output Value.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACCTL0 register.
+//
+//*****************************************************************************
+#define COMP_ACCTL0_TOEN 0x00000800 // Trigger Output Enable.
+#define COMP_ACCTL0_ASRCP_M 0x00000600 // Analog Source Positive.
+#define COMP_ACCTL0_ASRCP_PIN 0x00000000 // Pin value
+#define COMP_ACCTL0_ASRCP_PIN0 0x00000200 // Pin value of C0+
+#define COMP_ACCTL0_ASRCP_REF 0x00000400 // Internal voltage reference
+#define COMP_ACCTL0_TSLVAL 0x00000080 // Trigger Sense Level Value.
+#define COMP_ACCTL0_TSEN_M 0x00000060 // Trigger Sense.
+#define COMP_ACCTL0_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL
+#define COMP_ACCTL0_TSEN_FALL 0x00000020 // Falling edge
+#define COMP_ACCTL0_TSEN_RISE 0x00000040 // Rising edge
+#define COMP_ACCTL0_TSEN_BOTH 0x00000060 // Either edge
+#define COMP_ACCTL0_ISLVAL 0x00000010 // Interrupt Sense Level Value.
+#define COMP_ACCTL0_ISEN_M 0x0000000C // Interrupt Sense.
+#define COMP_ACCTL0_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL
+#define COMP_ACCTL0_ISEN_FALL 0x00000004 // Falling edge
+#define COMP_ACCTL0_ISEN_RISE 0x00000008 // Rising edge
+#define COMP_ACCTL0_ISEN_BOTH 0x0000000C // Either edge
+#define COMP_ACCTL0_CINV 0x00000002 // Comparator Output Invert.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACSTAT1 register.
+//
+//*****************************************************************************
+#define COMP_ACSTAT1_OVAL 0x00000002 // Comparator Output Value.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACCTL1 register.
+//
+//*****************************************************************************
+#define COMP_ACCTL1_TOEN 0x00000800 // Trigger Output Enable.
+#define COMP_ACCTL1_ASRCP_M 0x00000600 // Analog Source Positive.
+#define COMP_ACCTL1_ASRCP_PIN 0x00000000 // Pin value
+#define COMP_ACCTL1_ASRCP_PIN0 0x00000200 // Pin value of C0+
+#define COMP_ACCTL1_ASRCP_REF 0x00000400 // Internal voltage reference
+#define COMP_ACCTL1_TSLVAL 0x00000080 // Trigger Sense Level Value.
+#define COMP_ACCTL1_TSEN_M 0x00000060 // Trigger Sense.
+#define COMP_ACCTL1_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL
+#define COMP_ACCTL1_TSEN_FALL 0x00000020 // Falling edge
+#define COMP_ACCTL1_TSEN_RISE 0x00000040 // Rising edge
+#define COMP_ACCTL1_TSEN_BOTH 0x00000060 // Either edge
+#define COMP_ACCTL1_ISLVAL 0x00000010 // Interrupt Sense Level Value.
+#define COMP_ACCTL1_ISEN_M 0x0000000C // Interrupt Sense.
+#define COMP_ACCTL1_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL
+#define COMP_ACCTL1_ISEN_FALL 0x00000004 // Falling edge
+#define COMP_ACCTL1_ISEN_RISE 0x00000008 // Rising edge
+#define COMP_ACCTL1_ISEN_BOTH 0x0000000C // Either edge
+#define COMP_ACCTL1_CINV 0x00000002 // Comparator Output Invert.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MR0 register.
+//
+//*****************************************************************************
+#define PHY_MR0_RESET 0x00008000 // Reset Registers.
+#define PHY_MR0_LOOPBK 0x00004000 // Loopback Mode.
+#define PHY_MR0_SPEEDSL 0x00002000 // Speed Select.
+#define PHY_MR0_ANEGEN 0x00001000 // Auto-Negotiation Enable.
+#define PHY_MR0_PWRDN 0x00000800 // Power Down.
+#define PHY_MR0_ISO 0x00000400 // Isolate.
+#define PHY_MR0_RANEG 0x00000200 // Restart Auto-Negotiation.
+#define PHY_MR0_DUPLEX 0x00000100 // Set Duplex Mode.
+#define PHY_MR0_COLT 0x00000080 // Collision Test.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_RIS register.
+//
+//*****************************************************************************
+#define MAC_RIS_PHYINT 0x00000040 // PHY Interrupt.
+#define MAC_RIS_MDINT 0x00000020 // MII Transaction Complete.
+#define MAC_RIS_RXER 0x00000010 // Receive Error.
+#define MAC_RIS_FOV 0x00000008 // FIFO Overrun.
+#define MAC_RIS_TXEMP 0x00000004 // Transmit FIFO Empty.
+#define MAC_RIS_TXER 0x00000002 // Transmit Error.
+#define MAC_RIS_RXINT 0x00000001 // Packet Received.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_IACK register.
+//
+//*****************************************************************************
+#define MAC_IACK_PHYINT 0x00000040 // Clear PHY Interrupt.
+#define MAC_IACK_MDINT 0x00000020 // Clear MII Transaction Complete.
+#define MAC_IACK_RXER 0x00000010 // Clear Receive Error.
+#define MAC_IACK_FOV 0x00000008 // Clear FIFO Overrun.
+#define MAC_IACK_TXEMP 0x00000004 // Clear Transmit FIFO Empty.
+#define MAC_IACK_TXER 0x00000002 // Clear Transmit Error.
+#define MAC_IACK_RXINT 0x00000001 // Clear Packet Received.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MR1 register.
+//
+//*****************************************************************************
+#define PHY_MR1_100X_F 0x00004000 // 100BASE-TX Full-Duplex Mode.
+#define PHY_MR1_100X_H 0x00002000 // 100BASE-TX Half-Duplex Mode.
+#define PHY_MR1_10T_F 0x00001000 // 10BASE-T Full-Duplex Mode.
+#define PHY_MR1_10T_H 0x00000800 // 10BASE-T Half-Duplex Mode.
+#define PHY_MR1_MFPS 0x00000040 // Management Frames with Preamble
+ // Suppressed.
+#define PHY_MR1_ANEGC 0x00000020 // Auto-Negotiation Complete.
+#define PHY_MR1_RFAULT 0x00000010 // Remote Fault.
+#define PHY_MR1_ANEGA 0x00000008 // Auto-Negotiation.
+#define PHY_MR1_LINK 0x00000004 // Link Made.
+#define PHY_MR1_JAB 0x00000002 // Jabber Condition.
+#define PHY_MR1_EXTD 0x00000001 // Extended Capabilities.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MR2 register.
+//
+//*****************************************************************************
+#define PHY_MR2_OUI_M 0x0000FFFF // Organizationally Unique
+ // Identifier[21:6].
+#define PHY_MR2_OUI_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MR3 register.
+//
+//*****************************************************************************
+#define PHY_MR3_OUI_M 0x0000FC00 // Organizationally Unique
+ // Identifier[5:0].
+#define PHY_MR3_MN_M 0x000003F0 // Model Number.
+#define PHY_MR3_RN_M 0x0000000F // Revision Number.
+#define PHY_MR3_OUI_S 10
+#define PHY_MR3_MN_S 4
+#define PHY_MR3_RN_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_IM register.
+//
+//*****************************************************************************
+#define MAC_IM_PHYINTM 0x00000040 // Mask PHY Interrupt.
+#define MAC_IM_MDINTM 0x00000020 // Mask MII Transaction Complete.
+#define MAC_IM_RXERM 0x00000010 // Mask Receive Error.
+#define MAC_IM_FOVM 0x00000008 // Mask FIFO Overrun.
+#define MAC_IM_TXEMPM 0x00000004 // Mask Transmit FIFO Empty.
+#define MAC_IM_TXERM 0x00000002 // Mask Transmit Error.
+#define MAC_IM_RXINTM 0x00000001 // Mask Packet Received.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MR4 register.
+//
+//*****************************************************************************
+#define PHY_MR4_NP 0x00008000 // Next Page.
+#define PHY_MR4_RF 0x00002000 // Remote Fault.
+#define PHY_MR4_A3 0x00000100 // Technology Ability Field[3].
+#define PHY_MR4_A2 0x00000080 // Technology Ability Field[2].
+#define PHY_MR4_A1 0x00000040 // Technology Ability Field[1].
+#define PHY_MR4_A0 0x00000020 // Technology Ability Field[0].
+#define PHY_MR4_S_M 0x0000001F // Selector Field.
+#define PHY_MR4_S_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MR5 register.
+//
+//*****************************************************************************
+#define PHY_MR5_NP 0x00008000 // Next Page.
+#define PHY_MR5_ACK 0x00004000 // Acknowledge.
+#define PHY_MR5_RF 0x00002000 // Remote Fault.
+#define PHY_MR5_A_M 0x00001FE0 // Technology Ability Field.
+#define PHY_MR5_S_M 0x0000001F // Selector Field.
+#define PHY_MR5_S_8023 0x00000001 // IEEE Std 802.3
+#define PHY_MR5_S_8029 0x00000002 // IEEE Std 802.9 ISLAN-16T
+#define PHY_MR5_S_8025 0x00000003 // IEEE Std 802.5
+#define PHY_MR5_S_1394 0x00000004 // IEEE Std 1394
+#define PHY_MR5_A_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MR6 register.
+//
+//*****************************************************************************
+#define PHY_MR6_PDF 0x00000010 // Parallel Detection Fault.
+#define PHY_MR6_LPNPA 0x00000008 // Link Partner is Next Page Able.
+#define PHY_MR6_PRX 0x00000002 // New Page Received.
+#define PHY_MR6_LPANEGA 0x00000001 // Link Partner is Auto-Negotiation
+ // Able.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_RCTL register.
+//
+//*****************************************************************************
+#define MAC_RCTL_RSTFIFO 0x00000010 // Clear Receive FIFO.
+#define MAC_RCTL_BADCRC 0x00000008 // Enable Reject Bad CRC.
+#define MAC_RCTL_PRMS 0x00000004 // Enable Promiscuous Mode.
+#define MAC_RCTL_AMUL 0x00000002 // Enable Multicast Frames.
+#define MAC_RCTL_RXEN 0x00000001 // Enable Receiver.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_TCTL register.
+//
+//*****************************************************************************
+#define MAC_TCTL_DUPLEX 0x00000010 // Enable Duplex Mode.
+#define MAC_TCTL_CRC 0x00000004 // Enable CRC Generation.
+#define MAC_TCTL_PADEN 0x00000002 // Enable Packet Padding.
+#define MAC_TCTL_TXEN 0x00000001 // Enable Transmitter.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_DATA register.
+//
+//*****************************************************************************
+#define MAC_DATA_TXDATA_M 0xFFFFFFFF // Transmit FIFO Data.
+#define MAC_DATA_RXDATA_M 0xFFFFFFFF // Receive FIFO Data.
+#define MAC_DATA_RXDATA_S 0
+#define MAC_DATA_TXDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MR16 register.
+//
+//*****************************************************************************
+#define PHY_MR16_RPTR 0x00008000 // Repeater Mode.
+#define PHY_MR16_INPOL 0x00004000 // Interrupt Polarity.
+#define PHY_MR16_TXHIM 0x00001000 // Transmit High Impedance Mode.
+#define PHY_MR16_SQEI 0x00000800 // SQE Inhibit Testing.
+#define PHY_MR16_NL10 0x00000400 // Natural Loopback Mode.
+#define PHY_MR16_APOL 0x00000020 // Auto-Polarity Disable.
+#define PHY_MR16_RVSPOL 0x00000010 // Receive Data Polarity.
+#define PHY_MR16_PCSBP 0x00000002 // PCS Bypass.
+#define PHY_MR16_RXCC 0x00000001 // Receive Clock Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MR17 register.
+//
+//*****************************************************************************
+#define PHY_MR17_JABBER_IE 0x00008000 // Jabber Interrupt Enable.
+#define PHY_MR17_RXER_IE 0x00004000 // Receive Error Interrupt Enable.
+#define PHY_MR17_PRX_IE 0x00002000 // Page Received Interrupt Enable.
+#define PHY_MR17_PDF_IE 0x00001000 // Parallel Detection Fault
+ // Interrupt Enable.
+#define PHY_MR17_LPACK_IE 0x00000800 // LP Acknowledge Interrupt Enable.
+#define PHY_MR17_LSCHG_IE 0x00000400 // Link Status Change Interrupt
+ // Enable.
+#define PHY_MR17_RFAULT_IE 0x00000200 // Remote Fault Interrupt Enable.
+#define PHY_MR17_ANEGCOMP_IE 0x00000100 // Auto-Negotiation Complete
+ // Interrupt Enable.
+#define PHY_MR17_JABBER_INT 0x00000080 // Jabber Event Interrupt.
+#define PHY_MR17_RXER_INT 0x00000040 // Receive Error Interrupt.
+#define PHY_MR17_PRX_INT 0x00000020 // Page Receive Interrupt.
+#define PHY_MR17_PDF_INT 0x00000010 // Parallel Detection Fault
+ // Interrupt.
+#define PHY_MR17_LPACK_INT 0x00000008 // LP Acknowledge Interrupt.
+#define PHY_MR17_LSCHG_INT 0x00000004 // Link Status Change Interrupt.
+#define PHY_MR17_RFAULT_INT 0x00000002 // Remote Fault Interrupt.
+#define PHY_MR17_ANEGCOMP_INT 0x00000001 // Auto-Negotiation Complete
+ // Interrupt.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MR18 register.
+//
+//*****************************************************************************
+#define PHY_MR18_ANEGF 0x00001000 // Auto-Negotiation Failure.
+#define PHY_MR18_DPLX 0x00000800 // Duplex Mode.
+#define PHY_MR18_RATE 0x00000400 // Rate.
+#define PHY_MR18_RXSD 0x00000200 // Receive Detection.
+#define PHY_MR18_RX_LOCK 0x00000100 // Receive PLL Lock.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MR19 register.
+//
+//*****************************************************************************
+#define PHY_MR19_TXO_M 0x0000C000 // Transmit Amplitude Selection.
+#define PHY_MR19_TXO_00DB 0x00000000 // Gain set for 0.0dB of insertion
+ // loss
+#define PHY_MR19_TXO_04DB 0x00004000 // Gain set for 0.4dB of insertion
+ // loss
+#define PHY_MR19_TXO_08DB 0x00008000 // Gain set for 0.8dB of insertion
+ // loss
+#define PHY_MR19_TXO_12DB 0x0000C000 // Gain set for 1.2dB of insertion
+ // loss
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_IA0 register.
+//
+//*****************************************************************************
+#define MAC_IA0_MACOCT4_M 0xFF000000 // MAC Address Octet 4.
+#define MAC_IA0_MACOCT3_M 0x00FF0000 // MAC Address Octet 3.
+#define MAC_IA0_MACOCT2_M 0x0000FF00 // MAC Address Octet 2.
+#define MAC_IA0_MACOCT1_M 0x000000FF // MAC Address Octet 1.
+#define MAC_IA0_MACOCT4_S 24
+#define MAC_IA0_MACOCT3_S 16
+#define MAC_IA0_MACOCT2_S 8
+#define MAC_IA0_MACOCT1_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MR23 register.
+//
+//*****************************************************************************
+#define PHY_MR23_LED1_M 0x000000F0 // LED1 Source.
+#define PHY_MR23_LED1_LINK 0x00000000 // Link OK
+#define PHY_MR23_LED1_RXTX 0x00000010 // RX or TX Activity (Default LED1)
+#define PHY_MR23_LED1_100 0x00000050 // 100BASE-TX mode
+#define PHY_MR23_LED1_10 0x00000060 // 10BASE-T mode
+#define PHY_MR23_LED1_DUPLEX 0x00000070 // Full-Duplex
+#define PHY_MR23_LED1_LINKACT 0x00000080 // Link OK & Blink=RX or TX
+ // Activity
+#define PHY_MR23_LED0_M 0x0000000F // LED0 Source.
+#define PHY_MR23_LED0_LINK 0x00000000 // Link OK (Default LED0)
+#define PHY_MR23_LED0_RXTX 0x00000001 // RX or TX Activity
+#define PHY_MR23_LED0_100 0x00000005 // 100BASE-TX mode
+#define PHY_MR23_LED0_10 0x00000006 // 10BASE-T mode
+#define PHY_MR23_LED0_DUPLEX 0x00000007 // Full-Duplex
+#define PHY_MR23_LED0_LINKACT 0x00000008 // Link OK & Blink=RX or TX
+ // Activity
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_IA1 register.
+//
+//*****************************************************************************
+#define MAC_IA1_MACOCT6_M 0x0000FF00 // MAC Address Octet 6.
+#define MAC_IA1_MACOCT5_M 0x000000FF // MAC Address Octet 5.
+#define MAC_IA1_MACOCT6_S 8
+#define MAC_IA1_MACOCT5_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MR24 register.
+//
+//*****************************************************************************
+#define PHY_MR24_PD_MODE 0x00000080 // Parallel Detection Mode.
+#define PHY_MR24_AUTO_SW 0x00000040 // Auto-Switching Enable.
+#define PHY_MR24_MDIX 0x00000020 // Auto-Switching Configuration.
+#define PHY_MR24_MDIX_CM 0x00000010 // Auto-Switching Complete.
+#define PHY_MR24_MDIX_SD_M 0x0000000F // Auto-Switching Seed.
+#define PHY_MR24_MDIX_SD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_THR register.
+//
+//*****************************************************************************
+#define MAC_THR_THRESH_M 0x0000003F // Threshold Value.
+#define MAC_THR_THRESH_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MCTL register.
+//
+//*****************************************************************************
+#define MAC_MCTL_REGADR_M 0x000000F8 // MII Register Address.
+#define MAC_MCTL_WRITE 0x00000002 // MII Register Transaction Type.
+#define MAC_MCTL_START 0x00000001 // MII Register Transaction Enable.
+#define MAC_MCTL_REGADR_S 3
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MDV register.
+//
+//*****************************************************************************
+#define MAC_MDV_DIV_M 0x000000FF // Clock Divider.
+#define MAC_MDV_DIV_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MTXD register.
+//
+//*****************************************************************************
+#define MAC_MTXD_MDTX_M 0x0000FFFF // MII Register Transmit Data.
+#define MAC_MTXD_MDTX_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MRXD register.
+//
+//*****************************************************************************
+#define MAC_MRXD_MDRX_M 0x0000FFFF // MII Register Receive Data.
+#define MAC_MRXD_MDRX_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_NP register.
+//
+//*****************************************************************************
+#define MAC_NP_NPR_M 0x0000003F // Number of Packets in Receive
+ // FIFO.
+#define MAC_NP_NPR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_TR register.
+//
+//*****************************************************************************
+#define MAC_TR_NEWTX 0x00000001 // New Transmission.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCC register.
+//
+//*****************************************************************************
+#define HIB_RTCC_M 0xFFFFFFFF // RTC Counter.
+#define HIB_RTCC_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCM0 register.
+//
+//*****************************************************************************
+#define HIB_RTCM0_M 0xFFFFFFFF // RTC Match 0.
+#define HIB_RTCM0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCM1 register.
+//
+//*****************************************************************************
+#define HIB_RTCM1_M 0xFFFFFFFF // RTC Match 1.
+#define HIB_RTCM1_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCLD register.
+//
+//*****************************************************************************
+#define HIB_RTCLD_M 0xFFFFFFFF // RTC Load.
+#define HIB_RTCLD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_CTL register.
+//
+//*****************************************************************************
+#define HIB_CTL_VABORT 0x00000080 // Power Cut Abort Enable.
+#define HIB_CTL_CLK32EN 0x00000040 // Clocking Enable.
+#define HIB_CTL_LOWBATEN 0x00000020 // Low Battery Monitoring Enable.
+#define HIB_CTL_PINWEN 0x00000010 // External WAKE Pin Enable.
+#define HIB_CTL_RTCWEN 0x00000008 // RTC Wake-up Enable.
+#define HIB_CTL_CLKSEL 0x00000004 // Hibernation Module Clock Select.
+#define HIB_CTL_HIBREQ 0x00000002 // Hibernation Request.
+#define HIB_CTL_RTCEN 0x00000001 // RTC Timer Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_IM register.
+//
+//*****************************************************************************
+#define HIB_IM_EXTW 0x00000008 // External Wake-Up Interrupt Mask.
+#define HIB_IM_LOWBAT 0x00000004 // Low Battery Voltage Interrupt
+ // Mask.
+#define HIB_IM_RTCALT1 0x00000002 // RTC Alert1 Interrupt Mask.
+#define HIB_IM_RTCALT0 0x00000001 // RTC Alert0 Interrupt Mask.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RIS register.
+//
+//*****************************************************************************
+#define HIB_RIS_EXTW 0x00000008 // External Wake-Up Raw Interrupt
+ // Status.
+#define HIB_RIS_LOWBAT 0x00000004 // Low Battery Voltage Raw
+ // Interrupt Status.
+#define HIB_RIS_RTCALT1 0x00000002 // RTC Alert1 Raw Interrupt Status.
+#define HIB_RIS_RTCALT0 0x00000001 // RTC Alert0 Raw Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_MIS register.
+//
+//*****************************************************************************
+#define HIB_MIS_EXTW 0x00000008 // External Wake-Up Masked
+ // Interrupt Status.
+#define HIB_MIS_LOWBAT 0x00000004 // Low Battery Voltage Masked
+ // Interrupt Status.
+#define HIB_MIS_RTCALT1 0x00000002 // RTC Alert1 Masked Interrupt
+ // Status.
+#define HIB_MIS_RTCALT0 0x00000001 // RTC Alert0 Masked Interrupt
+ // Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_IC register.
+//
+//*****************************************************************************
+#define HIB_IC_EXTW 0x00000008 // External Wake-Up Masked
+ // Interrupt Clear.
+#define HIB_IC_LOWBAT 0x00000004 // Low Battery Voltage Masked
+ // Interrupt Clear.
+#define HIB_IC_RTCALT1 0x00000002 // RTC Alert1 Masked Interrupt
+ // Clear.
+#define HIB_IC_RTCALT0 0x00000001 // RTC Alert0 Masked Interrupt
+ // Clear.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCT register.
+//
+//*****************************************************************************
+#define HIB_RTCT_TRIM_M 0x0000FFFF // RTC Trim Value.
+#define HIB_RTCT_TRIM_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_DATA register.
+//
+//*****************************************************************************
+#define HIB_DATA_RTD_M 0xFFFFFFFF // Hibernation Module NV
+ // Registers[63:0].
+#define HIB_DATA_RTD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMA register.
+//
+//*****************************************************************************
+#define FLASH_FMA_OFFSET_M 0x0003FFFF // Address Offset.
+#define FLASH_FMA_OFFSET_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMD register.
+//
+//*****************************************************************************
+#define FLASH_FMD_DATA_M 0xFFFFFFFF // Data Value.
+#define FLASH_FMD_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMC register.
+//
+//*****************************************************************************
+#define FLASH_FMC_WRKEY_M 0xFFFF0000 // Flash Write Key.
+#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key
+#define FLASH_FMC_COMT 0x00000008 // Commit Register Value.
+#define FLASH_FMC_MERASE 0x00000004 // Mass Erase Flash Memory.
+#define FLASH_FMC_ERASE 0x00000002 // Erase a Page of Flash Memory.
+#define FLASH_FMC_WRITE 0x00000001 // Write a Word into Flash Memory.
+#define FLASH_FMC_WRKEY_S 16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FCRIS register.
+//
+//*****************************************************************************
+#define FLASH_FCRIS_PRIS 0x00000002 // Programming Raw Interrupt
+ // Status.
+#define FLASH_FCRIS_ARIS 0x00000001 // Access Raw Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FCIM register.
+//
+//*****************************************************************************
+#define FLASH_FCIM_PMASK 0x00000002 // Programming Interrupt Mask.
+#define FLASH_FCIM_AMASK 0x00000001 // Access Interrupt Mask.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FCMISC register.
+//
+//*****************************************************************************
+#define FLASH_FCMISC_PMISC 0x00000002 // Programming Masked Interrupt
+ // Status and Clear.
+#define FLASH_FCMISC_AMISC 0x00000001 // Access Masked Interrupt Status
+ // and Clear.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USECRL register.
+//
+//*****************************************************************************
+#define FLASH_USECRL_M 0x000000FF // Microsecond Reload Value.
+#define FLASH_USECRL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERDBG register.
+//
+//*****************************************************************************
+#define FLASH_USERDBG_NW 0x80000000 // User Debug Not Written.
+#define FLASH_USERDBG_DATA_M 0x7FFFFFFC // User Data.
+#define FLASH_USERDBG_DBG1 0x00000002 // Debug Control 1.
+#define FLASH_USERDBG_DBG0 0x00000001 // Debug Control 0.
+#define FLASH_USERDBG_DATA_S 2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG0 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG0_NW 0x80000000 // Not Written.
+#define FLASH_USERREG0_DATA_M 0x7FFFFFFF // User Data.
+#define FLASH_USERREG0_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG1 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG1_NW 0x80000000 // Not Written.
+#define FLASH_USERREG1_DATA_M 0x7FFFFFFF // User Data.
+#define FLASH_USERREG1_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the erase size of the FLASH block that is
+// erased by an erase operation, and the protect size is the size of the FLASH
+// block that is protected by each protection register.
+//
+//*****************************************************************************
+#define FLASH_PROTECT_SIZE 0x00000800
+#define FLASH_ERASE_SIZE 0x00000400
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DID0 register.
+//
+//*****************************************************************************
+#define SYSCTL_DID0_VER_M 0x70000000 // DID0 Version.
+#define SYSCTL_DID0_VER_1 0x10000000 // Second version of the DID0
+ // register format.
+#define SYSCTL_DID0_CLASS_M 0x00FF0000 // Device Class.
+#define SYSCTL_DID0_CLASS_FURY 0x00010000 // Stellaris(r) Fury-class devices.
+#define SYSCTL_DID0_MAJ_M 0x0000FF00 // Major Revision.
+#define SYSCTL_DID0_MAJ_REVA 0x00000000 // Revision A (initial device)
+#define SYSCTL_DID0_MAJ_REVB 0x00000100 // Revision B (first base layer
+ // revision)
+#define SYSCTL_DID0_MAJ_REVC 0x00000200 // Revision C (second base layer
+ // revision)
+#define SYSCTL_DID0_MIN_M 0x000000FF // Minor Revision.
+#define SYSCTL_DID0_MIN_0 0x00000000 // Initial device, or a major
+ // revision update.
+#define SYSCTL_DID0_MIN_1 0x00000001 // First metal layer change.
+#define SYSCTL_DID0_MIN_2 0x00000002 // Second metal layer change.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DID1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DID1_VER_M 0xF0000000 // DID1 Version.
+#define SYSCTL_DID1_VER_1 0x10000000 // Second version of the DID1
+ // register format.
+#define SYSCTL_DID1_FAM_M 0x0F000000 // Family.
+#define SYSCTL_DID1_FAM_STELLARIS \
+ 0x00000000 // Stellaris family of
+ // microcontollers, that is, all
+ // devices with external part
+ // numbers starting with LM3S.
+#define SYSCTL_DID1_PRTNO_M 0x00FF0000 // Part Number.
+#define SYSCTL_DID1_PRTNO_6965 0x00730000 // LM3S6965
+#define SYSCTL_DID1_PINCNT_M 0x0000E000 // Package Pin Count.
+#define SYSCTL_DID1_PINCNT_100 0x00004000 // 100-pin or 108-ball package
+#define SYSCTL_DID1_TEMP_M 0x000000E0 // Temperature Range.
+#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temperature range (0C
+ // to 70C)
+#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temperature range
+ // (-40C to 85C)
+#define SYSCTL_DID1_TEMP_E 0x00000040 // Extended temperature range (-40C
+ // to 105C)
+#define SYSCTL_DID1_PKG_M 0x00000018 // Package Type.
+#define SYSCTL_DID1_PKG_28SOIC 0x00000000 // SOIC package
+#define SYSCTL_DID1_PKG_48QFP 0x00000008 // LQFP package
+#define SYSCTL_DID1_PKG_BGA 0x00000010 // BGA package
+#define SYSCTL_DID1_ROHS 0x00000004 // RoHS-Compliance.
+#define SYSCTL_DID1_QUAL_M 0x00000003 // Qualification Status.
+#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering Sample (unqualified)
+#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot Production (unqualified)
+#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully Qualified
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC0_SRAMSZ_M 0xFFFF0000 // SRAM Size.
+#define SYSCTL_DC0_SRAMSZ_64KB 0x00FF0000 // 64 KB of SRAM
+#define SYSCTL_DC0_FLASHSZ_M 0x0000FFFF // Flash Size.
+#define SYSCTL_DC0_FLASHSZ_256K 0x0000007F // 256 KB of Flash
+#define SYSCTL_DC0_SRAMSZ_S 16 // SRAM size shift
+#define SYSCTL_DC0_FLASHSZ_S 0 // Flash size shift
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC1_PWM 0x00100000 // PWM Module Present.
+#define SYSCTL_DC1_ADC 0x00010000 // ADC Module Present.
+#define SYSCTL_DC1_MINSYSDIV_M 0x0000F000 // System Clock Divider.
+#define SYSCTL_DC1_MINSYSDIV_50 0x00003000 // Specifies a 50-MHz CPU clock
+ // with a PLL divider of 4.
+#define SYSCTL_DC1_ADCSPD_M 0x00000300 // Max ADC Speed.
+#define SYSCTL_DC1_ADCSPD_1M 0x00000300 // 1M samples/second
+#define SYSCTL_DC1_MPU 0x00000080 // MPU Present.
+#define SYSCTL_DC1_HIB 0x00000040 // Hibernation Module Present.
+#define SYSCTL_DC1_TEMP 0x00000020 // Temp Sensor Present.
+#define SYSCTL_DC1_PLL 0x00000010 // PLL Present.
+#define SYSCTL_DC1_WDT 0x00000008 // Watchdog Timer Present.
+#define SYSCTL_DC1_SWO 0x00000004 // SWO Trace Port Present.
+#define SYSCTL_DC1_SWD 0x00000002 // SWD Present.
+#define SYSCTL_DC1_JTAG 0x00000001 // JTAG Present.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC2_COMP1 0x02000000 // Analog Comparator 1 Present.
+#define SYSCTL_DC2_COMP0 0x01000000 // Analog Comparator 0 Present.
+#define SYSCTL_DC2_TIMER3 0x00080000 // Timer 3 Present.
+#define SYSCTL_DC2_TIMER2 0x00040000 // Timer 2 Present.
+#define SYSCTL_DC2_TIMER1 0x00020000 // Timer 1 Present.
+#define SYSCTL_DC2_TIMER0 0x00010000 // Timer 0 Present.
+#define SYSCTL_DC2_I2C1 0x00004000 // I2C Module 1 Present.
+#define SYSCTL_DC2_I2C0 0x00001000 // I2C Module 0 Present.
+#define SYSCTL_DC2_QEI1 0x00000200 // QEI1 Present.
+#define SYSCTL_DC2_QEI0 0x00000100 // QEI0 Present.
+#define SYSCTL_DC2_SSI0 0x00000010 // SSI0 Present.
+#define SYSCTL_DC2_UART2 0x00000004 // UART2 Present.
+#define SYSCTL_DC2_UART1 0x00000002 // UART1 Present.
+#define SYSCTL_DC2_UART0 0x00000001 // UART0 Present.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC3 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC3_32KHZ 0x80000000 // 32KHz Input Clock Available.
+#define SYSCTL_DC3_CCP3 0x08000000 // CCP3 Pin Present.
+#define SYSCTL_DC3_CCP2 0x04000000 // CCP2 Pin Present.
+#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 Pin Present.
+#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 Pin Present.
+#define SYSCTL_DC3_ADC3 0x00080000 // ADC3 Pin Present.
+#define SYSCTL_DC3_ADC2 0x00040000 // ADC2 Pin Present.
+#define SYSCTL_DC3_ADC1 0x00020000 // ADC1 Pin Present.
+#define SYSCTL_DC3_ADC0 0x00010000 // ADC0 Pin Present.
+#define SYSCTL_DC3_PWMFAULT 0x00008000 // PWM Fault Pin Present.
+#define SYSCTL_DC3_C1PLUS 0x00000400 // C1+ Pin Present.
+#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- Pin Present.
+#define SYSCTL_DC3_C0O 0x00000100 // C0o Pin Present.
+#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ Pin Present.
+#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- Pin Present.
+#define SYSCTL_DC3_PWM5 0x00000020 // PWM5 Pin Present.
+#define SYSCTL_DC3_PWM4 0x00000010 // PWM4 Pin Present.
+#define SYSCTL_DC3_PWM3 0x00000008 // PWM3 Pin Present.
+#define SYSCTL_DC3_PWM2 0x00000004 // PWM2 Pin Present.
+#define SYSCTL_DC3_PWM1 0x00000002 // PWM1 Pin Present.
+#define SYSCTL_DC3_PWM0 0x00000001 // PWM0 Pin Present.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC4 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC4_EPHY0 0x40000000 // Ethernet PHY0 Present.
+#define SYSCTL_DC4_EMAC0 0x10000000 // Ethernet MAC0 Present.
+#define SYSCTL_DC4_GPIOG 0x00000040 // GPIO Port G Present.
+#define SYSCTL_DC4_GPIOF 0x00000020 // GPIO Port F Present.
+#define SYSCTL_DC4_GPIOE 0x00000010 // GPIO Port E Present.
+#define SYSCTL_DC4_GPIOD 0x00000008 // GPIO Port D Present.
+#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO Port C Present.
+#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO Port B Present.
+#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO Port A Present.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PBORCTL register.
+//
+//*****************************************************************************
+#define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR Interrupt or Reset.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_LDOPCTL register.
+//
+//*****************************************************************************
+#define SYSCTL_LDOPCTL_M 0x0000003F // LDO Output Voltage.
+#define SYSCTL_LDOPCTL_2_50V 0x00000000 // 2.50
+#define SYSCTL_LDOPCTL_2_45V 0x00000001 // 2.45
+#define SYSCTL_LDOPCTL_2_40V 0x00000002 // 2.40
+#define SYSCTL_LDOPCTL_2_35V 0x00000003 // 2.35
+#define SYSCTL_LDOPCTL_2_30V 0x00000004 // 2.30
+#define SYSCTL_LDOPCTL_2_25V 0x00000005 // 2.25
+#define SYSCTL_LDOPCTL_2_75V 0x0000001B // 2.75
+#define SYSCTL_LDOPCTL_2_70V 0x0000001C // 2.70
+#define SYSCTL_LDOPCTL_2_65V 0x0000001D // 2.65
+#define SYSCTL_LDOPCTL_2_60V 0x0000001E // 2.60
+#define SYSCTL_LDOPCTL_2_55V 0x0000001F // 2.55
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCR0 register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCR0_PWM 0x00100000 // PWM Reset Control.
+#define SYSCTL_SRCR0_ADC 0x00010000 // ADC0 Reset Control.
+#define SYSCTL_SRCR0_HIB 0x00000040 // HIB Reset Control.
+#define SYSCTL_SRCR0_WDT 0x00000008 // WDT Reset Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCR1 register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCR1_COMP1 0x02000000 // Analog Comp 1 Reset Control.
+#define SYSCTL_SRCR1_COMP0 0x01000000 // Analog Comp 0 Reset Control.
+#define SYSCTL_SRCR1_TIMER3 0x00080000 // Timer 3 Reset Control.
+#define SYSCTL_SRCR1_TIMER2 0x00040000 // Timer 2 Reset Control.
+#define SYSCTL_SRCR1_TIMER1 0x00020000 // Timer 1 Reset Control.
+#define SYSCTL_SRCR1_TIMER0 0x00010000 // Timer 0 Reset Control.
+#define SYSCTL_SRCR1_I2C1 0x00004000 // I2C1 Reset Control.
+#define SYSCTL_SRCR1_I2C0 0x00001000 // I2C0 Reset Control.
+#define SYSCTL_SRCR1_QEI1 0x00000200 // QEI1 Reset Control.
+#define SYSCTL_SRCR1_QEI0 0x00000100 // QEI0 Reset Control.
+#define SYSCTL_SRCR1_SSI0 0x00000010 // SSI0 Reset Control.
+#define SYSCTL_SRCR1_UART2 0x00000004 // UART2 Reset Control.
+#define SYSCTL_SRCR1_UART1 0x00000002 // UART1 Reset Control.
+#define SYSCTL_SRCR1_UART0 0x00000001 // UART0 Reset Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCR2 register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCR2_EPHY0 0x40000000 // PHY0 Reset Control.
+#define SYSCTL_SRCR2_EMAC0 0x10000000 // MAC0 Reset Control.
+#define SYSCTL_SRCR2_GPIOG 0x00000040 // Port G Reset Control.
+#define SYSCTL_SRCR2_GPIOF 0x00000020 // Port F Reset Control.
+#define SYSCTL_SRCR2_GPIOE 0x00000010 // Port E Reset Control.
+#define SYSCTL_SRCR2_GPIOD 0x00000008 // Port D Reset Control.
+#define SYSCTL_SRCR2_GPIOC 0x00000004 // Port C Reset Control.
+#define SYSCTL_SRCR2_GPIOB 0x00000002 // Port B Reset Control.
+#define SYSCTL_SRCR2_GPIOA 0x00000001 // Port A Reset Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RIS register.
+//
+//*****************************************************************************
+#define SYSCTL_RIS_PLLLRIS 0x00000040 // PLL Lock Raw Interrupt Status.
+#define SYSCTL_RIS_BORRIS 0x00000002 // Brown-Out Reset Raw Interrupt
+ // Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_IMC register.
+//
+//*****************************************************************************
+#define SYSCTL_IMC_PLLLIM 0x00000040 // PLL Lock Interrupt Mask.
+#define SYSCTL_IMC_BORIM 0x00000002 // Brown-Out Reset Interrupt Mask.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_MISC register.
+//
+//*****************************************************************************
+#define SYSCTL_MISC_PLLLMIS 0x00000040 // PLL Lock Masked Interrupt
+ // Status.
+#define SYSCTL_MISC_BORMIS 0x00000002 // BOR Masked Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RESC register.
+//
+//*****************************************************************************
+#define SYSCTL_RESC_LDO 0x00000020 // LDO Reset.
+#define SYSCTL_RESC_SW 0x00000010 // Software Reset.
+#define SYSCTL_RESC_WDT 0x00000008 // Watchdog Timer Reset.
+#define SYSCTL_RESC_BOR 0x00000004 // Brown-Out Reset.
+#define SYSCTL_RESC_POR 0x00000002 // Power-On Reset.
+#define SYSCTL_RESC_EXT 0x00000001 // External Reset.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCC register.
+//
+//*****************************************************************************
+#define SYSCTL_RCC_ACG 0x08000000 // Auto Clock Gating.
+#define SYSCTL_RCC_SYSDIV_M 0x07800000 // System Clock Divisor.
+#define SYSCTL_RCC_SYSDIV_2 0x00800000 // /2
+#define SYSCTL_RCC_SYSDIV_3 0x01000000 // /3
+#define SYSCTL_RCC_SYSDIV_4 0x01800000 // /4
+#define SYSCTL_RCC_SYSDIV_5 0x02000000 // /5
+#define SYSCTL_RCC_SYSDIV_6 0x02800000 // /6
+#define SYSCTL_RCC_SYSDIV_7 0x03000000 // /7
+#define SYSCTL_RCC_SYSDIV_8 0x03800000 // /8
+#define SYSCTL_RCC_SYSDIV_9 0x04000000 // /9
+#define SYSCTL_RCC_SYSDIV_10 0x04800000 // /10
+#define SYSCTL_RCC_SYSDIV_11 0x05000000 // /11
+#define SYSCTL_RCC_SYSDIV_12 0x05800000 // /12
+#define SYSCTL_RCC_SYSDIV_13 0x06000000 // /13
+#define SYSCTL_RCC_SYSDIV_14 0x06800000 // /14
+#define SYSCTL_RCC_SYSDIV_15 0x07000000 // /15
+#define SYSCTL_RCC_SYSDIV_16 0x07800000 // /16
+#define SYSCTL_RCC_USESYSDIV 0x00400000 // Enable System Clock Divider.
+#define SYSCTL_RCC_USEPWMDIV 0x00100000 // Enable PWM Clock Divisor.
+#define SYSCTL_RCC_PWMDIV_M 0x000E0000 // PWM Unit Clock Divisor.
+#define SYSCTL_RCC_PWMDIV_2 0x00000000 // /2
+#define SYSCTL_RCC_PWMDIV_4 0x00020000 // /4
+#define SYSCTL_RCC_PWMDIV_8 0x00040000 // /8
+#define SYSCTL_RCC_PWMDIV_16 0x00060000 // /16
+#define SYSCTL_RCC_PWMDIV_32 0x00080000 // /32
+#define SYSCTL_RCC_PWMDIV_64 0x000A0000 // /64
+#define SYSCTL_RCC_PWRDN 0x00002000 // PLL Power Down.
+#define SYSCTL_RCC_BYPASS 0x00000800 // PLL Bypass.
+#define SYSCTL_RCC_XTAL_M 0x000003C0 // Crystal Value.
+#define SYSCTL_RCC_XTAL_1MHZ 0x00000000 // 1.000
+#define SYSCTL_RCC_XTAL_1_84MHZ 0x00000040 // 1.8432
+#define SYSCTL_RCC_XTAL_2MHZ 0x00000080 // 2.000
+#define SYSCTL_RCC_XTAL_2_45MHZ 0x000000C0 // 2.4576
+#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100 // 3.579545 MHz
+#define SYSCTL_RCC_XTAL_3_68MHZ 0x00000140 // 3.6864 MHz
+#define SYSCTL_RCC_XTAL_4MHZ 0x00000180 // 4 MHz
+#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // 4.096 MHz
+#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // 4.9152 MHz
+#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // 5 MHz
+#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // 5.12 MHz
+#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // 6 MHz (reset value)
+#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // 6.144 MHz
+#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // 7.3728 MHz
+#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // 8 MHz
+#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // 8.192 MHz
+#define SYSCTL_RCC_OSCSRC_M 0x00000030 // Oscillator Source.
+#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // MOSC
+#define SYSCTL_RCC_OSCSRC_INT 0x00000010 // IOSC
+#define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // IOSC/4
+#define SYSCTL_RCC_OSCSRC_30 0x00000030 // 30 kHz
+#define SYSCTL_RCC_IOSCDIS 0x00000002 // Internal Oscillator Disable.
+#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main Oscillator Disable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PLLCFG register.
+//
+//*****************************************************************************
+#define SYSCTL_PLLCFG_F_M 0x00003FE0 // PLL F Value.
+#define SYSCTL_PLLCFG_R_M 0x0000001F // PLL R Value.
+#define SYSCTL_PLLCFG_F_S 5
+#define SYSCTL_PLLCFG_R_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCC2_USERCC2 0x80000000 // Use RCC2.
+#define SYSCTL_RCC2_SYSDIV2_M 0x1F800000 // System Clock Divisor.
+#define SYSCTL_RCC2_SYSDIV2_2 0x00800000 // System clock /2
+#define SYSCTL_RCC2_SYSDIV2_3 0x01000000 // System clock /3
+#define SYSCTL_RCC2_SYSDIV2_4 0x01800000 // System clock /4
+#define SYSCTL_RCC2_SYSDIV2_5 0x02000000 // System clock /5
+#define SYSCTL_RCC2_SYSDIV2_6 0x02800000 // System clock /6
+#define SYSCTL_RCC2_SYSDIV2_7 0x03000000 // System clock /7
+#define SYSCTL_RCC2_SYSDIV2_8 0x03800000 // System clock /8
+#define SYSCTL_RCC2_SYSDIV2_9 0x04000000 // System clock /9
+#define SYSCTL_RCC2_SYSDIV2_10 0x04800000 // System clock /10
+#define SYSCTL_RCC2_SYSDIV2_11 0x05000000 // System clock /11
+#define SYSCTL_RCC2_SYSDIV2_12 0x05800000 // System clock /12
+#define SYSCTL_RCC2_SYSDIV2_13 0x06000000 // System clock /13
+#define SYSCTL_RCC2_SYSDIV2_14 0x06800000 // System clock /14
+#define SYSCTL_RCC2_SYSDIV2_15 0x07000000 // System clock /15
+#define SYSCTL_RCC2_SYSDIV2_16 0x07800000 // System clock /16
+#define SYSCTL_RCC2_SYSDIV2_17 0x08000000 // System clock /17
+#define SYSCTL_RCC2_SYSDIV2_18 0x08800000 // System clock /18
+#define SYSCTL_RCC2_SYSDIV2_19 0x09000000 // System clock /19
+#define SYSCTL_RCC2_SYSDIV2_20 0x09800000 // System clock /20
+#define SYSCTL_RCC2_SYSDIV2_21 0x0A000000 // System clock /21
+#define SYSCTL_RCC2_SYSDIV2_22 0x0A800000 // System clock /22
+#define SYSCTL_RCC2_SYSDIV2_23 0x0B000000 // System clock /23
+#define SYSCTL_RCC2_SYSDIV2_24 0x0B800000 // System clock /24
+#define SYSCTL_RCC2_SYSDIV2_25 0x0C000000 // System clock /25
+#define SYSCTL_RCC2_SYSDIV2_26 0x0C800000 // System clock /26
+#define SYSCTL_RCC2_SYSDIV2_27 0x0D000000 // System clock /27
+#define SYSCTL_RCC2_SYSDIV2_28 0x0D800000 // System clock /28
+#define SYSCTL_RCC2_SYSDIV2_29 0x0E000000 // System clock /29
+#define SYSCTL_RCC2_SYSDIV2_30 0x0E800000 // System clock /30
+#define SYSCTL_RCC2_SYSDIV2_31 0x0F000000 // System clock /31
+#define SYSCTL_RCC2_SYSDIV2_32 0x0F800000 // System clock /32
+#define SYSCTL_RCC2_SYSDIV2_33 0x10000000 // System clock /33
+#define SYSCTL_RCC2_SYSDIV2_34 0x10800000 // System clock /34
+#define SYSCTL_RCC2_SYSDIV2_35 0x11000000 // System clock /35
+#define SYSCTL_RCC2_SYSDIV2_36 0x11800000 // System clock /36
+#define SYSCTL_RCC2_SYSDIV2_37 0x12000000 // System clock /37
+#define SYSCTL_RCC2_SYSDIV2_38 0x12800000 // System clock /38
+#define SYSCTL_RCC2_SYSDIV2_39 0x13000000 // System clock /39
+#define SYSCTL_RCC2_SYSDIV2_40 0x13800000 // System clock /40
+#define SYSCTL_RCC2_SYSDIV2_41 0x14000000 // System clock /41
+#define SYSCTL_RCC2_SYSDIV2_42 0x14800000 // System clock /42
+#define SYSCTL_RCC2_SYSDIV2_43 0x15000000 // System clock /43
+#define SYSCTL_RCC2_SYSDIV2_44 0x15800000 // System clock /44
+#define SYSCTL_RCC2_SYSDIV2_45 0x16000000 // System clock /45
+#define SYSCTL_RCC2_SYSDIV2_46 0x16800000 // System clock /46
+#define SYSCTL_RCC2_SYSDIV2_47 0x17000000 // System clock /47
+#define SYSCTL_RCC2_SYSDIV2_48 0x17800000 // System clock /48
+#define SYSCTL_RCC2_SYSDIV2_49 0x18000000 // System clock /49
+#define SYSCTL_RCC2_SYSDIV2_50 0x18800000 // System clock /50
+#define SYSCTL_RCC2_SYSDIV2_51 0x19000000 // System clock /51
+#define SYSCTL_RCC2_SYSDIV2_52 0x19800000 // System clock /52
+#define SYSCTL_RCC2_SYSDIV2_53 0x1A000000 // System clock /53
+#define SYSCTL_RCC2_SYSDIV2_54 0x1A800000 // System clock /54
+#define SYSCTL_RCC2_SYSDIV2_55 0x1B000000 // System clock /55
+#define SYSCTL_RCC2_SYSDIV2_56 0x1B800000 // System clock /56
+#define SYSCTL_RCC2_SYSDIV2_57 0x1C000000 // System clock /57
+#define SYSCTL_RCC2_SYSDIV2_58 0x1C800000 // System clock /58
+#define SYSCTL_RCC2_SYSDIV2_59 0x1D000000 // System clock /59
+#define SYSCTL_RCC2_SYSDIV2_60 0x1D800000 // System clock /60
+#define SYSCTL_RCC2_SYSDIV2_61 0x1E000000 // System clock /61
+#define SYSCTL_RCC2_SYSDIV2_62 0x1E800000 // System clock /62
+#define SYSCTL_RCC2_SYSDIV2_63 0x1F000000 // System clock /63
+#define SYSCTL_RCC2_SYSDIV2_64 0x1F800000 // System clock /64
+#define SYSCTL_RCC2_PWRDN2 0x00002000 // Power-Down PLL.
+#define SYSCTL_RCC2_BYPASS2 0x00000800 // Bypass PLL.
+#define SYSCTL_RCC2_OSCSRC2_M 0x00000070 // Oscillator Source.
+#define SYSCTL_RCC2_OSCSRC2_MO 0x00000000 // MOSC
+#define SYSCTL_RCC2_OSCSRC2_IO 0x00000010 // IOSC
+#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020 // IOSC/4
+#define SYSCTL_RCC2_OSCSRC2_30 0x00000030 // 30 kHz
+#define SYSCTL_RCC2_OSCSRC2_32 0x00000070 // 32 kHz
+#define SYSCTL_RCC2_SYSDIV2_S 23
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGC0_PWM 0x00100000 // PWM Clock Gating Control.
+#define SYSCTL_RCGC0_ADC 0x00010000 // ADC0 Clock Gating Control.
+#define SYSCTL_RCGC0_ADCSPD_M 0x00000300 // ADC Sample Speed.
+#define SYSCTL_RCGC0_ADCSPD125K 0x00000000 // 125K samples/second
+#define SYSCTL_RCGC0_ADCSPD250K 0x00000100 // 250K samples/second
+#define SYSCTL_RCGC0_ADCSPD500K 0x00000200 // 500K samples/second
+#define SYSCTL_RCGC0_ADCSPD1M 0x00000300 // 1M samples/second
+#define SYSCTL_RCGC0_HIB 0x00000040 // HIB Clock Gating Control.
+#define SYSCTL_RCGC0_WDT 0x00000008 // WDT Clock Gating Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock
+ // Gating.
+#define SYSCTL_RCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock
+ // Gating.
+#define SYSCTL_RCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control.
+#define SYSCTL_RCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control.
+#define SYSCTL_RCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control.
+#define SYSCTL_RCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control.
+#define SYSCTL_RCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control.
+#define SYSCTL_RCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control.
+#define SYSCTL_RCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control.
+#define SYSCTL_RCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control.
+#define SYSCTL_RCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control.
+#define SYSCTL_RCGC1_UART2 0x00000004 // UART2 Clock Gating Control.
+#define SYSCTL_RCGC1_UART1 0x00000002 // UART1 Clock Gating Control.
+#define SYSCTL_RCGC1_UART0 0x00000001 // UART0 Clock Gating Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGC2_EPHY0 0x40000000 // PHY0 Clock Gating Control.
+#define SYSCTL_RCGC2_EMAC0 0x10000000 // MAC0 Clock Gating Control.
+#define SYSCTL_RCGC2_GPIOG 0x00000040 // Port G Clock Gating Control.
+#define SYSCTL_RCGC2_GPIOF 0x00000020 // Port F Clock Gating Control.
+#define SYSCTL_RCGC2_GPIOE 0x00000010 // Port E Clock Gating Control.
+#define SYSCTL_RCGC2_GPIOD 0x00000008 // Port D Clock Gating Control.
+#define SYSCTL_RCGC2_GPIOC 0x00000004 // Port C Clock Gating Control.
+#define SYSCTL_RCGC2_GPIOB 0x00000002 // Port B Clock Gating Control.
+#define SYSCTL_RCGC2_GPIOA 0x00000001 // Port A Clock Gating Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGC0_PWM 0x00100000 // PWM Clock Gating Control.
+#define SYSCTL_SCGC0_ADC 0x00010000 // ADC0 Clock Gating Control.
+#define SYSCTL_SCGC0_ADCSPD_M 0x00000300 // ADC Sample Speed.
+#define SYSCTL_SCGC0_ADCSPD125K 0x00000000 // 125K samples/second
+#define SYSCTL_SCGC0_ADCSPD250K 0x00000100 // 250K samples/second
+#define SYSCTL_SCGC0_ADCSPD500K 0x00000200 // 500K samples/second
+#define SYSCTL_SCGC0_ADCSPD1M 0x00000300 // 1M samples/second
+#define SYSCTL_SCGC0_HIB 0x00000040 // HIB Clock Gating Control.
+#define SYSCTL_SCGC0_WDT 0x00000008 // WDT Clock Gating Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock
+ // Gating.
+#define SYSCTL_SCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock
+ // Gating.
+#define SYSCTL_SCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control.
+#define SYSCTL_SCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control.
+#define SYSCTL_SCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control.
+#define SYSCTL_SCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control.
+#define SYSCTL_SCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control.
+#define SYSCTL_SCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control.
+#define SYSCTL_SCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control.
+#define SYSCTL_SCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control.
+#define SYSCTL_SCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control.
+#define SYSCTL_SCGC1_UART2 0x00000004 // UART2 Clock Gating Control.
+#define SYSCTL_SCGC1_UART1 0x00000002 // UART1 Clock Gating Control.
+#define SYSCTL_SCGC1_UART0 0x00000001 // UART0 Clock Gating Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGC2_EPHY0 0x40000000 // PHY0 Clock Gating Control.
+#define SYSCTL_SCGC2_EMAC0 0x10000000 // MAC0 Clock Gating Control.
+#define SYSCTL_SCGC2_GPIOG 0x00000040 // Port G Clock Gating Control.
+#define SYSCTL_SCGC2_GPIOF 0x00000020 // Port F Clock Gating Control.
+#define SYSCTL_SCGC2_GPIOE 0x00000010 // Port E Clock Gating Control.
+#define SYSCTL_SCGC2_GPIOD 0x00000008 // Port D Clock Gating Control.
+#define SYSCTL_SCGC2_GPIOC 0x00000004 // Port C Clock Gating Control.
+#define SYSCTL_SCGC2_GPIOB 0x00000002 // Port B Clock Gating Control.
+#define SYSCTL_SCGC2_GPIOA 0x00000001 // Port A Clock Gating Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGC0_PWM 0x00100000 // PWM Clock Gating Control.
+#define SYSCTL_DCGC0_ADC 0x00010000 // ADC0 Clock Gating Control.
+#define SYSCTL_DCGC0_ADCSPD_M 0x00000300 // ADC Sample Speed.
+#define SYSCTL_DCGC0_ADCSPD125K 0x00000000 // 125K samples/second
+#define SYSCTL_DCGC0_ADCSPD250K 0x00000100 // 250K samples/second
+#define SYSCTL_DCGC0_ADCSPD500K 0x00000200 // 500K samples/second
+#define SYSCTL_DCGC0_ADCSPD1M 0x00000300 // 1M samples/second
+#define SYSCTL_DCGC0_HIB 0x00000040 // HIB Clock Gating Control.
+#define SYSCTL_DCGC0_WDT 0x00000008 // WDT Clock Gating Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock
+ // Gating.
+#define SYSCTL_DCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock
+ // Gating.
+#define SYSCTL_DCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control.
+#define SYSCTL_DCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control.
+#define SYSCTL_DCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control.
+#define SYSCTL_DCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control.
+#define SYSCTL_DCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control.
+#define SYSCTL_DCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control.
+#define SYSCTL_DCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control.
+#define SYSCTL_DCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control.
+#define SYSCTL_DCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control.
+#define SYSCTL_DCGC1_UART2 0x00000004 // UART2 Clock Gating Control.
+#define SYSCTL_DCGC1_UART1 0x00000002 // UART1 Clock Gating Control.
+#define SYSCTL_DCGC1_UART0 0x00000001 // UART0 Clock Gating Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGC2_EPHY0 0x40000000 // PHY0 Clock Gating Control.
+#define SYSCTL_DCGC2_EMAC0 0x10000000 // MAC0 Clock Gating Control.
+#define SYSCTL_DCGC2_GPIOG 0x00000040 // Port G Clock Gating Control.
+#define SYSCTL_DCGC2_GPIOF 0x00000020 // Port F Clock Gating Control.
+#define SYSCTL_DCGC2_GPIOE 0x00000010 // Port E Clock Gating Control.
+#define SYSCTL_DCGC2_GPIOD 0x00000008 // Port D Clock Gating Control.
+#define SYSCTL_DCGC2_GPIOC 0x00000004 // Port C Clock Gating Control.
+#define SYSCTL_DCGC2_GPIOB 0x00000002 // Port B Clock Gating Control.
+#define SYSCTL_DCGC2_GPIOA 0x00000001 // Port A Clock Gating Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DSLPCLKCFG
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DSLPCLKCFG_D_M 0x1F800000 // Divider Field Override.
+#define SYSCTL_DSLPCLKCFG_O_M 0x00000070 // Clock Source.
+#define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000 // MOSC
+#define SYSCTL_DSLPCLKCFG_O_IO 0x00000010 // IOSC
+#define SYSCTL_DSLPCLKCFG_O_30 0x00000030 // 30 kHz
+#define SYSCTL_DSLPCLKCFG_O_32 0x00000070 // 32 kHz
+#define SYSCTL_DSLPCLKCFG_D_S 23
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_INT_TYPE register.
+//
+//*****************************************************************************
+#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32)
+#define NVIC_INT_TYPE_LINES_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_ST_CTRL_COUNT 0x00010000 // Count flag
+#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source
+#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt enable
+#define NVIC_ST_CTRL_ENABLE 0x00000001 // Counter mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_RELOAD register.
+//
+//*****************************************************************************
+#define NVIC_ST_RELOAD_M 0x00FFFFFF // Counter load value
+#define NVIC_ST_RELOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_CURRENT
+// register.
+//
+//*****************************************************************************
+#define NVIC_ST_CURRENT_M 0x00FFFFFF // Counter current value
+#define NVIC_ST_CURRENT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_CAL register.
+//
+//*****************************************************************************
+#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock
+#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew
+#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value
+#define NVIC_ST_CAL_ONEMS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN0 register.
+//
+//*****************************************************************************
+#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable
+#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable
+#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable
+#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable
+#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable
+#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable
+#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable
+#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable
+#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable
+#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable
+#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable
+#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable
+#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable
+#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable
+#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable
+#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable
+#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable
+#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable
+#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable
+#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable
+#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable
+#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable
+#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable
+#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable
+#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable
+#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable
+#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable
+#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable
+#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable
+#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable
+#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable
+#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN1 register.
+//
+//*****************************************************************************
+#define NVIC_EN1_INT59 0x08000000 // Interrupt 59 enable
+#define NVIC_EN1_INT58 0x04000000 // Interrupt 58 enable
+#define NVIC_EN1_INT57 0x02000000 // Interrupt 57 enable
+#define NVIC_EN1_INT56 0x01000000 // Interrupt 56 enable
+#define NVIC_EN1_INT55 0x00800000 // Interrupt 55 enable
+#define NVIC_EN1_INT54 0x00400000 // Interrupt 54 enable
+#define NVIC_EN1_INT53 0x00200000 // Interrupt 53 enable
+#define NVIC_EN1_INT52 0x00100000 // Interrupt 52 enable
+#define NVIC_EN1_INT51 0x00080000 // Interrupt 51 enable
+#define NVIC_EN1_INT50 0x00040000 // Interrupt 50 enable
+#define NVIC_EN1_INT49 0x00020000 // Interrupt 49 enable
+#define NVIC_EN1_INT48 0x00010000 // Interrupt 48 enable
+#define NVIC_EN1_INT47 0x00008000 // Interrupt 47 enable
+#define NVIC_EN1_INT46 0x00004000 // Interrupt 46 enable
+#define NVIC_EN1_INT45 0x00002000 // Interrupt 45 enable
+#define NVIC_EN1_INT44 0x00001000 // Interrupt 44 enable
+#define NVIC_EN1_INT43 0x00000800 // Interrupt 43 enable
+#define NVIC_EN1_INT42 0x00000400 // Interrupt 42 enable
+#define NVIC_EN1_INT41 0x00000200 // Interrupt 41 enable
+#define NVIC_EN1_INT40 0x00000100 // Interrupt 40 enable
+#define NVIC_EN1_INT39 0x00000080 // Interrupt 39 enable
+#define NVIC_EN1_INT38 0x00000040 // Interrupt 38 enable
+#define NVIC_EN1_INT37 0x00000020 // Interrupt 37 enable
+#define NVIC_EN1_INT36 0x00000010 // Interrupt 36 enable
+#define NVIC_EN1_INT35 0x00000008 // Interrupt 35 enable
+#define NVIC_EN1_INT34 0x00000004 // Interrupt 34 enable
+#define NVIC_EN1_INT33 0x00000002 // Interrupt 33 enable
+#define NVIC_EN1_INT32 0x00000001 // Interrupt 32 enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS0 register.
+//
+//*****************************************************************************
+#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable
+#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable
+#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable
+#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable
+#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable
+#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable
+#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable
+#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable
+#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable
+#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable
+#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable
+#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable
+#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable
+#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable
+#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable
+#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable
+#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable
+#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable
+#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable
+#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable
+#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable
+#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable
+#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable
+#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable
+#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable
+#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable
+#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable
+#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable
+#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable
+#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable
+#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable
+#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS1 register.
+//
+//*****************************************************************************
+#define NVIC_DIS1_INT59 0x08000000 // Interrupt 59 disable
+#define NVIC_DIS1_INT58 0x04000000 // Interrupt 58 disable
+#define NVIC_DIS1_INT57 0x02000000 // Interrupt 57 disable
+#define NVIC_DIS1_INT56 0x01000000 // Interrupt 56 disable
+#define NVIC_DIS1_INT55 0x00800000 // Interrupt 55 disable
+#define NVIC_DIS1_INT54 0x00400000 // Interrupt 54 disable
+#define NVIC_DIS1_INT53 0x00200000 // Interrupt 53 disable
+#define NVIC_DIS1_INT52 0x00100000 // Interrupt 52 disable
+#define NVIC_DIS1_INT51 0x00080000 // Interrupt 51 disable
+#define NVIC_DIS1_INT50 0x00040000 // Interrupt 50 disable
+#define NVIC_DIS1_INT49 0x00020000 // Interrupt 49 disable
+#define NVIC_DIS1_INT48 0x00010000 // Interrupt 48 disable
+#define NVIC_DIS1_INT47 0x00008000 // Interrupt 47 disable
+#define NVIC_DIS1_INT46 0x00004000 // Interrupt 46 disable
+#define NVIC_DIS1_INT45 0x00002000 // Interrupt 45 disable
+#define NVIC_DIS1_INT44 0x00001000 // Interrupt 44 disable
+#define NVIC_DIS1_INT43 0x00000800 // Interrupt 43 disable
+#define NVIC_DIS1_INT42 0x00000400 // Interrupt 42 disable
+#define NVIC_DIS1_INT41 0x00000200 // Interrupt 41 disable
+#define NVIC_DIS1_INT40 0x00000100 // Interrupt 40 disable
+#define NVIC_DIS1_INT39 0x00000080 // Interrupt 39 disable
+#define NVIC_DIS1_INT38 0x00000040 // Interrupt 38 disable
+#define NVIC_DIS1_INT37 0x00000020 // Interrupt 37 disable
+#define NVIC_DIS1_INT36 0x00000010 // Interrupt 36 disable
+#define NVIC_DIS1_INT35 0x00000008 // Interrupt 35 disable
+#define NVIC_DIS1_INT34 0x00000004 // Interrupt 34 disable
+#define NVIC_DIS1_INT33 0x00000002 // Interrupt 33 disable
+#define NVIC_DIS1_INT32 0x00000001 // Interrupt 32 disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND0 register.
+//
+//*****************************************************************************
+#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend
+#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend
+#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend
+#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend
+#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend
+#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend
+#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend
+#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend
+#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend
+#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend
+#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend
+#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend
+#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend
+#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend
+#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend
+#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend
+#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend
+#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend
+#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend
+#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend
+#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend
+#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend
+#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend
+#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend
+#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend
+#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend
+#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend
+#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend
+#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend
+#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend
+#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend
+#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND1 register.
+//
+//*****************************************************************************
+#define NVIC_PEND1_INT59 0x08000000 // Interrupt 59 pend
+#define NVIC_PEND1_INT58 0x04000000 // Interrupt 58 pend
+#define NVIC_PEND1_INT57 0x02000000 // Interrupt 57 pend
+#define NVIC_PEND1_INT56 0x01000000 // Interrupt 56 pend
+#define NVIC_PEND1_INT55 0x00800000 // Interrupt 55 pend
+#define NVIC_PEND1_INT54 0x00400000 // Interrupt 54 pend
+#define NVIC_PEND1_INT53 0x00200000 // Interrupt 53 pend
+#define NVIC_PEND1_INT52 0x00100000 // Interrupt 52 pend
+#define NVIC_PEND1_INT51 0x00080000 // Interrupt 51 pend
+#define NVIC_PEND1_INT50 0x00040000 // Interrupt 50 pend
+#define NVIC_PEND1_INT49 0x00020000 // Interrupt 49 pend
+#define NVIC_PEND1_INT48 0x00010000 // Interrupt 48 pend
+#define NVIC_PEND1_INT47 0x00008000 // Interrupt 47 pend
+#define NVIC_PEND1_INT46 0x00004000 // Interrupt 46 pend
+#define NVIC_PEND1_INT45 0x00002000 // Interrupt 45 pend
+#define NVIC_PEND1_INT44 0x00001000 // Interrupt 44 pend
+#define NVIC_PEND1_INT43 0x00000800 // Interrupt 43 pend
+#define NVIC_PEND1_INT42 0x00000400 // Interrupt 42 pend
+#define NVIC_PEND1_INT41 0x00000200 // Interrupt 41 pend
+#define NVIC_PEND1_INT40 0x00000100 // Interrupt 40 pend
+#define NVIC_PEND1_INT39 0x00000080 // Interrupt 39 pend
+#define NVIC_PEND1_INT38 0x00000040 // Interrupt 38 pend
+#define NVIC_PEND1_INT37 0x00000020 // Interrupt 37 pend
+#define NVIC_PEND1_INT36 0x00000010 // Interrupt 36 pend
+#define NVIC_PEND1_INT35 0x00000008 // Interrupt 35 pend
+#define NVIC_PEND1_INT34 0x00000004 // Interrupt 34 pend
+#define NVIC_PEND1_INT33 0x00000002 // Interrupt 33 pend
+#define NVIC_PEND1_INT32 0x00000001 // Interrupt 32 pend
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND0 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend
+#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend
+#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend
+#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend
+#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend
+#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend
+#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend
+#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend
+#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend
+#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend
+#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend
+#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend
+#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend
+#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend
+#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend
+#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend
+#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend
+#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend
+#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend
+#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend
+#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend
+#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend
+#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend
+#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend
+#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend
+#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend
+#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend
+#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend
+#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend
+#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend
+#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend
+#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND1 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND1_INT59 0x08000000 // Interrupt 59 unpend
+#define NVIC_UNPEND1_INT58 0x04000000 // Interrupt 58 unpend
+#define NVIC_UNPEND1_INT57 0x02000000 // Interrupt 57 unpend
+#define NVIC_UNPEND1_INT56 0x01000000 // Interrupt 56 unpend
+#define NVIC_UNPEND1_INT55 0x00800000 // Interrupt 55 unpend
+#define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend
+#define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend
+#define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend
+#define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend
+#define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend
+#define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend
+#define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend
+#define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend
+#define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend
+#define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend
+#define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend
+#define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend
+#define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend
+#define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend
+#define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend
+#define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend
+#define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend
+#define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend
+#define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend
+#define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend
+#define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend
+#define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend
+#define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE0 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active
+#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active
+#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active
+#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active
+#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active
+#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active
+#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active
+#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active
+#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active
+#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active
+#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active
+#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active
+#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active
+#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active
+#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active
+#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active
+#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active
+#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active
+#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active
+#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active
+#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active
+#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active
+#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active
+#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active
+#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active
+#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active
+#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active
+#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active
+#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active
+#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active
+#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active
+#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE1 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE1_INT59 0x08000000 // Interrupt 59 active
+#define NVIC_ACTIVE1_INT58 0x04000000 // Interrupt 58 active
+#define NVIC_ACTIVE1_INT57 0x02000000 // Interrupt 57 active
+#define NVIC_ACTIVE1_INT56 0x01000000 // Interrupt 56 active
+#define NVIC_ACTIVE1_INT55 0x00800000 // Interrupt 55 active
+#define NVIC_ACTIVE1_INT54 0x00400000 // Interrupt 54 active
+#define NVIC_ACTIVE1_INT53 0x00200000 // Interrupt 53 active
+#define NVIC_ACTIVE1_INT52 0x00100000 // Interrupt 52 active
+#define NVIC_ACTIVE1_INT51 0x00080000 // Interrupt 51 active
+#define NVIC_ACTIVE1_INT50 0x00040000 // Interrupt 50 active
+#define NVIC_ACTIVE1_INT49 0x00020000 // Interrupt 49 active
+#define NVIC_ACTIVE1_INT48 0x00010000 // Interrupt 48 active
+#define NVIC_ACTIVE1_INT47 0x00008000 // Interrupt 47 active
+#define NVIC_ACTIVE1_INT46 0x00004000 // Interrupt 46 active
+#define NVIC_ACTIVE1_INT45 0x00002000 // Interrupt 45 active
+#define NVIC_ACTIVE1_INT44 0x00001000 // Interrupt 44 active
+#define NVIC_ACTIVE1_INT43 0x00000800 // Interrupt 43 active
+#define NVIC_ACTIVE1_INT42 0x00000400 // Interrupt 42 active
+#define NVIC_ACTIVE1_INT41 0x00000200 // Interrupt 41 active
+#define NVIC_ACTIVE1_INT40 0x00000100 // Interrupt 40 active
+#define NVIC_ACTIVE1_INT39 0x00000080 // Interrupt 39 active
+#define NVIC_ACTIVE1_INT38 0x00000040 // Interrupt 38 active
+#define NVIC_ACTIVE1_INT37 0x00000020 // Interrupt 37 active
+#define NVIC_ACTIVE1_INT36 0x00000010 // Interrupt 36 active
+#define NVIC_ACTIVE1_INT35 0x00000008 // Interrupt 35 active
+#define NVIC_ACTIVE1_INT34 0x00000004 // Interrupt 34 active
+#define NVIC_ACTIVE1_INT33 0x00000002 // Interrupt 33 active
+#define NVIC_ACTIVE1_INT32 0x00000001 // Interrupt 32 active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI0 register.
+//
+//*****************************************************************************
+#define NVIC_PRI0_INT3_M 0xFF000000 // Interrupt 3 priority mask
+#define NVIC_PRI0_INT2_M 0x00FF0000 // Interrupt 2 priority mask
+#define NVIC_PRI0_INT1_M 0x0000FF00 // Interrupt 1 priority mask
+#define NVIC_PRI0_INT0_M 0x000000FF // Interrupt 0 priority mask
+#define NVIC_PRI0_INT3_S 24
+#define NVIC_PRI0_INT2_S 16
+#define NVIC_PRI0_INT1_S 8
+#define NVIC_PRI0_INT0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI1 register.
+//
+//*****************************************************************************
+#define NVIC_PRI1_INT7_M 0xFF000000 // Interrupt 7 priority mask
+#define NVIC_PRI1_INT6_M 0x00FF0000 // Interrupt 6 priority mask
+#define NVIC_PRI1_INT5_M 0x0000FF00 // Interrupt 5 priority mask
+#define NVIC_PRI1_INT4_M 0x000000FF // Interrupt 4 priority mask
+#define NVIC_PRI1_INT7_S 24
+#define NVIC_PRI1_INT6_S 16
+#define NVIC_PRI1_INT5_S 8
+#define NVIC_PRI1_INT4_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI2 register.
+//
+//*****************************************************************************
+#define NVIC_PRI2_INT11_M 0xFF000000 // Interrupt 11 priority mask
+#define NVIC_PRI2_INT10_M 0x00FF0000 // Interrupt 10 priority mask
+#define NVIC_PRI2_INT9_M 0x0000FF00 // Interrupt 9 priority mask
+#define NVIC_PRI2_INT8_M 0x000000FF // Interrupt 8 priority mask
+#define NVIC_PRI2_INT11_S 24
+#define NVIC_PRI2_INT10_S 16
+#define NVIC_PRI2_INT9_S 8
+#define NVIC_PRI2_INT8_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI3 register.
+//
+//*****************************************************************************
+#define NVIC_PRI3_INT15_M 0xFF000000 // Interrupt 15 priority mask
+#define NVIC_PRI3_INT14_M 0x00FF0000 // Interrupt 14 priority mask
+#define NVIC_PRI3_INT13_M 0x0000FF00 // Interrupt 13 priority mask
+#define NVIC_PRI3_INT12_M 0x000000FF // Interrupt 12 priority mask
+#define NVIC_PRI3_INT15_S 24
+#define NVIC_PRI3_INT14_S 16
+#define NVIC_PRI3_INT13_S 8
+#define NVIC_PRI3_INT12_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI4 register.
+//
+//*****************************************************************************
+#define NVIC_PRI4_INT19_M 0xFF000000 // Interrupt 19 priority mask
+#define NVIC_PRI4_INT18_M 0x00FF0000 // Interrupt 18 priority mask
+#define NVIC_PRI4_INT17_M 0x0000FF00 // Interrupt 17 priority mask
+#define NVIC_PRI4_INT16_M 0x000000FF // Interrupt 16 priority mask
+#define NVIC_PRI4_INT19_S 24
+#define NVIC_PRI4_INT18_S 16
+#define NVIC_PRI4_INT17_S 8
+#define NVIC_PRI4_INT16_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI5 register.
+//
+//*****************************************************************************
+#define NVIC_PRI5_INT23_M 0xFF000000 // Interrupt 23 priority mask
+#define NVIC_PRI5_INT22_M 0x00FF0000 // Interrupt 22 priority mask
+#define NVIC_PRI5_INT21_M 0x0000FF00 // Interrupt 21 priority mask
+#define NVIC_PRI5_INT20_M 0x000000FF // Interrupt 20 priority mask
+#define NVIC_PRI5_INT23_S 24
+#define NVIC_PRI5_INT22_S 16
+#define NVIC_PRI5_INT21_S 8
+#define NVIC_PRI5_INT20_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI6 register.
+//
+//*****************************************************************************
+#define NVIC_PRI6_INT27_M 0xFF000000 // Interrupt 27 priority mask
+#define NVIC_PRI6_INT26_M 0x00FF0000 // Interrupt 26 priority mask
+#define NVIC_PRI6_INT25_M 0x0000FF00 // Interrupt 25 priority mask
+#define NVIC_PRI6_INT24_M 0x000000FF // Interrupt 24 priority mask
+#define NVIC_PRI6_INT27_S 24
+#define NVIC_PRI6_INT26_S 16
+#define NVIC_PRI6_INT25_S 8
+#define NVIC_PRI6_INT24_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI7 register.
+//
+//*****************************************************************************
+#define NVIC_PRI7_INT31_M 0xFF000000 // Interrupt 31 priority mask
+#define NVIC_PRI7_INT30_M 0x00FF0000 // Interrupt 30 priority mask
+#define NVIC_PRI7_INT29_M 0x0000FF00 // Interrupt 29 priority mask
+#define NVIC_PRI7_INT28_M 0x000000FF // Interrupt 28 priority mask
+#define NVIC_PRI7_INT31_S 24
+#define NVIC_PRI7_INT30_S 16
+#define NVIC_PRI7_INT29_S 8
+#define NVIC_PRI7_INT28_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI8 register.
+//
+//*****************************************************************************
+#define NVIC_PRI8_INT35_M 0xFF000000 // Interrupt 35 priority mask
+#define NVIC_PRI8_INT34_M 0x00FF0000 // Interrupt 34 priority mask
+#define NVIC_PRI8_INT33_M 0x0000FF00 // Interrupt 33 priority mask
+#define NVIC_PRI8_INT32_M 0x000000FF // Interrupt 32 priority mask
+#define NVIC_PRI8_INT35_S 24
+#define NVIC_PRI8_INT34_S 16
+#define NVIC_PRI8_INT33_S 8
+#define NVIC_PRI8_INT32_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI9 register.
+//
+//*****************************************************************************
+#define NVIC_PRI9_INT39_M 0xFF000000 // Interrupt 39 priority mask
+#define NVIC_PRI9_INT38_M 0x00FF0000 // Interrupt 38 priority mask
+#define NVIC_PRI9_INT37_M 0x0000FF00 // Interrupt 37 priority mask
+#define NVIC_PRI9_INT36_M 0x000000FF // Interrupt 36 priority mask
+#define NVIC_PRI9_INT39_S 24
+#define NVIC_PRI9_INT38_S 16
+#define NVIC_PRI9_INT37_S 8
+#define NVIC_PRI9_INT36_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI10 register.
+//
+//*****************************************************************************
+#define NVIC_PRI10_INT43_M 0xFF000000 // Interrupt 43 priority mask
+#define NVIC_PRI10_INT42_M 0x00FF0000 // Interrupt 42 priority mask
+#define NVIC_PRI10_INT41_M 0x0000FF00 // Interrupt 41 priority mask
+#define NVIC_PRI10_INT40_M 0x000000FF // Interrupt 40 priority mask
+#define NVIC_PRI10_INT43_S 24
+#define NVIC_PRI10_INT42_S 16
+#define NVIC_PRI10_INT41_S 8
+#define NVIC_PRI10_INT40_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_CPUID register.
+//
+//*****************************************************************************
+#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer
+#define NVIC_CPUID_VAR_M 0x00F00000 // Variant
+#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Processor part number
+#define NVIC_CPUID_REV_M 0x0000000F // Revision
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_INT_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_INT_CTRL_NMI_SET 0x80000000 // Pend a NMI
+#define NVIC_INT_CTRL_PEND_SV 0x10000000 // Pend a PendSV
+#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // Unpend a PendSV
+#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug interrupt handling
+#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Debug interrupt pending
+#define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000 // Highest pending exception
+#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to base
+#define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF // Current active exception
+#define NVIC_INT_CTRL_VEC_PEN_S 12
+#define NVIC_INT_CTRL_VEC_ACT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_VTABLE register.
+//
+//*****************************************************************************
+#define NVIC_VTABLE_BASE 0x20000000 // Vector table base
+#define NVIC_VTABLE_OFFSET_M 0x1FFFFF00 // Vector table offset
+#define NVIC_VTABLE_OFFSET_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_APINT register.
+//
+//*****************************************************************************
+#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Vector key mask
+#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key
+#define NVIC_APINT_ENDIANESS 0x00008000 // Data endianess
+#define NVIC_APINT_PRIGROUP_M 0x00000700 // Priority group
+#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split
+#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split
+#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split
+#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split
+#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split
+#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split
+#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split
+#define NVIC_APINT_SYSRESETREQ 0x00000004 // System reset request
+#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear active NMI/fault info
+#define NVIC_APINT_VECT_RESET 0x00000001 // System reset
+#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wakeup on pend
+#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep sleep enable
+#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR exit
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_CFG_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore bus fault in NMI/fault
+#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on divide by 0
+#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on unaligned access
+#define NVIC_CFG_CTRL_DEEP_PEND 0x00000004 // Allow deep interrupt trigger
+#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow main interrupt trigger
+#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread state control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_PRI1 register.
+//
+//*****************************************************************************
+#define NVIC_SYS_PRI1_RES_M 0xFF000000 // Priority of reserved handler
+#define NVIC_SYS_PRI1_USAGE_M 0x00FF0000 // Priority of usage fault handler
+#define NVIC_SYS_PRI1_BUS_M 0x0000FF00 // Priority of bus fault handler
+#define NVIC_SYS_PRI1_MEM_M 0x000000FF // Priority of mem manage handler
+#define NVIC_SYS_PRI1_USAGE_S 16
+#define NVIC_SYS_PRI1_BUS_S 8
+#define NVIC_SYS_PRI1_MEM_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_PRI2 register.
+//
+//*****************************************************************************
+#define NVIC_SYS_PRI2_SVC_M 0xFF000000 // Priority of SVCall handler
+#define NVIC_SYS_PRI2_RES_M 0x00FFFFFF // Priority of reserved handlers
+#define NVIC_SYS_PRI2_SVC_S 24
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_PRI3 register.
+//
+//*****************************************************************************
+#define NVIC_SYS_PRI3_TICK_M 0xFF000000 // Priority of Sys Tick handler
+#define NVIC_SYS_PRI3_PENDSV_M 0x00FF0000 // Priority of PendSV handler
+#define NVIC_SYS_PRI3_RES_M 0x0000FF00 // Priority of reserved handler
+#define NVIC_SYS_PRI3_DEBUG_M 0x000000FF // Priority of debug handler
+#define NVIC_SYS_PRI3_TICK_S 24
+#define NVIC_SYS_PRI3_PENDSV_S 16
+#define NVIC_SYS_PRI3_DEBUG_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_HND_CTRL
+// register.
+//
+//*****************************************************************************
+#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage fault enable
+#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus fault enable
+#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Mem manage fault enable
+#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVCall is pended
+#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus fault is pended
+#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // Sys tick is active
+#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV is active
+#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Monitor is active
+#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVCall is active
+#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage fault is active
+#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus fault is active
+#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Mem manage is active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FAULT_STAT
+// register.
+//
+//*****************************************************************************
+#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide by zero fault
+#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned access fault
+#define NVIC_FAULT_STAT_NOCP 0x00080000 // No coprocessor fault
+#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC fault
+#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid state fault
+#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined instruction fault
+#define NVIC_FAULT_STAT_BFARV 0x00008000 // BFAR is valid
+#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack bus fault
+#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack bus fault
+#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise data bus error
+#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise data bus error
+#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction bus fault
+#define NVIC_FAULT_STAT_MMARV 0x00000080 // MMAR is valid
+#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack access violation
+#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack access violation
+#define NVIC_FAULT_STAT_DERR 0x00000002 // Data access violation
+#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction access violation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_HFAULT_STAT
+// register.
+//
+//*****************************************************************************
+#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug event
+#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Cannot execute fault handler
+#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector table read fault
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DEBUG_STAT
+// register.
+//
+//*****************************************************************************
+#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted
+#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch
+#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match
+#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction
+#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MM_ADDR register.
+//
+//*****************************************************************************
+#define NVIC_MM_ADDR_M 0xFFFFFFFF // Data fault address
+#define NVIC_MM_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FAULT_ADDR
+// register.
+//
+//*****************************************************************************
+#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Data bus fault address
+#define NVIC_FAULT_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_TYPE register.
+//
+//*****************************************************************************
+#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I regions
+#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D regions
+#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or unified MPU
+#define NVIC_MPU_TYPE_IREGION_S 16
+#define NVIC_MPU_TYPE_DREGION_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004 // MPU default region in priv mode
+#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU enabled during faults
+#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_NUMBER
+// register.
+//
+//*****************************************************************************
+#define NVIC_MPU_NUMBER_M 0x000000FF // MPU region to access
+#define NVIC_MPU_NUMBER_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE_ADDR_M 0xFFFFFFE0 // Base address mask
+#define NVIC_MPU_BASE_VALID 0x00000010 // Region number valid
+#define NVIC_MPU_BASE_REGION_M 0x0000000F // Region number
+#define NVIC_MPU_BASE_ADDR_S 8
+#define NVIC_MPU_BASE_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR_M 0xFFFF0000 // Attributes
+#define NVIC_MPU_ATTR_AP_NO_NO 0x00000000 // prv: no access, usr: no access
+#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000 // Bufferable
+#define NVIC_MPU_ATTR_CACHEABLE 0x00020000 // Cacheable
+#define NVIC_MPU_ATTR_SHAREABLE 0x00040000 // Shareable
+#define NVIC_MPU_ATTR_TEX_M 0x00380000 // Type extension mask
+#define NVIC_MPU_ATTR_AP_RW_NO 0x01000000 // prv: rw, usr: none
+#define NVIC_MPU_ATTR_AP_RW_RO 0x02000000 // prv: rw, usr: read-only
+#define NVIC_MPU_ATTR_AP_RW_RW 0x03000000 // prv: rw, usr: rw
+#define NVIC_MPU_ATTR_AP_RO_NO 0x05000000 // prv: ro, usr: none
+#define NVIC_MPU_ATTR_AP_RO_RO 0x06000000 // prv: ro, usr: ro
+#define NVIC_MPU_ATTR_AP_M 0x07000000 // Access permissions mask
+#define NVIC_MPU_ATTR_XN 0x10000000 // Execute disable
+#define NVIC_MPU_ATTR_SRD_M 0x0000FF00 // Sub-region disable mask
+#define NVIC_MPU_ATTR_SRD_0 0x00000100 // Sub-region 0 disable
+#define NVIC_MPU_ATTR_SRD_1 0x00000200 // Sub-region 1 disable
+#define NVIC_MPU_ATTR_SRD_2 0x00000400 // Sub-region 2 disable
+#define NVIC_MPU_ATTR_SRD_3 0x00000800 // Sub-region 3 disable
+#define NVIC_MPU_ATTR_SRD_4 0x00001000 // Sub-region 4 disable
+#define NVIC_MPU_ATTR_SRD_5 0x00002000 // Sub-region 5 disable
+#define NVIC_MPU_ATTR_SRD_6 0x00004000 // Sub-region 6 disable
+#define NVIC_MPU_ATTR_SRD_7 0x00008000 // Sub-region 7 disable
+#define NVIC_MPU_ATTR_SIZE_M 0x0000003E // Region size mask
+#define NVIC_MPU_ATTR_SIZE_32B 0x00000008 // Region size 32 bytes
+#define NVIC_MPU_ATTR_SIZE_64B 0x0000000A // Region size 64 bytes
+#define NVIC_MPU_ATTR_SIZE_128B 0x0000000C // Region size 128 bytes
+#define NVIC_MPU_ATTR_SIZE_256B 0x0000000E // Region size 256 bytes
+#define NVIC_MPU_ATTR_SIZE_512B 0x00000010 // Region size 512 bytes
+#define NVIC_MPU_ATTR_SIZE_1K 0x00000012 // Region size 1 Kbytes
+#define NVIC_MPU_ATTR_SIZE_2K 0x00000014 // Region size 2 Kbytes
+#define NVIC_MPU_ATTR_SIZE_4K 0x00000016 // Region size 4 Kbytes
+#define NVIC_MPU_ATTR_SIZE_8K 0x00000018 // Region size 8 Kbytes
+#define NVIC_MPU_ATTR_SIZE_16K 0x0000001A // Region size 16 Kbytes
+#define NVIC_MPU_ATTR_SIZE_32K 0x0000001C // Region size 32 Kbytes
+#define NVIC_MPU_ATTR_SIZE_64K 0x0000001E // Region size 64 Kbytes
+#define NVIC_MPU_ATTR_SIZE_128K 0x00000020 // Region size 128 Kbytes
+#define NVIC_MPU_ATTR_SIZE_256K 0x00000022 // Region size 256 Kbytes
+#define NVIC_MPU_ATTR_SIZE_512K 0x00000024 // Region size 512 Kbytes
+#define NVIC_MPU_ATTR_SIZE_1M 0x00000026 // Region size 1 Mbytes
+#define NVIC_MPU_ATTR_SIZE_2M 0x00000028 // Region size 2 Mbytes
+#define NVIC_MPU_ATTR_SIZE_4M 0x0000002A // Region size 4 Mbytes
+#define NVIC_MPU_ATTR_SIZE_8M 0x0000002C // Region size 8 Mbytes
+#define NVIC_MPU_ATTR_SIZE_16M 0x0000002E // Region size 16 Mbytes
+#define NVIC_MPU_ATTR_SIZE_32M 0x00000030 // Region size 32 Mbytes
+#define NVIC_MPU_ATTR_SIZE_64M 0x00000032 // Region size 64 Mbytes
+#define NVIC_MPU_ATTR_SIZE_128M 0x00000034 // Region size 128 Mbytes
+#define NVIC_MPU_ATTR_SIZE_256M 0x00000036 // Region size 256 Mbytes
+#define NVIC_MPU_ATTR_SIZE_512M 0x00000038 // Region size 512 Mbytes
+#define NVIC_MPU_ATTR_SIZE_1G 0x0000003A // Region size 1 Gbytes
+#define NVIC_MPU_ATTR_SIZE_2G 0x0000003C // Region size 2 Gbytes
+#define NVIC_MPU_ATTR_SIZE_4G 0x0000003E // Region size 4 Gbytes
+#define NVIC_MPU_ATTR_ENABLE 0x00000001 // Region enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask
+#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key
+#define NVIC_DBG_CTRL_S_RESET_ST \
+ 0x02000000 // Core has reset since last read
+#define NVIC_DBG_CTRL_S_RETIRE_ST \
+ 0x01000000 // Core has executed insruction
+ // since last read
+#define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 // Core is locked up
+#define NVIC_DBG_CTRL_S_SLEEP 0x00040000 // Core is sleeping
+#define NVIC_DBG_CTRL_S_HALT 0x00020000 // Core status on halt
+#define NVIC_DBG_CTRL_S_REGRDY 0x00010000 // Register read/write available
+#define NVIC_DBG_CTRL_C_SNAPSTALL \
+ 0x00000020 // Breaks a stalled load/store
+#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping
+#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core
+#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core
+#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_XFER register.
+//
+//*****************************************************************************
+#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read
+#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register
+#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask
+#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP
+#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP
+#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP
+#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register
+#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15
+#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14
+#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13
+#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12
+#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11
+#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10
+#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9
+#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8
+#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7
+#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6
+#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5
+#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4
+#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3
+#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2
+#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1
+#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_DATA register.
+//
+//*****************************************************************************
+#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache
+#define NVIC_DBG_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_INT register.
+//
+//*****************************************************************************
+#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault
+#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors
+#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error
+#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state
+#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check
+#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error
+#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault
+#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status
+#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset
+#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending
+#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SW_TRIG register.
+//
+//*****************************************************************************
+#define NVIC_SW_TRIG_INTID_M 0x000003FF // Interrupt to trigger
+#define NVIC_SW_TRIG_INTID_S 0
+
+#endif // __LM3S6965_H__
Property changes on: branches/eagle_mmc/src/platform/lm3s/lm3s6965.h
___________________________________________________________________
Name: svn:executable
+ *
Added: branches/eagle_mmc/src/platform/lm3s/lm3s8962.h
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/lm3s8962.h 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lm3s/lm3s8962.h 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,4880 @@
+//*****************************************************************************
+//
+// lm3s8962.h - LM3S8962 Register Definitions
+//
+// Copyright (c) 2007-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4781 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __LM3S8962_H__
+#define __LM3S8962_H__
+
+//*****************************************************************************
+//
+// Watchdog Timer (WATCHDOG)
+//
+//*****************************************************************************
+#define WATCHDOG_LOAD_R (*((volatile unsigned long *)0x40000000))
+#define WATCHDOG_VALUE_R (*((volatile unsigned long *)0x40000004))
+#define WATCHDOG_CTL_R (*((volatile unsigned long *)0x40000008))
+#define WATCHDOG_ICR_R (*((volatile unsigned long *)0x4000000C))
+#define WATCHDOG_RIS_R (*((volatile unsigned long *)0x40000010))
+#define WATCHDOG_MIS_R (*((volatile unsigned long *)0x40000014))
+#define WATCHDOG_TEST_R (*((volatile unsigned long *)0x40000418))
+#define WATCHDOG_LOCK_R (*((volatile unsigned long *)0x40000C00))
+
+//*****************************************************************************
+//
+// General-Purpose Input/Outputs (PORTA)
+//
+//*****************************************************************************
+#define GPIO_PORTA_DATA_BITS_R ((volatile unsigned long *)0x40004000)
+#define GPIO_PORTA_DATA_R (*((volatile unsigned long *)0x400043FC))
+#define GPIO_PORTA_DIR_R (*((volatile unsigned long *)0x40004400))
+#define GPIO_PORTA_IS_R (*((volatile unsigned long *)0x40004404))
+#define GPIO_PORTA_IBE_R (*((volatile unsigned long *)0x40004408))
+#define GPIO_PORTA_IEV_R (*((volatile unsigned long *)0x4000440C))
+#define GPIO_PORTA_IM_R (*((volatile unsigned long *)0x40004410))
+#define GPIO_PORTA_RIS_R (*((volatile unsigned long *)0x40004414))
+#define GPIO_PORTA_MIS_R (*((volatile unsigned long *)0x40004418))
+#define GPIO_PORTA_ICR_R (*((volatile unsigned long *)0x4000441C))
+#define GPIO_PORTA_AFSEL_R (*((volatile unsigned long *)0x40004420))
+#define GPIO_PORTA_DR2R_R (*((volatile unsigned long *)0x40004500))
+#define GPIO_PORTA_DR4R_R (*((volatile unsigned long *)0x40004504))
+#define GPIO_PORTA_DR8R_R (*((volatile unsigned long *)0x40004508))
+#define GPIO_PORTA_ODR_R (*((volatile unsigned long *)0x4000450C))
+#define GPIO_PORTA_PUR_R (*((volatile unsigned long *)0x40004510))
+#define GPIO_PORTA_PDR_R (*((volatile unsigned long *)0x40004514))
+#define GPIO_PORTA_SLR_R (*((volatile unsigned long *)0x40004518))
+#define GPIO_PORTA_DEN_R (*((volatile unsigned long *)0x4000451C))
+#define GPIO_PORTA_LOCK_R (*((volatile unsigned long *)0x40004520))
+#define GPIO_PORTA_CR_R (*((volatile unsigned long *)0x40004524))
+
+//*****************************************************************************
+//
+// General-Purpose Input/Outputs (PORTB)
+//
+//*****************************************************************************
+#define GPIO_PORTB_DATA_BITS_R ((volatile unsigned long *)0x40005000)
+#define GPIO_PORTB_DATA_R (*((volatile unsigned long *)0x400053FC))
+#define GPIO_PORTB_DIR_R (*((volatile unsigned long *)0x40005400))
+#define GPIO_PORTB_IS_R (*((volatile unsigned long *)0x40005404))
+#define GPIO_PORTB_IBE_R (*((volatile unsigned long *)0x40005408))
+#define GPIO_PORTB_IEV_R (*((volatile unsigned long *)0x4000540C))
+#define GPIO_PORTB_IM_R (*((volatile unsigned long *)0x40005410))
+#define GPIO_PORTB_RIS_R (*((volatile unsigned long *)0x40005414))
+#define GPIO_PORTB_MIS_R (*((volatile unsigned long *)0x40005418))
+#define GPIO_PORTB_ICR_R (*((volatile unsigned long *)0x4000541C))
+#define GPIO_PORTB_AFSEL_R (*((volatile unsigned long *)0x40005420))
+#define GPIO_PORTB_DR2R_R (*((volatile unsigned long *)0x40005500))
+#define GPIO_PORTB_DR4R_R (*((volatile unsigned long *)0x40005504))
+#define GPIO_PORTB_DR8R_R (*((volatile unsigned long *)0x40005508))
+#define GPIO_PORTB_ODR_R (*((volatile unsigned long *)0x4000550C))
+#define GPIO_PORTB_PUR_R (*((volatile unsigned long *)0x40005510))
+#define GPIO_PORTB_PDR_R (*((volatile unsigned long *)0x40005514))
+#define GPIO_PORTB_SLR_R (*((volatile unsigned long *)0x40005518))
+#define GPIO_PORTB_DEN_R (*((volatile unsigned long *)0x4000551C))
+#define GPIO_PORTB_LOCK_R (*((volatile unsigned long *)0x40005520))
+#define GPIO_PORTB_CR_R (*((volatile unsigned long *)0x40005524))
+
+//*****************************************************************************
+//
+// General-Purpose Input/Outputs (PORTC)
+//
+//*****************************************************************************
+#define GPIO_PORTC_DATA_BITS_R ((volatile unsigned long *)0x40006000)
+#define GPIO_PORTC_DATA_R (*((volatile unsigned long *)0x400063FC))
+#define GPIO_PORTC_DIR_R (*((volatile unsigned long *)0x40006400))
+#define GPIO_PORTC_IS_R (*((volatile unsigned long *)0x40006404))
+#define GPIO_PORTC_IBE_R (*((volatile unsigned long *)0x40006408))
+#define GPIO_PORTC_IEV_R (*((volatile unsigned long *)0x4000640C))
+#define GPIO_PORTC_IM_R (*((volatile unsigned long *)0x40006410))
+#define GPIO_PORTC_RIS_R (*((volatile unsigned long *)0x40006414))
+#define GPIO_PORTC_MIS_R (*((volatile unsigned long *)0x40006418))
+#define GPIO_PORTC_ICR_R (*((volatile unsigned long *)0x4000641C))
+#define GPIO_PORTC_AFSEL_R (*((volatile unsigned long *)0x40006420))
+#define GPIO_PORTC_DR2R_R (*((volatile unsigned long *)0x40006500))
+#define GPIO_PORTC_DR4R_R (*((volatile unsigned long *)0x40006504))
+#define GPIO_PORTC_DR8R_R (*((volatile unsigned long *)0x40006508))
+#define GPIO_PORTC_ODR_R (*((volatile unsigned long *)0x4000650C))
+#define GPIO_PORTC_PUR_R (*((volatile unsigned long *)0x40006510))
+#define GPIO_PORTC_PDR_R (*((volatile unsigned long *)0x40006514))
+#define GPIO_PORTC_SLR_R (*((volatile unsigned long *)0x40006518))
+#define GPIO_PORTC_DEN_R (*((volatile unsigned long *)0x4000651C))
+#define GPIO_PORTC_LOCK_R (*((volatile unsigned long *)0x40006520))
+#define GPIO_PORTC_CR_R (*((volatile unsigned long *)0x40006524))
+
+//*****************************************************************************
+//
+// General-Purpose Input/Outputs (PORTD)
+//
+//*****************************************************************************
+#define GPIO_PORTD_DATA_BITS_R ((volatile unsigned long *)0x40007000)
+#define GPIO_PORTD_DATA_R (*((volatile unsigned long *)0x400073FC))
+#define GPIO_PORTD_DIR_R (*((volatile unsigned long *)0x40007400))
+#define GPIO_PORTD_IS_R (*((volatile unsigned long *)0x40007404))
+#define GPIO_PORTD_IBE_R (*((volatile unsigned long *)0x40007408))
+#define GPIO_PORTD_IEV_R (*((volatile unsigned long *)0x4000740C))
+#define GPIO_PORTD_IM_R (*((volatile unsigned long *)0x40007410))
+#define GPIO_PORTD_RIS_R (*((volatile unsigned long *)0x40007414))
+#define GPIO_PORTD_MIS_R (*((volatile unsigned long *)0x40007418))
+#define GPIO_PORTD_ICR_R (*((volatile unsigned long *)0x4000741C))
+#define GPIO_PORTD_AFSEL_R (*((volatile unsigned long *)0x40007420))
+#define GPIO_PORTD_DR2R_R (*((volatile unsigned long *)0x40007500))
+#define GPIO_PORTD_DR4R_R (*((volatile unsigned long *)0x40007504))
+#define GPIO_PORTD_DR8R_R (*((volatile unsigned long *)0x40007508))
+#define GPIO_PORTD_ODR_R (*((volatile unsigned long *)0x4000750C))
+#define GPIO_PORTD_PUR_R (*((volatile unsigned long *)0x40007510))
+#define GPIO_PORTD_PDR_R (*((volatile unsigned long *)0x40007514))
+#define GPIO_PORTD_SLR_R (*((volatile unsigned long *)0x40007518))
+#define GPIO_PORTD_DEN_R (*((volatile unsigned long *)0x4000751C))
+#define GPIO_PORTD_LOCK_R (*((volatile unsigned long *)0x40007520))
+#define GPIO_PORTD_CR_R (*((volatile unsigned long *)0x40007524))
+
+//*****************************************************************************
+//
+// Synchronous Serial Interface (SSI0)
+//
+//*****************************************************************************
+#define SSI0_CR0_R (*((volatile unsigned long *)0x40008000))
+#define SSI0_CR1_R (*((volatile unsigned long *)0x40008004))
+#define SSI0_DR_R (*((volatile unsigned long *)0x40008008))
+#define SSI0_SR_R (*((volatile unsigned long *)0x4000800C))
+#define SSI0_CPSR_R (*((volatile unsigned long *)0x40008010))
+#define SSI0_IM_R (*((volatile unsigned long *)0x40008014))
+#define SSI0_RIS_R (*((volatile unsigned long *)0x40008018))
+#define SSI0_MIS_R (*((volatile unsigned long *)0x4000801C))
+#define SSI0_ICR_R (*((volatile unsigned long *)0x40008020))
+
+//*****************************************************************************
+//
+// Universal Asynchronous Receivers/Transmitters (UART0)
+//
+//*****************************************************************************
+#define UART0_DR_R (*((volatile unsigned long *)0x4000C000))
+#define UART0_RSR_R (*((volatile unsigned long *)0x4000C004))
+#define UART0_ECR_R (*((volatile unsigned long *)0x4000C004))
+#define UART0_FR_R (*((volatile unsigned long *)0x4000C018))
+#define UART0_ILPR_R (*((volatile unsigned long *)0x4000C020))
+#define UART0_IBRD_R (*((volatile unsigned long *)0x4000C024))
+#define UART0_FBRD_R (*((volatile unsigned long *)0x4000C028))
+#define UART0_LCRH_R (*((volatile unsigned long *)0x4000C02C))
+#define UART0_CTL_R (*((volatile unsigned long *)0x4000C030))
+#define UART0_IFLS_R (*((volatile unsigned long *)0x4000C034))
+#define UART0_IM_R (*((volatile unsigned long *)0x4000C038))
+#define UART0_RIS_R (*((volatile unsigned long *)0x4000C03C))
+#define UART0_MIS_R (*((volatile unsigned long *)0x4000C040))
+#define UART0_ICR_R (*((volatile unsigned long *)0x4000C044))
+
+//*****************************************************************************
+//
+// Universal Asynchronous Receivers/Transmitters (UART1)
+//
+//*****************************************************************************
+#define UART1_DR_R (*((volatile unsigned long *)0x4000D000))
+#define UART1_RSR_R (*((volatile unsigned long *)0x4000D004))
+#define UART1_ECR_R (*((volatile unsigned long *)0x4000D004))
+#define UART1_FR_R (*((volatile unsigned long *)0x4000D018))
+#define UART1_ILPR_R (*((volatile unsigned long *)0x4000D020))
+#define UART1_IBRD_R (*((volatile unsigned long *)0x4000D024))
+#define UART1_FBRD_R (*((volatile unsigned long *)0x4000D028))
+#define UART1_LCRH_R (*((volatile unsigned long *)0x4000D02C))
+#define UART1_CTL_R (*((volatile unsigned long *)0x4000D030))
+#define UART1_IFLS_R (*((volatile unsigned long *)0x4000D034))
+#define UART1_IM_R (*((volatile unsigned long *)0x4000D038))
+#define UART1_RIS_R (*((volatile unsigned long *)0x4000D03C))
+#define UART1_MIS_R (*((volatile unsigned long *)0x4000D040))
+#define UART1_ICR_R (*((volatile unsigned long *)0x4000D044))
+
+//*****************************************************************************
+//
+// Inter-Integrated Circuit (MASTER) Interface
+//
+//*****************************************************************************
+#define I2C0_MASTER_MSA_R (*((volatile unsigned long *)0x40020000))
+#define I2C0_MASTER_SOAR_R (*((volatile unsigned long *)0x40020000))
+#define I2C0_MASTER_SCSR_R (*((volatile unsigned long *)0x40020004))
+#define I2C0_MASTER_MCS_R (*((volatile unsigned long *)0x40020004))
+#define I2C0_MASTER_SDR_R (*((volatile unsigned long *)0x40020008))
+#define I2C0_MASTER_MDR_R (*((volatile unsigned long *)0x40020008))
+#define I2C0_MASTER_MTPR_R (*((volatile unsigned long *)0x4002000C))
+#define I2C0_MASTER_SIMR_R (*((volatile unsigned long *)0x4002000C))
+#define I2C0_MASTER_SRIS_R (*((volatile unsigned long *)0x40020010))
+#define I2C0_MASTER_MIMR_R (*((volatile unsigned long *)0x40020010))
+#define I2C0_MASTER_MRIS_R (*((volatile unsigned long *)0x40020014))
+#define I2C0_MASTER_SMIS_R (*((volatile unsigned long *)0x40020014))
+#define I2C0_MASTER_SICR_R (*((volatile unsigned long *)0x40020018))
+#define I2C0_MASTER_MMIS_R (*((volatile unsigned long *)0x40020018))
+#define I2C0_MASTER_MICR_R (*((volatile unsigned long *)0x4002001C))
+#define I2C0_MASTER_MCR_R (*((volatile unsigned long *)0x40020020))
+
+//*****************************************************************************
+//
+// Inter-Integrated Circuit (SLAVE) Interface
+//
+//*****************************************************************************
+#define I2C0_SLAVE_MSA_R (*((volatile unsigned long *)0x40020800))
+#define I2C0_SLAVE_SOAR_R (*((volatile unsigned long *)0x40020800))
+#define I2C0_SLAVE_SCSR_R (*((volatile unsigned long *)0x40020804))
+#define I2C0_SLAVE_MCS_R (*((volatile unsigned long *)0x40020804))
+#define I2C0_SLAVE_SDR_R (*((volatile unsigned long *)0x40020808))
+#define I2C0_SLAVE_MDR_R (*((volatile unsigned long *)0x40020808))
+#define I2C0_SLAVE_MTPR_R (*((volatile unsigned long *)0x4002080C))
+#define I2C0_SLAVE_SIMR_R (*((volatile unsigned long *)0x4002080C))
+#define I2C0_SLAVE_SRIS_R (*((volatile unsigned long *)0x40020810))
+#define I2C0_SLAVE_MIMR_R (*((volatile unsigned long *)0x40020810))
+#define I2C0_SLAVE_MRIS_R (*((volatile unsigned long *)0x40020814))
+#define I2C0_SLAVE_SMIS_R (*((volatile unsigned long *)0x40020814))
+#define I2C0_SLAVE_SICR_R (*((volatile unsigned long *)0x40020818))
+#define I2C0_SLAVE_MMIS_R (*((volatile unsigned long *)0x40020818))
+#define I2C0_SLAVE_MICR_R (*((volatile unsigned long *)0x4002081C))
+#define I2C0_SLAVE_MCR_R (*((volatile unsigned long *)0x40020820))
+
+//*****************************************************************************
+//
+// General-Purpose Input/Outputs (PORTE)
+//
+//*****************************************************************************
+#define GPIO_PORTE_DATA_BITS_R ((volatile unsigned long *)0x40024000)
+#define GPIO_PORTE_DATA_R (*((volatile unsigned long *)0x400243FC))
+#define GPIO_PORTE_DIR_R (*((volatile unsigned long *)0x40024400))
+#define GPIO_PORTE_IS_R (*((volatile unsigned long *)0x40024404))
+#define GPIO_PORTE_IBE_R (*((volatile unsigned long *)0x40024408))
+#define GPIO_PORTE_IEV_R (*((volatile unsigned long *)0x4002440C))
+#define GPIO_PORTE_IM_R (*((volatile unsigned long *)0x40024410))
+#define GPIO_PORTE_RIS_R (*((volatile unsigned long *)0x40024414))
+#define GPIO_PORTE_MIS_R (*((volatile unsigned long *)0x40024418))
+#define GPIO_PORTE_ICR_R (*((volatile unsigned long *)0x4002441C))
+#define GPIO_PORTE_AFSEL_R (*((volatile unsigned long *)0x40024420))
+#define GPIO_PORTE_DR2R_R (*((volatile unsigned long *)0x40024500))
+#define GPIO_PORTE_DR4R_R (*((volatile unsigned long *)0x40024504))
+#define GPIO_PORTE_DR8R_R (*((volatile unsigned long *)0x40024508))
+#define GPIO_PORTE_ODR_R (*((volatile unsigned long *)0x4002450C))
+#define GPIO_PORTE_PUR_R (*((volatile unsigned long *)0x40024510))
+#define GPIO_PORTE_PDR_R (*((volatile unsigned long *)0x40024514))
+#define GPIO_PORTE_SLR_R (*((volatile unsigned long *)0x40024518))
+#define GPIO_PORTE_DEN_R (*((volatile unsigned long *)0x4002451C))
+#define GPIO_PORTE_LOCK_R (*((volatile unsigned long *)0x40024520))
+#define GPIO_PORTE_CR_R (*((volatile unsigned long *)0x40024524))
+
+//*****************************************************************************
+//
+// General-Purpose Input/Outputs (PORTF)
+//
+//*****************************************************************************
+#define GPIO_PORTF_DATA_BITS_R ((volatile unsigned long *)0x40025000)
+#define GPIO_PORTF_DATA_R (*((volatile unsigned long *)0x400253FC))
+#define GPIO_PORTF_DIR_R (*((volatile unsigned long *)0x40025400))
+#define GPIO_PORTF_IS_R (*((volatile unsigned long *)0x40025404))
+#define GPIO_PORTF_IBE_R (*((volatile unsigned long *)0x40025408))
+#define GPIO_PORTF_IEV_R (*((volatile unsigned long *)0x4002540C))
+#define GPIO_PORTF_IM_R (*((volatile unsigned long *)0x40025410))
+#define GPIO_PORTF_RIS_R (*((volatile unsigned long *)0x40025414))
+#define GPIO_PORTF_MIS_R (*((volatile unsigned long *)0x40025418))
+#define GPIO_PORTF_ICR_R (*((volatile unsigned long *)0x4002541C))
+#define GPIO_PORTF_AFSEL_R (*((volatile unsigned long *)0x40025420))
+#define GPIO_PORTF_DR2R_R (*((volatile unsigned long *)0x40025500))
+#define GPIO_PORTF_DR4R_R (*((volatile unsigned long *)0x40025504))
+#define GPIO_PORTF_DR8R_R (*((volatile unsigned long *)0x40025508))
+#define GPIO_PORTF_ODR_R (*((volatile unsigned long *)0x4002550C))
+#define GPIO_PORTF_PUR_R (*((volatile unsigned long *)0x40025510))
+#define GPIO_PORTF_PDR_R (*((volatile unsigned long *)0x40025514))
+#define GPIO_PORTF_SLR_R (*((volatile unsigned long *)0x40025518))
+#define GPIO_PORTF_DEN_R (*((volatile unsigned long *)0x4002551C))
+#define GPIO_PORTF_LOCK_R (*((volatile unsigned long *)0x40025520))
+#define GPIO_PORTF_CR_R (*((volatile unsigned long *)0x40025524))
+
+//*****************************************************************************
+//
+// General-Purpose Input/Outputs (PORTG)
+//
+//*****************************************************************************
+#define GPIO_PORTG_DATA_BITS_R ((volatile unsigned long *)0x40026000)
+#define GPIO_PORTG_DATA_R (*((volatile unsigned long *)0x400263FC))
+#define GPIO_PORTG_DIR_R (*((volatile unsigned long *)0x40026400))
+#define GPIO_PORTG_IS_R (*((volatile unsigned long *)0x40026404))
+#define GPIO_PORTG_IBE_R (*((volatile unsigned long *)0x40026408))
+#define GPIO_PORTG_IEV_R (*((volatile unsigned long *)0x4002640C))
+#define GPIO_PORTG_IM_R (*((volatile unsigned long *)0x40026410))
+#define GPIO_PORTG_RIS_R (*((volatile unsigned long *)0x40026414))
+#define GPIO_PORTG_MIS_R (*((volatile unsigned long *)0x40026418))
+#define GPIO_PORTG_ICR_R (*((volatile unsigned long *)0x4002641C))
+#define GPIO_PORTG_AFSEL_R (*((volatile unsigned long *)0x40026420))
+#define GPIO_PORTG_DR2R_R (*((volatile unsigned long *)0x40026500))
+#define GPIO_PORTG_DR4R_R (*((volatile unsigned long *)0x40026504))
+#define GPIO_PORTG_DR8R_R (*((volatile unsigned long *)0x40026508))
+#define GPIO_PORTG_ODR_R (*((volatile unsigned long *)0x4002650C))
+#define GPIO_PORTG_PUR_R (*((volatile unsigned long *)0x40026510))
+#define GPIO_PORTG_PDR_R (*((volatile unsigned long *)0x40026514))
+#define GPIO_PORTG_SLR_R (*((volatile unsigned long *)0x40026518))
+#define GPIO_PORTG_DEN_R (*((volatile unsigned long *)0x4002651C))
+#define GPIO_PORTG_LOCK_R (*((volatile unsigned long *)0x40026520))
+#define GPIO_PORTG_CR_R (*((volatile unsigned long *)0x40026524))
+
+//*****************************************************************************
+//
+// Pulse Width Modulator (PWM)
+//
+//*****************************************************************************
+#define PWM_CTL_R (*((volatile unsigned long *)0x40028000))
+#define PWM_SYNC_R (*((volatile unsigned long *)0x40028004))
+#define PWM_ENABLE_R (*((volatile unsigned long *)0x40028008))
+#define PWM_INVERT_R (*((volatile unsigned long *)0x4002800C))
+#define PWM_FAULT_R (*((volatile unsigned long *)0x40028010))
+#define PWM_INTEN_R (*((volatile unsigned long *)0x40028014))
+#define PWM_RIS_R (*((volatile unsigned long *)0x40028018))
+#define PWM_ISC_R (*((volatile unsigned long *)0x4002801C))
+#define PWM_STATUS_R (*((volatile unsigned long *)0x40028020))
+#define PWM_0_CTL_R (*((volatile unsigned long *)0x40028040))
+#define PWM_0_INTEN_R (*((volatile unsigned long *)0x40028044))
+#define PWM_0_RIS_R (*((volatile unsigned long *)0x40028048))
+#define PWM_0_ISC_R (*((volatile unsigned long *)0x4002804C))
+#define PWM_0_LOAD_R (*((volatile unsigned long *)0x40028050))
+#define PWM_0_COUNT_R (*((volatile unsigned long *)0x40028054))
+#define PWM_0_CMPA_R (*((volatile unsigned long *)0x40028058))
+#define PWM_0_CMPB_R (*((volatile unsigned long *)0x4002805C))
+#define PWM_0_GENA_R (*((volatile unsigned long *)0x40028060))
+#define PWM_0_GENB_R (*((volatile unsigned long *)0x40028064))
+#define PWM_0_DBCTL_R (*((volatile unsigned long *)0x40028068))
+#define PWM_0_DBRISE_R (*((volatile unsigned long *)0x4002806C))
+#define PWM_0_DBFALL_R (*((volatile unsigned long *)0x40028070))
+#define PWM_1_CTL_R (*((volatile unsigned long *)0x40028080))
+#define PWM_1_INTEN_R (*((volatile unsigned long *)0x40028084))
+#define PWM_1_RIS_R (*((volatile unsigned long *)0x40028088))
+#define PWM_1_ISC_R (*((volatile unsigned long *)0x4002808C))
+#define PWM_1_LOAD_R (*((volatile unsigned long *)0x40028090))
+#define PWM_1_COUNT_R (*((volatile unsigned long *)0x40028094))
+#define PWM_1_CMPA_R (*((volatile unsigned long *)0x40028098))
+#define PWM_1_CMPB_R (*((volatile unsigned long *)0x4002809C))
+#define PWM_1_GENA_R (*((volatile unsigned long *)0x400280A0))
+#define PWM_1_GENB_R (*((volatile unsigned long *)0x400280A4))
+#define PWM_1_DBCTL_R (*((volatile unsigned long *)0x400280A8))
+#define PWM_1_DBRISE_R (*((volatile unsigned long *)0x400280AC))
+#define PWM_1_DBFALL_R (*((volatile unsigned long *)0x400280B0))
+#define PWM_2_CTL_R (*((volatile unsigned long *)0x400280C0))
+#define PWM_2_INTEN_R (*((volatile unsigned long *)0x400280C4))
+#define PWM_2_RIS_R (*((volatile unsigned long *)0x400280C8))
+#define PWM_2_ISC_R (*((volatile unsigned long *)0x400280CC))
+#define PWM_2_LOAD_R (*((volatile unsigned long *)0x400280D0))
+#define PWM_2_COUNT_R (*((volatile unsigned long *)0x400280D4))
+#define PWM_2_CMPA_R (*((volatile unsigned long *)0x400280D8))
+#define PWM_2_CMPB_R (*((volatile unsigned long *)0x400280DC))
+#define PWM_2_GENA_R (*((volatile unsigned long *)0x400280E0))
+#define PWM_2_GENB_R (*((volatile unsigned long *)0x400280E4))
+#define PWM_2_DBCTL_R (*((volatile unsigned long *)0x400280E8))
+#define PWM_2_DBRISE_R (*((volatile unsigned long *)0x400280EC))
+#define PWM_2_DBFALL_R (*((volatile unsigned long *)0x400280F0))
+
+//*****************************************************************************
+//
+// Quadrature Encoder Interface (QEI0)
+//
+//*****************************************************************************
+#define QEI0_CTL_R (*((volatile unsigned long *)0x4002C000))
+#define QEI0_STAT_R (*((volatile unsigned long *)0x4002C004))
+#define QEI0_POS_R (*((volatile unsigned long *)0x4002C008))
+#define QEI0_MAXPOS_R (*((volatile unsigned long *)0x4002C00C))
+#define QEI0_LOAD_R (*((volatile unsigned long *)0x4002C010))
+#define QEI0_TIME_R (*((volatile unsigned long *)0x4002C014))
+#define QEI0_COUNT_R (*((volatile unsigned long *)0x4002C018))
+#define QEI0_SPEED_R (*((volatile unsigned long *)0x4002C01C))
+#define QEI0_INTEN_R (*((volatile unsigned long *)0x4002C020))
+#define QEI0_RIS_R (*((volatile unsigned long *)0x4002C024))
+#define QEI0_ISC_R (*((volatile unsigned long *)0x4002C028))
+
+//*****************************************************************************
+//
+// Quadrature Encoder Interface (QEI1)
+//
+//*****************************************************************************
+#define QEI1_CTL_R (*((volatile unsigned long *)0x4002D000))
+#define QEI1_STAT_R (*((volatile unsigned long *)0x4002D004))
+#define QEI1_POS_R (*((volatile unsigned long *)0x4002D008))
+#define QEI1_MAXPOS_R (*((volatile unsigned long *)0x4002D00C))
+#define QEI1_LOAD_R (*((volatile unsigned long *)0x4002D010))
+#define QEI1_TIME_R (*((volatile unsigned long *)0x4002D014))
+#define QEI1_COUNT_R (*((volatile unsigned long *)0x4002D018))
+#define QEI1_SPEED_R (*((volatile unsigned long *)0x4002D01C))
+#define QEI1_INTEN_R (*((volatile unsigned long *)0x4002D020))
+#define QEI1_RIS_R (*((volatile unsigned long *)0x4002D024))
+#define QEI1_ISC_R (*((volatile unsigned long *)0x4002D028))
+
+//*****************************************************************************
+//
+// General-Purpose Timers (TIMER0)
+//
+//*****************************************************************************
+#define TIMER0_CFG_R (*((volatile unsigned long *)0x40030000))
+#define TIMER0_TAMR_R (*((volatile unsigned long *)0x40030004))
+#define TIMER0_TBMR_R (*((volatile unsigned long *)0x40030008))
+#define TIMER0_CTL_R (*((volatile unsigned long *)0x4003000C))
+#define TIMER0_IMR_R (*((volatile unsigned long *)0x40030018))
+#define TIMER0_RIS_R (*((volatile unsigned long *)0x4003001C))
+#define TIMER0_MIS_R (*((volatile unsigned long *)0x40030020))
+#define TIMER0_ICR_R (*((volatile unsigned long *)0x40030024))
+#define TIMER0_TAILR_R (*((volatile unsigned long *)0x40030028))
+#define TIMER0_TBILR_R (*((volatile unsigned long *)0x4003002C))
+#define TIMER0_TAMATCHR_R (*((volatile unsigned long *)0x40030030))
+#define TIMER0_TBMATCHR_R (*((volatile unsigned long *)0x40030034))
+#define TIMER0_TAPR_R (*((volatile unsigned long *)0x40030038))
+#define TIMER0_TBPR_R (*((volatile unsigned long *)0x4003003C))
+#define TIMER0_TAPMR_R (*((volatile unsigned long *)0x40030040))
+#define TIMER0_TBPMR_R (*((volatile unsigned long *)0x40030044))
+#define TIMER0_TAR_R (*((volatile unsigned long *)0x40030048))
+#define TIMER0_TBR_R (*((volatile unsigned long *)0x4003004C))
+
+//*****************************************************************************
+//
+// General-Purpose Timers (TIMER1)
+//
+//*****************************************************************************
+#define TIMER1_CFG_R (*((volatile unsigned long *)0x40031000))
+#define TIMER1_TAMR_R (*((volatile unsigned long *)0x40031004))
+#define TIMER1_TBMR_R (*((volatile unsigned long *)0x40031008))
+#define TIMER1_CTL_R (*((volatile unsigned long *)0x4003100C))
+#define TIMER1_IMR_R (*((volatile unsigned long *)0x40031018))
+#define TIMER1_RIS_R (*((volatile unsigned long *)0x4003101C))
+#define TIMER1_MIS_R (*((volatile unsigned long *)0x40031020))
+#define TIMER1_ICR_R (*((volatile unsigned long *)0x40031024))
+#define TIMER1_TAILR_R (*((volatile unsigned long *)0x40031028))
+#define TIMER1_TBILR_R (*((volatile unsigned long *)0x4003102C))
+#define TIMER1_TAMATCHR_R (*((volatile unsigned long *)0x40031030))
+#define TIMER1_TBMATCHR_R (*((volatile unsigned long *)0x40031034))
+#define TIMER1_TAPR_R (*((volatile unsigned long *)0x40031038))
+#define TIMER1_TBPR_R (*((volatile unsigned long *)0x4003103C))
+#define TIMER1_TAPMR_R (*((volatile unsigned long *)0x40031040))
+#define TIMER1_TBPMR_R (*((volatile unsigned long *)0x40031044))
+#define TIMER1_TAR_R (*((volatile unsigned long *)0x40031048))
+#define TIMER1_TBR_R (*((volatile unsigned long *)0x4003104C))
+
+//*****************************************************************************
+//
+// General-Purpose Timers (TIMER2)
+//
+//*****************************************************************************
+#define TIMER2_CFG_R (*((volatile unsigned long *)0x40032000))
+#define TIMER2_TAMR_R (*((volatile unsigned long *)0x40032004))
+#define TIMER2_TBMR_R (*((volatile unsigned long *)0x40032008))
+#define TIMER2_CTL_R (*((volatile unsigned long *)0x4003200C))
+#define TIMER2_IMR_R (*((volatile unsigned long *)0x40032018))
+#define TIMER2_RIS_R (*((volatile unsigned long *)0x4003201C))
+#define TIMER2_MIS_R (*((volatile unsigned long *)0x40032020))
+#define TIMER2_ICR_R (*((volatile unsigned long *)0x40032024))
+#define TIMER2_TAILR_R (*((volatile unsigned long *)0x40032028))
+#define TIMER2_TBILR_R (*((volatile unsigned long *)0x4003202C))
+#define TIMER2_TAMATCHR_R (*((volatile unsigned long *)0x40032030))
+#define TIMER2_TBMATCHR_R (*((volatile unsigned long *)0x40032034))
+#define TIMER2_TAPR_R (*((volatile unsigned long *)0x40032038))
+#define TIMER2_TBPR_R (*((volatile unsigned long *)0x4003203C))
+#define TIMER2_TAPMR_R (*((volatile unsigned long *)0x40032040))
+#define TIMER2_TBPMR_R (*((volatile unsigned long *)0x40032044))
+#define TIMER2_TAR_R (*((volatile unsigned long *)0x40032048))
+#define TIMER2_TBR_R (*((volatile unsigned long *)0x4003204C))
+
+//*****************************************************************************
+//
+// General-Purpose Timers (TIMER3)
+//
+//*****************************************************************************
+#define TIMER3_CFG_R (*((volatile unsigned long *)0x40033000))
+#define TIMER3_TAMR_R (*((volatile unsigned long *)0x40033004))
+#define TIMER3_TBMR_R (*((volatile unsigned long *)0x40033008))
+#define TIMER3_CTL_R (*((volatile unsigned long *)0x4003300C))
+#define TIMER3_IMR_R (*((volatile unsigned long *)0x40033018))
+#define TIMER3_RIS_R (*((volatile unsigned long *)0x4003301C))
+#define TIMER3_MIS_R (*((volatile unsigned long *)0x40033020))
+#define TIMER3_ICR_R (*((volatile unsigned long *)0x40033024))
+#define TIMER3_TAILR_R (*((volatile unsigned long *)0x40033028))
+#define TIMER3_TBILR_R (*((volatile unsigned long *)0x4003302C))
+#define TIMER3_TAMATCHR_R (*((volatile unsigned long *)0x40033030))
+#define TIMER3_TBMATCHR_R (*((volatile unsigned long *)0x40033034))
+#define TIMER3_TAPR_R (*((volatile unsigned long *)0x40033038))
+#define TIMER3_TBPR_R (*((volatile unsigned long *)0x4003303C))
+#define TIMER3_TAPMR_R (*((volatile unsigned long *)0x40033040))
+#define TIMER3_TBPMR_R (*((volatile unsigned long *)0x40033044))
+#define TIMER3_TAR_R (*((volatile unsigned long *)0x40033048))
+#define TIMER3_TBR_R (*((volatile unsigned long *)0x4003304C))
+
+//*****************************************************************************
+//
+// Analog-to-Digital Converter (ADC)
+//
+//*****************************************************************************
+#define ADC_ACTSS_R (*((volatile unsigned long *)0x40038000))
+#define ADC_RIS_R (*((volatile unsigned long *)0x40038004))
+#define ADC_IM_R (*((volatile unsigned long *)0x40038008))
+#define ADC_ISC_R (*((volatile unsigned long *)0x4003800C))
+#define ADC_OSTAT_R (*((volatile unsigned long *)0x40038010))
+#define ADC_EMUX_R (*((volatile unsigned long *)0x40038014))
+#define ADC_USTAT_R (*((volatile unsigned long *)0x40038018))
+#define ADC_SSPRI_R (*((volatile unsigned long *)0x40038020))
+#define ADC_PSSI_R (*((volatile unsigned long *)0x40038028))
+#define ADC_SAC_R (*((volatile unsigned long *)0x40038030))
+#define ADC_SSMUX0_R (*((volatile unsigned long *)0x40038040))
+#define ADC_SSCTL0_R (*((volatile unsigned long *)0x40038044))
+#define ADC_SSFIFO0_R (*((volatile unsigned long *)0x40038048))
+#define ADC_SSFSTAT0_R (*((volatile unsigned long *)0x4003804C))
+#define ADC_SSMUX1_R (*((volatile unsigned long *)0x40038060))
+#define ADC_SSCTL1_R (*((volatile unsigned long *)0x40038064))
+#define ADC_SSFIFO1_R (*((volatile unsigned long *)0x40038068))
+#define ADC_SSFSTAT1_R (*((volatile unsigned long *)0x4003806C))
+#define ADC_SSMUX2_R (*((volatile unsigned long *)0x40038080))
+#define ADC_SSCTL2_R (*((volatile unsigned long *)0x40038084))
+#define ADC_SSFIFO2_R (*((volatile unsigned long *)0x40038088))
+#define ADC_SSFSTAT2_R (*((volatile unsigned long *)0x4003808C))
+#define ADC_SSMUX3_R (*((volatile unsigned long *)0x400380A0))
+#define ADC_SSCTL3_R (*((volatile unsigned long *)0x400380A4))
+#define ADC_SSFIFO3_R (*((volatile unsigned long *)0x400380A8))
+#define ADC_SSFSTAT3_R (*((volatile unsigned long *)0x400380AC))
+#define ADC_TMLB_R (*((volatile unsigned long *)0x40038100))
+
+//*****************************************************************************
+//
+// Analog Comparator (COMP)
+//
+//*****************************************************************************
+#define COMP_ACMIS_R (*((volatile unsigned long *)0x4003C000))
+#define COMP_ACRIS_R (*((volatile unsigned long *)0x4003C004))
+#define COMP_ACINTEN_R (*((volatile unsigned long *)0x4003C008))
+#define COMP_ACREFCTL_R (*((volatile unsigned long *)0x4003C010))
+#define COMP_ACSTAT0_R (*((volatile unsigned long *)0x4003C020))
+#define COMP_ACCTL0_R (*((volatile unsigned long *)0x4003C024))
+
+//*****************************************************************************
+//
+// Controller Area Network (CAN0) Module
+//
+//*****************************************************************************
+#define CAN0_CTL_R (*((volatile unsigned long *)0x40040000))
+#define CAN0_STS_R (*((volatile unsigned long *)0x40040004))
+#define CAN0_ERR_R (*((volatile unsigned long *)0x40040008))
+#define CAN0_BIT_R (*((volatile unsigned long *)0x4004000C))
+#define CAN0_INT_R (*((volatile unsigned long *)0x40040010))
+#define CAN0_TST_R (*((volatile unsigned long *)0x40040014))
+#define CAN0_BRPE_R (*((volatile unsigned long *)0x40040018))
+#define CAN0_IF1CRQ_R (*((volatile unsigned long *)0x40040020))
+#define CAN0_IF1CMSK_R (*((volatile unsigned long *)0x40040024))
+#define CAN0_IF1MSK1_R (*((volatile unsigned long *)0x40040028))
+#define CAN0_IF1MSK2_R (*((volatile unsigned long *)0x4004002C))
+#define CAN0_IF1ARB1_R (*((volatile unsigned long *)0x40040030))
+#define CAN0_IF1ARB2_R (*((volatile unsigned long *)0x40040034))
+#define CAN0_IF1MCTL_R (*((volatile unsigned long *)0x40040038))
+#define CAN0_IF1DA1_R (*((volatile unsigned long *)0x4004003C))
+#define CAN0_IF1DA2_R (*((volatile unsigned long *)0x40040040))
+#define CAN0_IF1DB1_R (*((volatile unsigned long *)0x40040044))
+#define CAN0_IF1DB2_R (*((volatile unsigned long *)0x40040048))
+#define CAN0_IF2CRQ_R (*((volatile unsigned long *)0x40040080))
+#define CAN0_IF2CMSK_R (*((volatile unsigned long *)0x40040084))
+#define CAN0_IF2MSK1_R (*((volatile unsigned long *)0x40040088))
+#define CAN0_IF2MSK2_R (*((volatile unsigned long *)0x4004008C))
+#define CAN0_IF2ARB1_R (*((volatile unsigned long *)0x40040090))
+#define CAN0_IF2ARB2_R (*((volatile unsigned long *)0x40040094))
+#define CAN0_IF2MCTL_R (*((volatile unsigned long *)0x40040098))
+#define CAN0_IF2DA1_R (*((volatile unsigned long *)0x4004009C))
+#define CAN0_IF2DA2_R (*((volatile unsigned long *)0x400400A0))
+#define CAN0_IF2DB1_R (*((volatile unsigned long *)0x400400A4))
+#define CAN0_IF2DB2_R (*((volatile unsigned long *)0x400400A8))
+#define CAN0_TXRQ1_R (*((volatile unsigned long *)0x40040100))
+#define CAN0_TXRQ2_R (*((volatile unsigned long *)0x40040104))
+#define CAN0_NWDA1_R (*((volatile unsigned long *)0x40040120))
+#define CAN0_NWDA2_R (*((volatile unsigned long *)0x40040124))
+#define CAN0_MSG1INT_R (*((volatile unsigned long *)0x40040140))
+#define CAN0_MSG2INT_R (*((volatile unsigned long *)0x40040144))
+#define CAN0_MSG1VAL_R (*((volatile unsigned long *)0x40040160))
+#define CAN0_MSG2VAL_R (*((volatile unsigned long *)0x40040164))
+
+//*****************************************************************************
+//
+// Ethernet Controller (MAC)
+//
+//*****************************************************************************
+#define MAC_MR0_R (*((volatile unsigned long *)0x40048000))
+#define MAC_RIS_R (*((volatile unsigned long *)0x40048000))
+#define MAC_IACK_R (*((volatile unsigned long *)0x40048000))
+#define MAC_MR1_R (*((volatile unsigned long *)0x40048001))
+#define MAC_MR2_R (*((volatile unsigned long *)0x40048002))
+#define MAC_MR3_R (*((volatile unsigned long *)0x40048003))
+#define MAC_IM_R (*((volatile unsigned long *)0x40048004))
+#define MAC_MR4_R (*((volatile unsigned long *)0x40048004))
+#define MAC_MR5_R (*((volatile unsigned long *)0x40048005))
+#define MAC_MR6_R (*((volatile unsigned long *)0x40048006))
+#define MAC_RCTL_R (*((volatile unsigned long *)0x40048008))
+#define MAC_TCTL_R (*((volatile unsigned long *)0x4004800C))
+#define MAC_DATA_R (*((volatile unsigned long *)0x40048010))
+#define MAC_MR16_R (*((volatile unsigned long *)0x40048010))
+#define MAC_MR17_R (*((volatile unsigned long *)0x40048011))
+#define MAC_MR18_R (*((volatile unsigned long *)0x40048012))
+#define MAC_MR19_R (*((volatile unsigned long *)0x40048013))
+#define MAC_IA0_R (*((volatile unsigned long *)0x40048014))
+#define MAC_MR23_R (*((volatile unsigned long *)0x40048017))
+#define MAC_IA1_R (*((volatile unsigned long *)0x40048018))
+#define MAC_MR24_R (*((volatile unsigned long *)0x40048018))
+#define MAC_THR_R (*((volatile unsigned long *)0x4004801C))
+#define MAC_MCTL_R (*((volatile unsigned long *)0x40048020))
+#define MAC_MDV_R (*((volatile unsigned long *)0x40048024))
+#define MAC_MTXD_R (*((volatile unsigned long *)0x4004802C))
+#define MAC_MRXD_R (*((volatile unsigned long *)0x40048030))
+#define MAC_NP_R (*((volatile unsigned long *)0x40048034))
+#define MAC_TR_R (*((volatile unsigned long *)0x40048038))
+#define MAC_TS_R (*((volatile unsigned long *)0x4004803C))
+
+//*****************************************************************************
+//
+// Hibernation Module (HIB)
+//
+//*****************************************************************************
+#define HIB_RTCC_R (*((volatile unsigned long *)0x400FC000))
+#define HIB_RTCM0_R (*((volatile unsigned long *)0x400FC004))
+#define HIB_RTCM1_R (*((volatile unsigned long *)0x400FC008))
+#define HIB_RTCLD_R (*((volatile unsigned long *)0x400FC00C))
+#define HIB_CTL_R (*((volatile unsigned long *)0x400FC010))
+#define HIB_IM_R (*((volatile unsigned long *)0x400FC014))
+#define HIB_RIS_R (*((volatile unsigned long *)0x400FC018))
+#define HIB_MIS_R (*((volatile unsigned long *)0x400FC01C))
+#define HIB_IC_R (*((volatile unsigned long *)0x400FC020))
+#define HIB_RTCT_R (*((volatile unsigned long *)0x400FC024))
+#define HIB_DATA_R (*((volatile unsigned long *)0x400FC030))
+
+//*****************************************************************************
+//
+// Internal Memory (FLASH)
+//
+//*****************************************************************************
+#define FLASH_FMA_R (*((volatile unsigned long *)0x400FD000))
+#define FLASH_FMD_R (*((volatile unsigned long *)0x400FD004))
+#define FLASH_FMC_R (*((volatile unsigned long *)0x400FD008))
+#define FLASH_FCRIS_R (*((volatile unsigned long *)0x400FD00C))
+#define FLASH_FCIM_R (*((volatile unsigned long *)0x400FD010))
+#define FLASH_FCMISC_R (*((volatile unsigned long *)0x400FD014))
+#define FLASH_USECRL_R (*((volatile unsigned long *)0x400FE140))
+#define FLASH_USERDBG_R (*((volatile unsigned long *)0x400FE1D0))
+#define FLASH_USERREG0_R (*((volatile unsigned long *)0x400FE1E0))
+#define FLASH_USERREG1_R (*((volatile unsigned long *)0x400FE1E4))
+#define FLASH_FMPRE0_R (*((volatile unsigned long *)0x400FE200))
+#define FLASH_FMPRE1_R (*((volatile unsigned long *)0x400FE204))
+#define FLASH_FMPRE2_R (*((volatile unsigned long *)0x400FE208))
+#define FLASH_FMPRE3_R (*((volatile unsigned long *)0x400FE20C))
+#define FLASH_FMPPE0_R (*((volatile unsigned long *)0x400FE400))
+#define FLASH_FMPPE1_R (*((volatile unsigned long *)0x400FE404))
+#define FLASH_FMPPE2_R (*((volatile unsigned long *)0x400FE408))
+#define FLASH_FMPPE3_R (*((volatile unsigned long *)0x400FE40C))
+
+//*****************************************************************************
+//
+// System Control (SYSCTL)
+//
+//*****************************************************************************
+#define SYSCTL_DID0_R (*((volatile unsigned long *)0x400FE000))
+#define SYSCTL_DID1_R (*((volatile unsigned long *)0x400FE004))
+#define SYSCTL_DC0_R (*((volatile unsigned long *)0x400FE008))
+#define SYSCTL_DC1_R (*((volatile unsigned long *)0x400FE010))
+#define SYSCTL_DC2_R (*((volatile unsigned long *)0x400FE014))
+#define SYSCTL_DC3_R (*((volatile unsigned long *)0x400FE018))
+#define SYSCTL_DC4_R (*((volatile unsigned long *)0x400FE01C))
+#define SYSCTL_PBORCTL_R (*((volatile unsigned long *)0x400FE030))
+#define SYSCTL_LDOPCTL_R (*((volatile unsigned long *)0x400FE034))
+#define SYSCTL_SRCR0_R (*((volatile unsigned long *)0x400FE040))
+#define SYSCTL_SRCR1_R (*((volatile unsigned long *)0x400FE044))
+#define SYSCTL_SRCR2_R (*((volatile unsigned long *)0x400FE048))
+#define SYSCTL_RIS_R (*((volatile unsigned long *)0x400FE050))
+#define SYSCTL_IMC_R (*((volatile unsigned long *)0x400FE054))
+#define SYSCTL_MISC_R (*((volatile unsigned long *)0x400FE058))
+#define SYSCTL_RESC_R (*((volatile unsigned long *)0x400FE05C))
+#define SYSCTL_RCC_R (*((volatile unsigned long *)0x400FE060))
+#define SYSCTL_PLLCFG_R (*((volatile unsigned long *)0x400FE064))
+#define SYSCTL_RCC2_R (*((volatile unsigned long *)0x400FE070))
+#define SYSCTL_RCGC0_R (*((volatile unsigned long *)0x400FE100))
+#define SYSCTL_RCGC1_R (*((volatile unsigned long *)0x400FE104))
+#define SYSCTL_RCGC2_R (*((volatile unsigned long *)0x400FE108))
+#define SYSCTL_SCGC0_R (*((volatile unsigned long *)0x400FE110))
+#define SYSCTL_SCGC1_R (*((volatile unsigned long *)0x400FE114))
+#define SYSCTL_SCGC2_R (*((volatile unsigned long *)0x400FE118))
+#define SYSCTL_DCGC0_R (*((volatile unsigned long *)0x400FE120))
+#define SYSCTL_DCGC1_R (*((volatile unsigned long *)0x400FE124))
+#define SYSCTL_DCGC2_R (*((volatile unsigned long *)0x400FE128))
+#define SYSCTL_DSLPCLKCFG_R (*((volatile unsigned long *)0x400FE144))
+
+//*****************************************************************************
+//
+// Nested Vectored Interrupt Ctrl (NVIC)
+//
+//*****************************************************************************
+#define NVIC_INT_TYPE_R (*((volatile unsigned long *)0xE000E004))
+#define NVIC_ST_CTRL_R (*((volatile unsigned long *)0xE000E010))
+#define NVIC_ST_RELOAD_R (*((volatile unsigned long *)0xE000E014))
+#define NVIC_ST_CURRENT_R (*((volatile unsigned long *)0xE000E018))
+#define NVIC_ST_CAL_R (*((volatile unsigned long *)0xE000E01C))
+#define NVIC_EN0_R (*((volatile unsigned long *)0xE000E100))
+#define NVIC_EN1_R (*((volatile unsigned long *)0xE000E104))
+#define NVIC_DIS0_R (*((volatile unsigned long *)0xE000E180))
+#define NVIC_DIS1_R (*((volatile unsigned long *)0xE000E184))
+#define NVIC_PEND0_R (*((volatile unsigned long *)0xE000E200))
+#define NVIC_PEND1_R (*((volatile unsigned long *)0xE000E204))
+#define NVIC_UNPEND0_R (*((volatile unsigned long *)0xE000E280))
+#define NVIC_UNPEND1_R (*((volatile unsigned long *)0xE000E284))
+#define NVIC_ACTIVE0_R (*((volatile unsigned long *)0xE000E300))
+#define NVIC_ACTIVE1_R (*((volatile unsigned long *)0xE000E304))
+#define NVIC_PRI0_R (*((volatile unsigned long *)0xE000E400))
+#define NVIC_PRI1_R (*((volatile unsigned long *)0xE000E404))
+#define NVIC_PRI2_R (*((volatile unsigned long *)0xE000E408))
+#define NVIC_PRI3_R (*((volatile unsigned long *)0xE000E40C))
+#define NVIC_PRI4_R (*((volatile unsigned long *)0xE000E410))
+#define NVIC_PRI5_R (*((volatile unsigned long *)0xE000E414))
+#define NVIC_PRI6_R (*((volatile unsigned long *)0xE000E418))
+#define NVIC_PRI7_R (*((volatile unsigned long *)0xE000E41C))
+#define NVIC_PRI8_R (*((volatile unsigned long *)0xE000E420))
+#define NVIC_PRI9_R (*((volatile unsigned long *)0xE000E424))
+#define NVIC_PRI10_R (*((volatile unsigned long *)0xE000E428))
+#define NVIC_CPUID_R (*((volatile unsigned long *)0xE000ED00))
+#define NVIC_INT_CTRL_R (*((volatile unsigned long *)0xE000ED04))
+#define NVIC_VTABLE_R (*((volatile unsigned long *)0xE000ED08))
+#define NVIC_APINT_R (*((volatile unsigned long *)0xE000ED0C))
+#define NVIC_SYS_CTRL_R (*((volatile unsigned long *)0xE000ED10))
+#define NVIC_CFG_CTRL_R (*((volatile unsigned long *)0xE000ED14))
+#define NVIC_SYS_PRI1_R (*((volatile unsigned long *)0xE000ED18))
+#define NVIC_SYS_PRI2_R (*((volatile unsigned long *)0xE000ED1C))
+#define NVIC_SYS_PRI3_R (*((volatile unsigned long *)0xE000ED20))
+#define NVIC_SYS_HND_CTRL_R (*((volatile unsigned long *)0xE000ED24))
+#define NVIC_FAULT_STAT_R (*((volatile unsigned long *)0xE000ED28))
+#define NVIC_HFAULT_STAT_R (*((volatile unsigned long *)0xE000ED2C))
+#define NVIC_DEBUG_STAT_R (*((volatile unsigned long *)0xE000ED30))
+#define NVIC_MM_ADDR_R (*((volatile unsigned long *)0xE000ED34))
+#define NVIC_FAULT_ADDR_R (*((volatile unsigned long *)0xE000ED38))
+#define NVIC_MPU_TYPE_R (*((volatile unsigned long *)0xE000ED90))
+#define NVIC_MPU_CTRL_R (*((volatile unsigned long *)0xE000ED94))
+#define NVIC_MPU_NUMBER_R (*((volatile unsigned long *)0xE000ED98))
+#define NVIC_MPU_R (*((volatile unsigned long *)0xE000ED9C))
+#define NVIC_MPU_ATTR_R (*((volatile unsigned long *)0xE000EDA0))
+#define NVIC_DBG_CTRL_R (*((volatile unsigned long *)0xE000EDF0))
+#define NVIC_DBG_XFER_R (*((volatile unsigned long *)0xE000EDF4))
+#define NVIC_DBG_DATA_R (*((volatile unsigned long *)0xE000EDF8))
+#define NVIC_DBG_INT_R (*((volatile unsigned long *)0xE000EDFC))
+#define NVIC_SW_TRIG_R (*((volatile unsigned long *)0xE000EF00))
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_LOAD register.
+//
+//*****************************************************************************
+#define WDT_LOAD_M 0xFFFFFFFF // Watchdog Load Value.
+#define WDT_LOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_VALUE register.
+//
+//*****************************************************************************
+#define WDT_VALUE_M 0xFFFFFFFF // Watchdog Value.
+#define WDT_VALUE_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_CTL register.
+//
+//*****************************************************************************
+#define WDT_CTL_RESEN 0x00000002 // Watchdog Reset Enable.
+#define WDT_CTL_INTEN 0x00000001 // Watchdog Interrupt Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_ICR register.
+//
+//*****************************************************************************
+#define WDT_ICR_M 0xFFFFFFFF // Watchdog Interrupt Clear.
+#define WDT_ICR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_RIS register.
+//
+//*****************************************************************************
+#define WDT_RIS_WDTRIS 0x00000001 // Watchdog Raw Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_MIS register.
+//
+//*****************************************************************************
+#define WDT_MIS_WDTMIS 0x00000001 // Watchdog Masked Interrupt
+ // Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_TEST register.
+//
+//*****************************************************************************
+#define WDT_TEST_STALL 0x00000100 // Watchdog Stall Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_LOCK register.
+//
+//*****************************************************************************
+#define WDT_LOCK_M 0xFFFFFFFF // Watchdog Lock.
+#define WDT_LOCK_UNLOCKED 0x00000000 // Unlocked
+#define WDT_LOCK_LOCKED 0x00000001 // Locked
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_LOCK register.
+//
+//*****************************************************************************
+#define GPIO_LOCK_M 0xFFFFFFFF // GPIO Lock.
+#define GPIO_LOCK_UNLOCKED 0x00000000 // unlocked
+#define GPIO_LOCK_LOCKED 0x00000001 // locked
+#define GPIO_LOCK_KEY 0x1ACCE551 // Unlocks the GPIO_CR register
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_CR0 register.
+//
+//*****************************************************************************
+#define SSI_CR0_SCR_M 0x0000FF00 // SSI Serial Clock Rate.
+#define SSI_CR0_SPH 0x00000080 // SSI Serial Clock Phase.
+#define SSI_CR0_SPO 0x00000040 // SSI Serial Clock Polarity.
+#define SSI_CR0_FRF_M 0x00000030 // SSI Frame Format Select.
+#define SSI_CR0_FRF_MOTO 0x00000000 // Freescale SPI Frame Format
+#define SSI_CR0_FRF_TI 0x00000010 // Texas Instruments Synchronous
+ // Serial Frame Format
+#define SSI_CR0_FRF_NMW 0x00000020 // MICROWIRE Frame Format
+#define SSI_CR0_DSS_M 0x0000000F // SSI Data Size Select.
+#define SSI_CR0_DSS_4 0x00000003 // 4-bit data
+#define SSI_CR0_DSS_5 0x00000004 // 5-bit data
+#define SSI_CR0_DSS_6 0x00000005 // 6-bit data
+#define SSI_CR0_DSS_7 0x00000006 // 7-bit data
+#define SSI_CR0_DSS_8 0x00000007 // 8-bit data
+#define SSI_CR0_DSS_9 0x00000008 // 9-bit data
+#define SSI_CR0_DSS_10 0x00000009 // 10-bit data
+#define SSI_CR0_DSS_11 0x0000000A // 11-bit data
+#define SSI_CR0_DSS_12 0x0000000B // 12-bit data
+#define SSI_CR0_DSS_13 0x0000000C // 13-bit data
+#define SSI_CR0_DSS_14 0x0000000D // 14-bit data
+#define SSI_CR0_DSS_15 0x0000000E // 15-bit data
+#define SSI_CR0_DSS_16 0x0000000F // 16-bit data
+#define SSI_CR0_SCR_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_CR1 register.
+//
+//*****************************************************************************
+#define SSI_CR1_SOD 0x00000008 // SSI Slave Mode Output Disable.
+#define SSI_CR1_MS 0x00000004 // SSI Master/Slave Select.
+#define SSI_CR1_SSE 0x00000002 // SSI Synchronous Serial Port
+ // Enable.
+#define SSI_CR1_LBM 0x00000001 // SSI Loopback Mode.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_DR register.
+//
+//*****************************************************************************
+#define SSI_DR_DATA_M 0x0000FFFF // SSI Receive/Transmit Data.
+#define SSI_DR_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_SR register.
+//
+//*****************************************************************************
+#define SSI_SR_BSY 0x00000010 // SSI Busy Bit.
+#define SSI_SR_RFF 0x00000008 // SSI Receive FIFO Full.
+#define SSI_SR_RNE 0x00000004 // SSI Receive FIFO Not Empty.
+#define SSI_SR_TNF 0x00000002 // SSI Transmit FIFO Not Full.
+#define SSI_SR_TFE 0x00000001 // SSI Transmit FIFO Empty.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_CPSR register.
+//
+//*****************************************************************************
+#define SSI_CPSR_CPSDVSR_M 0x000000FF // SSI Clock Prescale Divisor.
+#define SSI_CPSR_CPSDVSR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_IM register.
+//
+//*****************************************************************************
+#define SSI_IM_TXIM 0x00000008 // SSI Transmit FIFO Interrupt
+ // Mask.
+#define SSI_IM_RXIM 0x00000004 // SSI Receive FIFO Interrupt Mask.
+#define SSI_IM_RTIM 0x00000002 // SSI Receive Time-Out Interrupt
+ // Mask.
+#define SSI_IM_RORIM 0x00000001 // SSI Receive Overrun Interrupt
+ // Mask.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_RIS register.
+//
+//*****************************************************************************
+#define SSI_RIS_TXRIS 0x00000008 // SSI Transmit FIFO Raw Interrupt
+ // Status.
+#define SSI_RIS_RXRIS 0x00000004 // SSI Receive FIFO Raw Interrupt
+ // Status.
+#define SSI_RIS_RTRIS 0x00000002 // SSI Receive Time-Out Raw
+ // Interrupt Status.
+#define SSI_RIS_RORRIS 0x00000001 // SSI Receive Overrun Raw
+ // Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_MIS register.
+//
+//*****************************************************************************
+#define SSI_MIS_TXMIS 0x00000008 // SSI Transmit FIFO Masked
+ // Interrupt Status.
+#define SSI_MIS_RXMIS 0x00000004 // SSI Receive FIFO Masked
+ // Interrupt Status.
+#define SSI_MIS_RTMIS 0x00000002 // SSI Receive Time-Out Masked
+ // Interrupt Status.
+#define SSI_MIS_RORMIS 0x00000001 // SSI Receive Overrun Masked
+ // Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_ICR register.
+//
+//*****************************************************************************
+#define SSI_ICR_RTIC 0x00000002 // SSI Receive Time-Out Interrupt
+ // Clear.
+#define SSI_ICR_RORIC 0x00000001 // SSI Receive Overrun Interrupt
+ // Clear.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_DR register.
+//
+//*****************************************************************************
+#define UART_DR_OE 0x00000800 // UART Overrun Error.
+#define UART_DR_BE 0x00000400 // UART Break Error.
+#define UART_DR_PE 0x00000200 // UART Parity Error.
+#define UART_DR_FE 0x00000100 // UART Framing Error.
+#define UART_DR_DATA_M 0x000000FF // Data Transmitted or Received.
+#define UART_DR_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_RSR register.
+//
+//*****************************************************************************
+#define UART_RSR_OE 0x00000008 // UART Overrun Error.
+#define UART_RSR_BE 0x00000004 // UART Break Error.
+#define UART_RSR_PE 0x00000002 // UART Parity Error.
+#define UART_RSR_FE 0x00000001 // UART Framing Error.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_ECR register.
+//
+//*****************************************************************************
+#define UART_ECR_DATA_M 0x000000FF // Error Clear.
+#define UART_ECR_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_FR register.
+//
+//*****************************************************************************
+#define UART_FR_TXFE 0x00000080 // UART Transmit FIFO Empty.
+#define UART_FR_RXFF 0x00000040 // UART Receive FIFO Full.
+#define UART_FR_TXFF 0x00000020 // UART Transmit FIFO Full.
+#define UART_FR_RXFE 0x00000010 // UART Receive FIFO Empty.
+#define UART_FR_BUSY 0x00000008 // UART Busy.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_ILPR register.
+//
+//*****************************************************************************
+#define UART_ILPR_ILPDVSR_M 0x000000FF // IrDA Low-Power Divisor.
+#define UART_ILPR_ILPDVSR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_IBRD register.
+//
+//*****************************************************************************
+#define UART_IBRD_DIVINT_M 0x0000FFFF // Integer Baud-Rate Divisor.
+#define UART_IBRD_DIVINT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_FBRD register.
+//
+//*****************************************************************************
+#define UART_FBRD_DIVFRAC_M 0x0000003F // Fractional Baud-Rate Divisor.
+#define UART_FBRD_DIVFRAC_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_LCRH register.
+//
+//*****************************************************************************
+#define UART_LCRH_SPS 0x00000080 // UART Stick Parity Select.
+#define UART_LCRH_WLEN_M 0x00000060 // UART Word Length.
+#define UART_LCRH_WLEN_5 0x00000000 // 5 bits (default)
+#define UART_LCRH_WLEN_6 0x00000020 // 6 bits
+#define UART_LCRH_WLEN_7 0x00000040 // 7 bits
+#define UART_LCRH_WLEN_8 0x00000060 // 8 bits
+#define UART_LCRH_FEN 0x00000010 // UART Enable FIFOs.
+#define UART_LCRH_STP2 0x00000008 // UART Two Stop Bits Select.
+#define UART_LCRH_EPS 0x00000004 // UART Even Parity Select.
+#define UART_LCRH_PEN 0x00000002 // UART Parity Enable.
+#define UART_LCRH_BRK 0x00000001 // UART Send Break.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_CTL register.
+//
+//*****************************************************************************
+#define UART_CTL_RXE 0x00000200 // UART Receive Enable.
+#define UART_CTL_TXE 0x00000100 // UART Transmit Enable.
+#define UART_CTL_LBE 0x00000080 // UART Loop Back Enable.
+#define UART_CTL_SIRLP 0x00000004 // UART SIR Low Power Mode.
+#define UART_CTL_SIREN 0x00000002 // UART SIR Enable.
+#define UART_CTL_UARTEN 0x00000001 // UART Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_IFLS register.
+//
+//*****************************************************************************
+#define UART_IFLS_RX_M 0x00000038 // UART Receive Interrupt FIFO
+ // Level Select.
+#define UART_IFLS_RX1_8 0x00000000 // RX FIFO <= 1/8 full
+#define UART_IFLS_RX2_8 0x00000008 // RX FIFO <= 1/4 full
+#define UART_IFLS_RX4_8 0x00000010 // RX FIFO <= 1/2 full (default)
+#define UART_IFLS_RX6_8 0x00000018 // RX FIFO <= 3/4 full
+#define UART_IFLS_RX7_8 0x00000020 // RX FIFO <= 7/8 full
+#define UART_IFLS_TX_M 0x00000007 // UART Transmit Interrupt FIFO
+ // Level Select.
+#define UART_IFLS_TX1_8 0x00000000 // TX FIFO >= 1/8 full
+#define UART_IFLS_TX2_8 0x00000001 // TX FIFO >= 1/4 full
+#define UART_IFLS_TX4_8 0x00000002 // TX FIFO >= 1/2 full (default)
+#define UART_IFLS_TX6_8 0x00000003 // TX FIFO >= 3/4 full
+#define UART_IFLS_TX7_8 0x00000004 // TX FIFO >= 7/8 full
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_IM register.
+//
+//*****************************************************************************
+#define UART_IM_OEIM 0x00000400 // UART Overrun Error Interrupt
+ // Mask.
+#define UART_IM_BEIM 0x00000200 // UART Break Error Interrupt Mask.
+#define UART_IM_PEIM 0x00000100 // UART Parity Error Interrupt
+ // Mask.
+#define UART_IM_FEIM 0x00000080 // UART Framing Error Interrupt
+ // Mask.
+#define UART_IM_RTIM 0x00000040 // UART Receive Time-Out Interrupt
+ // Mask.
+#define UART_IM_TXIM 0x00000020 // UART Transmit Interrupt Mask.
+#define UART_IM_RXIM 0x00000010 // UART Receive Interrupt Mask.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_RIS register.
+//
+//*****************************************************************************
+#define UART_RIS_OERIS 0x00000400 // UART Overrun Error Raw Interrupt
+ // Status.
+#define UART_RIS_BERIS 0x00000200 // UART Break Error Raw Interrupt
+ // Status.
+#define UART_RIS_PERIS 0x00000100 // UART Parity Error Raw Interrupt
+ // Status.
+#define UART_RIS_FERIS 0x00000080 // UART Framing Error Raw Interrupt
+ // Status.
+#define UART_RIS_RTRIS 0x00000040 // UART Receive Time-Out Raw
+ // Interrupt Status.
+#define UART_RIS_TXRIS 0x00000020 // UART Transmit Raw Interrupt
+ // Status.
+#define UART_RIS_RXRIS 0x00000010 // UART Receive Raw Interrupt
+ // Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_MIS register.
+//
+//*****************************************************************************
+#define UART_MIS_OEMIS 0x00000400 // UART Overrun Error Masked
+ // Interrupt Status.
+#define UART_MIS_BEMIS 0x00000200 // UART Break Error Masked
+ // Interrupt Status.
+#define UART_MIS_PEMIS 0x00000100 // UART Parity Error Masked
+ // Interrupt Status.
+#define UART_MIS_FEMIS 0x00000080 // UART Framing Error Masked
+ // Interrupt Status.
+#define UART_MIS_RTMIS 0x00000040 // UART Receive Time-Out Masked
+ // Interrupt Status.
+#define UART_MIS_TXMIS 0x00000020 // UART Transmit Masked Interrupt
+ // Status.
+#define UART_MIS_RXMIS 0x00000010 // UART Receive Masked Interrupt
+ // Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_ICR register.
+//
+//*****************************************************************************
+#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear.
+#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear.
+#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear.
+#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear.
+#define UART_ICR_RTIC 0x00000040 // Receive Time-Out Interrupt
+ // Clear.
+#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear.
+#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MSA register.
+//
+//*****************************************************************************
+#define I2C_MSA_SA_M 0x000000FE // I2C Slave Address.
+#define I2C_MSA_RS 0x00000001 // Receive not send.
+#define I2C_MSA_SA_S 1
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SOAR register.
+//
+//*****************************************************************************
+#define I2C_SOAR_OAR_M 0x0000007F // I2C Slave Own Address.
+#define I2C_SOAR_OAR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SCSR register.
+//
+//*****************************************************************************
+#define I2C_SCSR_FBR 0x00000004 // First Byte Received.
+#define I2C_SCSR_TREQ 0x00000002 // Transmit Request.
+#define I2C_SCSR_DA 0x00000001 // Device Active.
+#define I2C_SCSR_RREQ 0x00000001 // Receive Request.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MCS register.
+//
+//*****************************************************************************
+#define I2C_MCS_BUSBSY 0x00000040 // Bus Busy.
+#define I2C_MCS_IDLE 0x00000020 // I2C Idle.
+#define I2C_MCS_ARBLST 0x00000010 // Arbitration Lost.
+#define I2C_MCS_ACK 0x00000008 // Data Acknowledge Enable.
+#define I2C_MCS_DATACK 0x00000008 // Acknowledge Data.
+#define I2C_MCS_ADRACK 0x00000004 // Acknowledge Address.
+#define I2C_MCS_STOP 0x00000004 // Generate STOP.
+#define I2C_MCS_START 0x00000002 // Generate START.
+#define I2C_MCS_ERROR 0x00000002 // Error.
+#define I2C_MCS_RUN 0x00000001 // I2C Master Enable.
+#define I2C_MCS_BUSY 0x00000001 // I2C Busy.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SDR register.
+//
+//*****************************************************************************
+#define I2C_SDR_DATA_M 0x000000FF // Data for Transfer.
+#define I2C_SDR_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MDR register.
+//
+//*****************************************************************************
+#define I2C_MDR_DATA_M 0x000000FF // Data Transferred.
+#define I2C_MDR_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MTPR register.
+//
+//*****************************************************************************
+#define I2C_MTPR_TPR_M 0x000000FF // SCL Clock Period.
+#define I2C_MTPR_TPR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SIMR register.
+//
+//*****************************************************************************
+#define I2C_SIMR_IM 0x00000001 // Data Interrupt Mask.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SRIS register.
+//
+//*****************************************************************************
+#define I2C_SRIS_RIS 0x00000001 // Data Raw Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MIMR register.
+//
+//*****************************************************************************
+#define I2C_MIMR_IM 0x00000001 // Interrupt Mask.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MRIS register.
+//
+//*****************************************************************************
+#define I2C_MRIS_RIS 0x00000001 // Raw Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SMIS register.
+//
+//*****************************************************************************
+#define I2C_SMIS_MIS 0x00000001 // Data Masked Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SICR register.
+//
+//*****************************************************************************
+#define I2C_SICR_IC 0x00000001 // Data Interrupt Clear.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MMIS register.
+//
+//*****************************************************************************
+#define I2C_MMIS_MIS 0x00000001 // Masked Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MICR register.
+//
+//*****************************************************************************
+#define I2C_MICR_IC 0x00000001 // Interrupt Clear.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MCR register.
+//
+//*****************************************************************************
+#define I2C_MCR_SFE 0x00000020 // I2C Slave Function Enable.
+#define I2C_MCR_MFE 0x00000010 // I2C Master Function Enable.
+#define I2C_MCR_LPBK 0x00000001 // I2C Loopback.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_CTL register.
+//
+//*****************************************************************************
+#define PWM_CTL_GLOBALSYNC2 0x00000004 // Update PWM Generator 2.
+#define PWM_CTL_GLOBALSYNC1 0x00000002 // Update PWM Generator 1.
+#define PWM_CTL_GLOBALSYNC0 0x00000001 // Update PWM Generator 0.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_SYNC register.
+//
+//*****************************************************************************
+#define PWM_SYNC_SYNC2 0x00000004 // Reset Generator 2 Counter.
+#define PWM_SYNC_SYNC1 0x00000002 // Reset Generator 1 Counter.
+#define PWM_SYNC_SYNC0 0x00000001 // Reset Generator 0 Counter.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_ENABLE register.
+//
+//*****************************************************************************
+#define PWM_ENABLE_PWM5EN 0x00000020 // PWM5 Output Enable.
+#define PWM_ENABLE_PWM4EN 0x00000010 // PWM4 Output Enable.
+#define PWM_ENABLE_PWM3EN 0x00000008 // PWM3 Output Enable.
+#define PWM_ENABLE_PWM2EN 0x00000004 // PWM2 Output Enable.
+#define PWM_ENABLE_PWM1EN 0x00000002 // PWM1 Output Enable.
+#define PWM_ENABLE_PWM0EN 0x00000001 // PWM0 Output Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_INVERT register.
+//
+//*****************************************************************************
+#define PWM_INVERT_PWM5INV 0x00000020 // Invert PWM5 Signal.
+#define PWM_INVERT_PWM4INV 0x00000010 // Invert PWM4 Signal.
+#define PWM_INVERT_PWM3INV 0x00000008 // Invert PWM3 Signal.
+#define PWM_INVERT_PWM2INV 0x00000004 // Invert PWM2 Signal.
+#define PWM_INVERT_PWM1INV 0x00000002 // Invert PWM1 Signal.
+#define PWM_INVERT_PWM0INV 0x00000001 // Invert PWM0 Signal.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_FAULT register.
+//
+//*****************************************************************************
+#define PWM_FAULT_FAULT5 0x00000020 // PWM5 Fault.
+#define PWM_FAULT_FAULT4 0x00000010 // PWM4 Fault.
+#define PWM_FAULT_FAULT3 0x00000008 // PWM3 Fault.
+#define PWM_FAULT_FAULT2 0x00000004 // PWM2 Fault.
+#define PWM_FAULT_FAULT1 0x00000002 // PWM1 Fault.
+#define PWM_FAULT_FAULT0 0x00000001 // PWM0 Fault.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_INTEN register.
+//
+//*****************************************************************************
+#define PWM_INTEN_INTFAULT 0x00010000 // Fault Interrupt Enable.
+#define PWM_INTEN_INTPWM2 0x00000004 // PWM2 Interrupt Enable.
+#define PWM_INTEN_INTPWM1 0x00000002 // PWM1 Interrupt Enable.
+#define PWM_INTEN_INTPWM0 0x00000001 // PWM0 Interrupt Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_RIS register.
+//
+//*****************************************************************************
+#define PWM_RIS_INTFAULT 0x00010000 // Fault Interrupt Asserted.
+#define PWM_RIS_INTPWM2 0x00000004 // PWM2 Interrupt Asserted.
+#define PWM_RIS_INTPWM1 0x00000002 // PWM1 Interrupt Asserted.
+#define PWM_RIS_INTPWM0 0x00000001 // PWM0 Interrupt Asserted.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_ISC register.
+//
+//*****************************************************************************
+#define PWM_ISC_INTFAULT 0x00010000 // Fault Interrupt Asserted.
+#define PWM_ISC_INTPWM2 0x00000004 // PWM2 Interrupt Status.
+#define PWM_ISC_INTPWM1 0x00000002 // PWM1 Interrupt Status.
+#define PWM_ISC_INTPWM0 0x00000001 // PWM0 Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_STATUS register.
+//
+//*****************************************************************************
+#define PWM_STATUS_FAULT 0x00000001 // Fault Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_CTL,
+// PWM_O_1_CTL, and PWM_O_2_CTL registers.
+//
+//*****************************************************************************
+#define PWM_X_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode.
+#define PWM_X_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode.
+#define PWM_X_CTL_LOADUPD 0x00000008 // Load Register Update Mode.
+#define PWM_X_CTL_DEBUG 0x00000004 // Debug Mode.
+#define PWM_X_CTL_MODE 0x00000002 // Counter Mode.
+#define PWM_X_CTL_ENABLE 0x00000001 // PWM Block Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_INTEN,
+// PWM_O_1_INTEN, and PWM_O_2_INTEN registers.
+//
+//*****************************************************************************
+#define PWM_X_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=Comparator B
+ // Down.
+#define PWM_X_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=Comparator B
+ // Up.
+#define PWM_X_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=Comparator A
+ // Down.
+#define PWM_X_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=Comparator A
+ // Up.
+#define PWM_X_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=Load.
+#define PWM_X_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0.
+#define PWM_X_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=Comparator
+ // B Down.
+#define PWM_X_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=Comparator
+ // B Up.
+#define PWM_X_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=Comparator
+ // A Down.
+#define PWM_X_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=Comparator
+ // A Up.
+#define PWM_X_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=Load.
+#define PWM_X_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_RIS,
+// PWM_O_1_RIS, and PWM_O_2_RIS registers.
+//
+//*****************************************************************************
+#define PWM_X_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt
+ // Status.
+#define PWM_X_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt
+ // Status.
+#define PWM_X_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt
+ // Status.
+#define PWM_X_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt
+ // Status.
+#define PWM_X_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status.
+#define PWM_X_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_ISC,
+// PWM_O_1_ISC, and PWM_O_2_ISC registers.
+//
+//*****************************************************************************
+#define PWM_X_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt.
+#define PWM_X_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt.
+#define PWM_X_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt.
+#define PWM_X_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt.
+#define PWM_X_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt.
+#define PWM_X_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_LOAD,
+// PWM_O_1_LOAD, and PWM_O_2_LOAD registers.
+//
+//*****************************************************************************
+#define PWM_X_LOAD_M 0x0000FFFF // Counter Load Value.
+#define PWM_X_LOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_COUNT,
+// PWM_O_1_COUNT, and PWM_O_2_COUNT registers.
+//
+//*****************************************************************************
+#define PWM_X_COUNT_M 0x0000FFFF // Counter Value.
+#define PWM_X_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_CMPA,
+// PWM_O_1_CMPA, and PWM_O_2_CMPA registers.
+//
+//*****************************************************************************
+#define PWM_X_CMPA_M 0x0000FFFF // Comparator A Value.
+#define PWM_X_CMPA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_CMPB,
+// PWM_O_1_CMPB, and PWM_O_2_CMPB registers.
+//
+//*****************************************************************************
+#define PWM_X_CMPB_M 0x0000FFFF // Comparator B Value.
+#define PWM_X_CMPB_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_GENA,
+// PWM_O_1_GENA, and PWM_O_2_GENA registers.
+//
+//*****************************************************************************
+#define PWM_X_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down.
+#define PWM_X_GENA_ACTCMPBD_NONE \
+ 0x00000000 // Do nothing.
+#define PWM_X_GENA_ACTCMPBD_INV 0x00000400 // Invert the output signal.
+#define PWM_X_GENA_ACTCMPBD_ZERO \
+ 0x00000800 // Set the output signal to 0.
+#define PWM_X_GENA_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1.
+#define PWM_X_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up.
+#define PWM_X_GENA_ACTCMPBU_NONE \
+ 0x00000000 // Do nothing.
+#define PWM_X_GENA_ACTCMPBU_INV 0x00000100 // Invert the output signal.
+#define PWM_X_GENA_ACTCMPBU_ZERO \
+ 0x00000200 // Set the output signal to 0.
+#define PWM_X_GENA_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1.
+#define PWM_X_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down.
+#define PWM_X_GENA_ACTCMPAD_NONE \
+ 0x00000000 // Do nothing.
+#define PWM_X_GENA_ACTCMPAD_INV 0x00000040 // Invert the output signal.
+#define PWM_X_GENA_ACTCMPAD_ZERO \
+ 0x00000080 // Set the output signal to 0.
+#define PWM_X_GENA_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1.
+#define PWM_X_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up.
+#define PWM_X_GENA_ACTCMPAU_NONE \
+ 0x00000000 // Do nothing.
+#define PWM_X_GENA_ACTCMPAU_INV 0x00000010 // Invert the output signal.
+#define PWM_X_GENA_ACTCMPAU_ZERO \
+ 0x00000020 // Set the output signal to 0.
+#define PWM_X_GENA_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1.
+#define PWM_X_GENA_ACTLOAD_M 0x0000000C // Action for Counter=Load.
+#define PWM_X_GENA_ACTLOAD_NONE 0x00000000 // Do nothing.
+#define PWM_X_GENA_ACTLOAD_INV 0x00000004 // Invert the output signal.
+#define PWM_X_GENA_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0.
+#define PWM_X_GENA_ACTLOAD_ONE 0x0000000C // Set the output signal to 1.
+#define PWM_X_GENA_ACTZERO_M 0x00000003 // Action for Counter=0.
+#define PWM_X_GENA_ACTZERO_NONE 0x00000000 // Do nothing.
+#define PWM_X_GENA_ACTZERO_INV 0x00000001 // Invert the output signal.
+#define PWM_X_GENA_ACTZERO_ZERO 0x00000002 // Set the output signal to 0.
+#define PWM_X_GENA_ACTZERO_ONE 0x00000003 // Set the output signal to 1.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_GENB,
+// PWM_O_1_GENB, and PWM_O_2_GENB registers.
+//
+//*****************************************************************************
+#define PWM_X_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down.
+#define PWM_X_GENB_ACTCMPBD_NONE \
+ 0x00000000 // Do nothing.
+#define PWM_X_GENB_ACTCMPBD_INV 0x00000400 // Invert the output signal.
+#define PWM_X_GENB_ACTCMPBD_ZERO \
+ 0x00000800 // Set the output signal to 0.
+#define PWM_X_GENB_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1.
+#define PWM_X_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up.
+#define PWM_X_GENB_ACTCMPBU_NONE \
+ 0x00000000 // Do nothing.
+#define PWM_X_GENB_ACTCMPBU_INV 0x00000100 // Invert the output signal.
+#define PWM_X_GENB_ACTCMPBU_ZERO \
+ 0x00000200 // Set the output signal to 0.
+#define PWM_X_GENB_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1.
+#define PWM_X_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down.
+#define PWM_X_GENB_ACTCMPAD_NONE \
+ 0x00000000 // Do nothing.
+#define PWM_X_GENB_ACTCMPAD_INV 0x00000040 // Invert the output signal.
+#define PWM_X_GENB_ACTCMPAD_ZERO \
+ 0x00000080 // Set the output signal to 0.
+#define PWM_X_GENB_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1.
+#define PWM_X_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up.
+#define PWM_X_GENB_ACTCMPAU_NONE \
+ 0x00000000 // Do nothing.
+#define PWM_X_GENB_ACTCMPAU_INV 0x00000010 // Invert the output signal.
+#define PWM_X_GENB_ACTCMPAU_ZERO \
+ 0x00000020 // Set the output signal to 0.
+#define PWM_X_GENB_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1.
+#define PWM_X_GENB_ACTLOAD_M 0x0000000C // Action for Counter=Load.
+#define PWM_X_GENB_ACTLOAD_NONE 0x00000000 // Do nothing.
+#define PWM_X_GENB_ACTLOAD_INV 0x00000004 // Invert the output signal.
+#define PWM_X_GENB_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0.
+#define PWM_X_GENB_ACTLOAD_ONE 0x0000000C // Set the output signal to 1.
+#define PWM_X_GENB_ACTZERO_M 0x00000003 // Action for Counter=0.
+#define PWM_X_GENB_ACTZERO_NONE 0x00000000 // Do nothing.
+#define PWM_X_GENB_ACTZERO_INV 0x00000001 // Invert the output signal.
+#define PWM_X_GENB_ACTZERO_ZERO 0x00000002 // Set the output signal to 0.
+#define PWM_X_GENB_ACTZERO_ONE 0x00000003 // Set the output signal to 1.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_DBCTL,
+// PWM_O_1_DBCTL, and PWM_O_2_DBCTL registers.
+//
+//*****************************************************************************
+#define PWM_X_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_DBRISE,
+// PWM_O_1_DBRISE, and PWM_O_2_DBRISE registers.
+//
+//*****************************************************************************
+#define PWM_X_DBRISE_DELAY_M 0x00000FFF // Dead-Band Rise Delay.
+#define PWM_X_DBRISE_DELAY_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_DBFALL,
+// PWM_O_1_DBFALL, and PWM_O_2_DBFALL registers.
+//
+//*****************************************************************************
+#define PWM_X_DBFALL_DELAY_M 0x00000FFF // Dead-Band Fall Delay.
+#define PWM_X_DBFALL_DELAY_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_CTL register.
+//
+//*****************************************************************************
+#define QEI_CTL_STALLEN 0x00001000 // Stall QEI.
+#define QEI_CTL_INVI 0x00000800 // Invert Index Pulse.
+#define QEI_CTL_INVB 0x00000400 // Invert PhB.
+#define QEI_CTL_INVA 0x00000200 // Invert PhA.
+#define QEI_CTL_VELDIV_M 0x000001C0 // Predivide Velocity.
+#define QEI_CTL_VELDIV_1 0x00000000 // /1
+#define QEI_CTL_VELDIV_2 0x00000040 // /2
+#define QEI_CTL_VELDIV_4 0x00000080 // /4
+#define QEI_CTL_VELDIV_8 0x000000C0 // /8
+#define QEI_CTL_VELDIV_16 0x00000100 // /16
+#define QEI_CTL_VELDIV_32 0x00000140 // /32
+#define QEI_CTL_VELDIV_64 0x00000180 // /64
+#define QEI_CTL_VELDIV_128 0x000001C0 // /128
+#define QEI_CTL_VELEN 0x00000020 // Capture Velocity.
+#define QEI_CTL_RESMODE 0x00000010 // Reset Mode.
+#define QEI_CTL_CAPMODE 0x00000008 // Capture Mode.
+#define QEI_CTL_SIGMODE 0x00000004 // Signal Mode.
+#define QEI_CTL_SWAP 0x00000002 // Swap Signals.
+#define QEI_CTL_ENABLE 0x00000001 // Enable QEI.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_STAT register.
+//
+//*****************************************************************************
+#define QEI_STAT_DIRECTION 0x00000002 // Direction of Rotation.
+#define QEI_STAT_ERROR 0x00000001 // Error Detected.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_POS register.
+//
+//*****************************************************************************
+#define QEI_POS_M 0xFFFFFFFF // Current Position Integrator
+ // Value.
+#define QEI_POS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_MAXPOS register.
+//
+//*****************************************************************************
+#define QEI_MAXPOS_M 0xFFFFFFFF // Maximum Position Integrator
+ // Value.
+#define QEI_MAXPOS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_LOAD register.
+//
+//*****************************************************************************
+#define QEI_LOAD_M 0xFFFFFFFF // Velocity Timer Load Value.
+#define QEI_LOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_TIME register.
+//
+//*****************************************************************************
+#define QEI_TIME_M 0xFFFFFFFF // Velocity Timer Current Value.
+#define QEI_TIME_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_COUNT register.
+//
+//*****************************************************************************
+#define QEI_COUNT_M 0xFFFFFFFF // Velocity Pulse Count.
+#define QEI_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_SPEED register.
+//
+//*****************************************************************************
+#define QEI_SPEED_M 0xFFFFFFFF // Velocity.
+#define QEI_SPEED_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_INTEN register.
+//
+//*****************************************************************************
+#define QEI_INTEN_ERROR 0x00000008 // Phase Error Interrupt Enable.
+#define QEI_INTEN_DIR 0x00000004 // Direction Change Interrupt
+ // Enable.
+#define QEI_INTEN_TIMER 0x00000002 // Timer Expires Interrupt Enable.
+#define QEI_INTEN_INDEX 0x00000001 // Index Pulse Detected Interrupt
+ // Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_RIS register.
+//
+//*****************************************************************************
+#define QEI_RIS_ERROR 0x00000008 // Phase Error Detected.
+#define QEI_RIS_DIR 0x00000004 // Direction Change Detected.
+#define QEI_RIS_TIMER 0x00000002 // Velocity Timer Expired.
+#define QEI_RIS_INDEX 0x00000001 // Index Pulse Asserted.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_ISC register.
+//
+//*****************************************************************************
+#define QEI_ISC_ERROR 0x00000008 // Phase Error Interrupt.
+#define QEI_ISC_DIR 0x00000004 // Direction Change Interrupt.
+#define QEI_ISC_TIMER 0x00000002 // Velocity Timer Expired
+ // Interrupt.
+#define QEI_ISC_INDEX 0x00000001 // Index Pulse Interrupt.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_CFG register.
+//
+//*****************************************************************************
+#define TIMER_CFG_M 0x00000007 // GPTM Configuration.
+#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32-bit timer configuration.
+#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32-bit real-time clock (RTC)
+ // counter configuration.
+#define TIMER_CFG_16_BIT 0x00000004 // 16-bit timer configuration,
+ // function is controlled by bits
+ // 1:0 of GPTMTAMR and GPTMTBMR.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAMR register.
+//
+//*****************************************************************************
+#define TIMER_TAMR_TAAMS 0x00000008 // GPTM TimerA Alternate Mode
+ // Select.
+#define TIMER_TAMR_TACMR 0x00000004 // GPTM TimerA Capture Mode.
+#define TIMER_TAMR_TAMR_M 0x00000003 // GPTM TimerA Mode.
+#define TIMER_TAMR_TAMR_1_SHOT 0x00000001 // One-Shot Timer mode
+#define TIMER_TAMR_TAMR_PERIOD 0x00000002 // Periodic Timer mode
+#define TIMER_TAMR_TAMR_CAP 0x00000003 // Capture mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBMR register.
+//
+//*****************************************************************************
+#define TIMER_TBMR_TBAMS 0x00000008 // GPTM TimerB Alternate Mode
+ // Select.
+#define TIMER_TBMR_TBCMR 0x00000004 // GPTM TimerB Capture Mode.
+#define TIMER_TBMR_TBMR_M 0x00000003 // GPTM TimerB Mode.
+#define TIMER_TBMR_TBMR_1_SHOT 0x00000001 // One-Shot Timer mode
+#define TIMER_TBMR_TBMR_PERIOD 0x00000002 // Periodic Timer mode
+#define TIMER_TBMR_TBMR_CAP 0x00000003 // Capture mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_CTL register.
+//
+//*****************************************************************************
+#define TIMER_CTL_TBPWML 0x00004000 // GPTM TimerB PWM Output Level.
+#define TIMER_CTL_TBOTE 0x00002000 // GPTM TimerB Output Trigger
+ // Enable.
+#define TIMER_CTL_TBEVENT_M 0x00000C00 // GPTM TimerB Event Mode.
+#define TIMER_CTL_TBEVENT_POS 0x00000000 // Positive edge
+#define TIMER_CTL_TBEVENT_NEG 0x00000400 // Negative edge
+#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // Both edges
+#define TIMER_CTL_TBSTALL 0x00000200 // GPTM TimerB Stall Enable.
+#define TIMER_CTL_TBEN 0x00000100 // GPTM TimerB Enable.
+#define TIMER_CTL_TAPWML 0x00000040 // GPTM TimerA PWM Output Level.
+#define TIMER_CTL_TAOTE 0x00000020 // GPTM TimerA Output Trigger
+ // Enable.
+#define TIMER_CTL_RTCEN 0x00000010 // GPTM RTC Enable.
+#define TIMER_CTL_TAEVENT_M 0x0000000C // GPTM TimerA Event Mode.
+#define TIMER_CTL_TAEVENT_POS 0x00000000 // Positive edge
+#define TIMER_CTL_TAEVENT_NEG 0x00000004 // Negative edge
+#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // Both edges
+#define TIMER_CTL_TASTALL 0x00000002 // GPTM TimerA Stall Enable.
+#define TIMER_CTL_TAEN 0x00000001 // GPTM TimerA Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_IMR register.
+//
+//*****************************************************************************
+#define TIMER_IMR_CBEIM 0x00000400 // GPTM CaptureB Event Interrupt
+ // Mask.
+#define TIMER_IMR_CBMIM 0x00000200 // GPTM CaptureB Match Interrupt
+ // Mask.
+#define TIMER_IMR_TBTOIM 0x00000100 // GPTM TimerB Time-Out Interrupt
+ // Mask.
+#define TIMER_IMR_RTCIM 0x00000008 // GPTM RTC Interrupt Mask.
+#define TIMER_IMR_CAEIM 0x00000004 // GPTM CaptureA Event Interrupt
+ // Mask.
+#define TIMER_IMR_CAMIM 0x00000002 // GPTM CaptureA Match Interrupt
+ // Mask.
+#define TIMER_IMR_TATOIM 0x00000001 // GPTM TimerA Time-Out Interrupt
+ // Mask.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_RIS register.
+//
+//*****************************************************************************
+#define TIMER_RIS_CBERIS 0x00000400 // GPTM CaptureB Event Raw
+ // Interrupt.
+#define TIMER_RIS_CBMRIS 0x00000200 // GPTM CaptureB Match Raw
+ // Interrupt.
+#define TIMER_RIS_TBTORIS 0x00000100 // GPTM TimerB Time-Out Raw
+ // Interrupt.
+#define TIMER_RIS_RTCRIS 0x00000008 // GPTM RTC Raw Interrupt.
+#define TIMER_RIS_CAERIS 0x00000004 // GPTM CaptureA Event Raw
+ // Interrupt.
+#define TIMER_RIS_CAMRIS 0x00000002 // GPTM CaptureA Match Raw
+ // Interrupt.
+#define TIMER_RIS_TATORIS 0x00000001 // GPTM TimerA Time-Out Raw
+ // Interrupt.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_MIS register.
+//
+//*****************************************************************************
+#define TIMER_MIS_CBEMIS 0x00000400 // GPTM CaptureB Event Masked
+ // Interrupt.
+#define TIMER_MIS_CBMMIS 0x00000200 // GPTM CaptureB Match Masked
+ // Interrupt.
+#define TIMER_MIS_TBTOMIS 0x00000100 // GPTM TimerB Time-Out Masked
+ // Interrupt.
+#define TIMER_MIS_RTCMIS 0x00000008 // GPTM RTC Masked Interrupt.
+#define TIMER_MIS_CAEMIS 0x00000004 // GPTM CaptureA Event Masked
+ // Interrupt.
+#define TIMER_MIS_CAMMIS 0x00000002 // GPTM CaptureA Match Masked
+ // Interrupt.
+#define TIMER_MIS_TATOMIS 0x00000001 // GPTM TimerA Time-Out Masked
+ // Interrupt.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_ICR register.
+//
+//*****************************************************************************
+#define TIMER_ICR_CBECINT 0x00000400 // GPTM CaptureB Event Interrupt
+ // Clear.
+#define TIMER_ICR_CBMCINT 0x00000200 // GPTM CaptureB Match Interrupt
+ // Clear.
+#define TIMER_ICR_TBTOCINT 0x00000100 // GPTM TimerB Time-Out Interrupt
+ // Clear.
+#define TIMER_ICR_RTCCINT 0x00000008 // GPTM RTC Interrupt Clear.
+#define TIMER_ICR_CAECINT 0x00000004 // GPTM CaptureA Event Interrupt
+ // Clear.
+#define TIMER_ICR_CAMCINT 0x00000002 // GPTM CaptureA Match Raw
+ // Interrupt.
+#define TIMER_ICR_TATOCINT 0x00000001 // GPTM TimerA Time-Out Raw
+ // Interrupt.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAILR register.
+//
+//*****************************************************************************
+#define TIMER_TAILR_TAILRH_M 0xFFFF0000 // GPTM TimerA Interval Load
+ // Register High.
+#define TIMER_TAILR_TAILRL_M 0x0000FFFF // GPTM TimerA Interval Load
+ // Register Low.
+#define TIMER_TAILR_TAILRH_S 16
+#define TIMER_TAILR_TAILRL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBILR register.
+//
+//*****************************************************************************
+#define TIMER_TBILR_TBILRL_M 0x0000FFFF // GPTM TimerB Interval Load
+ // Register.
+#define TIMER_TBILR_TBILRL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAMATCHR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TAMATCHR_TAMRH_M 0xFFFF0000 // GPTM TimerA Match Register High.
+#define TIMER_TAMATCHR_TAMRL_M 0x0000FFFF // GPTM TimerA Match Register Low.
+#define TIMER_TAMATCHR_TAMRH_S 16
+#define TIMER_TAMATCHR_TAMRL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBMATCHR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TBMATCHR_TBMRL_M 0x0000FFFF // GPTM TimerB Match Register Low.
+#define TIMER_TBMATCHR_TBMRL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAPR register.
+//
+//*****************************************************************************
+#define TIMER_TAPR_TAPSR_M 0x000000FF // GPTM TimerA Prescale.
+#define TIMER_TAPR_TAPSR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBPR register.
+//
+//*****************************************************************************
+#define TIMER_TBPR_TBPSR_M 0x000000FF // GPTM TimerB Prescale.
+#define TIMER_TBPR_TBPSR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAPMR register.
+//
+//*****************************************************************************
+#define TIMER_TAPMR_TAPSMR_M 0x000000FF // GPTM TimerA Prescale Match.
+#define TIMER_TAPMR_TAPSMR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBPMR register.
+//
+//*****************************************************************************
+#define TIMER_TBPMR_TBPSMR_M 0x000000FF // GPTM TimerB Prescale Match.
+#define TIMER_TBPMR_TBPSMR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAR register.
+//
+//*****************************************************************************
+#define TIMER_TAR_TARH_M 0xFFFF0000 // GPTM TimerA Register High.
+#define TIMER_TAR_TARL_M 0x0000FFFF // GPTM TimerA Register Low.
+#define TIMER_TAR_TARH_S 16
+#define TIMER_TAR_TARL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBR register.
+//
+//*****************************************************************************
+#define TIMER_TBR_TBRL_M 0x0000FFFF // GPTM TimerB.
+#define TIMER_TBR_TBRL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_ACTSS register.
+//
+//*****************************************************************************
+#define ADC_ACTSS_ASEN3 0x00000008 // ADC SS3 Enable.
+#define ADC_ACTSS_ASEN2 0x00000004 // ADC SS2 Enable.
+#define ADC_ACTSS_ASEN1 0x00000002 // ADC SS1 Enable.
+#define ADC_ACTSS_ASEN0 0x00000001 // ADC SS0 Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_RIS register.
+//
+//*****************************************************************************
+#define ADC_RIS_INR3 0x00000008 // SS3 Raw Interrupt Status.
+#define ADC_RIS_INR2 0x00000004 // SS2 Raw Interrupt Status.
+#define ADC_RIS_INR1 0x00000002 // SS1 Raw Interrupt Status.
+#define ADC_RIS_INR0 0x00000001 // SS0 Raw Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_IM register.
+//
+//*****************************************************************************
+#define ADC_IM_MASK3 0x00000008 // SS3 Interrupt Mask.
+#define ADC_IM_MASK2 0x00000004 // SS2 Interrupt Mask.
+#define ADC_IM_MASK1 0x00000002 // SS1 Interrupt Mask.
+#define ADC_IM_MASK0 0x00000001 // SS0 Interrupt Mask.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_ISC register.
+//
+//*****************************************************************************
+#define ADC_ISC_IN3 0x00000008 // SS3 Interrupt Status and Clear.
+#define ADC_ISC_IN2 0x00000004 // SS2 Interrupt Status and Clear.
+#define ADC_ISC_IN1 0x00000002 // SS1 Interrupt Status and Clear.
+#define ADC_ISC_IN0 0x00000001 // SS0 Interrupt Status and Clear.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_OSTAT register.
+//
+//*****************************************************************************
+#define ADC_OSTAT_OV3 0x00000008 // SS3 FIFO Overflow.
+#define ADC_OSTAT_OV2 0x00000004 // SS2 FIFO Overflow.
+#define ADC_OSTAT_OV1 0x00000002 // SS1 FIFO Overflow.
+#define ADC_OSTAT_OV0 0x00000001 // SS0 FIFO Overflow.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_EMUX register.
+//
+//*****************************************************************************
+#define ADC_EMUX_EM3_M 0x0000F000 // SS3 Trigger Select.
+#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Controller (default)
+#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog Comparator 0
+#define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External (GPIO PB4)
+#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer
+#define ADC_EMUX_EM3_PWM0 0x00006000 // PWM0
+#define ADC_EMUX_EM3_PWM1 0x00007000 // PWM1
+#define ADC_EMUX_EM3_PWM2 0x00008000 // PWM2
+#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always (continuously sample)
+#define ADC_EMUX_EM2_M 0x00000F00 // SS2 Trigger Select.
+#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Controller (default)
+#define ADC_EMUX_EM2_COMP0 0x00000100 // Analog Comparator 0
+#define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External (GPIO PB4)
+#define ADC_EMUX_EM2_TIMER 0x00000500 // Timer
+#define ADC_EMUX_EM2_PWM0 0x00000600 // PWM0
+#define ADC_EMUX_EM2_PWM1 0x00000700 // PWM1
+#define ADC_EMUX_EM2_PWM2 0x00000800 // PWM2
+#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always (continuously sample)
+#define ADC_EMUX_EM1_M 0x000000F0 // SS1 Trigger Select.
+#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Controller (default)
+#define ADC_EMUX_EM1_COMP0 0x00000010 // Analog Comparator 0
+#define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External (GPIO PB4)
+#define ADC_EMUX_EM1_TIMER 0x00000050 // Timer
+#define ADC_EMUX_EM1_PWM0 0x00000060 // PWM0
+#define ADC_EMUX_EM1_PWM1 0x00000070 // PWM1
+#define ADC_EMUX_EM1_PWM2 0x00000080 // PWM2
+#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always (continuously sample)
+#define ADC_EMUX_EM0_M 0x0000000F // SS0 Trigger Select.
+#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Controller (default)
+#define ADC_EMUX_EM0_COMP0 0x00000001 // Analog Comparator 0
+#define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External (GPIO PB4)
+#define ADC_EMUX_EM0_TIMER 0x00000005 // Timer
+#define ADC_EMUX_EM0_PWM0 0x00000006 // PWM0
+#define ADC_EMUX_EM0_PWM1 0x00000007 // PWM1
+#define ADC_EMUX_EM0_PWM2 0x00000008 // PWM2
+#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always (continuously sample)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_USTAT register.
+//
+//*****************************************************************************
+#define ADC_USTAT_UV3 0x00000008 // SS3 FIFO Underflow.
+#define ADC_USTAT_UV2 0x00000004 // SS2 FIFO Underflow.
+#define ADC_USTAT_UV1 0x00000002 // SS1 FIFO Underflow.
+#define ADC_USTAT_UV0 0x00000001 // SS0 FIFO Underflow.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSPRI register.
+//
+//*****************************************************************************
+#define ADC_SSPRI_SS3_M 0x00003000 // SS3 Priority.
+#define ADC_SSPRI_SS3_1ST 0x00000000 // First priority
+#define ADC_SSPRI_SS3_2ND 0x00001000 // Second priority
+#define ADC_SSPRI_SS3_3RD 0x00002000 // Third priority
+#define ADC_SSPRI_SS3_4TH 0x00003000 // Fourth priority
+#define ADC_SSPRI_SS2_M 0x00000300 // SS2 Priority.
+#define ADC_SSPRI_SS2_1ST 0x00000000 // First priority
+#define ADC_SSPRI_SS2_2ND 0x00000100 // Second priority
+#define ADC_SSPRI_SS2_3RD 0x00000200 // Third priority
+#define ADC_SSPRI_SS2_4TH 0x00000300 // Fourth priority
+#define ADC_SSPRI_SS1_M 0x00000030 // SS1 Priority.
+#define ADC_SSPRI_SS1_1ST 0x00000000 // First priority
+#define ADC_SSPRI_SS1_2ND 0x00000010 // Second priority
+#define ADC_SSPRI_SS1_3RD 0x00000020 // Third priority
+#define ADC_SSPRI_SS1_4TH 0x00000030 // Fourth priority
+#define ADC_SSPRI_SS0_M 0x00000003 // SS0 Priority.
+#define ADC_SSPRI_SS0_1ST 0x00000000 // First priority
+#define ADC_SSPRI_SS0_2ND 0x00000001 // Second priority
+#define ADC_SSPRI_SS0_3RD 0x00000002 // Third priority
+#define ADC_SSPRI_SS0_4TH 0x00000003 // Fourth priority
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_PSSI register.
+//
+//*****************************************************************************
+#define ADC_PSSI_SS3 0x00000008 // SS3 Initiate.
+#define ADC_PSSI_SS2 0x00000004 // SS2 Initiate.
+#define ADC_PSSI_SS1 0x00000002 // SS1 Initiate.
+#define ADC_PSSI_SS0 0x00000001 // SS0 Initiate.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SAC register.
+//
+//*****************************************************************************
+#define ADC_SAC_AVG_M 0x00000007 // Hardware Averaging Control.
+#define ADC_SAC_AVG_OFF 0x00000000 // No hardware oversampling
+#define ADC_SAC_AVG_2X 0x00000001 // 2x hardware oversampling
+#define ADC_SAC_AVG_4X 0x00000002 // 4x hardware oversampling
+#define ADC_SAC_AVG_8X 0x00000003 // 8x hardware oversampling
+#define ADC_SAC_AVG_16X 0x00000004 // 16x hardware oversampling
+#define ADC_SAC_AVG_32X 0x00000005 // 32x hardware oversampling
+#define ADC_SAC_AVG_64X 0x00000006 // 64x hardware oversampling
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX0 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX0_MUX7_M 0x30000000 // 8th Sample Input Select.
+#define ADC_SSMUX0_MUX6_M 0x03000000 // 7th Sample Input Select.
+#define ADC_SSMUX0_MUX5_M 0x00300000 // 6th Sample Input Select.
+#define ADC_SSMUX0_MUX4_M 0x00030000 // 5th Sample Input Select.
+#define ADC_SSMUX0_MUX3_M 0x00003000 // 4th Sample Input Select.
+#define ADC_SSMUX0_MUX2_M 0x00000300 // 3rd Sample Input Select.
+#define ADC_SSMUX0_MUX1_M 0x00000030 // 2nd Sample Input Select.
+#define ADC_SSMUX0_MUX0_M 0x00000003 // 1st Sample Input Select.
+#define ADC_SSMUX0_MUX7_S 28
+#define ADC_SSMUX0_MUX6_S 24
+#define ADC_SSMUX0_MUX5_S 20
+#define ADC_SSMUX0_MUX4_S 16
+#define ADC_SSMUX0_MUX3_S 12
+#define ADC_SSMUX0_MUX2_S 8
+#define ADC_SSMUX0_MUX1_S 4
+#define ADC_SSMUX0_MUX0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL0 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL0_TS7 0x80000000 // 8th Sample Temp Sensor Select.
+#define ADC_SSCTL0_IE7 0x40000000 // 8th Sample Interrupt Enable.
+#define ADC_SSCTL0_END7 0x20000000 // 8th Sample is End of Sequence.
+#define ADC_SSCTL0_D7 0x10000000 // 8th Sample Diff Input Select.
+#define ADC_SSCTL0_TS6 0x08000000 // 7th Sample Temp Sensor Select.
+#define ADC_SSCTL0_IE6 0x04000000 // 7th Sample Interrupt Enable.
+#define ADC_SSCTL0_END6 0x02000000 // 7th Sample is End of Sequence.
+#define ADC_SSCTL0_D6 0x01000000 // 7th Sample Diff Input Select.
+#define ADC_SSCTL0_TS5 0x00800000 // 6th Sample Temp Sensor Select.
+#define ADC_SSCTL0_IE5 0x00400000 // 6th Sample Interrupt Enable.
+#define ADC_SSCTL0_END5 0x00200000 // 6th Sample is End of Sequence.
+#define ADC_SSCTL0_D5 0x00100000 // 6th Sample Diff Input Select.
+#define ADC_SSCTL0_TS4 0x00080000 // 5th Sample Temp Sensor Select.
+#define ADC_SSCTL0_IE4 0x00040000 // 5th Sample Interrupt Enable.
+#define ADC_SSCTL0_END4 0x00020000 // 5th Sample is End of Sequence.
+#define ADC_SSCTL0_D4 0x00010000 // 5th Sample Diff Input Select.
+#define ADC_SSCTL0_TS3 0x00008000 // 4th Sample Temp Sensor Select.
+#define ADC_SSCTL0_IE3 0x00004000 // 4th Sample Interrupt Enable.
+#define ADC_SSCTL0_END3 0x00002000 // 4th Sample is End of Sequence.
+#define ADC_SSCTL0_D3 0x00001000 // 4th Sample Diff Input Select.
+#define ADC_SSCTL0_TS2 0x00000800 // 3rd Sample Temp Sensor Select.
+#define ADC_SSCTL0_IE2 0x00000400 // 3rd Sample Interrupt Enable.
+#define ADC_SSCTL0_END2 0x00000200 // 3rd Sample is End of Sequence.
+#define ADC_SSCTL0_D2 0x00000100 // 3rd Sample Diff Input Select.
+#define ADC_SSCTL0_TS1 0x00000080 // 2nd Sample Temp Sensor Select.
+#define ADC_SSCTL0_IE1 0x00000040 // 2nd Sample Interrupt Enable.
+#define ADC_SSCTL0_END1 0x00000020 // 2nd Sample is End of Sequence.
+#define ADC_SSCTL0_D1 0x00000010 // 2nd Sample Diff Input Select.
+#define ADC_SSCTL0_TS0 0x00000008 // 1st Sample Temp Sensor Select.
+#define ADC_SSCTL0_IE0 0x00000004 // 1st Sample Interrupt Enable.
+#define ADC_SSCTL0_END0 0x00000002 // 1st Sample is End of Sequence.
+#define ADC_SSCTL0_D0 0x00000001 // 1st Sample Diff Input Select.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO0 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO0_DATA_M 0x000003FF // Conversion Result Data.
+#define ADC_SSFIFO0_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT0 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT0_FULL 0x00001000 // FIFO Full.
+#define ADC_SSFSTAT0_EMPTY 0x00000100 // FIFO Empty.
+#define ADC_SSFSTAT0_HPTR_M 0x000000F0 // FIFO Head Pointer.
+#define ADC_SSFSTAT0_TPTR_M 0x0000000F // FIFO Tail Pointer.
+#define ADC_SSFSTAT0_HPTR_S 4
+#define ADC_SSFSTAT0_TPTR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX1 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX1_MUX3_M 0x00003000 // 4th Sample Input Select.
+#define ADC_SSMUX1_MUX2_M 0x00000300 // 3rd Sample Input Select.
+#define ADC_SSMUX1_MUX1_M 0x00000030 // 2nd Sample Input Select.
+#define ADC_SSMUX1_MUX0_M 0x00000003 // 1st Sample Input Select.
+#define ADC_SSMUX1_MUX3_S 12
+#define ADC_SSMUX1_MUX2_S 8
+#define ADC_SSMUX1_MUX1_S 4
+#define ADC_SSMUX1_MUX0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL1 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL1_TS3 0x00008000 // 4th Sample Temp Sensor Select.
+#define ADC_SSCTL1_IE3 0x00004000 // 4th Sample Interrupt Enable.
+#define ADC_SSCTL1_END3 0x00002000 // 4th Sample is End of Sequence.
+#define ADC_SSCTL1_D3 0x00001000 // 4th Sample Diff Input Select.
+#define ADC_SSCTL1_TS2 0x00000800 // 3rd Sample Temp Sensor Select.
+#define ADC_SSCTL1_IE2 0x00000400 // 3rd Sample Interrupt Enable.
+#define ADC_SSCTL1_END2 0x00000200 // 3rd Sample is End of Sequence.
+#define ADC_SSCTL1_D2 0x00000100 // 3rd Sample Diff Input Select.
+#define ADC_SSCTL1_TS1 0x00000080 // 2nd Sample Temp Sensor Select.
+#define ADC_SSCTL1_IE1 0x00000040 // 2nd Sample Interrupt Enable.
+#define ADC_SSCTL1_END1 0x00000020 // 2nd Sample is End of Sequence.
+#define ADC_SSCTL1_D1 0x00000010 // 2nd Sample Diff Input Select.
+#define ADC_SSCTL1_TS0 0x00000008 // 1st Sample Temp Sensor Select.
+#define ADC_SSCTL1_IE0 0x00000004 // 1st Sample Interrupt Enable.
+#define ADC_SSCTL1_END0 0x00000002 // 1st Sample is End of Sequence.
+#define ADC_SSCTL1_D0 0x00000001 // 1st Sample Diff Input Select.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO1 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO1_DATA_M 0x000003FF // Conversion Result Data.
+#define ADC_SSFIFO1_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT1 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT1_FULL 0x00001000 // FIFO Full.
+#define ADC_SSFSTAT1_EMPTY 0x00000100 // FIFO Empty.
+#define ADC_SSFSTAT1_HPTR_M 0x000000F0 // FIFO Head Pointer.
+#define ADC_SSFSTAT1_TPTR_M 0x0000000F // FIFO Tail Pointer.
+#define ADC_SSFSTAT1_HPTR_S 4
+#define ADC_SSFSTAT1_TPTR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX2 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX2_MUX3_M 0x00003000 // 4th Sample Input Select.
+#define ADC_SSMUX2_MUX2_M 0x00000300 // 3rd Sample Input Select.
+#define ADC_SSMUX2_MUX1_M 0x00000030 // 2nd Sample Input Select.
+#define ADC_SSMUX2_MUX0_M 0x00000003 // 1st Sample Input Select.
+#define ADC_SSMUX2_MUX3_S 12
+#define ADC_SSMUX2_MUX2_S 8
+#define ADC_SSMUX2_MUX1_S 4
+#define ADC_SSMUX2_MUX0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL2 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL2_TS3 0x00008000 // 4th Sample Temp Sensor Select.
+#define ADC_SSCTL2_IE3 0x00004000 // 4th Sample Interrupt Enable.
+#define ADC_SSCTL2_END3 0x00002000 // 4th Sample is End of Sequence.
+#define ADC_SSCTL2_D3 0x00001000 // 4th Sample Diff Input Select.
+#define ADC_SSCTL2_TS2 0x00000800 // 3rd Sample Temp Sensor Select.
+#define ADC_SSCTL2_IE2 0x00000400 // 3rd Sample Interrupt Enable.
+#define ADC_SSCTL2_END2 0x00000200 // 3rd Sample is End of Sequence.
+#define ADC_SSCTL2_D2 0x00000100 // 3rd Sample Diff Input Select.
+#define ADC_SSCTL2_TS1 0x00000080 // 2nd Sample Temp Sensor Select.
+#define ADC_SSCTL2_IE1 0x00000040 // 2nd Sample Interrupt Enable.
+#define ADC_SSCTL2_END1 0x00000020 // 2nd Sample is End of Sequence.
+#define ADC_SSCTL2_D1 0x00000010 // 2nd Sample Diff Input Select.
+#define ADC_SSCTL2_TS0 0x00000008 // 1st Sample Temp Sensor Select.
+#define ADC_SSCTL2_IE0 0x00000004 // 1st Sample Interrupt Enable.
+#define ADC_SSCTL2_END0 0x00000002 // 1st Sample is End of Sequence.
+#define ADC_SSCTL2_D0 0x00000001 // 1st Sample Diff Input Select.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO2 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO2_DATA_M 0x000003FF // Conversion Result Data.
+#define ADC_SSFIFO2_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT2 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT2_FULL 0x00001000 // FIFO Full.
+#define ADC_SSFSTAT2_EMPTY 0x00000100 // FIFO Empty.
+#define ADC_SSFSTAT2_HPTR_M 0x000000F0 // FIFO Head Pointer.
+#define ADC_SSFSTAT2_TPTR_M 0x0000000F // FIFO Tail Pointer.
+#define ADC_SSFSTAT2_HPTR_S 4
+#define ADC_SSFSTAT2_TPTR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX3 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX3_MUX0_M 0x00000003 // 1st Sample Input Select.
+#define ADC_SSMUX3_MUX0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL3 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL3_TS0 0x00000008 // 1st Sample Temp Sensor Select.
+#define ADC_SSCTL3_IE0 0x00000004 // 1st Sample Interrupt Enable.
+#define ADC_SSCTL3_END0 0x00000002 // 1st Sample is End of Sequence.
+#define ADC_SSCTL3_D0 0x00000001 // 1st Sample Diff Input Select.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO3 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO3_DATA_M 0x000003FF // Conversion Result Data.
+#define ADC_SSFIFO3_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT3 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT3_FULL 0x00001000 // FIFO Full.
+#define ADC_SSFSTAT3_EMPTY 0x00000100 // FIFO Empty.
+#define ADC_SSFSTAT3_HPTR_M 0x000000F0 // FIFO Head Pointer.
+#define ADC_SSFSTAT3_TPTR_M 0x0000000F // FIFO Tail Pointer.
+#define ADC_SSFSTAT3_HPTR_S 4
+#define ADC_SSFSTAT3_TPTR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_TMLB register.
+//
+//*****************************************************************************
+#define ADC_TMLB_LB 0x00000001 // Loopback Mode Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the the interpretation of the data in the
+// SSFIFOx when the ADC TMLB is enabled.
+//
+//*****************************************************************************
+#define ADC_SSFIFO_TMLB_CNT_M 0x000003C0 // Continuous Sample Counter.
+#define ADC_SSFIFO_TMLB_CONT 0x00000020 // Continuation Sample Indicator.
+#define ADC_SSFIFO_TMLB_DIFF 0x00000010 // Differential Sample Indicator.
+#define ADC_SSFIFO_TMLB_TS 0x00000008 // Temp Sensor Sample Indicator.
+#define ADC_SSFIFO_TMLB_MUX_M 0x00000007 // Analog Input Indicator.
+#define ADC_SSFIFO_TMLB_CNT_S 6 // Sample counter shift
+#define ADC_SSFIFO_TMLB_MUX_S 0 // Input channel number shift
+
+//*****************************************************************************
+//
+// The following are defines for the the interpretation of the data in the
+// SSFIFOx when the ADC TMLB is enabled.
+//
+//*****************************************************************************
+#define ADC_TMLB_CNT_M 0x000003C0 // Continuous Sample Counter.
+#define ADC_TMLB_CONT 0x00000020 // Continuation Sample Indicator.
+#define ADC_TMLB_DIFF 0x00000010 // Differential Sample Indicator.
+#define ADC_TMLB_TS 0x00000008 // Temp Sensor Sample Indicator.
+#define ADC_TMLB_MUX_M 0x00000007 // Analog Input Indicator.
+#define ADC_TMLB_CNT_S 6 // Sample counter shift
+#define ADC_TMLB_MUX_S 0 // Input channel number shift
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACMIS register.
+//
+//*****************************************************************************
+#define COMP_ACMIS_IN0 0x00000001 // Comparator 0 Masked Interrupt
+ // Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACRIS register.
+//
+//*****************************************************************************
+#define COMP_ACRIS_IN0 0x00000001 // Comparator 0 Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACINTEN register.
+//
+//*****************************************************************************
+#define COMP_ACINTEN_IN0 0x00000001 // Comparator 0 Interrupt Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACREFCTL
+// register.
+//
+//*****************************************************************************
+#define COMP_ACREFCTL_EN 0x00000200 // Resistor Ladder Enable.
+#define COMP_ACREFCTL_RNG 0x00000100 // Resistor Ladder Range.
+#define COMP_ACREFCTL_VREF_M 0x0000000F // Resistor Ladder Voltage Ref.
+#define COMP_ACREFCTL_VREF_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACSTAT0 register.
+//
+//*****************************************************************************
+#define COMP_ACSTAT0_OVAL 0x00000002 // Comparator Output Value.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACCTL0 register.
+//
+//*****************************************************************************
+#define COMP_ACCTL0_TOEN 0x00000800 // Trigger Output Enable.
+#define COMP_ACCTL0_ASRCP_M 0x00000600 // Analog Source Positive.
+#define COMP_ACCTL0_ASRCP_PIN 0x00000000 // Pin value
+#define COMP_ACCTL0_ASRCP_PIN0 0x00000200 // Pin value of C0+
+#define COMP_ACCTL0_ASRCP_REF 0x00000400 // Internal voltage reference
+#define COMP_ACCTL0_TSLVAL 0x00000080 // Trigger Sense Level Value.
+#define COMP_ACCTL0_TSEN_M 0x00000060 // Trigger Sense.
+#define COMP_ACCTL0_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL
+#define COMP_ACCTL0_TSEN_FALL 0x00000020 // Falling edge
+#define COMP_ACCTL0_TSEN_RISE 0x00000040 // Rising edge
+#define COMP_ACCTL0_TSEN_BOTH 0x00000060 // Either edge
+#define COMP_ACCTL0_ISLVAL 0x00000010 // Interrupt Sense Level Value.
+#define COMP_ACCTL0_ISEN_M 0x0000000C // Interrupt Sense.
+#define COMP_ACCTL0_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL
+#define COMP_ACCTL0_ISEN_FALL 0x00000004 // Falling edge
+#define COMP_ACCTL0_ISEN_RISE 0x00000008 // Rising edge
+#define COMP_ACCTL0_ISEN_BOTH 0x0000000C // Either edge
+#define COMP_ACCTL0_CINV 0x00000002 // Comparator Output Invert.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_CTL register.
+//
+//*****************************************************************************
+#define CAN_CTL_TEST 0x00000080 // Test Mode Enable.
+#define CAN_CTL_CCE 0x00000040 // Configuration Change Enable.
+#define CAN_CTL_DAR 0x00000020 // Disable
+ // Automatic-Retransmission.
+#define CAN_CTL_EIE 0x00000008 // Error Interrupt Enable.
+#define CAN_CTL_SIE 0x00000004 // Status Interrupt Enable.
+#define CAN_CTL_IE 0x00000002 // CAN Interrupt Enable.
+#define CAN_CTL_INIT 0x00000001 // Initialization.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_STS register.
+//
+//*****************************************************************************
+#define CAN_STS_BOFF 0x00000080 // Bus-Off Status.
+#define CAN_STS_EWARN 0x00000040 // Warning Status.
+#define CAN_STS_EPASS 0x00000020 // Error Passive.
+#define CAN_STS_RXOK 0x00000010 // Received a Message Successfully.
+#define CAN_STS_TXOK 0x00000008 // Transmitted a Message
+ // Successfully.
+#define CAN_STS_LEC_M 0x00000007 // Last Error Code.
+#define CAN_STS_LEC_NONE 0x00000000 // No Error
+#define CAN_STS_LEC_STUFF 0x00000001 // Stuff Error
+#define CAN_STS_LEC_FORM 0x00000002 // Format Error
+#define CAN_STS_LEC_ACK 0x00000003 // ACK Error
+#define CAN_STS_LEC_BIT1 0x00000004 // Bit 1 Error
+#define CAN_STS_LEC_BIT0 0x00000005 // Bit 0 Error
+#define CAN_STS_LEC_CRC 0x00000006 // CRC Error
+#define CAN_STS_LEC_NOEVENT 0x00000007 // Unused
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_ERR register.
+//
+//*****************************************************************************
+#define CAN_ERR_RP 0x00008000 // Received Error Passive.
+#define CAN_ERR_REC_M 0x00007F00 // Receive Error Counter.
+#define CAN_ERR_TEC_M 0x000000FF // Transmit Error Counter.
+#define CAN_ERR_REC_S 8
+#define CAN_ERR_TEC_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_BIT register.
+//
+//*****************************************************************************
+#define CAN_BIT_TSEG2_M 0x00007000 // Time Segment after Sample Point.
+#define CAN_BIT_TSEG1_M 0x00000F00 // Time Segment Before Sample
+ // Point.
+#define CAN_BIT_SJW_M 0x000000C0 // (Re)Synchronization Jump Width.
+#define CAN_BIT_BRP_M 0x0000003F // Baud Rate Prescaler.
+#define CAN_BIT_TSEG2_S 12
+#define CAN_BIT_TSEG1_S 8
+#define CAN_BIT_SJW_S 6
+#define CAN_BIT_BRP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_INT register.
+//
+//*****************************************************************************
+#define CAN_INT_INTID_M 0x0000FFFF // Interrupt Identifier.
+#define CAN_INT_INTID_NONE 0x00000000 // No interrupt pending
+#define CAN_INT_INTID_STATUS 0x00008000 // Status Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_TST register.
+//
+//*****************************************************************************
+#define CAN_TST_RX 0x00000080 // Receive Observation.
+#define CAN_TST_TX_M 0x00000060 // Transmit Control.
+#define CAN_TST_TX_CANCTL 0x00000000 // CANnTx is controlled by the CAN
+ // module; default operation
+#define CAN_TST_TX_SAMPLE 0x00000020 // The sample point is driven on
+ // the CANnTx signal. This mode is
+ // useful to monitor bit timing.
+#define CAN_TST_TX_DOMINANT 0x00000040 // CANnTx drives a low value. This
+ // mode is useful for checking the
+ // physical layer of the CAN bus.
+#define CAN_TST_TX_RECESSIVE 0x00000060 // CANnTx drives a high value. This
+ // mode is useful for checking the
+ // physical layer of the CAN bus.
+#define CAN_TST_LBACK 0x00000010 // Loopback Mode.
+#define CAN_TST_SILENT 0x00000008 // Silent Mode.
+#define CAN_TST_BASIC 0x00000004 // Basic Mode.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_BRPE register.
+//
+//*****************************************************************************
+#define CAN_BRPE_BRPE_M 0x0000000F // Baud Rate Prescaler Extension.
+#define CAN_BRPE_BRPE_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1CRQ register.
+//
+//*****************************************************************************
+#define CAN_IF1CRQ_BUSY 0x00008000 // Busy Flag.
+#define CAN_IF1CRQ_MNUM_M 0x0000003F // Message Number.
+#define CAN_IF1CRQ_MNUM_RSVD 0x00000000 // 0 is not a valid message number;
+ // it is interpreted as 0x20, or
+ // object 32.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1CMSK register.
+//
+//*****************************************************************************
+#define CAN_IF1CMSK_WRNRD 0x00000080 // Write, Not Read.
+#define CAN_IF1CMSK_MASK 0x00000040 // Access Mask Bits.
+#define CAN_IF1CMSK_ARB 0x00000020 // Access Arbitration Bits.
+#define CAN_IF1CMSK_CONTROL 0x00000010 // Access Control Bits.
+#define CAN_IF1CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit.
+#define CAN_IF1CMSK_NEWDAT 0x00000004 // NEWDAT
+#define CAN_IF1CMSK_TXRQST 0x00000004 // TXRQST Bit.
+#define CAN_IF1CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3.
+#define CAN_IF1CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1MSK1 register.
+//
+//*****************************************************************************
+#define CAN_IF1MSK1_IDMSK_M 0x0000FFFF // Identifier Mask.
+#define CAN_IF1MSK1_IDMSK_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1MSK2 register.
+//
+//*****************************************************************************
+#define CAN_IF1MSK2_MXTD 0x00008000 // Mask Extended Identifier.
+#define CAN_IF1MSK2_MDIR 0x00004000 // Mask Message Direction.
+#define CAN_IF1MSK2_IDMSK_M 0x00001FFF // Identifier Mask.
+#define CAN_IF1MSK2_IDMSK_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1ARB1 register.
+//
+//*****************************************************************************
+#define CAN_IF1ARB1_ID_M 0x0000FFFF // Message Identifier.
+#define CAN_IF1ARB1_ID_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1ARB2 register.
+//
+//*****************************************************************************
+#define CAN_IF1ARB2_MSGVAL 0x00008000 // Message Valid.
+#define CAN_IF1ARB2_XTD 0x00004000 // Extended Identifier.
+#define CAN_IF1ARB2_DIR 0x00002000 // Message Direction.
+#define CAN_IF1ARB2_ID_M 0x00001FFF // Message Identifier.
+#define CAN_IF1ARB2_ID_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1MCTL register.
+//
+//*****************************************************************************
+#define CAN_IF1MCTL_NEWDAT 0x00008000 // New Data.
+#define CAN_IF1MCTL_MSGLST 0x00004000 // Message Lost.
+#define CAN_IF1MCTL_INTPND 0x00002000 // Interrupt Pending.
+#define CAN_IF1MCTL_UMASK 0x00001000 // Use Acceptance Mask.
+#define CAN_IF1MCTL_TXIE 0x00000800 // Transmit Interrupt Enable.
+#define CAN_IF1MCTL_RXIE 0x00000400 // Receive Interrupt Enable.
+#define CAN_IF1MCTL_RMTEN 0x00000200 // Remote Enable.
+#define CAN_IF1MCTL_TXRQST 0x00000100 // Transmit Request.
+#define CAN_IF1MCTL_EOB 0x00000080 // End of Buffer.
+#define CAN_IF1MCTL_DLC_M 0x0000000F // Data Length Code.
+#define CAN_IF1MCTL_DLC_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1DA1 register.
+//
+//*****************************************************************************
+#define CAN_IF1DA1_DATA_M 0x0000FFFF // Data.
+#define CAN_IF1DA1_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1DA2 register.
+//
+//*****************************************************************************
+#define CAN_IF1DA2_DATA_M 0x0000FFFF // Data.
+#define CAN_IF1DA2_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1DB1 register.
+//
+//*****************************************************************************
+#define CAN_IF1DB1_DATA_M 0x0000FFFF // Data.
+#define CAN_IF1DB1_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1DB2 register.
+//
+//*****************************************************************************
+#define CAN_IF1DB2_DATA_M 0x0000FFFF // Data.
+#define CAN_IF1DB2_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2CRQ register.
+//
+//*****************************************************************************
+#define CAN_IF2CRQ_BUSY 0x00008000 // Busy Flag.
+#define CAN_IF2CRQ_MNUM_M 0x0000003F // Message Number.
+#define CAN_IF2CRQ_MNUM_RSVD 0x00000000 // 0 is not a valid message number;
+ // it is interpreted as 0x20, or
+ // object 32.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2CMSK register.
+//
+//*****************************************************************************
+#define CAN_IF2CMSK_WRNRD 0x00000080 // Write, Not Read.
+#define CAN_IF2CMSK_MASK 0x00000040 // Access Mask Bits.
+#define CAN_IF2CMSK_ARB 0x00000020 // Access Arbitration Bits.
+#define CAN_IF2CMSK_CONTROL 0x00000010 // Access Control Bits.
+#define CAN_IF2CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit.
+#define CAN_IF2CMSK_NEWDAT 0x00000004 // NEWDAT
+#define CAN_IF2CMSK_TXRQST 0x00000004 // TXRQST Bit.
+#define CAN_IF2CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3.
+#define CAN_IF2CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2MSK1 register.
+//
+//*****************************************************************************
+#define CAN_IF2MSK1_IDMSK_M 0x0000FFFF // Identifier Mask.
+#define CAN_IF2MSK1_IDMSK_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2MSK2 register.
+//
+//*****************************************************************************
+#define CAN_IF2MSK2_MXTD 0x00008000 // Mask Extended Identifier.
+#define CAN_IF2MSK2_MDIR 0x00004000 // Mask Message Direction.
+#define CAN_IF2MSK2_IDMSK_M 0x00001FFF // Identifier Mask.
+#define CAN_IF2MSK2_IDMSK_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2ARB1 register.
+//
+//*****************************************************************************
+#define CAN_IF2ARB1_ID_M 0x0000FFFF // Message Identifier.
+#define CAN_IF2ARB1_ID_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2ARB2 register.
+//
+//*****************************************************************************
+#define CAN_IF2ARB2_MSGVAL 0x00008000 // Message Valid.
+#define CAN_IF2ARB2_XTD 0x00004000 // Extended Identifier.
+#define CAN_IF2ARB2_DIR 0x00002000 // Message Direction.
+#define CAN_IF2ARB2_ID_M 0x00001FFF // Message Identifier.
+#define CAN_IF2ARB2_ID_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2MCTL register.
+//
+//*****************************************************************************
+#define CAN_IF2MCTL_NEWDAT 0x00008000 // New Data.
+#define CAN_IF2MCTL_MSGLST 0x00004000 // Message Lost.
+#define CAN_IF2MCTL_INTPND 0x00002000 // Interrupt Pending.
+#define CAN_IF2MCTL_UMASK 0x00001000 // Use Acceptance Mask.
+#define CAN_IF2MCTL_TXIE 0x00000800 // Transmit Interrupt Enable.
+#define CAN_IF2MCTL_RXIE 0x00000400 // Receive Interrupt Enable.
+#define CAN_IF2MCTL_RMTEN 0x00000200 // Remote Enable.
+#define CAN_IF2MCTL_TXRQST 0x00000100 // Transmit Request.
+#define CAN_IF2MCTL_EOB 0x00000080 // End of Buffer.
+#define CAN_IF2MCTL_DLC_M 0x0000000F // Data Length Code.
+#define CAN_IF2MCTL_DLC_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2DA1 register.
+//
+//*****************************************************************************
+#define CAN_IF2DA1_DATA_M 0x0000FFFF // Data.
+#define CAN_IF2DA1_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2DA2 register.
+//
+//*****************************************************************************
+#define CAN_IF2DA2_DATA_M 0x0000FFFF // Data.
+#define CAN_IF2DA2_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2DB1 register.
+//
+//*****************************************************************************
+#define CAN_IF2DB1_DATA_M 0x0000FFFF // Data.
+#define CAN_IF2DB1_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2DB2 register.
+//
+//*****************************************************************************
+#define CAN_IF2DB2_DATA_M 0x0000FFFF // Data.
+#define CAN_IF2DB2_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_TXRQ1 register.
+//
+//*****************************************************************************
+#define CAN_TXRQ1_TXRQST_M 0x0000FFFF // Transmission Request Bits.
+#define CAN_TXRQ1_TXRQST_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_TXRQ2 register.
+//
+//*****************************************************************************
+#define CAN_TXRQ2_TXRQST_M 0x0000FFFF // Transmission Request Bits.
+#define CAN_TXRQ2_TXRQST_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_NWDA1 register.
+//
+//*****************************************************************************
+#define CAN_NWDA1_NEWDAT_M 0x0000FFFF // New Data Bits.
+#define CAN_NWDA1_NEWDAT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_NWDA2 register.
+//
+//*****************************************************************************
+#define CAN_NWDA2_NEWDAT_M 0x0000FFFF // New Data Bits.
+#define CAN_NWDA2_NEWDAT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_MSG1INT register.
+//
+//*****************************************************************************
+#define CAN_MSG1INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits.
+#define CAN_MSG1INT_INTPND_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_MSG2INT register.
+//
+//*****************************************************************************
+#define CAN_MSG2INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits.
+#define CAN_MSG2INT_INTPND_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_MSG1VAL register.
+//
+//*****************************************************************************
+#define CAN_MSG1VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits.
+#define CAN_MSG1VAL_MSGVAL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_MSG2VAL register.
+//
+//*****************************************************************************
+#define CAN_MSG2VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits.
+#define CAN_MSG2VAL_MSGVAL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MR0 register.
+//
+//*****************************************************************************
+#define PHY_MR0_RESET 0x00008000 // Reset Registers.
+#define PHY_MR0_LOOPBK 0x00004000 // Loopback Mode.
+#define PHY_MR0_SPEEDSL 0x00002000 // Speed Select.
+#define PHY_MR0_ANEGEN 0x00001000 // Auto-Negotiation Enable.
+#define PHY_MR0_PWRDN 0x00000800 // Power Down.
+#define PHY_MR0_ISO 0x00000400 // Isolate.
+#define PHY_MR0_RANEG 0x00000200 // Restart Auto-Negotiation.
+#define PHY_MR0_DUPLEX 0x00000100 // Set Duplex Mode.
+#define PHY_MR0_COLT 0x00000080 // Collision Test.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_RIS register.
+//
+//*****************************************************************************
+#define MAC_RIS_PHYINT 0x00000040 // PHY Interrupt.
+#define MAC_RIS_MDINT 0x00000020 // MII Transaction Complete.
+#define MAC_RIS_RXER 0x00000010 // Receive Error.
+#define MAC_RIS_FOV 0x00000008 // FIFO Overrun.
+#define MAC_RIS_TXEMP 0x00000004 // Transmit FIFO Empty.
+#define MAC_RIS_TXER 0x00000002 // Transmit Error.
+#define MAC_RIS_RXINT 0x00000001 // Packet Received.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_IACK register.
+//
+//*****************************************************************************
+#define MAC_IACK_PHYINT 0x00000040 // Clear PHY Interrupt.
+#define MAC_IACK_MDINT 0x00000020 // Clear MII Transaction Complete.
+#define MAC_IACK_RXER 0x00000010 // Clear Receive Error.
+#define MAC_IACK_FOV 0x00000008 // Clear FIFO Overrun.
+#define MAC_IACK_TXEMP 0x00000004 // Clear Transmit FIFO Empty.
+#define MAC_IACK_TXER 0x00000002 // Clear Transmit Error.
+#define MAC_IACK_RXINT 0x00000001 // Clear Packet Received.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MR1 register.
+//
+//*****************************************************************************
+#define PHY_MR1_100X_F 0x00004000 // 100BASE-TX Full-Duplex Mode.
+#define PHY_MR1_100X_H 0x00002000 // 100BASE-TX Half-Duplex Mode.
+#define PHY_MR1_10T_F 0x00001000 // 10BASE-T Full-Duplex Mode.
+#define PHY_MR1_10T_H 0x00000800 // 10BASE-T Half-Duplex Mode.
+#define PHY_MR1_MFPS 0x00000040 // Management Frames with Preamble
+ // Suppressed.
+#define PHY_MR1_ANEGC 0x00000020 // Auto-Negotiation Complete.
+#define PHY_MR1_RFAULT 0x00000010 // Remote Fault.
+#define PHY_MR1_ANEGA 0x00000008 // Auto-Negotiation.
+#define PHY_MR1_LINK 0x00000004 // Link Made.
+#define PHY_MR1_JAB 0x00000002 // Jabber Condition.
+#define PHY_MR1_EXTD 0x00000001 // Extended Capabilities.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MR2 register.
+//
+//*****************************************************************************
+#define PHY_MR2_OUI_M 0x0000FFFF // Organizationally Unique
+ // Identifier[21:6].
+#define PHY_MR2_OUI_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MR3 register.
+//
+//*****************************************************************************
+#define PHY_MR3_OUI_M 0x0000FC00 // Organizationally Unique
+ // Identifier[5:0].
+#define PHY_MR3_MN_M 0x000003F0 // Model Number.
+#define PHY_MR3_RN_M 0x0000000F // Revision Number.
+#define PHY_MR3_OUI_S 10
+#define PHY_MR3_MN_S 4
+#define PHY_MR3_RN_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_IM register.
+//
+//*****************************************************************************
+#define MAC_IM_PHYINTM 0x00000040 // Mask PHY Interrupt.
+#define MAC_IM_MDINTM 0x00000020 // Mask MII Transaction Complete.
+#define MAC_IM_RXERM 0x00000010 // Mask Receive Error.
+#define MAC_IM_FOVM 0x00000008 // Mask FIFO Overrun.
+#define MAC_IM_TXEMPM 0x00000004 // Mask Transmit FIFO Empty.
+#define MAC_IM_TXERM 0x00000002 // Mask Transmit Error.
+#define MAC_IM_RXINTM 0x00000001 // Mask Packet Received.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MR4 register.
+//
+//*****************************************************************************
+#define PHY_MR4_NP 0x00008000 // Next Page.
+#define PHY_MR4_RF 0x00002000 // Remote Fault.
+#define PHY_MR4_A3 0x00000100 // Technology Ability Field[3].
+#define PHY_MR4_A2 0x00000080 // Technology Ability Field[2].
+#define PHY_MR4_A1 0x00000040 // Technology Ability Field[1].
+#define PHY_MR4_A0 0x00000020 // Technology Ability Field[0].
+#define PHY_MR4_S_M 0x0000001F // Selector Field.
+#define PHY_MR4_S_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MR5 register.
+//
+//*****************************************************************************
+#define PHY_MR5_NP 0x00008000 // Next Page.
+#define PHY_MR5_ACK 0x00004000 // Acknowledge.
+#define PHY_MR5_RF 0x00002000 // Remote Fault.
+#define PHY_MR5_A_M 0x00001FE0 // Technology Ability Field.
+#define PHY_MR5_S_M 0x0000001F // Selector Field.
+#define PHY_MR5_S_8023 0x00000001 // IEEE Std 802.3
+#define PHY_MR5_S_8029 0x00000002 // IEEE Std 802.9 ISLAN-16T
+#define PHY_MR5_S_8025 0x00000003 // IEEE Std 802.5
+#define PHY_MR5_S_1394 0x00000004 // IEEE Std 1394
+#define PHY_MR5_A_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MR6 register.
+//
+//*****************************************************************************
+#define PHY_MR6_PDF 0x00000010 // Parallel Detection Fault.
+#define PHY_MR6_LPNPA 0x00000008 // Link Partner is Next Page Able.
+#define PHY_MR6_PRX 0x00000002 // New Page Received.
+#define PHY_MR6_LPANEGA 0x00000001 // Link Partner is Auto-Negotiation
+ // Able.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_RCTL register.
+//
+//*****************************************************************************
+#define MAC_RCTL_RSTFIFO 0x00000010 // Clear Receive FIFO.
+#define MAC_RCTL_BADCRC 0x00000008 // Enable Reject Bad CRC.
+#define MAC_RCTL_PRMS 0x00000004 // Enable Promiscuous Mode.
+#define MAC_RCTL_AMUL 0x00000002 // Enable Multicast Frames.
+#define MAC_RCTL_RXEN 0x00000001 // Enable Receiver.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_TCTL register.
+//
+//*****************************************************************************
+#define MAC_TCTL_DUPLEX 0x00000010 // Enable Duplex Mode.
+#define MAC_TCTL_CRC 0x00000004 // Enable CRC Generation.
+#define MAC_TCTL_PADEN 0x00000002 // Enable Packet Padding.
+#define MAC_TCTL_TXEN 0x00000001 // Enable Transmitter.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_DATA register.
+//
+//*****************************************************************************
+#define MAC_DATA_TXDATA_M 0xFFFFFFFF // Transmit FIFO Data.
+#define MAC_DATA_RXDATA_M 0xFFFFFFFF // Receive FIFO Data.
+#define MAC_DATA_RXDATA_S 0
+#define MAC_DATA_TXDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MR16 register.
+//
+//*****************************************************************************
+#define PHY_MR16_RPTR 0x00008000 // Repeater Mode.
+#define PHY_MR16_INPOL 0x00004000 // Interrupt Polarity.
+#define PHY_MR16_TXHIM 0x00001000 // Transmit High Impedance Mode.
+#define PHY_MR16_SQEI 0x00000800 // SQE Inhibit Testing.
+#define PHY_MR16_NL10 0x00000400 // Natural Loopback Mode.
+#define PHY_MR16_APOL 0x00000020 // Auto-Polarity Disable.
+#define PHY_MR16_RVSPOL 0x00000010 // Receive Data Polarity.
+#define PHY_MR16_PCSBP 0x00000002 // PCS Bypass.
+#define PHY_MR16_RXCC 0x00000001 // Receive Clock Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MR17 register.
+//
+//*****************************************************************************
+#define PHY_MR17_JABBER_IE 0x00008000 // Jabber Interrupt Enable.
+#define PHY_MR17_RXER_IE 0x00004000 // Receive Error Interrupt Enable.
+#define PHY_MR17_PRX_IE 0x00002000 // Page Received Interrupt Enable.
+#define PHY_MR17_PDF_IE 0x00001000 // Parallel Detection Fault
+ // Interrupt Enable.
+#define PHY_MR17_LPACK_IE 0x00000800 // LP Acknowledge Interrupt Enable.
+#define PHY_MR17_LSCHG_IE 0x00000400 // Link Status Change Interrupt
+ // Enable.
+#define PHY_MR17_RFAULT_IE 0x00000200 // Remote Fault Interrupt Enable.
+#define PHY_MR17_ANEGCOMP_IE 0x00000100 // Auto-Negotiation Complete
+ // Interrupt Enable.
+#define PHY_MR17_JABBER_INT 0x00000080 // Jabber Event Interrupt.
+#define PHY_MR17_RXER_INT 0x00000040 // Receive Error Interrupt.
+#define PHY_MR17_PRX_INT 0x00000020 // Page Receive Interrupt.
+#define PHY_MR17_PDF_INT 0x00000010 // Parallel Detection Fault
+ // Interrupt.
+#define PHY_MR17_LPACK_INT 0x00000008 // LP Acknowledge Interrupt.
+#define PHY_MR17_LSCHG_INT 0x00000004 // Link Status Change Interrupt.
+#define PHY_MR17_RFAULT_INT 0x00000002 // Remote Fault Interrupt.
+#define PHY_MR17_ANEGCOMP_INT 0x00000001 // Auto-Negotiation Complete
+ // Interrupt.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MR18 register.
+//
+//*****************************************************************************
+#define PHY_MR18_ANEGF 0x00001000 // Auto-Negotiation Failure.
+#define PHY_MR18_DPLX 0x00000800 // Duplex Mode.
+#define PHY_MR18_RATE 0x00000400 // Rate.
+#define PHY_MR18_RXSD 0x00000200 // Receive Detection.
+#define PHY_MR18_RX_LOCK 0x00000100 // Receive PLL Lock.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MR19 register.
+//
+//*****************************************************************************
+#define PHY_MR19_TXO_M 0x0000C000 // Transmit Amplitude Selection.
+#define PHY_MR19_TXO_00DB 0x00000000 // Gain set for 0.0dB of insertion
+ // loss
+#define PHY_MR19_TXO_04DB 0x00004000 // Gain set for 0.4dB of insertion
+ // loss
+#define PHY_MR19_TXO_08DB 0x00008000 // Gain set for 0.8dB of insertion
+ // loss
+#define PHY_MR19_TXO_12DB 0x0000C000 // Gain set for 1.2dB of insertion
+ // loss
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_IA0 register.
+//
+//*****************************************************************************
+#define MAC_IA0_MACOCT4_M 0xFF000000 // MAC Address Octet 4.
+#define MAC_IA0_MACOCT3_M 0x00FF0000 // MAC Address Octet 3.
+#define MAC_IA0_MACOCT2_M 0x0000FF00 // MAC Address Octet 2.
+#define MAC_IA0_MACOCT1_M 0x000000FF // MAC Address Octet 1.
+#define MAC_IA0_MACOCT4_S 24
+#define MAC_IA0_MACOCT3_S 16
+#define MAC_IA0_MACOCT2_S 8
+#define MAC_IA0_MACOCT1_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MR23 register.
+//
+//*****************************************************************************
+#define PHY_MR23_LED1_M 0x000000F0 // LED1 Source.
+#define PHY_MR23_LED1_LINK 0x00000000 // Link OK
+#define PHY_MR23_LED1_RXTX 0x00000010 // RX or TX Activity (Default LED1)
+#define PHY_MR23_LED1_100 0x00000050 // 100BASE-TX mode
+#define PHY_MR23_LED1_10 0x00000060 // 10BASE-T mode
+#define PHY_MR23_LED1_DUPLEX 0x00000070 // Full-Duplex
+#define PHY_MR23_LED1_LINKACT 0x00000080 // Link OK & Blink=RX or TX
+ // Activity
+#define PHY_MR23_LED0_M 0x0000000F // LED0 Source.
+#define PHY_MR23_LED0_LINK 0x00000000 // Link OK (Default LED0)
+#define PHY_MR23_LED0_RXTX 0x00000001 // RX or TX Activity
+#define PHY_MR23_LED0_100 0x00000005 // 100BASE-TX mode
+#define PHY_MR23_LED0_10 0x00000006 // 10BASE-T mode
+#define PHY_MR23_LED0_DUPLEX 0x00000007 // Full-Duplex
+#define PHY_MR23_LED0_LINKACT 0x00000008 // Link OK & Blink=RX or TX
+ // Activity
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_IA1 register.
+//
+//*****************************************************************************
+#define MAC_IA1_MACOCT6_M 0x0000FF00 // MAC Address Octet 6.
+#define MAC_IA1_MACOCT5_M 0x000000FF // MAC Address Octet 5.
+#define MAC_IA1_MACOCT6_S 8
+#define MAC_IA1_MACOCT5_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MR24 register.
+//
+//*****************************************************************************
+#define PHY_MR24_PD_MODE 0x00000080 // Parallel Detection Mode.
+#define PHY_MR24_AUTO_SW 0x00000040 // Auto-Switching Enable.
+#define PHY_MR24_MDIX 0x00000020 // Auto-Switching Configuration.
+#define PHY_MR24_MDIX_CM 0x00000010 // Auto-Switching Complete.
+#define PHY_MR24_MDIX_SD_M 0x0000000F // Auto-Switching Seed.
+#define PHY_MR24_MDIX_SD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_THR register.
+//
+//*****************************************************************************
+#define MAC_THR_THRESH_M 0x0000003F // Threshold Value.
+#define MAC_THR_THRESH_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MCTL register.
+//
+//*****************************************************************************
+#define MAC_MCTL_REGADR_M 0x000000F8 // MII Register Address.
+#define MAC_MCTL_WRITE 0x00000002 // MII Register Transaction Type.
+#define MAC_MCTL_START 0x00000001 // MII Register Transaction Enable.
+#define MAC_MCTL_REGADR_S 3
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MDV register.
+//
+//*****************************************************************************
+#define MAC_MDV_DIV_M 0x000000FF // Clock Divider.
+#define MAC_MDV_DIV_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MTXD register.
+//
+//*****************************************************************************
+#define MAC_MTXD_MDTX_M 0x0000FFFF // MII Register Transmit Data.
+#define MAC_MTXD_MDTX_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MRXD register.
+//
+//*****************************************************************************
+#define MAC_MRXD_MDRX_M 0x0000FFFF // MII Register Receive Data.
+#define MAC_MRXD_MDRX_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_NP register.
+//
+//*****************************************************************************
+#define MAC_NP_NPR_M 0x0000003F // Number of Packets in Receive
+ // FIFO.
+#define MAC_NP_NPR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_TR register.
+//
+//*****************************************************************************
+#define MAC_TR_NEWTX 0x00000001 // New Transmission.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_TS register.
+//
+//*****************************************************************************
+#define MAC_TS_TSEN 0x00000001 // Time Stamp Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCC register.
+//
+//*****************************************************************************
+#define HIB_RTCC_M 0xFFFFFFFF // RTC Counter.
+#define HIB_RTCC_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCM0 register.
+//
+//*****************************************************************************
+#define HIB_RTCM0_M 0xFFFFFFFF // RTC Match 0.
+#define HIB_RTCM0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCM1 register.
+//
+//*****************************************************************************
+#define HIB_RTCM1_M 0xFFFFFFFF // RTC Match 1.
+#define HIB_RTCM1_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCLD register.
+//
+//*****************************************************************************
+#define HIB_RTCLD_M 0xFFFFFFFF // RTC Load.
+#define HIB_RTCLD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_CTL register.
+//
+//*****************************************************************************
+#define HIB_CTL_VABORT 0x00000080 // Power Cut Abort Enable.
+#define HIB_CTL_CLK32EN 0x00000040 // Clocking Enable.
+#define HIB_CTL_LOWBATEN 0x00000020 // Low Battery Monitoring Enable.
+#define HIB_CTL_PINWEN 0x00000010 // External WAKE Pin Enable.
+#define HIB_CTL_RTCWEN 0x00000008 // RTC Wake-up Enable.
+#define HIB_CTL_CLKSEL 0x00000004 // Hibernation Module Clock Select.
+#define HIB_CTL_HIBREQ 0x00000002 // Hibernation Request.
+#define HIB_CTL_RTCEN 0x00000001 // RTC Timer Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_IM register.
+//
+//*****************************************************************************
+#define HIB_IM_EXTW 0x00000008 // External Wake-Up Interrupt Mask.
+#define HIB_IM_LOWBAT 0x00000004 // Low Battery Voltage Interrupt
+ // Mask.
+#define HIB_IM_RTCALT1 0x00000002 // RTC Alert1 Interrupt Mask.
+#define HIB_IM_RTCALT0 0x00000001 // RTC Alert0 Interrupt Mask.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RIS register.
+//
+//*****************************************************************************
+#define HIB_RIS_EXTW 0x00000008 // External Wake-Up Raw Interrupt
+ // Status.
+#define HIB_RIS_LOWBAT 0x00000004 // Low Battery Voltage Raw
+ // Interrupt Status.
+#define HIB_RIS_RTCALT1 0x00000002 // RTC Alert1 Raw Interrupt Status.
+#define HIB_RIS_RTCALT0 0x00000001 // RTC Alert0 Raw Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_MIS register.
+//
+//*****************************************************************************
+#define HIB_MIS_EXTW 0x00000008 // External Wake-Up Masked
+ // Interrupt Status.
+#define HIB_MIS_LOWBAT 0x00000004 // Low Battery Voltage Masked
+ // Interrupt Status.
+#define HIB_MIS_RTCALT1 0x00000002 // RTC Alert1 Masked Interrupt
+ // Status.
+#define HIB_MIS_RTCALT0 0x00000001 // RTC Alert0 Masked Interrupt
+ // Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_IC register.
+//
+//*****************************************************************************
+#define HIB_IC_EXTW 0x00000008 // External Wake-Up Masked
+ // Interrupt Clear.
+#define HIB_IC_LOWBAT 0x00000004 // Low Battery Voltage Masked
+ // Interrupt Clear.
+#define HIB_IC_RTCALT1 0x00000002 // RTC Alert1 Masked Interrupt
+ // Clear.
+#define HIB_IC_RTCALT0 0x00000001 // RTC Alert0 Masked Interrupt
+ // Clear.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCT register.
+//
+//*****************************************************************************
+#define HIB_RTCT_TRIM_M 0x0000FFFF // RTC Trim Value.
+#define HIB_RTCT_TRIM_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_DATA register.
+//
+//*****************************************************************************
+#define HIB_DATA_RTD_M 0xFFFFFFFF // Hibernation Module NV
+ // Registers[63:0].
+#define HIB_DATA_RTD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMA register.
+//
+//*****************************************************************************
+#define FLASH_FMA_OFFSET_M 0x0003FFFF // Address Offset.
+#define FLASH_FMA_OFFSET_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMD register.
+//
+//*****************************************************************************
+#define FLASH_FMD_DATA_M 0xFFFFFFFF // Data Value.
+#define FLASH_FMD_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMC register.
+//
+//*****************************************************************************
+#define FLASH_FMC_WRKEY_M 0xFFFF0000 // Flash Write Key.
+#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key
+#define FLASH_FMC_COMT 0x00000008 // Commit Register Value.
+#define FLASH_FMC_MERASE 0x00000004 // Mass Erase Flash Memory.
+#define FLASH_FMC_ERASE 0x00000002 // Erase a Page of Flash Memory.
+#define FLASH_FMC_WRITE 0x00000001 // Write a Word into Flash Memory.
+#define FLASH_FMC_WRKEY_S 16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FCRIS register.
+//
+//*****************************************************************************
+#define FLASH_FCRIS_PRIS 0x00000002 // Programming Raw Interrupt
+ // Status.
+#define FLASH_FCRIS_ARIS 0x00000001 // Access Raw Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FCIM register.
+//
+//*****************************************************************************
+#define FLASH_FCIM_PMASK 0x00000002 // Programming Interrupt Mask.
+#define FLASH_FCIM_AMASK 0x00000001 // Access Interrupt Mask.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FCMISC register.
+//
+//*****************************************************************************
+#define FLASH_FCMISC_PMISC 0x00000002 // Programming Masked Interrupt
+ // Status and Clear.
+#define FLASH_FCMISC_AMISC 0x00000001 // Access Masked Interrupt Status
+ // and Clear.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USECRL register.
+//
+//*****************************************************************************
+#define FLASH_USECRL_M 0x000000FF // Microsecond Reload Value.
+#define FLASH_USECRL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERDBG register.
+//
+//*****************************************************************************
+#define FLASH_USERDBG_NW 0x80000000 // User Debug Not Written.
+#define FLASH_USERDBG_DATA_M 0x7FFFFFFC // User Data.
+#define FLASH_USERDBG_DBG1 0x00000002 // Debug Control 1.
+#define FLASH_USERDBG_DBG0 0x00000001 // Debug Control 0.
+#define FLASH_USERDBG_DATA_S 2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG0 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG0_NW 0x80000000 // Not Written.
+#define FLASH_USERREG0_DATA_M 0x7FFFFFFF // User Data.
+#define FLASH_USERREG0_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG1 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG1_NW 0x80000000 // Not Written.
+#define FLASH_USERREG1_DATA_M 0x7FFFFFFF // User Data.
+#define FLASH_USERREG1_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the erase size of the FLASH block that is
+// erased by an erase operation, and the protect size is the size of the FLASH
+// block that is protected by each protection register.
+//
+//*****************************************************************************
+#define FLASH_PROTECT_SIZE 0x00000800
+#define FLASH_ERASE_SIZE 0x00000400
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DID0 register.
+//
+//*****************************************************************************
+#define SYSCTL_DID0_VER_M 0x70000000 // DID0 Version.
+#define SYSCTL_DID0_VER_1 0x10000000 // Second version of the DID0
+ // register format.
+#define SYSCTL_DID0_CLASS_M 0x00FF0000 // Device Class.
+#define SYSCTL_DID0_CLASS_FURY 0x00010000 // Stellaris(r) Fury-class devices.
+#define SYSCTL_DID0_MAJ_M 0x0000FF00 // Major Revision.
+#define SYSCTL_DID0_MAJ_REVA 0x00000000 // Revision A (initial device)
+#define SYSCTL_DID0_MAJ_REVB 0x00000100 // Revision B (first base layer
+ // revision)
+#define SYSCTL_DID0_MAJ_REVC 0x00000200 // Revision C (second base layer
+ // revision)
+#define SYSCTL_DID0_MIN_M 0x000000FF // Minor Revision.
+#define SYSCTL_DID0_MIN_0 0x00000000 // Initial device, or a major
+ // revision update.
+#define SYSCTL_DID0_MIN_1 0x00000001 // First metal layer change.
+#define SYSCTL_DID0_MIN_2 0x00000002 // Second metal layer change.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DID1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DID1_VER_M 0xF0000000 // DID1 Version.
+#define SYSCTL_DID1_VER_1 0x10000000 // Second version of the DID1
+ // register format.
+#define SYSCTL_DID1_FAM_M 0x0F000000 // Family.
+#define SYSCTL_DID1_FAM_STELLARIS \
+ 0x00000000 // Stellaris family of
+ // microcontollers, that is, all
+ // devices with external part
+ // numbers starting with LM3S.
+#define SYSCTL_DID1_PRTNO_M 0x00FF0000 // Part Number.
+#define SYSCTL_DID1_PRTNO_8962 0x00A60000 // LM3S8962
+#define SYSCTL_DID1_PINCNT_M 0x0000E000 // Package Pin Count.
+#define SYSCTL_DID1_PINCNT_100 0x00004000 // 100-pin or 108-ball package
+#define SYSCTL_DID1_TEMP_M 0x000000E0 // Temperature Range.
+#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temperature range (0C
+ // to 70C)
+#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temperature range
+ // (-40C to 85C)
+#define SYSCTL_DID1_TEMP_E 0x00000040 // Extended temperature range (-40C
+ // to 105C)
+#define SYSCTL_DID1_PKG_M 0x00000018 // Package Type.
+#define SYSCTL_DID1_PKG_28SOIC 0x00000000 // SOIC package
+#define SYSCTL_DID1_PKG_48QFP 0x00000008 // LQFP package
+#define SYSCTL_DID1_PKG_BGA 0x00000010 // BGA package
+#define SYSCTL_DID1_ROHS 0x00000004 // RoHS-Compliance.
+#define SYSCTL_DID1_QUAL_M 0x00000003 // Qualification Status.
+#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering Sample (unqualified)
+#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot Production (unqualified)
+#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully Qualified
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC0_SRAMSZ_M 0xFFFF0000 // SRAM Size.
+#define SYSCTL_DC0_SRAMSZ_64KB 0x00FF0000 // 64 KB of SRAM
+#define SYSCTL_DC0_FLASHSZ_M 0x0000FFFF // Flash Size.
+#define SYSCTL_DC0_FLASHSZ_256K 0x0000007F // 256 KB of Flash
+#define SYSCTL_DC0_SRAMSZ_S 16 // SRAM size shift
+#define SYSCTL_DC0_FLASHSZ_S 0 // Flash size shift
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC1_CAN0 0x01000000 // CAN Module 0 Present.
+#define SYSCTL_DC1_PWM 0x00100000 // PWM Module Present.
+#define SYSCTL_DC1_ADC 0x00010000 // ADC Module Present.
+#define SYSCTL_DC1_MINSYSDIV_M 0x0000F000 // System Clock Divider.
+#define SYSCTL_DC1_MINSYSDIV_50 0x00003000 // Specifies a 50-MHz CPU clock
+ // with a PLL divider of 4.
+#define SYSCTL_DC1_ADCSPD_M 0x00000300 // Max ADC Speed.
+#define SYSCTL_DC1_ADCSPD_500K 0x00000200 // 500K samples/second
+#define SYSCTL_DC1_MPU 0x00000080 // MPU Present.
+#define SYSCTL_DC1_HIB 0x00000040 // Hibernation Module Present.
+#define SYSCTL_DC1_TEMP 0x00000020 // Temp Sensor Present.
+#define SYSCTL_DC1_PLL 0x00000010 // PLL Present.
+#define SYSCTL_DC1_WDT 0x00000008 // Watchdog Timer Present.
+#define SYSCTL_DC1_SWO 0x00000004 // SWO Trace Port Present.
+#define SYSCTL_DC1_SWD 0x00000002 // SWD Present.
+#define SYSCTL_DC1_JTAG 0x00000001 // JTAG Present.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC2_COMP0 0x01000000 // Analog Comparator 0 Present.
+#define SYSCTL_DC2_TIMER3 0x00080000 // Timer 3 Present.
+#define SYSCTL_DC2_TIMER2 0x00040000 // Timer 2 Present.
+#define SYSCTL_DC2_TIMER1 0x00020000 // Timer 1 Present.
+#define SYSCTL_DC2_TIMER0 0x00010000 // Timer 0 Present.
+#define SYSCTL_DC2_I2C0 0x00001000 // I2C Module 0 Present.
+#define SYSCTL_DC2_QEI1 0x00000200 // QEI1 Present.
+#define SYSCTL_DC2_QEI0 0x00000100 // QEI0 Present.
+#define SYSCTL_DC2_SSI0 0x00000010 // SSI0 Present.
+#define SYSCTL_DC2_UART1 0x00000002 // UART1 Present.
+#define SYSCTL_DC2_UART0 0x00000001 // UART0 Present.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC3 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC3_32KHZ 0x80000000 // 32KHz Input Clock Available.
+#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 Pin Present.
+#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 Pin Present.
+#define SYSCTL_DC3_ADC3 0x00080000 // ADC3 Pin Present.
+#define SYSCTL_DC3_ADC2 0x00040000 // ADC2 Pin Present.
+#define SYSCTL_DC3_ADC1 0x00020000 // ADC1 Pin Present.
+#define SYSCTL_DC3_ADC0 0x00010000 // ADC0 Pin Present.
+#define SYSCTL_DC3_PWMFAULT 0x00008000 // PWM Fault Pin Present.
+#define SYSCTL_DC3_C0O 0x00000100 // C0o Pin Present.
+#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ Pin Present.
+#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- Pin Present.
+#define SYSCTL_DC3_PWM5 0x00000020 // PWM5 Pin Present.
+#define SYSCTL_DC3_PWM4 0x00000010 // PWM4 Pin Present.
+#define SYSCTL_DC3_PWM3 0x00000008 // PWM3 Pin Present.
+#define SYSCTL_DC3_PWM2 0x00000004 // PWM2 Pin Present.
+#define SYSCTL_DC3_PWM1 0x00000002 // PWM1 Pin Present.
+#define SYSCTL_DC3_PWM0 0x00000001 // PWM0 Pin Present.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC4 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC4_EPHY0 0x40000000 // Ethernet PHY0 Present.
+#define SYSCTL_DC4_EMAC0 0x10000000 // Ethernet MAC0 Present.
+#define SYSCTL_DC4_E1588 0x01000000 // 1588 Capable.
+#define SYSCTL_DC4_GPIOG 0x00000040 // GPIO Port G Present.
+#define SYSCTL_DC4_GPIOF 0x00000020 // GPIO Port F Present.
+#define SYSCTL_DC4_GPIOE 0x00000010 // GPIO Port E Present.
+#define SYSCTL_DC4_GPIOD 0x00000008 // GPIO Port D Present.
+#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO Port C Present.
+#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO Port B Present.
+#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO Port A Present.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PBORCTL register.
+//
+//*****************************************************************************
+#define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR Interrupt or Reset.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_LDOPCTL register.
+//
+//*****************************************************************************
+#define SYSCTL_LDOPCTL_M 0x0000003F // LDO Output Voltage.
+#define SYSCTL_LDOPCTL_2_50V 0x00000000 // 2.50
+#define SYSCTL_LDOPCTL_2_45V 0x00000001 // 2.45
+#define SYSCTL_LDOPCTL_2_40V 0x00000002 // 2.40
+#define SYSCTL_LDOPCTL_2_35V 0x00000003 // 2.35
+#define SYSCTL_LDOPCTL_2_30V 0x00000004 // 2.30
+#define SYSCTL_LDOPCTL_2_25V 0x00000005 // 2.25
+#define SYSCTL_LDOPCTL_2_75V 0x0000001B // 2.75
+#define SYSCTL_LDOPCTL_2_70V 0x0000001C // 2.70
+#define SYSCTL_LDOPCTL_2_65V 0x0000001D // 2.65
+#define SYSCTL_LDOPCTL_2_60V 0x0000001E // 2.60
+#define SYSCTL_LDOPCTL_2_55V 0x0000001F // 2.55
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCR0 register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCR0_CAN0 0x01000000 // CAN0 Reset Control.
+#define SYSCTL_SRCR0_PWM 0x00100000 // PWM Reset Control.
+#define SYSCTL_SRCR0_ADC 0x00010000 // ADC0 Reset Control.
+#define SYSCTL_SRCR0_HIB 0x00000040 // HIB Reset Control.
+#define SYSCTL_SRCR0_WDT 0x00000008 // WDT Reset Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCR1 register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCR1_COMP0 0x01000000 // Analog Comp 0 Reset Control.
+#define SYSCTL_SRCR1_TIMER3 0x00080000 // Timer 3 Reset Control.
+#define SYSCTL_SRCR1_TIMER2 0x00040000 // Timer 2 Reset Control.
+#define SYSCTL_SRCR1_TIMER1 0x00020000 // Timer 1 Reset Control.
+#define SYSCTL_SRCR1_TIMER0 0x00010000 // Timer 0 Reset Control.
+#define SYSCTL_SRCR1_I2C0 0x00001000 // I2C0 Reset Control.
+#define SYSCTL_SRCR1_QEI1 0x00000200 // QEI1 Reset Control.
+#define SYSCTL_SRCR1_QEI0 0x00000100 // QEI0 Reset Control.
+#define SYSCTL_SRCR1_SSI0 0x00000010 // SSI0 Reset Control.
+#define SYSCTL_SRCR1_UART1 0x00000002 // UART1 Reset Control.
+#define SYSCTL_SRCR1_UART0 0x00000001 // UART0 Reset Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCR2 register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCR2_EPHY0 0x40000000 // PHY0 Reset Control.
+#define SYSCTL_SRCR2_EMAC0 0x10000000 // MAC0 Reset Control.
+#define SYSCTL_SRCR2_GPIOG 0x00000040 // Port G Reset Control.
+#define SYSCTL_SRCR2_GPIOF 0x00000020 // Port F Reset Control.
+#define SYSCTL_SRCR2_GPIOE 0x00000010 // Port E Reset Control.
+#define SYSCTL_SRCR2_GPIOD 0x00000008 // Port D Reset Control.
+#define SYSCTL_SRCR2_GPIOC 0x00000004 // Port C Reset Control.
+#define SYSCTL_SRCR2_GPIOB 0x00000002 // Port B Reset Control.
+#define SYSCTL_SRCR2_GPIOA 0x00000001 // Port A Reset Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RIS register.
+//
+//*****************************************************************************
+#define SYSCTL_RIS_PLLLRIS 0x00000040 // PLL Lock Raw Interrupt Status.
+#define SYSCTL_RIS_BORRIS 0x00000002 // Brown-Out Reset Raw Interrupt
+ // Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_IMC register.
+//
+//*****************************************************************************
+#define SYSCTL_IMC_PLLLIM 0x00000040 // PLL Lock Interrupt Mask.
+#define SYSCTL_IMC_BORIM 0x00000002 // Brown-Out Reset Interrupt Mask.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_MISC register.
+//
+//*****************************************************************************
+#define SYSCTL_MISC_PLLLMIS 0x00000040 // PLL Lock Masked Interrupt
+ // Status.
+#define SYSCTL_MISC_BORMIS 0x00000002 // BOR Masked Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RESC register.
+//
+//*****************************************************************************
+#define SYSCTL_RESC_LDO 0x00000020 // LDO Reset.
+#define SYSCTL_RESC_SW 0x00000010 // Software Reset.
+#define SYSCTL_RESC_WDT 0x00000008 // Watchdog Timer Reset.
+#define SYSCTL_RESC_BOR 0x00000004 // Brown-Out Reset.
+#define SYSCTL_RESC_POR 0x00000002 // Power-On Reset.
+#define SYSCTL_RESC_EXT 0x00000001 // External Reset.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCC register.
+//
+//*****************************************************************************
+#define SYSCTL_RCC_ACG 0x08000000 // Auto Clock Gating.
+#define SYSCTL_RCC_SYSDIV_M 0x07800000 // System Clock Divisor.
+#define SYSCTL_RCC_SYSDIV_2 0x00800000 // /2
+#define SYSCTL_RCC_SYSDIV_3 0x01000000 // /3
+#define SYSCTL_RCC_SYSDIV_4 0x01800000 // /4
+#define SYSCTL_RCC_SYSDIV_5 0x02000000 // /5
+#define SYSCTL_RCC_SYSDIV_6 0x02800000 // /6
+#define SYSCTL_RCC_SYSDIV_7 0x03000000 // /7
+#define SYSCTL_RCC_SYSDIV_8 0x03800000 // /8
+#define SYSCTL_RCC_SYSDIV_9 0x04000000 // /9
+#define SYSCTL_RCC_SYSDIV_10 0x04800000 // /10
+#define SYSCTL_RCC_SYSDIV_11 0x05000000 // /11
+#define SYSCTL_RCC_SYSDIV_12 0x05800000 // /12
+#define SYSCTL_RCC_SYSDIV_13 0x06000000 // /13
+#define SYSCTL_RCC_SYSDIV_14 0x06800000 // /14
+#define SYSCTL_RCC_SYSDIV_15 0x07000000 // /15
+#define SYSCTL_RCC_SYSDIV_16 0x07800000 // /16
+#define SYSCTL_RCC_USESYSDIV 0x00400000 // Enable System Clock Divider.
+#define SYSCTL_RCC_USEPWMDIV 0x00100000 // Enable PWM Clock Divisor.
+#define SYSCTL_RCC_PWMDIV_M 0x000E0000 // PWM Unit Clock Divisor.
+#define SYSCTL_RCC_PWMDIV_2 0x00000000 // /2
+#define SYSCTL_RCC_PWMDIV_4 0x00020000 // /4
+#define SYSCTL_RCC_PWMDIV_8 0x00040000 // /8
+#define SYSCTL_RCC_PWMDIV_16 0x00060000 // /16
+#define SYSCTL_RCC_PWMDIV_32 0x00080000 // /32
+#define SYSCTL_RCC_PWMDIV_64 0x000A0000 // /64
+#define SYSCTL_RCC_PWRDN 0x00002000 // PLL Power Down.
+#define SYSCTL_RCC_BYPASS 0x00000800 // PLL Bypass.
+#define SYSCTL_RCC_XTAL_M 0x000003C0 // Crystal Value.
+#define SYSCTL_RCC_XTAL_1MHZ 0x00000000 // 1.000
+#define SYSCTL_RCC_XTAL_1_84MHZ 0x00000040 // 1.8432
+#define SYSCTL_RCC_XTAL_2MHZ 0x00000080 // 2.000
+#define SYSCTL_RCC_XTAL_2_45MHZ 0x000000C0 // 2.4576
+#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100 // 3.579545 MHz
+#define SYSCTL_RCC_XTAL_3_68MHZ 0x00000140 // 3.6864 MHz
+#define SYSCTL_RCC_XTAL_4MHZ 0x00000180 // 4 MHz
+#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // 4.096 MHz
+#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // 4.9152 MHz
+#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // 5 MHz
+#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // 5.12 MHz
+#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // 6 MHz (reset value)
+#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // 6.144 MHz
+#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // 7.3728 MHz
+#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // 8 MHz
+#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // 8.192 MHz
+#define SYSCTL_RCC_OSCSRC_M 0x00000030 // Oscillator Source.
+#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // MOSC
+#define SYSCTL_RCC_OSCSRC_INT 0x00000010 // IOSC
+#define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // IOSC/4
+#define SYSCTL_RCC_OSCSRC_30 0x00000030 // 30 kHz
+#define SYSCTL_RCC_IOSCDIS 0x00000002 // Internal Oscillator Disable.
+#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main Oscillator Disable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PLLCFG register.
+//
+//*****************************************************************************
+#define SYSCTL_PLLCFG_F_M 0x00003FE0 // PLL F Value.
+#define SYSCTL_PLLCFG_R_M 0x0000001F // PLL R Value.
+#define SYSCTL_PLLCFG_F_S 5
+#define SYSCTL_PLLCFG_R_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCC2_USERCC2 0x80000000 // Use RCC2.
+#define SYSCTL_RCC2_SYSDIV2_M 0x1F800000 // System Clock Divisor.
+#define SYSCTL_RCC2_SYSDIV2_2 0x00800000 // System clock /2
+#define SYSCTL_RCC2_SYSDIV2_3 0x01000000 // System clock /3
+#define SYSCTL_RCC2_SYSDIV2_4 0x01800000 // System clock /4
+#define SYSCTL_RCC2_SYSDIV2_5 0x02000000 // System clock /5
+#define SYSCTL_RCC2_SYSDIV2_6 0x02800000 // System clock /6
+#define SYSCTL_RCC2_SYSDIV2_7 0x03000000 // System clock /7
+#define SYSCTL_RCC2_SYSDIV2_8 0x03800000 // System clock /8
+#define SYSCTL_RCC2_SYSDIV2_9 0x04000000 // System clock /9
+#define SYSCTL_RCC2_SYSDIV2_10 0x04800000 // System clock /10
+#define SYSCTL_RCC2_SYSDIV2_11 0x05000000 // System clock /11
+#define SYSCTL_RCC2_SYSDIV2_12 0x05800000 // System clock /12
+#define SYSCTL_RCC2_SYSDIV2_13 0x06000000 // System clock /13
+#define SYSCTL_RCC2_SYSDIV2_14 0x06800000 // System clock /14
+#define SYSCTL_RCC2_SYSDIV2_15 0x07000000 // System clock /15
+#define SYSCTL_RCC2_SYSDIV2_16 0x07800000 // System clock /16
+#define SYSCTL_RCC2_SYSDIV2_17 0x08000000 // System clock /17
+#define SYSCTL_RCC2_SYSDIV2_18 0x08800000 // System clock /18
+#define SYSCTL_RCC2_SYSDIV2_19 0x09000000 // System clock /19
+#define SYSCTL_RCC2_SYSDIV2_20 0x09800000 // System clock /20
+#define SYSCTL_RCC2_SYSDIV2_21 0x0A000000 // System clock /21
+#define SYSCTL_RCC2_SYSDIV2_22 0x0A800000 // System clock /22
+#define SYSCTL_RCC2_SYSDIV2_23 0x0B000000 // System clock /23
+#define SYSCTL_RCC2_SYSDIV2_24 0x0B800000 // System clock /24
+#define SYSCTL_RCC2_SYSDIV2_25 0x0C000000 // System clock /25
+#define SYSCTL_RCC2_SYSDIV2_26 0x0C800000 // System clock /26
+#define SYSCTL_RCC2_SYSDIV2_27 0x0D000000 // System clock /27
+#define SYSCTL_RCC2_SYSDIV2_28 0x0D800000 // System clock /28
+#define SYSCTL_RCC2_SYSDIV2_29 0x0E000000 // System clock /29
+#define SYSCTL_RCC2_SYSDIV2_30 0x0E800000 // System clock /30
+#define SYSCTL_RCC2_SYSDIV2_31 0x0F000000 // System clock /31
+#define SYSCTL_RCC2_SYSDIV2_32 0x0F800000 // System clock /32
+#define SYSCTL_RCC2_SYSDIV2_33 0x10000000 // System clock /33
+#define SYSCTL_RCC2_SYSDIV2_34 0x10800000 // System clock /34
+#define SYSCTL_RCC2_SYSDIV2_35 0x11000000 // System clock /35
+#define SYSCTL_RCC2_SYSDIV2_36 0x11800000 // System clock /36
+#define SYSCTL_RCC2_SYSDIV2_37 0x12000000 // System clock /37
+#define SYSCTL_RCC2_SYSDIV2_38 0x12800000 // System clock /38
+#define SYSCTL_RCC2_SYSDIV2_39 0x13000000 // System clock /39
+#define SYSCTL_RCC2_SYSDIV2_40 0x13800000 // System clock /40
+#define SYSCTL_RCC2_SYSDIV2_41 0x14000000 // System clock /41
+#define SYSCTL_RCC2_SYSDIV2_42 0x14800000 // System clock /42
+#define SYSCTL_RCC2_SYSDIV2_43 0x15000000 // System clock /43
+#define SYSCTL_RCC2_SYSDIV2_44 0x15800000 // System clock /44
+#define SYSCTL_RCC2_SYSDIV2_45 0x16000000 // System clock /45
+#define SYSCTL_RCC2_SYSDIV2_46 0x16800000 // System clock /46
+#define SYSCTL_RCC2_SYSDIV2_47 0x17000000 // System clock /47
+#define SYSCTL_RCC2_SYSDIV2_48 0x17800000 // System clock /48
+#define SYSCTL_RCC2_SYSDIV2_49 0x18000000 // System clock /49
+#define SYSCTL_RCC2_SYSDIV2_50 0x18800000 // System clock /50
+#define SYSCTL_RCC2_SYSDIV2_51 0x19000000 // System clock /51
+#define SYSCTL_RCC2_SYSDIV2_52 0x19800000 // System clock /52
+#define SYSCTL_RCC2_SYSDIV2_53 0x1A000000 // System clock /53
+#define SYSCTL_RCC2_SYSDIV2_54 0x1A800000 // System clock /54
+#define SYSCTL_RCC2_SYSDIV2_55 0x1B000000 // System clock /55
+#define SYSCTL_RCC2_SYSDIV2_56 0x1B800000 // System clock /56
+#define SYSCTL_RCC2_SYSDIV2_57 0x1C000000 // System clock /57
+#define SYSCTL_RCC2_SYSDIV2_58 0x1C800000 // System clock /58
+#define SYSCTL_RCC2_SYSDIV2_59 0x1D000000 // System clock /59
+#define SYSCTL_RCC2_SYSDIV2_60 0x1D800000 // System clock /60
+#define SYSCTL_RCC2_SYSDIV2_61 0x1E000000 // System clock /61
+#define SYSCTL_RCC2_SYSDIV2_62 0x1E800000 // System clock /62
+#define SYSCTL_RCC2_SYSDIV2_63 0x1F000000 // System clock /63
+#define SYSCTL_RCC2_SYSDIV2_64 0x1F800000 // System clock /64
+#define SYSCTL_RCC2_PWRDN2 0x00002000 // Power-Down PLL.
+#define SYSCTL_RCC2_BYPASS2 0x00000800 // Bypass PLL.
+#define SYSCTL_RCC2_OSCSRC2_M 0x00000070 // Oscillator Source.
+#define SYSCTL_RCC2_OSCSRC2_MO 0x00000000 // MOSC
+#define SYSCTL_RCC2_OSCSRC2_IO 0x00000010 // IOSC
+#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020 // IOSC/4
+#define SYSCTL_RCC2_OSCSRC2_30 0x00000030 // 30 kHz
+#define SYSCTL_RCC2_OSCSRC2_32 0x00000070 // 32 kHz
+#define SYSCTL_RCC2_SYSDIV2_S 23
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control.
+#define SYSCTL_RCGC0_PWM 0x00100000 // PWM Clock Gating Control.
+#define SYSCTL_RCGC0_ADC 0x00010000 // ADC0 Clock Gating Control.
+#define SYSCTL_RCGC0_ADCSPD_M 0x00000300 // ADC Sample Speed.
+#define SYSCTL_RCGC0_ADCSPD125K 0x00000000 // 125K samples/second
+#define SYSCTL_RCGC0_ADCSPD250K 0x00000100 // 250K samples/second
+#define SYSCTL_RCGC0_ADCSPD500K 0x00000200 // 500K samples/second
+#define SYSCTL_RCGC0_HIB 0x00000040 // HIB Clock Gating Control.
+#define SYSCTL_RCGC0_WDT 0x00000008 // WDT Clock Gating Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock
+ // Gating.
+#define SYSCTL_RCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control.
+#define SYSCTL_RCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control.
+#define SYSCTL_RCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control.
+#define SYSCTL_RCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control.
+#define SYSCTL_RCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control.
+#define SYSCTL_RCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control.
+#define SYSCTL_RCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control.
+#define SYSCTL_RCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control.
+#define SYSCTL_RCGC1_UART1 0x00000002 // UART1 Clock Gating Control.
+#define SYSCTL_RCGC1_UART0 0x00000001 // UART0 Clock Gating Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGC2_EPHY0 0x40000000 // PHY0 Clock Gating Control.
+#define SYSCTL_RCGC2_EMAC0 0x10000000 // MAC0 Clock Gating Control.
+#define SYSCTL_RCGC2_GPIOG 0x00000040 // Port G Clock Gating Control.
+#define SYSCTL_RCGC2_GPIOF 0x00000020 // Port F Clock Gating Control.
+#define SYSCTL_RCGC2_GPIOE 0x00000010 // Port E Clock Gating Control.
+#define SYSCTL_RCGC2_GPIOD 0x00000008 // Port D Clock Gating Control.
+#define SYSCTL_RCGC2_GPIOC 0x00000004 // Port C Clock Gating Control.
+#define SYSCTL_RCGC2_GPIOB 0x00000002 // Port B Clock Gating Control.
+#define SYSCTL_RCGC2_GPIOA 0x00000001 // Port A Clock Gating Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control.
+#define SYSCTL_SCGC0_PWM 0x00100000 // PWM Clock Gating Control.
+#define SYSCTL_SCGC0_ADC 0x00010000 // ADC0 Clock Gating Control.
+#define SYSCTL_SCGC0_ADCSPD_M 0x00000300 // ADC Sample Speed.
+#define SYSCTL_SCGC0_ADCSPD125K 0x00000000 // 125K samples/second
+#define SYSCTL_SCGC0_ADCSPD250K 0x00000100 // 250K samples/second
+#define SYSCTL_SCGC0_ADCSPD500K 0x00000200 // 500K samples/second
+#define SYSCTL_SCGC0_HIB 0x00000040 // HIB Clock Gating Control.
+#define SYSCTL_SCGC0_WDT 0x00000008 // WDT Clock Gating Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock
+ // Gating.
+#define SYSCTL_SCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control.
+#define SYSCTL_SCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control.
+#define SYSCTL_SCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control.
+#define SYSCTL_SCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control.
+#define SYSCTL_SCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control.
+#define SYSCTL_SCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control.
+#define SYSCTL_SCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control.
+#define SYSCTL_SCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control.
+#define SYSCTL_SCGC1_UART1 0x00000002 // UART1 Clock Gating Control.
+#define SYSCTL_SCGC1_UART0 0x00000001 // UART0 Clock Gating Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGC2_EPHY0 0x40000000 // PHY0 Clock Gating Control.
+#define SYSCTL_SCGC2_EMAC0 0x10000000 // MAC0 Clock Gating Control.
+#define SYSCTL_SCGC2_GPIOG 0x00000040 // Port G Clock Gating Control.
+#define SYSCTL_SCGC2_GPIOF 0x00000020 // Port F Clock Gating Control.
+#define SYSCTL_SCGC2_GPIOE 0x00000010 // Port E Clock Gating Control.
+#define SYSCTL_SCGC2_GPIOD 0x00000008 // Port D Clock Gating Control.
+#define SYSCTL_SCGC2_GPIOC 0x00000004 // Port C Clock Gating Control.
+#define SYSCTL_SCGC2_GPIOB 0x00000002 // Port B Clock Gating Control.
+#define SYSCTL_SCGC2_GPIOA 0x00000001 // Port A Clock Gating Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control.
+#define SYSCTL_DCGC0_PWM 0x00100000 // PWM Clock Gating Control.
+#define SYSCTL_DCGC0_ADC 0x00010000 // ADC0 Clock Gating Control.
+#define SYSCTL_DCGC0_ADCSPD_M 0x00000300 // ADC Sample Speed.
+#define SYSCTL_DCGC0_ADCSPD125K 0x00000000 // 125K samples/second
+#define SYSCTL_DCGC0_ADCSPD250K 0x00000100 // 250K samples/second
+#define SYSCTL_DCGC0_ADCSPD500K 0x00000200 // 500K samples/second
+#define SYSCTL_DCGC0_HIB 0x00000040 // HIB Clock Gating Control.
+#define SYSCTL_DCGC0_WDT 0x00000008 // WDT Clock Gating Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock
+ // Gating.
+#define SYSCTL_DCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control.
+#define SYSCTL_DCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control.
+#define SYSCTL_DCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control.
+#define SYSCTL_DCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control.
+#define SYSCTL_DCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control.
+#define SYSCTL_DCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control.
+#define SYSCTL_DCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control.
+#define SYSCTL_DCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control.
+#define SYSCTL_DCGC1_UART1 0x00000002 // UART1 Clock Gating Control.
+#define SYSCTL_DCGC1_UART0 0x00000001 // UART0 Clock Gating Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGC2_EPHY0 0x40000000 // PHY0 Clock Gating Control.
+#define SYSCTL_DCGC2_EMAC0 0x10000000 // MAC0 Clock Gating Control.
+#define SYSCTL_DCGC2_GPIOG 0x00000040 // Port G Clock Gating Control.
+#define SYSCTL_DCGC2_GPIOF 0x00000020 // Port F Clock Gating Control.
+#define SYSCTL_DCGC2_GPIOE 0x00000010 // Port E Clock Gating Control.
+#define SYSCTL_DCGC2_GPIOD 0x00000008 // Port D Clock Gating Control.
+#define SYSCTL_DCGC2_GPIOC 0x00000004 // Port C Clock Gating Control.
+#define SYSCTL_DCGC2_GPIOB 0x00000002 // Port B Clock Gating Control.
+#define SYSCTL_DCGC2_GPIOA 0x00000001 // Port A Clock Gating Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DSLPCLKCFG
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DSLPCLKCFG_D_M 0x1F800000 // Divider Field Override.
+#define SYSCTL_DSLPCLKCFG_O_M 0x00000070 // Clock Source.
+#define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000 // MOSC
+#define SYSCTL_DSLPCLKCFG_O_IO 0x00000010 // IOSC
+#define SYSCTL_DSLPCLKCFG_O_30 0x00000030 // 30 kHz
+#define SYSCTL_DSLPCLKCFG_O_32 0x00000070 // 32 kHz
+#define SYSCTL_DSLPCLKCFG_D_S 23
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_INT_TYPE register.
+//
+//*****************************************************************************
+#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32)
+#define NVIC_INT_TYPE_LINES_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_ST_CTRL_COUNT 0x00010000 // Count flag
+#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source
+#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt enable
+#define NVIC_ST_CTRL_ENABLE 0x00000001 // Counter mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_RELOAD register.
+//
+//*****************************************************************************
+#define NVIC_ST_RELOAD_M 0x00FFFFFF // Counter load value
+#define NVIC_ST_RELOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_CURRENT
+// register.
+//
+//*****************************************************************************
+#define NVIC_ST_CURRENT_M 0x00FFFFFF // Counter current value
+#define NVIC_ST_CURRENT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_CAL register.
+//
+//*****************************************************************************
+#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock
+#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew
+#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value
+#define NVIC_ST_CAL_ONEMS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN0 register.
+//
+//*****************************************************************************
+#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable
+#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable
+#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable
+#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable
+#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable
+#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable
+#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable
+#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable
+#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable
+#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable
+#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable
+#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable
+#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable
+#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable
+#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable
+#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable
+#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable
+#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable
+#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable
+#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable
+#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable
+#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable
+#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable
+#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable
+#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable
+#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable
+#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable
+#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable
+#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable
+#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable
+#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable
+#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN1 register.
+//
+//*****************************************************************************
+#define NVIC_EN1_INT59 0x08000000 // Interrupt 59 enable
+#define NVIC_EN1_INT58 0x04000000 // Interrupt 58 enable
+#define NVIC_EN1_INT57 0x02000000 // Interrupt 57 enable
+#define NVIC_EN1_INT56 0x01000000 // Interrupt 56 enable
+#define NVIC_EN1_INT55 0x00800000 // Interrupt 55 enable
+#define NVIC_EN1_INT54 0x00400000 // Interrupt 54 enable
+#define NVIC_EN1_INT53 0x00200000 // Interrupt 53 enable
+#define NVIC_EN1_INT52 0x00100000 // Interrupt 52 enable
+#define NVIC_EN1_INT51 0x00080000 // Interrupt 51 enable
+#define NVIC_EN1_INT50 0x00040000 // Interrupt 50 enable
+#define NVIC_EN1_INT49 0x00020000 // Interrupt 49 enable
+#define NVIC_EN1_INT48 0x00010000 // Interrupt 48 enable
+#define NVIC_EN1_INT47 0x00008000 // Interrupt 47 enable
+#define NVIC_EN1_INT46 0x00004000 // Interrupt 46 enable
+#define NVIC_EN1_INT45 0x00002000 // Interrupt 45 enable
+#define NVIC_EN1_INT44 0x00001000 // Interrupt 44 enable
+#define NVIC_EN1_INT43 0x00000800 // Interrupt 43 enable
+#define NVIC_EN1_INT42 0x00000400 // Interrupt 42 enable
+#define NVIC_EN1_INT41 0x00000200 // Interrupt 41 enable
+#define NVIC_EN1_INT40 0x00000100 // Interrupt 40 enable
+#define NVIC_EN1_INT39 0x00000080 // Interrupt 39 enable
+#define NVIC_EN1_INT38 0x00000040 // Interrupt 38 enable
+#define NVIC_EN1_INT37 0x00000020 // Interrupt 37 enable
+#define NVIC_EN1_INT36 0x00000010 // Interrupt 36 enable
+#define NVIC_EN1_INT35 0x00000008 // Interrupt 35 enable
+#define NVIC_EN1_INT34 0x00000004 // Interrupt 34 enable
+#define NVIC_EN1_INT33 0x00000002 // Interrupt 33 enable
+#define NVIC_EN1_INT32 0x00000001 // Interrupt 32 enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS0 register.
+//
+//*****************************************************************************
+#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable
+#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable
+#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable
+#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable
+#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable
+#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable
+#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable
+#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable
+#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable
+#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable
+#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable
+#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable
+#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable
+#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable
+#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable
+#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable
+#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable
+#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable
+#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable
+#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable
+#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable
+#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable
+#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable
+#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable
+#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable
+#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable
+#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable
+#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable
+#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable
+#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable
+#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable
+#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS1 register.
+//
+//*****************************************************************************
+#define NVIC_DIS1_INT59 0x08000000 // Interrupt 59 disable
+#define NVIC_DIS1_INT58 0x04000000 // Interrupt 58 disable
+#define NVIC_DIS1_INT57 0x02000000 // Interrupt 57 disable
+#define NVIC_DIS1_INT56 0x01000000 // Interrupt 56 disable
+#define NVIC_DIS1_INT55 0x00800000 // Interrupt 55 disable
+#define NVIC_DIS1_INT54 0x00400000 // Interrupt 54 disable
+#define NVIC_DIS1_INT53 0x00200000 // Interrupt 53 disable
+#define NVIC_DIS1_INT52 0x00100000 // Interrupt 52 disable
+#define NVIC_DIS1_INT51 0x00080000 // Interrupt 51 disable
+#define NVIC_DIS1_INT50 0x00040000 // Interrupt 50 disable
+#define NVIC_DIS1_INT49 0x00020000 // Interrupt 49 disable
+#define NVIC_DIS1_INT48 0x00010000 // Interrupt 48 disable
+#define NVIC_DIS1_INT47 0x00008000 // Interrupt 47 disable
+#define NVIC_DIS1_INT46 0x00004000 // Interrupt 46 disable
+#define NVIC_DIS1_INT45 0x00002000 // Interrupt 45 disable
+#define NVIC_DIS1_INT44 0x00001000 // Interrupt 44 disable
+#define NVIC_DIS1_INT43 0x00000800 // Interrupt 43 disable
+#define NVIC_DIS1_INT42 0x00000400 // Interrupt 42 disable
+#define NVIC_DIS1_INT41 0x00000200 // Interrupt 41 disable
+#define NVIC_DIS1_INT40 0x00000100 // Interrupt 40 disable
+#define NVIC_DIS1_INT39 0x00000080 // Interrupt 39 disable
+#define NVIC_DIS1_INT38 0x00000040 // Interrupt 38 disable
+#define NVIC_DIS1_INT37 0x00000020 // Interrupt 37 disable
+#define NVIC_DIS1_INT36 0x00000010 // Interrupt 36 disable
+#define NVIC_DIS1_INT35 0x00000008 // Interrupt 35 disable
+#define NVIC_DIS1_INT34 0x00000004 // Interrupt 34 disable
+#define NVIC_DIS1_INT33 0x00000002 // Interrupt 33 disable
+#define NVIC_DIS1_INT32 0x00000001 // Interrupt 32 disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND0 register.
+//
+//*****************************************************************************
+#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend
+#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend
+#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend
+#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend
+#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend
+#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend
+#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend
+#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend
+#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend
+#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend
+#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend
+#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend
+#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend
+#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend
+#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend
+#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend
+#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend
+#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend
+#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend
+#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend
+#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend
+#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend
+#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend
+#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend
+#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend
+#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend
+#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend
+#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend
+#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend
+#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend
+#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend
+#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND1 register.
+//
+//*****************************************************************************
+#define NVIC_PEND1_INT59 0x08000000 // Interrupt 59 pend
+#define NVIC_PEND1_INT58 0x04000000 // Interrupt 58 pend
+#define NVIC_PEND1_INT57 0x02000000 // Interrupt 57 pend
+#define NVIC_PEND1_INT56 0x01000000 // Interrupt 56 pend
+#define NVIC_PEND1_INT55 0x00800000 // Interrupt 55 pend
+#define NVIC_PEND1_INT54 0x00400000 // Interrupt 54 pend
+#define NVIC_PEND1_INT53 0x00200000 // Interrupt 53 pend
+#define NVIC_PEND1_INT52 0x00100000 // Interrupt 52 pend
+#define NVIC_PEND1_INT51 0x00080000 // Interrupt 51 pend
+#define NVIC_PEND1_INT50 0x00040000 // Interrupt 50 pend
+#define NVIC_PEND1_INT49 0x00020000 // Interrupt 49 pend
+#define NVIC_PEND1_INT48 0x00010000 // Interrupt 48 pend
+#define NVIC_PEND1_INT47 0x00008000 // Interrupt 47 pend
+#define NVIC_PEND1_INT46 0x00004000 // Interrupt 46 pend
+#define NVIC_PEND1_INT45 0x00002000 // Interrupt 45 pend
+#define NVIC_PEND1_INT44 0x00001000 // Interrupt 44 pend
+#define NVIC_PEND1_INT43 0x00000800 // Interrupt 43 pend
+#define NVIC_PEND1_INT42 0x00000400 // Interrupt 42 pend
+#define NVIC_PEND1_INT41 0x00000200 // Interrupt 41 pend
+#define NVIC_PEND1_INT40 0x00000100 // Interrupt 40 pend
+#define NVIC_PEND1_INT39 0x00000080 // Interrupt 39 pend
+#define NVIC_PEND1_INT38 0x00000040 // Interrupt 38 pend
+#define NVIC_PEND1_INT37 0x00000020 // Interrupt 37 pend
+#define NVIC_PEND1_INT36 0x00000010 // Interrupt 36 pend
+#define NVIC_PEND1_INT35 0x00000008 // Interrupt 35 pend
+#define NVIC_PEND1_INT34 0x00000004 // Interrupt 34 pend
+#define NVIC_PEND1_INT33 0x00000002 // Interrupt 33 pend
+#define NVIC_PEND1_INT32 0x00000001 // Interrupt 32 pend
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND0 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend
+#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend
+#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend
+#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend
+#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend
+#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend
+#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend
+#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend
+#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend
+#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend
+#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend
+#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend
+#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend
+#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend
+#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend
+#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend
+#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend
+#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend
+#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend
+#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend
+#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend
+#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend
+#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend
+#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend
+#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend
+#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend
+#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend
+#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend
+#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend
+#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend
+#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend
+#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND1 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND1_INT59 0x08000000 // Interrupt 59 unpend
+#define NVIC_UNPEND1_INT58 0x04000000 // Interrupt 58 unpend
+#define NVIC_UNPEND1_INT57 0x02000000 // Interrupt 57 unpend
+#define NVIC_UNPEND1_INT56 0x01000000 // Interrupt 56 unpend
+#define NVIC_UNPEND1_INT55 0x00800000 // Interrupt 55 unpend
+#define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend
+#define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend
+#define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend
+#define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend
+#define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend
+#define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend
+#define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend
+#define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend
+#define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend
+#define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend
+#define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend
+#define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend
+#define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend
+#define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend
+#define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend
+#define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend
+#define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend
+#define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend
+#define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend
+#define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend
+#define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend
+#define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend
+#define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE0 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active
+#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active
+#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active
+#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active
+#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active
+#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active
+#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active
+#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active
+#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active
+#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active
+#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active
+#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active
+#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active
+#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active
+#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active
+#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active
+#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active
+#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active
+#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active
+#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active
+#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active
+#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active
+#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active
+#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active
+#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active
+#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active
+#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active
+#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active
+#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active
+#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active
+#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active
+#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE1 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE1_INT59 0x08000000 // Interrupt 59 active
+#define NVIC_ACTIVE1_INT58 0x04000000 // Interrupt 58 active
+#define NVIC_ACTIVE1_INT57 0x02000000 // Interrupt 57 active
+#define NVIC_ACTIVE1_INT56 0x01000000 // Interrupt 56 active
+#define NVIC_ACTIVE1_INT55 0x00800000 // Interrupt 55 active
+#define NVIC_ACTIVE1_INT54 0x00400000 // Interrupt 54 active
+#define NVIC_ACTIVE1_INT53 0x00200000 // Interrupt 53 active
+#define NVIC_ACTIVE1_INT52 0x00100000 // Interrupt 52 active
+#define NVIC_ACTIVE1_INT51 0x00080000 // Interrupt 51 active
+#define NVIC_ACTIVE1_INT50 0x00040000 // Interrupt 50 active
+#define NVIC_ACTIVE1_INT49 0x00020000 // Interrupt 49 active
+#define NVIC_ACTIVE1_INT48 0x00010000 // Interrupt 48 active
+#define NVIC_ACTIVE1_INT47 0x00008000 // Interrupt 47 active
+#define NVIC_ACTIVE1_INT46 0x00004000 // Interrupt 46 active
+#define NVIC_ACTIVE1_INT45 0x00002000 // Interrupt 45 active
+#define NVIC_ACTIVE1_INT44 0x00001000 // Interrupt 44 active
+#define NVIC_ACTIVE1_INT43 0x00000800 // Interrupt 43 active
+#define NVIC_ACTIVE1_INT42 0x00000400 // Interrupt 42 active
+#define NVIC_ACTIVE1_INT41 0x00000200 // Interrupt 41 active
+#define NVIC_ACTIVE1_INT40 0x00000100 // Interrupt 40 active
+#define NVIC_ACTIVE1_INT39 0x00000080 // Interrupt 39 active
+#define NVIC_ACTIVE1_INT38 0x00000040 // Interrupt 38 active
+#define NVIC_ACTIVE1_INT37 0x00000020 // Interrupt 37 active
+#define NVIC_ACTIVE1_INT36 0x00000010 // Interrupt 36 active
+#define NVIC_ACTIVE1_INT35 0x00000008 // Interrupt 35 active
+#define NVIC_ACTIVE1_INT34 0x00000004 // Interrupt 34 active
+#define NVIC_ACTIVE1_INT33 0x00000002 // Interrupt 33 active
+#define NVIC_ACTIVE1_INT32 0x00000001 // Interrupt 32 active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI0 register.
+//
+//*****************************************************************************
+#define NVIC_PRI0_INT3_M 0xFF000000 // Interrupt 3 priority mask
+#define NVIC_PRI0_INT2_M 0x00FF0000 // Interrupt 2 priority mask
+#define NVIC_PRI0_INT1_M 0x0000FF00 // Interrupt 1 priority mask
+#define NVIC_PRI0_INT0_M 0x000000FF // Interrupt 0 priority mask
+#define NVIC_PRI0_INT3_S 24
+#define NVIC_PRI0_INT2_S 16
+#define NVIC_PRI0_INT1_S 8
+#define NVIC_PRI0_INT0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI1 register.
+//
+//*****************************************************************************
+#define NVIC_PRI1_INT7_M 0xFF000000 // Interrupt 7 priority mask
+#define NVIC_PRI1_INT6_M 0x00FF0000 // Interrupt 6 priority mask
+#define NVIC_PRI1_INT5_M 0x0000FF00 // Interrupt 5 priority mask
+#define NVIC_PRI1_INT4_M 0x000000FF // Interrupt 4 priority mask
+#define NVIC_PRI1_INT7_S 24
+#define NVIC_PRI1_INT6_S 16
+#define NVIC_PRI1_INT5_S 8
+#define NVIC_PRI1_INT4_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI2 register.
+//
+//*****************************************************************************
+#define NVIC_PRI2_INT11_M 0xFF000000 // Interrupt 11 priority mask
+#define NVIC_PRI2_INT10_M 0x00FF0000 // Interrupt 10 priority mask
+#define NVIC_PRI2_INT9_M 0x0000FF00 // Interrupt 9 priority mask
+#define NVIC_PRI2_INT8_M 0x000000FF // Interrupt 8 priority mask
+#define NVIC_PRI2_INT11_S 24
+#define NVIC_PRI2_INT10_S 16
+#define NVIC_PRI2_INT9_S 8
+#define NVIC_PRI2_INT8_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI3 register.
+//
+//*****************************************************************************
+#define NVIC_PRI3_INT15_M 0xFF000000 // Interrupt 15 priority mask
+#define NVIC_PRI3_INT14_M 0x00FF0000 // Interrupt 14 priority mask
+#define NVIC_PRI3_INT13_M 0x0000FF00 // Interrupt 13 priority mask
+#define NVIC_PRI3_INT12_M 0x000000FF // Interrupt 12 priority mask
+#define NVIC_PRI3_INT15_S 24
+#define NVIC_PRI3_INT14_S 16
+#define NVIC_PRI3_INT13_S 8
+#define NVIC_PRI3_INT12_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI4 register.
+//
+//*****************************************************************************
+#define NVIC_PRI4_INT19_M 0xFF000000 // Interrupt 19 priority mask
+#define NVIC_PRI4_INT18_M 0x00FF0000 // Interrupt 18 priority mask
+#define NVIC_PRI4_INT17_M 0x0000FF00 // Interrupt 17 priority mask
+#define NVIC_PRI4_INT16_M 0x000000FF // Interrupt 16 priority mask
+#define NVIC_PRI4_INT19_S 24
+#define NVIC_PRI4_INT18_S 16
+#define NVIC_PRI4_INT17_S 8
+#define NVIC_PRI4_INT16_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI5 register.
+//
+//*****************************************************************************
+#define NVIC_PRI5_INT23_M 0xFF000000 // Interrupt 23 priority mask
+#define NVIC_PRI5_INT22_M 0x00FF0000 // Interrupt 22 priority mask
+#define NVIC_PRI5_INT21_M 0x0000FF00 // Interrupt 21 priority mask
+#define NVIC_PRI5_INT20_M 0x000000FF // Interrupt 20 priority mask
+#define NVIC_PRI5_INT23_S 24
+#define NVIC_PRI5_INT22_S 16
+#define NVIC_PRI5_INT21_S 8
+#define NVIC_PRI5_INT20_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI6 register.
+//
+//*****************************************************************************
+#define NVIC_PRI6_INT27_M 0xFF000000 // Interrupt 27 priority mask
+#define NVIC_PRI6_INT26_M 0x00FF0000 // Interrupt 26 priority mask
+#define NVIC_PRI6_INT25_M 0x0000FF00 // Interrupt 25 priority mask
+#define NVIC_PRI6_INT24_M 0x000000FF // Interrupt 24 priority mask
+#define NVIC_PRI6_INT27_S 24
+#define NVIC_PRI6_INT26_S 16
+#define NVIC_PRI6_INT25_S 8
+#define NVIC_PRI6_INT24_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI7 register.
+//
+//*****************************************************************************
+#define NVIC_PRI7_INT31_M 0xFF000000 // Interrupt 31 priority mask
+#define NVIC_PRI7_INT30_M 0x00FF0000 // Interrupt 30 priority mask
+#define NVIC_PRI7_INT29_M 0x0000FF00 // Interrupt 29 priority mask
+#define NVIC_PRI7_INT28_M 0x000000FF // Interrupt 28 priority mask
+#define NVIC_PRI7_INT31_S 24
+#define NVIC_PRI7_INT30_S 16
+#define NVIC_PRI7_INT29_S 8
+#define NVIC_PRI7_INT28_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI8 register.
+//
+//*****************************************************************************
+#define NVIC_PRI8_INT35_M 0xFF000000 // Interrupt 35 priority mask
+#define NVIC_PRI8_INT34_M 0x00FF0000 // Interrupt 34 priority mask
+#define NVIC_PRI8_INT33_M 0x0000FF00 // Interrupt 33 priority mask
+#define NVIC_PRI8_INT32_M 0x000000FF // Interrupt 32 priority mask
+#define NVIC_PRI8_INT35_S 24
+#define NVIC_PRI8_INT34_S 16
+#define NVIC_PRI8_INT33_S 8
+#define NVIC_PRI8_INT32_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI9 register.
+//
+//*****************************************************************************
+#define NVIC_PRI9_INT39_M 0xFF000000 // Interrupt 39 priority mask
+#define NVIC_PRI9_INT38_M 0x00FF0000 // Interrupt 38 priority mask
+#define NVIC_PRI9_INT37_M 0x0000FF00 // Interrupt 37 priority mask
+#define NVIC_PRI9_INT36_M 0x000000FF // Interrupt 36 priority mask
+#define NVIC_PRI9_INT39_S 24
+#define NVIC_PRI9_INT38_S 16
+#define NVIC_PRI9_INT37_S 8
+#define NVIC_PRI9_INT36_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI10 register.
+//
+//*****************************************************************************
+#define NVIC_PRI10_INT43_M 0xFF000000 // Interrupt 43 priority mask
+#define NVIC_PRI10_INT42_M 0x00FF0000 // Interrupt 42 priority mask
+#define NVIC_PRI10_INT41_M 0x0000FF00 // Interrupt 41 priority mask
+#define NVIC_PRI10_INT40_M 0x000000FF // Interrupt 40 priority mask
+#define NVIC_PRI10_INT43_S 24
+#define NVIC_PRI10_INT42_S 16
+#define NVIC_PRI10_INT41_S 8
+#define NVIC_PRI10_INT40_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_CPUID register.
+//
+//*****************************************************************************
+#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer
+#define NVIC_CPUID_VAR_M 0x00F00000 // Variant
+#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Processor part number
+#define NVIC_CPUID_REV_M 0x0000000F // Revision
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_INT_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_INT_CTRL_NMI_SET 0x80000000 // Pend a NMI
+#define NVIC_INT_CTRL_PEND_SV 0x10000000 // Pend a PendSV
+#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // Unpend a PendSV
+#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug interrupt handling
+#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Debug interrupt pending
+#define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000 // Highest pending exception
+#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to base
+#define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF // Current active exception
+#define NVIC_INT_CTRL_VEC_PEN_S 12
+#define NVIC_INT_CTRL_VEC_ACT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_VTABLE register.
+//
+//*****************************************************************************
+#define NVIC_VTABLE_BASE 0x20000000 // Vector table base
+#define NVIC_VTABLE_OFFSET_M 0x1FFFFF00 // Vector table offset
+#define NVIC_VTABLE_OFFSET_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_APINT register.
+//
+//*****************************************************************************
+#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Vector key mask
+#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key
+#define NVIC_APINT_ENDIANESS 0x00008000 // Data endianess
+#define NVIC_APINT_PRIGROUP_M 0x00000700 // Priority group
+#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split
+#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split
+#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split
+#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split
+#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split
+#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split
+#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split
+#define NVIC_APINT_SYSRESETREQ 0x00000004 // System reset request
+#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear active NMI/fault info
+#define NVIC_APINT_VECT_RESET 0x00000001 // System reset
+#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wakeup on pend
+#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep sleep enable
+#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR exit
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_CFG_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore bus fault in NMI/fault
+#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on divide by 0
+#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on unaligned access
+#define NVIC_CFG_CTRL_DEEP_PEND 0x00000004 // Allow deep interrupt trigger
+#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow main interrupt trigger
+#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread state control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_PRI1 register.
+//
+//*****************************************************************************
+#define NVIC_SYS_PRI1_RES_M 0xFF000000 // Priority of reserved handler
+#define NVIC_SYS_PRI1_USAGE_M 0x00FF0000 // Priority of usage fault handler
+#define NVIC_SYS_PRI1_BUS_M 0x0000FF00 // Priority of bus fault handler
+#define NVIC_SYS_PRI1_MEM_M 0x000000FF // Priority of mem manage handler
+#define NVIC_SYS_PRI1_USAGE_S 16
+#define NVIC_SYS_PRI1_BUS_S 8
+#define NVIC_SYS_PRI1_MEM_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_PRI2 register.
+//
+//*****************************************************************************
+#define NVIC_SYS_PRI2_SVC_M 0xFF000000 // Priority of SVCall handler
+#define NVIC_SYS_PRI2_RES_M 0x00FFFFFF // Priority of reserved handlers
+#define NVIC_SYS_PRI2_SVC_S 24
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_PRI3 register.
+//
+//*****************************************************************************
+#define NVIC_SYS_PRI3_TICK_M 0xFF000000 // Priority of Sys Tick handler
+#define NVIC_SYS_PRI3_PENDSV_M 0x00FF0000 // Priority of PendSV handler
+#define NVIC_SYS_PRI3_RES_M 0x0000FF00 // Priority of reserved handler
+#define NVIC_SYS_PRI3_DEBUG_M 0x000000FF // Priority of debug handler
+#define NVIC_SYS_PRI3_TICK_S 24
+#define NVIC_SYS_PRI3_PENDSV_S 16
+#define NVIC_SYS_PRI3_DEBUG_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_HND_CTRL
+// register.
+//
+//*****************************************************************************
+#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage fault enable
+#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus fault enable
+#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Mem manage fault enable
+#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVCall is pended
+#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus fault is pended
+#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // Sys tick is active
+#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV is active
+#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Monitor is active
+#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVCall is active
+#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage fault is active
+#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus fault is active
+#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Mem manage is active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FAULT_STAT
+// register.
+//
+//*****************************************************************************
+#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide by zero fault
+#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned access fault
+#define NVIC_FAULT_STAT_NOCP 0x00080000 // No coprocessor fault
+#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC fault
+#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid state fault
+#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined instruction fault
+#define NVIC_FAULT_STAT_BFARV 0x00008000 // BFAR is valid
+#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack bus fault
+#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack bus fault
+#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise data bus error
+#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise data bus error
+#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction bus fault
+#define NVIC_FAULT_STAT_MMARV 0x00000080 // MMAR is valid
+#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack access violation
+#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack access violation
+#define NVIC_FAULT_STAT_DERR 0x00000002 // Data access violation
+#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction access violation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_HFAULT_STAT
+// register.
+//
+//*****************************************************************************
+#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug event
+#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Cannot execute fault handler
+#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector table read fault
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DEBUG_STAT
+// register.
+//
+//*****************************************************************************
+#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted
+#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch
+#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match
+#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction
+#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MM_ADDR register.
+//
+//*****************************************************************************
+#define NVIC_MM_ADDR_M 0xFFFFFFFF // Data fault address
+#define NVIC_MM_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FAULT_ADDR
+// register.
+//
+//*****************************************************************************
+#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Data bus fault address
+#define NVIC_FAULT_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_TYPE register.
+//
+//*****************************************************************************
+#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I regions
+#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D regions
+#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or unified MPU
+#define NVIC_MPU_TYPE_IREGION_S 16
+#define NVIC_MPU_TYPE_DREGION_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004 // MPU default region in priv mode
+#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU enabled during faults
+#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_NUMBER
+// register.
+//
+//*****************************************************************************
+#define NVIC_MPU_NUMBER_M 0x000000FF // MPU region to access
+#define NVIC_MPU_NUMBER_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE_ADDR_M 0xFFFFFFE0 // Base address mask
+#define NVIC_MPU_BASE_VALID 0x00000010 // Region number valid
+#define NVIC_MPU_BASE_REGION_M 0x0000000F // Region number
+#define NVIC_MPU_BASE_ADDR_S 8
+#define NVIC_MPU_BASE_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR_M 0xFFFF0000 // Attributes
+#define NVIC_MPU_ATTR_AP_NO_NO 0x00000000 // prv: no access, usr: no access
+#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000 // Bufferable
+#define NVIC_MPU_ATTR_CACHEABLE 0x00020000 // Cacheable
+#define NVIC_MPU_ATTR_SHAREABLE 0x00040000 // Shareable
+#define NVIC_MPU_ATTR_TEX_M 0x00380000 // Type extension mask
+#define NVIC_MPU_ATTR_AP_RW_NO 0x01000000 // prv: rw, usr: none
+#define NVIC_MPU_ATTR_AP_RW_RO 0x02000000 // prv: rw, usr: read-only
+#define NVIC_MPU_ATTR_AP_RW_RW 0x03000000 // prv: rw, usr: rw
+#define NVIC_MPU_ATTR_AP_RO_NO 0x05000000 // prv: ro, usr: none
+#define NVIC_MPU_ATTR_AP_RO_RO 0x06000000 // prv: ro, usr: ro
+#define NVIC_MPU_ATTR_AP_M 0x07000000 // Access permissions mask
+#define NVIC_MPU_ATTR_XN 0x10000000 // Execute disable
+#define NVIC_MPU_ATTR_SRD_M 0x0000FF00 // Sub-region disable mask
+#define NVIC_MPU_ATTR_SRD_0 0x00000100 // Sub-region 0 disable
+#define NVIC_MPU_ATTR_SRD_1 0x00000200 // Sub-region 1 disable
+#define NVIC_MPU_ATTR_SRD_2 0x00000400 // Sub-region 2 disable
+#define NVIC_MPU_ATTR_SRD_3 0x00000800 // Sub-region 3 disable
+#define NVIC_MPU_ATTR_SRD_4 0x00001000 // Sub-region 4 disable
+#define NVIC_MPU_ATTR_SRD_5 0x00002000 // Sub-region 5 disable
+#define NVIC_MPU_ATTR_SRD_6 0x00004000 // Sub-region 6 disable
+#define NVIC_MPU_ATTR_SRD_7 0x00008000 // Sub-region 7 disable
+#define NVIC_MPU_ATTR_SIZE_M 0x0000003E // Region size mask
+#define NVIC_MPU_ATTR_SIZE_32B 0x00000008 // Region size 32 bytes
+#define NVIC_MPU_ATTR_SIZE_64B 0x0000000A // Region size 64 bytes
+#define NVIC_MPU_ATTR_SIZE_128B 0x0000000C // Region size 128 bytes
+#define NVIC_MPU_ATTR_SIZE_256B 0x0000000E // Region size 256 bytes
+#define NVIC_MPU_ATTR_SIZE_512B 0x00000010 // Region size 512 bytes
+#define NVIC_MPU_ATTR_SIZE_1K 0x00000012 // Region size 1 Kbytes
+#define NVIC_MPU_ATTR_SIZE_2K 0x00000014 // Region size 2 Kbytes
+#define NVIC_MPU_ATTR_SIZE_4K 0x00000016 // Region size 4 Kbytes
+#define NVIC_MPU_ATTR_SIZE_8K 0x00000018 // Region size 8 Kbytes
+#define NVIC_MPU_ATTR_SIZE_16K 0x0000001A // Region size 16 Kbytes
+#define NVIC_MPU_ATTR_SIZE_32K 0x0000001C // Region size 32 Kbytes
+#define NVIC_MPU_ATTR_SIZE_64K 0x0000001E // Region size 64 Kbytes
+#define NVIC_MPU_ATTR_SIZE_128K 0x00000020 // Region size 128 Kbytes
+#define NVIC_MPU_ATTR_SIZE_256K 0x00000022 // Region size 256 Kbytes
+#define NVIC_MPU_ATTR_SIZE_512K 0x00000024 // Region size 512 Kbytes
+#define NVIC_MPU_ATTR_SIZE_1M 0x00000026 // Region size 1 Mbytes
+#define NVIC_MPU_ATTR_SIZE_2M 0x00000028 // Region size 2 Mbytes
+#define NVIC_MPU_ATTR_SIZE_4M 0x0000002A // Region size 4 Mbytes
+#define NVIC_MPU_ATTR_SIZE_8M 0x0000002C // Region size 8 Mbytes
+#define NVIC_MPU_ATTR_SIZE_16M 0x0000002E // Region size 16 Mbytes
+#define NVIC_MPU_ATTR_SIZE_32M 0x00000030 // Region size 32 Mbytes
+#define NVIC_MPU_ATTR_SIZE_64M 0x00000032 // Region size 64 Mbytes
+#define NVIC_MPU_ATTR_SIZE_128M 0x00000034 // Region size 128 Mbytes
+#define NVIC_MPU_ATTR_SIZE_256M 0x00000036 // Region size 256 Mbytes
+#define NVIC_MPU_ATTR_SIZE_512M 0x00000038 // Region size 512 Mbytes
+#define NVIC_MPU_ATTR_SIZE_1G 0x0000003A // Region size 1 Gbytes
+#define NVIC_MPU_ATTR_SIZE_2G 0x0000003C // Region size 2 Gbytes
+#define NVIC_MPU_ATTR_SIZE_4G 0x0000003E // Region size 4 Gbytes
+#define NVIC_MPU_ATTR_ENABLE 0x00000001 // Region enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask
+#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key
+#define NVIC_DBG_CTRL_S_RESET_ST \
+ 0x02000000 // Core has reset since last read
+#define NVIC_DBG_CTRL_S_RETIRE_ST \
+ 0x01000000 // Core has executed insruction
+ // since last read
+#define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 // Core is locked up
+#define NVIC_DBG_CTRL_S_SLEEP 0x00040000 // Core is sleeping
+#define NVIC_DBG_CTRL_S_HALT 0x00020000 // Core status on halt
+#define NVIC_DBG_CTRL_S_REGRDY 0x00010000 // Register read/write available
+#define NVIC_DBG_CTRL_C_SNAPSTALL \
+ 0x00000020 // Breaks a stalled load/store
+#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping
+#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core
+#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core
+#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_XFER register.
+//
+//*****************************************************************************
+#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read
+#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register
+#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask
+#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP
+#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP
+#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP
+#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register
+#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15
+#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14
+#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13
+#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12
+#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11
+#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10
+#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9
+#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8
+#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7
+#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6
+#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5
+#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4
+#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3
+#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2
+#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1
+#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_DATA register.
+//
+//*****************************************************************************
+#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache
+#define NVIC_DBG_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_INT register.
+//
+//*****************************************************************************
+#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault
+#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors
+#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error
+#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state
+#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check
+#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error
+#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault
+#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status
+#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset
+#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending
+#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SW_TRIG register.
+//
+//*****************************************************************************
+#define NVIC_SW_TRIG_INTID_M 0x000003FF // Interrupt to trigger
+#define NVIC_SW_TRIG_INTID_S 0
+
+#endif // __LM3S8962_H__
Property changes on: branches/eagle_mmc/src/platform/lm3s/lm3s8962.h
___________________________________________________________________
Name: svn:executable
+ *
Added: branches/eagle_mmc/src/platform/lm3s/lm3s9b92.h
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/lm3s9b92.h 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lm3s/lm3s9b92.h 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,11836 @@
+//*****************************************************************************
+//
+// lm3s9b92.h - LM3S9B92 Register Definitions
+//
+// Copyright (c) 2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4781 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __LM3S9B92_H__
+#define __LM3S9B92_H__
+
+//*****************************************************************************
+//
+// Watchdog Timers (WATCHDOG0)
+//
+//*****************************************************************************
+#define WATCHDOG0_LOAD_R (*((volatile unsigned long *)0x40000000))
+#define WATCHDOG0_VALUE_R (*((volatile unsigned long *)0x40000004))
+#define WATCHDOG0_CTL_R (*((volatile unsigned long *)0x40000008))
+#define WATCHDOG0_ICR_R (*((volatile unsigned long *)0x4000000C))
+#define WATCHDOG0_RIS_R (*((volatile unsigned long *)0x40000010))
+#define WATCHDOG0_MIS_R (*((volatile unsigned long *)0x40000014))
+#define WATCHDOG0_TEST_R (*((volatile unsigned long *)0x40000418))
+#define WATCHDOG0_LOCK_R (*((volatile unsigned long *)0x40000C00))
+
+//*****************************************************************************
+//
+// Watchdog Timers (WATCHDOG1)
+//
+//*****************************************************************************
+#define WATCHDOG1_LOAD_R (*((volatile unsigned long *)0x40001000))
+#define WATCHDOG1_VALUE_R (*((volatile unsigned long *)0x40001004))
+#define WATCHDOG1_CTL_R (*((volatile unsigned long *)0x40001008))
+#define WATCHDOG1_ICR_R (*((volatile unsigned long *)0x4000100C))
+#define WATCHDOG1_RIS_R (*((volatile unsigned long *)0x40001010))
+#define WATCHDOG1_MIS_R (*((volatile unsigned long *)0x40001014))
+#define WATCHDOG1_TEST_R (*((volatile unsigned long *)0x40001418))
+#define WATCHDOG1_LOCK_R (*((volatile unsigned long *)0x40001C00))
+
+//*****************************************************************************
+//
+// General-Purpose Input/Outputs (PORTA)
+//
+//*****************************************************************************
+#define GPIO_PORTA_DATA_BITS_R ((volatile unsigned long *)0x40004000)
+#define GPIO_PORTA_DATA_R (*((volatile unsigned long *)0x400043FC))
+#define GPIO_PORTA_DIR_R (*((volatile unsigned long *)0x40004400))
+#define GPIO_PORTA_IS_R (*((volatile unsigned long *)0x40004404))
+#define GPIO_PORTA_IBE_R (*((volatile unsigned long *)0x40004408))
+#define GPIO_PORTA_IEV_R (*((volatile unsigned long *)0x4000440C))
+#define GPIO_PORTA_IM_R (*((volatile unsigned long *)0x40004410))
+#define GPIO_PORTA_RIS_R (*((volatile unsigned long *)0x40004414))
+#define GPIO_PORTA_MIS_R (*((volatile unsigned long *)0x40004418))
+#define GPIO_PORTA_ICR_R (*((volatile unsigned long *)0x4000441C))
+#define GPIO_PORTA_AFSEL_R (*((volatile unsigned long *)0x40004420))
+#define GPIO_PORTA_DR2R_R (*((volatile unsigned long *)0x40004500))
+#define GPIO_PORTA_DR4R_R (*((volatile unsigned long *)0x40004504))
+#define GPIO_PORTA_DR8R_R (*((volatile unsigned long *)0x40004508))
+#define GPIO_PORTA_ODR_R (*((volatile unsigned long *)0x4000450C))
+#define GPIO_PORTA_PUR_R (*((volatile unsigned long *)0x40004510))
+#define GPIO_PORTA_PDR_R (*((volatile unsigned long *)0x40004514))
+#define GPIO_PORTA_SLR_R (*((volatile unsigned long *)0x40004518))
+#define GPIO_PORTA_DEN_R (*((volatile unsigned long *)0x4000451C))
+#define GPIO_PORTA_LOCK_R (*((volatile unsigned long *)0x40004520))
+#define GPIO_PORTA_CR_R (*((volatile unsigned long *)0x40004524))
+#define GPIO_PORTA_AMSEL_R (*((volatile unsigned long *)0x40004528))
+#define GPIO_PORTA_PCTL_R (*((volatile unsigned long *)0x4000452C))
+
+//*****************************************************************************
+//
+// General-Purpose Input/Outputs (PORTB)
+//
+//*****************************************************************************
+#define GPIO_PORTB_DATA_BITS_R ((volatile unsigned long *)0x40005000)
+#define GPIO_PORTB_DATA_R (*((volatile unsigned long *)0x400053FC))
+#define GPIO_PORTB_DIR_R (*((volatile unsigned long *)0x40005400))
+#define GPIO_PORTB_IS_R (*((volatile unsigned long *)0x40005404))
+#define GPIO_PORTB_IBE_R (*((volatile unsigned long *)0x40005408))
+#define GPIO_PORTB_IEV_R (*((volatile unsigned long *)0x4000540C))
+#define GPIO_PORTB_IM_R (*((volatile unsigned long *)0x40005410))
+#define GPIO_PORTB_RIS_R (*((volatile unsigned long *)0x40005414))
+#define GPIO_PORTB_MIS_R (*((volatile unsigned long *)0x40005418))
+#define GPIO_PORTB_ICR_R (*((volatile unsigned long *)0x4000541C))
+#define GPIO_PORTB_AFSEL_R (*((volatile unsigned long *)0x40005420))
+#define GPIO_PORTB_DR2R_R (*((volatile unsigned long *)0x40005500))
+#define GPIO_PORTB_DR4R_R (*((volatile unsigned long *)0x40005504))
+#define GPIO_PORTB_DR8R_R (*((volatile unsigned long *)0x40005508))
+#define GPIO_PORTB_ODR_R (*((volatile unsigned long *)0x4000550C))
+#define GPIO_PORTB_PUR_R (*((volatile unsigned long *)0x40005510))
+#define GPIO_PORTB_PDR_R (*((volatile unsigned long *)0x40005514))
+#define GPIO_PORTB_SLR_R (*((volatile unsigned long *)0x40005518))
+#define GPIO_PORTB_DEN_R (*((volatile unsigned long *)0x4000551C))
+#define GPIO_PORTB_LOCK_R (*((volatile unsigned long *)0x40005520))
+#define GPIO_PORTB_CR_R (*((volatile unsigned long *)0x40005524))
+#define GPIO_PORTB_AMSEL_R (*((volatile unsigned long *)0x40005528))
+#define GPIO_PORTB_PCTL_R (*((volatile unsigned long *)0x4000552C))
+
+//*****************************************************************************
+//
+// General-Purpose Input/Outputs (PORTC)
+//
+//*****************************************************************************
+#define GPIO_PORTC_DATA_BITS_R ((volatile unsigned long *)0x40006000)
+#define GPIO_PORTC_DATA_R (*((volatile unsigned long *)0x400063FC))
+#define GPIO_PORTC_DIR_R (*((volatile unsigned long *)0x40006400))
+#define GPIO_PORTC_IS_R (*((volatile unsigned long *)0x40006404))
+#define GPIO_PORTC_IBE_R (*((volatile unsigned long *)0x40006408))
+#define GPIO_PORTC_IEV_R (*((volatile unsigned long *)0x4000640C))
+#define GPIO_PORTC_IM_R (*((volatile unsigned long *)0x40006410))
+#define GPIO_PORTC_RIS_R (*((volatile unsigned long *)0x40006414))
+#define GPIO_PORTC_MIS_R (*((volatile unsigned long *)0x40006418))
+#define GPIO_PORTC_ICR_R (*((volatile unsigned long *)0x4000641C))
+#define GPIO_PORTC_AFSEL_R (*((volatile unsigned long *)0x40006420))
+#define GPIO_PORTC_DR2R_R (*((volatile unsigned long *)0x40006500))
+#define GPIO_PORTC_DR4R_R (*((volatile unsigned long *)0x40006504))
+#define GPIO_PORTC_DR8R_R (*((volatile unsigned long *)0x40006508))
+#define GPIO_PORTC_ODR_R (*((volatile unsigned long *)0x4000650C))
+#define GPIO_PORTC_PUR_R (*((volatile unsigned long *)0x40006510))
+#define GPIO_PORTC_PDR_R (*((volatile unsigned long *)0x40006514))
+#define GPIO_PORTC_SLR_R (*((volatile unsigned long *)0x40006518))
+#define GPIO_PORTC_DEN_R (*((volatile unsigned long *)0x4000651C))
+#define GPIO_PORTC_LOCK_R (*((volatile unsigned long *)0x40006520))
+#define GPIO_PORTC_CR_R (*((volatile unsigned long *)0x40006524))
+#define GPIO_PORTC_AMSEL_R (*((volatile unsigned long *)0x40006528))
+#define GPIO_PORTC_PCTL_R (*((volatile unsigned long *)0x4000652C))
+
+//*****************************************************************************
+//
+// General-Purpose Input/Outputs (PORTD)
+//
+//*****************************************************************************
+#define GPIO_PORTD_DATA_BITS_R ((volatile unsigned long *)0x40007000)
+#define GPIO_PORTD_DATA_R (*((volatile unsigned long *)0x400073FC))
+#define GPIO_PORTD_DIR_R (*((volatile unsigned long *)0x40007400))
+#define GPIO_PORTD_IS_R (*((volatile unsigned long *)0x40007404))
+#define GPIO_PORTD_IBE_R (*((volatile unsigned long *)0x40007408))
+#define GPIO_PORTD_IEV_R (*((volatile unsigned long *)0x4000740C))
+#define GPIO_PORTD_IM_R (*((volatile unsigned long *)0x40007410))
+#define GPIO_PORTD_RIS_R (*((volatile unsigned long *)0x40007414))
+#define GPIO_PORTD_MIS_R (*((volatile unsigned long *)0x40007418))
+#define GPIO_PORTD_ICR_R (*((volatile unsigned long *)0x4000741C))
+#define GPIO_PORTD_AFSEL_R (*((volatile unsigned long *)0x40007420))
+#define GPIO_PORTD_DR2R_R (*((volatile unsigned long *)0x40007500))
+#define GPIO_PORTD_DR4R_R (*((volatile unsigned long *)0x40007504))
+#define GPIO_PORTD_DR8R_R (*((volatile unsigned long *)0x40007508))
+#define GPIO_PORTD_ODR_R (*((volatile unsigned long *)0x4000750C))
+#define GPIO_PORTD_PUR_R (*((volatile unsigned long *)0x40007510))
+#define GPIO_PORTD_PDR_R (*((volatile unsigned long *)0x40007514))
+#define GPIO_PORTD_SLR_R (*((volatile unsigned long *)0x40007518))
+#define GPIO_PORTD_DEN_R (*((volatile unsigned long *)0x4000751C))
+#define GPIO_PORTD_LOCK_R (*((volatile unsigned long *)0x40007520))
+#define GPIO_PORTD_CR_R (*((volatile unsigned long *)0x40007524))
+#define GPIO_PORTD_AMSEL_R (*((volatile unsigned long *)0x40007528))
+#define GPIO_PORTD_PCTL_R (*((volatile unsigned long *)0x4000752C))
+
+//*****************************************************************************
+//
+// Synchronous Serial Interface (SSI0)
+//
+//*****************************************************************************
+#define SSI0_CR0_R (*((volatile unsigned long *)0x40008000))
+#define SSI0_CR1_R (*((volatile unsigned long *)0x40008004))
+#define SSI0_DR_R (*((volatile unsigned long *)0x40008008))
+#define SSI0_SR_R (*((volatile unsigned long *)0x4000800C))
+#define SSI0_CPSR_R (*((volatile unsigned long *)0x40008010))
+#define SSI0_IM_R (*((volatile unsigned long *)0x40008014))
+#define SSI0_RIS_R (*((volatile unsigned long *)0x40008018))
+#define SSI0_MIS_R (*((volatile unsigned long *)0x4000801C))
+#define SSI0_ICR_R (*((volatile unsigned long *)0x40008020))
+#define SSI0_DMACTL_R (*((volatile unsigned long *)0x40008024))
+
+//*****************************************************************************
+//
+// Synchronous Serial Interface (SSI1)
+//
+//*****************************************************************************
+#define SSI1_CR0_R (*((volatile unsigned long *)0x40009000))
+#define SSI1_CR1_R (*((volatile unsigned long *)0x40009004))
+#define SSI1_DR_R (*((volatile unsigned long *)0x40009008))
+#define SSI1_SR_R (*((volatile unsigned long *)0x4000900C))
+#define SSI1_CPSR_R (*((volatile unsigned long *)0x40009010))
+#define SSI1_IM_R (*((volatile unsigned long *)0x40009014))
+#define SSI1_RIS_R (*((volatile unsigned long *)0x40009018))
+#define SSI1_MIS_R (*((volatile unsigned long *)0x4000901C))
+#define SSI1_ICR_R (*((volatile unsigned long *)0x40009020))
+#define SSI1_DMACTL_R (*((volatile unsigned long *)0x40009024))
+
+//*****************************************************************************
+//
+// Universal Asynchronous Receivers/Transmitters (UART0)
+//
+//*****************************************************************************
+#define UART0_DR_R (*((volatile unsigned long *)0x4000C000))
+#define UART0_RSR_R (*((volatile unsigned long *)0x4000C004))
+#define UART0_ECR_R (*((volatile unsigned long *)0x4000C004))
+#define UART0_FR_R (*((volatile unsigned long *)0x4000C018))
+#define UART0_ILPR_R (*((volatile unsigned long *)0x4000C020))
+#define UART0_IBRD_R (*((volatile unsigned long *)0x4000C024))
+#define UART0_FBRD_R (*((volatile unsigned long *)0x4000C028))
+#define UART0_LCRH_R (*((volatile unsigned long *)0x4000C02C))
+#define UART0_CTL_R (*((volatile unsigned long *)0x4000C030))
+#define UART0_IFLS_R (*((volatile unsigned long *)0x4000C034))
+#define UART0_IM_R (*((volatile unsigned long *)0x4000C038))
+#define UART0_RIS_R (*((volatile unsigned long *)0x4000C03C))
+#define UART0_MIS_R (*((volatile unsigned long *)0x4000C040))
+#define UART0_ICR_R (*((volatile unsigned long *)0x4000C044))
+#define UART0_DMACTL_R (*((volatile unsigned long *)0x4000C048))
+#define UART0_LCTL_R (*((volatile unsigned long *)0x4000C090))
+#define UART0_LSS_R (*((volatile unsigned long *)0x4000C094))
+#define UART0_LTIM_R (*((volatile unsigned long *)0x4000C098))
+
+//*****************************************************************************
+//
+// Universal Asynchronous Receivers/Transmitters (UART1)
+//
+//*****************************************************************************
+#define UART1_DR_R (*((volatile unsigned long *)0x4000D000))
+#define UART1_RSR_R (*((volatile unsigned long *)0x4000D004))
+#define UART1_ECR_R (*((volatile unsigned long *)0x4000D004))
+#define UART1_FR_R (*((volatile unsigned long *)0x4000D018))
+#define UART1_ILPR_R (*((volatile unsigned long *)0x4000D020))
+#define UART1_IBRD_R (*((volatile unsigned long *)0x4000D024))
+#define UART1_FBRD_R (*((volatile unsigned long *)0x4000D028))
+#define UART1_LCRH_R (*((volatile unsigned long *)0x4000D02C))
+#define UART1_CTL_R (*((volatile unsigned long *)0x4000D030))
+#define UART1_IFLS_R (*((volatile unsigned long *)0x4000D034))
+#define UART1_IM_R (*((volatile unsigned long *)0x4000D038))
+#define UART1_RIS_R (*((volatile unsigned long *)0x4000D03C))
+#define UART1_MIS_R (*((volatile unsigned long *)0x4000D040))
+#define UART1_ICR_R (*((volatile unsigned long *)0x4000D044))
+#define UART1_DMACTL_R (*((volatile unsigned long *)0x4000D048))
+#define UART1_LCTL_R (*((volatile unsigned long *)0x4000D090))
+#define UART1_LSS_R (*((volatile unsigned long *)0x4000D094))
+#define UART1_LTIM_R (*((volatile unsigned long *)0x4000D098))
+
+//*****************************************************************************
+//
+// Universal Asynchronous Receivers/Transmitters (UART2)
+//
+//*****************************************************************************
+#define UART2_DR_R (*((volatile unsigned long *)0x4000E000))
+#define UART2_RSR_R (*((volatile unsigned long *)0x4000E004))
+#define UART2_ECR_R (*((volatile unsigned long *)0x4000E004))
+#define UART2_FR_R (*((volatile unsigned long *)0x4000E018))
+#define UART2_ILPR_R (*((volatile unsigned long *)0x4000E020))
+#define UART2_IBRD_R (*((volatile unsigned long *)0x4000E024))
+#define UART2_FBRD_R (*((volatile unsigned long *)0x4000E028))
+#define UART2_LCRH_R (*((volatile unsigned long *)0x4000E02C))
+#define UART2_CTL_R (*((volatile unsigned long *)0x4000E030))
+#define UART2_IFLS_R (*((volatile unsigned long *)0x4000E034))
+#define UART2_IM_R (*((volatile unsigned long *)0x4000E038))
+#define UART2_RIS_R (*((volatile unsigned long *)0x4000E03C))
+#define UART2_MIS_R (*((volatile unsigned long *)0x4000E040))
+#define UART2_ICR_R (*((volatile unsigned long *)0x4000E044))
+#define UART2_DMACTL_R (*((volatile unsigned long *)0x4000E048))
+#define UART2_LCTL_R (*((volatile unsigned long *)0x4000E090))
+#define UART2_LSS_R (*((volatile unsigned long *)0x4000E094))
+#define UART2_LTIM_R (*((volatile unsigned long *)0x4000E098))
+
+//*****************************************************************************
+//
+// Inter-Integrated Circuit (MASTER) Interface
+//
+//*****************************************************************************
+#define I2C0_MASTER_MSA_R (*((volatile unsigned long *)0x40020000))
+#define I2C0_MASTER_SOAR_R (*((volatile unsigned long *)0x40020000))
+#define I2C0_MASTER_SCSR_R (*((volatile unsigned long *)0x40020004))
+#define I2C0_MASTER_MCS_R (*((volatile unsigned long *)0x40020004))
+#define I2C0_MASTER_SDR_R (*((volatile unsigned long *)0x40020008))
+#define I2C0_MASTER_MDR_R (*((volatile unsigned long *)0x40020008))
+#define I2C0_MASTER_MTPR_R (*((volatile unsigned long *)0x4002000C))
+#define I2C0_MASTER_SIMR_R (*((volatile unsigned long *)0x4002000C))
+#define I2C0_MASTER_SRIS_R (*((volatile unsigned long *)0x40020010))
+#define I2C0_MASTER_MIMR_R (*((volatile unsigned long *)0x40020010))
+#define I2C0_MASTER_MRIS_R (*((volatile unsigned long *)0x40020014))
+#define I2C0_MASTER_SMIS_R (*((volatile unsigned long *)0x40020014))
+#define I2C0_MASTER_SICR_R (*((volatile unsigned long *)0x40020018))
+#define I2C0_MASTER_MMIS_R (*((volatile unsigned long *)0x40020018))
+#define I2C0_MASTER_MICR_R (*((volatile unsigned long *)0x4002001C))
+#define I2C0_MASTER_MCR_R (*((volatile unsigned long *)0x40020020))
+
+//*****************************************************************************
+//
+// Inter-Integrated Circuit (SLAVE) Interface
+//
+//*****************************************************************************
+#define I2C0_SLAVE_MSA_R (*((volatile unsigned long *)0x40020800))
+#define I2C0_SLAVE_SOAR_R (*((volatile unsigned long *)0x40020800))
+#define I2C0_SLAVE_SCSR_R (*((volatile unsigned long *)0x40020804))
+#define I2C0_SLAVE_MCS_R (*((volatile unsigned long *)0x40020804))
+#define I2C0_SLAVE_SDR_R (*((volatile unsigned long *)0x40020808))
+#define I2C0_SLAVE_MDR_R (*((volatile unsigned long *)0x40020808))
+#define I2C0_SLAVE_MTPR_R (*((volatile unsigned long *)0x4002080C))
+#define I2C0_SLAVE_SIMR_R (*((volatile unsigned long *)0x4002080C))
+#define I2C0_SLAVE_SRIS_R (*((volatile unsigned long *)0x40020810))
+#define I2C0_SLAVE_MIMR_R (*((volatile unsigned long *)0x40020810))
+#define I2C0_SLAVE_MRIS_R (*((volatile unsigned long *)0x40020814))
+#define I2C0_SLAVE_SMIS_R (*((volatile unsigned long *)0x40020814))
+#define I2C0_SLAVE_SICR_R (*((volatile unsigned long *)0x40020818))
+#define I2C0_SLAVE_MMIS_R (*((volatile unsigned long *)0x40020818))
+#define I2C0_SLAVE_MICR_R (*((volatile unsigned long *)0x4002081C))
+#define I2C0_SLAVE_MCR_R (*((volatile unsigned long *)0x40020820))
+
+//*****************************************************************************
+//
+// Inter-Integrated Circuit (MASTER) Interface
+//
+//*****************************************************************************
+#define I2C1_MASTER_MSA_R (*((volatile unsigned long *)0x40021000))
+#define I2C1_MASTER_SOAR_R (*((volatile unsigned long *)0x40021000))
+#define I2C1_MASTER_SCSR_R (*((volatile unsigned long *)0x40021004))
+#define I2C1_MASTER_MCS_R (*((volatile unsigned long *)0x40021004))
+#define I2C1_MASTER_SDR_R (*((volatile unsigned long *)0x40021008))
+#define I2C1_MASTER_MDR_R (*((volatile unsigned long *)0x40021008))
+#define I2C1_MASTER_MTPR_R (*((volatile unsigned long *)0x4002100C))
+#define I2C1_MASTER_SIMR_R (*((volatile unsigned long *)0x4002100C))
+#define I2C1_MASTER_SRIS_R (*((volatile unsigned long *)0x40021010))
+#define I2C1_MASTER_MIMR_R (*((volatile unsigned long *)0x40021010))
+#define I2C1_MASTER_MRIS_R (*((volatile unsigned long *)0x40021014))
+#define I2C1_MASTER_SMIS_R (*((volatile unsigned long *)0x40021014))
+#define I2C1_MASTER_SICR_R (*((volatile unsigned long *)0x40021018))
+#define I2C1_MASTER_MMIS_R (*((volatile unsigned long *)0x40021018))
+#define I2C1_MASTER_MICR_R (*((volatile unsigned long *)0x4002101C))
+#define I2C1_MASTER_MCR_R (*((volatile unsigned long *)0x40021020))
+
+//*****************************************************************************
+//
+// Inter-Integrated Circuit (SLAVE) Interface
+//
+//*****************************************************************************
+#define I2C1_SLAVE_MSA_R (*((volatile unsigned long *)0x40021800))
+#define I2C1_SLAVE_SOAR_R (*((volatile unsigned long *)0x40021800))
+#define I2C1_SLAVE_SCSR_R (*((volatile unsigned long *)0x40021804))
+#define I2C1_SLAVE_MCS_R (*((volatile unsigned long *)0x40021804))
+#define I2C1_SLAVE_SDR_R (*((volatile unsigned long *)0x40021808))
+#define I2C1_SLAVE_MDR_R (*((volatile unsigned long *)0x40021808))
+#define I2C1_SLAVE_MTPR_R (*((volatile unsigned long *)0x4002180C))
+#define I2C1_SLAVE_SIMR_R (*((volatile unsigned long *)0x4002180C))
+#define I2C1_SLAVE_SRIS_R (*((volatile unsigned long *)0x40021810))
+#define I2C1_SLAVE_MIMR_R (*((volatile unsigned long *)0x40021810))
+#define I2C1_SLAVE_MRIS_R (*((volatile unsigned long *)0x40021814))
+#define I2C1_SLAVE_SMIS_R (*((volatile unsigned long *)0x40021814))
+#define I2C1_SLAVE_SICR_R (*((volatile unsigned long *)0x40021818))
+#define I2C1_SLAVE_MMIS_R (*((volatile unsigned long *)0x40021818))
+#define I2C1_SLAVE_MICR_R (*((volatile unsigned long *)0x4002181C))
+#define I2C1_SLAVE_MCR_R (*((volatile unsigned long *)0x40021820))
+
+//*****************************************************************************
+//
+// General-Purpose Input/Outputs (PORTE)
+//
+//*****************************************************************************
+#define GPIO_PORTE_DATA_BITS_R ((volatile unsigned long *)0x40024000)
+#define GPIO_PORTE_DATA_R (*((volatile unsigned long *)0x400243FC))
+#define GPIO_PORTE_DIR_R (*((volatile unsigned long *)0x40024400))
+#define GPIO_PORTE_IS_R (*((volatile unsigned long *)0x40024404))
+#define GPIO_PORTE_IBE_R (*((volatile unsigned long *)0x40024408))
+#define GPIO_PORTE_IEV_R (*((volatile unsigned long *)0x4002440C))
+#define GPIO_PORTE_IM_R (*((volatile unsigned long *)0x40024410))
+#define GPIO_PORTE_RIS_R (*((volatile unsigned long *)0x40024414))
+#define GPIO_PORTE_MIS_R (*((volatile unsigned long *)0x40024418))
+#define GPIO_PORTE_ICR_R (*((volatile unsigned long *)0x4002441C))
+#define GPIO_PORTE_AFSEL_R (*((volatile unsigned long *)0x40024420))
+#define GPIO_PORTE_DR2R_R (*((volatile unsigned long *)0x40024500))
+#define GPIO_PORTE_DR4R_R (*((volatile unsigned long *)0x40024504))
+#define GPIO_PORTE_DR8R_R (*((volatile unsigned long *)0x40024508))
+#define GPIO_PORTE_ODR_R (*((volatile unsigned long *)0x4002450C))
+#define GPIO_PORTE_PUR_R (*((volatile unsigned long *)0x40024510))
+#define GPIO_PORTE_PDR_R (*((volatile unsigned long *)0x40024514))
+#define GPIO_PORTE_SLR_R (*((volatile unsigned long *)0x40024518))
+#define GPIO_PORTE_DEN_R (*((volatile unsigned long *)0x4002451C))
+#define GPIO_PORTE_LOCK_R (*((volatile unsigned long *)0x40024520))
+#define GPIO_PORTE_CR_R (*((volatile unsigned long *)0x40024524))
+#define GPIO_PORTE_AMSEL_R (*((volatile unsigned long *)0x40024528))
+#define GPIO_PORTE_PCTL_R (*((volatile unsigned long *)0x4002452C))
+
+//*****************************************************************************
+//
+// General-Purpose Input/Outputs (PORTF)
+//
+//*****************************************************************************
+#define GPIO_PORTF_DATA_BITS_R ((volatile unsigned long *)0x40025000)
+#define GPIO_PORTF_DATA_R (*((volatile unsigned long *)0x400253FC))
+#define GPIO_PORTF_DIR_R (*((volatile unsigned long *)0x40025400))
+#define GPIO_PORTF_IS_R (*((volatile unsigned long *)0x40025404))
+#define GPIO_PORTF_IBE_R (*((volatile unsigned long *)0x40025408))
+#define GPIO_PORTF_IEV_R (*((volatile unsigned long *)0x4002540C))
+#define GPIO_PORTF_IM_R (*((volatile unsigned long *)0x40025410))
+#define GPIO_PORTF_RIS_R (*((volatile unsigned long *)0x40025414))
+#define GPIO_PORTF_MIS_R (*((volatile unsigned long *)0x40025418))
+#define GPIO_PORTF_ICR_R (*((volatile unsigned long *)0x4002541C))
+#define GPIO_PORTF_AFSEL_R (*((volatile unsigned long *)0x40025420))
+#define GPIO_PORTF_DR2R_R (*((volatile unsigned long *)0x40025500))
+#define GPIO_PORTF_DR4R_R (*((volatile unsigned long *)0x40025504))
+#define GPIO_PORTF_DR8R_R (*((volatile unsigned long *)0x40025508))
+#define GPIO_PORTF_ODR_R (*((volatile unsigned long *)0x4002550C))
+#define GPIO_PORTF_PUR_R (*((volatile unsigned long *)0x40025510))
+#define GPIO_PORTF_PDR_R (*((volatile unsigned long *)0x40025514))
+#define GPIO_PORTF_SLR_R (*((volatile unsigned long *)0x40025518))
+#define GPIO_PORTF_DEN_R (*((volatile unsigned long *)0x4002551C))
+#define GPIO_PORTF_LOCK_R (*((volatile unsigned long *)0x40025520))
+#define GPIO_PORTF_CR_R (*((volatile unsigned long *)0x40025524))
+#define GPIO_PORTF_AMSEL_R (*((volatile unsigned long *)0x40025528))
+#define GPIO_PORTF_PCTL_R (*((volatile unsigned long *)0x4002552C))
+
+//*****************************************************************************
+//
+// General-Purpose Input/Outputs (PORTG)
+//
+//*****************************************************************************
+#define GPIO_PORTG_DATA_BITS_R ((volatile unsigned long *)0x40026000)
+#define GPIO_PORTG_DATA_R (*((volatile unsigned long *)0x400263FC))
+#define GPIO_PORTG_DIR_R (*((volatile unsigned long *)0x40026400))
+#define GPIO_PORTG_IS_R (*((volatile unsigned long *)0x40026404))
+#define GPIO_PORTG_IBE_R (*((volatile unsigned long *)0x40026408))
+#define GPIO_PORTG_IEV_R (*((volatile unsigned long *)0x4002640C))
+#define GPIO_PORTG_IM_R (*((volatile unsigned long *)0x40026410))
+#define GPIO_PORTG_RIS_R (*((volatile unsigned long *)0x40026414))
+#define GPIO_PORTG_MIS_R (*((volatile unsigned long *)0x40026418))
+#define GPIO_PORTG_ICR_R (*((volatile unsigned long *)0x4002641C))
+#define GPIO_PORTG_AFSEL_R (*((volatile unsigned long *)0x40026420))
+#define GPIO_PORTG_DR2R_R (*((volatile unsigned long *)0x40026500))
+#define GPIO_PORTG_DR4R_R (*((volatile unsigned long *)0x40026504))
+#define GPIO_PORTG_DR8R_R (*((volatile unsigned long *)0x40026508))
+#define GPIO_PORTG_ODR_R (*((volatile unsigned long *)0x4002650C))
+#define GPIO_PORTG_PUR_R (*((volatile unsigned long *)0x40026510))
+#define GPIO_PORTG_PDR_R (*((volatile unsigned long *)0x40026514))
+#define GPIO_PORTG_SLR_R (*((volatile unsigned long *)0x40026518))
+#define GPIO_PORTG_DEN_R (*((volatile unsigned long *)0x4002651C))
+#define GPIO_PORTG_LOCK_R (*((volatile unsigned long *)0x40026520))
+#define GPIO_PORTG_CR_R (*((volatile unsigned long *)0x40026524))
+#define GPIO_PORTG_AMSEL_R (*((volatile unsigned long *)0x40026528))
+#define GPIO_PORTG_PCTL_R (*((volatile unsigned long *)0x4002652C))
+
+//*****************************************************************************
+//
+// General-Purpose Input/Outputs (PORTH)
+//
+//*****************************************************************************
+#define GPIO_PORTH_DATA_BITS_R ((volatile unsigned long *)0x40027000)
+#define GPIO_PORTH_DATA_R (*((volatile unsigned long *)0x400273FC))
+#define GPIO_PORTH_DIR_R (*((volatile unsigned long *)0x40027400))
+#define GPIO_PORTH_IS_R (*((volatile unsigned long *)0x40027404))
+#define GPIO_PORTH_IBE_R (*((volatile unsigned long *)0x40027408))
+#define GPIO_PORTH_IEV_R (*((volatile unsigned long *)0x4002740C))
+#define GPIO_PORTH_IM_R (*((volatile unsigned long *)0x40027410))
+#define GPIO_PORTH_RIS_R (*((volatile unsigned long *)0x40027414))
+#define GPIO_PORTH_MIS_R (*((volatile unsigned long *)0x40027418))
+#define GPIO_PORTH_ICR_R (*((volatile unsigned long *)0x4002741C))
+#define GPIO_PORTH_AFSEL_R (*((volatile unsigned long *)0x40027420))
+#define GPIO_PORTH_DR2R_R (*((volatile unsigned long *)0x40027500))
+#define GPIO_PORTH_DR4R_R (*((volatile unsigned long *)0x40027504))
+#define GPIO_PORTH_DR8R_R (*((volatile unsigned long *)0x40027508))
+#define GPIO_PORTH_ODR_R (*((volatile unsigned long *)0x4002750C))
+#define GPIO_PORTH_PUR_R (*((volatile unsigned long *)0x40027510))
+#define GPIO_PORTH_PDR_R (*((volatile unsigned long *)0x40027514))
+#define GPIO_PORTH_SLR_R (*((volatile unsigned long *)0x40027518))
+#define GPIO_PORTH_DEN_R (*((volatile unsigned long *)0x4002751C))
+#define GPIO_PORTH_LOCK_R (*((volatile unsigned long *)0x40027520))
+#define GPIO_PORTH_CR_R (*((volatile unsigned long *)0x40027524))
+#define GPIO_PORTH_AMSEL_R (*((volatile unsigned long *)0x40027528))
+#define GPIO_PORTH_PCTL_R (*((volatile unsigned long *)0x4002752C))
+
+//*****************************************************************************
+//
+// Pulse Width Modulator (PWM)
+//
+//*****************************************************************************
+#define PWM_CTL_R (*((volatile unsigned long *)0x40028000))
+#define PWM_SYNC_R (*((volatile unsigned long *)0x40028004))
+#define PWM_ENABLE_R (*((volatile unsigned long *)0x40028008))
+#define PWM_INVERT_R (*((volatile unsigned long *)0x4002800C))
+#define PWM_FAULT_R (*((volatile unsigned long *)0x40028010))
+#define PWM_INTEN_R (*((volatile unsigned long *)0x40028014))
+#define PWM_RIS_R (*((volatile unsigned long *)0x40028018))
+#define PWM_ISC_R (*((volatile unsigned long *)0x4002801C))
+#define PWM_STATUS_R (*((volatile unsigned long *)0x40028020))
+#define PWM_FAULTVAL_R (*((volatile unsigned long *)0x40028024))
+#define PWM_0_CTL_R (*((volatile unsigned long *)0x40028040))
+#define PWM_0_INTEN_R (*((volatile unsigned long *)0x40028044))
+#define PWM_0_RIS_R (*((volatile unsigned long *)0x40028048))
+#define PWM_0_ISC_R (*((volatile unsigned long *)0x4002804C))
+#define PWM_0_LOAD_R (*((volatile unsigned long *)0x40028050))
+#define PWM_0_COUNT_R (*((volatile unsigned long *)0x40028054))
+#define PWM_0_CMPA_R (*((volatile unsigned long *)0x40028058))
+#define PWM_0_CMPB_R (*((volatile unsigned long *)0x4002805C))
+#define PWM_0_GENA_R (*((volatile unsigned long *)0x40028060))
+#define PWM_0_GENB_R (*((volatile unsigned long *)0x40028064))
+#define PWM_0_DBCTL_R (*((volatile unsigned long *)0x40028068))
+#define PWM_0_DBRISE_R (*((volatile unsigned long *)0x4002806C))
+#define PWM_0_DBFALL_R (*((volatile unsigned long *)0x40028070))
+#define PWM_0_FLTSRC0_R (*((volatile unsigned long *)0x40028074))
+#define PWM_0_FLTSRC1_R (*((volatile unsigned long *)0x40028078))
+#define PWM_0_MINFLTPER_R (*((volatile unsigned long *)0x4002807C))
+#define PWM_1_CTL_R (*((volatile unsigned long *)0x40028080))
+#define PWM_1_INTEN_R (*((volatile unsigned long *)0x40028084))
+#define PWM_1_RIS_R (*((volatile unsigned long *)0x40028088))
+#define PWM_1_ISC_R (*((volatile unsigned long *)0x4002808C))
+#define PWM_1_LOAD_R (*((volatile unsigned long *)0x40028090))
+#define PWM_1_COUNT_R (*((volatile unsigned long *)0x40028094))
+#define PWM_1_CMPA_R (*((volatile unsigned long *)0x40028098))
+#define PWM_1_CMPB_R (*((volatile unsigned long *)0x4002809C))
+#define PWM_1_GENA_R (*((volatile unsigned long *)0x400280A0))
+#define PWM_1_GENB_R (*((volatile unsigned long *)0x400280A4))
+#define PWM_1_DBCTL_R (*((volatile unsigned long *)0x400280A8))
+#define PWM_1_DBRISE_R (*((volatile unsigned long *)0x400280AC))
+#define PWM_1_DBFALL_R (*((volatile unsigned long *)0x400280B0))
+#define PWM_1_FLTSRC0_R (*((volatile unsigned long *)0x400280B4))
+#define PWM_1_FLTSRC1_R (*((volatile unsigned long *)0x400280B8))
+#define PWM_1_MINFLTPER_R (*((volatile unsigned long *)0x400280BC))
+#define PWM_2_CTL_R (*((volatile unsigned long *)0x400280C0))
+#define PWM_2_INTEN_R (*((volatile unsigned long *)0x400280C4))
+#define PWM_2_RIS_R (*((volatile unsigned long *)0x400280C8))
+#define PWM_2_ISC_R (*((volatile unsigned long *)0x400280CC))
+#define PWM_2_LOAD_R (*((volatile unsigned long *)0x400280D0))
+#define PWM_2_COUNT_R (*((volatile unsigned long *)0x400280D4))
+#define PWM_2_CMPA_R (*((volatile unsigned long *)0x400280D8))
+#define PWM_2_CMPB_R (*((volatile unsigned long *)0x400280DC))
+#define PWM_2_GENA_R (*((volatile unsigned long *)0x400280E0))
+#define PWM_2_GENB_R (*((volatile unsigned long *)0x400280E4))
+#define PWM_2_DBCTL_R (*((volatile unsigned long *)0x400280E8))
+#define PWM_2_DBRISE_R (*((volatile unsigned long *)0x400280EC))
+#define PWM_2_DBFALL_R (*((volatile unsigned long *)0x400280F0))
+#define PWM_2_FLTSRC0_R (*((volatile unsigned long *)0x400280F4))
+#define PWM_2_FLTSRC1_R (*((volatile unsigned long *)0x400280F8))
+#define PWM_2_MINFLTPER_R (*((volatile unsigned long *)0x400280FC))
+#define PWM_3_CTL_R (*((volatile unsigned long *)0x40028100))
+#define PWM_3_INTEN_R (*((volatile unsigned long *)0x40028104))
+#define PWM_3_RIS_R (*((volatile unsigned long *)0x40028108))
+#define PWM_3_ISC_R (*((volatile unsigned long *)0x4002810C))
+#define PWM_3_LOAD_R (*((volatile unsigned long *)0x40028110))
+#define PWM_3_COUNT_R (*((volatile unsigned long *)0x40028114))
+#define PWM_3_CMPA_R (*((volatile unsigned long *)0x40028118))
+#define PWM_3_CMPB_R (*((volatile unsigned long *)0x4002811C))
+#define PWM_3_GENA_R (*((volatile unsigned long *)0x40028120))
+#define PWM_3_GENB_R (*((volatile unsigned long *)0x40028124))
+#define PWM_3_DBCTL_R (*((volatile unsigned long *)0x40028128))
+#define PWM_3_DBRISE_R (*((volatile unsigned long *)0x4002812C))
+#define PWM_3_DBFALL_R (*((volatile unsigned long *)0x40028130))
+#define PWM_3_FLTSRC0_R (*((volatile unsigned long *)0x40028134))
+#define PWM_3_FLTSRC1_R (*((volatile unsigned long *)0x40028138))
+#define PWM_3_MINFLTPER_R (*((volatile unsigned long *)0x4002813C))
+#define PWM_0_FLTSEN_R (*((volatile unsigned long *)0x40028800))
+#define PWM_0_FLTSTAT0_R (*((volatile unsigned long *)0x40028804))
+#define PWM_0_FLTSTAT1_R (*((volatile unsigned long *)0x40028808))
+#define PWM_1_FLTSEN_R (*((volatile unsigned long *)0x40028880))
+#define PWM_1_FLTSTAT0_R (*((volatile unsigned long *)0x40028884))
+#define PWM_1_FLTSTAT1_R (*((volatile unsigned long *)0x40028888))
+#define PWM_2_FLTSEN_R (*((volatile unsigned long *)0x40028900))
+#define PWM_2_FLTSTAT0_R (*((volatile unsigned long *)0x40028904))
+#define PWM_2_FLTSTAT1_R (*((volatile unsigned long *)0x40028908))
+#define PWM_3_FLTSEN_R (*((volatile unsigned long *)0x40028980))
+#define PWM_3_FLTSTAT0_R (*((volatile unsigned long *)0x40028984))
+#define PWM_3_FLTSTAT1_R (*((volatile unsigned long *)0x40028988))
+
+//*****************************************************************************
+//
+// Quadrature Encoder Interface (QEI0)
+//
+//*****************************************************************************
+#define QEI0_CTL_R (*((volatile unsigned long *)0x4002C000))
+#define QEI0_STAT_R (*((volatile unsigned long *)0x4002C004))
+#define QEI0_POS_R (*((volatile unsigned long *)0x4002C008))
+#define QEI0_MAXPOS_R (*((volatile unsigned long *)0x4002C00C))
+#define QEI0_LOAD_R (*((volatile unsigned long *)0x4002C010))
+#define QEI0_TIME_R (*((volatile unsigned long *)0x4002C014))
+#define QEI0_COUNT_R (*((volatile unsigned long *)0x4002C018))
+#define QEI0_SPEED_R (*((volatile unsigned long *)0x4002C01C))
+#define QEI0_INTEN_R (*((volatile unsigned long *)0x4002C020))
+#define QEI0_RIS_R (*((volatile unsigned long *)0x4002C024))
+#define QEI0_ISC_R (*((volatile unsigned long *)0x4002C028))
+
+//*****************************************************************************
+//
+// Quadrature Encoder Interface (QEI1)
+//
+//*****************************************************************************
+#define QEI1_CTL_R (*((volatile unsigned long *)0x4002D000))
+#define QEI1_STAT_R (*((volatile unsigned long *)0x4002D004))
+#define QEI1_POS_R (*((volatile unsigned long *)0x4002D008))
+#define QEI1_MAXPOS_R (*((volatile unsigned long *)0x4002D00C))
+#define QEI1_LOAD_R (*((volatile unsigned long *)0x4002D010))
+#define QEI1_TIME_R (*((volatile unsigned long *)0x4002D014))
+#define QEI1_COUNT_R (*((volatile unsigned long *)0x4002D018))
+#define QEI1_SPEED_R (*((volatile unsigned long *)0x4002D01C))
+#define QEI1_INTEN_R (*((volatile unsigned long *)0x4002D020))
+#define QEI1_RIS_R (*((volatile unsigned long *)0x4002D024))
+#define QEI1_ISC_R (*((volatile unsigned long *)0x4002D028))
+
+//*****************************************************************************
+//
+// General-Purpose Timers (TIMER0)
+//
+//*****************************************************************************
+#define TIMER0_CFG_R (*((volatile unsigned long *)0x40030000))
+#define TIMER0_TAMR_R (*((volatile unsigned long *)0x40030004))
+#define TIMER0_TBMR_R (*((volatile unsigned long *)0x40030008))
+#define TIMER0_CTL_R (*((volatile unsigned long *)0x4003000C))
+#define TIMER0_IMR_R (*((volatile unsigned long *)0x40030018))
+#define TIMER0_RIS_R (*((volatile unsigned long *)0x4003001C))
+#define TIMER0_MIS_R (*((volatile unsigned long *)0x40030020))
+#define TIMER0_ICR_R (*((volatile unsigned long *)0x40030024))
+#define TIMER0_TAILR_R (*((volatile unsigned long *)0x40030028))
+#define TIMER0_TBILR_R (*((volatile unsigned long *)0x4003002C))
+#define TIMER0_TAMATCHR_R (*((volatile unsigned long *)0x40030030))
+#define TIMER0_TBMATCHR_R (*((volatile unsigned long *)0x40030034))
+#define TIMER0_TAPR_R (*((volatile unsigned long *)0x40030038))
+#define TIMER0_TBPR_R (*((volatile unsigned long *)0x4003003C))
+#define TIMER0_TAR_R (*((volatile unsigned long *)0x40030048))
+#define TIMER0_TBR_R (*((volatile unsigned long *)0x4003004C))
+#define TIMER0_TAV_R (*((volatile unsigned long *)0x40030050))
+#define TIMER0_TBV_R (*((volatile unsigned long *)0x40030054))
+
+//*****************************************************************************
+//
+// General-Purpose Timers (TIMER1)
+//
+//*****************************************************************************
+#define TIMER1_CFG_R (*((volatile unsigned long *)0x40031000))
+#define TIMER1_TAMR_R (*((volatile unsigned long *)0x40031004))
+#define TIMER1_TBMR_R (*((volatile unsigned long *)0x40031008))
+#define TIMER1_CTL_R (*((volatile unsigned long *)0x4003100C))
+#define TIMER1_IMR_R (*((volatile unsigned long *)0x40031018))
+#define TIMER1_RIS_R (*((volatile unsigned long *)0x4003101C))
+#define TIMER1_MIS_R (*((volatile unsigned long *)0x40031020))
+#define TIMER1_ICR_R (*((volatile unsigned long *)0x40031024))
+#define TIMER1_TAILR_R (*((volatile unsigned long *)0x40031028))
+#define TIMER1_TBILR_R (*((volatile unsigned long *)0x4003102C))
+#define TIMER1_TAMATCHR_R (*((volatile unsigned long *)0x40031030))
+#define TIMER1_TBMATCHR_R (*((volatile unsigned long *)0x40031034))
+#define TIMER1_TAPR_R (*((volatile unsigned long *)0x40031038))
+#define TIMER1_TBPR_R (*((volatile unsigned long *)0x4003103C))
+#define TIMER1_TAR_R (*((volatile unsigned long *)0x40031048))
+#define TIMER1_TBR_R (*((volatile unsigned long *)0x4003104C))
+#define TIMER1_TAV_R (*((volatile unsigned long *)0x40031050))
+#define TIMER1_TBV_R (*((volatile unsigned long *)0x40031054))
+
+//*****************************************************************************
+//
+// General-Purpose Timers (TIMER2)
+//
+//*****************************************************************************
+#define TIMER2_CFG_R (*((volatile unsigned long *)0x40032000))
+#define TIMER2_TAMR_R (*((volatile unsigned long *)0x40032004))
+#define TIMER2_TBMR_R (*((volatile unsigned long *)0x40032008))
+#define TIMER2_CTL_R (*((volatile unsigned long *)0x4003200C))
+#define TIMER2_IMR_R (*((volatile unsigned long *)0x40032018))
+#define TIMER2_RIS_R (*((volatile unsigned long *)0x4003201C))
+#define TIMER2_MIS_R (*((volatile unsigned long *)0x40032020))
+#define TIMER2_ICR_R (*((volatile unsigned long *)0x40032024))
+#define TIMER2_TAILR_R (*((volatile unsigned long *)0x40032028))
+#define TIMER2_TBILR_R (*((volatile unsigned long *)0x4003202C))
+#define TIMER2_TAMATCHR_R (*((volatile unsigned long *)0x40032030))
+#define TIMER2_TBMATCHR_R (*((volatile unsigned long *)0x40032034))
+#define TIMER2_TAPR_R (*((volatile unsigned long *)0x40032038))
+#define TIMER2_TBPR_R (*((volatile unsigned long *)0x4003203C))
+#define TIMER2_TAR_R (*((volatile unsigned long *)0x40032048))
+#define TIMER2_TBR_R (*((volatile unsigned long *)0x4003204C))
+#define TIMER2_TAV_R (*((volatile unsigned long *)0x40032050))
+#define TIMER2_TBV_R (*((volatile unsigned long *)0x40032054))
+
+//*****************************************************************************
+//
+// General-Purpose Timers (TIMER3)
+//
+//*****************************************************************************
+#define TIMER3_CFG_R (*((volatile unsigned long *)0x40033000))
+#define TIMER3_TAMR_R (*((volatile unsigned long *)0x40033004))
+#define TIMER3_TBMR_R (*((volatile unsigned long *)0x40033008))
+#define TIMER3_CTL_R (*((volatile unsigned long *)0x4003300C))
+#define TIMER3_IMR_R (*((volatile unsigned long *)0x40033018))
+#define TIMER3_RIS_R (*((volatile unsigned long *)0x4003301C))
+#define TIMER3_MIS_R (*((volatile unsigned long *)0x40033020))
+#define TIMER3_ICR_R (*((volatile unsigned long *)0x40033024))
+#define TIMER3_TAILR_R (*((volatile unsigned long *)0x40033028))
+#define TIMER3_TBILR_R (*((volatile unsigned long *)0x4003302C))
+#define TIMER3_TAMATCHR_R (*((volatile unsigned long *)0x40033030))
+#define TIMER3_TBMATCHR_R (*((volatile unsigned long *)0x40033034))
+#define TIMER3_TAPR_R (*((volatile unsigned long *)0x40033038))
+#define TIMER3_TBPR_R (*((volatile unsigned long *)0x4003303C))
+#define TIMER3_TAR_R (*((volatile unsigned long *)0x40033048))
+#define TIMER3_TBR_R (*((volatile unsigned long *)0x4003304C))
+#define TIMER3_TAV_R (*((volatile unsigned long *)0x40033050))
+#define TIMER3_TBV_R (*((volatile unsigned long *)0x40033054))
+
+//*****************************************************************************
+//
+// Analog-to-Digital Converter (ADC0)
+//
+//*****************************************************************************
+#define ADC0_ACTSS_R (*((volatile unsigned long *)0x40038000))
+#define ADC0_RIS_R (*((volatile unsigned long *)0x40038004))
+#define ADC0_IM_R (*((volatile unsigned long *)0x40038008))
+#define ADC0_ISC_R (*((volatile unsigned long *)0x4003800C))
+#define ADC0_OSTAT_R (*((volatile unsigned long *)0x40038010))
+#define ADC0_EMUX_R (*((volatile unsigned long *)0x40038014))
+#define ADC0_USTAT_R (*((volatile unsigned long *)0x40038018))
+#define ADC0_SSPRI_R (*((volatile unsigned long *)0x40038020))
+#define ADC0_PSSI_R (*((volatile unsigned long *)0x40038028))
+#define ADC0_SAC_R (*((volatile unsigned long *)0x40038030))
+#define ADC0_DCISC_R (*((volatile unsigned long *)0x40038034))
+#define ADC0_CTL_R (*((volatile unsigned long *)0x40038038))
+#define ADC0_SSMUX0_R (*((volatile unsigned long *)0x40038040))
+#define ADC0_SSCTL0_R (*((volatile unsigned long *)0x40038044))
+#define ADC0_SSFIFO0_R (*((volatile unsigned long *)0x40038048))
+#define ADC0_SSFSTAT0_R (*((volatile unsigned long *)0x4003804C))
+#define ADC0_SSOP0_R (*((volatile unsigned long *)0x40038050))
+#define ADC0_SSDC0_R (*((volatile unsigned long *)0x40038054))
+#define ADC0_SSMUX1_R (*((volatile unsigned long *)0x40038060))
+#define ADC0_SSCTL1_R (*((volatile unsigned long *)0x40038064))
+#define ADC0_SSFIFO1_R (*((volatile unsigned long *)0x40038068))
+#define ADC0_SSFSTAT1_R (*((volatile unsigned long *)0x4003806C))
+#define ADC0_SSOP1_R (*((volatile unsigned long *)0x40038070))
+#define ADC0_SSDC1_R (*((volatile unsigned long *)0x40038074))
+#define ADC0_SSMUX2_R (*((volatile unsigned long *)0x40038080))
+#define ADC0_SSCTL2_R (*((volatile unsigned long *)0x40038084))
+#define ADC0_SSFIFO2_R (*((volatile unsigned long *)0x40038088))
+#define ADC0_SSFSTAT2_R (*((volatile unsigned long *)0x4003808C))
+#define ADC0_SSOP2_R (*((volatile unsigned long *)0x40038090))
+#define ADC0_SSDC2_R (*((volatile unsigned long *)0x40038094))
+#define ADC0_SSMUX3_R (*((volatile unsigned long *)0x400380A0))
+#define ADC0_SSCTL3_R (*((volatile unsigned long *)0x400380A4))
+#define ADC0_SSFIFO3_R (*((volatile unsigned long *)0x400380A8))
+#define ADC0_SSFSTAT3_R (*((volatile unsigned long *)0x400380AC))
+#define ADC0_SSOP3_R (*((volatile unsigned long *)0x400380B0))
+#define ADC0_SSDC3_R (*((volatile unsigned long *)0x400380B4))
+#define ADC0_DCRIC_R (*((volatile unsigned long *)0x40038D00))
+#define ADC0_DCCTL0_R (*((volatile unsigned long *)0x40038E00))
+#define ADC0_DCCTL1_R (*((volatile unsigned long *)0x40038E04))
+#define ADC0_DCCTL2_R (*((volatile unsigned long *)0x40038E08))
+#define ADC0_DCCTL3_R (*((volatile unsigned long *)0x40038E0C))
+#define ADC0_DCCTL4_R (*((volatile unsigned long *)0x40038E10))
+#define ADC0_DCCTL5_R (*((volatile unsigned long *)0x40038E14))
+#define ADC0_DCCTL6_R (*((volatile unsigned long *)0x40038E18))
+#define ADC0_DCCTL7_R (*((volatile unsigned long *)0x40038E1C))
+#define ADC0_DCCMP0_R (*((volatile unsigned long *)0x40038E40))
+#define ADC0_DCCMP1_R (*((volatile unsigned long *)0x40038E44))
+#define ADC0_DCCMP2_R (*((volatile unsigned long *)0x40038E48))
+#define ADC0_DCCMP3_R (*((volatile unsigned long *)0x40038E4C))
+#define ADC0_DCCMP4_R (*((volatile unsigned long *)0x40038E50))
+#define ADC0_DCCMP5_R (*((volatile unsigned long *)0x40038E54))
+#define ADC0_DCCMP6_R (*((volatile unsigned long *)0x40038E58))
+#define ADC0_DCCMP7_R (*((volatile unsigned long *)0x40038E5C))
+
+//*****************************************************************************
+//
+// Analog-to-Digital Converter (ADC1)
+//
+//*****************************************************************************
+#define ADC1_ACTSS_R (*((volatile unsigned long *)0x40039000))
+#define ADC1_RIS_R (*((volatile unsigned long *)0x40039004))
+#define ADC1_IM_R (*((volatile unsigned long *)0x40039008))
+#define ADC1_ISC_R (*((volatile unsigned long *)0x4003900C))
+#define ADC1_OSTAT_R (*((volatile unsigned long *)0x40039010))
+#define ADC1_EMUX_R (*((volatile unsigned long *)0x40039014))
+#define ADC1_USTAT_R (*((volatile unsigned long *)0x40039018))
+#define ADC1_SSPRI_R (*((volatile unsigned long *)0x40039020))
+#define ADC1_PSSI_R (*((volatile unsigned long *)0x40039028))
+#define ADC1_SAC_R (*((volatile unsigned long *)0x40039030))
+#define ADC1_DCISC_R (*((volatile unsigned long *)0x40039034))
+#define ADC1_CTL_R (*((volatile unsigned long *)0x40039038))
+#define ADC1_SSMUX0_R (*((volatile unsigned long *)0x40039040))
+#define ADC1_SSCTL0_R (*((volatile unsigned long *)0x40039044))
+#define ADC1_SSFIFO0_R (*((volatile unsigned long *)0x40039048))
+#define ADC1_SSFSTAT0_R (*((volatile unsigned long *)0x4003904C))
+#define ADC1_SSOP0_R (*((volatile unsigned long *)0x40039050))
+#define ADC1_SSDC0_R (*((volatile unsigned long *)0x40039054))
+#define ADC1_SSMUX1_R (*((volatile unsigned long *)0x40039060))
+#define ADC1_SSCTL1_R (*((volatile unsigned long *)0x40039064))
+#define ADC1_SSFIFO1_R (*((volatile unsigned long *)0x40039068))
+#define ADC1_SSFSTAT1_R (*((volatile unsigned long *)0x4003906C))
+#define ADC1_SSOP1_R (*((volatile unsigned long *)0x40039070))
+#define ADC1_SSDC1_R (*((volatile unsigned long *)0x40039074))
+#define ADC1_SSMUX2_R (*((volatile unsigned long *)0x40039080))
+#define ADC1_SSCTL2_R (*((volatile unsigned long *)0x40039084))
+#define ADC1_SSFIFO2_R (*((volatile unsigned long *)0x40039088))
+#define ADC1_SSFSTAT2_R (*((volatile unsigned long *)0x4003908C))
+#define ADC1_SSOP2_R (*((volatile unsigned long *)0x40039090))
+#define ADC1_SSDC2_R (*((volatile unsigned long *)0x40039094))
+#define ADC1_SSMUX3_R (*((volatile unsigned long *)0x400390A0))
+#define ADC1_SSCTL3_R (*((volatile unsigned long *)0x400390A4))
+#define ADC1_SSFIFO3_R (*((volatile unsigned long *)0x400390A8))
+#define ADC1_SSFSTAT3_R (*((volatile unsigned long *)0x400390AC))
+#define ADC1_SSOP3_R (*((volatile unsigned long *)0x400390B0))
+#define ADC1_SSDC3_R (*((volatile unsigned long *)0x400390B4))
+#define ADC1_DCRIC_R (*((volatile unsigned long *)0x40039D00))
+#define ADC1_DCCTL0_R (*((volatile unsigned long *)0x40039E00))
+#define ADC1_DCCTL1_R (*((volatile unsigned long *)0x40039E04))
+#define ADC1_DCCTL2_R (*((volatile unsigned long *)0x40039E08))
+#define ADC1_DCCTL3_R (*((volatile unsigned long *)0x40039E0C))
+#define ADC1_DCCTL4_R (*((volatile unsigned long *)0x40039E10))
+#define ADC1_DCCTL5_R (*((volatile unsigned long *)0x40039E14))
+#define ADC1_DCCTL6_R (*((volatile unsigned long *)0x40039E18))
+#define ADC1_DCCTL7_R (*((volatile unsigned long *)0x40039E1C))
+#define ADC1_DCCMP0_R (*((volatile unsigned long *)0x40039E40))
+#define ADC1_DCCMP1_R (*((volatile unsigned long *)0x40039E44))
+#define ADC1_DCCMP2_R (*((volatile unsigned long *)0x40039E48))
+#define ADC1_DCCMP3_R (*((volatile unsigned long *)0x40039E4C))
+#define ADC1_DCCMP4_R (*((volatile unsigned long *)0x40039E50))
+#define ADC1_DCCMP5_R (*((volatile unsigned long *)0x40039E54))
+#define ADC1_DCCMP6_R (*((volatile unsigned long *)0x40039E58))
+#define ADC1_DCCMP7_R (*((volatile unsigned long *)0x40039E5C))
+
+//*****************************************************************************
+//
+// Analog Comparators (COMP)
+//
+//*****************************************************************************
+#define COMP_ACMIS_R (*((volatile unsigned long *)0x4003C000))
+#define COMP_ACRIS_R (*((volatile unsigned long *)0x4003C004))
+#define COMP_ACINTEN_R (*((volatile unsigned long *)0x4003C008))
+#define COMP_ACREFCTL_R (*((volatile unsigned long *)0x4003C010))
+#define COMP_ACSTAT0_R (*((volatile unsigned long *)0x4003C020))
+#define COMP_ACCTL0_R (*((volatile unsigned long *)0x4003C024))
+#define COMP_ACSTAT1_R (*((volatile unsigned long *)0x4003C040))
+#define COMP_ACCTL1_R (*((volatile unsigned long *)0x4003C044))
+#define COMP_ACSTAT2_R (*((volatile unsigned long *)0x4003C060))
+#define COMP_ACCTL2_R (*((volatile unsigned long *)0x4003C064))
+
+//*****************************************************************************
+//
+// General-Purpose Input/Outputs (PORTJ)
+//
+//*****************************************************************************
+#define GPIO_PORTJ_DATA_BITS_R ((volatile unsigned long *)0x4003D000)
+#define GPIO_PORTJ_DATA_R (*((volatile unsigned long *)0x4003D3FC))
+#define GPIO_PORTJ_DIR_R (*((volatile unsigned long *)0x4003D400))
+#define GPIO_PORTJ_IS_R (*((volatile unsigned long *)0x4003D404))
+#define GPIO_PORTJ_IBE_R (*((volatile unsigned long *)0x4003D408))
+#define GPIO_PORTJ_IEV_R (*((volatile unsigned long *)0x4003D40C))
+#define GPIO_PORTJ_IM_R (*((volatile unsigned long *)0x4003D410))
+#define GPIO_PORTJ_RIS_R (*((volatile unsigned long *)0x4003D414))
+#define GPIO_PORTJ_MIS_R (*((volatile unsigned long *)0x4003D418))
+#define GPIO_PORTJ_ICR_R (*((volatile unsigned long *)0x4003D41C))
+#define GPIO_PORTJ_AFSEL_R (*((volatile unsigned long *)0x4003D420))
+#define GPIO_PORTJ_DR2R_R (*((volatile unsigned long *)0x4003D500))
+#define GPIO_PORTJ_DR4R_R (*((volatile unsigned long *)0x4003D504))
+#define GPIO_PORTJ_DR8R_R (*((volatile unsigned long *)0x4003D508))
+#define GPIO_PORTJ_ODR_R (*((volatile unsigned long *)0x4003D50C))
+#define GPIO_PORTJ_PUR_R (*((volatile unsigned long *)0x4003D510))
+#define GPIO_PORTJ_PDR_R (*((volatile unsigned long *)0x4003D514))
+#define GPIO_PORTJ_SLR_R (*((volatile unsigned long *)0x4003D518))
+#define GPIO_PORTJ_DEN_R (*((volatile unsigned long *)0x4003D51C))
+#define GPIO_PORTJ_LOCK_R (*((volatile unsigned long *)0x4003D520))
+#define GPIO_PORTJ_CR_R (*((volatile unsigned long *)0x4003D524))
+#define GPIO_PORTJ_AMSEL_R (*((volatile unsigned long *)0x4003D528))
+#define GPIO_PORTJ_PCTL_R (*((volatile unsigned long *)0x4003D52C))
+
+//*****************************************************************************
+//
+// Controller Area Network (CAN0) Module
+//
+//*****************************************************************************
+#define CAN0_CTL_R (*((volatile unsigned long *)0x40040000))
+#define CAN0_STS_R (*((volatile unsigned long *)0x40040004))
+#define CAN0_ERR_R (*((volatile unsigned long *)0x40040008))
+#define CAN0_BIT_R (*((volatile unsigned long *)0x4004000C))
+#define CAN0_INT_R (*((volatile unsigned long *)0x40040010))
+#define CAN0_TST_R (*((volatile unsigned long *)0x40040014))
+#define CAN0_BRPE_R (*((volatile unsigned long *)0x40040018))
+#define CAN0_IF1CRQ_R (*((volatile unsigned long *)0x40040020))
+#define CAN0_IF1CMSK_R (*((volatile unsigned long *)0x40040024))
+#define CAN0_IF1MSK1_R (*((volatile unsigned long *)0x40040028))
+#define CAN0_IF1MSK2_R (*((volatile unsigned long *)0x4004002C))
+#define CAN0_IF1ARB1_R (*((volatile unsigned long *)0x40040030))
+#define CAN0_IF1ARB2_R (*((volatile unsigned long *)0x40040034))
+#define CAN0_IF1MCTL_R (*((volatile unsigned long *)0x40040038))
+#define CAN0_IF1DA1_R (*((volatile unsigned long *)0x4004003C))
+#define CAN0_IF1DA2_R (*((volatile unsigned long *)0x40040040))
+#define CAN0_IF1DB1_R (*((volatile unsigned long *)0x40040044))
+#define CAN0_IF1DB2_R (*((volatile unsigned long *)0x40040048))
+#define CAN0_IF2CRQ_R (*((volatile unsigned long *)0x40040080))
+#define CAN0_IF2CMSK_R (*((volatile unsigned long *)0x40040084))
+#define CAN0_IF2MSK1_R (*((volatile unsigned long *)0x40040088))
+#define CAN0_IF2MSK2_R (*((volatile unsigned long *)0x4004008C))
+#define CAN0_IF2ARB1_R (*((volatile unsigned long *)0x40040090))
+#define CAN0_IF2ARB2_R (*((volatile unsigned long *)0x40040094))
+#define CAN0_IF2MCTL_R (*((volatile unsigned long *)0x40040098))
+#define CAN0_IF2DA1_R (*((volatile unsigned long *)0x4004009C))
+#define CAN0_IF2DA2_R (*((volatile unsigned long *)0x400400A0))
+#define CAN0_IF2DB1_R (*((volatile unsigned long *)0x400400A4))
+#define CAN0_IF2DB2_R (*((volatile unsigned long *)0x400400A8))
+#define CAN0_TXRQ1_R (*((volatile unsigned long *)0x40040100))
+#define CAN0_TXRQ2_R (*((volatile unsigned long *)0x40040104))
+#define CAN0_NWDA1_R (*((volatile unsigned long *)0x40040120))
+#define CAN0_NWDA2_R (*((volatile unsigned long *)0x40040124))
+#define CAN0_MSG1INT_R (*((volatile unsigned long *)0x40040140))
+#define CAN0_MSG2INT_R (*((volatile unsigned long *)0x40040144))
+#define CAN0_MSG1VAL_R (*((volatile unsigned long *)0x40040160))
+#define CAN0_MSG2VAL_R (*((volatile unsigned long *)0x40040164))
+
+//*****************************************************************************
+//
+// Controller Area Network (CAN1) Module
+//
+//*****************************************************************************
+#define CAN1_CTL_R (*((volatile unsigned long *)0x40041000))
+#define CAN1_STS_R (*((volatile unsigned long *)0x40041004))
+#define CAN1_ERR_R (*((volatile unsigned long *)0x40041008))
+#define CAN1_BIT_R (*((volatile unsigned long *)0x4004100C))
+#define CAN1_INT_R (*((volatile unsigned long *)0x40041010))
+#define CAN1_TST_R (*((volatile unsigned long *)0x40041014))
+#define CAN1_BRPE_R (*((volatile unsigned long *)0x40041018))
+#define CAN1_IF1CRQ_R (*((volatile unsigned long *)0x40041020))
+#define CAN1_IF1CMSK_R (*((volatile unsigned long *)0x40041024))
+#define CAN1_IF1MSK1_R (*((volatile unsigned long *)0x40041028))
+#define CAN1_IF1MSK2_R (*((volatile unsigned long *)0x4004102C))
+#define CAN1_IF1ARB1_R (*((volatile unsigned long *)0x40041030))
+#define CAN1_IF1ARB2_R (*((volatile unsigned long *)0x40041034))
+#define CAN1_IF1MCTL_R (*((volatile unsigned long *)0x40041038))
+#define CAN1_IF1DA1_R (*((volatile unsigned long *)0x4004103C))
+#define CAN1_IF1DA2_R (*((volatile unsigned long *)0x40041040))
+#define CAN1_IF1DB1_R (*((volatile unsigned long *)0x40041044))
+#define CAN1_IF1DB2_R (*((volatile unsigned long *)0x40041048))
+#define CAN1_IF2CRQ_R (*((volatile unsigned long *)0x40041080))
+#define CAN1_IF2CMSK_R (*((volatile unsigned long *)0x40041084))
+#define CAN1_IF2MSK1_R (*((volatile unsigned long *)0x40041088))
+#define CAN1_IF2MSK2_R (*((volatile unsigned long *)0x4004108C))
+#define CAN1_IF2ARB1_R (*((volatile unsigned long *)0x40041090))
+#define CAN1_IF2ARB2_R (*((volatile unsigned long *)0x40041094))
+#define CAN1_IF2MCTL_R (*((volatile unsigned long *)0x40041098))
+#define CAN1_IF2DA1_R (*((volatile unsigned long *)0x4004109C))
+#define CAN1_IF2DA2_R (*((volatile unsigned long *)0x400410A0))
+#define CAN1_IF2DB1_R (*((volatile unsigned long *)0x400410A4))
+#define CAN1_IF2DB2_R (*((volatile unsigned long *)0x400410A8))
+#define CAN1_TXRQ1_R (*((volatile unsigned long *)0x40041100))
+#define CAN1_TXRQ2_R (*((volatile unsigned long *)0x40041104))
+#define CAN1_NWDA1_R (*((volatile unsigned long *)0x40041120))
+#define CAN1_NWDA2_R (*((volatile unsigned long *)0x40041124))
+#define CAN1_MSG1INT_R (*((volatile unsigned long *)0x40041140))
+#define CAN1_MSG2INT_R (*((volatile unsigned long *)0x40041144))
+#define CAN1_MSG1VAL_R (*((volatile unsigned long *)0x40041160))
+#define CAN1_MSG2VAL_R (*((volatile unsigned long *)0x40041164))
+
+//*****************************************************************************
+//
+// Ethernet Controller (MAC)
+//
+//*****************************************************************************
+#define MAC_MR0_R (*((volatile unsigned long *)0x40048000))
+#define MAC_RIS_R (*((volatile unsigned long *)0x40048000))
+#define MAC_IACK_R (*((volatile unsigned long *)0x40048000))
+#define MAC_MR1_R (*((volatile unsigned long *)0x40048001))
+#define MAC_MR2_R (*((volatile unsigned long *)0x40048002))
+#define MAC_MR3_R (*((volatile unsigned long *)0x40048003))
+#define MAC_IM_R (*((volatile unsigned long *)0x40048004))
+#define MAC_MR4_R (*((volatile unsigned long *)0x40048004))
+#define MAC_MR5_R (*((volatile unsigned long *)0x40048005))
+#define MAC_MR6_R (*((volatile unsigned long *)0x40048006))
+#define MAC_RCTL_R (*((volatile unsigned long *)0x40048008))
+#define MAC_TCTL_R (*((volatile unsigned long *)0x4004800C))
+#define MAC_DATA_R (*((volatile unsigned long *)0x40048010))
+#define MAC_MR16_R (*((volatile unsigned long *)0x40048010))
+#define MAC_MR17_R (*((volatile unsigned long *)0x40048011))
+#define MAC_IA0_R (*((volatile unsigned long *)0x40048014))
+#define MAC_IA1_R (*((volatile unsigned long *)0x40048018))
+#define MAC_MR27_R (*((volatile unsigned long *)0x4004801B))
+#define MAC_THR_R (*((volatile unsigned long *)0x4004801C))
+#define MAC_MR29_R (*((volatile unsigned long *)0x4004801D))
+#define MAC_MR30_R (*((volatile unsigned long *)0x4004801E))
+#define MAC_MR31_R (*((volatile unsigned long *)0x4004801F))
+#define MAC_MCTL_R (*((volatile unsigned long *)0x40048020))
+#define MAC_MDV_R (*((volatile unsigned long *)0x40048024))
+#define MAC_MTXD_R (*((volatile unsigned long *)0x4004802C))
+#define MAC_MRXD_R (*((volatile unsigned long *)0x40048030))
+#define MAC_NP_R (*((volatile unsigned long *)0x40048034))
+#define MAC_TR_R (*((volatile unsigned long *)0x40048038))
+#define MAC_LED_R (*((volatile unsigned long *)0x40048040))
+#define MAC_MDIX_R (*((volatile unsigned long *)0x40048044))
+
+//*****************************************************************************
+//
+// Universal Serial Bus (USB0) Controller
+//
+//*****************************************************************************
+#define USB0_FADDR_R (*((volatile unsigned long *)0x40050000))
+#define USB0_POWER_R (*((volatile unsigned long *)0x40050001))
+#define USB0_TXIS_R (*((volatile unsigned long *)0x40050002))
+#define USB0_RXIS_R (*((volatile unsigned long *)0x40050004))
+#define USB0_TXIE_R (*((volatile unsigned long *)0x40050006))
+#define USB0_RXIE_R (*((volatile unsigned long *)0x40050008))
+#define USB0_IS_R (*((volatile unsigned long *)0x4005000A))
+#define USB0_IE_R (*((volatile unsigned long *)0x4005000B))
+#define USB0_FRAME_R (*((volatile unsigned long *)0x4005000C))
+#define USB0_EPIDX_R (*((volatile unsigned long *)0x4005000E))
+#define USB0_TEST_R (*((volatile unsigned long *)0x4005000F))
+#define USB0_FIFO0_R (*((volatile unsigned long *)0x40050020))
+#define USB0_FIFO1_R (*((volatile unsigned long *)0x40050024))
+#define USB0_FIFO2_R (*((volatile unsigned long *)0x40050028))
+#define USB0_FIFO3_R (*((volatile unsigned long *)0x4005002C))
+#define USB0_FIFO4_R (*((volatile unsigned long *)0x40050030))
+#define USB0_FIFO5_R (*((volatile unsigned long *)0x40050034))
+#define USB0_FIFO6_R (*((volatile unsigned long *)0x40050038))
+#define USB0_FIFO7_R (*((volatile unsigned long *)0x4005003C))
+#define USB0_FIFO8_R (*((volatile unsigned long *)0x40050040))
+#define USB0_FIFO9_R (*((volatile unsigned long *)0x40050044))
+#define USB0_FIFO10_R (*((volatile unsigned long *)0x40050048))
+#define USB0_FIFO11_R (*((volatile unsigned long *)0x4005004C))
+#define USB0_FIFO12_R (*((volatile unsigned long *)0x40050050))
+#define USB0_FIFO13_R (*((volatile unsigned long *)0x40050054))
+#define USB0_FIFO14_R (*((volatile unsigned long *)0x40050058))
+#define USB0_FIFO15_R (*((volatile unsigned long *)0x4005005C))
+#define USB0_DEVCTL_R (*((volatile unsigned long *)0x40050060))
+#define USB0_TXFIFOSZ_R (*((volatile unsigned long *)0x40050062))
+#define USB0_RXFIFOSZ_R (*((volatile unsigned long *)0x40050063))
+#define USB0_TXFIFOADD_R (*((volatile unsigned long *)0x40050064))
+#define USB0_RXFIFOADD_R (*((volatile unsigned long *)0x40050066))
+#define USB0_CONTIM_R (*((volatile unsigned long *)0x4005007A))
+#define USB0_VPLEN_R (*((volatile unsigned long *)0x4005007B))
+#define USB0_FSEOF_R (*((volatile unsigned long *)0x4005007D))
+#define USB0_LSEOF_R (*((volatile unsigned long *)0x4005007E))
+#define USB0_TXFUNCADDR0_R (*((volatile unsigned long *)0x40050080))
+#define USB0_TXHUBADDR0_R (*((volatile unsigned long *)0x40050082))
+#define USB0_TXHUBPORT0_R (*((volatile unsigned long *)0x40050083))
+#define USB0_TXFUNCADDR1_R (*((volatile unsigned long *)0x40050088))
+#define USB0_TXHUBADDR1_R (*((volatile unsigned long *)0x4005008A))
+#define USB0_TXHUBPORT1_R (*((volatile unsigned long *)0x4005008B))
+#define USB0_RXFUNCADDR1_R (*((volatile unsigned long *)0x4005008C))
+#define USB0_RXHUBADDR1_R (*((volatile unsigned long *)0x4005008E))
+#define USB0_RXHUBPORT1_R (*((volatile unsigned long *)0x4005008F))
+#define USB0_TXFUNCADDR2_R (*((volatile unsigned long *)0x40050090))
+#define USB0_TXHUBADDR2_R (*((volatile unsigned long *)0x40050092))
+#define USB0_TXHUBPORT2_R (*((volatile unsigned long *)0x40050093))
+#define USB0_RXFUNCADDR2_R (*((volatile unsigned long *)0x40050094))
+#define USB0_RXHUBADDR2_R (*((volatile unsigned long *)0x40050096))
+#define USB0_RXHUBPORT2_R (*((volatile unsigned long *)0x40050097))
+#define USB0_TXFUNCADDR3_R (*((volatile unsigned long *)0x40050098))
+#define USB0_TXHUBADDR3_R (*((volatile unsigned long *)0x4005009A))
+#define USB0_TXHUBPORT3_R (*((volatile unsigned long *)0x4005009B))
+#define USB0_RXFUNCADDR3_R (*((volatile unsigned long *)0x4005009C))
+#define USB0_RXHUBADDR3_R (*((volatile unsigned long *)0x4005009E))
+#define USB0_RXHUBPORT3_R (*((volatile unsigned long *)0x4005009F))
+#define USB0_TXFUNCADDR4_R (*((volatile unsigned long *)0x400500A0))
+#define USB0_TXHUBADDR4_R (*((volatile unsigned long *)0x400500A2))
+#define USB0_TXHUBPORT4_R (*((volatile unsigned long *)0x400500A3))
+#define USB0_RXFUNCADDR4_R (*((volatile unsigned long *)0x400500A4))
+#define USB0_RXHUBADDR4_R (*((volatile unsigned long *)0x400500A6))
+#define USB0_RXHUBPORT4_R (*((volatile unsigned long *)0x400500A7))
+#define USB0_TXFUNCADDR5_R (*((volatile unsigned long *)0x400500A8))
+#define USB0_TXHUBADDR5_R (*((volatile unsigned long *)0x400500AA))
+#define USB0_TXHUBPORT5_R (*((volatile unsigned long *)0x400500AB))
+#define USB0_RXFUNCADDR5_R (*((volatile unsigned long *)0x400500AC))
+#define USB0_RXHUBADDR5_R (*((volatile unsigned long *)0x400500AE))
+#define USB0_RXHUBPORT5_R (*((volatile unsigned long *)0x400500AF))
+#define USB0_TXFUNCADDR6_R (*((volatile unsigned long *)0x400500B0))
+#define USB0_TXHUBADDR6_R (*((volatile unsigned long *)0x400500B2))
+#define USB0_TXHUBPORT6_R (*((volatile unsigned long *)0x400500B3))
+#define USB0_RXFUNCADDR6_R (*((volatile unsigned long *)0x400500B4))
+#define USB0_RXHUBADDR6_R (*((volatile unsigned long *)0x400500B6))
+#define USB0_RXHUBPORT6_R (*((volatile unsigned long *)0x400500B7))
+#define USB0_TXFUNCADDR7_R (*((volatile unsigned long *)0x400500B8))
+#define USB0_TXHUBADDR7_R (*((volatile unsigned long *)0x400500BA))
+#define USB0_TXHUBPORT7_R (*((volatile unsigned long *)0x400500BB))
+#define USB0_RXFUNCADDR7_R (*((volatile unsigned long *)0x400500BC))
+#define USB0_RXHUBADDR7_R (*((volatile unsigned long *)0x400500BE))
+#define USB0_RXHUBPORT7_R (*((volatile unsigned long *)0x400500BF))
+#define USB0_TXFUNCADDR8_R (*((volatile unsigned long *)0x400500C0))
+#define USB0_TXHUBADDR8_R (*((volatile unsigned long *)0x400500C2))
+#define USB0_TXHUBPORT8_R (*((volatile unsigned long *)0x400500C3))
+#define USB0_RXFUNCADDR8_R (*((volatile unsigned long *)0x400500C4))
+#define USB0_RXHUBADDR8_R (*((volatile unsigned long *)0x400500C6))
+#define USB0_RXHUBPORT8_R (*((volatile unsigned long *)0x400500C7))
+#define USB0_TXFUNCADDR9_R (*((volatile unsigned long *)0x400500C8))
+#define USB0_TXHUBADDR9_R (*((volatile unsigned long *)0x400500CA))
+#define USB0_TXHUBPORT9_R (*((volatile unsigned long *)0x400500CB))
+#define USB0_RXFUNCADDR9_R (*((volatile unsigned long *)0x400500CC))
+#define USB0_RXHUBADDR9_R (*((volatile unsigned long *)0x400500CE))
+#define USB0_RXHUBPORT9_R (*((volatile unsigned long *)0x400500CF))
+#define USB0_TXFUNCADDR10_R (*((volatile unsigned long *)0x400500D0))
+#define USB0_TXHUBADDR10_R (*((volatile unsigned long *)0x400500D2))
+#define USB0_TXHUBPORT10_R (*((volatile unsigned long *)0x400500D3))
+#define USB0_RXFUNCADDR10_R (*((volatile unsigned long *)0x400500D4))
+#define USB0_RXHUBADDR10_R (*((volatile unsigned long *)0x400500D6))
+#define USB0_RXHUBPORT10_R (*((volatile unsigned long *)0x400500D7))
+#define USB0_TXFUNCADDR11_R (*((volatile unsigned long *)0x400500D8))
+#define USB0_TXHUBADDR11_R (*((volatile unsigned long *)0x400500DA))
+#define USB0_TXHUBPORT11_R (*((volatile unsigned long *)0x400500DB))
+#define USB0_RXFUNCADDR11_R (*((volatile unsigned long *)0x400500DC))
+#define USB0_RXHUBADDR11_R (*((volatile unsigned long *)0x400500DE))
+#define USB0_RXHUBPORT11_R (*((volatile unsigned long *)0x400500DF))
+#define USB0_TXFUNCADDR12_R (*((volatile unsigned long *)0x400500E0))
+#define USB0_TXHUBADDR12_R (*((volatile unsigned long *)0x400500E2))
+#define USB0_TXHUBPORT12_R (*((volatile unsigned long *)0x400500E3))
+#define USB0_RXFUNCADDR12_R (*((volatile unsigned long *)0x400500E4))
+#define USB0_RXHUBADDR12_R (*((volatile unsigned long *)0x400500E6))
+#define USB0_RXHUBPORT12_R (*((volatile unsigned long *)0x400500E7))
+#define USB0_TXFUNCADDR13_R (*((volatile unsigned long *)0x400500E8))
+#define USB0_TXHUBADDR13_R (*((volatile unsigned long *)0x400500EA))
+#define USB0_TXHUBPORT13_R (*((volatile unsigned long *)0x400500EB))
+#define USB0_RXFUNCADDR13_R (*((volatile unsigned long *)0x400500EC))
+#define USB0_RXHUBADDR13_R (*((volatile unsigned long *)0x400500EE))
+#define USB0_RXHUBPORT13_R (*((volatile unsigned long *)0x400500EF))
+#define USB0_TXFUNCADDR14_R (*((volatile unsigned long *)0x400500F0))
+#define USB0_TXHUBADDR14_R (*((volatile unsigned long *)0x400500F2))
+#define USB0_TXHUBPORT14_R (*((volatile unsigned long *)0x400500F3))
+#define USB0_RXFUNCADDR14_R (*((volatile unsigned long *)0x400500F4))
+#define USB0_RXHUBADDR14_R (*((volatile unsigned long *)0x400500F6))
+#define USB0_RXHUBPORT14_R (*((volatile unsigned long *)0x400500F7))
+#define USB0_TXFUNCADDR15_R (*((volatile unsigned long *)0x400500F8))
+#define USB0_TXHUBADDR15_R (*((volatile unsigned long *)0x400500FA))
+#define USB0_TXHUBPORT15_R (*((volatile unsigned long *)0x400500FB))
+#define USB0_RXFUNCADDR15_R (*((volatile unsigned long *)0x400500FC))
+#define USB0_RXHUBADDR15_R (*((volatile unsigned long *)0x400500FE))
+#define USB0_RXHUBPORT15_R (*((volatile unsigned long *)0x400500FF))
+#define USB0_CSRL0_R (*((volatile unsigned long *)0x40050102))
+#define USB0_CSRH0_R (*((volatile unsigned long *)0x40050103))
+#define USB0_COUNT0_R (*((volatile unsigned long *)0x40050108))
+#define USB0_TYPE0_R (*((volatile unsigned long *)0x4005010A))
+#define USB0_NAKLMT_R (*((volatile unsigned long *)0x4005010B))
+#define USB0_TXMAXP1_R (*((volatile unsigned long *)0x40050110))
+#define USB0_TXCSRL1_R (*((volatile unsigned long *)0x40050112))
+#define USB0_TXCSRH1_R (*((volatile unsigned long *)0x40050113))
+#define USB0_RXMAXP1_R (*((volatile unsigned long *)0x40050114))
+#define USB0_RXCSRL1_R (*((volatile unsigned long *)0x40050116))
+#define USB0_RXCSRH1_R (*((volatile unsigned long *)0x40050117))
+#define USB0_RXCOUNT1_R (*((volatile unsigned long *)0x40050118))
+#define USB0_TXTYPE1_R (*((volatile unsigned long *)0x4005011A))
+#define USB0_TXINTERVAL1_R (*((volatile unsigned long *)0x4005011B))
+#define USB0_RXTYPE1_R (*((volatile unsigned long *)0x4005011C))
+#define USB0_RXINTERVAL1_R (*((volatile unsigned long *)0x4005011D))
+#define USB0_TXMAXP2_R (*((volatile unsigned long *)0x40050120))
+#define USB0_TXCSRL2_R (*((volatile unsigned long *)0x40050122))
+#define USB0_TXCSRH2_R (*((volatile unsigned long *)0x40050123))
+#define USB0_RXMAXP2_R (*((volatile unsigned long *)0x40050124))
+#define USB0_RXCSRL2_R (*((volatile unsigned long *)0x40050126))
+#define USB0_RXCSRH2_R (*((volatile unsigned long *)0x40050127))
+#define USB0_RXCOUNT2_R (*((volatile unsigned long *)0x40050128))
+#define USB0_TXTYPE2_R (*((volatile unsigned long *)0x4005012A))
+#define USB0_TXINTERVAL2_R (*((volatile unsigned long *)0x4005012B))
+#define USB0_RXTYPE2_R (*((volatile unsigned long *)0x4005012C))
+#define USB0_RXINTERVAL2_R (*((volatile unsigned long *)0x4005012D))
+#define USB0_TXMAXP3_R (*((volatile unsigned long *)0x40050130))
+#define USB0_TXCSRL3_R (*((volatile unsigned long *)0x40050132))
+#define USB0_TXCSRH3_R (*((volatile unsigned long *)0x40050133))
+#define USB0_RXMAXP3_R (*((volatile unsigned long *)0x40050134))
+#define USB0_RXCSRL3_R (*((volatile unsigned long *)0x40050136))
+#define USB0_RXCSRH3_R (*((volatile unsigned long *)0x40050137))
+#define USB0_RXCOUNT3_R (*((volatile unsigned long *)0x40050138))
+#define USB0_TXTYPE3_R (*((volatile unsigned long *)0x4005013A))
+#define USB0_TXINTERVAL3_R (*((volatile unsigned long *)0x4005013B))
+#define USB0_RXTYPE3_R (*((volatile unsigned long *)0x4005013C))
+#define USB0_RXINTERVAL3_R (*((volatile unsigned long *)0x4005013D))
+#define USB0_TXMAXP4_R (*((volatile unsigned long *)0x40050140))
+#define USB0_TXCSRL4_R (*((volatile unsigned long *)0x40050142))
+#define USB0_TXCSRH4_R (*((volatile unsigned long *)0x40050143))
+#define USB0_RXMAXP4_R (*((volatile unsigned long *)0x40050144))
+#define USB0_RXCSRL4_R (*((volatile unsigned long *)0x40050146))
+#define USB0_RXCSRH4_R (*((volatile unsigned long *)0x40050147))
+#define USB0_RXCOUNT4_R (*((volatile unsigned long *)0x40050148))
+#define USB0_TXTYPE4_R (*((volatile unsigned long *)0x4005014A))
+#define USB0_TXINTERVAL4_R (*((volatile unsigned long *)0x4005014B))
+#define USB0_RXTYPE4_R (*((volatile unsigned long *)0x4005014C))
+#define USB0_RXINTERVAL4_R (*((volatile unsigned long *)0x4005014D))
+#define USB0_TXMAXP5_R (*((volatile unsigned long *)0x40050150))
+#define USB0_TXCSRL5_R (*((volatile unsigned long *)0x40050152))
+#define USB0_TXCSRH5_R (*((volatile unsigned long *)0x40050153))
+#define USB0_RXMAXP5_R (*((volatile unsigned long *)0x40050154))
+#define USB0_RXCSRL5_R (*((volatile unsigned long *)0x40050156))
+#define USB0_RXCSRH5_R (*((volatile unsigned long *)0x40050157))
+#define USB0_RXCOUNT5_R (*((volatile unsigned long *)0x40050158))
+#define USB0_TXTYPE5_R (*((volatile unsigned long *)0x4005015A))
+#define USB0_TXINTERVAL5_R (*((volatile unsigned long *)0x4005015B))
+#define USB0_RXTYPE5_R (*((volatile unsigned long *)0x4005015C))
+#define USB0_RXINTERVAL5_R (*((volatile unsigned long *)0x4005015D))
+#define USB0_TXMAXP6_R (*((volatile unsigned long *)0x40050160))
+#define USB0_TXCSRL6_R (*((volatile unsigned long *)0x40050162))
+#define USB0_TXCSRH6_R (*((volatile unsigned long *)0x40050163))
+#define USB0_RXMAXP6_R (*((volatile unsigned long *)0x40050164))
+#define USB0_RXCSRL6_R (*((volatile unsigned long *)0x40050166))
+#define USB0_RXCSRH6_R (*((volatile unsigned long *)0x40050167))
+#define USB0_RXCOUNT6_R (*((volatile unsigned long *)0x40050168))
+#define USB0_TXTYPE6_R (*((volatile unsigned long *)0x4005016A))
+#define USB0_TXINTERVAL6_R (*((volatile unsigned long *)0x4005016B))
+#define USB0_RXTYPE6_R (*((volatile unsigned long *)0x4005016C))
+#define USB0_RXINTERVAL6_R (*((volatile unsigned long *)0x4005016D))
+#define USB0_TXMAXP7_R (*((volatile unsigned long *)0x40050170))
+#define USB0_TXCSRL7_R (*((volatile unsigned long *)0x40050172))
+#define USB0_TXCSRH7_R (*((volatile unsigned long *)0x40050173))
+#define USB0_RXMAXP7_R (*((volatile unsigned long *)0x40050174))
+#define USB0_RXCSRL7_R (*((volatile unsigned long *)0x40050176))
+#define USB0_RXCSRH7_R (*((volatile unsigned long *)0x40050177))
+#define USB0_RXCOUNT7_R (*((volatile unsigned long *)0x40050178))
+#define USB0_TXTYPE7_R (*((volatile unsigned long *)0x4005017A))
+#define USB0_TXINTERVAL7_R (*((volatile unsigned long *)0x4005017B))
+#define USB0_RXTYPE7_R (*((volatile unsigned long *)0x4005017C))
+#define USB0_RXINTERVAL7_R (*((volatile unsigned long *)0x4005017D))
+#define USB0_TXMAXP8_R (*((volatile unsigned long *)0x40050180))
+#define USB0_TXCSRL8_R (*((volatile unsigned long *)0x40050182))
+#define USB0_TXCSRH8_R (*((volatile unsigned long *)0x40050183))
+#define USB0_RXMAXP8_R (*((volatile unsigned long *)0x40050184))
+#define USB0_RXCSRL8_R (*((volatile unsigned long *)0x40050186))
+#define USB0_RXCSRH8_R (*((volatile unsigned long *)0x40050187))
+#define USB0_RXCOUNT8_R (*((volatile unsigned long *)0x40050188))
+#define USB0_TXTYPE8_R (*((volatile unsigned long *)0x4005018A))
+#define USB0_TXINTERVAL8_R (*((volatile unsigned long *)0x4005018B))
+#define USB0_RXTYPE8_R (*((volatile unsigned long *)0x4005018C))
+#define USB0_RXINTERVAL8_R (*((volatile unsigned long *)0x4005018D))
+#define USB0_TXMAXP9_R (*((volatile unsigned long *)0x40050190))
+#define USB0_TXCSRL9_R (*((volatile unsigned long *)0x40050192))
+#define USB0_TXCSRH9_R (*((volatile unsigned long *)0x40050193))
+#define USB0_RXMAXP9_R (*((volatile unsigned long *)0x40050194))
+#define USB0_RXCSRL9_R (*((volatile unsigned long *)0x40050196))
+#define USB0_RXCSRH9_R (*((volatile unsigned long *)0x40050197))
+#define USB0_RXCOUNT9_R (*((volatile unsigned long *)0x40050198))
+#define USB0_TXTYPE9_R (*((volatile unsigned long *)0x4005019A))
+#define USB0_TXINTERVAL9_R (*((volatile unsigned long *)0x4005019B))
+#define USB0_RXTYPE9_R (*((volatile unsigned long *)0x4005019C))
+#define USB0_RXINTERVAL9_R (*((volatile unsigned long *)0x4005019D))
+#define USB0_TXMAXP10_R (*((volatile unsigned long *)0x400501A0))
+#define USB0_TXCSRL10_R (*((volatile unsigned long *)0x400501A2))
+#define USB0_TXCSRH10_R (*((volatile unsigned long *)0x400501A3))
+#define USB0_RXMAXP10_R (*((volatile unsigned long *)0x400501A4))
+#define USB0_RXCSRL10_R (*((volatile unsigned long *)0x400501A6))
+#define USB0_RXCSRH10_R (*((volatile unsigned long *)0x400501A7))
+#define USB0_RXCOUNT10_R (*((volatile unsigned long *)0x400501A8))
+#define USB0_TXTYPE10_R (*((volatile unsigned long *)0x400501AA))
+#define USB0_TXINTERVAL10_R (*((volatile unsigned long *)0x400501AB))
+#define USB0_RXTYPE10_R (*((volatile unsigned long *)0x400501AC))
+#define USB0_RXINTERVAL10_R (*((volatile unsigned long *)0x400501AD))
+#define USB0_TXMAXP11_R (*((volatile unsigned long *)0x400501B0))
+#define USB0_TXCSRL11_R (*((volatile unsigned long *)0x400501B2))
+#define USB0_TXCSRH11_R (*((volatile unsigned long *)0x400501B3))
+#define USB0_RXMAXP11_R (*((volatile unsigned long *)0x400501B4))
+#define USB0_RXCSRL11_R (*((volatile unsigned long *)0x400501B6))
+#define USB0_RXCSRH11_R (*((volatile unsigned long *)0x400501B7))
+#define USB0_RXCOUNT11_R (*((volatile unsigned long *)0x400501B8))
+#define USB0_TXTYPE11_R (*((volatile unsigned long *)0x400501BA))
+#define USB0_TXINTERVAL11_R (*((volatile unsigned long *)0x400501BB))
+#define USB0_RXTYPE11_R (*((volatile unsigned long *)0x400501BC))
+#define USB0_RXINTERVAL11_R (*((volatile unsigned long *)0x400501BD))
+#define USB0_TXMAXP12_R (*((volatile unsigned long *)0x400501C0))
+#define USB0_TXCSRL12_R (*((volatile unsigned long *)0x400501C2))
+#define USB0_TXCSRH12_R (*((volatile unsigned long *)0x400501C3))
+#define USB0_RXMAXP12_R (*((volatile unsigned long *)0x400501C4))
+#define USB0_RXCSRL12_R (*((volatile unsigned long *)0x400501C6))
+#define USB0_RXCSRH12_R (*((volatile unsigned long *)0x400501C7))
+#define USB0_RXCOUNT12_R (*((volatile unsigned long *)0x400501C8))
+#define USB0_TXTYPE12_R (*((volatile unsigned long *)0x400501CA))
+#define USB0_TXINTERVAL12_R (*((volatile unsigned long *)0x400501CB))
+#define USB0_RXTYPE12_R (*((volatile unsigned long *)0x400501CC))
+#define USB0_RXINTERVAL12_R (*((volatile unsigned long *)0x400501CD))
+#define USB0_TXMAXP13_R (*((volatile unsigned long *)0x400501D0))
+#define USB0_TXCSRL13_R (*((volatile unsigned long *)0x400501D2))
+#define USB0_TXCSRH13_R (*((volatile unsigned long *)0x400501D3))
+#define USB0_RXMAXP13_R (*((volatile unsigned long *)0x400501D4))
+#define USB0_RXCSRL13_R (*((volatile unsigned long *)0x400501D6))
+#define USB0_RXCSRH13_R (*((volatile unsigned long *)0x400501D7))
+#define USB0_RXCOUNT13_R (*((volatile unsigned long *)0x400501D8))
+#define USB0_TXTYPE13_R (*((volatile unsigned long *)0x400501DA))
+#define USB0_TXINTERVAL13_R (*((volatile unsigned long *)0x400501DB))
+#define USB0_RXTYPE13_R (*((volatile unsigned long *)0x400501DC))
+#define USB0_RXINTERVAL13_R (*((volatile unsigned long *)0x400501DD))
+#define USB0_TXMAXP14_R (*((volatile unsigned long *)0x400501E0))
+#define USB0_TXCSRL14_R (*((volatile unsigned long *)0x400501E2))
+#define USB0_TXCSRH14_R (*((volatile unsigned long *)0x400501E3))
+#define USB0_RXMAXP14_R (*((volatile unsigned long *)0x400501E4))
+#define USB0_RXCSRL14_R (*((volatile unsigned long *)0x400501E6))
+#define USB0_RXCSRH14_R (*((volatile unsigned long *)0x400501E7))
+#define USB0_RXCOUNT14_R (*((volatile unsigned long *)0x400501E8))
+#define USB0_TXTYPE14_R (*((volatile unsigned long *)0x400501EA))
+#define USB0_TXINTERVAL14_R (*((volatile unsigned long *)0x400501EB))
+#define USB0_RXTYPE14_R (*((volatile unsigned long *)0x400501EC))
+#define USB0_RXINTERVAL14_R (*((volatile unsigned long *)0x400501ED))
+#define USB0_TXMAXP15_R (*((volatile unsigned long *)0x400501F0))
+#define USB0_TXCSRL15_R (*((volatile unsigned long *)0x400501F2))
+#define USB0_TXCSRH15_R (*((volatile unsigned long *)0x400501F3))
+#define USB0_RXMAXP15_R (*((volatile unsigned long *)0x400501F4))
+#define USB0_RXCSRL15_R (*((volatile unsigned long *)0x400501F6))
+#define USB0_RXCSRH15_R (*((volatile unsigned long *)0x400501F7))
+#define USB0_RXCOUNT15_R (*((volatile unsigned long *)0x400501F8))
+#define USB0_TXTYPE15_R (*((volatile unsigned long *)0x400501FA))
+#define USB0_TXINTERVAL15_R (*((volatile unsigned long *)0x400501FB))
+#define USB0_RXTYPE15_R (*((volatile unsigned long *)0x400501FC))
+#define USB0_RXINTERVAL15_R (*((volatile unsigned long *)0x400501FD))
+#define USB0_RQPKTCOUNT1_R (*((volatile unsigned long *)0x40050304))
+#define USB0_RQPKTCOUNT2_R (*((volatile unsigned long *)0x40050308))
+#define USB0_RQPKTCOUNT3_R (*((volatile unsigned long *)0x4005030C))
+#define USB0_RQPKTCOUNT4_R (*((volatile unsigned long *)0x40050310))
+#define USB0_RQPKTCOUNT5_R (*((volatile unsigned long *)0x40050314))
+#define USB0_RQPKTCOUNT6_R (*((volatile unsigned long *)0x40050318))
+#define USB0_RQPKTCOUNT7_R (*((volatile unsigned long *)0x4005031C))
+#define USB0_RQPKTCOUNT8_R (*((volatile unsigned long *)0x40050320))
+#define USB0_RQPKTCOUNT9_R (*((volatile unsigned long *)0x40050324))
+#define USB0_RQPKTCOUNT10_R (*((volatile unsigned long *)0x40050328))
+#define USB0_RQPKTCOUNT11_R (*((volatile unsigned long *)0x4005032C))
+#define USB0_RQPKTCOUNT12_R (*((volatile unsigned long *)0x40050330))
+#define USB0_RQPKTCOUNT13_R (*((volatile unsigned long *)0x40050334))
+#define USB0_RQPKTCOUNT14_R (*((volatile unsigned long *)0x40050338))
+#define USB0_RQPKTCOUNT15_R (*((volatile unsigned long *)0x4005033C))
+#define USB0_RXDPKTBUFDIS_R (*((volatile unsigned long *)0x40050340))
+#define USB0_TXDPKTBUFDIS_R (*((volatile unsigned long *)0x40050342))
+#define USB0_EPC_R (*((volatile unsigned long *)0x40050400))
+#define USB0_EPCRIS_R (*((volatile unsigned long *)0x40050404))
+#define USB0_EPCIM_R (*((volatile unsigned long *)0x40050408))
+#define USB0_EPCISC_R (*((volatile unsigned long *)0x4005040C))
+#define USB0_DRRIS_R (*((volatile unsigned long *)0x40050410))
+#define USB0_DRIM_R (*((volatile unsigned long *)0x40050414))
+#define USB0_DRISC_R (*((volatile unsigned long *)0x40050418))
+#define USB0_VDC_R (*((volatile unsigned long *)0x40050430))
+#define USB0_VDCRIS_R (*((volatile unsigned long *)0x40050434))
+#define USB0_VDCIM_R (*((volatile unsigned long *)0x40050438))
+#define USB0_VDCISC_R (*((volatile unsigned long *)0x4005043C))
+#define USB0_IDVRIS_R (*((volatile unsigned long *)0x40050444))
+#define USB0_IDVIM_R (*((volatile unsigned long *)0x40050448))
+#define USB0_IDVISC_R (*((volatile unsigned long *)0x4005044C))
+#define USB0_EPS_R (*((volatile unsigned long *)0x40050450))
+
+//*****************************************************************************
+//
+// Inter-Integrated Circuit Sound (I2S0) Interface
+//
+//*****************************************************************************
+#define I2S0_TXFIFO_R (*((volatile unsigned long *)0x40054000))
+#define I2S0_TXFIFOCFG_R (*((volatile unsigned long *)0x40054004))
+#define I2S0_TXCFG_R (*((volatile unsigned long *)0x40054008))
+#define I2S0_TXLIMIT_R (*((volatile unsigned long *)0x4005400C))
+#define I2S0_TXISM_R (*((volatile unsigned long *)0x40054010))
+#define I2S0_TXLEV_R (*((volatile unsigned long *)0x40054018))
+#define I2S0_RXFIFO_R (*((volatile unsigned long *)0x40054800))
+#define I2S0_RXFIFOCFG_R (*((volatile unsigned long *)0x40054804))
+#define I2S0_RXCFG_R (*((volatile unsigned long *)0x40054808))
+#define I2S0_RXLIMIT_R (*((volatile unsigned long *)0x4005480C))
+#define I2S0_RXISM_R (*((volatile unsigned long *)0x40054810))
+#define I2S0_RXLEV_R (*((volatile unsigned long *)0x40054818))
+#define I2S0_CFG_R (*((volatile unsigned long *)0x40054C00))
+#define I2S0_IM_R (*((volatile unsigned long *)0x40054C10))
+#define I2S0_RIS_R (*((volatile unsigned long *)0x40054C14))
+#define I2S0_MIS_R (*((volatile unsigned long *)0x40054C18))
+#define I2S0_IC_R (*((volatile unsigned long *)0x40054C1C))
+
+//*****************************************************************************
+//
+// General-Purpose Input/Outputs (AHB)
+//
+//*****************************************************************************
+#define GPIO_PORTA_AHB_DATA_BITS_R \
+ ((volatile unsigned long *)0x40058000)
+#define GPIO_PORTA_AHB_DATA_R (*((volatile unsigned long *)0x400583FC))
+#define GPIO_PORTA_AHB_DIR_R (*((volatile unsigned long *)0x40058400))
+#define GPIO_PORTA_AHB_IS_R (*((volatile unsigned long *)0x40058404))
+#define GPIO_PORTA_AHB_IBE_R (*((volatile unsigned long *)0x40058408))
+#define GPIO_PORTA_AHB_IEV_R (*((volatile unsigned long *)0x4005840C))
+#define GPIO_PORTA_AHB_IM_R (*((volatile unsigned long *)0x40058410))
+#define GPIO_PORTA_AHB_RIS_R (*((volatile unsigned long *)0x40058414))
+#define GPIO_PORTA_AHB_MIS_R (*((volatile unsigned long *)0x40058418))
+#define GPIO_PORTA_AHB_ICR_R (*((volatile unsigned long *)0x4005841C))
+#define GPIO_PORTA_AHB_AFSEL_R (*((volatile unsigned long *)0x40058420))
+#define GPIO_PORTA_AHB_DR2R_R (*((volatile unsigned long *)0x40058500))
+#define GPIO_PORTA_AHB_DR4R_R (*((volatile unsigned long *)0x40058504))
+#define GPIO_PORTA_AHB_DR8R_R (*((volatile unsigned long *)0x40058508))
+#define GPIO_PORTA_AHB_ODR_R (*((volatile unsigned long *)0x4005850C))
+#define GPIO_PORTA_AHB_PUR_R (*((volatile unsigned long *)0x40058510))
+#define GPIO_PORTA_AHB_PDR_R (*((volatile unsigned long *)0x40058514))
+#define GPIO_PORTA_AHB_SLR_R (*((volatile unsigned long *)0x40058518))
+#define GPIO_PORTA_AHB_DEN_R (*((volatile unsigned long *)0x4005851C))
+#define GPIO_PORTA_AHB_LOCK_R (*((volatile unsigned long *)0x40058520))
+#define GPIO_PORTA_AHB_CR_R (*((volatile unsigned long *)0x40058524))
+#define GPIO_PORTA_AHB_AMSEL_R (*((volatile unsigned long *)0x40058528))
+#define GPIO_PORTA_AHB_PCTL_R (*((volatile unsigned long *)0x4005852C))
+
+//*****************************************************************************
+//
+// General-Purpose Input/Outputs (AHB)
+//
+//*****************************************************************************
+#define GPIO_PORTB_AHB_DATA_BITS_R \
+ ((volatile unsigned long *)0x40059000)
+#define GPIO_PORTB_AHB_DATA_R (*((volatile unsigned long *)0x400593FC))
+#define GPIO_PORTB_AHB_DIR_R (*((volatile unsigned long *)0x40059400))
+#define GPIO_PORTB_AHB_IS_R (*((volatile unsigned long *)0x40059404))
+#define GPIO_PORTB_AHB_IBE_R (*((volatile unsigned long *)0x40059408))
+#define GPIO_PORTB_AHB_IEV_R (*((volatile unsigned long *)0x4005940C))
+#define GPIO_PORTB_AHB_IM_R (*((volatile unsigned long *)0x40059410))
+#define GPIO_PORTB_AHB_RIS_R (*((volatile unsigned long *)0x40059414))
+#define GPIO_PORTB_AHB_MIS_R (*((volatile unsigned long *)0x40059418))
+#define GPIO_PORTB_AHB_ICR_R (*((volatile unsigned long *)0x4005941C))
+#define GPIO_PORTB_AHB_AFSEL_R (*((volatile unsigned long *)0x40059420))
+#define GPIO_PORTB_AHB_DR2R_R (*((volatile unsigned long *)0x40059500))
+#define GPIO_PORTB_AHB_DR4R_R (*((volatile unsigned long *)0x40059504))
+#define GPIO_PORTB_AHB_DR8R_R (*((volatile unsigned long *)0x40059508))
+#define GPIO_PORTB_AHB_ODR_R (*((volatile unsigned long *)0x4005950C))
+#define GPIO_PORTB_AHB_PUR_R (*((volatile unsigned long *)0x40059510))
+#define GPIO_PORTB_AHB_PDR_R (*((volatile unsigned long *)0x40059514))
+#define GPIO_PORTB_AHB_SLR_R (*((volatile unsigned long *)0x40059518))
+#define GPIO_PORTB_AHB_DEN_R (*((volatile unsigned long *)0x4005951C))
+#define GPIO_PORTB_AHB_LOCK_R (*((volatile unsigned long *)0x40059520))
+#define GPIO_PORTB_AHB_CR_R (*((volatile unsigned long *)0x40059524))
+#define GPIO_PORTB_AHB_AMSEL_R (*((volatile unsigned long *)0x40059528))
+#define GPIO_PORTB_AHB_PCTL_R (*((volatile unsigned long *)0x4005952C))
+
+//*****************************************************************************
+//
+// General-Purpose Input/Outputs (AHB)
+//
+//*****************************************************************************
+#define GPIO_PORTC_AHB_DATA_BITS_R \
+ ((volatile unsigned long *)0x4005A000)
+#define GPIO_PORTC_AHB_DATA_R (*((volatile unsigned long *)0x4005A3FC))
+#define GPIO_PORTC_AHB_DIR_R (*((volatile unsigned long *)0x4005A400))
+#define GPIO_PORTC_AHB_IS_R (*((volatile unsigned long *)0x4005A404))
+#define GPIO_PORTC_AHB_IBE_R (*((volatile unsigned long *)0x4005A408))
+#define GPIO_PORTC_AHB_IEV_R (*((volatile unsigned long *)0x4005A40C))
+#define GPIO_PORTC_AHB_IM_R (*((volatile unsigned long *)0x4005A410))
+#define GPIO_PORTC_AHB_RIS_R (*((volatile unsigned long *)0x4005A414))
+#define GPIO_PORTC_AHB_MIS_R (*((volatile unsigned long *)0x4005A418))
+#define GPIO_PORTC_AHB_ICR_R (*((volatile unsigned long *)0x4005A41C))
+#define GPIO_PORTC_AHB_AFSEL_R (*((volatile unsigned long *)0x4005A420))
+#define GPIO_PORTC_AHB_DR2R_R (*((volatile unsigned long *)0x4005A500))
+#define GPIO_PORTC_AHB_DR4R_R (*((volatile unsigned long *)0x4005A504))
+#define GPIO_PORTC_AHB_DR8R_R (*((volatile unsigned long *)0x4005A508))
+#define GPIO_PORTC_AHB_ODR_R (*((volatile unsigned long *)0x4005A50C))
+#define GPIO_PORTC_AHB_PUR_R (*((volatile unsigned long *)0x4005A510))
+#define GPIO_PORTC_AHB_PDR_R (*((volatile unsigned long *)0x4005A514))
+#define GPIO_PORTC_AHB_SLR_R (*((volatile unsigned long *)0x4005A518))
+#define GPIO_PORTC_AHB_DEN_R (*((volatile unsigned long *)0x4005A51C))
+#define GPIO_PORTC_AHB_LOCK_R (*((volatile unsigned long *)0x4005A520))
+#define GPIO_PORTC_AHB_CR_R (*((volatile unsigned long *)0x4005A524))
+#define GPIO_PORTC_AHB_AMSEL_R (*((volatile unsigned long *)0x4005A528))
+#define GPIO_PORTC_AHB_PCTL_R (*((volatile unsigned long *)0x4005A52C))
+
+//*****************************************************************************
+//
+// General-Purpose Input/Outputs (AHB)
+//
+//*****************************************************************************
+#define GPIO_PORTD_AHB_DATA_BITS_R \
+ ((volatile unsigned long *)0x4005B000)
+#define GPIO_PORTD_AHB_DATA_R (*((volatile unsigned long *)0x4005B3FC))
+#define GPIO_PORTD_AHB_DIR_R (*((volatile unsigned long *)0x4005B400))
+#define GPIO_PORTD_AHB_IS_R (*((volatile unsigned long *)0x4005B404))
+#define GPIO_PORTD_AHB_IBE_R (*((volatile unsigned long *)0x4005B408))
+#define GPIO_PORTD_AHB_IEV_R (*((volatile unsigned long *)0x4005B40C))
+#define GPIO_PORTD_AHB_IM_R (*((volatile unsigned long *)0x4005B410))
+#define GPIO_PORTD_AHB_RIS_R (*((volatile unsigned long *)0x4005B414))
+#define GPIO_PORTD_AHB_MIS_R (*((volatile unsigned long *)0x4005B418))
+#define GPIO_PORTD_AHB_ICR_R (*((volatile unsigned long *)0x4005B41C))
+#define GPIO_PORTD_AHB_AFSEL_R (*((volatile unsigned long *)0x4005B420))
+#define GPIO_PORTD_AHB_DR2R_R (*((volatile unsigned long *)0x4005B500))
+#define GPIO_PORTD_AHB_DR4R_R (*((volatile unsigned long *)0x4005B504))
+#define GPIO_PORTD_AHB_DR8R_R (*((volatile unsigned long *)0x4005B508))
+#define GPIO_PORTD_AHB_ODR_R (*((volatile unsigned long *)0x4005B50C))
+#define GPIO_PORTD_AHB_PUR_R (*((volatile unsigned long *)0x4005B510))
+#define GPIO_PORTD_AHB_PDR_R (*((volatile unsigned long *)0x4005B514))
+#define GPIO_PORTD_AHB_SLR_R (*((volatile unsigned long *)0x4005B518))
+#define GPIO_PORTD_AHB_DEN_R (*((volatile unsigned long *)0x4005B51C))
+#define GPIO_PORTD_AHB_LOCK_R (*((volatile unsigned long *)0x4005B520))
+#define GPIO_PORTD_AHB_CR_R (*((volatile unsigned long *)0x4005B524))
+#define GPIO_PORTD_AHB_AMSEL_R (*((volatile unsigned long *)0x4005B528))
+#define GPIO_PORTD_AHB_PCTL_R (*((volatile unsigned long *)0x4005B52C))
+
+//*****************************************************************************
+//
+// General-Purpose Input/Outputs (AHB)
+//
+//*****************************************************************************
+#define GPIO_PORTE_AHB_DATA_BITS_R \
+ ((volatile unsigned long *)0x4005C000)
+#define GPIO_PORTE_AHB_DATA_R (*((volatile unsigned long *)0x4005C3FC))
+#define GPIO_PORTE_AHB_DIR_R (*((volatile unsigned long *)0x4005C400))
+#define GPIO_PORTE_AHB_IS_R (*((volatile unsigned long *)0x4005C404))
+#define GPIO_PORTE_AHB_IBE_R (*((volatile unsigned long *)0x4005C408))
+#define GPIO_PORTE_AHB_IEV_R (*((volatile unsigned long *)0x4005C40C))
+#define GPIO_PORTE_AHB_IM_R (*((volatile unsigned long *)0x4005C410))
+#define GPIO_PORTE_AHB_RIS_R (*((volatile unsigned long *)0x4005C414))
+#define GPIO_PORTE_AHB_MIS_R (*((volatile unsigned long *)0x4005C418))
+#define GPIO_PORTE_AHB_ICR_R (*((volatile unsigned long *)0x4005C41C))
+#define GPIO_PORTE_AHB_AFSEL_R (*((volatile unsigned long *)0x4005C420))
+#define GPIO_PORTE_AHB_DR2R_R (*((volatile unsigned long *)0x4005C500))
+#define GPIO_PORTE_AHB_DR4R_R (*((volatile unsigned long *)0x4005C504))
+#define GPIO_PORTE_AHB_DR8R_R (*((volatile unsigned long *)0x4005C508))
+#define GPIO_PORTE_AHB_ODR_R (*((volatile unsigned long *)0x4005C50C))
+#define GPIO_PORTE_AHB_PUR_R (*((volatile unsigned long *)0x4005C510))
+#define GPIO_PORTE_AHB_PDR_R (*((volatile unsigned long *)0x4005C514))
+#define GPIO_PORTE_AHB_SLR_R (*((volatile unsigned long *)0x4005C518))
+#define GPIO_PORTE_AHB_DEN_R (*((volatile unsigned long *)0x4005C51C))
+#define GPIO_PORTE_AHB_LOCK_R (*((volatile unsigned long *)0x4005C520))
+#define GPIO_PORTE_AHB_CR_R (*((volatile unsigned long *)0x4005C524))
+#define GPIO_PORTE_AHB_AMSEL_R (*((volatile unsigned long *)0x4005C528))
+#define GPIO_PORTE_AHB_PCTL_R (*((volatile unsigned long *)0x4005C52C))
+
+//*****************************************************************************
+//
+// General-Purpose Input/Outputs (AHB)
+//
+//*****************************************************************************
+#define GPIO_PORTF_AHB_DATA_BITS_R \
+ ((volatile unsigned long *)0x4005D000)
+#define GPIO_PORTF_AHB_DATA_R (*((volatile unsigned long *)0x4005D3FC))
+#define GPIO_PORTF_AHB_DIR_R (*((volatile unsigned long *)0x4005D400))
+#define GPIO_PORTF_AHB_IS_R (*((volatile unsigned long *)0x4005D404))
+#define GPIO_PORTF_AHB_IBE_R (*((volatile unsigned long *)0x4005D408))
+#define GPIO_PORTF_AHB_IEV_R (*((volatile unsigned long *)0x4005D40C))
+#define GPIO_PORTF_AHB_IM_R (*((volatile unsigned long *)0x4005D410))
+#define GPIO_PORTF_AHB_RIS_R (*((volatile unsigned long *)0x4005D414))
+#define GPIO_PORTF_AHB_MIS_R (*((volatile unsigned long *)0x4005D418))
+#define GPIO_PORTF_AHB_ICR_R (*((volatile unsigned long *)0x4005D41C))
+#define GPIO_PORTF_AHB_AFSEL_R (*((volatile unsigned long *)0x4005D420))
+#define GPIO_PORTF_AHB_DR2R_R (*((volatile unsigned long *)0x4005D500))
+#define GPIO_PORTF_AHB_DR4R_R (*((volatile unsigned long *)0x4005D504))
+#define GPIO_PORTF_AHB_DR8R_R (*((volatile unsigned long *)0x4005D508))
+#define GPIO_PORTF_AHB_ODR_R (*((volatile unsigned long *)0x4005D50C))
+#define GPIO_PORTF_AHB_PUR_R (*((volatile unsigned long *)0x4005D510))
+#define GPIO_PORTF_AHB_PDR_R (*((volatile unsigned long *)0x4005D514))
+#define GPIO_PORTF_AHB_SLR_R (*((volatile unsigned long *)0x4005D518))
+#define GPIO_PORTF_AHB_DEN_R (*((volatile unsigned long *)0x4005D51C))
+#define GPIO_PORTF_AHB_LOCK_R (*((volatile unsigned long *)0x4005D520))
+#define GPIO_PORTF_AHB_CR_R (*((volatile unsigned long *)0x4005D524))
+#define GPIO_PORTF_AHB_AMSEL_R (*((volatile unsigned long *)0x4005D528))
+#define GPIO_PORTF_AHB_PCTL_R (*((volatile unsigned long *)0x4005D52C))
+
+//*****************************************************************************
+//
+// General-Purpose Input/Outputs (AHB)
+//
+//*****************************************************************************
+#define GPIO_PORTG_AHB_DATA_BITS_R \
+ ((volatile unsigned long *)0x4005E000)
+#define GPIO_PORTG_AHB_DATA_R (*((volatile unsigned long *)0x4005E3FC))
+#define GPIO_PORTG_AHB_DIR_R (*((volatile unsigned long *)0x4005E400))
+#define GPIO_PORTG_AHB_IS_R (*((volatile unsigned long *)0x4005E404))
+#define GPIO_PORTG_AHB_IBE_R (*((volatile unsigned long *)0x4005E408))
+#define GPIO_PORTG_AHB_IEV_R (*((volatile unsigned long *)0x4005E40C))
+#define GPIO_PORTG_AHB_IM_R (*((volatile unsigned long *)0x4005E410))
+#define GPIO_PORTG_AHB_RIS_R (*((volatile unsigned long *)0x4005E414))
+#define GPIO_PORTG_AHB_MIS_R (*((volatile unsigned long *)0x4005E418))
+#define GPIO_PORTG_AHB_ICR_R (*((volatile unsigned long *)0x4005E41C))
+#define GPIO_PORTG_AHB_AFSEL_R (*((volatile unsigned long *)0x4005E420))
+#define GPIO_PORTG_AHB_DR2R_R (*((volatile unsigned long *)0x4005E500))
+#define GPIO_PORTG_AHB_DR4R_R (*((volatile unsigned long *)0x4005E504))
+#define GPIO_PORTG_AHB_DR8R_R (*((volatile unsigned long *)0x4005E508))
+#define GPIO_PORTG_AHB_ODR_R (*((volatile unsigned long *)0x4005E50C))
+#define GPIO_PORTG_AHB_PUR_R (*((volatile unsigned long *)0x4005E510))
+#define GPIO_PORTG_AHB_PDR_R (*((volatile unsigned long *)0x4005E514))
+#define GPIO_PORTG_AHB_SLR_R (*((volatile unsigned long *)0x4005E518))
+#define GPIO_PORTG_AHB_DEN_R (*((volatile unsigned long *)0x4005E51C))
+#define GPIO_PORTG_AHB_LOCK_R (*((volatile unsigned long *)0x4005E520))
+#define GPIO_PORTG_AHB_CR_R (*((volatile unsigned long *)0x4005E524))
+#define GPIO_PORTG_AHB_AMSEL_R (*((volatile unsigned long *)0x4005E528))
+#define GPIO_PORTG_AHB_PCTL_R (*((volatile unsigned long *)0x4005E52C))
+
+//*****************************************************************************
+//
+// General-Purpose Input/Outputs (AHB)
+//
+//*****************************************************************************
+#define GPIO_PORTH_AHB_DATA_BITS_R \
+ ((volatile unsigned long *)0x4005F000)
+#define GPIO_PORTH_AHB_DATA_R (*((volatile unsigned long *)0x4005F3FC))
+#define GPIO_PORTH_AHB_DIR_R (*((volatile unsigned long *)0x4005F400))
+#define GPIO_PORTH_AHB_IS_R (*((volatile unsigned long *)0x4005F404))
+#define GPIO_PORTH_AHB_IBE_R (*((volatile unsigned long *)0x4005F408))
+#define GPIO_PORTH_AHB_IEV_R (*((volatile unsigned long *)0x4005F40C))
+#define GPIO_PORTH_AHB_IM_R (*((volatile unsigned long *)0x4005F410))
+#define GPIO_PORTH_AHB_RIS_R (*((volatile unsigned long *)0x4005F414))
+#define GPIO_PORTH_AHB_MIS_R (*((volatile unsigned long *)0x4005F418))
+#define GPIO_PORTH_AHB_ICR_R (*((volatile unsigned long *)0x4005F41C))
+#define GPIO_PORTH_AHB_AFSEL_R (*((volatile unsigned long *)0x4005F420))
+#define GPIO_PORTH_AHB_DR2R_R (*((volatile unsigned long *)0x4005F500))
+#define GPIO_PORTH_AHB_DR4R_R (*((volatile unsigned long *)0x4005F504))
+#define GPIO_PORTH_AHB_DR8R_R (*((volatile unsigned long *)0x4005F508))
+#define GPIO_PORTH_AHB_ODR_R (*((volatile unsigned long *)0x4005F50C))
+#define GPIO_PORTH_AHB_PUR_R (*((volatile unsigned long *)0x4005F510))
+#define GPIO_PORTH_AHB_PDR_R (*((volatile unsigned long *)0x4005F514))
+#define GPIO_PORTH_AHB_SLR_R (*((volatile unsigned long *)0x4005F518))
+#define GPIO_PORTH_AHB_DEN_R (*((volatile unsigned long *)0x4005F51C))
+#define GPIO_PORTH_AHB_LOCK_R (*((volatile unsigned long *)0x4005F520))
+#define GPIO_PORTH_AHB_CR_R (*((volatile unsigned long *)0x4005F524))
+#define GPIO_PORTH_AHB_AMSEL_R (*((volatile unsigned long *)0x4005F528))
+#define GPIO_PORTH_AHB_PCTL_R (*((volatile unsigned long *)0x4005F52C))
+
+//*****************************************************************************
+//
+// General-Purpose Input/Outputs (AHB)
+//
+//*****************************************************************************
+#define GPIO_PORTJ_AHB_DATA_BITS_R \
+ ((volatile unsigned long *)0x40060000)
+#define GPIO_PORTJ_AHB_DATA_R (*((volatile unsigned long *)0x400603FC))
+#define GPIO_PORTJ_AHB_DIR_R (*((volatile unsigned long *)0x40060400))
+#define GPIO_PORTJ_AHB_IS_R (*((volatile unsigned long *)0x40060404))
+#define GPIO_PORTJ_AHB_IBE_R (*((volatile unsigned long *)0x40060408))
+#define GPIO_PORTJ_AHB_IEV_R (*((volatile unsigned long *)0x4006040C))
+#define GPIO_PORTJ_AHB_IM_R (*((volatile unsigned long *)0x40060410))
+#define GPIO_PORTJ_AHB_RIS_R (*((volatile unsigned long *)0x40060414))
+#define GPIO_PORTJ_AHB_MIS_R (*((volatile unsigned long *)0x40060418))
+#define GPIO_PORTJ_AHB_ICR_R (*((volatile unsigned long *)0x4006041C))
+#define GPIO_PORTJ_AHB_AFSEL_R (*((volatile unsigned long *)0x40060420))
+#define GPIO_PORTJ_AHB_DR2R_R (*((volatile unsigned long *)0x40060500))
+#define GPIO_PORTJ_AHB_DR4R_R (*((volatile unsigned long *)0x40060504))
+#define GPIO_PORTJ_AHB_DR8R_R (*((volatile unsigned long *)0x40060508))
+#define GPIO_PORTJ_AHB_ODR_R (*((volatile unsigned long *)0x4006050C))
+#define GPIO_PORTJ_AHB_PUR_R (*((volatile unsigned long *)0x40060510))
+#define GPIO_PORTJ_AHB_PDR_R (*((volatile unsigned long *)0x40060514))
+#define GPIO_PORTJ_AHB_SLR_R (*((volatile unsigned long *)0x40060518))
+#define GPIO_PORTJ_AHB_DEN_R (*((volatile unsigned long *)0x4006051C))
+#define GPIO_PORTJ_AHB_LOCK_R (*((volatile unsigned long *)0x40060520))
+#define GPIO_PORTJ_AHB_CR_R (*((volatile unsigned long *)0x40060524))
+#define GPIO_PORTJ_AHB_AMSEL_R (*((volatile unsigned long *)0x40060528))
+#define GPIO_PORTJ_AHB_PCTL_R (*((volatile unsigned long *)0x4006052C))
+
+//*****************************************************************************
+//
+// External Peripheral Interface (EPI0)
+//
+//*****************************************************************************
+#define EPI0_CFG_R (*((volatile unsigned long *)0x400D0000))
+#define EPI0_BAUD_R (*((volatile unsigned long *)0x400D0004))
+#define EPI0_SDRAMCFG_R (*((volatile unsigned long *)0x400D0010))
+#define EPI0_GPCFG_R (*((volatile unsigned long *)0x400D0010))
+#define EPI0_HB8CFG_R (*((volatile unsigned long *)0x400D0010))
+#define EPI0_SDRAMCFG2_R (*((volatile unsigned long *)0x400D0014))
+#define EPI0_HB8CFG2_R (*((volatile unsigned long *)0x400D0014))
+#define EPI0_GPCFG2_R (*((volatile unsigned long *)0x400D0014))
+#define EPI0_ADDRMAP_R (*((volatile unsigned long *)0x400D001C))
+#define EPI0_RSIZE0_R (*((volatile unsigned long *)0x400D0020))
+#define EPI0_RADDR0_R (*((volatile unsigned long *)0x400D0024))
+#define EPI0_RPSTD0_R (*((volatile unsigned long *)0x400D0028))
+#define EPI0_RSIZE1_R (*((volatile unsigned long *)0x400D0030))
+#define EPI0_RADDR1_R (*((volatile unsigned long *)0x400D0034))
+#define EPI0_RPSTD1_R (*((volatile unsigned long *)0x400D0038))
+#define EPI0_STAT_R (*((volatile unsigned long *)0x400D0060))
+#define EPI0_RFIFOCNT_R (*((volatile unsigned long *)0x400D006C))
+#define EPI0_READFIFO_R (*((volatile unsigned long *)0x400D0070))
+#define EPI0_READFIFO1_R (*((volatile unsigned long *)0x400D0074))
+#define EPI0_READFIFO2_R (*((volatile unsigned long *)0x400D0078))
+#define EPI0_READFIFO3_R (*((volatile unsigned long *)0x400D007C))
+#define EPI0_READFIFO4_R (*((volatile unsigned long *)0x400D0080))
+#define EPI0_READFIFO5_R (*((volatile unsigned long *)0x400D0084))
+#define EPI0_READFIFO6_R (*((volatile unsigned long *)0x400D0088))
+#define EPI0_READFIFO7_R (*((volatile unsigned long *)0x400D008C))
+#define EPI0_FIFOLVL_R (*((volatile unsigned long *)0x400D0200))
+#define EPI0_WFIFOCNT_R (*((volatile unsigned long *)0x400D0204))
+#define EPI0_IM_R (*((volatile unsigned long *)0x400D0210))
+#define EPI0_RIS_R (*((volatile unsigned long *)0x400D0214))
+#define EPI0_MIS_R (*((volatile unsigned long *)0x400D0218))
+#define EPI0_EISC_R (*((volatile unsigned long *)0x400D021C))
+
+//*****************************************************************************
+//
+// Internal Memory (FLASH)
+//
+//*****************************************************************************
+#define FLASH_FMA_R (*((volatile unsigned long *)0x400FD000))
+#define FLASH_FMD_R (*((volatile unsigned long *)0x400FD004))
+#define FLASH_FMC_R (*((volatile unsigned long *)0x400FD008))
+#define FLASH_FCRIS_R (*((volatile unsigned long *)0x400FD00C))
+#define FLASH_FCIM_R (*((volatile unsigned long *)0x400FD010))
+#define FLASH_FCMISC_R (*((volatile unsigned long *)0x400FD014))
+#define FLASH_FMC2_R (*((volatile unsigned long *)0x400FD020))
+#define FLASH_FWBVAL_R (*((volatile unsigned long *)0x400FD030))
+#define FLASH_FWBN_R (*((volatile unsigned long *)0x400FD100))
+#define FLASH_RMCTL_R (*((volatile unsigned long *)0x400FE0F0))
+#define FLASH_RMVER_R (*((volatile unsigned long *)0x400FE0F4))
+#define FLASH_USERDBG_R (*((volatile unsigned long *)0x400FE1D0))
+#define FLASH_USERREG0_R (*((volatile unsigned long *)0x400FE1E0))
+#define FLASH_USERREG1_R (*((volatile unsigned long *)0x400FE1E4))
+#define FLASH_USERREG2_R (*((volatile unsigned long *)0x400FE1E8))
+#define FLASH_USERREG3_R (*((volatile unsigned long *)0x400FE1EC))
+#define FLASH_FMPRE0_R (*((volatile unsigned long *)0x400FE200))
+#define FLASH_FMPRE1_R (*((volatile unsigned long *)0x400FE204))
+#define FLASH_FMPRE2_R (*((volatile unsigned long *)0x400FE208))
+#define FLASH_FMPRE3_R (*((volatile unsigned long *)0x400FE20C))
+#define FLASH_FMPPE0_R (*((volatile unsigned long *)0x400FE400))
+#define FLASH_FMPPE1_R (*((volatile unsigned long *)0x400FE404))
+#define FLASH_FMPPE2_R (*((volatile unsigned long *)0x400FE408))
+#define FLASH_FMPPE3_R (*((volatile unsigned long *)0x400FE40C))
+
+//*****************************************************************************
+//
+// System Control (SYSCTL)
+//
+//*****************************************************************************
+#define SYSCTL_DID0_R (*((volatile unsigned long *)0x400FE000))
+#define SYSCTL_DID1_R (*((volatile unsigned long *)0x400FE004))
+#define SYSCTL_DC0_R (*((volatile unsigned long *)0x400FE008))
+#define SYSCTL_DC1_R (*((volatile unsigned long *)0x400FE010))
+#define SYSCTL_DC2_R (*((volatile unsigned long *)0x400FE014))
+#define SYSCTL_DC3_R (*((volatile unsigned long *)0x400FE018))
+#define SYSCTL_DC4_R (*((volatile unsigned long *)0x400FE01C))
+#define SYSCTL_DC5_R (*((volatile unsigned long *)0x400FE020))
+#define SYSCTL_DC6_R (*((volatile unsigned long *)0x400FE024))
+#define SYSCTL_DC7_R (*((volatile unsigned long *)0x400FE028))
+#define SYSCTL_DC8_R (*((volatile unsigned long *)0x400FE02C))
+#define SYSCTL_PBORCTL_R (*((volatile unsigned long *)0x400FE030))
+#define SYSCTL_SRCR0_R (*((volatile unsigned long *)0x400FE040))
+#define SYSCTL_SRCR1_R (*((volatile unsigned long *)0x400FE044))
+#define SYSCTL_SRCR2_R (*((volatile unsigned long *)0x400FE048))
+#define SYSCTL_RIS_R (*((volatile unsigned long *)0x400FE050))
+#define SYSCTL_IMC_R (*((volatile unsigned long *)0x400FE054))
+#define SYSCTL_MISC_R (*((volatile unsigned long *)0x400FE058))
+#define SYSCTL_RESC_R (*((volatile unsigned long *)0x400FE05C))
+#define SYSCTL_RCC_R (*((volatile unsigned long *)0x400FE060))
+#define SYSCTL_PLLCFG_R (*((volatile unsigned long *)0x400FE064))
+#define SYSCTL_GPIOHBCTL_R (*((volatile unsigned long *)0x400FE06C))
+#define SYSCTL_RCC2_R (*((volatile unsigned long *)0x400FE070))
+#define SYSCTL_MOSCCTL_R (*((volatile unsigned long *)0x400FE07C))
+#define SYSCTL_RCGC0_R (*((volatile unsigned long *)0x400FE100))
+#define SYSCTL_RCGC1_R (*((volatile unsigned long *)0x400FE104))
+#define SYSCTL_RCGC2_R (*((volatile unsigned long *)0x400FE108))
+#define SYSCTL_SCGC0_R (*((volatile unsigned long *)0x400FE110))
+#define SYSCTL_SCGC1_R (*((volatile unsigned long *)0x400FE114))
+#define SYSCTL_SCGC2_R (*((volatile unsigned long *)0x400FE118))
+#define SYSCTL_DCGC0_R (*((volatile unsigned long *)0x400FE120))
+#define SYSCTL_DCGC1_R (*((volatile unsigned long *)0x400FE124))
+#define SYSCTL_DCGC2_R (*((volatile unsigned long *)0x400FE128))
+#define SYSCTL_DSLPCLKCFG_R (*((volatile unsigned long *)0x400FE144))
+#define SYSCTL_DSFLASHCFG_R (*((volatile unsigned long *)0x400FE14C))
+#define SYSCTL_PIOSCCAL_R (*((volatile unsigned long *)0x400FE150))
+#define SYSCTL_I2SMCLKCFG_R (*((volatile unsigned long *)0x400FE170))
+#define SYSCTL_DC9_R (*((volatile unsigned long *)0x400FE190))
+#define SYSCTL_NVMSTAT_R (*((volatile unsigned long *)0x400FE1A0))
+
+//*****************************************************************************
+//
+// Micro Direct Memory Access (UDMA)
+//
+//*****************************************************************************
+#define UDMA_STAT_R (*((volatile unsigned long *)0x400FF000))
+#define UDMA_CFG_R (*((volatile unsigned long *)0x400FF004))
+#define UDMA_CTLBASE_R (*((volatile unsigned long *)0x400FF008))
+#define UDMA_ALTBASE_R (*((volatile unsigned long *)0x400FF00C))
+#define UDMA_WAITSTAT_R (*((volatile unsigned long *)0x400FF010))
+#define UDMA_SWREQ_R (*((volatile unsigned long *)0x400FF014))
+#define UDMA_USEBURSTSET_R (*((volatile unsigned long *)0x400FF018))
+#define UDMA_USEBURSTCLR_R (*((volatile unsigned long *)0x400FF01C))
+#define UDMA_REQMASKSET_R (*((volatile unsigned long *)0x400FF020))
+#define UDMA_REQMASKCLR_R (*((volatile unsigned long *)0x400FF024))
+#define UDMA_ENASET_R (*((volatile unsigned long *)0x400FF028))
+#define UDMA_ENACLR_R (*((volatile unsigned long *)0x400FF02C))
+#define UDMA_ALTSET_R (*((volatile unsigned long *)0x400FF030))
+#define UDMA_ALTCLR_R (*((volatile unsigned long *)0x400FF034))
+#define UDMA_PRIOSET_R (*((volatile unsigned long *)0x400FF038))
+#define UDMA_PRIOCLR_R (*((volatile unsigned long *)0x400FF03C))
+#define UDMA_ERRCLR_R (*((volatile unsigned long *)0x400FF04C))
+#define UDMA_CHALT_R (*((volatile unsigned long *)0x400FF500))
+#define UDMA_CHIS_R (*((volatile unsigned long *)0x400FF504))
+
+//*****************************************************************************
+//
+// Micro Direct Memory Access (UDMA) Offsets
+//
+//*****************************************************************************
+#define UDMA_SRCENDP 0x0x00000000
+#define UDMA_DSTENDP 0x0x00000004
+#define UDMA_CHCTL 0x0x00000008
+
+//*****************************************************************************
+//
+// Nested Vectored Interrupt Ctrl (NVIC)
+//
+//*****************************************************************************
+#define NVIC_INT_TYPE_R (*((volatile unsigned long *)0xE000E004))
+#define NVIC_ST_CTRL_R (*((volatile unsigned long *)0xE000E010))
+#define NVIC_ST_RELOAD_R (*((volatile unsigned long *)0xE000E014))
+#define NVIC_ST_CURRENT_R (*((volatile unsigned long *)0xE000E018))
+#define NVIC_ST_CAL_R (*((volatile unsigned long *)0xE000E01C))
+#define NVIC_EN0_R (*((volatile unsigned long *)0xE000E100))
+#define NVIC_EN1_R (*((volatile unsigned long *)0xE000E104))
+#define NVIC_DIS0_R (*((volatile unsigned long *)0xE000E180))
+#define NVIC_DIS1_R (*((volatile unsigned long *)0xE000E184))
+#define NVIC_PEND0_R (*((volatile unsigned long *)0xE000E200))
+#define NVIC_PEND1_R (*((volatile unsigned long *)0xE000E204))
+#define NVIC_UNPEND0_R (*((volatile unsigned long *)0xE000E280))
+#define NVIC_UNPEND1_R (*((volatile unsigned long *)0xE000E284))
+#define NVIC_ACTIVE0_R (*((volatile unsigned long *)0xE000E300))
+#define NVIC_ACTIVE1_R (*((volatile unsigned long *)0xE000E304))
+#define NVIC_PRI0_R (*((volatile unsigned long *)0xE000E400))
+#define NVIC_PRI1_R (*((volatile unsigned long *)0xE000E404))
+#define NVIC_PRI2_R (*((volatile unsigned long *)0xE000E408))
+#define NVIC_PRI3_R (*((volatile unsigned long *)0xE000E40C))
+#define NVIC_PRI4_R (*((volatile unsigned long *)0xE000E410))
+#define NVIC_PRI5_R (*((volatile unsigned long *)0xE000E414))
+#define NVIC_PRI6_R (*((volatile unsigned long *)0xE000E418))
+#define NVIC_PRI7_R (*((volatile unsigned long *)0xE000E41C))
+#define NVIC_PRI8_R (*((volatile unsigned long *)0xE000E420))
+#define NVIC_PRI9_R (*((volatile unsigned long *)0xE000E424))
+#define NVIC_PRI10_R (*((volatile unsigned long *)0xE000E428))
+#define NVIC_PRI11_R (*((volatile unsigned long *)0xE000E42C))
+#define NVIC_PRI12_R (*((volatile unsigned long *)0xE000E430))
+#define NVIC_PRI13_R (*((volatile unsigned long *)0xE000E434))
+#define NVIC_CPUID_R (*((volatile unsigned long *)0xE000ED00))
+#define NVIC_INT_CTRL_R (*((volatile unsigned long *)0xE000ED04))
+#define NVIC_VTABLE_R (*((volatile unsigned long *)0xE000ED08))
+#define NVIC_APINT_R (*((volatile unsigned long *)0xE000ED0C))
+#define NVIC_SYS_CTRL_R (*((volatile unsigned long *)0xE000ED10))
+#define NVIC_CFG_CTRL_R (*((volatile unsigned long *)0xE000ED14))
+#define NVIC_SYS_PRI1_R (*((volatile unsigned long *)0xE000ED18))
+#define NVIC_SYS_PRI2_R (*((volatile unsigned long *)0xE000ED1C))
+#define NVIC_SYS_PRI3_R (*((volatile unsigned long *)0xE000ED20))
+#define NVIC_SYS_HND_CTRL_R (*((volatile unsigned long *)0xE000ED24))
+#define NVIC_FAULT_STAT_R (*((volatile unsigned long *)0xE000ED28))
+#define NVIC_HFAULT_STAT_R (*((volatile unsigned long *)0xE000ED2C))
+#define NVIC_DEBUG_STAT_R (*((volatile unsigned long *)0xE000ED30))
+#define NVIC_MM_ADDR_R (*((volatile unsigned long *)0xE000ED34))
+#define NVIC_FAULT_ADDR_R (*((volatile unsigned long *)0xE000ED38))
+#define NVIC_MPU_TYPE_R (*((volatile unsigned long *)0xE000ED90))
+#define NVIC_MPU_CTRL_R (*((volatile unsigned long *)0xE000ED94))
+#define NVIC_MPU_NUMBER_R (*((volatile unsigned long *)0xE000ED98))
+#define NVIC_MPU_R (*((volatile unsigned long *)0xE000ED9C))
+#define NVIC_MPU_ATTR_R (*((volatile unsigned long *)0xE000EDA0))
+#define NVIC_DBG_CTRL_R (*((volatile unsigned long *)0xE000EDF0))
+#define NVIC_DBG_XFER_R (*((volatile unsigned long *)0xE000EDF4))
+#define NVIC_DBG_DATA_R (*((volatile unsigned long *)0xE000EDF8))
+#define NVIC_DBG_INT_R (*((volatile unsigned long *)0xE000EDFC))
+#define NVIC_SW_TRIG_R (*((volatile unsigned long *)0xE000EF00))
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_LOAD register.
+//
+//*****************************************************************************
+#define WDT_LOAD_M 0xFFFFFFFF // Watchdog Load Value.
+#define WDT_LOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_VALUE register.
+//
+//*****************************************************************************
+#define WDT_VALUE_M 0xFFFFFFFF // Watchdog Value.
+#define WDT_VALUE_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_CTL register.
+//
+//*****************************************************************************
+#define WDT_CTL_WRC 0x80000000 // Write Complete.
+#define WDT_CTL_RESEN 0x00000002 // Watchdog Reset Enable.
+#define WDT_CTL_INTEN 0x00000001 // Watchdog Interrupt Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_ICR register.
+//
+//*****************************************************************************
+#define WDT_ICR_M 0xFFFFFFFF // Watchdog Interrupt Clear.
+#define WDT_ICR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_RIS register.
+//
+//*****************************************************************************
+#define WDT_RIS_WDTRIS 0x00000001 // Watchdog Raw Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_MIS register.
+//
+//*****************************************************************************
+#define WDT_MIS_WDTMIS 0x00000001 // Watchdog Masked Interrupt
+ // Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_TEST register.
+//
+//*****************************************************************************
+#define WDT_TEST_STALL 0x00000100 // Watchdog Stall Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_LOCK register.
+//
+//*****************************************************************************
+#define WDT_LOCK_M 0xFFFFFFFF // Watchdog Lock.
+#define WDT_LOCK_UNLOCKED 0x00000000 // Unlocked
+#define WDT_LOCK_LOCKED 0x00000001 // Locked
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_LOCK register.
+//
+//*****************************************************************************
+#define GPIO_LOCK_M 0xFFFFFFFF // GPIO Lock.
+#define GPIO_LOCK_UNLOCKED 0x00000000 // The GPIOCR register is unlocked
+ // and may be modified.
+#define GPIO_LOCK_LOCKED 0x00000001 // The GPIOCR register is locked
+ // and may not be modified.
+#define GPIO_LOCK_KEY 0x4C4F434B // Unlocks the GPIO_CR register
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_CR0 register.
+//
+//*****************************************************************************
+#define SSI_CR0_SCR_M 0x0000FF00 // SSI Serial Clock Rate.
+#define SSI_CR0_SPH 0x00000080 // SSI Serial Clock Phase.
+#define SSI_CR0_SPO 0x00000040 // SSI Serial Clock Polarity.
+#define SSI_CR0_FRF_M 0x00000030 // SSI Frame Format Select.
+#define SSI_CR0_FRF_MOTO 0x00000000 // Freescale SPI Frame Format
+#define SSI_CR0_FRF_TI 0x00000010 // Texas Instruments Synchronous
+ // Serial Frame Format
+#define SSI_CR0_FRF_NMW 0x00000020 // MICROWIRE Frame Format
+#define SSI_CR0_DSS_M 0x0000000F // SSI Data Size Select.
+#define SSI_CR0_DSS_4 0x00000003 // 4-bit data
+#define SSI_CR0_DSS_5 0x00000004 // 5-bit data
+#define SSI_CR0_DSS_6 0x00000005 // 6-bit data
+#define SSI_CR0_DSS_7 0x00000006 // 7-bit data
+#define SSI_CR0_DSS_8 0x00000007 // 8-bit data
+#define SSI_CR0_DSS_9 0x00000008 // 9-bit data
+#define SSI_CR0_DSS_10 0x00000009 // 10-bit data
+#define SSI_CR0_DSS_11 0x0000000A // 11-bit data
+#define SSI_CR0_DSS_12 0x0000000B // 12-bit data
+#define SSI_CR0_DSS_13 0x0000000C // 13-bit data
+#define SSI_CR0_DSS_14 0x0000000D // 14-bit data
+#define SSI_CR0_DSS_15 0x0000000E // 15-bit data
+#define SSI_CR0_DSS_16 0x0000000F // 16-bit data
+#define SSI_CR0_SCR_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_CR1 register.
+//
+//*****************************************************************************
+#define SSI_CR1_EOT 0x00000010 // End of Transmission.
+#define SSI_CR1_SOD 0x00000008 // SSI Slave Mode Output Disable.
+#define SSI_CR1_MS 0x00000004 // SSI Master/Slave Select.
+#define SSI_CR1_SSE 0x00000002 // SSI Synchronous Serial Port
+ // Enable.
+#define SSI_CR1_LBM 0x00000001 // SSI Loopback Mode.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_DR register.
+//
+//*****************************************************************************
+#define SSI_DR_DATA_M 0x0000FFFF // SSI Receive/Transmit Data.
+#define SSI_DR_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_SR register.
+//
+//*****************************************************************************
+#define SSI_SR_BSY 0x00000010 // SSI Busy Bit.
+#define SSI_SR_RFF 0x00000008 // SSI Receive FIFO Full.
+#define SSI_SR_RNE 0x00000004 // SSI Receive FIFO Not Empty.
+#define SSI_SR_TNF 0x00000002 // SSI Transmit FIFO Not Full.
+#define SSI_SR_TFE 0x00000001 // SSI Transmit FIFO Empty.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_CPSR register.
+//
+//*****************************************************************************
+#define SSI_CPSR_CPSDVSR_M 0x000000FF // SSI Clock Prescale Divisor.
+#define SSI_CPSR_CPSDVSR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_IM register.
+//
+//*****************************************************************************
+#define SSI_IM_TXIM 0x00000008 // SSI Transmit FIFO Interrupt
+ // Mask.
+#define SSI_IM_RXIM 0x00000004 // SSI Receive FIFO Interrupt Mask.
+#define SSI_IM_RTIM 0x00000002 // SSI Receive Time-Out Interrupt
+ // Mask.
+#define SSI_IM_RORIM 0x00000001 // SSI Receive Overrun Interrupt
+ // Mask.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_RIS register.
+//
+//*****************************************************************************
+#define SSI_RIS_TXRIS 0x00000008 // SSI Transmit FIFO Raw Interrupt
+ // Status.
+#define SSI_RIS_RXRIS 0x00000004 // SSI Receive FIFO Raw Interrupt
+ // Status.
+#define SSI_RIS_RTRIS 0x00000002 // SSI Receive Time-Out Raw
+ // Interrupt Status.
+#define SSI_RIS_RORRIS 0x00000001 // SSI Receive Overrun Raw
+ // Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_MIS register.
+//
+//*****************************************************************************
+#define SSI_MIS_TXMIS 0x00000008 // SSI Transmit FIFO Masked
+ // Interrupt Status.
+#define SSI_MIS_RXMIS 0x00000004 // SSI Receive FIFO Masked
+ // Interrupt Status.
+#define SSI_MIS_RTMIS 0x00000002 // SSI Receive Time-Out Masked
+ // Interrupt Status.
+#define SSI_MIS_RORMIS 0x00000001 // SSI Receive Overrun Masked
+ // Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_ICR register.
+//
+//*****************************************************************************
+#define SSI_ICR_RTIC 0x00000002 // SSI Receive Time-Out Interrupt
+ // Clear.
+#define SSI_ICR_RORIC 0x00000001 // SSI Receive Overrun Interrupt
+ // Clear.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_DMACTL register.
+//
+//*****************************************************************************
+#define SSI_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable.
+#define SSI_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_DR register.
+//
+//*****************************************************************************
+#define UART_DR_OE 0x00000800 // UART Overrun Error.
+#define UART_DR_BE 0x00000400 // UART Break Error.
+#define UART_DR_PE 0x00000200 // UART Parity Error.
+#define UART_DR_FE 0x00000100 // UART Framing Error.
+#define UART_DR_DATA_M 0x000000FF // Data Transmitted or Received.
+#define UART_DR_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_RSR register.
+//
+//*****************************************************************************
+#define UART_RSR_OE 0x00000008 // UART Overrun Error.
+#define UART_RSR_BE 0x00000004 // UART Break Error.
+#define UART_RSR_PE 0x00000002 // UART Parity Error.
+#define UART_RSR_FE 0x00000001 // UART Framing Error.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_ECR register.
+//
+//*****************************************************************************
+#define UART_ECR_DATA_M 0x000000FF // Error Clear.
+#define UART_ECR_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_FR register.
+//
+//*****************************************************************************
+#define UART_FR_RI 0x00000100 // Ring Indicator.
+#define UART_FR_TXFE 0x00000080 // UART Transmit FIFO Empty.
+#define UART_FR_RXFF 0x00000040 // UART Receive FIFO Full.
+#define UART_FR_TXFF 0x00000020 // UART Transmit FIFO Full.
+#define UART_FR_RXFE 0x00000010 // UART Receive FIFO Empty.
+#define UART_FR_BUSY 0x00000008 // UART Busy.
+#define UART_FR_DCD 0x00000004 // Data Carrier Detect.
+#define UART_FR_DSR 0x00000002 // Data Set Ready.
+#define UART_FR_CTS 0x00000001 // Clear To Send.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_ILPR register.
+//
+//*****************************************************************************
+#define UART_ILPR_ILPDVSR_M 0x000000FF // IrDA Low-Power Divisor.
+#define UART_ILPR_ILPDVSR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_IBRD register.
+//
+//*****************************************************************************
+#define UART_IBRD_DIVINT_M 0x0000FFFF // Integer Baud-Rate Divisor.
+#define UART_IBRD_DIVINT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_FBRD register.
+//
+//*****************************************************************************
+#define UART_FBRD_DIVFRAC_M 0x0000003F // Fractional Baud-Rate Divisor.
+#define UART_FBRD_DIVFRAC_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_LCRH register.
+//
+//*****************************************************************************
+#define UART_LCRH_SPS 0x00000080 // UART Stick Parity Select.
+#define UART_LCRH_WLEN_M 0x00000060 // UART Word Length.
+#define UART_LCRH_WLEN_5 0x00000000 // 5 bits (default)
+#define UART_LCRH_WLEN_6 0x00000020 // 6 bits
+#define UART_LCRH_WLEN_7 0x00000040 // 7 bits
+#define UART_LCRH_WLEN_8 0x00000060 // 8 bits
+#define UART_LCRH_FEN 0x00000010 // UART Enable FIFOs.
+#define UART_LCRH_STP2 0x00000008 // UART Two Stop Bits Select.
+#define UART_LCRH_EPS 0x00000004 // UART Even Parity Select.
+#define UART_LCRH_PEN 0x00000002 // UART Parity Enable.
+#define UART_LCRH_BRK 0x00000001 // UART Send Break.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_CTL register.
+//
+//*****************************************************************************
+#define UART_CTL_CTSEN 0x00008000 // Enable Clear To Send.
+#define UART_CTL_RTSEN 0x00004000 // Enable Request to Send.
+#define UART_CTL_RTS 0x00000800 // Request to Send.
+#define UART_CTL_DTR 0x00000400 // Data Terminal Ready.
+#define UART_CTL_RXE 0x00000200 // UART Receive Enable.
+#define UART_CTL_TXE 0x00000100 // UART Transmit Enable.
+#define UART_CTL_LBE 0x00000080 // UART Loop Back Enable.
+#define UART_CTL_LIN 0x00000040 // LIN Mode Enable.
+#define UART_CTL_HSE 0x00000020 // High-Speed Enable.
+#define UART_CTL_EOT 0x00000010 // End of Transmission.
+#define UART_CTL_SMART 0x00000008 // ISO 7816 Smart Card Support.
+#define UART_CTL_SIRLP 0x00000004 // UART SIR Low Power Mode.
+#define UART_CTL_SIREN 0x00000002 // UART SIR Enable.
+#define UART_CTL_UARTEN 0x00000001 // UART Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_IFLS register.
+//
+//*****************************************************************************
+#define UART_IFLS_RX_M 0x00000038 // UART Receive Interrupt FIFO
+ // Level Select.
+#define UART_IFLS_RX1_8 0x00000000 // RX FIFO <= 1/8 full
+#define UART_IFLS_RX2_8 0x00000008 // RX FIFO <= 1/4 full
+#define UART_IFLS_RX4_8 0x00000010 // RX FIFO <= 1/2 full (default)
+#define UART_IFLS_RX6_8 0x00000018 // RX FIFO <= 3/4 full
+#define UART_IFLS_RX7_8 0x00000020 // RX FIFO <= 7/8 full
+#define UART_IFLS_TX_M 0x00000007 // UART Transmit Interrupt FIFO
+ // Level Select.
+#define UART_IFLS_TX1_8 0x00000000 // TX FIFO >= 1/8 full
+#define UART_IFLS_TX2_8 0x00000001 // TX FIFO >= 1/4 full
+#define UART_IFLS_TX4_8 0x00000002 // TX FIFO >= 1/2 full (default)
+#define UART_IFLS_TX6_8 0x00000003 // TX FIFO >= 3/4 full
+#define UART_IFLS_TX7_8 0x00000004 // TX FIFO >= 7/8 full
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_IM register.
+//
+//*****************************************************************************
+#define UART_IM_LME5IM 0x00008000 // LIN Mode Edge 5 Interrupt Mask.
+#define UART_IM_LME1IM 0x00004000 // LIN Mode Edge 1 Interrupt Mask.
+#define UART_IM_LMSBIM 0x00002000 // LIN Mode Sync Break Interrupt
+ // Mask.
+#define UART_IM_OEIM 0x00000400 // UART Overrun Error Interrupt
+ // Mask.
+#define UART_IM_BEIM 0x00000200 // UART Break Error Interrupt Mask.
+#define UART_IM_PEIM 0x00000100 // UART Parity Error Interrupt
+ // Mask.
+#define UART_IM_FEIM 0x00000080 // UART Framing Error Interrupt
+ // Mask.
+#define UART_IM_RTIM 0x00000040 // UART Receive Time-Out Interrupt
+ // Mask.
+#define UART_IM_TXIM 0x00000020 // UART Transmit Interrupt Mask.
+#define UART_IM_RXIM 0x00000010 // UART Receive Interrupt Mask.
+#define UART_IM_DSRMIM 0x00000008 // UART Data Set Ready Modem
+ // Interrupt Mask.
+#define UART_IM_DCDMIM 0x00000004 // UART Data Carrier Detect Modem
+ // Interrupt Mask.
+#define UART_IM_CTSMIM 0x00000002 // UART Clear to Send Modem
+ // Interrupt Mask.
+#define UART_IM_RIMIM 0x00000001 // UART Ring Indicator Modem
+ // Interrupt Mask.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_RIS register.
+//
+//*****************************************************************************
+#define UART_RIS_LME5RIS 0x00008000 // LIN Mode Edge 5 Raw Interrupt
+ // Status.
+#define UART_RIS_LME1RIS 0x00004000 // LIN Mode Edge 1 Raw Interrupt
+ // Status.
+#define UART_RIS_LMSBRIS 0x00002000 // LIN Mode Sync Break Raw
+ // Interrupt Status.
+#define UART_RIS_OERIS 0x00000400 // UART Overrun Error Raw Interrupt
+ // Status.
+#define UART_RIS_BERIS 0x00000200 // UART Break Error Raw Interrupt
+ // Status.
+#define UART_RIS_PERIS 0x00000100 // UART Parity Error Raw Interrupt
+ // Status.
+#define UART_RIS_FERIS 0x00000080 // UART Framing Error Raw Interrupt
+ // Status.
+#define UART_RIS_RTRIS 0x00000040 // UART Receive Time-Out Raw
+ // Interrupt Status.
+#define UART_RIS_TXRIS 0x00000020 // UART Transmit Raw Interrupt
+ // Status.
+#define UART_RIS_RXRIS 0x00000010 // UART Receive Raw Interrupt
+ // Status.
+#define UART_RIS_DSRRIS 0x00000008 // UART Data Set Ready Modem Raw
+ // Interrupt Status.
+#define UART_RIS_DCDRIS 0x00000004 // UART Data Carrier Detect odem
+ // Raw Interrupt Status.
+#define UART_RIS_CTSRIS 0x00000002 // UART Clear to Send Modem Raw
+ // Interrupt Status.
+#define UART_RIS_RIRIS 0x00000001 // UART Ring Indicator Modem Raw
+ // Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_MIS register.
+//
+//*****************************************************************************
+#define UART_MIS_LME5MIS 0x00008000 // LIN Mode Edge 5 Masked Interrupt
+ // Status.
+#define UART_MIS_LME1MIS 0x00004000 // LIN Mode Edge 1 Masked Interrupt
+ // Status.
+#define UART_MIS_LMSBMIS 0x00002000 // LIN Mode Sync Break Masked
+ // Interrupt Status.
+#define UART_MIS_OEMIS 0x00000400 // UART Overrun Error Masked
+ // Interrupt Status.
+#define UART_MIS_BEMIS 0x00000200 // UART Break Error Masked
+ // Interrupt Status.
+#define UART_MIS_PEMIS 0x00000100 // UART Parity Error Masked
+ // Interrupt Status.
+#define UART_MIS_FEMIS 0x00000080 // UART Framing Error Masked
+ // Interrupt Status.
+#define UART_MIS_RTMIS 0x00000040 // UART Receive Time-Out Masked
+ // Interrupt Status.
+#define UART_MIS_TXMIS 0x00000020 // UART Transmit Masked Interrupt
+ // Status.
+#define UART_MIS_RXMIS 0x00000010 // UART Receive Masked Interrupt
+ // Status.
+#define UART_MIS_DSRMIS 0x00000008 // UART Data Set Ready Modem Masked
+ // Interrupt Status.
+#define UART_MIS_DCDMIS 0x00000004 // UART Data Carrier Detect odem
+ // Masked Interrupt Status.
+#define UART_MIS_CTSMIS 0x00000002 // UART Clear to Send Modem Masked
+ // Interrupt Status.
+#define UART_MIS_RIMIS 0x00000001 // UART Ring Indicator Modem Masked
+ // Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_ICR register.
+//
+//*****************************************************************************
+#define UART_ICR_LME5MIC 0x00008000 // LIN Mode Edge 5 Interrupt Clear.
+#define UART_ICR_LME1MIC 0x00004000 // LIN Mode Edge 1 Interrupt Clear.
+#define UART_ICR_LMSBMIC 0x00002000 // LIN Mode Sync Break Interrupt
+ // Clear.
+#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear.
+#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear.
+#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear.
+#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear.
+#define UART_ICR_RTIC 0x00000040 // Receive Time-Out Interrupt
+ // Clear.
+#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear.
+#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear.
+#define UART_ICR_DSRMIC 0x00000008 // UART Data Set Ready Modem
+ // Interrupt Clear.
+#define UART_ICR_DCDMIC 0x00000004 // UART Data Carrier Detect odem
+ // Interrupt Clear.
+#define UART_ICR_CTSMIC 0x00000002 // UART Clear to Send Modem
+ // Interrupt Clear.
+#define UART_ICR_RIMIC 0x00000001 // UART Ring Indicator Modem
+ // Interrupt Clear.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_DMACTL register.
+//
+//*****************************************************************************
+#define UART_DMACTL_DMAERR 0x00000004 // DMA on Error.
+#define UART_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable.
+#define UART_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_LCTL register.
+//
+//*****************************************************************************
+#define UART_LCTL_BLEN_M 0x00000030 // Sync Break Length.
+#define UART_LCTL_BLEN_13T 0x00000000 // Sync break length is 13T bits
+ // (default)
+#define UART_LCTL_BLEN_14T 0x00000010 // Sync break length is 14T bits
+#define UART_LCTL_BLEN_15T 0x00000020 // Sync break length is 15T bits
+#define UART_LCTL_BLEN_16T 0x00000030 // Sync break length is 16T bits
+#define UART_LCTL_MASTER 0x00000001 // LIN Master Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_LSS register.
+//
+//*****************************************************************************
+#define UART_LSS_TSS_M 0x0000FFFF // Timer Snap Shot.
+#define UART_LSS_TSS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_LTIM register.
+//
+//*****************************************************************************
+#define UART_LTIM_TIMER_M 0x0000FFFF // Timer Value.
+#define UART_LTIM_TIMER_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MSA register.
+//
+//*****************************************************************************
+#define I2C_MSA_SA_M 0x000000FE // I2C Slave Address.
+#define I2C_MSA_RS 0x00000001 // Receive not send.
+#define I2C_MSA_SA_S 1
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SOAR register.
+//
+//*****************************************************************************
+#define I2C_SOAR_OAR_M 0x0000007F // I2C Slave Own Address.
+#define I2C_SOAR_OAR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SCSR register.
+//
+//*****************************************************************************
+#define I2C_SCSR_FBR 0x00000004 // First Byte Received.
+#define I2C_SCSR_TREQ 0x00000002 // Transmit Request.
+#define I2C_SCSR_DA 0x00000001 // Device Active.
+#define I2C_SCSR_RREQ 0x00000001 // Receive Request.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MCS register.
+//
+//*****************************************************************************
+#define I2C_MCS_BUSBSY 0x00000040 // Bus Busy.
+#define I2C_MCS_IDLE 0x00000020 // I2C Idle.
+#define I2C_MCS_ARBLST 0x00000010 // Arbitration Lost.
+#define I2C_MCS_ACK 0x00000008 // Data Acknowledge Enable.
+#define I2C_MCS_DATACK 0x00000008 // Acknowledge Data.
+#define I2C_MCS_ADRACK 0x00000004 // Acknowledge Address.
+#define I2C_MCS_STOP 0x00000004 // Generate STOP.
+#define I2C_MCS_START 0x00000002 // Generate START.
+#define I2C_MCS_ERROR 0x00000002 // Error.
+#define I2C_MCS_RUN 0x00000001 // I2C Master Enable.
+#define I2C_MCS_BUSY 0x00000001 // I2C Busy.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SDR register.
+//
+//*****************************************************************************
+#define I2C_SDR_DATA_M 0x000000FF // Data for Transfer.
+#define I2C_SDR_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MDR register.
+//
+//*****************************************************************************
+#define I2C_MDR_DATA_M 0x000000FF // Data Transferred.
+#define I2C_MDR_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MTPR register.
+//
+//*****************************************************************************
+#define I2C_MTPR_TPR_M 0x000000FF // SCL Clock Period.
+#define I2C_MTPR_TPR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SIMR register.
+//
+//*****************************************************************************
+#define I2C_SIMR_STOPIM 0x00000004 // Stop Condition Interrupt Mask.
+#define I2C_SIMR_STARTIM 0x00000002 // Start Condition Interrupt Mask.
+#define I2C_SIMR_DATAIM 0x00000001 // Data Interrupt Mask.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SRIS register.
+//
+//*****************************************************************************
+#define I2C_SRIS_STOPRIS 0x00000004 // Stop Condition Raw Interrupt
+ // Status.
+#define I2C_SRIS_STARTRIS 0x00000002 // Start Condition Raw Interrupt
+ // Status.
+#define I2C_SRIS_DATARIS 0x00000001 // Data Raw Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MIMR register.
+//
+//*****************************************************************************
+#define I2C_MIMR_IM 0x00000001 // Interrupt Mask.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MRIS register.
+//
+//*****************************************************************************
+#define I2C_MRIS_RIS 0x00000001 // Raw Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SMIS register.
+//
+//*****************************************************************************
+#define I2C_SMIS_STOPMIS 0x00000004 // Stop Condition Masked Interrupt
+ // Status.
+#define I2C_SMIS_STARTMIS 0x00000002 // Start Condition Masked Interrupt
+ // Status.
+#define I2C_SMIS_DATAMIS 0x00000001 // Data Masked Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SICR register.
+//
+//*****************************************************************************
+#define I2C_SICR_STOPIC 0x00000004 // Stop Condition Interrupt Clear.
+#define I2C_SICR_STARTIC 0x00000002 // Start Condition Interrupt Clear.
+#define I2C_SICR_DATAIC 0x00000001 // Data Interrupt Clear.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MMIS register.
+//
+//*****************************************************************************
+#define I2C_MMIS_MIS 0x00000001 // Masked Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MICR register.
+//
+//*****************************************************************************
+#define I2C_MICR_IC 0x00000001 // Interrupt Clear.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MCR register.
+//
+//*****************************************************************************
+#define I2C_MCR_SFE 0x00000020 // I2C Slave Function Enable.
+#define I2C_MCR_MFE 0x00000010 // I2C Master Function Enable.
+#define I2C_MCR_LPBK 0x00000001 // I2C Loopback.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_CTL register.
+//
+//*****************************************************************************
+#define PWM_CTL_GLOBALSYNC3 0x00000008 // Update PWM Generator 3.
+#define PWM_CTL_GLOBALSYNC2 0x00000004 // Update PWM Generator 2.
+#define PWM_CTL_GLOBALSYNC1 0x00000002 // Update PWM Generator 1.
+#define PWM_CTL_GLOBALSYNC0 0x00000001 // Update PWM Generator 0.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_SYNC register.
+//
+//*****************************************************************************
+#define PWM_SYNC_SYNC3 0x00000008 // Reset Generator 3 Counter.
+#define PWM_SYNC_SYNC2 0x00000004 // Reset Generator 2 Counter.
+#define PWM_SYNC_SYNC1 0x00000002 // Reset Generator 1 Counter.
+#define PWM_SYNC_SYNC0 0x00000001 // Reset Generator 0 Counter.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_ENABLE register.
+//
+//*****************************************************************************
+#define PWM_ENABLE_PWM7EN 0x00000080 // PWM7 Output Enable.
+#define PWM_ENABLE_PWM6EN 0x00000040 // PWM6 Output Enable.
+#define PWM_ENABLE_PWM5EN 0x00000020 // PWM5 Output Enable.
+#define PWM_ENABLE_PWM4EN 0x00000010 // PWM4 Output Enable.
+#define PWM_ENABLE_PWM3EN 0x00000008 // PWM3 Output Enable.
+#define PWM_ENABLE_PWM2EN 0x00000004 // PWM2 Output Enable.
+#define PWM_ENABLE_PWM1EN 0x00000002 // PWM1 Output Enable.
+#define PWM_ENABLE_PWM0EN 0x00000001 // PWM0 Output Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_INVERT register.
+//
+//*****************************************************************************
+#define PWM_INVERT_PWM7INV 0x00000080 // Invert PWM7 Signal.
+#define PWM_INVERT_PWM6INV 0x00000040 // Invert PWM6 Signal.
+#define PWM_INVERT_PWM5INV 0x00000020 // Invert PWM5 Signal.
+#define PWM_INVERT_PWM4INV 0x00000010 // Invert PWM4 Signal.
+#define PWM_INVERT_PWM3INV 0x00000008 // Invert PWM3 Signal.
+#define PWM_INVERT_PWM2INV 0x00000004 // Invert PWM2 Signal.
+#define PWM_INVERT_PWM1INV 0x00000002 // Invert PWM1 Signal.
+#define PWM_INVERT_PWM0INV 0x00000001 // Invert PWM0 Signal.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_FAULT register.
+//
+//*****************************************************************************
+#define PWM_FAULT_FAULT7 0x00000080 // PWM7 Fault.
+#define PWM_FAULT_FAULT6 0x00000040 // PWM6 Fault.
+#define PWM_FAULT_FAULT5 0x00000020 // PWM5 Fault.
+#define PWM_FAULT_FAULT4 0x00000010 // PWM4 Fault.
+#define PWM_FAULT_FAULT3 0x00000008 // PWM3 Fault.
+#define PWM_FAULT_FAULT2 0x00000004 // PWM2 Fault.
+#define PWM_FAULT_FAULT1 0x00000002 // PWM1 Fault.
+#define PWM_FAULT_FAULT0 0x00000001 // PWM0 Fault.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_INTEN register.
+//
+//*****************************************************************************
+#define PWM_INTEN_INTFAULT3 0x00080000 // Interrupt Fault 3.
+#define PWM_INTEN_INTFAULT2 0x00040000 // Interrupt Fault 2.
+#define PWM_INTEN_INTFAULT1 0x00020000 // Interrupt Fault 1.
+#define PWM_INTEN_INTFAULT0 0x00010000 // Interrupt Fault 0.
+#define PWM_INTEN_INTPWM3 0x00000008 // PWM3 Interrupt Enable.
+#define PWM_INTEN_INTPWM2 0x00000004 // PWM2 Interrupt Enable.
+#define PWM_INTEN_INTPWM1 0x00000002 // PWM1 Interrupt Enable.
+#define PWM_INTEN_INTPWM0 0x00000001 // PWM0 Interrupt Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_RIS register.
+//
+//*****************************************************************************
+#define PWM_RIS_INTFAULT3 0x00080000 // Interrupt Fault PWM 3.
+#define PWM_RIS_INTFAULT2 0x00040000 // Interrupt Fault PWM 2.
+#define PWM_RIS_INTFAULT1 0x00020000 // Interrupt Fault PWM 1.
+#define PWM_RIS_INTFAULT0 0x00010000 // Interrupt Fault PWM 0.
+#define PWM_RIS_INTPWM3 0x00000008 // PWM3 Interrupt Asserted.
+#define PWM_RIS_INTPWM2 0x00000004 // PWM2 Interrupt Asserted.
+#define PWM_RIS_INTPWM1 0x00000002 // PWM1 Interrupt Asserted.
+#define PWM_RIS_INTPWM0 0x00000001 // PWM0 Interrupt Asserted.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_ISC register.
+//
+//*****************************************************************************
+#define PWM_ISC_INTFAULT3 0x00080000 // FAULT3 Interrupt Asserted.
+#define PWM_ISC_INTFAULT2 0x00040000 // FAULT2 Interrupt Asserted.
+#define PWM_ISC_INTFAULT1 0x00020000 // FAULT1 Interrupt Asserted.
+#define PWM_ISC_INTFAULT0 0x00010000 // FAULT0 Interrupt Asserted.
+#define PWM_ISC_INTPWM3 0x00000008 // PWM3 Interrupt Status.
+#define PWM_ISC_INTPWM2 0x00000004 // PWM2 Interrupt Status.
+#define PWM_ISC_INTPWM1 0x00000002 // PWM1 Interrupt Status.
+#define PWM_ISC_INTPWM0 0x00000001 // PWM0 Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_STATUS register.
+//
+//*****************************************************************************
+#define PWM_STATUS_FAULT3 0x00000008 // Fault3 Interrupt Status.
+#define PWM_STATUS_FAULT2 0x00000004 // Fault2 Interrupt Status.
+#define PWM_STATUS_FAULT1 0x00000002 // Fault1 Interrupt Status.
+#define PWM_STATUS_FAULT0 0x00000001 // Fault0 Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_FAULTVAL register.
+//
+//*****************************************************************************
+#define PWM_FAULTVAL_PWM7 0x00000080 // PWM7 Fault Value.
+#define PWM_FAULTVAL_PWM6 0x00000040 // PWM6 Fault Value.
+#define PWM_FAULTVAL_PWM5 0x00000020 // PWM5 Fault Value.
+#define PWM_FAULTVAL_PWM4 0x00000010 // PWM4 Fault Value.
+#define PWM_FAULTVAL_PWM3 0x00000008 // PWM3 Fault Value.
+#define PWM_FAULTVAL_PWM2 0x00000004 // PWM2 Fault Value.
+#define PWM_FAULTVAL_PWM1 0x00000002 // PWM1 Fault Value.
+#define PWM_FAULTVAL_PWM0 0x00000001 // PWM0 Fault Value.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_CTL,
+// PWM_O_1_CTL, PWM_O_2_CTL, and PWM_O_3_CTL registers.
+//
+//*****************************************************************************
+#define PWM_X_CTL_LATCH 0x00040000 // Latch Fault Input.
+#define PWM_X_CTL_MINFLTPER 0x00020000 // Minimum Fault Period.
+#define PWM_X_CTL_FLTSRC 0x00010000 // Fault Condition Source.
+#define PWM_X_CTL_DBFALLUPD_M 0x0000C000 // Specifies the update mode for
+ // the PWMnDBFALL register.
+#define PWM_X_CTL_DBFALLUPD_I 0x00000000 // Immediate
+#define PWM_X_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized
+#define PWM_X_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized
+#define PWM_X_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode.
+#define PWM_X_CTL_DBRISEUPD_I 0x00000000 // Immediate
+#define PWM_X_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized
+#define PWM_X_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized
+#define PWM_X_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode.
+#define PWM_X_CTL_DBCTLUPD_I 0x00000000 // Immediate
+#define PWM_X_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized
+#define PWM_X_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized
+#define PWM_X_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode.
+#define PWM_X_CTL_GENBUPD_I 0x00000000 // Immediate
+#define PWM_X_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized
+#define PWM_X_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized
+#define PWM_X_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode.
+#define PWM_X_CTL_GENAUPD_I 0x00000000 // Immediate
+#define PWM_X_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized
+#define PWM_X_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized
+#define PWM_X_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode.
+#define PWM_X_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode.
+#define PWM_X_CTL_LOADUPD 0x00000008 // Load Register Update Mode.
+#define PWM_X_CTL_DEBUG 0x00000004 // Debug Mode.
+#define PWM_X_CTL_MODE 0x00000002 // Counter Mode.
+#define PWM_X_CTL_ENABLE 0x00000001 // PWM Block Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_INTEN,
+// PWM_O_1_INTEN, PWM_O_2_INTEN, and PWM_O_3_INTEN registers.
+//
+//*****************************************************************************
+#define PWM_X_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=Comparator B
+ // Down.
+#define PWM_X_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=Comparator B
+ // Up.
+#define PWM_X_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=Comparator A
+ // Down.
+#define PWM_X_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=Comparator A
+ // Up.
+#define PWM_X_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=Load.
+#define PWM_X_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0.
+#define PWM_X_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=Comparator
+ // B Down.
+#define PWM_X_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=Comparator
+ // B Up.
+#define PWM_X_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=Comparator
+ // A Down.
+#define PWM_X_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=Comparator
+ // A Up.
+#define PWM_X_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=Load.
+#define PWM_X_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_RIS,
+// PWM_O_1_RIS, PWM_O_2_RIS, and PWM_O_3_RIS registers.
+//
+//*****************************************************************************
+#define PWM_X_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt
+ // Status.
+#define PWM_X_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt
+ // Status.
+#define PWM_X_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt
+ // Status.
+#define PWM_X_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt
+ // Status.
+#define PWM_X_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status.
+#define PWM_X_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_ISC,
+// PWM_O_1_ISC, PWM_O_2_ISC, and PWM_O_3_ISC registers.
+//
+//*****************************************************************************
+#define PWM_X_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt.
+#define PWM_X_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt.
+#define PWM_X_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt.
+#define PWM_X_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt.
+#define PWM_X_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt.
+#define PWM_X_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_LOAD,
+// PWM_O_1_LOAD, PWM_O_2_LOAD, and PWM_O_3_LOAD registers.
+//
+//*****************************************************************************
+#define PWM_X_LOAD_M 0x0000FFFF // Counter Load Value.
+#define PWM_X_LOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_COUNT,
+// PWM_O_1_COUNT, PWM_O_2_COUNT, and PWM_O_3_COUNT registers.
+//
+//*****************************************************************************
+#define PWM_X_COUNT_M 0x0000FFFF // Counter Value.
+#define PWM_X_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_CMPA,
+// PWM_O_1_CMPA, PWM_O_2_CMPA, and PWM_O_3_CMPA registers.
+//
+//*****************************************************************************
+#define PWM_X_CMPA_M 0x0000FFFF // Comparator A Value.
+#define PWM_X_CMPA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_CMPB,
+// PWM_O_1_CMPB, PWM_O_2_CMPB, and PWM_O_3_CMPB registers.
+//
+//*****************************************************************************
+#define PWM_X_CMPB_M 0x0000FFFF // Comparator B Value.
+#define PWM_X_CMPB_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_GENA,
+// PWM_O_1_GENA, PWM_O_2_GENA, and PWM_O_3_GENA registers.
+//
+//*****************************************************************************
+#define PWM_X_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down.
+#define PWM_X_GENA_ACTCMPBD_NONE \
+ 0x00000000 // Do nothing.
+#define PWM_X_GENA_ACTCMPBD_INV 0x00000400 // Invert the output signal.
+#define PWM_X_GENA_ACTCMPBD_ZERO \
+ 0x00000800 // Set the output signal to 0.
+#define PWM_X_GENA_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1.
+#define PWM_X_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up.
+#define PWM_X_GENA_ACTCMPBU_NONE \
+ 0x00000000 // Do nothing.
+#define PWM_X_GENA_ACTCMPBU_INV 0x00000100 // Invert the output signal.
+#define PWM_X_GENA_ACTCMPBU_ZERO \
+ 0x00000200 // Set the output signal to 0.
+#define PWM_X_GENA_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1.
+#define PWM_X_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down.
+#define PWM_X_GENA_ACTCMPAD_NONE \
+ 0x00000000 // Do nothing.
+#define PWM_X_GENA_ACTCMPAD_INV 0x00000040 // Invert the output signal.
+#define PWM_X_GENA_ACTCMPAD_ZERO \
+ 0x00000080 // Set the output signal to 0.
+#define PWM_X_GENA_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1.
+#define PWM_X_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up.
+#define PWM_X_GENA_ACTCMPAU_NONE \
+ 0x00000000 // Do nothing.
+#define PWM_X_GENA_ACTCMPAU_INV 0x00000010 // Invert the output signal.
+#define PWM_X_GENA_ACTCMPAU_ZERO \
+ 0x00000020 // Set the output signal to 0.
+#define PWM_X_GENA_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1.
+#define PWM_X_GENA_ACTLOAD_M 0x0000000C // Action for Counter=Load.
+#define PWM_X_GENA_ACTLOAD_NONE 0x00000000 // Do nothing.
+#define PWM_X_GENA_ACTLOAD_INV 0x00000004 // Invert the output signal.
+#define PWM_X_GENA_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0.
+#define PWM_X_GENA_ACTLOAD_ONE 0x0000000C // Set the output signal to 1.
+#define PWM_X_GENA_ACTZERO_M 0x00000003 // Action for Counter=0.
+#define PWM_X_GENA_ACTZERO_NONE 0x00000000 // Do nothing.
+#define PWM_X_GENA_ACTZERO_INV 0x00000001 // Invert the output signal.
+#define PWM_X_GENA_ACTZERO_ZERO 0x00000002 // Set the output signal to 0.
+#define PWM_X_GENA_ACTZERO_ONE 0x00000003 // Set the output signal to 1.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_GENB,
+// PWM_O_1_GENB, PWM_O_2_GENB, and PWM_O_3_GENB registers.
+//
+//*****************************************************************************
+#define PWM_X_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down.
+#define PWM_X_GENB_ACTCMPBD_NONE \
+ 0x00000000 // Do nothing.
+#define PWM_X_GENB_ACTCMPBD_INV 0x00000400 // Invert the output signal.
+#define PWM_X_GENB_ACTCMPBD_ZERO \
+ 0x00000800 // Set the output signal to 0.
+#define PWM_X_GENB_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1.
+#define PWM_X_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up.
+#define PWM_X_GENB_ACTCMPBU_NONE \
+ 0x00000000 // Do nothing.
+#define PWM_X_GENB_ACTCMPBU_INV 0x00000100 // Invert the output signal.
+#define PWM_X_GENB_ACTCMPBU_ZERO \
+ 0x00000200 // Set the output signal to 0.
+#define PWM_X_GENB_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1.
+#define PWM_X_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down.
+#define PWM_X_GENB_ACTCMPAD_NONE \
+ 0x00000000 // Do nothing.
+#define PWM_X_GENB_ACTCMPAD_INV 0x00000040 // Invert the output signal.
+#define PWM_X_GENB_ACTCMPAD_ZERO \
+ 0x00000080 // Set the output signal to 0.
+#define PWM_X_GENB_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1.
+#define PWM_X_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up.
+#define PWM_X_GENB_ACTCMPAU_NONE \
+ 0x00000000 // Do nothing.
+#define PWM_X_GENB_ACTCMPAU_INV 0x00000010 // Invert the output signal.
+#define PWM_X_GENB_ACTCMPAU_ZERO \
+ 0x00000020 // Set the output signal to 0.
+#define PWM_X_GENB_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1.
+#define PWM_X_GENB_ACTLOAD_M 0x0000000C // Action for Counter=Load.
+#define PWM_X_GENB_ACTLOAD_NONE 0x00000000 // Do nothing.
+#define PWM_X_GENB_ACTLOAD_INV 0x00000004 // Invert the output signal.
+#define PWM_X_GENB_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0.
+#define PWM_X_GENB_ACTLOAD_ONE 0x0000000C // Set the output signal to 1.
+#define PWM_X_GENB_ACTZERO_M 0x00000003 // Action for Counter=0.
+#define PWM_X_GENB_ACTZERO_NONE 0x00000000 // Do nothing.
+#define PWM_X_GENB_ACTZERO_INV 0x00000001 // Invert the output signal.
+#define PWM_X_GENB_ACTZERO_ZERO 0x00000002 // Set the output signal to 0.
+#define PWM_X_GENB_ACTZERO_ONE 0x00000003 // Set the output signal to 1.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_DBCTL,
+// PWM_O_1_DBCTL, PWM_O_2_DBCTL, and PWM_O_3_DBCTL registers.
+//
+//*****************************************************************************
+#define PWM_X_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_DBRISE,
+// PWM_O_1_DBRISE, PWM_O_2_DBRISE, and PWM_O_3_DBRISE registers.
+//
+//*****************************************************************************
+#define PWM_X_DBRISE_DELAY_M 0x00000FFF // Dead-Band Rise Delay.
+#define PWM_X_DBRISE_DELAY_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_DBFALL,
+// PWM_O_1_DBFALL, PWM_O_2_DBFALL, and PWM_O_3_DBFALL registers.
+//
+//*****************************************************************************
+#define PWM_X_DBFALL_DELAY_M 0x00000FFF // Dead-Band Fall Delay.
+#define PWM_X_DBFALL_DELAY_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_FLTSRC0,
+// PWM_O_1_FLTSRC0, PWM_O_2_FLTSRC0, and PWM_O_3_FLTSRC0 registers.
+//
+//*****************************************************************************
+#define PWM_X_FLTSRC0_FAULT3 0x00000008 // Fault3.
+#define PWM_X_FLTSRC0_FAULT2 0x00000004 // Fault2.
+#define PWM_X_FLTSRC0_FAULT1 0x00000002 // Fault1.
+#define PWM_X_FLTSRC0_FAULT0 0x00000001 // Fault0.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_FLTSRC1,
+// PWM_O_1_FLTSRC1, PWM_O_2_FLTSRC1, and PWM_O_3_FLTSRC1 registers.
+//
+//*****************************************************************************
+#define PWM_X_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7.
+#define PWM_X_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6.
+#define PWM_X_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5.
+#define PWM_X_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4.
+#define PWM_X_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3.
+#define PWM_X_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2.
+#define PWM_X_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1.
+#define PWM_X_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_MINFLTPER,
+// PWM_O_1_MINFLTPER, PWM_O_2_MINFLTPER, and PWM_O_3_MINFLTPER registers.
+//
+//*****************************************************************************
+#define PWM_X_MINFLTPER_M 0x0000FFFF // Minimum Fault Period.
+#define PWM_X_MINFLTPER_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_FLTSEN,
+// PWM_O_1_FLTSEN, PWM_O_2_FLTSEN, and PWM_O_3_FLTSEN registers.
+//
+//*****************************************************************************
+#define PWM_X_FLTSEN_FAULT3 0x00000008 // Fault3 Sense.
+#define PWM_X_FLTSEN_FAULT2 0x00000004 // Fault2 Sense.
+#define PWM_X_FLTSEN_FAULT1 0x00000002 // Fault1 Sense.
+#define PWM_X_FLTSEN_FAULT0 0x00000001 // Fault0 Sense.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_FLTSTAT0,
+// PWM_O_1_FLTSTAT0, PWM_O_2_FLTSTAT0, and PWM_O_3_FLTSTAT0 registers.
+//
+//*****************************************************************************
+#define PWM_X_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3.
+#define PWM_X_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2.
+#define PWM_X_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1.
+#define PWM_X_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_FLTSTAT1,
+// PWM_O_1_FLTSTAT1, PWM_O_2_FLTSTAT1, and PWM_O_3_FLTSTAT1 registers.
+//
+//*****************************************************************************
+#define PWM_X_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger.
+#define PWM_X_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger.
+#define PWM_X_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger.
+#define PWM_X_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger.
+#define PWM_X_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger.
+#define PWM_X_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger.
+#define PWM_X_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger.
+#define PWM_X_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_CTL register.
+//
+//*****************************************************************************
+#define QEI_CTL_FILTCNT_M 0x000F0000 // Input Filter Pre-Scale Count.
+#define QEI_CTL_FILTEN 0x00002000 // Enable Input Filter.
+#define QEI_CTL_STALLEN 0x00001000 // Stall QEI.
+#define QEI_CTL_INVI 0x00000800 // Invert Index Pulse.
+#define QEI_CTL_INVB 0x00000400 // Invert PhB.
+#define QEI_CTL_INVA 0x00000200 // Invert PhA.
+#define QEI_CTL_VELDIV_M 0x000001C0 // Predivide Velocity.
+#define QEI_CTL_VELDIV_1 0x00000000 // /1
+#define QEI_CTL_VELDIV_2 0x00000040 // /2
+#define QEI_CTL_VELDIV_4 0x00000080 // /4
+#define QEI_CTL_VELDIV_8 0x000000C0 // /8
+#define QEI_CTL_VELDIV_16 0x00000100 // /16
+#define QEI_CTL_VELDIV_32 0x00000140 // /32
+#define QEI_CTL_VELDIV_64 0x00000180 // /64
+#define QEI_CTL_VELDIV_128 0x000001C0 // /128
+#define QEI_CTL_VELEN 0x00000020 // Capture Velocity.
+#define QEI_CTL_RESMODE 0x00000010 // Reset Mode.
+#define QEI_CTL_CAPMODE 0x00000008 // Capture Mode.
+#define QEI_CTL_SIGMODE 0x00000004 // Signal Mode.
+#define QEI_CTL_SWAP 0x00000002 // Swap Signals.
+#define QEI_CTL_ENABLE 0x00000001 // Enable QEI.
+#define QEI_CTL_FILTCNT_S 16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_STAT register.
+//
+//*****************************************************************************
+#define QEI_STAT_DIRECTION 0x00000002 // Direction of Rotation.
+#define QEI_STAT_ERROR 0x00000001 // Error Detected.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_POS register.
+//
+//*****************************************************************************
+#define QEI_POS_M 0xFFFFFFFF // Current Position Integrator
+ // Value.
+#define QEI_POS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_MAXPOS register.
+//
+//*****************************************************************************
+#define QEI_MAXPOS_M 0xFFFFFFFF // Maximum Position Integrator
+ // Value.
+#define QEI_MAXPOS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_LOAD register.
+//
+//*****************************************************************************
+#define QEI_LOAD_M 0xFFFFFFFF // Velocity Timer Load Value.
+#define QEI_LOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_TIME register.
+//
+//*****************************************************************************
+#define QEI_TIME_M 0xFFFFFFFF // Velocity Timer Current Value.
+#define QEI_TIME_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_COUNT register.
+//
+//*****************************************************************************
+#define QEI_COUNT_M 0xFFFFFFFF // Velocity Pulse Count.
+#define QEI_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_SPEED register.
+//
+//*****************************************************************************
+#define QEI_SPEED_M 0xFFFFFFFF // Velocity.
+#define QEI_SPEED_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_INTEN register.
+//
+//*****************************************************************************
+#define QEI_INTEN_ERROR 0x00000008 // Phase Error Interrupt Enable.
+#define QEI_INTEN_DIR 0x00000004 // Direction Change Interrupt
+ // Enable.
+#define QEI_INTEN_TIMER 0x00000002 // Timer Expires Interrupt Enable.
+#define QEI_INTEN_INDEX 0x00000001 // Index Pulse Detected Interrupt
+ // Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_RIS register.
+//
+//*****************************************************************************
+#define QEI_RIS_ERROR 0x00000008 // Phase Error Detected.
+#define QEI_RIS_DIR 0x00000004 // Direction Change Detected.
+#define QEI_RIS_TIMER 0x00000002 // Velocity Timer Expired.
+#define QEI_RIS_INDEX 0x00000001 // Index Pulse Asserted.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_ISC register.
+//
+//*****************************************************************************
+#define QEI_ISC_ERROR 0x00000008 // Phase Error Interrupt.
+#define QEI_ISC_DIR 0x00000004 // Direction Change Interrupt.
+#define QEI_ISC_TIMER 0x00000002 // Velocity Timer Expired
+ // Interrupt.
+#define QEI_ISC_INDEX 0x00000001 // Index Pulse Interrupt.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_CFG register.
+//
+//*****************************************************************************
+#define TIMER_CFG_M 0x00000007 // GPTM Configuration.
+#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32-bit timer configuration.
+#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32-bit real-time clock (RTC)
+ // counter configuration.
+#define TIMER_CFG_16_BIT 0x00000004 // 16-bit timer configuration,
+ // function is controlled by bits
+ // 1:0 of GPTMTAMR and GPTMTBMR.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAMR register.
+//
+//*****************************************************************************
+#define TIMER_TAMR_TASNAPS 0x00000080 // GPTM Timer A Snap-Shot Mode.
+#define TIMER_TAMR_TAWOT 0x00000040 // GPTM Timer A Wait-on-Trigger.
+#define TIMER_TAMR_TAMIE 0x00000020 // GPTM Timer A Match Interrupt
+ // Enable.
+#define TIMER_TAMR_TACDIR 0x00000010 // GPTM Timer A Count Direction.
+#define TIMER_TAMR_TAAMS 0x00000008 // GPTM Timer A Alternate Mode
+ // Select.
+#define TIMER_TAMR_TACMR 0x00000004 // GPTM Timer A Capture Mode.
+#define TIMER_TAMR_TAMR_M 0x00000003 // GPTM Timer A Mode.
+#define TIMER_TAMR_TAMR_1_SHOT 0x00000001 // One-Shot Timer mode
+#define TIMER_TAMR_TAMR_PERIOD 0x00000002 // Periodic Timer mode
+#define TIMER_TAMR_TAMR_CAP 0x00000003 // Capture mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBMR register.
+//
+//*****************************************************************************
+#define TIMER_TBMR_TBSNAPS 0x00000080 // GPTM Timer B Snap-Shot Mode.
+#define TIMER_TBMR_TBWOT 0x00000040 // GPTM Timer B Wait-on-Trigger.
+#define TIMER_TBMR_TBMIE 0x00000020 // GPTM Timer B Match Interrupt
+ // Enable.
+#define TIMER_TBMR_TBCDIR 0x00000010 // GPTM Timer B Count Direction.
+#define TIMER_TBMR_TBAMS 0x00000008 // GPTM Timer B Alternate Mode
+ // Select.
+#define TIMER_TBMR_TBCMR 0x00000004 // GPTM Timer B Capture Mode.
+#define TIMER_TBMR_TBMR_M 0x00000003 // GPTM Timer B Mode.
+#define TIMER_TBMR_TBMR_1_SHOT 0x00000001 // One-Shot Timer mode
+#define TIMER_TBMR_TBMR_PERIOD 0x00000002 // Periodic Timer mode
+#define TIMER_TBMR_TBMR_CAP 0x00000003 // Capture mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_CTL register.
+//
+//*****************************************************************************
+#define TIMER_CTL_TBPWML 0x00004000 // GPTM Timer B PWM Output Level.
+#define TIMER_CTL_TBOTE 0x00002000 // GPTM Timer B Output Trigger
+ // Enable.
+#define TIMER_CTL_TBEVENT_M 0x00000C00 // GPTM Timer B Event Mode.
+#define TIMER_CTL_TBEVENT_POS 0x00000000 // Positive edge
+#define TIMER_CTL_TBEVENT_NEG 0x00000400 // Negative edge
+#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // Both edges
+#define TIMER_CTL_TBSTALL 0x00000200 // GPTM Timer B Stall Enable.
+#define TIMER_CTL_TBEN 0x00000100 // GPTM Timer B Enable.
+#define TIMER_CTL_TAPWML 0x00000040 // GPTM Timer A PWM Output Level.
+#define TIMER_CTL_TAOTE 0x00000020 // GPTM Timer A Output Trigger
+ // Enable.
+#define TIMER_CTL_RTCEN 0x00000010 // GPTM RTC Enable.
+#define TIMER_CTL_TAEVENT_M 0x0000000C // GPTM Timer A Event Mode.
+#define TIMER_CTL_TAEVENT_POS 0x00000000 // Positive edge
+#define TIMER_CTL_TAEVENT_NEG 0x00000004 // Negative edge
+#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // Both edges
+#define TIMER_CTL_TASTALL 0x00000002 // GPTM Timer A Stall Enable.
+#define TIMER_CTL_TAEN 0x00000001 // GPTM Timer A Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_IMR register.
+//
+//*****************************************************************************
+#define TIMER_IMR_TBMIM 0x00000800 // GPTM Timer B Mode Match
+ // Interrupt Mask.
+#define TIMER_IMR_CBEIM 0x00000400 // GPTM Capture B Event Interrupt
+ // Mask.
+#define TIMER_IMR_CBMIM 0x00000200 // GPTM Capture B Match Interrupt
+ // Mask.
+#define TIMER_IMR_TBTOIM 0x00000100 // GPTM Timer B Time-Out Interrupt
+ // Mask.
+#define TIMER_IMR_TAMIM 0x00000010 // GPTM Timer A Mode Match
+ // Interrupt Mask.
+#define TIMER_IMR_RTCIM 0x00000008 // GPTM RTC Interrupt Mask.
+#define TIMER_IMR_CAEIM 0x00000004 // GPTM Capture A Event Interrupt
+ // Mask.
+#define TIMER_IMR_CAMIM 0x00000002 // GPTM Capture A Match Interrupt
+ // Mask.
+#define TIMER_IMR_TATOIM 0x00000001 // GPTM Timer A Time-Out Interrupt
+ // Mask.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_RIS register.
+//
+//*****************************************************************************
+#define TIMER_RIS_TBMRIS 0x00000800 // GPTM Timer B Mode Match Raw
+ // Interrupt.
+#define TIMER_RIS_CBERIS 0x00000400 // GPTM Capture B Event Raw
+ // Interrupt.
+#define TIMER_RIS_CBMRIS 0x00000200 // GPTM Capture B Match Raw
+ // Interrupt.
+#define TIMER_RIS_TBTORIS 0x00000100 // GPTM Timer B Time-Out Raw
+ // Interrupt.
+#define TIMER_RIS_TAMRIS 0x00000010 // GPTM Timer A Mode Match Raw
+ // Interrupt.
+#define TIMER_RIS_RTCRIS 0x00000008 // GPTM RTC Raw Interrupt.
+#define TIMER_RIS_CAERIS 0x00000004 // GPTM Capture A Event Raw
+ // Interrupt.
+#define TIMER_RIS_CAMRIS 0x00000002 // GPTM Capture A Match Raw
+ // Interrupt.
+#define TIMER_RIS_TATORIS 0x00000001 // GPTM Timer A Time-Out Raw
+ // Interrupt.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_MIS register.
+//
+//*****************************************************************************
+#define TIMER_MIS_TBMMIS 0x00000800 // GPTM Timer B Mode Match Masked
+ // Interrupt.
+#define TIMER_MIS_CBEMIS 0x00000400 // GPTM Capture B Event Masked
+ // Interrupt.
+#define TIMER_MIS_CBMMIS 0x00000200 // GPTM Capture B Match Masked
+ // Interrupt.
+#define TIMER_MIS_TBTOMIS 0x00000100 // GPTM Timer B Time-Out Masked
+ // Interrupt.
+#define TIMER_MIS_TAMMIS 0x00000010 // GPTM Timer A Mode Match Masked
+ // Interrupt.
+#define TIMER_MIS_RTCMIS 0x00000008 // GPTM RTC Masked Interrupt.
+#define TIMER_MIS_CAEMIS 0x00000004 // GPTM Capture A Event Masked
+ // Interrupt.
+#define TIMER_MIS_CAMMIS 0x00000002 // GPTM Capture A Match Masked
+ // Interrupt.
+#define TIMER_MIS_TATOMIS 0x00000001 // GPTM Timer A Time-Out Masked
+ // Interrupt.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_ICR register.
+//
+//*****************************************************************************
+#define TIMER_ICR_TBMCINT 0x00000800 // GPTM Timer B Mode Match
+ // Interrupt Clear.
+#define TIMER_ICR_CBECINT 0x00000400 // GPTM Capture B Event Interrupt
+ // Clear.
+#define TIMER_ICR_CBMCINT 0x00000200 // GPTM Capture B Match Interrupt
+ // Clear.
+#define TIMER_ICR_TBTOCINT 0x00000100 // GPTM Timer B Time-Out Interrupt
+ // Clear.
+#define TIMER_ICR_TAMCINT 0x00000010 // GPTM Timer A Mode Match
+ // Interrupt Clear.
+#define TIMER_ICR_RTCCINT 0x00000008 // GPTM RTC Interrupt Clear.
+#define TIMER_ICR_CAECINT 0x00000004 // GPTM Capture A Event Interrupt
+ // Clear.
+#define TIMER_ICR_CAMCINT 0x00000002 // GPTM Capture A Match Interrupt
+ // Clear.
+#define TIMER_ICR_TATOCINT 0x00000001 // GPTM Timer A Time-Out Raw
+ // Interrupt.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAILR register.
+//
+//*****************************************************************************
+#define TIMER_TAILR_TAILRH_M 0xFFFF0000 // GPTM Timer A Interval Load
+ // Register High.
+#define TIMER_TAILR_TAILRL_M 0x0000FFFF // GPTM Timer A Interval Load
+ // Register Low.
+#define TIMER_TAILR_TAILRH_S 16
+#define TIMER_TAILR_TAILRL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBILR register.
+//
+//*****************************************************************************
+#define TIMER_TBILR_TBILRL_M 0x0000FFFF // GPTM Timer B Interval Load
+ // Register.
+#define TIMER_TBILR_TBILRL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAMATCHR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TAMATCHR_TAMRH_M 0xFFFF0000 // GPTM Timer A Match Register
+ // High.
+#define TIMER_TAMATCHR_TAMRL_M 0x0000FFFF // GPTM Timer A Match Register Low.
+#define TIMER_TAMATCHR_TAMRH_S 16
+#define TIMER_TAMATCHR_TAMRL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBMATCHR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TBMATCHR_TBMRL_M 0x0000FFFF // GPTM Timer B Match Register Low.
+#define TIMER_TBMATCHR_TBMRL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAPR register.
+//
+//*****************************************************************************
+#define TIMER_TAPR_TAPSR_M 0x000000FF // GPTM Timer A Prescale.
+#define TIMER_TAPR_TAPSR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBPR register.
+//
+//*****************************************************************************
+#define TIMER_TBPR_TBPSR_M 0x000000FF // GPTM Timer B Prescale.
+#define TIMER_TBPR_TBPSR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAR register.
+//
+//*****************************************************************************
+#define TIMER_TAR_TARH_M 0xFFFF0000 // GPTM Timer A Register High.
+#define TIMER_TAR_TARL_M 0x0000FFFF // GPTM Timer A Register Low.
+#define TIMER_TAR_TARH_S 16
+#define TIMER_TAR_TARL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBR register.
+//
+//*****************************************************************************
+#define TIMER_TBR_TBRL_M 0x0000FFFF // GPTM Timer B.
+#define TIMER_TBR_TBRL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAV register.
+//
+//*****************************************************************************
+#define TIMER_TAV_TAVH_M 0xFFFF0000 // GPTM Timer A Value High.
+#define TIMER_TAV_TAVL_M 0x0000FFFF // GPTM Timer A Register Low.
+#define TIMER_TAV_TAVH_S 16
+#define TIMER_TAV_TAVL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBV register.
+//
+//*****************************************************************************
+#define TIMER_TBV_TBVL_M 0x0000FFFF // GPTM Timer B Register.
+#define TIMER_TBV_TBVL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_ACTSS register.
+//
+//*****************************************************************************
+#define ADC_ACTSS_ASEN3 0x00000008 // ADC SS3 Enable.
+#define ADC_ACTSS_ASEN2 0x00000004 // ADC SS2 Enable.
+#define ADC_ACTSS_ASEN1 0x00000002 // ADC SS1 Enable.
+#define ADC_ACTSS_ASEN0 0x00000001 // ADC SS0 Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_RIS register.
+//
+//*****************************************************************************
+#define ADC_RIS_INRDC 0x00010000 // Digital Comparator Raw Interrupt
+ // Status.
+#define ADC_RIS_INR3 0x00000008 // SS3 Raw Interrupt Status.
+#define ADC_RIS_INR2 0x00000004 // SS2 Raw Interrupt Status.
+#define ADC_RIS_INR1 0x00000002 // SS1 Raw Interrupt Status.
+#define ADC_RIS_INR0 0x00000001 // SS0 Raw Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_IM register.
+//
+//*****************************************************************************
+#define ADC_IM_DCONSS3 0x00080000 // Digital Comparator Interrupt on
+ // SS3.
+#define ADC_IM_DCONSS2 0x00040000 // Digital Comparator Interrupt on
+ // SS2.
+#define ADC_IM_DCONSS1 0x00020000 // Digital Comparator Interrupt on
+ // SS1.
+#define ADC_IM_DCONSS0 0x00010000 // Digital Comparator Interrupt on
+ // SS0.
+#define ADC_IM_MASK3 0x00000008 // SS3 Interrupt Mask.
+#define ADC_IM_MASK2 0x00000004 // SS2 Interrupt Mask.
+#define ADC_IM_MASK1 0x00000002 // SS1 Interrupt Mask.
+#define ADC_IM_MASK0 0x00000001 // SS0 Interrupt Mask.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_ISC register.
+//
+//*****************************************************************************
+#define ADC_ISC_DCINSS3 0x00080000 // Digital Comparator Interrupt
+ // Status on SS3.
+#define ADC_ISC_DCINSS2 0x00040000 // Digital Comparator Interrupt
+ // Status on SS2.
+#define ADC_ISC_DCINSS1 0x00020000 // Digital Comparator Interrupt
+ // Status on SS1.
+#define ADC_ISC_DCINSS0 0x00010000 // Digital Comparator Interrupt
+ // Status on SS0.
+#define ADC_ISC_IN3 0x00000008 // SS3 Interrupt Status and Clear.
+#define ADC_ISC_IN2 0x00000004 // SS2 Interrupt Status and Clear.
+#define ADC_ISC_IN1 0x00000002 // SS1 Interrupt Status and Clear.
+#define ADC_ISC_IN0 0x00000001 // SS0 Interrupt Status and Clear.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_OSTAT register.
+//
+//*****************************************************************************
+#define ADC_OSTAT_OV3 0x00000008 // SS3 FIFO Overflow.
+#define ADC_OSTAT_OV2 0x00000004 // SS2 FIFO Overflow.
+#define ADC_OSTAT_OV1 0x00000002 // SS1 FIFO Overflow.
+#define ADC_OSTAT_OV0 0x00000001 // SS0 FIFO Overflow.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_EMUX register.
+//
+//*****************************************************************************
+#define ADC_EMUX_EM3_M 0x0000F000 // SS3 Trigger Select.
+#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Processor (default)
+#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog Comparator 0
+#define ADC_EMUX_EM3_COMP1 0x00002000 // Analog Comparator 1
+#define ADC_EMUX_EM3_COMP2 0x00003000 // Analog Comparator 2
+#define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External (GPIO PB4)
+#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer
+#define ADC_EMUX_EM3_PWM0 0x00006000 // PWM0
+#define ADC_EMUX_EM3_PWM1 0x00007000 // PWM1
+#define ADC_EMUX_EM3_PWM2 0x00008000 // PWM2
+#define ADC_EMUX_EM3_PWM3 0x00009000 // PWM3
+#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always (continuously sample)
+#define ADC_EMUX_EM2_M 0x00000F00 // SS2 Trigger Select.
+#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Processor (default)
+#define ADC_EMUX_EM2_COMP0 0x00000100 // Analog Comparator 0
+#define ADC_EMUX_EM2_COMP1 0x00000200 // Analog Comparator 1
+#define ADC_EMUX_EM2_COMP2 0x00000300 // Analog Comparator 2
+#define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External (GPIO PB4)
+#define ADC_EMUX_EM2_TIMER 0x00000500 // Timer
+#define ADC_EMUX_EM2_PWM0 0x00000600 // PWM0
+#define ADC_EMUX_EM2_PWM1 0x00000700 // PWM1
+#define ADC_EMUX_EM2_PWM2 0x00000800 // PWM2
+#define ADC_EMUX_EM2_PWM3 0x00000900 // PWM3
+#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always (continuously sample)
+#define ADC_EMUX_EM1_M 0x000000F0 // SS1 Trigger Select.
+#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Processor (default)
+#define ADC_EMUX_EM1_COMP0 0x00000010 // Analog Comparator 0
+#define ADC_EMUX_EM1_COMP1 0x00000020 // Analog Comparator 1
+#define ADC_EMUX_EM1_COMP2 0x00000030 // Analog Comparator 2
+#define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External (GPIO PB4)
+#define ADC_EMUX_EM1_TIMER 0x00000050 // Timer
+#define ADC_EMUX_EM1_PWM0 0x00000060 // PWM0
+#define ADC_EMUX_EM1_PWM1 0x00000070 // PWM1
+#define ADC_EMUX_EM1_PWM2 0x00000080 // PWM2
+#define ADC_EMUX_EM1_PWM3 0x00000090 // PWM3
+#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always (continuously sample)
+#define ADC_EMUX_EM0_M 0x0000000F // SS0 Trigger Select.
+#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Processor (default)
+#define ADC_EMUX_EM0_COMP0 0x00000001 // Analog Comparator 0
+#define ADC_EMUX_EM0_COMP1 0x00000002 // Analog Comparator 1
+#define ADC_EMUX_EM0_COMP2 0x00000003 // Analog Comparator 2
+#define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External (GPIO PB4)
+#define ADC_EMUX_EM0_TIMER 0x00000005 // Timer
+#define ADC_EMUX_EM0_PWM0 0x00000006 // PWM0
+#define ADC_EMUX_EM0_PWM1 0x00000007 // PWM1
+#define ADC_EMUX_EM0_PWM2 0x00000008 // PWM2
+#define ADC_EMUX_EM0_PWM3 0x00000009 // PWM3
+#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always (continuously sample)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_USTAT register.
+//
+//*****************************************************************************
+#define ADC_USTAT_UV3 0x00000008 // SS3 FIFO Underflow.
+#define ADC_USTAT_UV2 0x00000004 // SS2 FIFO Underflow.
+#define ADC_USTAT_UV1 0x00000002 // SS1 FIFO Underflow.
+#define ADC_USTAT_UV0 0x00000001 // SS0 FIFO Underflow.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSPRI register.
+//
+//*****************************************************************************
+#define ADC_SSPRI_SS3_M 0x00003000 // SS3 Priority.
+#define ADC_SSPRI_SS3_1ST 0x00000000 // First priority
+#define ADC_SSPRI_SS3_2ND 0x00001000 // Second priority
+#define ADC_SSPRI_SS3_3RD 0x00002000 // Third priority
+#define ADC_SSPRI_SS3_4TH 0x00003000 // Fourth priority
+#define ADC_SSPRI_SS2_M 0x00000300 // SS2 Priority.
+#define ADC_SSPRI_SS2_1ST 0x00000000 // First priority
+#define ADC_SSPRI_SS2_2ND 0x00000100 // Second priority
+#define ADC_SSPRI_SS2_3RD 0x00000200 // Third priority
+#define ADC_SSPRI_SS2_4TH 0x00000300 // Fourth priority
+#define ADC_SSPRI_SS1_M 0x00000030 // SS1 Priority.
+#define ADC_SSPRI_SS1_1ST 0x00000000 // First priority
+#define ADC_SSPRI_SS1_2ND 0x00000010 // Second priority
+#define ADC_SSPRI_SS1_3RD 0x00000020 // Third priority
+#define ADC_SSPRI_SS1_4TH 0x00000030 // Fourth priority
+#define ADC_SSPRI_SS0_M 0x00000003 // SS0 Priority.
+#define ADC_SSPRI_SS0_1ST 0x00000000 // First priority
+#define ADC_SSPRI_SS0_2ND 0x00000001 // Second priority
+#define ADC_SSPRI_SS0_3RD 0x00000002 // Third priority
+#define ADC_SSPRI_SS0_4TH 0x00000003 // Fourth priority
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_PSSI register.
+//
+//*****************************************************************************
+#define ADC_PSSI_GSYNC 0x80000000 // Global Synchronize.
+#define ADC_PSSI_SYNCWAIT 0x08000000 // Synchronize Wait.
+#define ADC_PSSI_SS3 0x00000008 // SS3 Initiate.
+#define ADC_PSSI_SS2 0x00000004 // SS2 Initiate.
+#define ADC_PSSI_SS1 0x00000002 // SS1 Initiate.
+#define ADC_PSSI_SS0 0x00000001 // SS0 Initiate.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SAC register.
+//
+//*****************************************************************************
+#define ADC_SAC_AVG_M 0x00000007 // Hardware Averaging Control.
+#define ADC_SAC_AVG_OFF 0x00000000 // No hardware oversampling
+#define ADC_SAC_AVG_2X 0x00000001 // 2x hardware oversampling
+#define ADC_SAC_AVG_4X 0x00000002 // 4x hardware oversampling
+#define ADC_SAC_AVG_8X 0x00000003 // 8x hardware oversampling
+#define ADC_SAC_AVG_16X 0x00000004 // 16x hardware oversampling
+#define ADC_SAC_AVG_32X 0x00000005 // 32x hardware oversampling
+#define ADC_SAC_AVG_64X 0x00000006 // 64x hardware oversampling
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCISC register.
+//
+//*****************************************************************************
+#define ADC_DCISC_DCINT7 0x00000080 // Digital Comparator 7 Interrupt
+ // Status and Clear.
+#define ADC_DCISC_DCINT6 0x00000040 // Digital Comparator 6 Interrupt
+ // Status and Clear.
+#define ADC_DCISC_DCINT5 0x00000020 // Digital Comparator 5 Interrupt
+ // Status and Clear.
+#define ADC_DCISC_DCINT4 0x00000010 // Digital Comparator 4 Interrupt
+ // Status and Clear.
+#define ADC_DCISC_DCINT3 0x00000008 // Digital Comparator 3 Interrupt
+ // Status and Clear.
+#define ADC_DCISC_DCINT2 0x00000004 // Digital Comparator 2 Interrupt
+ // Status and Clear.
+#define ADC_DCISC_DCINT1 0x00000002 // Digital Comparator 1 Interrupt
+ // Status and Clear.
+#define ADC_DCISC_DCINT0 0x00000001 // Digital Comparator 0 Interrupt
+ // Status and Clear.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_CTL register.
+//
+//*****************************************************************************
+#define ADC_CTL_VREF 0x00000001 // Voltage Reference Select.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX0 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX0_MUX7_M 0xF0000000 // 8th Sample Input Select.
+#define ADC_SSMUX0_MUX6_M 0x0F000000 // 7th Sample Input Select.
+#define ADC_SSMUX0_MUX5_M 0x00F00000 // 6th Sample Input Select.
+#define ADC_SSMUX0_MUX4_M 0x000F0000 // 5th Sample Input Select.
+#define ADC_SSMUX0_MUX3_M 0x0000F000 // 4th Sample Input Select.
+#define ADC_SSMUX0_MUX2_M 0x00000F00 // 3rd Sample Input Select.
+#define ADC_SSMUX0_MUX1_M 0x000000F0 // 2nd Sample Input Select.
+#define ADC_SSMUX0_MUX0_M 0x0000000F // 1st Sample Input Select.
+#define ADC_SSMUX0_MUX7_S 28
+#define ADC_SSMUX0_MUX6_S 24
+#define ADC_SSMUX0_MUX5_S 20
+#define ADC_SSMUX0_MUX4_S 16
+#define ADC_SSMUX0_MUX3_S 12
+#define ADC_SSMUX0_MUX2_S 8
+#define ADC_SSMUX0_MUX1_S 4
+#define ADC_SSMUX0_MUX0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL0 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL0_TS7 0x80000000 // 8th Sample Temp Sensor Select.
+#define ADC_SSCTL0_IE7 0x40000000 // 8th Sample Interrupt Enable.
+#define ADC_SSCTL0_END7 0x20000000 // 8th Sample is End of Sequence.
+#define ADC_SSCTL0_D7 0x10000000 // 8th Sample Diff Input Select.
+#define ADC_SSCTL0_TS6 0x08000000 // 7th Sample Temp Sensor Select.
+#define ADC_SSCTL0_IE6 0x04000000 // 7th Sample Interrupt Enable.
+#define ADC_SSCTL0_END6 0x02000000 // 7th Sample is End of Sequence.
+#define ADC_SSCTL0_D6 0x01000000 // 7th Sample Diff Input Select.
+#define ADC_SSCTL0_TS5 0x00800000 // 6th Sample Temp Sensor Select.
+#define ADC_SSCTL0_IE5 0x00400000 // 6th Sample Interrupt Enable.
+#define ADC_SSCTL0_END5 0x00200000 // 6th Sample is End of Sequence.
+#define ADC_SSCTL0_D5 0x00100000 // 6th Sample Diff Input Select.
+#define ADC_SSCTL0_TS4 0x00080000 // 5th Sample Temp Sensor Select.
+#define ADC_SSCTL0_IE4 0x00040000 // 5th Sample Interrupt Enable.
+#define ADC_SSCTL0_END4 0x00020000 // 5th Sample is End of Sequence.
+#define ADC_SSCTL0_D4 0x00010000 // 5th Sample Diff Input Select.
+#define ADC_SSCTL0_TS3 0x00008000 // 4th Sample Temp Sensor Select.
+#define ADC_SSCTL0_IE3 0x00004000 // 4th Sample Interrupt Enable.
+#define ADC_SSCTL0_END3 0x00002000 // 4th Sample is End of Sequence.
+#define ADC_SSCTL0_D3 0x00001000 // 4th Sample Diff Input Select.
+#define ADC_SSCTL0_TS2 0x00000800 // 3rd Sample Temp Sensor Select.
+#define ADC_SSCTL0_IE2 0x00000400 // 3rd Sample Interrupt Enable.
+#define ADC_SSCTL0_END2 0x00000200 // 3rd Sample is End of Sequence.
+#define ADC_SSCTL0_D2 0x00000100 // 3rd Sample Diff Input Select.
+#define ADC_SSCTL0_TS1 0x00000080 // 2nd Sample Temp Sensor Select.
+#define ADC_SSCTL0_IE1 0x00000040 // 2nd Sample Interrupt Enable.
+#define ADC_SSCTL0_END1 0x00000020 // 2nd Sample is End of Sequence.
+#define ADC_SSCTL0_D1 0x00000010 // 2nd Sample Diff Input Select.
+#define ADC_SSCTL0_TS0 0x00000008 // 1st Sample Temp Sensor Select.
+#define ADC_SSCTL0_IE0 0x00000004 // 1st Sample Interrupt Enable.
+#define ADC_SSCTL0_END0 0x00000002 // 1st Sample is End of Sequence.
+#define ADC_SSCTL0_D0 0x00000001 // 1st Sample Diff Input Select.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO0 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO0_DATA_M 0x000003FF // Conversion Result Data.
+#define ADC_SSFIFO0_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT0 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT0_FULL 0x00001000 // FIFO Full.
+#define ADC_SSFSTAT0_EMPTY 0x00000100 // FIFO Empty.
+#define ADC_SSFSTAT0_HPTR_M 0x000000F0 // FIFO Head Pointer.
+#define ADC_SSFSTAT0_TPTR_M 0x0000000F // FIFO Tail Pointer.
+#define ADC_SSFSTAT0_HPTR_S 4
+#define ADC_SSFSTAT0_TPTR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSOP0 register.
+//
+//*****************************************************************************
+#define ADC_SSOP0_S7DCOP 0x10000000 // Sample 7 Digital Comparator
+ // Operation.
+#define ADC_SSOP0_S6DCOP 0x01000000 // Sample 6 Digital Comparator
+ // Operation.
+#define ADC_SSOP0_S5DCOP 0x00100000 // Sample 5 Digital Comparator
+ // Operation.
+#define ADC_SSOP0_S4DCOP 0x00010000 // Sample 4 Digital Comparator
+ // Operation.
+#define ADC_SSOP0_S3DCOP 0x00001000 // Sample 3 Digital Comparator
+ // Operation.
+#define ADC_SSOP0_S2DCOP 0x00000100 // Sample 2 Digital Comparator
+ // Operation.
+#define ADC_SSOP0_S1DCOP 0x00000010 // Sample 1 Digital Comparator
+ // Operation.
+#define ADC_SSOP0_S0DCOP 0x00000001 // Sample 0 Digital Comparator
+ // Operation.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSDC0 register.
+//
+//*****************************************************************************
+#define ADC_SSDC0_S7DCSEL_M 0xF0000000 // Sample 7 Digital Comparator
+ // Select.
+#define ADC_SSDC0_S7DCSEL_0 0x00000000 // Digital Comparator Unit 0
+ // (ADCDCCMP0 and ADCCCTL0)
+#define ADC_SSDC0_S7DCSEL_1 0x10000000 // Digital Comparator Unit 1
+ // (ADCDCCMP1 and ADCCCTL1)
+#define ADC_SSDC0_S7DCSEL_2 0x20000000 // Digital Comparator Unit 2
+ // (ADCDCCMP2 and ADCCCTL2)
+#define ADC_SSDC0_S7DCSEL_3 0x30000000 // Digital Comparator Unit 3
+ // (ADCDCCMP3 and ADCCCTL3)
+#define ADC_SSDC0_S7DCSEL_4 0x40000000 // Digital Comparator Unit 4
+ // (ADCDCCMP4 and ADCCCTL4)
+#define ADC_SSDC0_S7DCSEL_5 0x50000000 // Digital Comparator Unit 5
+ // (ADCDCCMP5 and ADCCCTL5)
+#define ADC_SSDC0_S7DCSEL_6 0x60000000 // Digital Comparator Unit 6
+ // (ADCDCCMP6 and ADCCCTL6)
+#define ADC_SSDC0_S7DCSEL_7 0x70000000 // Digital Comparator Unit 7
+ // (ADCDCCMP7 and ADCCCTL7)
+#define ADC_SSDC0_S6DCSEL_M 0x0F000000 // Sample 6 Digital Comparator
+ // Select.
+#define ADC_SSDC0_S5DCSEL_M 0x00F00000 // Sample 5 Digital Comparator
+ // Select.
+#define ADC_SSDC0_S4DCSEL_M 0x000F0000 // Sample 4 Digital Comparator
+ // Select.
+#define ADC_SSDC0_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator
+ // Select.
+#define ADC_SSDC0_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator
+ // Select.
+#define ADC_SSDC0_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator
+ // Select.
+#define ADC_SSDC0_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator
+ // Select.
+#define ADC_SSDC0_S6DCSEL_S 24
+#define ADC_SSDC0_S5DCSEL_S 20
+#define ADC_SSDC0_S4DCSEL_S 16
+#define ADC_SSDC0_S3DCSEL_S 12
+#define ADC_SSDC0_S2DCSEL_S 8
+#define ADC_SSDC0_S1DCSEL_S 4
+#define ADC_SSDC0_S0DCSEL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX1 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX1_MUX3_M 0x0000F000 // 4th Sample Input Select.
+#define ADC_SSMUX1_MUX2_M 0x00000F00 // 3rd Sample Input Select.
+#define ADC_SSMUX1_MUX1_M 0x000000F0 // 2nd Sample Input Select.
+#define ADC_SSMUX1_MUX0_M 0x0000000F // 1st Sample Input Select.
+#define ADC_SSMUX1_MUX3_S 12
+#define ADC_SSMUX1_MUX2_S 8
+#define ADC_SSMUX1_MUX1_S 4
+#define ADC_SSMUX1_MUX0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL1 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL1_TS3 0x00008000 // 4th Sample Temp Sensor Select.
+#define ADC_SSCTL1_IE3 0x00004000 // 4th Sample Interrupt Enable.
+#define ADC_SSCTL1_END3 0x00002000 // 4th Sample is End of Sequence.
+#define ADC_SSCTL1_D3 0x00001000 // 4th Sample Diff Input Select.
+#define ADC_SSCTL1_TS2 0x00000800 // 3rd Sample Temp Sensor Select.
+#define ADC_SSCTL1_IE2 0x00000400 // 3rd Sample Interrupt Enable.
+#define ADC_SSCTL1_END2 0x00000200 // 3rd Sample is End of Sequence.
+#define ADC_SSCTL1_D2 0x00000100 // 3rd Sample Diff Input Select.
+#define ADC_SSCTL1_TS1 0x00000080 // 2nd Sample Temp Sensor Select.
+#define ADC_SSCTL1_IE1 0x00000040 // 2nd Sample Interrupt Enable.
+#define ADC_SSCTL1_END1 0x00000020 // 2nd Sample is End of Sequence.
+#define ADC_SSCTL1_D1 0x00000010 // 2nd Sample Diff Input Select.
+#define ADC_SSCTL1_TS0 0x00000008 // 1st Sample Temp Sensor Select.
+#define ADC_SSCTL1_IE0 0x00000004 // 1st Sample Interrupt Enable.
+#define ADC_SSCTL1_END0 0x00000002 // 1st Sample is End of Sequence.
+#define ADC_SSCTL1_D0 0x00000001 // 1st Sample Diff Input Select.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO1 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO1_DATA_M 0x000003FF // Conversion Result Data.
+#define ADC_SSFIFO1_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT1 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT1_FULL 0x00001000 // FIFO Full.
+#define ADC_SSFSTAT1_EMPTY 0x00000100 // FIFO Empty.
+#define ADC_SSFSTAT1_HPTR_M 0x000000F0 // FIFO Head Pointer.
+#define ADC_SSFSTAT1_TPTR_M 0x0000000F // FIFO Tail Pointer.
+#define ADC_SSFSTAT1_HPTR_S 4
+#define ADC_SSFSTAT1_TPTR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSOP1 register.
+//
+//*****************************************************************************
+#define ADC_SSOP1_S3DCOP 0x00001000 // Sample 3 Digital Comparator
+ // Operation.
+#define ADC_SSOP1_S2DCOP 0x00000100 // Sample 2 Digital Comparator
+ // Operation.
+#define ADC_SSOP1_S1DCOP 0x00000010 // Sample 1 Digital Comparator
+ // Operation.
+#define ADC_SSOP1_S0DCOP 0x00000001 // Sample 0 Digital Comparator
+ // Operation.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSDC1 register.
+//
+//*****************************************************************************
+#define ADC_SSDC1_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator
+ // Select.
+#define ADC_SSDC1_S3DCSEL_0 0x00000000 // Digital Comparator Unit 0
+ // (ADCDCCMP0 and ADCCCTL0)
+#define ADC_SSDC1_S3DCSEL_1 0x00001000 // Digital Comparator Unit 1
+ // (ADCDCCMP1 and ADCCCTL1)
+#define ADC_SSDC1_S3DCSEL_2 0x00002000 // Digital Comparator Unit 2
+ // (ADCDCCMP2 and ADCCCTL2)
+#define ADC_SSDC1_S3DCSEL_3 0x00003000 // Digital Comparator Unit 3
+ // (ADCDCCMP3 and ADCCCTL3)
+#define ADC_SSDC1_S3DCSEL_4 0x00004000 // Digital Comparator Unit 4
+ // (ADCDCCMP4 and ADCCCTL4)
+#define ADC_SSDC1_S3DCSEL_5 0x00005000 // Digital Comparator Unit 5
+ // (ADCDCCMP5 and ADCCCTL5)
+#define ADC_SSDC1_S3DCSEL_6 0x00006000 // Digital Comparator Unit 6
+ // (ADCDCCMP6 and ADCCCTL6)
+#define ADC_SSDC1_S3DCSEL_7 0x00007000 // Digital Comparator Unit 7
+ // (ADCDCCMP7 and ADCCCTL7)
+#define ADC_SSDC1_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator
+ // Select.
+#define ADC_SSDC1_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator
+ // Select.
+#define ADC_SSDC1_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator
+ // Select.
+#define ADC_SSDC1_S2DCSEL_S 8
+#define ADC_SSDC1_S1DCSEL_S 4
+#define ADC_SSDC1_S0DCSEL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX2 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX2_MUX3_M 0x0000F000 // 4th Sample Input Select.
+#define ADC_SSMUX2_MUX2_M 0x00000F00 // 3rd Sample Input Select.
+#define ADC_SSMUX2_MUX1_M 0x000000F0 // 2nd Sample Input Select.
+#define ADC_SSMUX2_MUX0_M 0x0000000F // 1st Sample Input Select.
+#define ADC_SSMUX2_MUX3_S 12
+#define ADC_SSMUX2_MUX2_S 8
+#define ADC_SSMUX2_MUX1_S 4
+#define ADC_SSMUX2_MUX0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL2 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL2_TS3 0x00008000 // 4th Sample Temp Sensor Select.
+#define ADC_SSCTL2_IE3 0x00004000 // 4th Sample Interrupt Enable.
+#define ADC_SSCTL2_END3 0x00002000 // 4th Sample is End of Sequence.
+#define ADC_SSCTL2_D3 0x00001000 // 4th Sample Diff Input Select.
+#define ADC_SSCTL2_TS2 0x00000800 // 3rd Sample Temp Sensor Select.
+#define ADC_SSCTL2_IE2 0x00000400 // 3rd Sample Interrupt Enable.
+#define ADC_SSCTL2_END2 0x00000200 // 3rd Sample is End of Sequence.
+#define ADC_SSCTL2_D2 0x00000100 // 3rd Sample Diff Input Select.
+#define ADC_SSCTL2_TS1 0x00000080 // 2nd Sample Temp Sensor Select.
+#define ADC_SSCTL2_IE1 0x00000040 // 2nd Sample Interrupt Enable.
+#define ADC_SSCTL2_END1 0x00000020 // 2nd Sample is End of Sequence.
+#define ADC_SSCTL2_D1 0x00000010 // 2nd Sample Diff Input Select.
+#define ADC_SSCTL2_TS0 0x00000008 // 1st Sample Temp Sensor Select.
+#define ADC_SSCTL2_IE0 0x00000004 // 1st Sample Interrupt Enable.
+#define ADC_SSCTL2_END0 0x00000002 // 1st Sample is End of Sequence.
+#define ADC_SSCTL2_D0 0x00000001 // 1st Sample Diff Input Select.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO2 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO2_DATA_M 0x000003FF // Conversion Result Data.
+#define ADC_SSFIFO2_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT2 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT2_FULL 0x00001000 // FIFO Full.
+#define ADC_SSFSTAT2_EMPTY 0x00000100 // FIFO Empty.
+#define ADC_SSFSTAT2_HPTR_M 0x000000F0 // FIFO Head Pointer.
+#define ADC_SSFSTAT2_TPTR_M 0x0000000F // FIFO Tail Pointer.
+#define ADC_SSFSTAT2_HPTR_S 4
+#define ADC_SSFSTAT2_TPTR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSOP2 register.
+//
+//*****************************************************************************
+#define ADC_SSOP2_S3DCOP 0x00001000 // Sample 3 Digital Comparator
+ // Operation.
+#define ADC_SSOP2_S2DCOP 0x00000100 // Sample 2 Digital Comparator
+ // Operation.
+#define ADC_SSOP2_S1DCOP 0x00000010 // Sample 1 Digital Comparator
+ // Operation.
+#define ADC_SSOP2_S0DCOP 0x00000001 // Sample 0 Digital Comparator
+ // Operation.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSDC2 register.
+//
+//*****************************************************************************
+#define ADC_SSDC2_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator
+ // Select.
+#define ADC_SSDC2_S3DCSEL_0 0x00000000 // Digital Comparator Unit 0
+ // (ADCDCCMP0 and ADCCCTL0)
+#define ADC_SSDC2_S3DCSEL_1 0x00001000 // Digital Comparator Unit 1
+ // (ADCDCCMP1 and ADCCCTL1)
+#define ADC_SSDC2_S3DCSEL_2 0x00002000 // Digital Comparator Unit 2
+ // (ADCDCCMP2 and ADCCCTL2)
+#define ADC_SSDC2_S3DCSEL_3 0x00003000 // Digital Comparator Unit 3
+ // (ADCDCCMP3 and ADCCCTL3)
+#define ADC_SSDC2_S3DCSEL_4 0x00004000 // Digital Comparator Unit 4
+ // (ADCDCCMP4 and ADCCCTL4)
+#define ADC_SSDC2_S3DCSEL_5 0x00005000 // Digital Comparator Unit 5
+ // (ADCDCCMP5 and ADCCCTL5)
+#define ADC_SSDC2_S3DCSEL_6 0x00006000 // Digital Comparator Unit 6
+ // (ADCDCCMP6 and ADCCCTL6)
+#define ADC_SSDC2_S3DCSEL_7 0x00007000 // Digital Comparator Unit 7
+ // (ADCDCCMP7 and ADCCCTL7)
+#define ADC_SSDC2_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator
+ // Select.
+#define ADC_SSDC2_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator
+ // Select.
+#define ADC_SSDC2_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator
+ // Select.
+#define ADC_SSDC2_S2DCSEL_S 8
+#define ADC_SSDC2_S1DCSEL_S 4
+#define ADC_SSDC2_S0DCSEL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX3 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX3_MUX0_M 0x0000000F // 1st Sample Input Select.
+#define ADC_SSMUX3_MUX0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL3 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL3_TS0 0x00000008 // 1st Sample Temp Sensor Select.
+#define ADC_SSCTL3_IE0 0x00000004 // 1st Sample Interrupt Enable.
+#define ADC_SSCTL3_END0 0x00000002 // 1st Sample is End of Sequence.
+#define ADC_SSCTL3_D0 0x00000001 // 1st Sample Diff Input Select.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO3 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO3_DATA_M 0x000003FF // Conversion Result Data.
+#define ADC_SSFIFO3_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT3 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT3_FULL 0x00001000 // FIFO Full.
+#define ADC_SSFSTAT3_EMPTY 0x00000100 // FIFO Empty.
+#define ADC_SSFSTAT3_HPTR_M 0x000000F0 // FIFO Head Pointer.
+#define ADC_SSFSTAT3_TPTR_M 0x0000000F // FIFO Tail Pointer.
+#define ADC_SSFSTAT3_HPTR_S 4
+#define ADC_SSFSTAT3_TPTR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSOP3 register.
+//
+//*****************************************************************************
+#define ADC_SSOP3_S0DCOP 0x00000001 // Sample 0 Digital Comparator
+ // Operation.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSDC3 register.
+//
+//*****************************************************************************
+#define ADC_SSDC3_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator
+ // Select.
+#define ADC_SSDC3_S0DCSEL_0 0x00000000 // Digital Comparator Unit 0
+ // (ADCDCCMP0 and ADCCCTL0)
+#define ADC_SSDC3_S0DCSEL_1 0x00000001 // Digital Comparator Unit 1
+ // (ADCDCCMP1 and ADCCCTL1)
+#define ADC_SSDC3_S0DCSEL_2 0x00000002 // Digital Comparator Unit 2
+ // (ADCDCCMP2 and ADCCCTL2)
+#define ADC_SSDC3_S0DCSEL_3 0x00000003 // Digital Comparator Unit 3
+ // (ADCDCCMP3 and ADCCCTL3)
+#define ADC_SSDC3_S0DCSEL_4 0x00000004 // Digital Comparator Unit 4
+ // (ADCDCCMP4 and ADCCCTL4)
+#define ADC_SSDC3_S0DCSEL_5 0x00000005 // Digital Comparator Unit 5
+ // (ADCDCCMP5 and ADCCCTL5)
+#define ADC_SSDC3_S0DCSEL_6 0x00000006 // Digital Comparator Unit 6
+ // (ADCDCCMP6 and ADCCCTL6)
+#define ADC_SSDC3_S0DCSEL_7 0x00000007 // Digital Comparator Unit 7
+ // (ADCDCCMP7 and ADCCCTL7)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCRIC register.
+//
+//*****************************************************************************
+#define ADC_DCRIC_DCTRIG7 0x00800000 // Digital Comparator Trigger 7.
+#define ADC_DCRIC_DCTRIG6 0x00400000 // Digital Comparator Trigger 6.
+#define ADC_DCRIC_DCTRIG5 0x00200000 // Digital Comparator Trigger 5.
+#define ADC_DCRIC_DCTRIG4 0x00100000 // Digital Comparator Trigger 4.
+#define ADC_DCRIC_DCTRIG3 0x00080000 // Digital Comparator Trigger 3.
+#define ADC_DCRIC_DCTRIG2 0x00040000 // Digital Comparator Trigger 2.
+#define ADC_DCRIC_DCTRIG1 0x00020000 // Digital Comparator Trigger 1.
+#define ADC_DCRIC_DCTRIG0 0x00010000 // Digital Comparator Trigger 0.
+#define ADC_DCRIC_DCINT7 0x00000080 // Digital Comparator Trigger 7.
+#define ADC_DCRIC_DCINT6 0x00000040 // Digital Comparator Trigger 6.
+#define ADC_DCRIC_DCINT5 0x00000020 // Digital Comparator Trigger 5.
+#define ADC_DCRIC_DCINT4 0x00000010 // Digital Comparator Trigger 4.
+#define ADC_DCRIC_DCINT3 0x00000008 // Digital Comparator Trigger 3.
+#define ADC_DCRIC_DCINT2 0x00000004 // Digital Comparator Trigger 2.
+#define ADC_DCRIC_DCINT1 0x00000002 // Digital Comparator Trigger 1.
+#define ADC_DCRIC_DCINT0 0x00000001 // Digital Comparator Trigger 0.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL0 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL0_CTE 0x00001000 // Comparison Trigger Enable.
+#define ADC_DCCTL0_CTC_M 0x00000C00 // Comparison Trigger Condition.
+#define ADC_DCCTL0_CTC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL0_CTC_MID 0x00000400 // Mid Band
+#define ADC_DCCTL0_CTC_HIGH 0x00000C00 // High Band
+#define ADC_DCCTL0_CTM_M 0x00000300 // Comparison Trigger Mode.
+#define ADC_DCCTL0_CTM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL0_CTM_ONCE 0x00000100 // Once
+#define ADC_DCCTL0_CTM_HALWAYS 0x00000200 // Hysteresis Always
+#define ADC_DCCTL0_CTM_HONCE 0x00000300 // Hysteresis Once
+#define ADC_DCCTL0_CIE 0x00000010 // Comparison Interrupt Enable.
+#define ADC_DCCTL0_CIC_M 0x0000000C // Comparison Interrupt Condition.
+#define ADC_DCCTL0_CIC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL0_CIC_MID 0x00000004 // Mid Band
+#define ADC_DCCTL0_CIC_HIGH 0x0000000C // High Band
+#define ADC_DCCTL0_CIM_M 0x00000003 // Comparison Interrupt Mode.
+#define ADC_DCCTL0_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL0_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL0_CIM_HALWAYS 0x00000002 // Hysteresis Always
+#define ADC_DCCTL0_CIM_HONCE 0x00000003 // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL1 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL1_CTE 0x00001000 // Comparison Trigger Enable.
+#define ADC_DCCTL1_CTC_M 0x00000C00 // Comparison Trigger Condition.
+#define ADC_DCCTL1_CTC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL1_CTC_MID 0x00000400 // Mid Band
+#define ADC_DCCTL1_CTC_HIGH 0x00000C00 // High Band
+#define ADC_DCCTL1_CTM_M 0x00000300 // Comparison Trigger Mode.
+#define ADC_DCCTL1_CTM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL1_CTM_ONCE 0x00000100 // Once
+#define ADC_DCCTL1_CTM_HALWAYS 0x00000200 // Hysteresis Always
+#define ADC_DCCTL1_CTM_HONCE 0x00000300 // Hysteresis Once
+#define ADC_DCCTL1_CIE 0x00000010 // Comparison Interrupt Enable.
+#define ADC_DCCTL1_CIC_M 0x0000000C // Comparison Interrupt Condition.
+#define ADC_DCCTL1_CIC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL1_CIC_MID 0x00000004 // Mid Band
+#define ADC_DCCTL1_CIC_HIGH 0x0000000C // High Band
+#define ADC_DCCTL1_CIM_M 0x00000003 // Comparison Interrupt Mode.
+#define ADC_DCCTL1_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL1_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL1_CIM_HALWAYS 0x00000002 // Hysteresis Always
+#define ADC_DCCTL1_CIM_HONCE 0x00000003 // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL2 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL2_CTE 0x00001000 // Comparison Trigger Enable.
+#define ADC_DCCTL2_CTC_M 0x00000C00 // Comparison Trigger Condition.
+#define ADC_DCCTL2_CTC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL2_CTC_MID 0x00000400 // Mid Band
+#define ADC_DCCTL2_CTC_HIGH 0x00000C00 // High Band
+#define ADC_DCCTL2_CTM_M 0x00000300 // Comparison Trigger Mode.
+#define ADC_DCCTL2_CTM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL2_CTM_ONCE 0x00000100 // Once
+#define ADC_DCCTL2_CTM_HALWAYS 0x00000200 // Hysteresis Always
+#define ADC_DCCTL2_CTM_HONCE 0x00000300 // Hysteresis Once
+#define ADC_DCCTL2_CIE 0x00000010 // Comparison Interrupt Enable.
+#define ADC_DCCTL2_CIC_M 0x0000000C // Comparison Interrupt Condition.
+#define ADC_DCCTL2_CIC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL2_CIC_MID 0x00000004 // Mid Band
+#define ADC_DCCTL2_CIC_HIGH 0x0000000C // High Band
+#define ADC_DCCTL2_CIM_M 0x00000003 // Comparison Interrupt Mode.
+#define ADC_DCCTL2_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL2_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL2_CIM_HALWAYS 0x00000002 // Hysteresis Always
+#define ADC_DCCTL2_CIM_HONCE 0x00000003 // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL3 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL3_CTE 0x00001000 // Comparison Trigger Enable.
+#define ADC_DCCTL3_CTC_M 0x00000C00 // Comparison Trigger Condition.
+#define ADC_DCCTL3_CTC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL3_CTC_MID 0x00000400 // Mid Band
+#define ADC_DCCTL3_CTC_HIGH 0x00000C00 // High Band
+#define ADC_DCCTL3_CTM_M 0x00000300 // Comparison Trigger Mode.
+#define ADC_DCCTL3_CTM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL3_CTM_ONCE 0x00000100 // Once
+#define ADC_DCCTL3_CTM_HALWAYS 0x00000200 // Hysteresis Always
+#define ADC_DCCTL3_CTM_HONCE 0x00000300 // Hysteresis Once
+#define ADC_DCCTL3_CIE 0x00000010 // Comparison Interrupt Enable.
+#define ADC_DCCTL3_CIC_M 0x0000000C // Comparison Interrupt Condition.
+#define ADC_DCCTL3_CIC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL3_CIC_MID 0x00000004 // Mid Band
+#define ADC_DCCTL3_CIC_HIGH 0x0000000C // High Band
+#define ADC_DCCTL3_CIM_M 0x00000003 // Comparison Interrupt Mode.
+#define ADC_DCCTL3_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL3_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL3_CIM_HALWAYS 0x00000002 // Hysteresis Always
+#define ADC_DCCTL3_CIM_HONCE 0x00000003 // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL4 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL4_CTE 0x00001000 // Comparison Trigger Enable.
+#define ADC_DCCTL4_CTC_M 0x00000C00 // Comparison Trigger Condition.
+#define ADC_DCCTL4_CTC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL4_CTC_MID 0x00000400 // Mid Band
+#define ADC_DCCTL4_CTC_HIGH 0x00000C00 // High Band
+#define ADC_DCCTL4_CTM_M 0x00000300 // Comparison Trigger Mode.
+#define ADC_DCCTL4_CTM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL4_CTM_ONCE 0x00000100 // Once
+#define ADC_DCCTL4_CTM_HALWAYS 0x00000200 // Hysteresis Always
+#define ADC_DCCTL4_CTM_HONCE 0x00000300 // Hysteresis Once
+#define ADC_DCCTL4_CIE 0x00000010 // Comparison Interrupt Enable.
+#define ADC_DCCTL4_CIC_M 0x0000000C // Comparison Interrupt Condition.
+#define ADC_DCCTL4_CIC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL4_CIC_MID 0x00000004 // Mid Band
+#define ADC_DCCTL4_CIC_HIGH 0x0000000C // High Band
+#define ADC_DCCTL4_CIM_M 0x00000003 // Comparison Interrupt Mode.
+#define ADC_DCCTL4_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL4_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL4_CIM_HALWAYS 0x00000002 // Hysteresis Always
+#define ADC_DCCTL4_CIM_HONCE 0x00000003 // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL5 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL5_CTE 0x00001000 // Comparison Trigger Enable.
+#define ADC_DCCTL5_CTC_M 0x00000C00 // Comparison Trigger Condition.
+#define ADC_DCCTL5_CTC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL5_CTC_MID 0x00000400 // Mid Band
+#define ADC_DCCTL5_CTC_HIGH 0x00000C00 // High Band
+#define ADC_DCCTL5_CTM_M 0x00000300 // Comparison Trigger Mode.
+#define ADC_DCCTL5_CTM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL5_CTM_ONCE 0x00000100 // Once
+#define ADC_DCCTL5_CTM_HALWAYS 0x00000200 // Hysteresis Always
+#define ADC_DCCTL5_CTM_HONCE 0x00000300 // Hysteresis Once
+#define ADC_DCCTL5_CIE 0x00000010 // Comparison Interrupt Enable.
+#define ADC_DCCTL5_CIC_M 0x0000000C // Comparison Interrupt Condition.
+#define ADC_DCCTL5_CIC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL5_CIC_MID 0x00000004 // Mid Band
+#define ADC_DCCTL5_CIC_HIGH 0x0000000C // High Band
+#define ADC_DCCTL5_CIM_M 0x00000003 // Comparison Interrupt Mode.
+#define ADC_DCCTL5_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL5_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL5_CIM_HALWAYS 0x00000002 // Hysteresis Always
+#define ADC_DCCTL5_CIM_HONCE 0x00000003 // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL6 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL6_CTE 0x00001000 // Comparison Trigger Enable.
+#define ADC_DCCTL6_CTC_M 0x00000C00 // Comparison Trigger Condition.
+#define ADC_DCCTL6_CTC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL6_CTC_MID 0x00000400 // Mid Band
+#define ADC_DCCTL6_CTC_HIGH 0x00000C00 // High Band
+#define ADC_DCCTL6_CTM_M 0x00000300 // Comparison Trigger Mode.
+#define ADC_DCCTL6_CTM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL6_CTM_ONCE 0x00000100 // Once
+#define ADC_DCCTL6_CTM_HALWAYS 0x00000200 // Hysteresis Always
+#define ADC_DCCTL6_CTM_HONCE 0x00000300 // Hysteresis Once
+#define ADC_DCCTL6_CIE 0x00000010 // Comparison Interrupt Enable.
+#define ADC_DCCTL6_CIC_M 0x0000000C // Comparison Interrupt Condition.
+#define ADC_DCCTL6_CIC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL6_CIC_MID 0x00000004 // Mid Band
+#define ADC_DCCTL6_CIC_HIGH 0x0000000C // High Band
+#define ADC_DCCTL6_CIM_M 0x00000003 // Comparison Interrupt Mode.
+#define ADC_DCCTL6_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL6_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL6_CIM_HALWAYS 0x00000002 // Hysteresis Always
+#define ADC_DCCTL6_CIM_HONCE 0x00000003 // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL7 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL7_CTE 0x00001000 // Comparison Trigger Enable.
+#define ADC_DCCTL7_CTC_M 0x00000C00 // Comparison Trigger Condition.
+#define ADC_DCCTL7_CTC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL7_CTC_MID 0x00000400 // Mid Band
+#define ADC_DCCTL7_CTC_HIGH 0x00000C00 // High Band
+#define ADC_DCCTL7_CTM_M 0x00000300 // Comparison Trigger Mode.
+#define ADC_DCCTL7_CTM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL7_CTM_ONCE 0x00000100 // Once
+#define ADC_DCCTL7_CTM_HALWAYS 0x00000200 // Hysteresis Always
+#define ADC_DCCTL7_CTM_HONCE 0x00000300 // Hysteresis Once
+#define ADC_DCCTL7_CIE 0x00000010 // Comparison Interrupt Enable.
+#define ADC_DCCTL7_CIC_M 0x0000000C // Comparison Interrupt Condition.
+#define ADC_DCCTL7_CIC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL7_CIC_MID 0x00000004 // Mid Band
+#define ADC_DCCTL7_CIC_HIGH 0x0000000C // High Band
+#define ADC_DCCTL7_CIM_M 0x00000003 // Comparison Interrupt Mode.
+#define ADC_DCCTL7_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL7_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL7_CIM_HALWAYS 0x00000002 // Hysteresis Always
+#define ADC_DCCTL7_CIM_HONCE 0x00000003 // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP0 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP0_COMP1_M 0x03FF0000 // Compare 1.
+#define ADC_DCCMP0_COMP0_M 0x000003FF // Compare 0.
+#define ADC_DCCMP0_COMP1_S 16
+#define ADC_DCCMP0_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP1 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP1_COMP1_M 0x03FF0000 // Compare 1.
+#define ADC_DCCMP1_COMP0_M 0x000003FF // Compare 0.
+#define ADC_DCCMP1_COMP1_S 16
+#define ADC_DCCMP1_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP2 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP2_COMP1_M 0x03FF0000 // Compare 1.
+#define ADC_DCCMP2_COMP0_M 0x000003FF // Compare 0.
+#define ADC_DCCMP2_COMP1_S 16
+#define ADC_DCCMP2_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP3 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP3_COMP1_M 0x03FF0000 // Compare 1.
+#define ADC_DCCMP3_COMP0_M 0x000003FF // Compare 0.
+#define ADC_DCCMP3_COMP1_S 16
+#define ADC_DCCMP3_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP4 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP4_COMP1_M 0x03FF0000 // Compare 1.
+#define ADC_DCCMP4_COMP0_M 0x000003FF // Compare 0.
+#define ADC_DCCMP4_COMP1_S 16
+#define ADC_DCCMP4_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP5 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP5_COMP1_M 0x03FF0000 // Compare 1.
+#define ADC_DCCMP5_COMP0_M 0x000003FF // Compare 0.
+#define ADC_DCCMP5_COMP1_S 16
+#define ADC_DCCMP5_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP6 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP6_COMP1_M 0x03FF0000 // Compare 1.
+#define ADC_DCCMP6_COMP0_M 0x000003FF // Compare 0.
+#define ADC_DCCMP6_COMP1_S 16
+#define ADC_DCCMP6_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP7 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP7_COMP1_M 0x03FF0000 // Compare 1.
+#define ADC_DCCMP7_COMP0_M 0x000003FF // Compare 0.
+#define ADC_DCCMP7_COMP1_S 16
+#define ADC_DCCMP7_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the the interpretation of the data in the
+// SSFIFOx when the ADC TMLB is enabled.
+//
+//*****************************************************************************
+#define ADC_SSFIFO_TMLB_CNT_M 0x000003C0 // Continuous Sample Counter.
+#define ADC_SSFIFO_TMLB_CONT 0x00000020 // Continuation Sample Indicator.
+#define ADC_SSFIFO_TMLB_DIFF 0x00000010 // Differential Sample Indicator.
+#define ADC_SSFIFO_TMLB_TS 0x00000008 // Temp Sensor Sample Indicator.
+#define ADC_SSFIFO_TMLB_MUX_M 0x00000007 // Analog Input Indicator.
+#define ADC_SSFIFO_TMLB_CNT_S 6 // Sample counter shift
+#define ADC_SSFIFO_TMLB_MUX_S 0 // Input channel number shift
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACMIS register.
+//
+//*****************************************************************************
+#define COMP_ACMIS_IN2 0x00000004 // Comparator 2 Masked Interrupt
+ // Status.
+#define COMP_ACMIS_IN1 0x00000002 // Comparator 1 Masked Interrupt
+ // Status.
+#define COMP_ACMIS_IN0 0x00000001 // Comparator 0 Masked Interrupt
+ // Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACRIS register.
+//
+//*****************************************************************************
+#define COMP_ACRIS_IN2 0x00000004 // Comparator 2 Interrupt Status.
+#define COMP_ACRIS_IN1 0x00000002 // Comparator 1 Interrupt Status.
+#define COMP_ACRIS_IN0 0x00000001 // Comparator 0 Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACINTEN register.
+//
+//*****************************************************************************
+#define COMP_ACINTEN_IN2 0x00000004 // Comparator 2 Interrupt Enable.
+#define COMP_ACINTEN_IN1 0x00000002 // Comparator 1 Interrupt Enable.
+#define COMP_ACINTEN_IN0 0x00000001 // Comparator 0 Interrupt Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACREFCTL
+// register.
+//
+//*****************************************************************************
+#define COMP_ACREFCTL_EN 0x00000200 // Resistor Ladder Enable.
+#define COMP_ACREFCTL_RNG 0x00000100 // Resistor Ladder Range.
+#define COMP_ACREFCTL_VREF_M 0x0000000F // Resistor Ladder Voltage Ref.
+#define COMP_ACREFCTL_VREF_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACSTAT0 register.
+//
+//*****************************************************************************
+#define COMP_ACSTAT0_OVAL 0x00000002 // Comparator Output Value.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACCTL0 register.
+//
+//*****************************************************************************
+#define COMP_ACCTL0_TOEN 0x00000800 // Trigger Output Enable.
+#define COMP_ACCTL0_ASRCP_M 0x00000600 // Analog Source Positive.
+#define COMP_ACCTL0_ASRCP_PIN 0x00000000 // Pin value
+#define COMP_ACCTL0_ASRCP_PIN0 0x00000200 // Pin value of C0+
+#define COMP_ACCTL0_ASRCP_REF 0x00000400 // Internal voltage reference
+ // (VIREF)
+#define COMP_ACCTL0_TSLVAL 0x00000080 // Trigger Sense Level Value.
+#define COMP_ACCTL0_TSEN_M 0x00000060 // Trigger Sense.
+#define COMP_ACCTL0_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL
+#define COMP_ACCTL0_TSEN_FALL 0x00000020 // Falling edge
+#define COMP_ACCTL0_TSEN_RISE 0x00000040 // Rising edge
+#define COMP_ACCTL0_TSEN_BOTH 0x00000060 // Either edge
+#define COMP_ACCTL0_ISLVAL 0x00000010 // Interrupt Sense Level Value.
+#define COMP_ACCTL0_ISEN_M 0x0000000C // Interrupt Sense.
+#define COMP_ACCTL0_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL
+#define COMP_ACCTL0_ISEN_FALL 0x00000004 // Falling edge
+#define COMP_ACCTL0_ISEN_RISE 0x00000008 // Rising edge
+#define COMP_ACCTL0_ISEN_BOTH 0x0000000C // Either edge
+#define COMP_ACCTL0_CINV 0x00000002 // Comparator Output Invert.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACSTAT1 register.
+//
+//*****************************************************************************
+#define COMP_ACSTAT1_OVAL 0x00000002 // Comparator Output Value.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACCTL1 register.
+//
+//*****************************************************************************
+#define COMP_ACCTL1_TOEN 0x00000800 // Trigger Output Enable.
+#define COMP_ACCTL1_ASRCP_M 0x00000600 // Analog Source Positive.
+#define COMP_ACCTL1_ASRCP_PIN 0x00000000 // Pin value
+#define COMP_ACCTL1_ASRCP_PIN0 0x00000200 // Pin value of C0+
+#define COMP_ACCTL1_ASRCP_REF 0x00000400 // Internal voltage reference
+ // (VIREF)
+#define COMP_ACCTL1_TSLVAL 0x00000080 // Trigger Sense Level Value.
+#define COMP_ACCTL1_TSEN_M 0x00000060 // Trigger Sense.
+#define COMP_ACCTL1_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL
+#define COMP_ACCTL1_TSEN_FALL 0x00000020 // Falling edge
+#define COMP_ACCTL1_TSEN_RISE 0x00000040 // Rising edge
+#define COMP_ACCTL1_TSEN_BOTH 0x00000060 // Either edge
+#define COMP_ACCTL1_ISLVAL 0x00000010 // Interrupt Sense Level Value.
+#define COMP_ACCTL1_ISEN_M 0x0000000C // Interrupt Sense.
+#define COMP_ACCTL1_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL
+#define COMP_ACCTL1_ISEN_FALL 0x00000004 // Falling edge
+#define COMP_ACCTL1_ISEN_RISE 0x00000008 // Rising edge
+#define COMP_ACCTL1_ISEN_BOTH 0x0000000C // Either edge
+#define COMP_ACCTL1_CINV 0x00000002 // Comparator Output Invert.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACSTAT2 register.
+//
+//*****************************************************************************
+#define COMP_ACSTAT2_OVAL 0x00000002 // Comparator Output Value.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACCTL2 register.
+//
+//*****************************************************************************
+#define COMP_ACCTL2_TOEN 0x00000800 // Trigger Output Enable.
+#define COMP_ACCTL2_ASRCP_M 0x00000600 // Analog Source Positive.
+#define COMP_ACCTL2_ASRCP_PIN 0x00000000 // Pin value
+#define COMP_ACCTL2_ASRCP_PIN0 0x00000200 // Pin value of C0+
+#define COMP_ACCTL2_ASRCP_REF 0x00000400 // Internal voltage reference
+ // (VIREF)
+#define COMP_ACCTL2_TSLVAL 0x00000080 // Trigger Sense Level Value.
+#define COMP_ACCTL2_TSEN_M 0x00000060 // Trigger Sense.
+#define COMP_ACCTL2_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL
+#define COMP_ACCTL2_TSEN_FALL 0x00000020 // Falling edge
+#define COMP_ACCTL2_TSEN_RISE 0x00000040 // Rising edge
+#define COMP_ACCTL2_TSEN_BOTH 0x00000060 // Either edge
+#define COMP_ACCTL2_ISLVAL 0x00000010 // Interrupt Sense Level Value.
+#define COMP_ACCTL2_ISEN_M 0x0000000C // Interrupt Sense.
+#define COMP_ACCTL2_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL
+#define COMP_ACCTL2_ISEN_FALL 0x00000004 // Falling edge
+#define COMP_ACCTL2_ISEN_RISE 0x00000008 // Rising edge
+#define COMP_ACCTL2_ISEN_BOTH 0x0000000C // Either edge
+#define COMP_ACCTL2_CINV 0x00000002 // Comparator Output Invert.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_CTL register.
+//
+//*****************************************************************************
+#define CAN_CTL_TEST 0x00000080 // Test Mode Enable.
+#define CAN_CTL_CCE 0x00000040 // Configuration Change Enable.
+#define CAN_CTL_DAR 0x00000020 // Disable
+ // Automatic-Retransmission.
+#define CAN_CTL_EIE 0x00000008 // Error Interrupt Enable.
+#define CAN_CTL_SIE 0x00000004 // Status Interrupt Enable.
+#define CAN_CTL_IE 0x00000002 // CAN Interrupt Enable.
+#define CAN_CTL_INIT 0x00000001 // Initialization.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_STS register.
+//
+//*****************************************************************************
+#define CAN_STS_BOFF 0x00000080 // Bus-Off Status.
+#define CAN_STS_EWARN 0x00000040 // Warning Status.
+#define CAN_STS_EPASS 0x00000020 // Error Passive.
+#define CAN_STS_RXOK 0x00000010 // Received a Message Successfully.
+#define CAN_STS_TXOK 0x00000008 // Transmitted a Message
+ // Successfully.
+#define CAN_STS_LEC_M 0x00000007 // Last Error Code.
+#define CAN_STS_LEC_NONE 0x00000000 // No Error
+#define CAN_STS_LEC_STUFF 0x00000001 // Stuff Error
+#define CAN_STS_LEC_FORM 0x00000002 // Format Error
+#define CAN_STS_LEC_ACK 0x00000003 // ACK Error
+#define CAN_STS_LEC_BIT1 0x00000004 // Bit 1 Error
+#define CAN_STS_LEC_BIT0 0x00000005 // Bit 0 Error
+#define CAN_STS_LEC_CRC 0x00000006 // CRC Error
+#define CAN_STS_LEC_NOEVENT 0x00000007 // Unused
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_ERR register.
+//
+//*****************************************************************************
+#define CAN_ERR_RP 0x00008000 // Received Error Passive.
+#define CAN_ERR_REC_M 0x00007F00 // Receive Error Counter.
+#define CAN_ERR_TEC_M 0x000000FF // Transmit Error Counter.
+#define CAN_ERR_REC_S 8
+#define CAN_ERR_TEC_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_BIT register.
+//
+//*****************************************************************************
+#define CAN_BIT_TSEG2_M 0x00007000 // Time Segment after Sample Point.
+#define CAN_BIT_TSEG1_M 0x00000F00 // Time Segment Before Sample
+ // Point.
+#define CAN_BIT_SJW_M 0x000000C0 // (Re)Synchronization Jump Width.
+#define CAN_BIT_BRP_M 0x0000003F // Baud Rate Prescaler.
+#define CAN_BIT_TSEG2_S 12
+#define CAN_BIT_TSEG1_S 8
+#define CAN_BIT_SJW_S 6
+#define CAN_BIT_BRP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_INT register.
+//
+//*****************************************************************************
+#define CAN_INT_INTID_M 0x0000FFFF // Interrupt Identifier.
+#define CAN_INT_INTID_NONE 0x00000000 // No interrupt pending
+#define CAN_INT_INTID_STATUS 0x00008000 // Status Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_TST register.
+//
+//*****************************************************************************
+#define CAN_TST_RX 0x00000080 // Receive Observation.
+#define CAN_TST_TX_M 0x00000060 // Transmit Control.
+#define CAN_TST_TX_CANCTL 0x00000000 // CANnTx is controlled by the CAN
+ // module; default operation
+#define CAN_TST_TX_SAMPLE 0x00000020 // The sample point is driven on
+ // the CANnTx signal. This mode is
+ // useful to monitor bit timing.
+#define CAN_TST_TX_DOMINANT 0x00000040 // CANnTx drives a low value. This
+ // mode is useful for checking the
+ // physical layer of the CAN bus.
+#define CAN_TST_TX_RECESSIVE 0x00000060 // CANnTx drives a high value. This
+ // mode is useful for checking the
+ // physical layer of the CAN bus.
+#define CAN_TST_LBACK 0x00000010 // Loopback Mode.
+#define CAN_TST_SILENT 0x00000008 // Silent Mode.
+#define CAN_TST_BASIC 0x00000004 // Basic Mode.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_BRPE register.
+//
+//*****************************************************************************
+#define CAN_BRPE_BRPE_M 0x0000000F // Baud Rate Prescaler Extension.
+#define CAN_BRPE_BRPE_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1CRQ register.
+//
+//*****************************************************************************
+#define CAN_IF1CRQ_BUSY 0x00008000 // Busy Flag.
+#define CAN_IF1CRQ_MNUM_M 0x0000003F // Message Number.
+#define CAN_IF1CRQ_MNUM_RSVD 0x00000000 // 0 is not a valid message number;
+ // it is interpreted as 0x20, or
+ // object 32.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1CMSK register.
+//
+//*****************************************************************************
+#define CAN_IF1CMSK_WRNRD 0x00000080 // Write, Not Read.
+#define CAN_IF1CMSK_MASK 0x00000040 // Access Mask Bits.
+#define CAN_IF1CMSK_ARB 0x00000020 // Access Arbitration Bits.
+#define CAN_IF1CMSK_CONTROL 0x00000010 // Access Control Bits.
+#define CAN_IF1CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit.
+#define CAN_IF1CMSK_NEWDAT 0x00000004 // NEWDAT
+#define CAN_IF1CMSK_TXRQST 0x00000004 // TXRQST Bit.
+#define CAN_IF1CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3.
+#define CAN_IF1CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1MSK1 register.
+//
+//*****************************************************************************
+#define CAN_IF1MSK1_IDMSK_M 0x0000FFFF // Identifier Mask.
+#define CAN_IF1MSK1_IDMSK_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1MSK2 register.
+//
+//*****************************************************************************
+#define CAN_IF1MSK2_MXTD 0x00008000 // Mask Extended Identifier.
+#define CAN_IF1MSK2_MDIR 0x00004000 // Mask Message Direction.
+#define CAN_IF1MSK2_IDMSK_M 0x00001FFF // Identifier Mask.
+#define CAN_IF1MSK2_IDMSK_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1ARB1 register.
+//
+//*****************************************************************************
+#define CAN_IF1ARB1_ID_M 0x0000FFFF // Message Identifier.
+#define CAN_IF1ARB1_ID_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1ARB2 register.
+//
+//*****************************************************************************
+#define CAN_IF1ARB2_MSGVAL 0x00008000 // Message Valid.
+#define CAN_IF1ARB2_XTD 0x00004000 // Extended Identifier.
+#define CAN_IF1ARB2_DIR 0x00002000 // Message Direction.
+#define CAN_IF1ARB2_ID_M 0x00001FFF // Message Identifier.
+#define CAN_IF1ARB2_ID_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1MCTL register.
+//
+//*****************************************************************************
+#define CAN_IF1MCTL_NEWDAT 0x00008000 // New Data.
+#define CAN_IF1MCTL_MSGLST 0x00004000 // Message Lost.
+#define CAN_IF1MCTL_INTPND 0x00002000 // Interrupt Pending.
+#define CAN_IF1MCTL_UMASK 0x00001000 // Use Acceptance Mask.
+#define CAN_IF1MCTL_TXIE 0x00000800 // Transmit Interrupt Enable.
+#define CAN_IF1MCTL_RXIE 0x00000400 // Receive Interrupt Enable.
+#define CAN_IF1MCTL_RMTEN 0x00000200 // Remote Enable.
+#define CAN_IF1MCTL_TXRQST 0x00000100 // Transmit Request.
+#define CAN_IF1MCTL_EOB 0x00000080 // End of Buffer.
+#define CAN_IF1MCTL_DLC_M 0x0000000F // Data Length Code.
+#define CAN_IF1MCTL_DLC_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1DA1 register.
+//
+//*****************************************************************************
+#define CAN_IF1DA1_DATA_M 0x0000FFFF // Data.
+#define CAN_IF1DA1_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1DA2 register.
+//
+//*****************************************************************************
+#define CAN_IF1DA2_DATA_M 0x0000FFFF // Data.
+#define CAN_IF1DA2_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1DB1 register.
+//
+//*****************************************************************************
+#define CAN_IF1DB1_DATA_M 0x0000FFFF // Data.
+#define CAN_IF1DB1_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1DB2 register.
+//
+//*****************************************************************************
+#define CAN_IF1DB2_DATA_M 0x0000FFFF // Data.
+#define CAN_IF1DB2_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2CRQ register.
+//
+//*****************************************************************************
+#define CAN_IF2CRQ_BUSY 0x00008000 // Busy Flag.
+#define CAN_IF2CRQ_MNUM_M 0x0000003F // Message Number.
+#define CAN_IF2CRQ_MNUM_RSVD 0x00000000 // 0 is not a valid message number;
+ // it is interpreted as 0x20, or
+ // object 32.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2CMSK register.
+//
+//*****************************************************************************
+#define CAN_IF2CMSK_WRNRD 0x00000080 // Write, Not Read.
+#define CAN_IF2CMSK_MASK 0x00000040 // Access Mask Bits.
+#define CAN_IF2CMSK_ARB 0x00000020 // Access Arbitration Bits.
+#define CAN_IF2CMSK_CONTROL 0x00000010 // Access Control Bits.
+#define CAN_IF2CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit.
+#define CAN_IF2CMSK_NEWDAT 0x00000004 // NEWDAT
+#define CAN_IF2CMSK_TXRQST 0x00000004 // TXRQST Bit.
+#define CAN_IF2CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3.
+#define CAN_IF2CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2MSK1 register.
+//
+//*****************************************************************************
+#define CAN_IF2MSK1_IDMSK_M 0x0000FFFF // Identifier Mask.
+#define CAN_IF2MSK1_IDMSK_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2MSK2 register.
+//
+//*****************************************************************************
+#define CAN_IF2MSK2_MXTD 0x00008000 // Mask Extended Identifier.
+#define CAN_IF2MSK2_MDIR 0x00004000 // Mask Message Direction.
+#define CAN_IF2MSK2_IDMSK_M 0x00001FFF // Identifier Mask.
+#define CAN_IF2MSK2_IDMSK_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2ARB1 register.
+//
+//*****************************************************************************
+#define CAN_IF2ARB1_ID_M 0x0000FFFF // Message Identifier.
+#define CAN_IF2ARB1_ID_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2ARB2 register.
+//
+//*****************************************************************************
+#define CAN_IF2ARB2_MSGVAL 0x00008000 // Message Valid.
+#define CAN_IF2ARB2_XTD 0x00004000 // Extended Identifier.
+#define CAN_IF2ARB2_DIR 0x00002000 // Message Direction.
+#define CAN_IF2ARB2_ID_M 0x00001FFF // Message Identifier.
+#define CAN_IF2ARB2_ID_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2MCTL register.
+//
+//*****************************************************************************
+#define CAN_IF2MCTL_NEWDAT 0x00008000 // New Data.
+#define CAN_IF2MCTL_MSGLST 0x00004000 // Message Lost.
+#define CAN_IF2MCTL_INTPND 0x00002000 // Interrupt Pending.
+#define CAN_IF2MCTL_UMASK 0x00001000 // Use Acceptance Mask.
+#define CAN_IF2MCTL_TXIE 0x00000800 // Transmit Interrupt Enable.
+#define CAN_IF2MCTL_RXIE 0x00000400 // Receive Interrupt Enable.
+#define CAN_IF2MCTL_RMTEN 0x00000200 // Remote Enable.
+#define CAN_IF2MCTL_TXRQST 0x00000100 // Transmit Request.
+#define CAN_IF2MCTL_EOB 0x00000080 // End of Buffer.
+#define CAN_IF2MCTL_DLC_M 0x0000000F // Data Length Code.
+#define CAN_IF2MCTL_DLC_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2DA1 register.
+//
+//*****************************************************************************
+#define CAN_IF2DA1_DATA_M 0x0000FFFF // Data.
+#define CAN_IF2DA1_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2DA2 register.
+//
+//*****************************************************************************
+#define CAN_IF2DA2_DATA_M 0x0000FFFF // Data.
+#define CAN_IF2DA2_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2DB1 register.
+//
+//*****************************************************************************
+#define CAN_IF2DB1_DATA_M 0x0000FFFF // Data.
+#define CAN_IF2DB1_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2DB2 register.
+//
+//*****************************************************************************
+#define CAN_IF2DB2_DATA_M 0x0000FFFF // Data.
+#define CAN_IF2DB2_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_TXRQ1 register.
+//
+//*****************************************************************************
+#define CAN_TXRQ1_TXRQST_M 0x0000FFFF // Transmission Request Bits.
+#define CAN_TXRQ1_TXRQST_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_TXRQ2 register.
+//
+//*****************************************************************************
+#define CAN_TXRQ2_TXRQST_M 0x0000FFFF // Transmission Request Bits.
+#define CAN_TXRQ2_TXRQST_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_NWDA1 register.
+//
+//*****************************************************************************
+#define CAN_NWDA1_NEWDAT_M 0x0000FFFF // New Data Bits.
+#define CAN_NWDA1_NEWDAT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_NWDA2 register.
+//
+//*****************************************************************************
+#define CAN_NWDA2_NEWDAT_M 0x0000FFFF // New Data Bits.
+#define CAN_NWDA2_NEWDAT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_MSG1INT register.
+//
+//*****************************************************************************
+#define CAN_MSG1INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits.
+#define CAN_MSG1INT_INTPND_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_MSG2INT register.
+//
+//*****************************************************************************
+#define CAN_MSG2INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits.
+#define CAN_MSG2INT_INTPND_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_MSG1VAL register.
+//
+//*****************************************************************************
+#define CAN_MSG1VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits.
+#define CAN_MSG1VAL_MSGVAL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_MSG2VAL register.
+//
+//*****************************************************************************
+#define CAN_MSG2VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits.
+#define CAN_MSG2VAL_MSGVAL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MR0 register.
+//
+//*****************************************************************************
+#define PHY_MR0_RESET 0x00008000 // Reset Registers.
+#define PHY_MR0_LOOPBK 0x00004000 // Loopback Mode.
+#define PHY_MR0_SPEEDSL 0x00002000 // Speed Select.
+#define PHY_MR0_ANEGEN 0x00001000 // Auto-Negotiation Enable.
+#define PHY_MR0_PWRDN 0x00000800 // Power Down.
+#define PHY_MR0_ISO 0x00000400 // Isolate.
+#define PHY_MR0_RANEG 0x00000200 // Restart Auto-Negotiation.
+#define PHY_MR0_DUPLEX 0x00000100 // Set Duplex Mode.
+#define PHY_MR0_COLT 0x00000080 // Collision Test.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_RIS register.
+//
+//*****************************************************************************
+#define MAC_RIS_PHYINT 0x00000040 // PHY Interrupt.
+#define MAC_RIS_MDINT 0x00000020 // MII Transaction Complete.
+#define MAC_RIS_RXER 0x00000010 // Receive Error.
+#define MAC_RIS_FOV 0x00000008 // FIFO Overrun.
+#define MAC_RIS_TXEMP 0x00000004 // Transmit FIFO Empty.
+#define MAC_RIS_TXER 0x00000002 // Transmit Error.
+#define MAC_RIS_RXINT 0x00000001 // Packet Received.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_IACK register.
+//
+//*****************************************************************************
+#define MAC_IACK_PHYINT 0x00000040 // Clear PHY Interrupt.
+#define MAC_IACK_MDINT 0x00000020 // Clear MII Transaction Complete.
+#define MAC_IACK_RXER 0x00000010 // Clear Receive Error.
+#define MAC_IACK_FOV 0x00000008 // Clear FIFO Overrun.
+#define MAC_IACK_TXEMP 0x00000004 // Clear Transmit FIFO Empty.
+#define MAC_IACK_TXER 0x00000002 // Clear Transmit Error.
+#define MAC_IACK_RXINT 0x00000001 // Clear Packet Received.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MR1 register.
+//
+//*****************************************************************************
+#define PHY_MR1_100X_F 0x00004000 // 100BASE-TX Full-Duplex Mode.
+#define PHY_MR1_100X_H 0x00002000 // 100BASE-TX Half-Duplex Mode.
+#define PHY_MR1_10T_F 0x00001000 // 10BASE-T Full-Duplex Mode.
+#define PHY_MR1_10T_H 0x00000800 // 10BASE-T Half-Duplex Mode.
+#define PHY_MR1_ANEGC 0x00000020 // Auto-Negotiation Complete.
+#define PHY_MR1_RFAULT 0x00000010 // Remote Fault.
+#define PHY_MR1_ANEGA 0x00000008 // Auto-Negotiation.
+#define PHY_MR1_LINK 0x00000004 // Link Made.
+#define PHY_MR1_JAB 0x00000002 // Jabber Condition.
+#define PHY_MR1_EXTD 0x00000001 // Extended Capabilities.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MR2 register.
+//
+//*****************************************************************************
+#define PHY_MR2_OUI_M 0x0000FFFF // Organizationally Unique
+ // Identifier[21:6].
+#define PHY_MR2_OUI_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MR3 register.
+//
+//*****************************************************************************
+#define PHY_MR3_OUI_M 0x0000FC00 // Organizationally Unique
+ // Identifier[5:0].
+#define PHY_MR3_MN_M 0x000003F0 // Model Number.
+#define PHY_MR3_RN_M 0x0000000F // Revision Number.
+#define PHY_MR3_OUI_S 10
+#define PHY_MR3_MN_S 4
+#define PHY_MR3_RN_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_IM register.
+//
+//*****************************************************************************
+#define MAC_IM_PHYINTM 0x00000040 // Mask PHY Interrupt.
+#define MAC_IM_MDINTM 0x00000020 // Mask MII Transaction Complete.
+#define MAC_IM_RXERM 0x00000010 // Mask Receive Error.
+#define MAC_IM_FOVM 0x00000008 // Mask FIFO Overrun.
+#define MAC_IM_TXEMPM 0x00000004 // Mask Transmit FIFO Empty.
+#define MAC_IM_TXERM 0x00000002 // Mask Transmit Error.
+#define MAC_IM_RXINTM 0x00000001 // Mask Packet Received.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MR4 register.
+//
+//*****************************************************************************
+#define PHY_MR4_NP 0x00008000 // Next Page.
+#define PHY_MR4_RF 0x00002000 // Remote Fault.
+#define PHY_MR4_A3 0x00000100 // Technology Ability Field[3].
+#define PHY_MR4_A2 0x00000080 // Technology Ability Field[2].
+#define PHY_MR4_A1 0x00000040 // Technology Ability Field[1].
+#define PHY_MR4_A0 0x00000020 // Technology Ability Field[0].
+#define PHY_MR4_S_M 0x0000001F // Selector Field.
+#define PHY_MR4_S_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MR5 register.
+//
+//*****************************************************************************
+#define PHY_MR5_NP 0x00008000 // Next Page.
+#define PHY_MR5_ACK 0x00004000 // Acknowledge.
+#define PHY_MR5_RF 0x00002000 // Remote Fault.
+#define PHY_MR5_A_M 0x00001FE0 // Technology Ability Field.
+#define PHY_MR5_S_M 0x0000001F // Selector Field.
+#define PHY_MR5_S_8023 0x00000001 // IEEE Std 802.3
+#define PHY_MR5_S_8029 0x00000002 // IEEE Std 802.9 ISLAN-16T
+#define PHY_MR5_S_8025 0x00000003 // IEEE Std 802.5
+#define PHY_MR5_S_1394 0x00000004 // IEEE Std 1394
+#define PHY_MR5_A_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MR6 register.
+//
+//*****************************************************************************
+#define PHY_MR6_PDF 0x00000010 // Parallel Detection Fault.
+#define PHY_MR6_LPNPA 0x00000008 // Link Partner is Next Page Able.
+#define PHY_MR6_PRX 0x00000002 // New Page Received.
+#define PHY_MR6_LPANEGA 0x00000001 // Link Partner is Auto-Negotiation
+ // Able.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_RCTL register.
+//
+//*****************************************************************************
+#define MAC_RCTL_RSTFIFO 0x00000010 // Clear Receive FIFO.
+#define MAC_RCTL_BADCRC 0x00000008 // Enable Reject Bad CRC.
+#define MAC_RCTL_PRMS 0x00000004 // Enable Promiscuous Mode.
+#define MAC_RCTL_AMUL 0x00000002 // Enable Multicast Frames.
+#define MAC_RCTL_RXEN 0x00000001 // Enable Receiver.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_TCTL register.
+//
+//*****************************************************************************
+#define MAC_TCTL_DUPLEX 0x00000010 // Enable Duplex Mode.
+#define MAC_TCTL_CRC 0x00000004 // Enable CRC Generation.
+#define MAC_TCTL_PADEN 0x00000002 // Enable Packet Padding.
+#define MAC_TCTL_TXEN 0x00000001 // Enable Transmitter.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_DATA register.
+//
+//*****************************************************************************
+#define MAC_DATA_TXDATA_M 0xFFFFFFFF // Transmit FIFO Data.
+#define MAC_DATA_RXDATA_M 0xFFFFFFFF // Receive FIFO Data.
+#define MAC_DATA_RXDATA_S 0
+#define MAC_DATA_TXDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MR16 register.
+//
+//*****************************************************************************
+#define PHY_MR16_SR_M 0x000003C0 // Silicon Revision Identifier.
+#define PHY_MR16_SR_S 6
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MR17 register.
+//
+//*****************************************************************************
+#define PHY_MR17_FASTRIP 0x00004000 // 10-BASE-T Fast Mode Enable.
+#define PHY_MR17_EDPD 0x00002000 // Enable Energy Detect Power Down.
+#define PHY_MR17_LSQE 0x00000800 // Low Squelch Enable.
+#define PHY_MR17_MDPB 0x00000400 // Management Data Preamble Bypass.
+#define PHY_MR17_FLPBK 0x00000200 // Far Loopback Mode.
+#define PHY_MR17_FASTEST 0x00000100 // Auto-Negotiation Test Mode.
+#define PHY_MR17_REFCE 0x00000010 // Reference Clock Enable.
+#define PHY_MR17_PADBP 0x00000008 // PHY Address Bypass.
+#define PHY_MR17_FGLS 0x00000004 // Force Good Link Status.
+#define PHY_MR17_ENON 0x00000002 // Energy On.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_IA0 register.
+//
+//*****************************************************************************
+#define MAC_IA0_MACOCT4_M 0xFF000000 // MAC Address Octet 4.
+#define MAC_IA0_MACOCT3_M 0x00FF0000 // MAC Address Octet 3.
+#define MAC_IA0_MACOCT2_M 0x0000FF00 // MAC Address Octet 2.
+#define MAC_IA0_MACOCT1_M 0x000000FF // MAC Address Octet 1.
+#define MAC_IA0_MACOCT4_S 24
+#define MAC_IA0_MACOCT3_S 16
+#define MAC_IA0_MACOCT2_S 8
+#define MAC_IA0_MACOCT1_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_IA1 register.
+//
+//*****************************************************************************
+#define MAC_IA1_MACOCT6_M 0x0000FF00 // MAC Address Octet 6.
+#define MAC_IA1_MACOCT5_M 0x000000FF // MAC Address Octet 5.
+#define MAC_IA1_MACOCT6_S 8
+#define MAC_IA1_MACOCT5_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MR27 register.
+//
+//*****************************************************************************
+#define PHY_MR27_XPOL 0x00000010 // Polarity State of 10 BASE-T.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_THR register.
+//
+//*****************************************************************************
+#define MAC_THR_THRESH_M 0x0000003F // Threshold Value.
+#define MAC_THR_THRESH_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MR29 register.
+//
+//*****************************************************************************
+#define PHY_MR29_EONIS 0x00000080 // ENERGYON Interrupt.
+#define PHY_MR29_ANCOMPIS 0x00000040 // Auto-Negotiation Complete
+ // Interrupt.
+#define PHY_MR29_RFLTIS 0x00000020 // Remote Fault Interrupt.
+#define PHY_MR29_LDIS 0x00000010 // Link Down Interrupt.
+#define PHY_MR29_LPACKIS 0x00000008 // Auto-Negotiation LP Acknowledge.
+#define PHY_MR29_PDFIS 0x00000004 // Parallel Detection Fault.
+#define PHY_MR29_PRXIS 0x00000002 // Auto Negotiation Page Received.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MR30 register.
+//
+//*****************************************************************************
+#define PHY_MR30_EONIM 0x00000080 // ENERGYON Interrupt Enabled.
+#define PHY_MR30_ANCOMPIM 0x00000040 // Auto-Negotiation Complete
+ // Interrupt Enabled.
+#define PHY_MR30_RFLTIM 0x00000020 // Remote Fault Interrupt Enabled.
+#define PHY_MR30_LDIM 0x00000010 // Link Down Interrupt Enabled.
+#define PHY_MR30_LPACKIM 0x00000008 // Auto-Negotiation LP Acknowledge
+ // Enabled.
+#define PHY_MR30_PDFIM 0x00000004 // Parallel Detection Fault
+ // Enabled.
+#define PHY_MR30_PRXIM 0x00000002 // Auto Negotiation Page Received
+ // Enabled.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MR31 register.
+//
+//*****************************************************************************
+#define PHY_MR31_AUTODONE 0x00001000 // Auto Negotiation Done.
+#define PHY_MR31_SPEED_M 0x0000001C // HCD Speed Value.
+#define PHY_MR31_SCRDIS 0x00000001 // Scramble Disable.
+#define PHY_MR31_SPEED_S 2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MCTL register.
+//
+//*****************************************************************************
+#define MAC_MCTL_REGADR_M 0x000000F8 // MII Register Address.
+#define MAC_MCTL_WRITE 0x00000002 // MII Register Transaction Type.
+#define MAC_MCTL_START 0x00000001 // MII Register Transaction Enable.
+#define MAC_MCTL_REGADR_S 3
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MDV register.
+//
+//*****************************************************************************
+#define MAC_MDV_DIV_M 0x000000FF // Clock Divider.
+#define MAC_MDV_DIV_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MTXD register.
+//
+//*****************************************************************************
+#define MAC_MTXD_MDTX_M 0x0000FFFF // MII Register Transmit Data.
+#define MAC_MTXD_MDTX_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MRXD register.
+//
+//*****************************************************************************
+#define MAC_MRXD_MDRX_M 0x0000FFFF // MII Register Receive Data.
+#define MAC_MRXD_MDRX_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_NP register.
+//
+//*****************************************************************************
+#define MAC_NP_NPR_M 0x0000003F // Number of Packets in Receive
+ // FIFO.
+#define MAC_NP_NPR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_TR register.
+//
+//*****************************************************************************
+#define MAC_TR_NEWTX 0x00000001 // New Transmission.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_LED register.
+//
+//*****************************************************************************
+#define MAC_LED_LED1_M 0x000000F0 // LED1 Source.
+#define MAC_LED_LED1_LINK 0x00000000 // Link OK
+#define MAC_LED_LED1_RXTX 0x00000010 // RX or TX Activity (Default LED1)
+#define MAC_LED_LED1_100 0x00000050 // 100BASE-TX mode
+#define MAC_LED_LED1_10 0x00000060 // 10BASE-T mode
+#define MAC_LED_LED1_DUPLEX 0x00000070 // Full-Duplex
+#define MAC_LED_LED1_LINKACT 0x00000080 // Link OK & Blink=RX or TX
+ // Activity
+#define MAC_LED_LED0_M 0x0000000F // LED0 Source.
+#define MAC_LED_LED0_LINK 0x00000000 // Link OK (Default LED0)
+#define MAC_LED_LED0_RXTX 0x00000001 // RX or TX Activity
+#define MAC_LED_LED0_100 0x00000005 // 100BASE-TX mode
+#define MAC_LED_LED0_10 0x00000006 // 10BASE-T mode
+#define MAC_LED_LED0_DUPLEX 0x00000007 // Full-Duplex
+#define MAC_LED_LED0_LINKACT 0x00000008 // Link OK & Blink=RX or TX
+ // Activity
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MDIX register.
+//
+//*****************************************************************************
+#define MAC_MDIX_EN 0x00000001 // MDI/MDI-X Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FADDR register.
+//
+//*****************************************************************************
+#define USB_FADDR_M 0x0000007F // Function Address.
+#define USB_FADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_POWER register.
+//
+//*****************************************************************************
+#define USB_POWER_ISOUP 0x00000080 // ISO Update.
+#define USB_POWER_SOFTCONN 0x00000040 // Soft Connect/Disconnect.
+#define USB_POWER_RESET 0x00000008 // Reset.
+#define USB_POWER_RESUME 0x00000004 // Resume Signaling.
+#define USB_POWER_SUSPEND 0x00000002 // Suspend Mode.
+#define USB_POWER_PWRDNPHY 0x00000001 // Power Down PHY.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXIS register.
+//
+//*****************************************************************************
+#define USB_TXIS_EP15 0x00008000 // TX Endpoint 15 Interrupt.
+#define USB_TXIS_EP14 0x00004000 // TX Endpoint 14 Interrupt.
+#define USB_TXIS_EP13 0x00002000 // TX Endpoint 13 Interrupt.
+#define USB_TXIS_EP12 0x00001000 // TX Endpoint 12 Interrupt.
+#define USB_TXIS_EP11 0x00000800 // TX Endpoint 11 Interrupt.
+#define USB_TXIS_EP10 0x00000400 // TX Endpoint 10 Interrupt.
+#define USB_TXIS_EP9 0x00000200 // TX Endpoint 9 Interrupt.
+#define USB_TXIS_EP8 0x00000100 // TX Endpoint 8 Interrupt.
+#define USB_TXIS_EP7 0x00000080 // TX Endpoint 7 Interrupt.
+#define USB_TXIS_EP6 0x00000040 // TX Endpoint 6 Interrupt.
+#define USB_TXIS_EP5 0x00000020 // TX Endpoint 5 Interrupt.
+#define USB_TXIS_EP4 0x00000010 // TX Endpoint 4 Interrupt.
+#define USB_TXIS_EP3 0x00000008 // TX Endpoint 3 Interrupt.
+#define USB_TXIS_EP2 0x00000004 // TX Endpoint 2 Interrupt.
+#define USB_TXIS_EP1 0x00000002 // TX Endpoint 1 Interrupt.
+#define USB_TXIS_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXIS register.
+//
+//*****************************************************************************
+#define USB_RXIS_EP15 0x00008000 // RX Endpoint 15 Interrupt.
+#define USB_RXIS_EP14 0x00004000 // RX Endpoint 14 Interrupt.
+#define USB_RXIS_EP13 0x00002000 // RX Endpoint 13 Interrupt.
+#define USB_RXIS_EP12 0x00001000 // RX Endpoint 12 Interrupt.
+#define USB_RXIS_EP11 0x00000800 // RX Endpoint 11 Interrupt.
+#define USB_RXIS_EP10 0x00000400 // RX Endpoint 10 Interrupt.
+#define USB_RXIS_EP9 0x00000200 // RX Endpoint 9 Interrupt.
+#define USB_RXIS_EP8 0x00000100 // RX Endpoint 8 Interrupt.
+#define USB_RXIS_EP7 0x00000080 // RX Endpoint 7 Interrupt.
+#define USB_RXIS_EP6 0x00000040 // RX Endpoint 6 Interrupt.
+#define USB_RXIS_EP5 0x00000020 // RX Endpoint 5 Interrupt.
+#define USB_RXIS_EP4 0x00000010 // RX Endpoint 4 Interrupt.
+#define USB_RXIS_EP3 0x00000008 // RX Endpoint 3 Interrupt.
+#define USB_RXIS_EP2 0x00000004 // RX Endpoint 2 Interrupt.
+#define USB_RXIS_EP1 0x00000002 // RX Endpoint 1 Interrupt.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXIE register.
+//
+//*****************************************************************************
+#define USB_TXIE_EP15 0x00008000 // TX Endpoint 15 Interrupt Enable.
+#define USB_TXIE_EP14 0x00004000 // TX Endpoint 14 Interrupt Enable.
+#define USB_TXIE_EP13 0x00002000 // TX Endpoint 13 Interrupt Enable.
+#define USB_TXIE_EP12 0x00001000 // TX Endpoint 12 Interrupt Enable.
+#define USB_TXIE_EP11 0x00000800 // TX Endpoint 11 Interrupt Enable.
+#define USB_TXIE_EP10 0x00000400 // TX Endpoint 10 Interrupt Enable.
+#define USB_TXIE_EP9 0x00000200 // TX Endpoint 9 Interrupt Enable.
+#define USB_TXIE_EP8 0x00000100 // TX Endpoint 8 Interrupt Enable.
+#define USB_TXIE_EP7 0x00000080 // TX Endpoint 7 Interrupt Enable.
+#define USB_TXIE_EP6 0x00000040 // TX Endpoint 6 Interrupt Enable.
+#define USB_TXIE_EP5 0x00000020 // TX Endpoint 5 Interrupt Enable.
+#define USB_TXIE_EP4 0x00000010 // TX Endpoint 4 Interrupt Enable.
+#define USB_TXIE_EP3 0x00000008 // TX Endpoint 3 Interrupt Enable.
+#define USB_TXIE_EP2 0x00000004 // TX Endpoint 2 Interrupt Enable.
+#define USB_TXIE_EP1 0x00000002 // TX Endpoint 1 Interrupt Enable.
+#define USB_TXIE_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt
+ // Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXIE register.
+//
+//*****************************************************************************
+#define USB_RXIE_EP15 0x00008000 // RX Endpoint 15 Interrupt Enable.
+#define USB_RXIE_EP14 0x00004000 // RX Endpoint 14 Interrupt Enable.
+#define USB_RXIE_EP13 0x00002000 // RX Endpoint 13 Interrupt Enable.
+#define USB_RXIE_EP12 0x00001000 // RX Endpoint 12 Interrupt Enable.
+#define USB_RXIE_EP11 0x00000800 // RX Endpoint 11 Interrupt Enable.
+#define USB_RXIE_EP10 0x00000400 // RX Endpoint 10 Interrupt Enable.
+#define USB_RXIE_EP9 0x00000200 // RX Endpoint 9 Interrupt Enable.
+#define USB_RXIE_EP8 0x00000100 // RX Endpoint 8 Interrupt Enable.
+#define USB_RXIE_EP7 0x00000080 // RX Endpoint 7 Interrupt Enable.
+#define USB_RXIE_EP6 0x00000040 // RX Endpoint 6 Interrupt Enable.
+#define USB_RXIE_EP5 0x00000020 // RX Endpoint 5 Interrupt Enable.
+#define USB_RXIE_EP4 0x00000010 // RX Endpoint 4 Interrupt Enable.
+#define USB_RXIE_EP3 0x00000008 // RX Endpoint 3 Interrupt Enable.
+#define USB_RXIE_EP2 0x00000004 // RX Endpoint 2 Interrupt Enable.
+#define USB_RXIE_EP1 0x00000002 // RX Endpoint 1 Interrupt Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IS register.
+//
+//*****************************************************************************
+#define USB_IS_VBUSERR 0x00000080 // VBus Error.
+#define USB_IS_SESREQ 0x00000040 // Session Request.
+#define USB_IS_DISCON 0x00000020 // Session Disconnect.
+#define USB_IS_CONN 0x00000010 // Session Connect.
+#define USB_IS_SOF 0x00000008 // Start of Frame.
+#define USB_IS_BABBLE 0x00000004 // Babble Detected.
+#define USB_IS_RESET 0x00000004 // Reset Signal Detected.
+#define USB_IS_RESUME 0x00000002 // Resume Signal Detected.
+#define USB_IS_SUSPEND 0x00000001 // Suspend Signal Detected.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IE register.
+//
+//*****************************************************************************
+#define USB_IE_VBUSERR 0x00000080 // Enable VBUS Error Interrupt.
+#define USB_IE_SESREQ 0x00000040 // Enable Session Request
+ // Interrupt.
+#define USB_IE_DISCON 0x00000020 // Enable Disconnect Interrupt.
+#define USB_IE_CONN 0x00000010 // Enable Connect Interrupt.
+#define USB_IE_SOF 0x00000008 // Enable Start-of-Frame Interrupt.
+#define USB_IE_BABBLE 0x00000004 // Enable Babble Interrupt.
+#define USB_IE_RESET 0x00000004 // Enable Reset Interrupt.
+#define USB_IE_RESUME 0x00000002 // Enable Resume Interrupt.
+#define USB_IE_SUSPND 0x00000001 // Enable Suspend Interrupt.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FRAME register.
+//
+//*****************************************************************************
+#define USB_FRAME_M 0x000007FF // Frame Number.
+#define USB_FRAME_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPIDX register.
+//
+//*****************************************************************************
+#define USB_EPIDX_EPIDX_M 0x0000000F // Endpoint Index.
+#define USB_EPIDX_EPIDX_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TEST register.
+//
+//*****************************************************************************
+#define USB_TEST_FORCEH 0x00000080 // Force Host Mode.
+#define USB_TEST_FIFOACC 0x00000040 // FIFO Access.
+#define USB_TEST_FORCEFS 0x00000020 // Force Full Speed.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO0 register.
+//
+//*****************************************************************************
+#define USB_FIFO0_EPDATA_M 0xFFFFFFFF // Endpoint Data.
+#define USB_FIFO0_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO1 register.
+//
+//*****************************************************************************
+#define USB_FIFO1_EPDATA_M 0xFFFFFFFF // Endpoint Data.
+#define USB_FIFO1_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO2 register.
+//
+//*****************************************************************************
+#define USB_FIFO2_EPDATA_M 0xFFFFFFFF // Endpoint Data.
+#define USB_FIFO2_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO3 register.
+//
+//*****************************************************************************
+#define USB_FIFO3_EPDATA_M 0xFFFFFFFF // Endpoint Data.
+#define USB_FIFO3_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO4 register.
+//
+//*****************************************************************************
+#define USB_FIFO4_EPDATA_M 0xFFFFFFFF // Endpoint Data.
+#define USB_FIFO4_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO5 register.
+//
+//*****************************************************************************
+#define USB_FIFO5_EPDATA_M 0xFFFFFFFF // Endpoint Data.
+#define USB_FIFO5_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO6 register.
+//
+//*****************************************************************************
+#define USB_FIFO6_EPDATA_M 0xFFFFFFFF // Endpoint Data.
+#define USB_FIFO6_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO7 register.
+//
+//*****************************************************************************
+#define USB_FIFO7_EPDATA_M 0xFFFFFFFF // Endpoint Data.
+#define USB_FIFO7_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO8 register.
+//
+//*****************************************************************************
+#define USB_FIFO8_EPDATA_M 0xFFFFFFFF // Endpoint Data.
+#define USB_FIFO8_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO9 register.
+//
+//*****************************************************************************
+#define USB_FIFO9_EPDATA_M 0xFFFFFFFF // Endpoint Data.
+#define USB_FIFO9_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO10 register.
+//
+//*****************************************************************************
+#define USB_FIFO10_EPDATA_M 0xFFFFFFFF // Endpoint Data.
+#define USB_FIFO10_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO11 register.
+//
+//*****************************************************************************
+#define USB_FIFO11_EPDATA_M 0xFFFFFFFF // Endpoint Data.
+#define USB_FIFO11_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO12 register.
+//
+//*****************************************************************************
+#define USB_FIFO12_EPDATA_M 0xFFFFFFFF // Endpoint Data.
+#define USB_FIFO12_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO13 register.
+//
+//*****************************************************************************
+#define USB_FIFO13_EPDATA_M 0xFFFFFFFF // Endpoint Data.
+#define USB_FIFO13_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO14 register.
+//
+//*****************************************************************************
+#define USB_FIFO14_EPDATA_M 0xFFFFFFFF // Endpoint Data.
+#define USB_FIFO14_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO15 register.
+//
+//*****************************************************************************
+#define USB_FIFO15_EPDATA_M 0xFFFFFFFF // Endpoint Data.
+#define USB_FIFO15_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DEVCTL register.
+//
+//*****************************************************************************
+#define USB_DEVCTL_DEV 0x00000080 // Device Mode.
+#define USB_DEVCTL_FSDEV 0x00000040 // Full-Speed Device Detected.
+#define USB_DEVCTL_LSDEV 0x00000020 // Low-Speed Device Detected.
+#define USB_DEVCTL_VBUS_M 0x00000018 // VBus Level.
+#define USB_DEVCTL_VBUS_NONE 0x00000000 // Below SessionEnd
+#define USB_DEVCTL_VBUS_SEND 0x00000008 // Above SessionEnd, below AValid
+#define USB_DEVCTL_VBUS_AVALID 0x00000010 // Above AValid, below VBusValid
+#define USB_DEVCTL_VBUS_VALID 0x00000018 // Above VBusValid
+#define USB_DEVCTL_HOST 0x00000004 // Host Mode.
+#define USB_DEVCTL_HOSTREQ 0x00000002 // Host Request.
+#define USB_DEVCTL_SESSION 0x00000001 // Session Start/End.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFIFOSZ register.
+//
+//*****************************************************************************
+#define USB_TXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support.
+#define USB_TXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size.
+#define USB_TXFIFOSZ_SIZE_8 0x00000000 // 8
+#define USB_TXFIFOSZ_SIZE_16 0x00000001 // 16
+#define USB_TXFIFOSZ_SIZE_32 0x00000002 // 32
+#define USB_TXFIFOSZ_SIZE_64 0x00000003 // 64
+#define USB_TXFIFOSZ_SIZE_128 0x00000004 // 128
+#define USB_TXFIFOSZ_SIZE_256 0x00000005 // 256
+#define USB_TXFIFOSZ_SIZE_512 0x00000006 // 512
+#define USB_TXFIFOSZ_SIZE_1024 0x00000007 // 1024
+#define USB_TXFIFOSZ_SIZE_2048 0x00000008 // 2048
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFIFOSZ register.
+//
+//*****************************************************************************
+#define USB_RXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support.
+#define USB_RXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size.
+#define USB_RXFIFOSZ_SIZE_8 0x00000000 // 8
+#define USB_RXFIFOSZ_SIZE_16 0x00000001 // 16
+#define USB_RXFIFOSZ_SIZE_32 0x00000002 // 32
+#define USB_RXFIFOSZ_SIZE_64 0x00000003 // 64
+#define USB_RXFIFOSZ_SIZE_128 0x00000004 // 128
+#define USB_RXFIFOSZ_SIZE_256 0x00000005 // 256
+#define USB_RXFIFOSZ_SIZE_512 0x00000006 // 512
+#define USB_RXFIFOSZ_SIZE_1024 0x00000007 // 1024
+#define USB_RXFIFOSZ_SIZE_2048 0x00000008 // 2048
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFIFOADD
+// register.
+//
+//*****************************************************************************
+#define USB_TXFIFOADD_ADDR_M 0x00001FFF // Transmit/Receive Start Address.
+#define USB_TXFIFOADD_ADDR_0 0x00000000 // 0
+#define USB_TXFIFOADD_ADDR_8 0x00000001 // 8
+#define USB_TXFIFOADD_ADDR_16 0x00000002 // 16
+#define USB_TXFIFOADD_ADDR_32 0x00000003 // 32
+#define USB_TXFIFOADD_ADDR_64 0x00000004 // 64
+#define USB_TXFIFOADD_ADDR_128 0x00000005 // 128
+#define USB_TXFIFOADD_ADDR_256 0x00000006 // 256
+#define USB_TXFIFOADD_ADDR_512 0x00000007 // 512
+#define USB_TXFIFOADD_ADDR_1024 0x00000008 // 1024
+#define USB_TXFIFOADD_ADDR_2048 0x00000009 // 2048
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFIFOADD
+// register.
+//
+//*****************************************************************************
+#define USB_RXFIFOADD_ADDR_M 0x00001FFF // Transmit/Receive Start Address.
+#define USB_RXFIFOADD_ADDR_0 0x00000000 // 0
+#define USB_RXFIFOADD_ADDR_8 0x00000001 // 8
+#define USB_RXFIFOADD_ADDR_16 0x00000002 // 16
+#define USB_RXFIFOADD_ADDR_32 0x00000003 // 32
+#define USB_RXFIFOADD_ADDR_64 0x00000004 // 64
+#define USB_RXFIFOADD_ADDR_128 0x00000005 // 128
+#define USB_RXFIFOADD_ADDR_256 0x00000006 // 256
+#define USB_RXFIFOADD_ADDR_512 0x00000007 // 512
+#define USB_RXFIFOADD_ADDR_1024 0x00000008 // 1024
+#define USB_RXFIFOADD_ADDR_2048 0x00000009 // 2048
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_CONTIM register.
+//
+//*****************************************************************************
+#define USB_CONTIM_WTCON_M 0x000000F0 // Connect Wait.
+#define USB_CONTIM_WTID_M 0x0000000F // Wait ID.
+#define USB_CONTIM_WTCON_S 4
+#define USB_CONTIM_WTID_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VPLEN register.
+//
+//*****************************************************************************
+#define USB_VPLEN_VPLEN_M 0x000000FF // VBus Pulse Length.
+#define USB_VPLEN_VPLEN_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FSEOF register.
+//
+//*****************************************************************************
+#define USB_FSEOF_FSEOFG_M 0x000000FF // Full-Speed End-of-Frame Gap.
+#define USB_FSEOF_FSEOFG_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_LSEOF register.
+//
+//*****************************************************************************
+#define USB_LSEOF_LSEOFG_M 0x000000FF // Low-Speed End-of-Frame Gap.
+#define USB_LSEOF_LSEOFG_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR0
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR0_ADDR_M 0x0000007F // Device Address.
+#define USB_TXFUNCADDR0_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR0
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR0_MULTTRAN 0x00000080 // Multiple Translators.
+#define USB_TXHUBADDR0_ADDR_M 0x0000007F // Hub Address.
+#define USB_TXHUBADDR0_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT0
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT0_PORT_M 0x0000007F // Hub Port.
+#define USB_TXHUBPORT0_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR1
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR1_ADDR_M 0x0000007F // Device Address.
+#define USB_TXFUNCADDR1_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR1
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR1_MULTTRAN 0x00000080 // Multiple Translators.
+#define USB_TXHUBADDR1_ADDR_M 0x0000007F // Hub Address.
+#define USB_TXHUBADDR1_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT1
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT1_PORT_M 0x0000007F // Hub Port.
+#define USB_TXHUBPORT1_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR1
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR1_ADDR_M 0x0000007F // Device Address.
+#define USB_RXFUNCADDR1_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR1
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR1_MULTTRAN 0x00000080 // Multiple Translators.
+#define USB_RXHUBADDR1_ADDR_M 0x0000007F // Hub Address.
+#define USB_RXHUBADDR1_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT1
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT1_PORT_M 0x0000007F // Hub Port.
+#define USB_RXHUBPORT1_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR2
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR2_ADDR_M 0x0000007F // Device Address.
+#define USB_TXFUNCADDR2_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR2
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR2_MULTTRAN 0x00000080 // Multiple Translators.
+#define USB_TXHUBADDR2_ADDR_M 0x0000007F // Hub Address.
+#define USB_TXHUBADDR2_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT2
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT2_PORT_M 0x0000007F // Hub Port.
+#define USB_TXHUBPORT2_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR2
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR2_ADDR_M 0x0000007F // Device Address.
+#define USB_RXFUNCADDR2_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR2
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR2_MULTTRAN 0x00000080 // Multiple Translators.
+#define USB_RXHUBADDR2_ADDR_M 0x0000007F // Hub Address.
+#define USB_RXHUBADDR2_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT2
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT2_PORT_M 0x0000007F // Hub Port.
+#define USB_RXHUBPORT2_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR3
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR3_ADDR_M 0x0000007F // Device Address.
+#define USB_TXFUNCADDR3_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR3
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR3_MULTTRAN 0x00000080 // Multiple Translators.
+#define USB_TXHUBADDR3_ADDR_M 0x0000007F // Hub Address.
+#define USB_TXHUBADDR3_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT3
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT3_PORT_M 0x0000007F // Hub Port.
+#define USB_TXHUBPORT3_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR3
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR3_ADDR_M 0x0000007F // Device Address.
+#define USB_RXFUNCADDR3_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR3
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR3_MULTTRAN 0x00000080 // Multiple Translators.
+#define USB_RXHUBADDR3_ADDR_M 0x0000007F // Hub Address.
+#define USB_RXHUBADDR3_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT3
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT3_PORT_M 0x0000007F // Hub Port.
+#define USB_RXHUBPORT3_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR4
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR4_ADDR_M 0x0000007F // Device Address.
+#define USB_TXFUNCADDR4_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR4
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR4_MULTTRAN 0x00000080 // Multiple Translators.
+#define USB_TXHUBADDR4_ADDR_M 0x0000007F // Hub Address.
+#define USB_TXHUBADDR4_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT4
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT4_PORT_M 0x0000007F // Hub Port.
+#define USB_TXHUBPORT4_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR4
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR4_ADDR_M 0x0000007F // Device Address.
+#define USB_RXFUNCADDR4_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR4
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR4_MULTTRAN 0x00000080 // Multiple Translators.
+#define USB_RXHUBADDR4_ADDR_M 0x0000007F // Hub Address.
+#define USB_RXHUBADDR4_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT4
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT4_PORT_M 0x0000007F // Hub Port.
+#define USB_RXHUBPORT4_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR5
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR5_ADDR_M 0x0000007F // Device Address.
+#define USB_TXFUNCADDR5_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR5
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR5_MULTTRAN 0x00000080 // Multiple Translators.
+#define USB_TXHUBADDR5_ADDR_M 0x0000007F // Hub Address.
+#define USB_TXHUBADDR5_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT5
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT5_PORT_M 0x0000007F // Hub Port.
+#define USB_TXHUBPORT5_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR5
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR5_ADDR_M 0x0000007F // Device Address.
+#define USB_RXFUNCADDR5_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR5
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR5_MULTTRAN 0x00000080 // Multiple Translators.
+#define USB_RXHUBADDR5_ADDR_M 0x0000007F // Hub Address.
+#define USB_RXHUBADDR5_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT5
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT5_PORT_M 0x0000007F // Hub Port.
+#define USB_RXHUBPORT5_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR6
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR6_ADDR_M 0x0000007F // Device Address.
+#define USB_TXFUNCADDR6_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR6
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR6_MULTTRAN 0x00000080 // Multiple Translators.
+#define USB_TXHUBADDR6_ADDR_M 0x0000007F // Hub Address.
+#define USB_TXHUBADDR6_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT6
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT6_PORT_M 0x0000007F // Hub Port.
+#define USB_TXHUBPORT6_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR6
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR6_ADDR_M 0x0000007F // Device Address.
+#define USB_RXFUNCADDR6_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR6
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR6_MULTTRAN 0x00000080 // Multiple Translators.
+#define USB_RXHUBADDR6_ADDR_M 0x0000007F // Hub Address.
+#define USB_RXHUBADDR6_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT6
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT6_PORT_M 0x0000007F // Hub Port.
+#define USB_RXHUBPORT6_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR7
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR7_ADDR_M 0x0000007F // Device Address.
+#define USB_TXFUNCADDR7_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR7
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR7_MULTTRAN 0x00000080 // Multiple Translators.
+#define USB_TXHUBADDR7_ADDR_M 0x0000007F // Hub Address.
+#define USB_TXHUBADDR7_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT7
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT7_PORT_M 0x0000007F // Hub Port.
+#define USB_TXHUBPORT7_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR7
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR7_ADDR_M 0x0000007F // Device Address.
+#define USB_RXFUNCADDR7_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR7
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR7_MULTTRAN 0x00000080 // Multiple Translators.
+#define USB_RXHUBADDR7_ADDR_M 0x0000007F // Hub Address.
+#define USB_RXHUBADDR7_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT7
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT7_PORT_M 0x0000007F // Hub Port.
+#define USB_RXHUBPORT7_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR8
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR8_ADDR_M 0x0000007F // Device Address.
+#define USB_TXFUNCADDR8_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR8
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR8_MULTTRAN 0x00000080 // Multiple Translators.
+#define USB_TXHUBADDR8_ADDR_M 0x0000007F // Hub Address.
+#define USB_TXHUBADDR8_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT8
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT8_PORT_M 0x0000007F // Hub Port.
+#define USB_TXHUBPORT8_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR8
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR8_ADDR_M 0x0000007F // Device Address.
+#define USB_RXFUNCADDR8_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR8
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR8_MULTTRAN 0x00000080 // Multiple Translators.
+#define USB_RXHUBADDR8_ADDR_M 0x0000007F // Hub Address.
+#define USB_RXHUBADDR8_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT8
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT8_PORT_M 0x0000007F // Hub Port.
+#define USB_RXHUBPORT8_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR9
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR9_ADDR_M 0x0000007F // Device Address.
+#define USB_TXFUNCADDR9_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR9
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR9_MULTTRAN 0x00000080 // Multiple Translators.
+#define USB_TXHUBADDR9_ADDR_M 0x0000007F // Hub Address.
+#define USB_TXHUBADDR9_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT9
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT9_PORT_M 0x0000007F // Hub Port.
+#define USB_TXHUBPORT9_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR9
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR9_ADDR_M 0x0000007F // Device Address.
+#define USB_RXFUNCADDR9_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR9
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR9_MULTTRAN 0x00000080 // Multiple Translators.
+#define USB_RXHUBADDR9_ADDR_M 0x0000007F // Hub Address.
+#define USB_RXHUBADDR9_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT9
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT9_PORT_M 0x0000007F // Hub Port.
+#define USB_RXHUBPORT9_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR10
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR10_ADDR_M 0x0000007F // Device Address.
+#define USB_TXFUNCADDR10_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR10
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR10_MULTTRAN \
+ 0x00000080 // Multiple Translators.
+#define USB_TXHUBADDR10_ADDR_M 0x0000007F // Hub Address.
+#define USB_TXHUBADDR10_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT10
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT10_PORT_M 0x0000007F // Hub Port.
+#define USB_TXHUBPORT10_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR10
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR10_ADDR_M 0x0000007F // Device Address.
+#define USB_RXFUNCADDR10_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR10
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR10_MULTTRAN \
+ 0x00000080 // Multiple Translators.
+#define USB_RXHUBADDR10_ADDR_M 0x0000007F // Hub Address.
+#define USB_RXHUBADDR10_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT10
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT10_PORT_M 0x0000007F // Hub Port.
+#define USB_RXHUBPORT10_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR11
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR11_ADDR_M 0x0000007F // Device Address.
+#define USB_TXFUNCADDR11_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR11
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR11_MULTTRAN \
+ 0x00000080 // Multiple Translators.
+#define USB_TXHUBADDR11_ADDR_M 0x0000007F // Hub Address.
+#define USB_TXHUBADDR11_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT11
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT11_PORT_M 0x0000007F // Hub Port.
+#define USB_TXHUBPORT11_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR11
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR11_ADDR_M 0x0000007F // Device Address.
+#define USB_RXFUNCADDR11_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR11
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR11_MULTTRAN \
+ 0x00000080 // Multiple Translators.
+#define USB_RXHUBADDR11_ADDR_M 0x0000007F // Hub Address.
+#define USB_RXHUBADDR11_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT11
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT11_PORT_M 0x0000007F // Hub Port.
+#define USB_RXHUBPORT11_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR12
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR12_ADDR_M 0x0000007F // Device Address.
+#define USB_TXFUNCADDR12_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR12
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR12_MULTTRAN \
+ 0x00000080 // Multiple Translators.
+#define USB_TXHUBADDR12_ADDR_M 0x0000007F // Hub Address.
+#define USB_TXHUBADDR12_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT12
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT12_PORT_M 0x0000007F // Hub Port.
+#define USB_TXHUBPORT12_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR12
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR12_ADDR_M 0x0000007F // Device Address.
+#define USB_RXFUNCADDR12_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR12
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR12_MULTTRAN \
+ 0x00000080 // Multiple Translators.
+#define USB_RXHUBADDR12_ADDR_M 0x0000007F // Hub Address.
+#define USB_RXHUBADDR12_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT12
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT12_PORT_M 0x0000007F // Hub Port.
+#define USB_RXHUBPORT12_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR13
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR13_ADDR_M 0x0000007F // Device Address.
+#define USB_TXFUNCADDR13_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR13
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR13_MULTTRAN \
+ 0x00000080 // Multiple Translators.
+#define USB_TXHUBADDR13_ADDR_M 0x0000007F // Hub Address.
+#define USB_TXHUBADDR13_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT13
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT13_PORT_M 0x0000007F // Hub Port.
+#define USB_TXHUBPORT13_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR13
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR13_ADDR_M 0x0000007F // Device Address.
+#define USB_RXFUNCADDR13_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR13
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR13_MULTTRAN \
+ 0x00000080 // Multiple Translators.
+#define USB_RXHUBADDR13_ADDR_M 0x0000007F // Hub Address.
+#define USB_RXHUBADDR13_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT13
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT13_PORT_M 0x0000007F // Hub Port.
+#define USB_RXHUBPORT13_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR14
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR14_ADDR_M 0x0000007F // Device Address.
+#define USB_TXFUNCADDR14_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR14
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR14_MULTTRAN \
+ 0x00000080 // Multiple Translators.
+#define USB_TXHUBADDR14_ADDR_M 0x0000007F // Hub Address.
+#define USB_TXHUBADDR14_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT14
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT14_PORT_M 0x0000007F // Hub Port.
+#define USB_TXHUBPORT14_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR14
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR14_ADDR_M 0x0000007F // Device Address.
+#define USB_RXFUNCADDR14_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR14
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR14_MULTTRAN \
+ 0x00000080 // Multiple Translators.
+#define USB_RXHUBADDR14_ADDR_M 0x0000007F // Hub Address.
+#define USB_RXHUBADDR14_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT14
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT14_PORT_M 0x0000007F // Hub Port.
+#define USB_RXHUBPORT14_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR15
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR15_ADDR_M 0x0000007F // Device Address.
+#define USB_TXFUNCADDR15_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR15
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR15_MULTTRAN \
+ 0x00000080 // Multiple Translators.
+#define USB_TXHUBADDR15_ADDR_M 0x0000007F // Hub Address.
+#define USB_TXHUBADDR15_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT15
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT15_PORT_M 0x0000007F // Hub Port.
+#define USB_TXHUBPORT15_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR15
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR15_ADDR_M 0x0000007F // Device Address.
+#define USB_RXFUNCADDR15_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR15
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR15_MULTTRAN \
+ 0x00000080 // Multiple Translators.
+#define USB_RXHUBADDR15_ADDR_M 0x0000007F // Hub Address.
+#define USB_RXHUBADDR15_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT15
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT15_PORT_M 0x0000007F // Hub Port.
+#define USB_RXHUBPORT15_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_CSRL0 register.
+//
+//*****************************************************************************
+#define USB_CSRL0_NAKTO 0x00000080 // NAK Timeout.
+#define USB_CSRL0_SETENDC 0x00000080 // Setup End Clear.
+#define USB_CSRL0_STATUS 0x00000040 // Status Packet.
+#define USB_CSRL0_RXRDYC 0x00000040 // RXRDY Clear.
+#define USB_CSRL0_REQPKT 0x00000020 // Request Packet.
+#define USB_CSRL0_STALL 0x00000020 // Send Stall.
+#define USB_CSRL0_SETEND 0x00000010 // Setup End.
+#define USB_CSRL0_ERROR 0x00000010 // Error.
+#define USB_CSRL0_DATAEND 0x00000008 // Data End.
+#define USB_CSRL0_SETUP 0x00000008 // Setup Packet.
+#define USB_CSRL0_STALLED 0x00000004 // Endpoint Stalled.
+#define USB_CSRL0_TXRDY 0x00000002 // Transmit Packet Ready.
+#define USB_CSRL0_RXRDY 0x00000001 // Receive Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_CSRH0 register.
+//
+//*****************************************************************************
+#define USB_CSRH0_DTWE 0x00000004 // Data Toggle Write Enable.
+#define USB_CSRH0_DT 0x00000002 // Data Toggle.
+#define USB_CSRH0_FLUSH 0x00000001 // Flush FIFO.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_COUNT0 register.
+//
+//*****************************************************************************
+#define USB_COUNT0_COUNT_M 0x0000007F // Count.
+#define USB_COUNT0_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TYPE0 register.
+//
+//*****************************************************************************
+#define USB_TYPE0_SPEED_M 0x000000C0 // Operating Speed.
+#define USB_TYPE0_SPEED_FULL 0x00000080 // Full
+#define USB_TYPE0_SPEED_LOW 0x000000C0 // Low
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_NAKLMT register.
+//
+//*****************************************************************************
+#define USB_NAKLMT_NAKLMT_M 0x0000001F // EP0 NAK Limit.
+#define USB_NAKLMT_NAKLMT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP1 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload.
+#define USB_TXMAXP1_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL1 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL1_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL1_INCTX 0x00000080 // Incomplete Transmit.
+#define USB_TXCSRL1_CLRDT 0x00000040 // Clear Data Toggle.
+#define USB_TXCSRL1_STALLED 0x00000020 // Endpoint Stalled.
+#define USB_TXCSRL1_STALL 0x00000010 // Send Stall.
+#define USB_TXCSRL1_SETUP 0x00000010 // Setup Packet.
+#define USB_TXCSRL1_FLUSH 0x00000008 // Flush FIFO.
+#define USB_TXCSRL1_ERROR 0x00000004 // Error.
+#define USB_TXCSRL1_UNDRN 0x00000004 // Underrun.
+#define USB_TXCSRL1_FIFONE 0x00000002 // FIFO Not Empty.
+#define USB_TXCSRL1_TXRDY 0x00000001 // Transmit Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH1 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH1_AUTOSET 0x00000080 // Auto Set.
+#define USB_TXCSRH1_ISO 0x00000040 // ISO.
+#define USB_TXCSRH1_MODE 0x00000020 // Mode.
+#define USB_TXCSRH1_DMAEN 0x00000010 // DMA Request Enable.
+#define USB_TXCSRH1_FDT 0x00000008 // Force Data Toggle.
+#define USB_TXCSRH1_DMAMOD 0x00000004 // DMA Request Mode.
+#define USB_TXCSRH1_DTWE 0x00000002 // Data Toggle Write Enable.
+#define USB_TXCSRH1_DT 0x00000001 // Data Toggle.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP1 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload.
+#define USB_RXMAXP1_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL1 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL1_CLRDT 0x00000080 // Clear Data Toggle.
+#define USB_RXCSRL1_STALLED 0x00000040 // Endpoint Stalled.
+#define USB_RXCSRL1_STALL 0x00000020 // Send Stall.
+#define USB_RXCSRL1_REQPKT 0x00000020 // Request Packet.
+#define USB_RXCSRL1_FLUSH 0x00000010 // Flush FIFO.
+#define USB_RXCSRL1_DATAERR 0x00000008 // Data Error.
+#define USB_RXCSRL1_NAKTO 0x00000008 // NAK Timeout.
+#define USB_RXCSRL1_OVER 0x00000004 // Overrun.
+#define USB_RXCSRL1_ERROR 0x00000004 // Error.
+#define USB_RXCSRL1_FULL 0x00000002 // FIFO Full.
+#define USB_RXCSRL1_RXRDY 0x00000001 // Receive Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH1 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH1_AUTOCL 0x00000080 // Auto Clear.
+#define USB_RXCSRH1_AUTORQ 0x00000040 // Auto Request.
+#define USB_RXCSRH1_ISO 0x00000040 // ISO.
+#define USB_RXCSRH1_DMAEN 0x00000020 // DMA Request Enable.
+#define USB_RXCSRH1_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH1_PIDERR 0x00000010 // PID Error.
+#define USB_RXCSRH1_DMAMOD 0x00000008 // DMA Request Mode.
+#define USB_RXCSRH1_DTWE 0x00000004 // Data Toggle Write Enable.
+#define USB_RXCSRH1_DT 0x00000002 // Data Toggle.
+#define USB_RXCSRH1_INCRX 0x00000001 // Incomplete Receive.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT1 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT1_COUNT_M 0x00001FFF // Receive Packet Count.
+#define USB_RXCOUNT1_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE1 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE1_SPEED_M 0x000000C0 // Operating Speed.
+#define USB_TXTYPE1_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE1_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE1_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE1_PROTO_M 0x00000030 // Protocol.
+#define USB_TXTYPE1_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE1_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE1_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE1_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE1_TEP_M 0x0000000F // Target Endpoint Number.
+#define USB_TXTYPE1_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL1
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL1_NAKLMT_M \
+ 0x000000FF // NAK Limit.
+#define USB_TXINTERVAL1_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL1_TXPOLL_S \
+ 0
+#define USB_TXINTERVAL1_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE1 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE1_SPEED_M 0x000000C0 // Operating Speed.
+#define USB_RXTYPE1_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE1_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE1_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE1_PROTO_M 0x00000030 // Protocol.
+#define USB_RXTYPE1_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE1_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE1_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE1_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE1_TEP_M 0x0000000F // Target Endpoint Number.
+#define USB_RXTYPE1_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL1
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL1_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL1_NAKLMT_M \
+ 0x000000FF // NAK Limit.
+#define USB_RXINTERVAL1_TXPOLL_S \
+ 0
+#define USB_RXINTERVAL1_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP2 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload.
+#define USB_TXMAXP2_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL2 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL2_INCTX 0x00000080 // Incomplete Transmit.
+#define USB_TXCSRL2_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL2_CLRDT 0x00000040 // Clear Data Toggle.
+#define USB_TXCSRL2_STALLED 0x00000020 // Endpoint Stalled.
+#define USB_TXCSRL2_SETUP 0x00000010 // Setup Packet.
+#define USB_TXCSRL2_STALL 0x00000010 // Send Stall.
+#define USB_TXCSRL2_FLUSH 0x00000008 // Flush FIFO.
+#define USB_TXCSRL2_ERROR 0x00000004 // Error.
+#define USB_TXCSRL2_UNDRN 0x00000004 // Underrun.
+#define USB_TXCSRL2_FIFONE 0x00000002 // FIFO Not Empty.
+#define USB_TXCSRL2_TXRDY 0x00000001 // Transmit Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH2 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH2_AUTOSET 0x00000080 // Auto Set.
+#define USB_TXCSRH2_ISO 0x00000040 // ISO.
+#define USB_TXCSRH2_MODE 0x00000020 // Mode.
+#define USB_TXCSRH2_DMAEN 0x00000010 // DMA Request Enable.
+#define USB_TXCSRH2_FDT 0x00000008 // Force Data Toggle.
+#define USB_TXCSRH2_DMAMOD 0x00000004 // DMA Request Mode.
+#define USB_TXCSRH2_DTWE 0x00000002 // Data Toggle Write Enable.
+#define USB_TXCSRH2_DT 0x00000001 // Data Toggle.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP2 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload.
+#define USB_RXMAXP2_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL2 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL2_CLRDT 0x00000080 // Clear Data Toggle.
+#define USB_RXCSRL2_STALLED 0x00000040 // Endpoint Stalled.
+#define USB_RXCSRL2_REQPKT 0x00000020 // Request Packet.
+#define USB_RXCSRL2_STALL 0x00000020 // Send Stall.
+#define USB_RXCSRL2_FLUSH 0x00000010 // Flush FIFO.
+#define USB_RXCSRL2_DATAERR 0x00000008 // Data Error.
+#define USB_RXCSRL2_NAKTO 0x00000008 // NAK Timeout.
+#define USB_RXCSRL2_ERROR 0x00000004 // Error.
+#define USB_RXCSRL2_OVER 0x00000004 // Overrun.
+#define USB_RXCSRL2_FULL 0x00000002 // FIFO Full.
+#define USB_RXCSRL2_RXRDY 0x00000001 // Receive Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH2 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH2_AUTOCL 0x00000080 // Auto Clear.
+#define USB_RXCSRH2_AUTORQ 0x00000040 // Auto Request.
+#define USB_RXCSRH2_ISO 0x00000040 // ISO.
+#define USB_RXCSRH2_DMAEN 0x00000020 // DMA Request Enable.
+#define USB_RXCSRH2_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH2_PIDERR 0x00000010 // PID Error.
+#define USB_RXCSRH2_DMAMOD 0x00000008 // DMA Request Mode.
+#define USB_RXCSRH2_DTWE 0x00000004 // Data Toggle Write Enable.
+#define USB_RXCSRH2_DT 0x00000002 // Data Toggle.
+#define USB_RXCSRH2_INCRX 0x00000001 // Incomplete Receive.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT2 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT2_COUNT_M 0x00001FFF // Receive Packet Count.
+#define USB_RXCOUNT2_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE2 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE2_SPEED_M 0x000000C0 // Operating Speed.
+#define USB_TXTYPE2_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE2_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE2_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE2_PROTO_M 0x00000030 // Protocol.
+#define USB_TXTYPE2_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE2_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE2_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE2_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE2_TEP_M 0x0000000F // Target Endpoint Number.
+#define USB_TXTYPE2_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL2
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL2_NAKLMT_M \
+ 0x000000FF // NAK Limit.
+#define USB_TXINTERVAL2_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL2_NAKLMT_S \
+ 0
+#define USB_TXINTERVAL2_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE2 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE2_SPEED_M 0x000000C0 // Operating Speed.
+#define USB_RXTYPE2_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE2_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE2_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE2_PROTO_M 0x00000030 // Protocol.
+#define USB_RXTYPE2_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE2_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE2_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE2_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE2_TEP_M 0x0000000F // Target Endpoint Number.
+#define USB_RXTYPE2_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL2
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL2_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL2_NAKLMT_M \
+ 0x000000FF // NAK Limit.
+#define USB_RXINTERVAL2_TXPOLL_S \
+ 0
+#define USB_RXINTERVAL2_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP3 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload.
+#define USB_TXMAXP3_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL3 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL3_INCTX 0x00000080 // Incomplete Transmit.
+#define USB_TXCSRL3_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL3_CLRDT 0x00000040 // Clear Data Toggle.
+#define USB_TXCSRL3_STALLED 0x00000020 // Endpoint Stalled.
+#define USB_TXCSRL3_SETUP 0x00000010 // Setup Packet.
+#define USB_TXCSRL3_STALL 0x00000010 // Send Stall.
+#define USB_TXCSRL3_FLUSH 0x00000008 // Flush FIFO.
+#define USB_TXCSRL3_ERROR 0x00000004 // Error.
+#define USB_TXCSRL3_UNDRN 0x00000004 // Underrun.
+#define USB_TXCSRL3_FIFONE 0x00000002 // FIFO Not Empty.
+#define USB_TXCSRL3_TXRDY 0x00000001 // Transmit Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH3 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH3_AUTOSET 0x00000080 // Auto Set.
+#define USB_TXCSRH3_ISO 0x00000040 // ISO.
+#define USB_TXCSRH3_MODE 0x00000020 // Mode.
+#define USB_TXCSRH3_DMAEN 0x00000010 // DMA Request Enable.
+#define USB_TXCSRH3_FDT 0x00000008 // Force Data Toggle.
+#define USB_TXCSRH3_DMAMOD 0x00000004 // DMA Request Mode.
+#define USB_TXCSRH3_DTWE 0x00000002 // Data Toggle Write Enable.
+#define USB_TXCSRH3_DT 0x00000001 // Data Toggle.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP3 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload.
+#define USB_RXMAXP3_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL3 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL3_CLRDT 0x00000080 // Clear Data Toggle.
+#define USB_RXCSRL3_STALLED 0x00000040 // Endpoint Stalled.
+#define USB_RXCSRL3_STALL 0x00000020 // Send Stall.
+#define USB_RXCSRL3_REQPKT 0x00000020 // Request Packet.
+#define USB_RXCSRL3_FLUSH 0x00000010 // Flush FIFO.
+#define USB_RXCSRL3_DATAERR 0x00000008 // Data Error.
+#define USB_RXCSRL3_NAKTO 0x00000008 // NAK Timeout.
+#define USB_RXCSRL3_ERROR 0x00000004 // Error.
+#define USB_RXCSRL3_OVER 0x00000004 // Overrun.
+#define USB_RXCSRL3_FULL 0x00000002 // FIFO Full.
+#define USB_RXCSRL3_RXRDY 0x00000001 // Receive Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH3 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH3_AUTOCL 0x00000080 // Auto Clear.
+#define USB_RXCSRH3_AUTORQ 0x00000040 // Auto Request.
+#define USB_RXCSRH3_ISO 0x00000040 // ISO.
+#define USB_RXCSRH3_DMAEN 0x00000020 // DMA Request Enable.
+#define USB_RXCSRH3_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH3_PIDERR 0x00000010 // PID Error.
+#define USB_RXCSRH3_DMAMOD 0x00000008 // DMA Request Mode.
+#define USB_RXCSRH3_DTWE 0x00000004 // Data Toggle Write Enable.
+#define USB_RXCSRH3_DT 0x00000002 // Data Toggle.
+#define USB_RXCSRH3_INCRX 0x00000001 // Incomplete Receive.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT3 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT3_COUNT_M 0x00001FFF // Receive Packet Count.
+#define USB_RXCOUNT3_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE3 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE3_SPEED_M 0x000000C0 // Operating Speed.
+#define USB_TXTYPE3_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE3_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE3_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE3_PROTO_M 0x00000030 // Protocol.
+#define USB_TXTYPE3_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE3_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE3_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE3_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE3_TEP_M 0x0000000F // Target Endpoint Number.
+#define USB_TXTYPE3_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL3
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL3_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL3_NAKLMT_M \
+ 0x000000FF // NAK Limit.
+#define USB_TXINTERVAL3_TXPOLL_S \
+ 0
+#define USB_TXINTERVAL3_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE3 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE3_SPEED_M 0x000000C0 // Operating Speed.
+#define USB_RXTYPE3_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE3_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE3_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE3_PROTO_M 0x00000030 // Protocol.
+#define USB_RXTYPE3_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE3_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE3_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE3_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE3_TEP_M 0x0000000F // Target Endpoint Number.
+#define USB_RXTYPE3_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL3
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL3_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL3_NAKLMT_M \
+ 0x000000FF // NAK Limit.
+#define USB_RXINTERVAL3_TXPOLL_S \
+ 0
+#define USB_RXINTERVAL3_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP4 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload.
+#define USB_TXMAXP4_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL4 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL4_INCTX 0x00000080 // Incomplete Transmit.
+#define USB_TXCSRL4_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL4_CLRDT 0x00000040 // Clear Data Toggle.
+#define USB_TXCSRL4_STALLED 0x00000020 // Endpoint Stalled.
+#define USB_TXCSRL4_SETUP 0x00000010 // Setup Packet.
+#define USB_TXCSRL4_STALL 0x00000010 // Send Stall.
+#define USB_TXCSRL4_FLUSH 0x00000008 // Flush FIFO.
+#define USB_TXCSRL4_ERROR 0x00000004 // Error.
+#define USB_TXCSRL4_UNDRN 0x00000004 // Underrun.
+#define USB_TXCSRL4_FIFONE 0x00000002 // FIFO Not Empty.
+#define USB_TXCSRL4_TXRDY 0x00000001 // Transmit Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH4 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH4_AUTOSET 0x00000080 // Auto Set.
+#define USB_TXCSRH4_ISO 0x00000040 // ISO.
+#define USB_TXCSRH4_MODE 0x00000020 // Mode.
+#define USB_TXCSRH4_DMAEN 0x00000010 // DMA Request Enable.
+#define USB_TXCSRH4_FDT 0x00000008 // Force Data Toggle.
+#define USB_TXCSRH4_DMAMOD 0x00000004 // DMA Request Mode.
+#define USB_TXCSRH4_DTWE 0x00000002 // Data Toggle Write Enable.
+#define USB_TXCSRH4_DT 0x00000001 // Data Toggle.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP4 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload.
+#define USB_RXMAXP4_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL4 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL4_CLRDT 0x00000080 // Clear Data Toggle.
+#define USB_RXCSRL4_STALLED 0x00000040 // Endpoint Stalled.
+#define USB_RXCSRL4_STALL 0x00000020 // Send Stall.
+#define USB_RXCSRL4_REQPKT 0x00000020 // Request Packet.
+#define USB_RXCSRL4_FLUSH 0x00000010 // Flush FIFO.
+#define USB_RXCSRL4_NAKTO 0x00000008 // NAK Timeout.
+#define USB_RXCSRL4_DATAERR 0x00000008 // Data Error.
+#define USB_RXCSRL4_OVER 0x00000004 // Overrun.
+#define USB_RXCSRL4_ERROR 0x00000004 // Error.
+#define USB_RXCSRL4_FULL 0x00000002 // FIFO Full.
+#define USB_RXCSRL4_RXRDY 0x00000001 // Receive Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH4 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH4_AUTOCL 0x00000080 // Auto Clear.
+#define USB_RXCSRH4_AUTORQ 0x00000040 // Auto Request.
+#define USB_RXCSRH4_ISO 0x00000040 // ISO.
+#define USB_RXCSRH4_DMAEN 0x00000020 // DMA Request Enable.
+#define USB_RXCSRH4_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH4_PIDERR 0x00000010 // PID Error.
+#define USB_RXCSRH4_DMAMOD 0x00000008 // DMA Request Mode.
+#define USB_RXCSRH4_DTWE 0x00000004 // Data Toggle Write Enable.
+#define USB_RXCSRH4_DT 0x00000002 // Data Toggle.
+#define USB_RXCSRH4_INCRX 0x00000001 // Incomplete Receive.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT4 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT4_COUNT_M 0x00001FFF // Receive Packet Count.
+#define USB_RXCOUNT4_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE4 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE4_SPEED_M 0x000000C0 // Operating Speed.
+#define USB_TXTYPE4_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE4_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE4_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE4_PROTO_M 0x00000030 // Protocol.
+#define USB_TXTYPE4_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE4_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE4_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE4_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE4_TEP_M 0x0000000F // Target Endpoint Number.
+#define USB_TXTYPE4_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL4
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL4_NAKLMT_M \
+ 0x000000FF // NAK Limit.
+#define USB_TXINTERVAL4_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL4_NAKLMT_S \
+ 0
+#define USB_TXINTERVAL4_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE4 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE4_SPEED_M 0x000000C0 // Operating Speed.
+#define USB_RXTYPE4_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE4_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE4_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE4_PROTO_M 0x00000030 // Protocol.
+#define USB_RXTYPE4_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE4_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE4_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE4_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE4_TEP_M 0x0000000F // Target Endpoint Number.
+#define USB_RXTYPE4_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL4
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL4_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL4_NAKLMT_M \
+ 0x000000FF // NAK Limit.
+#define USB_RXINTERVAL4_NAKLMT_S \
+ 0
+#define USB_RXINTERVAL4_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP5 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload.
+#define USB_TXMAXP5_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL5 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL5_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL5_INCTX 0x00000080 // Incomplete Transmit.
+#define USB_TXCSRL5_CLRDT 0x00000040 // Clear Data Toggle.
+#define USB_TXCSRL5_STALLED 0x00000020 // Endpoint Stalled.
+#define USB_TXCSRL5_SETUP 0x00000010 // Setup Packet.
+#define USB_TXCSRL5_STALL 0x00000010 // Send Stall.
+#define USB_TXCSRL5_FLUSH 0x00000008 // Flush FIFO.
+#define USB_TXCSRL5_ERROR 0x00000004 // Error.
+#define USB_TXCSRL5_UNDRN 0x00000004 // Underrun.
+#define USB_TXCSRL5_FIFONE 0x00000002 // FIFO Not Empty.
+#define USB_TXCSRL5_TXRDY 0x00000001 // Transmit Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH5 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH5_AUTOSET 0x00000080 // Auto Set.
+#define USB_TXCSRH5_ISO 0x00000040 // ISO.
+#define USB_TXCSRH5_MODE 0x00000020 // Mode.
+#define USB_TXCSRH5_DMAEN 0x00000010 // DMA Request Enable.
+#define USB_TXCSRH5_FDT 0x00000008 // Force Data Toggle.
+#define USB_TXCSRH5_DMAMOD 0x00000004 // DMA Request Mode.
+#define USB_TXCSRH5_DTWE 0x00000002 // Data Toggle Write Enable.
+#define USB_TXCSRH5_DT 0x00000001 // Data Toggle.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP5 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload.
+#define USB_RXMAXP5_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL5 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL5_CLRDT 0x00000080 // Clear Data Toggle.
+#define USB_RXCSRL5_STALLED 0x00000040 // Endpoint Stalled.
+#define USB_RXCSRL5_STALL 0x00000020 // Send Stall.
+#define USB_RXCSRL5_REQPKT 0x00000020 // Request Packet.
+#define USB_RXCSRL5_FLUSH 0x00000010 // Flush FIFO.
+#define USB_RXCSRL5_NAKTO 0x00000008 // NAK Timeout.
+#define USB_RXCSRL5_DATAERR 0x00000008 // Data Error.
+#define USB_RXCSRL5_ERROR 0x00000004 // Error.
+#define USB_RXCSRL5_OVER 0x00000004 // Overrun.
+#define USB_RXCSRL5_FULL 0x00000002 // FIFO Full.
+#define USB_RXCSRL5_RXRDY 0x00000001 // Receive Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH5 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH5_AUTOCL 0x00000080 // Auto Clear.
+#define USB_RXCSRH5_AUTORQ 0x00000040 // Auto Request.
+#define USB_RXCSRH5_ISO 0x00000040 // ISO.
+#define USB_RXCSRH5_DMAEN 0x00000020 // DMA Request Enable.
+#define USB_RXCSRH5_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH5_PIDERR 0x00000010 // PID Error.
+#define USB_RXCSRH5_DMAMOD 0x00000008 // DMA Request Mode.
+#define USB_RXCSRH5_DTWE 0x00000004 // Data Toggle Write Enable.
+#define USB_RXCSRH5_DT 0x00000002 // Data Toggle.
+#define USB_RXCSRH5_INCRX 0x00000001 // Incomplete Receive.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT5 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT5_COUNT_M 0x00001FFF // Receive Packet Count.
+#define USB_RXCOUNT5_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE5 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE5_SPEED_M 0x000000C0 // Operating Speed.
+#define USB_TXTYPE5_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE5_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE5_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE5_PROTO_M 0x00000030 // Protocol.
+#define USB_TXTYPE5_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE5_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE5_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE5_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE5_TEP_M 0x0000000F // Target Endpoint Number.
+#define USB_TXTYPE5_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL5
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL5_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL5_NAKLMT_M \
+ 0x000000FF // NAK Limit.
+#define USB_TXINTERVAL5_NAKLMT_S \
+ 0
+#define USB_TXINTERVAL5_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE5 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE5_SPEED_M 0x000000C0 // Operating Speed.
+#define USB_RXTYPE5_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE5_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE5_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE5_PROTO_M 0x00000030 // Protocol.
+#define USB_RXTYPE5_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE5_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE5_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE5_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE5_TEP_M 0x0000000F // Target Endpoint Number.
+#define USB_RXTYPE5_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL5
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL5_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL5_NAKLMT_M \
+ 0x000000FF // NAK Limit.
+#define USB_RXINTERVAL5_TXPOLL_S \
+ 0
+#define USB_RXINTERVAL5_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP6 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload.
+#define USB_TXMAXP6_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL6 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL6_INCTX 0x00000080 // Incomplete Transmit.
+#define USB_TXCSRL6_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL6_CLRDT 0x00000040 // Clear Data Toggle.
+#define USB_TXCSRL6_STALLED 0x00000020 // Endpoint Stalled.
+#define USB_TXCSRL6_STALL 0x00000010 // Send Stall.
+#define USB_TXCSRL6_SETUP 0x00000010 // Setup Packet.
+#define USB_TXCSRL6_FLUSH 0x00000008 // Flush FIFO.
+#define USB_TXCSRL6_ERROR 0x00000004 // Error.
+#define USB_TXCSRL6_UNDRN 0x00000004 // Underrun.
+#define USB_TXCSRL6_FIFONE 0x00000002 // FIFO Not Empty.
+#define USB_TXCSRL6_TXRDY 0x00000001 // Transmit Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH6 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH6_AUTOSET 0x00000080 // Auto Set.
+#define USB_TXCSRH6_ISO 0x00000040 // ISO.
+#define USB_TXCSRH6_MODE 0x00000020 // Mode.
+#define USB_TXCSRH6_DMAEN 0x00000010 // DMA Request Enable.
+#define USB_TXCSRH6_FDT 0x00000008 // Force Data Toggle.
+#define USB_TXCSRH6_DMAMOD 0x00000004 // DMA Request Mode.
+#define USB_TXCSRH6_DTWE 0x00000002 // Data Toggle Write Enable.
+#define USB_TXCSRH6_DT 0x00000001 // Data Toggle.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP6 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload.
+#define USB_RXMAXP6_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL6 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL6_CLRDT 0x00000080 // Clear Data Toggle.
+#define USB_RXCSRL6_STALLED 0x00000040 // Endpoint Stalled.
+#define USB_RXCSRL6_REQPKT 0x00000020 // Request Packet.
+#define USB_RXCSRL6_STALL 0x00000020 // Send Stall.
+#define USB_RXCSRL6_FLUSH 0x00000010 // Flush FIFO.
+#define USB_RXCSRL6_NAKTO 0x00000008 // NAK Timeout.
+#define USB_RXCSRL6_DATAERR 0x00000008 // Data Error.
+#define USB_RXCSRL6_ERROR 0x00000004 // Error.
+#define USB_RXCSRL6_OVER 0x00000004 // Overrun.
+#define USB_RXCSRL6_FULL 0x00000002 // FIFO Full.
+#define USB_RXCSRL6_RXRDY 0x00000001 // Receive Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH6 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH6_AUTOCL 0x00000080 // Auto Clear.
+#define USB_RXCSRH6_AUTORQ 0x00000040 // Auto Request.
+#define USB_RXCSRH6_ISO 0x00000040 // ISO.
+#define USB_RXCSRH6_DMAEN 0x00000020 // DMA Request Enable.
+#define USB_RXCSRH6_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH6_PIDERR 0x00000010 // PID Error.
+#define USB_RXCSRH6_DMAMOD 0x00000008 // DMA Request Mode.
+#define USB_RXCSRH6_DTWE 0x00000004 // Data Toggle Write Enable.
+#define USB_RXCSRH6_DT 0x00000002 // Data Toggle.
+#define USB_RXCSRH6_INCRX 0x00000001 // Incomplete Receive.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT6 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT6_COUNT_M 0x00001FFF // Receive Packet Count.
+#define USB_RXCOUNT6_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE6 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE6_SPEED_M 0x000000C0 // Operating Speed.
+#define USB_TXTYPE6_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE6_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE6_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE6_PROTO_M 0x00000030 // Protocol.
+#define USB_TXTYPE6_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE6_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE6_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE6_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE6_TEP_M 0x0000000F // Target Endpoint Number.
+#define USB_TXTYPE6_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL6
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL6_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL6_NAKLMT_M \
+ 0x000000FF // NAK Limit.
+#define USB_TXINTERVAL6_TXPOLL_S \
+ 0
+#define USB_TXINTERVAL6_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE6 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE6_SPEED_M 0x000000C0 // Operating Speed.
+#define USB_RXTYPE6_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE6_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE6_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE6_PROTO_M 0x00000030 // Protocol.
+#define USB_RXTYPE6_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE6_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE6_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE6_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE6_TEP_M 0x0000000F // Target Endpoint Number.
+#define USB_RXTYPE6_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL6
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL6_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL6_NAKLMT_M \
+ 0x000000FF // NAK Limit.
+#define USB_RXINTERVAL6_NAKLMT_S \
+ 0
+#define USB_RXINTERVAL6_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP7 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload.
+#define USB_TXMAXP7_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL7 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL7_INCTX 0x00000080 // Incomplete Transmit.
+#define USB_TXCSRL7_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL7_CLRDT 0x00000040 // Clear Data Toggle.
+#define USB_TXCSRL7_STALLED 0x00000020 // Endpoint Stalled.
+#define USB_TXCSRL7_STALL 0x00000010 // Send Stall.
+#define USB_TXCSRL7_SETUP 0x00000010 // Setup Packet.
+#define USB_TXCSRL7_FLUSH 0x00000008 // Flush FIFO.
+#define USB_TXCSRL7_ERROR 0x00000004 // Error.
+#define USB_TXCSRL7_UNDRN 0x00000004 // Underrun.
+#define USB_TXCSRL7_FIFONE 0x00000002 // FIFO Not Empty.
+#define USB_TXCSRL7_TXRDY 0x00000001 // Transmit Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH7 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH7_AUTOSET 0x00000080 // Auto Set.
+#define USB_TXCSRH7_ISO 0x00000040 // ISO.
+#define USB_TXCSRH7_MODE 0x00000020 // Mode.
+#define USB_TXCSRH7_DMAEN 0x00000010 // DMA Request Enable.
+#define USB_TXCSRH7_FDT 0x00000008 // Force Data Toggle.
+#define USB_TXCSRH7_DMAMOD 0x00000004 // DMA Request Mode.
+#define USB_TXCSRH7_DTWE 0x00000002 // Data Toggle Write Enable.
+#define USB_TXCSRH7_DT 0x00000001 // Data Toggle.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP7 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload.
+#define USB_RXMAXP7_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL7 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL7_CLRDT 0x00000080 // Clear Data Toggle.
+#define USB_RXCSRL7_STALLED 0x00000040 // Endpoint Stalled.
+#define USB_RXCSRL7_REQPKT 0x00000020 // Request Packet.
+#define USB_RXCSRL7_STALL 0x00000020 // Send Stall.
+#define USB_RXCSRL7_FLUSH 0x00000010 // Flush FIFO.
+#define USB_RXCSRL7_DATAERR 0x00000008 // Data Error.
+#define USB_RXCSRL7_NAKTO 0x00000008 // NAK Timeout.
+#define USB_RXCSRL7_ERROR 0x00000004 // Error.
+#define USB_RXCSRL7_OVER 0x00000004 // Overrun.
+#define USB_RXCSRL7_FULL 0x00000002 // FIFO Full.
+#define USB_RXCSRL7_RXRDY 0x00000001 // Receive Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH7 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH7_AUTOCL 0x00000080 // Auto Clear.
+#define USB_RXCSRH7_ISO 0x00000040 // ISO.
+#define USB_RXCSRH7_AUTORQ 0x00000040 // Auto Request.
+#define USB_RXCSRH7_DMAEN 0x00000020 // DMA Request Enable.
+#define USB_RXCSRH7_PIDERR 0x00000010 // PID Error.
+#define USB_RXCSRH7_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH7_DMAMOD 0x00000008 // DMA Request Mode.
+#define USB_RXCSRH7_DTWE 0x00000004 // Data Toggle Write Enable.
+#define USB_RXCSRH7_DT 0x00000002 // Data Toggle.
+#define USB_RXCSRH7_INCRX 0x00000001 // Incomplete Receive.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT7 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT7_COUNT_M 0x00001FFF // Receive Packet Count.
+#define USB_RXCOUNT7_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE7 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE7_SPEED_M 0x000000C0 // Operating Speed.
+#define USB_TXTYPE7_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE7_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE7_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE7_PROTO_M 0x00000030 // Protocol.
+#define USB_TXTYPE7_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE7_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE7_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE7_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE7_TEP_M 0x0000000F // Target Endpoint Number.
+#define USB_TXTYPE7_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL7
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL7_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL7_NAKLMT_M \
+ 0x000000FF // NAK Limit.
+#define USB_TXINTERVAL7_NAKLMT_S \
+ 0
+#define USB_TXINTERVAL7_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE7 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE7_SPEED_M 0x000000C0 // Operating Speed.
+#define USB_RXTYPE7_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE7_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE7_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE7_PROTO_M 0x00000030 // Protocol.
+#define USB_RXTYPE7_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE7_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE7_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE7_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE7_TEP_M 0x0000000F // Target Endpoint Number.
+#define USB_RXTYPE7_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL7
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL7_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL7_NAKLMT_M \
+ 0x000000FF // NAK Limit.
+#define USB_RXINTERVAL7_NAKLMT_S \
+ 0
+#define USB_RXINTERVAL7_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP8 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP8_MAXLOAD_M 0x000007FF // Maximum Payload.
+#define USB_TXMAXP8_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL8 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL8_INCTX 0x00000080 // Incomplete Transmit.
+#define USB_TXCSRL8_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL8_CLRDT 0x00000040 // Clear Data Toggle.
+#define USB_TXCSRL8_STALLED 0x00000020 // Endpoint Stalled.
+#define USB_TXCSRL8_STALL 0x00000010 // Send Stall.
+#define USB_TXCSRL8_SETUP 0x00000010 // Setup Packet.
+#define USB_TXCSRL8_FLUSH 0x00000008 // Flush FIFO.
+#define USB_TXCSRL8_ERROR 0x00000004 // Error.
+#define USB_TXCSRL8_UNDRN 0x00000004 // Underrun.
+#define USB_TXCSRL8_FIFONE 0x00000002 // FIFO Not Empty.
+#define USB_TXCSRL8_TXRDY 0x00000001 // Transmit Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH8 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH8_AUTOSET 0x00000080 // Auto Set.
+#define USB_TXCSRH8_ISO 0x00000040 // ISO.
+#define USB_TXCSRH8_MODE 0x00000020 // Mode.
+#define USB_TXCSRH8_DMAEN 0x00000010 // DMA Request Enable.
+#define USB_TXCSRH8_FDT 0x00000008 // Force Data Toggle.
+#define USB_TXCSRH8_DMAMOD 0x00000004 // DMA Request Mode.
+#define USB_TXCSRH8_DTWE 0x00000002 // Data Toggle Write Enable.
+#define USB_TXCSRH8_DT 0x00000001 // Data Toggle.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP8 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP8_MAXLOAD_M 0x000007FF // Maximum Payload.
+#define USB_RXMAXP8_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL8 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL8_CLRDT 0x00000080 // Clear Data Toggle.
+#define USB_RXCSRL8_STALLED 0x00000040 // Endpoint Stalled.
+#define USB_RXCSRL8_STALL 0x00000020 // Send Stall.
+#define USB_RXCSRL8_REQPKT 0x00000020 // Request Packet.
+#define USB_RXCSRL8_FLUSH 0x00000010 // Flush FIFO.
+#define USB_RXCSRL8_NAKTO 0x00000008 // NAK Timeout.
+#define USB_RXCSRL8_DATAERR 0x00000008 // Data Error.
+#define USB_RXCSRL8_OVER 0x00000004 // Overrun.
+#define USB_RXCSRL8_ERROR 0x00000004 // Error.
+#define USB_RXCSRL8_FULL 0x00000002 // FIFO Full.
+#define USB_RXCSRL8_RXRDY 0x00000001 // Receive Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH8 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH8_AUTOCL 0x00000080 // Auto Clear.
+#define USB_RXCSRH8_AUTORQ 0x00000040 // Auto Request.
+#define USB_RXCSRH8_ISO 0x00000040 // ISO.
+#define USB_RXCSRH8_DMAEN 0x00000020 // DMA Request Enable.
+#define USB_RXCSRH8_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH8_PIDERR 0x00000010 // PID Error.
+#define USB_RXCSRH8_DMAMOD 0x00000008 // DMA Request Mode.
+#define USB_RXCSRH8_DTWE 0x00000004 // Data Toggle Write Enable.
+#define USB_RXCSRH8_DT 0x00000002 // Data Toggle.
+#define USB_RXCSRH8_INCRX 0x00000001 // Incomplete Receive.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT8 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT8_COUNT_M 0x00001FFF // Receive Packet Count.
+#define USB_RXCOUNT8_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE8 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE8_SPEED_M 0x000000C0 // Operating Speed.
+#define USB_TXTYPE8_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE8_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE8_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE8_PROTO_M 0x00000030 // Protocol.
+#define USB_TXTYPE8_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE8_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE8_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE8_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE8_TEP_M 0x0000000F // Target Endpoint Number.
+#define USB_TXTYPE8_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL8
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL8_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL8_NAKLMT_M \
+ 0x000000FF // NAK Limit.
+#define USB_TXINTERVAL8_NAKLMT_S \
+ 0
+#define USB_TXINTERVAL8_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE8 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE8_SPEED_M 0x000000C0 // Operating Speed.
+#define USB_RXTYPE8_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE8_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE8_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE8_PROTO_M 0x00000030 // Protocol.
+#define USB_RXTYPE8_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE8_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE8_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE8_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE8_TEP_M 0x0000000F // Target Endpoint Number.
+#define USB_RXTYPE8_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL8
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL8_NAKLMT_M \
+ 0x000000FF // NAK Limit.
+#define USB_RXINTERVAL8_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL8_NAKLMT_S \
+ 0
+#define USB_RXINTERVAL8_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP9 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP9_MAXLOAD_M 0x000007FF // Maximum Payload.
+#define USB_TXMAXP9_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL9 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL9_INCTX 0x00000080 // Incomplete Transmit.
+#define USB_TXCSRL9_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL9_CLRDT 0x00000040 // Clear Data Toggle.
+#define USB_TXCSRL9_STALLED 0x00000020 // Endpoint Stalled.
+#define USB_TXCSRL9_SETUP 0x00000010 // Setup Packet.
+#define USB_TXCSRL9_STALL 0x00000010 // Send Stall.
+#define USB_TXCSRL9_FLUSH 0x00000008 // Flush FIFO.
+#define USB_TXCSRL9_ERROR 0x00000004 // Error.
+#define USB_TXCSRL9_UNDRN 0x00000004 // Underrun.
+#define USB_TXCSRL9_FIFONE 0x00000002 // FIFO Not Empty.
+#define USB_TXCSRL9_TXRDY 0x00000001 // Transmit Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH9 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH9_AUTOSET 0x00000080 // Auto Set.
+#define USB_TXCSRH9_ISO 0x00000040 // ISO.
+#define USB_TXCSRH9_MODE 0x00000020 // Mode.
+#define USB_TXCSRH9_DMAEN 0x00000010 // DMA Request Enable.
+#define USB_TXCSRH9_FDT 0x00000008 // Force Data Toggle.
+#define USB_TXCSRH9_DMAMOD 0x00000004 // DMA Request Mode.
+#define USB_TXCSRH9_DTWE 0x00000002 // Data Toggle Write Enable.
+#define USB_TXCSRH9_DT 0x00000001 // Data Toggle.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP9 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP9_MAXLOAD_M 0x000007FF // Maximum Payload.
+#define USB_RXMAXP9_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL9 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL9_CLRDT 0x00000080 // Clear Data Toggle.
+#define USB_RXCSRL9_STALLED 0x00000040 // Endpoint Stalled.
+#define USB_RXCSRL9_STALL 0x00000020 // Send Stall.
+#define USB_RXCSRL9_REQPKT 0x00000020 // Request Packet.
+#define USB_RXCSRL9_FLUSH 0x00000010 // Flush FIFO.
+#define USB_RXCSRL9_DATAERR 0x00000008 // Data Error.
+#define USB_RXCSRL9_NAKTO 0x00000008 // NAK Timeout.
+#define USB_RXCSRL9_ERROR 0x00000004 // Error.
+#define USB_RXCSRL9_OVER 0x00000004 // Overrun.
+#define USB_RXCSRL9_FULL 0x00000002 // FIFO Full.
+#define USB_RXCSRL9_RXRDY 0x00000001 // Receive Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH9 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH9_AUTOCL 0x00000080 // Auto Clear.
+#define USB_RXCSRH9_ISO 0x00000040 // ISO.
+#define USB_RXCSRH9_AUTORQ 0x00000040 // Auto Request.
+#define USB_RXCSRH9_DMAEN 0x00000020 // DMA Request Enable.
+#define USB_RXCSRH9_PIDERR 0x00000010 // PID Error.
+#define USB_RXCSRH9_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH9_DMAMOD 0x00000008 // DMA Request Mode.
+#define USB_RXCSRH9_DTWE 0x00000004 // Data Toggle Write Enable.
+#define USB_RXCSRH9_DT 0x00000002 // Data Toggle.
+#define USB_RXCSRH9_INCRX 0x00000001 // Incomplete Receive.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT9 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT9_COUNT_M 0x00001FFF // Receive Packet Count.
+#define USB_RXCOUNT9_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE9 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE9_SPEED_M 0x000000C0 // Operating Speed.
+#define USB_TXTYPE9_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE9_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE9_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE9_PROTO_M 0x00000030 // Protocol.
+#define USB_TXTYPE9_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE9_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE9_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE9_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE9_TEP_M 0x0000000F // Target Endpoint Number.
+#define USB_TXTYPE9_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL9
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL9_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL9_NAKLMT_M \
+ 0x000000FF // NAK Limit.
+#define USB_TXINTERVAL9_TXPOLL_S \
+ 0
+#define USB_TXINTERVAL9_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE9 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE9_SPEED_M 0x000000C0 // Operating Speed.
+#define USB_RXTYPE9_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE9_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE9_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE9_PROTO_M 0x00000030 // Protocol.
+#define USB_RXTYPE9_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE9_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE9_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE9_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE9_TEP_M 0x0000000F // Target Endpoint Number.
+#define USB_RXTYPE9_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL9
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL9_NAKLMT_M \
+ 0x000000FF // NAK Limit.
+#define USB_RXINTERVAL9_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL9_NAKLMT_S \
+ 0
+#define USB_RXINTERVAL9_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP10 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP10_MAXLOAD_M 0x000007FF // Maximum Payload.
+#define USB_TXMAXP10_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL10 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL10_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL10_INCTX 0x00000080 // Incomplete Transmit.
+#define USB_TXCSRL10_CLRDT 0x00000040 // Clear Data Toggle.
+#define USB_TXCSRL10_STALLED 0x00000020 // Endpoint Stalled.
+#define USB_TXCSRL10_SETUP 0x00000010 // Setup Packet.
+#define USB_TXCSRL10_STALL 0x00000010 // Send Stall.
+#define USB_TXCSRL10_FLUSH 0x00000008 // Flush FIFO.
+#define USB_TXCSRL10_UNDRN 0x00000004 // Underrun.
+#define USB_TXCSRL10_ERROR 0x00000004 // Error.
+#define USB_TXCSRL10_FIFONE 0x00000002 // FIFO Not Empty.
+#define USB_TXCSRL10_TXRDY 0x00000001 // Transmit Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH10 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH10_AUTOSET 0x00000080 // Auto Set.
+#define USB_TXCSRH10_ISO 0x00000040 // ISO.
+#define USB_TXCSRH10_MODE 0x00000020 // Mode.
+#define USB_TXCSRH10_DMAEN 0x00000010 // DMA Request Enable.
+#define USB_TXCSRH10_FDT 0x00000008 // Force Data Toggle.
+#define USB_TXCSRH10_DMAMOD 0x00000004 // DMA Request Mode.
+#define USB_TXCSRH10_DTWE 0x00000002 // Data Toggle Write Enable.
+#define USB_TXCSRH10_DT 0x00000001 // Data Toggle.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP10 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP10_MAXLOAD_M 0x000007FF // Maximum Payload.
+#define USB_RXMAXP10_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL10 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL10_CLRDT 0x00000080 // Clear Data Toggle.
+#define USB_RXCSRL10_STALLED 0x00000040 // Endpoint Stalled.
+#define USB_RXCSRL10_STALL 0x00000020 // Send Stall.
+#define USB_RXCSRL10_REQPKT 0x00000020 // Request Packet.
+#define USB_RXCSRL10_FLUSH 0x00000010 // Flush FIFO.
+#define USB_RXCSRL10_NAKTO 0x00000008 // NAK Timeout.
+#define USB_RXCSRL10_DATAERR 0x00000008 // Data Error.
+#define USB_RXCSRL10_OVER 0x00000004 // Overrun.
+#define USB_RXCSRL10_ERROR 0x00000004 // Error.
+#define USB_RXCSRL10_FULL 0x00000002 // FIFO Full.
+#define USB_RXCSRL10_RXRDY 0x00000001 // Receive Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH10 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH10_AUTOCL 0x00000080 // Auto Clear.
+#define USB_RXCSRH10_AUTORQ 0x00000040 // Auto Request.
+#define USB_RXCSRH10_ISO 0x00000040 // ISO.
+#define USB_RXCSRH10_DMAEN 0x00000020 // DMA Request Enable.
+#define USB_RXCSRH10_PIDERR 0x00000010 // PID Error.
+#define USB_RXCSRH10_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH10_DMAMOD 0x00000008 // DMA Request Mode.
+#define USB_RXCSRH10_DTWE 0x00000004 // Data Toggle Write Enable.
+#define USB_RXCSRH10_DT 0x00000002 // Data Toggle.
+#define USB_RXCSRH10_INCRX 0x00000001 // Incomplete Receive.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT10
+// register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT10_COUNT_M 0x00001FFF // Receive Packet Count.
+#define USB_RXCOUNT10_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE10 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE10_SPEED_M 0x000000C0 // Operating Speed.
+#define USB_TXTYPE10_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE10_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE10_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE10_PROTO_M 0x00000030 // Protocol.
+#define USB_TXTYPE10_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE10_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE10_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE10_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE10_TEP_M 0x0000000F // Target Endpoint Number.
+#define USB_TXTYPE10_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL10
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL10_NAKLMT_M \
+ 0x000000FF // NAK Limit.
+#define USB_TXINTERVAL10_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL10_TXPOLL_S \
+ 0
+#define USB_TXINTERVAL10_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE10 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE10_SPEED_M 0x000000C0 // Operating Speed.
+#define USB_RXTYPE10_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE10_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE10_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE10_PROTO_M 0x00000030 // Protocol.
+#define USB_RXTYPE10_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE10_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE10_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE10_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE10_TEP_M 0x0000000F // Target Endpoint Number.
+#define USB_RXTYPE10_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL10
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL10_NAKLMT_M \
+ 0x000000FF // NAK Limit.
+#define USB_RXINTERVAL10_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL10_TXPOLL_S \
+ 0
+#define USB_RXINTERVAL10_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP11 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP11_MAXLOAD_M 0x000007FF // Maximum Payload.
+#define USB_TXMAXP11_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL11 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL11_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL11_INCTX 0x00000080 // Incomplete Transmit.
+#define USB_TXCSRL11_CLRDT 0x00000040 // Clear Data Toggle.
+#define USB_TXCSRL11_STALLED 0x00000020 // Endpoint Stalled.
+#define USB_TXCSRL11_STALL 0x00000010 // Send Stall.
+#define USB_TXCSRL11_SETUP 0x00000010 // Setup Packet.
+#define USB_TXCSRL11_FLUSH 0x00000008 // Flush FIFO.
+#define USB_TXCSRL11_ERROR 0x00000004 // Error.
+#define USB_TXCSRL11_UNDRN 0x00000004 // Underrun.
+#define USB_TXCSRL11_FIFONE 0x00000002 // FIFO Not Empty.
+#define USB_TXCSRL11_TXRDY 0x00000001 // Transmit Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH11 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH11_AUTOSET 0x00000080 // Auto Set.
+#define USB_TXCSRH11_ISO 0x00000040 // ISO.
+#define USB_TXCSRH11_MODE 0x00000020 // Mode.
+#define USB_TXCSRH11_DMAEN 0x00000010 // DMA Request Enable.
+#define USB_TXCSRH11_FDT 0x00000008 // Force Data Toggle.
+#define USB_TXCSRH11_DMAMOD 0x00000004 // DMA Request Mode.
+#define USB_TXCSRH11_DTWE 0x00000002 // Data Toggle Write Enable.
+#define USB_TXCSRH11_DT 0x00000001 // Data Toggle.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP11 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP11_MAXLOAD_M 0x000007FF // Maximum Payload.
+#define USB_RXMAXP11_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL11 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL11_CLRDT 0x00000080 // Clear Data Toggle.
+#define USB_RXCSRL11_STALLED 0x00000040 // Endpoint Stalled.
+#define USB_RXCSRL11_STALL 0x00000020 // Send Stall.
+#define USB_RXCSRL11_REQPKT 0x00000020 // Request Packet.
+#define USB_RXCSRL11_FLUSH 0x00000010 // Flush FIFO.
+#define USB_RXCSRL11_DATAERR 0x00000008 // Data Error.
+#define USB_RXCSRL11_NAKTO 0x00000008 // NAK Timeout.
+#define USB_RXCSRL11_OVER 0x00000004 // Overrun.
+#define USB_RXCSRL11_ERROR 0x00000004 // Error.
+#define USB_RXCSRL11_FULL 0x00000002 // FIFO Full.
+#define USB_RXCSRL11_RXRDY 0x00000001 // Receive Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH11 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH11_AUTOCL 0x00000080 // Auto Clear.
+#define USB_RXCSRH11_ISO 0x00000040 // ISO.
+#define USB_RXCSRH11_AUTORQ 0x00000040 // Auto Request.
+#define USB_RXCSRH11_DMAEN 0x00000020 // DMA Request Enable.
+#define USB_RXCSRH11_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH11_PIDERR 0x00000010 // PID Error.
+#define USB_RXCSRH11_DMAMOD 0x00000008 // DMA Request Mode.
+#define USB_RXCSRH11_DTWE 0x00000004 // Data Toggle Write Enable.
+#define USB_RXCSRH11_DT 0x00000002 // Data Toggle.
+#define USB_RXCSRH11_INCRX 0x00000001 // Incomplete Receive.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT11
+// register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT11_COUNT_M 0x00001FFF // Receive Packet Count.
+#define USB_RXCOUNT11_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE11 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE11_SPEED_M 0x000000C0 // Operating Speed.
+#define USB_TXTYPE11_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE11_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE11_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE11_PROTO_M 0x00000030 // Protocol.
+#define USB_TXTYPE11_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE11_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE11_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE11_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE11_TEP_M 0x0000000F // Target Endpoint Number.
+#define USB_TXTYPE11_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL11
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL11_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL11_NAKLMT_M \
+ 0x000000FF // NAK Limit.
+#define USB_TXINTERVAL11_NAKLMT_S \
+ 0
+#define USB_TXINTERVAL11_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE11 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE11_SPEED_M 0x000000C0 // Operating Speed.
+#define USB_RXTYPE11_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE11_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE11_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE11_PROTO_M 0x00000030 // Protocol.
+#define USB_RXTYPE11_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE11_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE11_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE11_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE11_TEP_M 0x0000000F // Target Endpoint Number.
+#define USB_RXTYPE11_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL11
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL11_NAKLMT_M \
+ 0x000000FF // NAK Limit.
+#define USB_RXINTERVAL11_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL11_TXPOLL_S \
+ 0
+#define USB_RXINTERVAL11_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP12 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP12_MAXLOAD_M 0x000007FF // Maximum Payload.
+#define USB_TXMAXP12_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL12 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL12_INCTX 0x00000080 // Incomplete Transmit.
+#define USB_TXCSRL12_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL12_CLRDT 0x00000040 // Clear Data Toggle.
+#define USB_TXCSRL12_STALLED 0x00000020 // Endpoint Stalled.
+#define USB_TXCSRL12_SETUP 0x00000010 // Setup Packet.
+#define USB_TXCSRL12_STALL 0x00000010 // Send Stall.
+#define USB_TXCSRL12_FLUSH 0x00000008 // Flush FIFO.
+#define USB_TXCSRL12_UNDRN 0x00000004 // Underrun.
+#define USB_TXCSRL12_ERROR 0x00000004 // Error.
+#define USB_TXCSRL12_FIFONE 0x00000002 // FIFO Not Empty.
+#define USB_TXCSRL12_TXRDY 0x00000001 // Transmit Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH12 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH12_AUTOSET 0x00000080 // Auto Set.
+#define USB_TXCSRH12_ISO 0x00000040 // ISO.
+#define USB_TXCSRH12_MODE 0x00000020 // Mode.
+#define USB_TXCSRH12_DMAEN 0x00000010 // DMA Request Enable.
+#define USB_TXCSRH12_FDT 0x00000008 // Force Data Toggle.
+#define USB_TXCSRH12_DMAMOD 0x00000004 // DMA Request Mode.
+#define USB_TXCSRH12_DTWE 0x00000002 // Data Toggle Write Enable.
+#define USB_TXCSRH12_DT 0x00000001 // Data Toggle.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP12 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP12_MAXLOAD_M 0x000007FF // Maximum Payload.
+#define USB_RXMAXP12_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL12 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL12_CLRDT 0x00000080 // Clear Data Toggle.
+#define USB_RXCSRL12_STALLED 0x00000040 // Endpoint Stalled.
+#define USB_RXCSRL12_STALL 0x00000020 // Send Stall.
+#define USB_RXCSRL12_REQPKT 0x00000020 // Request Packet.
+#define USB_RXCSRL12_FLUSH 0x00000010 // Flush FIFO.
+#define USB_RXCSRL12_NAKTO 0x00000008 // NAK Timeout.
+#define USB_RXCSRL12_DATAERR 0x00000008 // Data Error.
+#define USB_RXCSRL12_ERROR 0x00000004 // Error.
+#define USB_RXCSRL12_OVER 0x00000004 // Overrun.
+#define USB_RXCSRL12_FULL 0x00000002 // FIFO Full.
+#define USB_RXCSRL12_RXRDY 0x00000001 // Receive Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH12 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH12_AUTOCL 0x00000080 // Auto Clear.
+#define USB_RXCSRH12_ISO 0x00000040 // ISO.
+#define USB_RXCSRH12_AUTORQ 0x00000040 // Auto Request.
+#define USB_RXCSRH12_DMAEN 0x00000020 // DMA Request Enable.
+#define USB_RXCSRH12_PIDERR 0x00000010 // PID Error.
+#define USB_RXCSRH12_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH12_DMAMOD 0x00000008 // DMA Request Mode.
+#define USB_RXCSRH12_DTWE 0x00000004 // Data Toggle Write Enable.
+#define USB_RXCSRH12_DT 0x00000002 // Data Toggle.
+#define USB_RXCSRH12_INCRX 0x00000001 // Incomplete Receive.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT12
+// register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT12_COUNT_M 0x00001FFF // Receive Packet Count.
+#define USB_RXCOUNT12_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE12 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE12_SPEED_M 0x000000C0 // Operating Speed.
+#define USB_TXTYPE12_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE12_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE12_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE12_PROTO_M 0x00000030 // Protocol.
+#define USB_TXTYPE12_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE12_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE12_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE12_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE12_TEP_M 0x0000000F // Target Endpoint Number.
+#define USB_TXTYPE12_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL12
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL12_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL12_NAKLMT_M \
+ 0x000000FF // NAK Limit.
+#define USB_TXINTERVAL12_TXPOLL_S \
+ 0
+#define USB_TXINTERVAL12_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE12 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE12_SPEED_M 0x000000C0 // Operating Speed.
+#define USB_RXTYPE12_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE12_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE12_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE12_PROTO_M 0x00000030 // Protocol.
+#define USB_RXTYPE12_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE12_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE12_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE12_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE12_TEP_M 0x0000000F // Target Endpoint Number.
+#define USB_RXTYPE12_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL12
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL12_NAKLMT_M \
+ 0x000000FF // NAK Limit.
+#define USB_RXINTERVAL12_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL12_NAKLMT_S \
+ 0
+#define USB_RXINTERVAL12_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP13 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP13_MAXLOAD_M 0x000007FF // Maximum Payload.
+#define USB_TXMAXP13_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL13 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL13_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL13_INCTX 0x00000080 // Incomplete Transmit.
+#define USB_TXCSRL13_CLRDT 0x00000040 // Clear Data Toggle.
+#define USB_TXCSRL13_STALLED 0x00000020 // Endpoint Stalled.
+#define USB_TXCSRL13_SETUP 0x00000010 // Setup Packet.
+#define USB_TXCSRL13_STALL 0x00000010 // Send Stall.
+#define USB_TXCSRL13_FLUSH 0x00000008 // Flush FIFO.
+#define USB_TXCSRL13_UNDRN 0x00000004 // Underrun.
+#define USB_TXCSRL13_ERROR 0x00000004 // Error.
+#define USB_TXCSRL13_FIFONE 0x00000002 // FIFO Not Empty.
+#define USB_TXCSRL13_TXRDY 0x00000001 // Transmit Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH13 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH13_AUTOSET 0x00000080 // Auto Set.
+#define USB_TXCSRH13_ISO 0x00000040 // ISO.
+#define USB_TXCSRH13_MODE 0x00000020 // Mode.
+#define USB_TXCSRH13_DMAEN 0x00000010 // DMA Request Enable.
+#define USB_TXCSRH13_FDT 0x00000008 // Force Data Toggle.
+#define USB_TXCSRH13_DMAMOD 0x00000004 // DMA Request Mode.
+#define USB_TXCSRH13_DTWE 0x00000002 // Data Toggle Write Enable.
+#define USB_TXCSRH13_DT 0x00000001 // Data Toggle.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP13 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP13_MAXLOAD_M 0x000007FF // Maximum Payload.
+#define USB_RXMAXP13_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL13 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL13_CLRDT 0x00000080 // Clear Data Toggle.
+#define USB_RXCSRL13_STALLED 0x00000040 // Endpoint Stalled.
+#define USB_RXCSRL13_REQPKT 0x00000020 // Request Packet.
+#define USB_RXCSRL13_STALL 0x00000020 // Send Stall.
+#define USB_RXCSRL13_FLUSH 0x00000010 // Flush FIFO.
+#define USB_RXCSRL13_NAKTO 0x00000008 // NAK Timeout.
+#define USB_RXCSRL13_DATAERR 0x00000008 // Data Error.
+#define USB_RXCSRL13_OVER 0x00000004 // Overrun.
+#define USB_RXCSRL13_ERROR 0x00000004 // Error.
+#define USB_RXCSRL13_FULL 0x00000002 // FIFO Full.
+#define USB_RXCSRL13_RXRDY 0x00000001 // Receive Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH13 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH13_AUTOCL 0x00000080 // Auto Clear.
+#define USB_RXCSRH13_ISO 0x00000040 // ISO.
+#define USB_RXCSRH13_AUTORQ 0x00000040 // Auto Request.
+#define USB_RXCSRH13_DMAEN 0x00000020 // DMA Request Enable.
+#define USB_RXCSRH13_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH13_PIDERR 0x00000010 // PID Error.
+#define USB_RXCSRH13_DMAMOD 0x00000008 // DMA Request Mode.
+#define USB_RXCSRH13_DTWE 0x00000004 // Data Toggle Write Enable.
+#define USB_RXCSRH13_DT 0x00000002 // Data Toggle.
+#define USB_RXCSRH13_INCRX 0x00000001 // Incomplete Receive.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT13
+// register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT13_COUNT_M 0x00001FFF // Receive Packet Count.
+#define USB_RXCOUNT13_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE13 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE13_SPEED_M 0x000000C0 // Operating Speed.
+#define USB_TXTYPE13_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE13_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE13_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE13_PROTO_M 0x00000030 // Protocol.
+#define USB_TXTYPE13_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE13_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE13_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE13_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE13_TEP_M 0x0000000F // Target Endpoint Number.
+#define USB_TXTYPE13_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL13
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL13_NAKLMT_M \
+ 0x000000FF // NAK Limit.
+#define USB_TXINTERVAL13_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL13_TXPOLL_S \
+ 0
+#define USB_TXINTERVAL13_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE13 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE13_SPEED_M 0x000000C0 // Operating Speed.
+#define USB_RXTYPE13_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE13_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE13_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE13_PROTO_M 0x00000030 // Protocol.
+#define USB_RXTYPE13_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE13_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE13_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE13_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE13_TEP_M 0x0000000F // Target Endpoint Number.
+#define USB_RXTYPE13_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL13
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL13_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL13_NAKLMT_M \
+ 0x000000FF // NAK Limit.
+#define USB_RXINTERVAL13_NAKLMT_S \
+ 0
+#define USB_RXINTERVAL13_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP14 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP14_MAXLOAD_M 0x000007FF // Maximum Payload.
+#define USB_TXMAXP14_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL14 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL14_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL14_INCTX 0x00000080 // Incomplete Transmit.
+#define USB_TXCSRL14_CLRDT 0x00000040 // Clear Data Toggle.
+#define USB_TXCSRL14_STALLED 0x00000020 // Endpoint Stalled.
+#define USB_TXCSRL14_STALL 0x00000010 // Send Stall.
+#define USB_TXCSRL14_SETUP 0x00000010 // Setup Packet.
+#define USB_TXCSRL14_FLUSH 0x00000008 // Flush FIFO.
+#define USB_TXCSRL14_ERROR 0x00000004 // Error.
+#define USB_TXCSRL14_UNDRN 0x00000004 // Underrun.
+#define USB_TXCSRL14_FIFONE 0x00000002 // FIFO Not Empty.
+#define USB_TXCSRL14_TXRDY 0x00000001 // Transmit Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH14 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH14_AUTOSET 0x00000080 // Auto Set.
+#define USB_TXCSRH14_ISO 0x00000040 // ISO.
+#define USB_TXCSRH14_MODE 0x00000020 // Mode.
+#define USB_TXCSRH14_DMAEN 0x00000010 // DMA Request Enable.
+#define USB_TXCSRH14_FDT 0x00000008 // Force Data Toggle.
+#define USB_TXCSRH14_DMAMOD 0x00000004 // DMA Request Mode.
+#define USB_TXCSRH14_DTWE 0x00000002 // Data Toggle Write Enable.
+#define USB_TXCSRH14_DT 0x00000001 // Data Toggle.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP14 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP14_MAXLOAD_M 0x000007FF // Maximum Payload.
+#define USB_RXMAXP14_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL14 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL14_CLRDT 0x00000080 // Clear Data Toggle.
+#define USB_RXCSRL14_STALLED 0x00000040 // Endpoint Stalled.
+#define USB_RXCSRL14_REQPKT 0x00000020 // Request Packet.
+#define USB_RXCSRL14_STALL 0x00000020 // Send Stall.
+#define USB_RXCSRL14_FLUSH 0x00000010 // Flush FIFO.
+#define USB_RXCSRL14_DATAERR 0x00000008 // Data Error.
+#define USB_RXCSRL14_NAKTO 0x00000008 // NAK Timeout.
+#define USB_RXCSRL14_OVER 0x00000004 // Overrun.
+#define USB_RXCSRL14_ERROR 0x00000004 // Error.
+#define USB_RXCSRL14_FULL 0x00000002 // FIFO Full.
+#define USB_RXCSRL14_RXRDY 0x00000001 // Receive Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH14 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH14_AUTOCL 0x00000080 // Auto Clear.
+#define USB_RXCSRH14_AUTORQ 0x00000040 // Auto Request.
+#define USB_RXCSRH14_ISO 0x00000040 // ISO.
+#define USB_RXCSRH14_DMAEN 0x00000020 // DMA Request Enable.
+#define USB_RXCSRH14_PIDERR 0x00000010 // PID Error.
+#define USB_RXCSRH14_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH14_DMAMOD 0x00000008 // DMA Request Mode.
+#define USB_RXCSRH14_DTWE 0x00000004 // Data Toggle Write Enable.
+#define USB_RXCSRH14_DT 0x00000002 // Data Toggle.
+#define USB_RXCSRH14_INCRX 0x00000001 // Incomplete Receive.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT14
+// register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT14_COUNT_M 0x00001FFF // Receive Packet Count.
+#define USB_RXCOUNT14_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE14 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE14_SPEED_M 0x000000C0 // Operating Speed.
+#define USB_TXTYPE14_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE14_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE14_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE14_PROTO_M 0x00000030 // Protocol.
+#define USB_TXTYPE14_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE14_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE14_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE14_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE14_TEP_M 0x0000000F // Target Endpoint Number.
+#define USB_TXTYPE14_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL14
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL14_NAKLMT_M \
+ 0x000000FF // NAK Limit.
+#define USB_TXINTERVAL14_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL14_TXPOLL_S \
+ 0
+#define USB_TXINTERVAL14_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE14 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE14_SPEED_M 0x000000C0 // Operating Speed.
+#define USB_RXTYPE14_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE14_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE14_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE14_PROTO_M 0x00000030 // Protocol.
+#define USB_RXTYPE14_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE14_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE14_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE14_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE14_TEP_M 0x0000000F // Target Endpoint Number.
+#define USB_RXTYPE14_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL14
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL14_NAKLMT_M \
+ 0x000000FF // NAK Limit.
+#define USB_RXINTERVAL14_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL14_NAKLMT_S \
+ 0
+#define USB_RXINTERVAL14_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP15 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP15_MAXLOAD_M 0x000007FF // Maximum Payload.
+#define USB_TXMAXP15_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL15 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL15_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL15_INCTX 0x00000080 // Incomplete Transmit.
+#define USB_TXCSRL15_CLRDT 0x00000040 // Clear Data Toggle.
+#define USB_TXCSRL15_STALLED 0x00000020 // Endpoint Stalled.
+#define USB_TXCSRL15_SETUP 0x00000010 // Setup Packet.
+#define USB_TXCSRL15_STALL 0x00000010 // Send Stall.
+#define USB_TXCSRL15_FLUSH 0x00000008 // Flush FIFO.
+#define USB_TXCSRL15_UNDRN 0x00000004 // Underrun.
+#define USB_TXCSRL15_ERROR 0x00000004 // Error.
+#define USB_TXCSRL15_FIFONE 0x00000002 // FIFO Not Empty.
+#define USB_TXCSRL15_TXRDY 0x00000001 // Transmit Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH15 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH15_AUTOSET 0x00000080 // Auto Set.
+#define USB_TXCSRH15_ISO 0x00000040 // ISO.
+#define USB_TXCSRH15_MODE 0x00000020 // Mode.
+#define USB_TXCSRH15_DMAEN 0x00000010 // DMA Request Enable.
+#define USB_TXCSRH15_FDT 0x00000008 // Force Data Toggle.
+#define USB_TXCSRH15_DMAMOD 0x00000004 // DMA Request Mode.
+#define USB_TXCSRH15_DTWE 0x00000002 // Data Toggle Write Enable.
+#define USB_TXCSRH15_DT 0x00000001 // Data Toggle.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP15 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP15_MAXLOAD_M 0x000007FF // Maximum Payload.
+#define USB_RXMAXP15_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL15 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL15_CLRDT 0x00000080 // Clear Data Toggle.
+#define USB_RXCSRL15_STALLED 0x00000040 // Endpoint Stalled.
+#define USB_RXCSRL15_STALL 0x00000020 // Send Stall.
+#define USB_RXCSRL15_REQPKT 0x00000020 // Request Packet.
+#define USB_RXCSRL15_FLUSH 0x00000010 // Flush FIFO.
+#define USB_RXCSRL15_DATAERR 0x00000008 // Data Error.
+#define USB_RXCSRL15_NAKTO 0x00000008 // NAK Timeout.
+#define USB_RXCSRL15_ERROR 0x00000004 // Error.
+#define USB_RXCSRL15_OVER 0x00000004 // Overrun.
+#define USB_RXCSRL15_FULL 0x00000002 // FIFO Full.
+#define USB_RXCSRL15_RXRDY 0x00000001 // Receive Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH15 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH15_AUTOCL 0x00000080 // Auto Clear.
+#define USB_RXCSRH15_AUTORQ 0x00000040 // Auto Request.
+#define USB_RXCSRH15_ISO 0x00000040 // ISO.
+#define USB_RXCSRH15_DMAEN 0x00000020 // DMA Request Enable.
+#define USB_RXCSRH15_PIDERR 0x00000010 // PID Error.
+#define USB_RXCSRH15_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH15_DMAMOD 0x00000008 // DMA Request Mode.
+#define USB_RXCSRH15_DTWE 0x00000004 // Data Toggle Write Enable.
+#define USB_RXCSRH15_DT 0x00000002 // Data Toggle.
+#define USB_RXCSRH15_INCRX 0x00000001 // Incomplete Receive.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT15
+// register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT15_COUNT_M 0x00001FFF // Receive Packet Count.
+#define USB_RXCOUNT15_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE15 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE15_SPEED_M 0x000000C0 // Operating Speed.
+#define USB_TXTYPE15_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE15_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE15_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE15_PROTO_M 0x00000030 // Protocol.
+#define USB_TXTYPE15_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE15_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE15_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE15_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE15_TEP_M 0x0000000F // Target Endpoint Number.
+#define USB_TXTYPE15_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL15
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL15_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL15_NAKLMT_M \
+ 0x000000FF // NAK Limit.
+#define USB_TXINTERVAL15_NAKLMT_S \
+ 0
+#define USB_TXINTERVAL15_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE15 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE15_SPEED_M 0x000000C0 // Operating Speed.
+#define USB_RXTYPE15_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE15_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE15_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE15_PROTO_M 0x00000030 // Protocol.
+#define USB_RXTYPE15_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE15_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE15_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE15_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE15_TEP_M 0x0000000F // Target Endpoint Number.
+#define USB_RXTYPE15_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL15
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL15_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL15_NAKLMT_M \
+ 0x000000FF // NAK Limit.
+#define USB_RXINTERVAL15_TXPOLL_S \
+ 0
+#define USB_RXINTERVAL15_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT1
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT1_M 0x0000FFFF // Block Transfer Packet Count.
+#define USB_RQPKTCOUNT1_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT2
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT2_M 0x0000FFFF // Block Transfer Packet Count.
+#define USB_RQPKTCOUNT2_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT3
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT3_M 0x0000FFFF // Block Transfer Packet Count.
+#define USB_RQPKTCOUNT3_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT4
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT4_COUNT_M 0x0000FFFF // Block Transfer Packet Count.
+#define USB_RQPKTCOUNT4_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT5
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT5_COUNT_M 0x0000FFFF // Block Transfer Packet Count.
+#define USB_RQPKTCOUNT5_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT6
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT6_COUNT_M 0x0000FFFF // Block Transfer Packet Count.
+#define USB_RQPKTCOUNT6_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT7
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT7_COUNT_M 0x0000FFFF // Block Transfer Packet Count.
+#define USB_RQPKTCOUNT7_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT8
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT8_COUNT_M 0x0000FFFF // Block Transfer Packet Count.
+#define USB_RQPKTCOUNT8_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT9
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT9_COUNT_M 0x0000FFFF // Block Transfer Packet Count.
+#define USB_RQPKTCOUNT9_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT10
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT10_COUNT_M \
+ 0x0000FFFF // Block Transfer Packet Count.
+#define USB_RQPKTCOUNT10_COUNT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT11
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT11_COUNT_M \
+ 0x0000FFFF // Block Transfer Packet Count.
+#define USB_RQPKTCOUNT11_COUNT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT12
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT12_COUNT_M \
+ 0x0000FFFF // Block Transfer Packet Count.
+#define USB_RQPKTCOUNT12_COUNT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT13
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT13_COUNT_M \
+ 0x0000FFFF // Block Transfer Packet Count.
+#define USB_RQPKTCOUNT13_COUNT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT14
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT14_COUNT_M \
+ 0x0000FFFF // Block Transfer Packet Count.
+#define USB_RQPKTCOUNT14_COUNT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT15
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT15_COUNT_M \
+ 0x0000FFFF // Block Transfer Packet Count.
+#define USB_RQPKTCOUNT15_COUNT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXDPKTBUFDIS
+// register.
+//
+//*****************************************************************************
+#define USB_RXDPKTBUFDIS_EP15 0x00008000 // EP15 RX Double-Packet Buffer
+ // Disable.
+#define USB_RXDPKTBUFDIS_EP14 0x00004000 // EP14 RX Double-Packet Buffer
+ // Disable.
+#define USB_RXDPKTBUFDIS_EP13 0x00002000 // EP13 RX Double-Packet Buffer
+ // Disable.
+#define USB_RXDPKTBUFDIS_EP12 0x00001000 // EP12 RX Double-Packet Buffer
+ // Disable.
+#define USB_RXDPKTBUFDIS_EP11 0x00000800 // EP11 RX Double-Packet Buffer
+ // Disable.
+#define USB_RXDPKTBUFDIS_EP10 0x00000400 // EP10 RX Double-Packet Buffer
+ // Disable.
+#define USB_RXDPKTBUFDIS_EP9 0x00000200 // EP9 RX Double-Packet Buffer
+ // Disable.
+#define USB_RXDPKTBUFDIS_EP8 0x00000100 // EP8 RX Double-Packet Buffer
+ // Disable.
+#define USB_RXDPKTBUFDIS_EP7 0x00000080 // EP7 RX Double-Packet Buffer
+ // Disable.
+#define USB_RXDPKTBUFDIS_EP6 0x00000040 // EP6 RX Double-Packet Buffer
+ // Disable.
+#define USB_RXDPKTBUFDIS_EP5 0x00000020 // EP5 RX Double-Packet Buffer
+ // Disable.
+#define USB_RXDPKTBUFDIS_EP4 0x00000010 // EP4 RX Double-Packet Buffer
+ // Disable.
+#define USB_RXDPKTBUFDIS_EP3 0x00000008 // EP3 RX Double-Packet Buffer
+ // Disable.
+#define USB_RXDPKTBUFDIS_EP2 0x00000004 // EP2 RX Double-Packet Buffer
+ // Disable.
+#define USB_RXDPKTBUFDIS_EP1 0x00000002 // EP1 RX Double-Packet Buffer
+ // Disable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXDPKTBUFDIS
+// register.
+//
+//*****************************************************************************
+#define USB_TXDPKTBUFDIS_EP15 0x00008000 // EP15 TX Double-Packet Buffer
+ // Disable.
+#define USB_TXDPKTBUFDIS_EP14 0x00004000 // EP14 TX Double-Packet Buffer
+ // Disable.
+#define USB_TXDPKTBUFDIS_EP13 0x00002000 // EP13 TX Double-Packet Buffer
+ // Disable.
+#define USB_TXDPKTBUFDIS_EP12 0x00001000 // EP12 TX Double-Packet Buffer
+ // Disable.
+#define USB_TXDPKTBUFDIS_EP11 0x00000800 // EP11 TX Double-Packet Buffer
+ // Disable.
+#define USB_TXDPKTBUFDIS_EP10 0x00000400 // EP10 TX Double-Packet Buffer
+ // Disable.
+#define USB_TXDPKTBUFDIS_EP9 0x00000200 // EP9 TX Double-Packet Buffer
+ // Disable.
+#define USB_TXDPKTBUFDIS_EP8 0x00000100 // EP8 TX Double-Packet Buffer
+ // Disable.
+#define USB_TXDPKTBUFDIS_EP7 0x00000080 // EP7 TX Double-Packet Buffer
+ // Disable.
+#define USB_TXDPKTBUFDIS_EP6 0x00000040 // EP6 TX Double-Packet Buffer
+ // Disable.
+#define USB_TXDPKTBUFDIS_EP5 0x00000020 // EP5 TX Double-Packet Buffer
+ // Disable.
+#define USB_TXDPKTBUFDIS_EP4 0x00000010 // EP4 TX Double-Packet Buffer
+ // Disable.
+#define USB_TXDPKTBUFDIS_EP3 0x00000008 // EP3 TX Double-Packet Buffer
+ // Disable.
+#define USB_TXDPKTBUFDIS_EP2 0x00000004 // EP2 TX Double-Packet Buffer
+ // Disable.
+#define USB_TXDPKTBUFDIS_EP1 0x00000002 // EP1 TX Double-Packet Buffer
+ // Disable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPC register.
+//
+//*****************************************************************************
+#define USB_EPC_PFLTACT_M 0x00000300 // Power Fault Action.
+#define USB_EPC_PFLTACT_UNCHG 0x00000000 // Unchanged
+#define USB_EPC_PFLTACT_TRIS 0x00000100 // Tristate
+#define USB_EPC_PFLTACT_LOW 0x00000200 // Low
+#define USB_EPC_PFLTACT_HIGH 0x00000300 // High
+#define USB_EPC_PFLTAEN 0x00000040 // Power Fault Action Enable.
+#define USB_EPC_PFLTSEN_HIGH 0x00000020 // Power Fault Sense.
+#define USB_EPC_PFLTEN 0x00000010 // Power Fault Input Enable.
+#define USB_EPC_EPENDE 0x00000004 // EPEN Drive Enable.
+#define USB_EPC_EPEN_M 0x00000003 // External Power Supply Enable
+ // Configuration.
+#define USB_EPC_EPEN_LOW 0x00000000 // Power Enable Active Low
+#define USB_EPC_EPEN_HIGH 0x00000001 // Power Enable Active High
+#define USB_EPC_EPEN_VBLOW 0x00000002 // Power Enable High if VBUS Low
+#define USB_EPC_EPEN_VBHIGH 0x00000003 // Power Enable High if VBUS High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPCRIS register.
+//
+//*****************************************************************************
+#define USB_EPCRIS_PF 0x00000001 // USB Power Fault Interrupt
+ // Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPCIM register.
+//
+//*****************************************************************************
+#define USB_EPCIM_PF 0x00000001 // USB Power Fault Interrupt Mask.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPCISC register.
+//
+//*****************************************************************************
+#define USB_EPCISC_PF 0x00000001 // USB Power Fault Interrupt Status
+ // and Clear.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DRRIS register.
+//
+//*****************************************************************************
+#define USB_DRRIS_RESUME 0x00000001 // Resume Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DRIM register.
+//
+//*****************************************************************************
+#define USB_DRIM_RESUME 0x00000001 // Resume Interrupt Mask.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DRISC register.
+//
+//*****************************************************************************
+#define USB_DRISC_RESUME 0x00000001 // Resume Interrupt Status and
+ // Clear.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VDC register.
+//
+//*****************************************************************************
+#define USB_VDC_VBDEN 0x00000001 // VBUS Droop Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VDCRIS register.
+//
+//*****************************************************************************
+#define USB_VDCRIS_VD 0x00000001 // VBUS Droop Raw Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VDCIM register.
+//
+//*****************************************************************************
+#define USB_VDCIM_VD 0x00000001 // VBUS Droop Interrupt Mask.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VDCISC register.
+//
+//*****************************************************************************
+#define USB_VDCISC_VD 0x00000001 // VBUS Droop Interrupt Status and
+ // Clear.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IDVRIS register.
+//
+//*****************************************************************************
+#define USB_IDVRIS_ID 0x00000001 // ID Valid Detect Raw Interrupt
+ // Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IDVIM register.
+//
+//*****************************************************************************
+#define USB_IDVIM_ID 0x00000001 // ID Valid Detect Interrupt Mask.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IDVISC register.
+//
+//*****************************************************************************
+#define USB_IDVISC_ID 0x00000001 // ID Valid Detect Interrupt Status
+ // and Clear.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPS register.
+//
+//*****************************************************************************
+#define USB_EPS_DMAC_M 0x00000F00 // DMA C Select.
+#define USB_EPS_DMAB_M 0x000000F0 // DMA B Select.
+#define USB_EPS_DMAA_M 0x0000000F // DMA A Select.
+#define USB_EPS_DMAB_S 4
+#define USB_EPS_DMAA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_TXFIFO register.
+//
+//*****************************************************************************
+#define I2S_TXFIFO_M 0xFFFFFFFF // TX Data.
+#define I2S_TXFIFO_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_TXFIFOCFG
+// register.
+//
+//*****************************************************************************
+#define I2S_TXFIFOCFG_CSS 0x00000002 // Compact Stereo Sample Size.
+#define I2S_TXFIFOCFG_LRS 0x00000001 // Left-Right Sample Indicator.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_TXCFG register.
+//
+//*****************************************************************************
+#define I2S_TXCFG_JST 0x20000000 // Justification of Output Data.
+#define I2S_TXCFG_DLY 0x10000000 // Data Delay.
+#define I2S_TXCFG_SCP 0x08000000 // SCLK Polarity.
+#define I2S_TXCFG_LRP 0x04000000 // Left/Right Clock Polarity.
+#define I2S_TXCFG_WM_M 0x03000000 // Write Mode.
+#define I2S_TXCFG_WM_DUAL 0x00000000 // Stereo mode
+#define I2S_TXCFG_WM_COMPACT 0x01000000 // Compact Stereo mode
+#define I2S_TXCFG_WM_MONO 0x02000000 // Mono mode
+#define I2S_TXCFG_FMT 0x00800000 // FIFO Empty.
+#define I2S_TXCFG_MSL 0x00400000 // SCLK Master/Slave.
+#define I2S_TXCFG_SSZ_M 0x0000FC00 // Sample Size.
+#define I2S_TXCFG_SDSZ_M 0x000003F0 // System Data Size.
+#define I2S_TXCFG_SSZ_S 10
+#define I2S_TXCFG_SDSZ_S 4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_TXLIMIT register.
+//
+//*****************************************************************************
+#define I2S_TXLIMIT_LIMIT_M 0x0000001F // FIFO Limit.
+#define I2S_TXLIMIT_LIMIT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_TXISM register.
+//
+//*****************************************************************************
+#define I2S_TXISM_FFI 0x00010000 // Transmit FIFO Service Request
+ // Interrupt.
+#define I2S_TXISM_FFM 0x00000001 // FIFO Interrupt Mask.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_TXLEV register.
+//
+//*****************************************************************************
+#define I2S_TXLEV_LEVEL_M 0x0000001F // Number of Audio Samples.
+#define I2S_TXLEV_LEVEL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_RXFIFO register.
+//
+//*****************************************************************************
+#define I2S_RXFIFO_M 0xFFFFFFFF // RX Data.
+#define I2S_RXFIFO_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_RXFIFOCFG
+// register.
+//
+//*****************************************************************************
+#define I2S_RXFIFOCFG_FMM 0x00000004 // FIFO Mono Mode.
+#define I2S_RXFIFOCFG_CSS 0x00000002 // Compact Stereo Sample Size.
+#define I2S_RXFIFOCFG_LRS 0x00000001 // Left-Right Sample Indicator.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_RXCFG register.
+//
+//*****************************************************************************
+#define I2S_RXCFG_JST 0x20000000 // Justification of Input Data.
+#define I2S_RXCFG_DLY 0x10000000 // Data Delay.
+#define I2S_RXCFG_SCP 0x08000000 // SCLK Polarity.
+#define I2S_RXCFG_LRP 0x04000000 // Left/Right Clock Polarity.
+#define I2S_RXCFG_RM 0x01000000 // Read Mode.
+#define I2S_RXCFG_MSL 0x00400000 // SCLK Master/Slave.
+#define I2S_RXCFG_SSZ_M 0x0000FC00 // Sample Size.
+#define I2S_RXCFG_SDSZ_M 0x000003F0 // System Data Size.
+#define I2S_RXCFG_SSZ_S 10
+#define I2S_RXCFG_SDSZ_S 4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_RXLIMIT register.
+//
+//*****************************************************************************
+#define I2S_RXLIMIT_LIMIT_M 0x0000001F // FIFO Limit.
+#define I2S_RXLIMIT_LIMIT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_RXISM register.
+//
+//*****************************************************************************
+#define I2S_RXISM_FFI 0x00010000 // Receive FIFO Service Request
+ // Interrupt.
+#define I2S_RXISM_FFM 0x00000001 // FIFO Interrupt Mask.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_RXLEV register.
+//
+//*****************************************************************************
+#define I2S_RXLEV_LEVEL_M 0x0000001F // Number of Audio Samples.
+#define I2S_RXLEV_LEVEL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_CFG register.
+//
+//*****************************************************************************
+#define I2S_CFG_RXSLV 0x00000020 // When set, this bit configures
+ // the receiver to use the
+ // externally driven I2S0RXMCLK
+ // signal.
+#define I2S_CFG_TXSLV 0x00000010 // When set, this bit configures
+ // the transmitter to use the
+ // externally driven I2S0TXMCLK
+ // signal.
+#define I2S_CFG_RXEN 0x00000002 // Serial Receive Engine Enable.
+#define I2S_CFG_TXEN 0x00000001 // Serial Transmit Engine Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_IM register.
+//
+//*****************************************************************************
+#define I2S_IM_RXRE 0x00000020 // Receive FIFO Read Error.
+#define I2S_IM_RXFSR 0x00000010 // Receive FIFO Service Request.
+#define I2S_IM_TXWE 0x00000002 // Transmit FIFO Write Error.
+#define I2S_IM_TXFSR 0x00000001 // Transmit FIFO Service Request.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_RIS register.
+//
+//*****************************************************************************
+#define I2S_RIS_RXRE 0x00000020 // Receive FIFO Read Error.
+#define I2S_RIS_RXFSR 0x00000010 // Receive FIFO Service Request.
+#define I2S_RIS_TXWE 0x00000002 // Transmit FIFO Write Error.
+#define I2S_RIS_TXFSR 0x00000001 // Transmit FIFO Service Request.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_MIS register.
+//
+//*****************************************************************************
+#define I2S_MIS_RXRE 0x00000020 // Receive FIFO Read Error.
+#define I2S_MIS_RXFSR 0x00000010 // Receive FIFO Service Request.
+#define I2S_MIS_TXWE 0x00000002 // Transmit FIFO Write Error.
+#define I2S_MIS_TXFSR 0x00000001 // Transmit FIFO Service Request.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_IC register.
+//
+//*****************************************************************************
+#define I2S_IC_RXRE 0x00000020 // Receive FIFO Read Error.
+#define I2S_IC_TXWE 0x00000002 // Transmit FIFO Write Error.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_CFG register.
+//
+//*****************************************************************************
+#define EPI_CFG_BLKEN 0x00000010 // Block Enable.
+#define EPI_CFG_MODE_M 0x0000000F // Mode Select.
+#define EPI_CFG_MODE_NONE 0x00000000 // General Purpose
+#define EPI_CFG_MODE_SDRAM 0x00000001 // Supports SDR SDRAM. Control,
+ // address, and data pins are
+ // configured using the EPISDRAMCFG
+ // and EPISDRAMCFG2 registers.
+#define EPI_CFG_MODE_HB8 0x00000002 // 8-Bit Host-Bus (HB8)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_BAUD register.
+//
+//*****************************************************************************
+#define EPI_BAUD_COUNT_M 0x0000FFFF // Baud Rate Counter.
+#define EPI_BAUD_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_SDRAMCFG register.
+//
+//*****************************************************************************
+#define EPI_SDRAMCFG_FREQ_M 0xC0000000 // Frequency Range.
+#define EPI_SDRAMCFG_FREQ_NONE 0x00000000 // 0
+#define EPI_SDRAMCFG_FREQ_15MHZ 0x40000000 // 15
+#define EPI_SDRAMCFG_FREQ_30MHZ 0x80000000 // 30
+#define EPI_SDRAMCFG_FREQ_50MHZ 0xC0000000 // 50
+#define EPI_SDRAMCFG_RFSH_M 0x07FF0000 // Refresh Counter.
+#define EPI_SDRAMCFG_SLEEP 0x00000200 // Sleep Mode.
+#define EPI_SDRAMCFG_SIZE_M 0x00000003 // Size of SDRAM.
+#define EPI_SDRAMCFG_SIZE_8MB 0x00000000 // 64Mb (8MB)
+#define EPI_SDRAMCFG_SIZE_16MB 0x00000001 // 128Mb (16MB)
+#define EPI_SDRAMCFG_SIZE_32MB 0x00000002 // 256Mb (32MB)
+#define EPI_SDRAMCFG_SIZE_64MB 0x00000003 // 512Mb (64MB)
+#define EPI_SDRAMCFG_RFSH_S 16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_GPCFG register.
+//
+//*****************************************************************************
+#define EPI_GPCFG_CLKPIN 0x80000000 // Clock Pin.
+#define EPI_GPCFG_CLKGATE 0x40000000 // Clock Gated.
+#define EPI_GPCFG_RDYEN 0x10000000 // Ready Enable.
+#define EPI_GPCFG_FRMPIN 0x08000000 // Framing Pin.
+#define EPI_GPCFG_FRM50 0x04000000 // 50/50 Frame.
+#define EPI_GPCFG_FRMCNT_M 0x03C00000 // Frame Count.
+#define EPI_GPCFG_RW 0x00200000 // Read and Write.
+#define EPI_GPCFG_WR2CYC 0x00080000 // 2-Cycle Writes.
+#define EPI_GPCFG_RD2CYC 0x00040000 // 2-Cycle Reads.
+#define EPI_GPCFG_MAXWAIT_M 0x0000FF00 // Maximum Wait.
+#define EPI_GPCFG_ASIZE_M 0x00000030 // Address Bus Size.
+#define EPI_GPCFG_ASIZE_NONE 0x00000000 // No address
+#define EPI_GPCFG_ASIZE_4BIT 0x00000010 // 4 Bits Wide (EPI24 to EPI27)
+#define EPI_GPCFG_ASIZE_12BIT 0x00000020 // 12 Bits Wide (EPI16 to EPI27).
+ // This size cannot be used with
+ // 24-bit data.
+#define EPI_GPCFG_ASIZE_20BIT 0x00000030 // 20 Bits Wide
+#define EPI_GPCFG_DSIZE_M 0x00000003 // Size of Data Bus.
+#define EPI_GPCFG_DSIZE_4BIT 0x00000000 // 8 Bits Wide (EPI0 to EPI7)
+#define EPI_GPCFG_DSIZE_16BIT 0x00000001 // 16 Bits Wide (EPI0 to EPI15)
+#define EPI_GPCFG_DSIZE_24BIT 0x00000002 // 24 Bits Wide (EPI0 to EPI23)
+#define EPI_GPCFG_DSIZE_32BIT 0x00000003 // 32 Bits Wide (EPI0 to
+ // EPI31).This size may not be used
+ // with a clock. This value is
+ // normally used for acquisition
+ // input and actuator control as
+ // well as other general-purpose
+ // uses that require 32 bits per
+ // direction.
+#define EPI_GPCFG_FRMCNT_S 22
+#define EPI_GPCFG_MAXWAIT_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB8CFG register.
+//
+//*****************************************************************************
+#define EPI_HB8CFG_XFFEN 0x00800000 // External FIFO FULL Enable.
+#define EPI_HB8CFG_XFEEN 0x00400000 // External FIFO EMPTY Enable.
+#define EPI_HB8CFG_WRHIGH 0x00200000 // WRITE Strobe Polarity.
+#define EPI_HB8CFG_RDHIGH 0x00100000 // READ Strobe Polarity.
+#define EPI_HB8CFG_MAXWAIT_M 0x0000FF00 // Maximum Wait.
+#define EPI_HB8CFG_WRWS_M 0x000000C0 // Write Wait States.
+#define EPI_HB8CFG_WRWS_0 0x00000000 // No wait states
+#define EPI_HB8CFG_WRWS_1 0x00000040 // 1 wait state
+#define EPI_HB8CFG_WRWS_2 0x00000080 // 2 wait states
+#define EPI_HB8CFG_WRWS_3 0x000000C0 // 3 wait states
+#define EPI_HB8CFG_RDWS_M 0x00000030 // Read Wait States.
+#define EPI_HB8CFG_RDWS_0 0x00000000 // No wait states
+#define EPI_HB8CFG_RDWS_1 0x00000010 // 1 wait state
+#define EPI_HB8CFG_RDWS_2 0x00000020 // 2 wait states
+#define EPI_HB8CFG_RDWS_3 0x00000030 // 3 wait states
+#define EPI_HB8CFG_MODE_M 0x00000003 // Host Bus Sub-Mode.
+#define EPI_HB8CFG_MODE_MUX 0x00000000 // ADMUX - AD[7:0]
+#define EPI_HB8CFG_MODE_NMUX 0x00000001 // ADNONMUX - D[7:0]
+#define EPI_HB8CFG_MODE_SRAM 0x00000002 // SRAM
+#define EPI_HB8CFG_MODE_FIFO 0x00000003 // XFIFO - D[7:0]
+#define EPI_HB8CFG_MAXWAIT_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_SDRAMCFG2
+// register.
+//
+//*****************************************************************************
+#define EPI_SDRAMCFG2_RCM 0x80000000 // Read Capture Mode.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB8CFG2 register.
+//
+//*****************************************************************************
+#define EPI_HB8CFG2_WORD 0x80000000 // Word Access Mode.
+#define EPI_HB8CFG2_CSCFG 0x01000000 // Chip Select Configuration.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_GPCFG2 register.
+//
+//*****************************************************************************
+#define EPI_GPCFG2_WORD 0x80000000 // Word Access Mode.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_ADDRMAP register.
+//
+//*****************************************************************************
+#define EPI_ADDRMAP_EPSZ_M 0x000000C0 // External Peripheral Size.
+#define EPI_ADDRMAP_EPSZ_256B 0x00000000 // 0x100 (256)
+#define EPI_ADDRMAP_EPSZ_64KB 0x00000040 // 0x1.0000 (64 KB)
+#define EPI_ADDRMAP_EPSZ_16MB 0x00000080 // 0x100.0000 (16 MB)
+#define EPI_ADDRMAP_EPSZ_512MB 0x000000C0 // 0x2000.0000 (512 MB)
+#define EPI_ADDRMAP_EPADR_M 0x00000030 // External Peripheral Address.
+#define EPI_ADDRMAP_EPADR_NONE 0x00000000 // Not mapped
+#define EPI_ADDRMAP_EPADR_A000 0x00000010 // At 0xA000.0000
+#define EPI_ADDRMAP_EPADR_C000 0x00000020 // At 0xC000.0000
+#define EPI_ADDRMAP_ERSZ_M 0x0000000C // External RAM Size.
+#define EPI_ADDRMAP_ERSZ_256B 0x00000000 // 0x100 (256)
+#define EPI_ADDRMAP_ERSZ_64KB 0x00000004 // 0x1.0000 (64KB)
+#define EPI_ADDRMAP_ERSZ_16MB 0x00000008 // 0x100.0000 (16MB)
+#define EPI_ADDRMAP_ERSZ_512MB 0x0000000C // 0x2000.0000 (512MB)
+#define EPI_ADDRMAP_ERADR_M 0x00000003 // External RAM Address.
+#define EPI_ADDRMAP_ERADR_NONE 0x00000000 // Not mapped
+#define EPI_ADDRMAP_ERADR_6000 0x00000001 // At 0x6000.0000
+#define EPI_ADDRMAP_ERADR_8000 0x00000002 // At 0x8000.0000
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RSIZE0 register.
+//
+//*****************************************************************************
+#define EPI_RSIZE0_SIZE_M 0x00000003 // Current Size.
+#define EPI_RSIZE0_SIZE_8BIT 0x00000001 // Byte (8 bits)
+#define EPI_RSIZE0_SIZE_16BIT 0x00000002 // Half-word (16 bits)
+#define EPI_RSIZE0_SIZE_32BIT 0x00000003 // Word (32 bits)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RADDR0 register.
+//
+//*****************************************************************************
+#define EPI_RADDR0_ADDR_M 0x1FFFFFFF // Current Address.
+#define EPI_RADDR0_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RPSTD0 register.
+//
+//*****************************************************************************
+#define EPI_RPSTD0_POSTCNT_M 0x00001FFF // Post Count.
+#define EPI_RPSTD0_POSTCNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RSIZE1 register.
+//
+//*****************************************************************************
+#define EPI_RSIZE1_SIZE_M 0x00000003 // Current Size.
+#define EPI_RSIZE1_SIZE_8BIT 0x00000001 // Byte (8 bits)
+#define EPI_RSIZE1_SIZE_16BIT 0x00000002 // Half-word (16 bits)
+#define EPI_RSIZE1_SIZE_32BIT 0x00000003 // Word (32 bits)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RADDR1 register.
+//
+//*****************************************************************************
+#define EPI_RADDR1_ADDR_M 0x1FFFFFFF // Current Address.
+#define EPI_RADDR1_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RPSTD1 register.
+//
+//*****************************************************************************
+#define EPI_RPSTD1_POSTCNT_M 0x00001FFF // Post Count.
+#define EPI_RPSTD1_POSTCNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_STAT register.
+//
+//*****************************************************************************
+#define EPI_STAT_CELOW 0x00000200 // Clock Enable Low.
+#define EPI_STAT_XFFULL 0x00000100 // External FIFO Full.
+#define EPI_STAT_XFEMPTY 0x00000080 // External FIFO Empty.
+#define EPI_STAT_INITSEQ 0x00000040 // Initialization Sequence.
+#define EPI_STAT_WBUSY 0x00000020 // Write Busy.
+#define EPI_STAT_NBRBUSY 0x00000010 // Non-Blocking Read Busy.
+#define EPI_STAT_ACTIVE 0x00000001 // Register Active.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RFIFOCNT register.
+//
+//*****************************************************************************
+#define EPI_RFIFOCNT_COUNT_M 0x00000007 // FIFO Count.
+#define EPI_RFIFOCNT_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO register.
+//
+//*****************************************************************************
+#define EPI_READFIFO_DATA_M 0xFFFFFFFF // Reads Data.
+#define EPI_READFIFO_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO1
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO1_DATA_M 0xFFFFFFFF // Reads Data.
+#define EPI_READFIFO1_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO2
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO2_DATA_M 0xFFFFFFFF // Reads Data.
+#define EPI_READFIFO2_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO3
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO3_DATA_M 0xFFFFFFFF // Reads Data.
+#define EPI_READFIFO3_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO4
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO4_DATA_M 0xFFFFFFFF // Reads Data.
+#define EPI_READFIFO4_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO5
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO5_DATA_M 0xFFFFFFFF // Reads Data.
+#define EPI_READFIFO5_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO6
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO6_DATA_M 0xFFFFFFFF // Reads Data.
+#define EPI_READFIFO6_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO7
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO7_DATA_M 0xFFFFFFFF // Reads Data.
+#define EPI_READFIFO7_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_FIFOLVL register.
+//
+//*****************************************************************************
+#define EPI_FIFOLVL_WFERR 0x00020000 // Write Full Error.
+#define EPI_FIFOLVL_RSERR 0x00010000 // Read Stall Error.
+#define EPI_FIFOLVL_WRFIFO_M 0x00000070 // Write FIFO.
+#define EPI_FIFOLVL_WRFIFO_EMPT 0x00000000 // Trigger when there are 1 to 4
+ // spaces available in the WFIFO.
+#define EPI_FIFOLVL_WRFIFO_1_4 0x00000020 // Trigger when there are 1 to 3
+ // spaces available in the WFIFO.
+#define EPI_FIFOLVL_WRFIFO_1_2 0x00000030 // Trigger when there are 1 to 2
+ // spaces available in the WFIFO.
+#define EPI_FIFOLVL_WRFIFO_3_4 0x00000040 // Trigger when there is 1 space
+ // available in the WFIFO.
+#define EPI_FIFOLVL_RDFIFO_M 0x00000007 // Read FIFO.
+#define EPI_FIFOLVL_RDFIFO_1_8 0x00000001 // Trigger when there are 1 or more
+ // entries in the NBRFIFO.
+#define EPI_FIFOLVL_RDFIFO_1_4 0x00000002 // Trigger when there are 2 or more
+ // entries in the NBRFIFO.
+#define EPI_FIFOLVL_RDFIFO_1_2 0x00000003 // Trigger when there are 4 or more
+ // entries in the NBRFIFO.
+#define EPI_FIFOLVL_RDFIFO_3_4 0x00000004 // Trigger when there are 6 or more
+ // entries in the NBRFIFO.
+#define EPI_FIFOLVL_RDFIFO_7_8 0x00000005 // Trigger when there are 7 or more
+ // entries in the NBRFIFO.
+#define EPI_FIFOLVL_RDFIFO_FULL 0x00000006 // Trigger when there are 8 entries
+ // in the NBRFIFO.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_WFIFOCNT register.
+//
+//*****************************************************************************
+#define EPI_WFIFOCNT_WTAV_M 0x00000007 // Available Write Transactions.
+#define EPI_WFIFOCNT_WTAV_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_IM register.
+//
+//*****************************************************************************
+#define EPI_IM_WRIM 0x00000004 // Write Interrupt Mask.
+#define EPI_IM_RDIM 0x00000002 // Read Interrupt Mask.
+#define EPI_IM_ERRIM 0x00000001 // Error Interrupt Mask.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RIS register.
+//
+//*****************************************************************************
+#define EPI_RIS_WRRIS 0x00000004 // Write Raw Interrupt Status.
+#define EPI_RIS_RDRIS 0x00000002 // Read Raw Interrupt Status.
+#define EPI_RIS_ERRRIS 0x00000001 // Error Raw Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_MIS register.
+//
+//*****************************************************************************
+#define EPI_MIS_WRMIS 0x00000004 // Write Masked Interrupt Status.
+#define EPI_MIS_RDMIS 0x00000002 // Read Masked Interrupt Status.
+#define EPI_MIS_ERRMIS 0x00000001 // Error Masked Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_EISC register.
+//
+//*****************************************************************************
+#define EPI_EISC_WTFULL 0x00000004 // Write FIFO Full Error.
+#define EPI_EISC_RSTALL 0x00000002 // Read Stalled Error.
+#define EPI_EISC_TOUT 0x00000001 // Timeout Error.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMA register.
+//
+//*****************************************************************************
+#define FLASH_FMA_OFFSET_M 0x0003FFFF // Address Offset.
+#define FLASH_FMA_OFFSET_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMD register.
+//
+//*****************************************************************************
+#define FLASH_FMD_DATA_M 0xFFFFFFFF // Data Value.
+#define FLASH_FMD_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMC register.
+//
+//*****************************************************************************
+#define FLASH_FMC_WRKEY_M 0xFFFF0000 // Flash Memory Write Key.
+#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key
+#define FLASH_FMC_COMT 0x00000008 // Commit Register Value.
+#define FLASH_FMC_MERASE 0x00000004 // Mass Erase Flash Memory.
+#define FLASH_FMC_ERASE 0x00000002 // Erase a Page of Flash Memory.
+#define FLASH_FMC_WRITE 0x00000001 // Write a Word into Flash Memory.
+#define FLASH_FMC_WRKEY_S 16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FCRIS register.
+//
+//*****************************************************************************
+#define FLASH_FCRIS_PRIS 0x00000002 // Programming Raw Interrupt
+ // Status.
+#define FLASH_FCRIS_ARIS 0x00000001 // Access Raw Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FCIM register.
+//
+//*****************************************************************************
+#define FLASH_FCIM_PMASK 0x00000002 // Programming Interrupt Mask.
+#define FLASH_FCIM_AMASK 0x00000001 // Access Interrupt Mask.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FCMISC register.
+//
+//*****************************************************************************
+#define FLASH_FCMISC_PMISC 0x00000002 // Programming Masked Interrupt
+ // Status and Clear.
+#define FLASH_FCMISC_AMISC 0x00000001 // Access Masked Interrupt Status
+ // and Clear.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMC2 register.
+//
+//*****************************************************************************
+#define FLASH_FMC2_WRKEY_M 0xFFFF0000 // Flash Memory Write Key.
+#define FLASH_FMC2_WRBUF 0x00000001 // Buffered Flash Memory Write.
+#define FLASH_FMC2_WRKEY_S 16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FWBVAL register.
+//
+//*****************************************************************************
+#define FLASH_FWBVAL_FWB_M 0xFFFFFFFF // Flash Memory Write Buffer.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FWBN register.
+//
+//*****************************************************************************
+#define FLASH_FWBN_DATA_M 0xFFFFFFFF // Data.
+#define FLASH_FWBN_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_RMCTL register.
+//
+//*****************************************************************************
+#define FLASH_RMCTL_BA 0x00000001 // Boot Alias.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_RMVER register.
+//
+//*****************************************************************************
+#define FLASH_RMVER_CONT_M 0xFF000000 // ROM Contents.
+#define FLASH_RMVER_CONT_LM_AES 0x02000000 // Stellaris Boot Loader &
+ // DriverLib with AES
+#define FLASH_RMVER_SIZE_M 0x00FF0000 // ROM Size.
+#define FLASH_RMVER_SIZE_23_75K 0x00020000 // Stellaris Boot Loader &
+ // DriverLib with AES,ethernet
+#define FLASH_RMVER_VER_M 0x0000FF00 // ROM Version.
+#define FLASH_RMVER_REV_M 0x000000FF // ROM Revision.
+#define FLASH_RMVER_VER_S 8
+#define FLASH_RMVER_REV_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERDBG register.
+//
+//*****************************************************************************
+#define FLASH_USERDBG_NW 0x80000000 // User Debug Not Written.
+#define FLASH_USERDBG_DATA_M 0x7FFFFFFC // User Data.
+#define FLASH_USERDBG_DBG1 0x00000002 // Debug Control 1.
+#define FLASH_USERDBG_DBG0 0x00000001 // Debug Control 0.
+#define FLASH_USERDBG_DATA_S 2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG0 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG0_NW 0x80000000 // Not Written.
+#define FLASH_USERREG0_DATA_M 0x7FFFFFFF // User Data.
+#define FLASH_USERREG0_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG1 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG1_NW 0x80000000 // Not Written.
+#define FLASH_USERREG1_DATA_M 0x7FFFFFFF // User Data.
+#define FLASH_USERREG1_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG2 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG2_NW 0x80000000 // Not Written.
+#define FLASH_USERREG2_DATA_M 0x7FFFFFFF // User Data.
+#define FLASH_USERREG2_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG3 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG3_NW 0x80000000 // Not Written.
+#define FLASH_USERREG3_DATA_M 0x7FFFFFFF // User Data.
+#define FLASH_USERREG3_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the erase size of the FLASH block that is
+// erased by an erase operation, and the protect size is the size of the FLASH
+// block that is protected by each protection register.
+//
+//*****************************************************************************
+#define FLASH_PROTECT_SIZE 0x00000800
+#define FLASH_ERASE_SIZE 0x00000400
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DID0 register.
+//
+//*****************************************************************************
+#define SYSCTL_DID0_VER_M 0x70000000 // DID0 Version.
+#define SYSCTL_DID0_VER_1 0x10000000 // Second version of the DID0
+ // register format.
+#define SYSCTL_DID0_CLASS_M 0x00FF0000 // Device Class.
+#define SYSCTL_DID0_CLASS_TEMPEST \
+ 0x00040000 // Stellaris(r) Tempest-class
+ // microcontrollers
+#define SYSCTL_DID0_MAJ_M 0x0000FF00 // Major Revision.
+#define SYSCTL_DID0_MAJ_REVA 0x00000000 // Revision A (initial device)
+#define SYSCTL_DID0_MAJ_REVB 0x00000100 // Revision B (first base layer
+ // revision)
+#define SYSCTL_DID0_MAJ_REVC 0x00000200 // Revision C (second base layer
+ // revision)
+#define SYSCTL_DID0_MIN_M 0x000000FF // Minor Revision.
+#define SYSCTL_DID0_MIN_0 0x00000000 // Initial device, or a major
+ // revision update.
+#define SYSCTL_DID0_MIN_1 0x00000001 // First metal layer change.
+#define SYSCTL_DID0_MIN_2 0x00000002 // Second metal layer change.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DID1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DID1_VER_M 0xF0000000 // DID1 Version.
+#define SYSCTL_DID1_VER_1 0x10000000 // Second version of the DID1
+ // register format.
+#define SYSCTL_DID1_FAM_M 0x0F000000 // Family.
+#define SYSCTL_DID1_FAM_STELLARIS \
+ 0x00000000 // Stellaris family of
+ // microcontollers, that is, all
+ // devices with external part
+ // numbers starting
+ // with LM3S.
+#define SYSCTL_DID1_PRTNO_M 0x00FF0000 // Part Number.
+#define SYSCTL_DID1_PRTNO_9B92 0x006A0000 // LM3S9B92
+#define SYSCTL_DID1_PINCNT_M 0x0000E000 // Package Pin Count.
+#define SYSCTL_DID1_PINCNT_100 0x00004000 // 100-pin package
+#define SYSCTL_DID1_TEMP_M 0x000000E0 // Temperature Range.
+#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temperature range (0C
+ // to 70C)
+#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temperature range
+ // (-40C to 85C)
+#define SYSCTL_DID1_TEMP_E 0x00000040 // Extended temperature range (-40C
+ // to 105C)
+#define SYSCTL_DID1_PKG_M 0x00000018 // Package Type.
+#define SYSCTL_DID1_PKG_28SOIC 0x00000000 // SOIC package
+#define SYSCTL_DID1_PKG_48QFP 0x00000008 // LQFP package
+#define SYSCTL_DID1_PKG_BGA 0x00000010 // BGA package
+#define SYSCTL_DID1_ROHS 0x00000004 // RoHS-Compliance.
+#define SYSCTL_DID1_QUAL_M 0x00000003 // Qualification Status.
+#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering Sample (unqualified)
+#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot Production (unqualified)
+#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully Qualified
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC0_SRAMSZ_M 0xFFFF0000 // SRAM Size.
+#define SYSCTL_DC0_SRAMSZ_96KB 0x017F0000 // 96 KB of SRAM
+#define SYSCTL_DC0_FLASHSZ_M 0x0000FFFF // Flash Size.
+#define SYSCTL_DC0_FLASHSZ_256K 0x0000007F // 256 KB of Flash
+#define SYSCTL_DC0_SRAMSZ_S 16 // SRAM size shift
+#define SYSCTL_DC0_FLASHSZ_S 0 // Flash size shift
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC1_WDT1 0x10000000 // Watchdog Timer1 Present.
+#define SYSCTL_DC1_CAN1 0x02000000 // CAN Module 1 Present.
+#define SYSCTL_DC1_CAN0 0x01000000 // CAN Module 0 Present.
+#define SYSCTL_DC1_PWM 0x00100000 // PWM Module Present.
+#define SYSCTL_DC1_ADC1 0x00020000 // ADC Module 1 Present.
+#define SYSCTL_DC1_ADC0 0x00010000 // ADC Module 0 Present.
+#define SYSCTL_DC1_MINSYSDIV_M 0x0000F000 // System Clock Divider.
+#define SYSCTL_DC1_MINSYSDIV_100 \
+ 0x00001000 // Divide VCO (400MHZ) by 5 minimum
+#define SYSCTL_DC1_MINSYSDIV_66 0x00002000 // Divide VCO (400MHZ) by 2*2 + 2 =
+ // 6 minimum
+#define SYSCTL_DC1_MINSYSDIV_50 0x00003000 // Specifies a 50-MHz CPU clock
+ // with a PLL divider of 4.
+#define SYSCTL_DC1_MINSYSDIV_25 0x00007000 // Specifies a 25-MHz clock with a
+ // PLL divider of 8.
+#define SYSCTL_DC1_MINSYSDIV_20 0x00009000 // Specifies a 20-MHz clock with a
+ // PLL divider of 10.
+#define SYSCTL_DC1_ADC1SPD_M 0x00000C00 // Max ADC1 Speed.
+#define SYSCTL_DC1_ADC1SPD_1M 0x00000C00 // 1M samples/second
+#define SYSCTL_DC1_ADC0SPD_M 0x00000300 // Max ADC0 Speed.
+#define SYSCTL_DC1_ADC0SPD_1M 0x00000300 // 1M samples/second
+#define SYSCTL_DC1_MPU 0x00000080 // MPU Present.
+#define SYSCTL_DC1_TEMP 0x00000020 // Temp Sensor Present.
+#define SYSCTL_DC1_PLL 0x00000010 // PLL Present.
+#define SYSCTL_DC1_WDT0 0x00000008 // Watchdog Timer 0 Present.
+#define SYSCTL_DC1_SWO 0x00000004 // SWO Trace Port Present.
+#define SYSCTL_DC1_SWD 0x00000002 // SWD Present.
+#define SYSCTL_DC1_JTAG 0x00000001 // JTAG Present.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC2_EPI0 0x40000000 // EPI Module 0 Present.
+#define SYSCTL_DC2_I2S0 0x10000000 // I2S Module 0 Present.
+#define SYSCTL_DC2_COMP2 0x04000000 // Analog Comparator 2 Present.
+#define SYSCTL_DC2_COMP1 0x02000000 // Analog Comparator 1 Present.
+#define SYSCTL_DC2_COMP0 0x01000000 // Analog Comparator 0 Present.
+#define SYSCTL_DC2_TIMER3 0x00080000 // Timer Module 3 Present.
+#define SYSCTL_DC2_TIMER2 0x00040000 // Timer Module 2 Present.
+#define SYSCTL_DC2_TIMER1 0x00020000 // Timer Module 1 Present.
+#define SYSCTL_DC2_TIMER0 0x00010000 // Timer Module 0 Present.
+#define SYSCTL_DC2_I2C1 0x00004000 // I2C Module 1 Present.
+#define SYSCTL_DC2_I2C0 0x00001000 // I2C Module 0 Present.
+#define SYSCTL_DC2_QEI1 0x00000200 // QEI Module 1 Present.
+#define SYSCTL_DC2_QEI0 0x00000100 // QEI Module 0 Present.
+#define SYSCTL_DC2_SSI1 0x00000020 // SSI Module 1 Present.
+#define SYSCTL_DC2_SSI0 0x00000010 // SSI Module 0 Present.
+#define SYSCTL_DC2_UART2 0x00000004 // UART Module 2 Present.
+#define SYSCTL_DC2_UART1 0x00000002 // UART Module 1 Present.
+#define SYSCTL_DC2_UART0 0x00000001 // UART Module 0 Present.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC3 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC3_32KHZ 0x80000000 // 32KHz Input Clock Available.
+#define SYSCTL_DC3_CCP5 0x20000000 // CCP5 Pin Present.
+#define SYSCTL_DC3_CCP4 0x10000000 // CCP4 Pin Present.
+#define SYSCTL_DC3_CCP3 0x08000000 // CCP3 Pin Present.
+#define SYSCTL_DC3_CCP2 0x04000000 // CCP2 Pin Present.
+#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 Pin Present.
+#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 Pin Present.
+#define SYSCTL_DC3_ADC0AIN7 0x00800000 // ADC Module 0 AIN7 Pin Present.
+#define SYSCTL_DC3_ADC0AIN6 0x00400000 // ADC Module 0 AIN6 Pin Present.
+#define SYSCTL_DC3_ADC0AIN5 0x00200000 // ADC Module 0 AIN5 Pin Present.
+#define SYSCTL_DC3_ADC0AIN4 0x00100000 // ADC Module 0 AIN4 Pin Present.
+#define SYSCTL_DC3_ADC0AIN3 0x00080000 // ADC Module 0 AIN3 Pin Present.
+#define SYSCTL_DC3_ADC0AIN2 0x00040000 // ADC Module 0 AIN2 Pin Present.
+#define SYSCTL_DC3_ADC0AIN1 0x00020000 // ADC Module 0 AIN1 Pin Present.
+#define SYSCTL_DC3_ADC0AIN0 0x00010000 // ADC Module 0 AIN0 Pin Present.
+#define SYSCTL_DC3_PWMFAULT 0x00008000 // PWM Fault Pin Present.
+#define SYSCTL_DC3_C2PLUS 0x00002000 // C2+ Pin Present.
+#define SYSCTL_DC3_C2MINUS 0x00001000 // C2- Pin Present.
+#define SYSCTL_DC3_C1PLUS 0x00000400 // C1+ Pin Present.
+#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- Pin Present.
+#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ Pin Present.
+#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- Pin Present.
+#define SYSCTL_DC3_PWM5 0x00000020 // PWM5 Pin Present.
+#define SYSCTL_DC3_PWM4 0x00000010 // PWM4 Pin Present.
+#define SYSCTL_DC3_PWM3 0x00000008 // PWM3 Pin Present.
+#define SYSCTL_DC3_PWM2 0x00000004 // PWM2 Pin Present.
+#define SYSCTL_DC3_PWM1 0x00000002 // PWM1 Pin Present.
+#define SYSCTL_DC3_PWM0 0x00000001 // PWM0 Pin Present.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC4 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC4_EPHY0 0x40000000 // Ethernet PHY Layer 0 Present.
+#define SYSCTL_DC4_EMAC0 0x10000000 // Ethernet MAC Layer 0 Present.
+#define SYSCTL_DC4_CCP7 0x00008000 // CCP7 Pin Present.
+#define SYSCTL_DC4_CCP6 0x00004000 // CCP6 Pin Present.
+#define SYSCTL_DC4_UDMA 0x00002000 // Micro-DMA Module Present.
+#define SYSCTL_DC4_ROM 0x00001000 // Internal Code ROM Present.
+#define SYSCTL_DC4_GPIOJ 0x00000100 // GPIO Port J Present.
+#define SYSCTL_DC4_GPIOH 0x00000080 // GPIO Port H Present.
+#define SYSCTL_DC4_GPIOG 0x00000040 // GPIO Port G Present.
+#define SYSCTL_DC4_GPIOF 0x00000020 // GPIO Port F Present.
+#define SYSCTL_DC4_GPIOE 0x00000010 // GPIO Port E Present.
+#define SYSCTL_DC4_GPIOD 0x00000008 // GPIO Port D Present.
+#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO Port C Present.
+#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO Port B Present.
+#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO Port A Present.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC5 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC5_PWMFAULT3 0x08000000 // PWM Fault 3 Pin Present.
+#define SYSCTL_DC5_PWMFAULT2 0x04000000 // PWM Fault 2 Pin Present.
+#define SYSCTL_DC5_PWMFAULT1 0x02000000 // PWM Fault 1 Pin Present.
+#define SYSCTL_DC5_PWMFAULT0 0x01000000 // PWM Fault 0 Pin Present.
+#define SYSCTL_DC5_PWMEFLT 0x00200000 // PWM Extended Fault Active.
+#define SYSCTL_DC5_PWMESYNC 0x00100000 // PWM Extended SYNC Active.
+#define SYSCTL_DC5_PWM7 0x00000080 // PWM7 Pin Present.
+#define SYSCTL_DC5_PWM6 0x00000040 // PWM6 Pin Present.
+#define SYSCTL_DC5_PWM5 0x00000020 // PWM5 Pin Present.
+#define SYSCTL_DC5_PWM4 0x00000010 // PWM4 Pin Present.
+#define SYSCTL_DC5_PWM3 0x00000008 // PWM3 Pin Present.
+#define SYSCTL_DC5_PWM2 0x00000004 // PWM2 Pin Present.
+#define SYSCTL_DC5_PWM1 0x00000002 // PWM1 Pin Present.
+#define SYSCTL_DC5_PWM0 0x00000001 // PWM0 Pin Present.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC6 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC6_USB0PHY 0x00000010 // USB Module 0 PHY Present.
+#define SYSCTL_DC6_USB0_M 0x00000003 // USB Module 0 Present.
+#define SYSCTL_DC6_USB0_OTG 0x00000003 // USB0 is OTG.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC7 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC7_DMACH30 0x40000000 // SW.
+#define SYSCTL_DC7_DMACH29 0x20000000 // I2S0_TX / CAN1_TX.
+#define SYSCTL_DC7_DMACH28 0x10000000 // I2S0_RX / CAN1_RX.
+#define SYSCTL_DC7_DMACH27 0x08000000 // CAN1_TX / ADC1_SS3.
+#define SYSCTL_DC7_DMACH26 0x04000000 // CAN1_RX / ADC1_SS2.
+#define SYSCTL_DC7_DMACH25 0x02000000 // SSI1_TX / ADC1_SS1.
+#define SYSCTL_DC7_DMACH24 0x01000000 // SSI1_RX / ADC1_SS0.
+#define SYSCTL_DC7_DMACH23 0x00800000 // UART1_TX / CAN2_TX.
+#define SYSCTL_DC7_DMACH22 0x00400000 // UART1_RX / CAN2_RX.
+#define SYSCTL_DC7_DMACH21 0x00200000 // Timer1B / EPI0_TX.
+#define SYSCTL_DC7_DMACH20 0x00100000 // Timer1A / EPI0_RX.
+#define SYSCTL_DC7_DMACH19 0x00080000 // Timer0B / Timer1B.
+#define SYSCTL_DC7_DMACH18 0x00040000 // Timer0A / Timer1A.
+#define SYSCTL_DC7_DMACH17 0x00020000 // ADC0_SS3.
+#define SYSCTL_DC7_DMACH16 0x00010000 // ADC0_SS2.
+#define SYSCTL_DC7_DMACH15 0x00008000 // ADC0_SS1 / Timer2B.
+#define SYSCTL_DC7_DMACH14 0x00004000 // ADC0_SS0 / Timer2A.
+#define SYSCTL_DC7_DMACH13 0x00002000 // CAN0_TX / UART2_TX.
+#define SYSCTL_DC7_DMACH12 0x00001000 // CAN0_RX / UART2_RX.
+#define SYSCTL_DC7_DMACH11 0x00000800 // SSI0_TX / UART1_TX.
+#define SYSCTL_DC7_DMACH10 0x00000400 // SSI0_RX / UART1_RX.
+#define SYSCTL_DC7_DMACH9 0x00000200 // UART0_TX / SSI1_TX.
+#define SYSCTL_DC7_DMACH8 0x00000100 // UART0_RX / SSI1_RX.
+#define SYSCTL_DC7_DMACH7 0x00000080 // ETH_TX / Timer2B.
+#define SYSCTL_DC7_DMACH6 0x00000040 // ETH_RX / Timer2A.
+#define SYSCTL_DC7_DMACH5 0x00000020 // USB_EP3_TX / Timer2B.
+#define SYSCTL_DC7_DMACH4 0x00000010 // USB_EP3_RX / Timer2A.
+#define SYSCTL_DC7_DMACH3 0x00000008 // USB_EP2_TX / Timer3B.
+#define SYSCTL_DC7_DMACH2 0x00000004 // USB_EP2_RX / Timer3A.
+#define SYSCTL_DC7_DMACH1 0x00000002 // USB_EP1_TX / UART2_TX.
+#define SYSCTL_DC7_DMACH0 0x00000001 // USB_EP1_RX / UART2_RX.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC8 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC8_ADC1AIN15 0x80000000 // ADC Module 1 AIN15 Pin Present.
+#define SYSCTL_DC8_ADC1AIN14 0x40000000 // ADC Module 1 AIN14 Pin Present.
+#define SYSCTL_DC8_ADC1AIN13 0x20000000 // ADC Module 1 AIN13 Pin Present.
+#define SYSCTL_DC8_ADC1AIN12 0x10000000 // ADC Module 1 AIN12 Pin Present.
+#define SYSCTL_DC8_ADC1AIN11 0x08000000 // ADC Module 1 AIN11 Pin Present.
+#define SYSCTL_DC8_ADC1AIN10 0x04000000 // ADC Module 1 AIN10 Pin Present.
+#define SYSCTL_DC8_ADC1AIN9 0x02000000 // ADC Module 1 AIN9 Pin Present.
+#define SYSCTL_DC8_ADC1AIN8 0x01000000 // ADC Module 1 AIN8 Pin Present.
+#define SYSCTL_DC8_ADC1AIN7 0x00800000 // ADC Module 1 AIN7 Pin Present.
+#define SYSCTL_DC8_ADC1AIN6 0x00400000 // ADC Module 1 AIN6 Pin Present.
+#define SYSCTL_DC8_ADC1AIN5 0x00200000 // ADC Module 1 AIN5 Pin Present.
+#define SYSCTL_DC8_ADC1AIN4 0x00100000 // ADC Module 1 AIN4 Pin Present.
+#define SYSCTL_DC8_ADC1AIN3 0x00080000 // ADC Module 1 AIN3 Pin Present.
+#define SYSCTL_DC8_ADC1AIN2 0x00040000 // ADC Module 1 AIN2 Pin Present.
+#define SYSCTL_DC8_ADC1AIN1 0x00020000 // ADC Module 1 AIN1 Pin Present.
+#define SYSCTL_DC8_ADC1AIN0 0x00010000 // ADC Module 1 AIN0 Pin Present.
+#define SYSCTL_DC8_ADC0AIN15 0x00008000 // ADC Module 0 AIN15 Pin Present.
+#define SYSCTL_DC8_ADC0AIN14 0x00004000 // ADC Module 0 AIN14 Pin Present.
+#define SYSCTL_DC8_ADC0AIN13 0x00002000 // ADC Module 0 AIN13 Pin Present.
+#define SYSCTL_DC8_ADC0AIN12 0x00001000 // ADC Module 0 AIN12 Pin Present.
+#define SYSCTL_DC8_ADC0AIN11 0x00000800 // ADC Module 0 AIN11 Pin Present.
+#define SYSCTL_DC8_ADC0AIN10 0x00000400 // ADC Module 0 AIN10 Pin Present.
+#define SYSCTL_DC8_ADC0AIN9 0x00000200 // ADC Module 0 AIN9 Pin Present.
+#define SYSCTL_DC8_ADC0AIN8 0x00000100 // ADC Module 0 AIN8 Pin Present.
+#define SYSCTL_DC8_ADC0AIN7 0x00000080 // ADC Module 0 AIN7 Pin Present.
+#define SYSCTL_DC8_ADC0AIN6 0x00000040 // ADC Module 0 AIN6 Pin Present.
+#define SYSCTL_DC8_ADC0AIN5 0x00000020 // ADC Module 0 AIN5 Pin Present.
+#define SYSCTL_DC8_ADC0AIN4 0x00000010 // ADC Module 0 AIN4 Pin Present.
+#define SYSCTL_DC8_ADC0AIN3 0x00000008 // ADC Module 0 AIN3 Pin Present.
+#define SYSCTL_DC8_ADC0AIN2 0x00000004 // ADC Module 0 AIN2 Pin Present.
+#define SYSCTL_DC8_ADC0AIN1 0x00000002 // ADC Module 0 AIN1 Pin Present.
+#define SYSCTL_DC8_ADC0AIN0 0x00000001 // ADC Module 0 AIN0 Pin Present.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PBORCTL register.
+//
+//*****************************************************************************
+#define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR Interrupt or Reset.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCR0 register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCR0_WDT1 0x10000000 // WDT1 Reset Control.
+#define SYSCTL_SRCR0_CAN1 0x02000000 // CAN1 Reset Control.
+#define SYSCTL_SRCR0_CAN0 0x01000000 // CAN0 Reset Control.
+#define SYSCTL_SRCR0_PWM 0x00100000 // PWM Reset Control.
+#define SYSCTL_SRCR0_ADC1 0x00020000 // ADC1 Reset Control.
+#define SYSCTL_SRCR0_ADC0 0x00010000 // ADC0 Reset Control.
+#define SYSCTL_SRCR0_WDT0 0x00000008 // WDT0 Reset Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCR1 register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCR1_EPI0 0x40000000 // EPI0 Reset Control.
+#define SYSCTL_SRCR1_I2S0 0x10000000 // I2S0 Reset Control.
+#define SYSCTL_SRCR1_COMP2 0x04000000 // Analog Comp 2 Reset Control.
+#define SYSCTL_SRCR1_COMP1 0x02000000 // Analog Comp 1 Reset Control.
+#define SYSCTL_SRCR1_COMP0 0x01000000 // Analog Comp 0 Reset Control.
+#define SYSCTL_SRCR1_TIMER3 0x00080000 // Timer 3 Reset Control.
+#define SYSCTL_SRCR1_TIMER2 0x00040000 // Timer 2 Reset Control.
+#define SYSCTL_SRCR1_TIMER1 0x00020000 // Timer 1 Reset Control.
+#define SYSCTL_SRCR1_TIMER0 0x00010000 // Timer 0 Reset Control.
+#define SYSCTL_SRCR1_I2C1 0x00004000 // I2C1 Reset Control.
+#define SYSCTL_SRCR1_I2C0 0x00001000 // I2C0 Reset Control.
+#define SYSCTL_SRCR1_QEI1 0x00000200 // QEI1 Reset Control.
+#define SYSCTL_SRCR1_QEI0 0x00000100 // QEI0 Reset Control.
+#define SYSCTL_SRCR1_SSI1 0x00000020 // SSI1 Reset Control.
+#define SYSCTL_SRCR1_SSI0 0x00000010 // SSI0 Reset Control.
+#define SYSCTL_SRCR1_UART2 0x00000004 // UART2 Reset Control.
+#define SYSCTL_SRCR1_UART1 0x00000002 // UART1 Reset Control.
+#define SYSCTL_SRCR1_UART0 0x00000001 // UART0 Reset Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCR2 register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCR2_EPHY0 0x40000000 // PHY0 Reset Control.
+#define SYSCTL_SRCR2_EMAC0 0x10000000 // MAC0 Reset Control.
+#define SYSCTL_SRCR2_USB0 0x00010000 // USB0 Reset Control.
+#define SYSCTL_SRCR2_UDMA 0x00002000 // Micro-DMA Reset Control.
+#define SYSCTL_SRCR2_GPIOJ 0x00000100 // Port J Reset Control.
+#define SYSCTL_SRCR2_GPIOH 0x00000080 // Port H Reset Control.
+#define SYSCTL_SRCR2_GPIOG 0x00000040 // Port G Reset Control.
+#define SYSCTL_SRCR2_GPIOF 0x00000020 // Port F Reset Control.
+#define SYSCTL_SRCR2_GPIOE 0x00000010 // Port E Reset Control.
+#define SYSCTL_SRCR2_GPIOD 0x00000008 // Port D Reset Control.
+#define SYSCTL_SRCR2_GPIOC 0x00000004 // Port C Reset Control.
+#define SYSCTL_SRCR2_GPIOB 0x00000002 // Port B Reset Control.
+#define SYSCTL_SRCR2_GPIOA 0x00000001 // Port A Reset Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RIS register.
+//
+//*****************************************************************************
+#define SYSCTL_RIS_MOSCPUPRIS 0x00000100 // MOSC Power Up Raw Interrupt
+ // Status.
+#define SYSCTL_RIS_USBPLLLRIS 0x00000080 // USB PLL Lock Raw Interrupt
+ // Status.
+#define SYSCTL_RIS_PLLLRIS 0x00000040 // PLL Lock Raw Interrupt Status.
+#define SYSCTL_RIS_BORRIS 0x00000002 // Brown-Out Reset Raw Interrupt
+ // Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_IMC register.
+//
+//*****************************************************************************
+#define SYSCTL_IMC_MOSCPUPIM 0x00000100 // MOSC Power Up Interrupt Mask.
+#define SYSCTL_IMC_USBPLLLIM 0x00000080 // USB PLL Lock Interrupt Mask.
+#define SYSCTL_IMC_PLLLIM 0x00000040 // PLL Lock Interrupt Mask.
+#define SYSCTL_IMC_BORIM 0x00000002 // Brown-Out Reset Interrupt Mask.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_MISC register.
+//
+//*****************************************************************************
+#define SYSCTL_MISC_MOSCPUPMIS 0x00000100 // MOSC Power Up Masked Interrupt
+ // Status.
+#define SYSCTL_MISC_USBPLLLMIS 0x00000080 // USB PLL Lock Masked Interrupt
+ // Status.
+#define SYSCTL_MISC_PLLLMIS 0x00000040 // PLL Lock Masked Interrupt
+ // Status.
+#define SYSCTL_MISC_BORMIS 0x00000002 // BOR Masked Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RESC register.
+//
+//*****************************************************************************
+#define SYSCTL_RESC_MOSCFAIL 0x00010000 // MOSC Failure Reset.
+#define SYSCTL_RESC_WDT1 0x00000020 // Watchdog Timer 1 Reset.
+#define SYSCTL_RESC_SW 0x00000010 // Software Reset.
+#define SYSCTL_RESC_WDT0 0x00000008 // Watchdog Timer 0 Reset.
+#define SYSCTL_RESC_BOR 0x00000004 // Brown-Out Reset.
+#define SYSCTL_RESC_POR 0x00000002 // Power-On Reset.
+#define SYSCTL_RESC_EXT 0x00000001 // External Reset.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCC register.
+//
+//*****************************************************************************
+#define SYSCTL_RCC_ACG 0x08000000 // Auto Clock Gating.
+#define SYSCTL_RCC_SYSDIV_M 0x07800000 // System Clock Divisor.
+#define SYSCTL_RCC_SYSDIV_2 0x00800000 // /2
+#define SYSCTL_RCC_SYSDIV_3 0x01000000 // /3
+#define SYSCTL_RCC_SYSDIV_4 0x01800000 // /4
+#define SYSCTL_RCC_SYSDIV_5 0x02000000 // /5
+#define SYSCTL_RCC_SYSDIV_6 0x02800000 // /6
+#define SYSCTL_RCC_SYSDIV_7 0x03000000 // /7
+#define SYSCTL_RCC_SYSDIV_8 0x03800000 // /8
+#define SYSCTL_RCC_SYSDIV_9 0x04000000 // /9
+#define SYSCTL_RCC_SYSDIV_10 0x04800000 // /10
+#define SYSCTL_RCC_SYSDIV_11 0x05000000 // /11
+#define SYSCTL_RCC_SYSDIV_12 0x05800000 // /12
+#define SYSCTL_RCC_SYSDIV_13 0x06000000 // /13
+#define SYSCTL_RCC_SYSDIV_14 0x06800000 // /14
+#define SYSCTL_RCC_SYSDIV_15 0x07000000 // /15
+#define SYSCTL_RCC_SYSDIV_16 0x07800000 // /16
+#define SYSCTL_RCC_USESYSDIV 0x00400000 // Enable System Clock Divider.
+#define SYSCTL_RCC_USEPWMDIV 0x00100000 // Enable PWM Clock Divisor.
+#define SYSCTL_RCC_PWMDIV_M 0x000E0000 // PWM Unit Clock Divisor.
+#define SYSCTL_RCC_PWMDIV_2 0x00000000 // /2
+#define SYSCTL_RCC_PWMDIV_4 0x00020000 // /4
+#define SYSCTL_RCC_PWMDIV_8 0x00040000 // /8
+#define SYSCTL_RCC_PWMDIV_16 0x00060000 // /16
+#define SYSCTL_RCC_PWMDIV_32 0x00080000 // /32
+#define SYSCTL_RCC_PWMDIV_64 0x000A0000 // /64
+#define SYSCTL_RCC_PWRDN 0x00002000 // PLL Power Down.
+#define SYSCTL_RCC_BYPASS 0x00000800 // PLL Bypass.
+#define SYSCTL_RCC_XTAL_M 0x000007C0 // Crystal Value.
+#define SYSCTL_RCC_XTAL_1MHZ 0x00000000 // 1.000
+#define SYSCTL_RCC_XTAL_1_84MHZ 0x00000040 // 1.8432
+#define SYSCTL_RCC_XTAL_2MHZ 0x00000080 // 2.000
+#define SYSCTL_RCC_XTAL_2_45MHZ 0x000000C0 // 2.4576
+#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100 // 3.579545 MHz
+#define SYSCTL_RCC_XTAL_3_68MHZ 0x00000140 // 3.6864 MHz
+#define SYSCTL_RCC_XTAL_4MHZ 0x00000180 // 4 MHz (USB)
+#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // 4.096 MHz
+#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // 4.9152 MHz
+#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // 5 MHz (USB)
+#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // 5.12 MHz
+#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // 6 MHz (reset value)(USB)
+#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // 6.144 MHz
+#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // 7.3728 MHz
+#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // 8 MHz (USB)
+#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // 8.192 MHz
+#define SYSCTL_RCC_XTAL_10MHZ 0x00000400 // 10.0 MHz (USB)
+#define SYSCTL_RCC_XTAL_12MHZ 0x00000440 // 12.0 MHz (USB)
+#define SYSCTL_RCC_XTAL_12_2MHZ 0x00000480 // 12.288 MHz
+#define SYSCTL_RCC_XTAL_13_5MHZ 0x000004C0 // 13.56 MHz
+#define SYSCTL_RCC_XTAL_14_3MHZ 0x00000500 // 14.31818 MHz
+#define SYSCTL_RCC_XTAL_16MHZ 0x00000540 // 16.0 MHz (USB)
+#define SYSCTL_RCC_XTAL_16_3MHZ 0x00000580 // 16.384 MHz
+#define SYSCTL_RCC_OSCSRC_M 0x00000030 // Oscillator Source.
+#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // MOSC
+#define SYSCTL_RCC_OSCSRC_INT 0x00000010 // PIOSC
+#define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // PIOSC/4
+#define SYSCTL_RCC_OSCSRC_30 0x00000030 // 30 kHz
+#define SYSCTL_RCC_IOSCDIS 0x00000002 // Precision Internal Oscillator
+ // Disable.
+#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main Oscillator Disable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PLLCFG register.
+//
+//*****************************************************************************
+#define SYSCTL_PLLCFG_F_M 0x00003FE0 // PLL F Value.
+#define SYSCTL_PLLCFG_R_M 0x0000001F // PLL R Value.
+#define SYSCTL_PLLCFG_F_S 5
+#define SYSCTL_PLLCFG_R_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_GPIOHBCTL
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_GPIOHBCTL_PORTJ 0x00000100 // Port J Advanced Host Bus.
+#define SYSCTL_GPIOHBCTL_PORTH 0x00000080 // Port H Advanced Host Bus.
+#define SYSCTL_GPIOHBCTL_PORTG 0x00000040 // Port G Advanced Host Bus.
+#define SYSCTL_GPIOHBCTL_PORTF 0x00000020 // Port F Advanced Host Bus.
+#define SYSCTL_GPIOHBCTL_PORTE 0x00000010 // Port E Advanced Host Bus.
+#define SYSCTL_GPIOHBCTL_PORTD 0x00000008 // Port D Advanced Host Bus.
+#define SYSCTL_GPIOHBCTL_PORTC 0x00000004 // Port C Advanced Host Bus.
+#define SYSCTL_GPIOHBCTL_PORTB 0x00000002 // Port B Advanced Host Bus.
+#define SYSCTL_GPIOHBCTL_PORTA 0x00000001 // Port A Advanced Host Bus.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCC2_USERCC2 0x80000000 // Use RCC2.
+#define SYSCTL_RCC2_USEFRACT 0x40000000 // Use FRACT.
+#define SYSCTL_RCC2_SYSDIV2_M 0x1F800000 // System Clock Divisor.
+#define SYSCTL_RCC2_SYSDIV2_2 0x00800000 // System clock /2
+#define SYSCTL_RCC2_SYSDIV2_3 0x01000000 // System clock /3
+#define SYSCTL_RCC2_SYSDIV2_4 0x01800000 // System clock /4
+#define SYSCTL_RCC2_SYSDIV2_5 0x02000000 // System clock /5
+#define SYSCTL_RCC2_SYSDIV2_6 0x02800000 // System clock /6
+#define SYSCTL_RCC2_SYSDIV2_7 0x03000000 // System clock /7
+#define SYSCTL_RCC2_SYSDIV2_8 0x03800000 // System clock /8
+#define SYSCTL_RCC2_SYSDIV2_9 0x04000000 // System clock /9
+#define SYSCTL_RCC2_SYSDIV2_10 0x04800000 // System clock /10
+#define SYSCTL_RCC2_SYSDIV2_11 0x05000000 // System clock /11
+#define SYSCTL_RCC2_SYSDIV2_12 0x05800000 // System clock /12
+#define SYSCTL_RCC2_SYSDIV2_13 0x06000000 // System clock /13
+#define SYSCTL_RCC2_SYSDIV2_14 0x06800000 // System clock /14
+#define SYSCTL_RCC2_SYSDIV2_15 0x07000000 // System clock /15
+#define SYSCTL_RCC2_SYSDIV2_16 0x07800000 // System clock /16
+#define SYSCTL_RCC2_SYSDIV2_17 0x08000000 // System clock /17
+#define SYSCTL_RCC2_SYSDIV2_18 0x08800000 // System clock /18
+#define SYSCTL_RCC2_SYSDIV2_19 0x09000000 // System clock /19
+#define SYSCTL_RCC2_SYSDIV2_20 0x09800000 // System clock /20
+#define SYSCTL_RCC2_SYSDIV2_21 0x0A000000 // System clock /21
+#define SYSCTL_RCC2_SYSDIV2_22 0x0A800000 // System clock /22
+#define SYSCTL_RCC2_SYSDIV2_23 0x0B000000 // System clock /23
+#define SYSCTL_RCC2_SYSDIV2_24 0x0B800000 // System clock /24
+#define SYSCTL_RCC2_SYSDIV2_25 0x0C000000 // System clock /25
+#define SYSCTL_RCC2_SYSDIV2_26 0x0C800000 // System clock /26
+#define SYSCTL_RCC2_SYSDIV2_27 0x0D000000 // System clock /27
+#define SYSCTL_RCC2_SYSDIV2_28 0x0D800000 // System clock /28
+#define SYSCTL_RCC2_SYSDIV2_29 0x0E000000 // System clock /29
+#define SYSCTL_RCC2_SYSDIV2_30 0x0E800000 // System clock /30
+#define SYSCTL_RCC2_SYSDIV2_31 0x0F000000 // System clock /31
+#define SYSCTL_RCC2_SYSDIV2_32 0x0F800000 // System clock /32
+#define SYSCTL_RCC2_SYSDIV2_33 0x10000000 // System clock /33
+#define SYSCTL_RCC2_SYSDIV2_34 0x10800000 // System clock /34
+#define SYSCTL_RCC2_SYSDIV2_35 0x11000000 // System clock /35
+#define SYSCTL_RCC2_SYSDIV2_36 0x11800000 // System clock /36
+#define SYSCTL_RCC2_SYSDIV2_37 0x12000000 // System clock /37
+#define SYSCTL_RCC2_SYSDIV2_38 0x12800000 // System clock /38
+#define SYSCTL_RCC2_SYSDIV2_39 0x13000000 // System clock /39
+#define SYSCTL_RCC2_SYSDIV2_40 0x13800000 // System clock /40
+#define SYSCTL_RCC2_SYSDIV2_41 0x14000000 // System clock /41
+#define SYSCTL_RCC2_SYSDIV2_42 0x14800000 // System clock /42
+#define SYSCTL_RCC2_SYSDIV2_43 0x15000000 // System clock /43
+#define SYSCTL_RCC2_SYSDIV2_44 0x15800000 // System clock /44
+#define SYSCTL_RCC2_SYSDIV2_45 0x16000000 // System clock /45
+#define SYSCTL_RCC2_SYSDIV2_46 0x16800000 // System clock /46
+#define SYSCTL_RCC2_SYSDIV2_47 0x17000000 // System clock /47
+#define SYSCTL_RCC2_SYSDIV2_48 0x17800000 // System clock /48
+#define SYSCTL_RCC2_SYSDIV2_49 0x18000000 // System clock /49
+#define SYSCTL_RCC2_SYSDIV2_50 0x18800000 // System clock /50
+#define SYSCTL_RCC2_SYSDIV2_51 0x19000000 // System clock /51
+#define SYSCTL_RCC2_SYSDIV2_52 0x19800000 // System clock /52
+#define SYSCTL_RCC2_SYSDIV2_53 0x1A000000 // System clock /53
+#define SYSCTL_RCC2_SYSDIV2_54 0x1A800000 // System clock /54
+#define SYSCTL_RCC2_SYSDIV2_55 0x1B000000 // System clock /55
+#define SYSCTL_RCC2_SYSDIV2_56 0x1B800000 // System clock /56
+#define SYSCTL_RCC2_SYSDIV2_57 0x1C000000 // System clock /57
+#define SYSCTL_RCC2_SYSDIV2_58 0x1C800000 // System clock /58
+#define SYSCTL_RCC2_SYSDIV2_59 0x1D000000 // System clock /59
+#define SYSCTL_RCC2_SYSDIV2_60 0x1D800000 // System clock /60
+#define SYSCTL_RCC2_SYSDIV2_61 0x1E000000 // System clock /61
+#define SYSCTL_RCC2_SYSDIV2_62 0x1E800000 // System clock /62
+#define SYSCTL_RCC2_SYSDIV2_63 0x1F000000 // System clock /63
+#define SYSCTL_RCC2_SYSDIV2_64 0x1F800000 // System clock /64
+#define SYSCTL_RCC2_FRACT 0x00400000 // Fractional Divider.
+#define SYSCTL_RCC2_USBPWRDN 0x00004000 // Power-Down USB PLL.
+#define SYSCTL_RCC2_PWRDN2 0x00002000 // Power-Down PLL.
+#define SYSCTL_RCC2_BYPASS2 0x00000800 // PLL Bypass.
+#define SYSCTL_RCC2_OSCSRC2_M 0x00000070 // Oscillator Source.
+#define SYSCTL_RCC2_OSCSRC2_MO 0x00000000 // MOSC
+#define SYSCTL_RCC2_OSCSRC2_IO 0x00000010 // PIOSC
+#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020 // PIOSC/4
+#define SYSCTL_RCC2_OSCSRC2_30 0x00000030 // 30 kHz
+#define SYSCTL_RCC2_SYSDIV2_S 23
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_MOSCCTL register.
+//
+//*****************************************************************************
+#define SYSCTL_MOSCCTL_CVAL 0x00000001 // Clock Validation for MOSC.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control.
+#define SYSCTL_RCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control.
+#define SYSCTL_RCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control.
+#define SYSCTL_RCGC0_PWM 0x00100000 // PWM Clock Gating Control.
+#define SYSCTL_RCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control.
+#define SYSCTL_RCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control.
+#define SYSCTL_RCGC0_ADC1SPD_M 0x00000C00 // ADC1 Sample Speed.
+#define SYSCTL_RCGC0_ADC1SPD_1M 0x00000C00 // 1M samples/second
+#define SYSCTL_RCGC0_ADC0SPD_M 0x00000300 // ADC0 Sample Speed.
+#define SYSCTL_RCGC0_ADC0SPD_1M 0x00000300 // 1M samples/second
+#define SYSCTL_RCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGC1_EPI0 0x40000000 // EPI0 Clock Gating.
+#define SYSCTL_RCGC1_I2S0 0x10000000 // I2S0 Clock Gating.
+#define SYSCTL_RCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock
+ // Gating.
+#define SYSCTL_RCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock
+ // Gating.
+#define SYSCTL_RCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock
+ // Gating.
+#define SYSCTL_RCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control.
+#define SYSCTL_RCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control.
+#define SYSCTL_RCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control.
+#define SYSCTL_RCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control.
+#define SYSCTL_RCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control.
+#define SYSCTL_RCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control.
+#define SYSCTL_RCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control.
+#define SYSCTL_RCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control.
+#define SYSCTL_RCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control.
+#define SYSCTL_RCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control.
+#define SYSCTL_RCGC1_UART2 0x00000004 // UART2 Clock Gating Control.
+#define SYSCTL_RCGC1_UART1 0x00000002 // UART1 Clock Gating Control.
+#define SYSCTL_RCGC1_UART0 0x00000001 // UART0 Clock Gating Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGC2_EPHY0 0x40000000 // PHY0 Clock Gating Control.
+#define SYSCTL_RCGC2_EMAC0 0x10000000 // MAC0 Clock Gating Control.
+#define SYSCTL_RCGC2_USB0 0x00010000 // USB0 Clock Gating Control.
+#define SYSCTL_RCGC2_UDMA 0x00002000 // Micro-DMA Clock Gating Control.
+#define SYSCTL_RCGC2_GPIOJ 0x00000100 // Port J Clock Gating Control.
+#define SYSCTL_RCGC2_GPIOH 0x00000080 // Port H Clock Gating Control.
+#define SYSCTL_RCGC2_GPIOG 0x00000040 // Port G Clock Gating Control.
+#define SYSCTL_RCGC2_GPIOF 0x00000020 // Port F Clock Gating Control.
+#define SYSCTL_RCGC2_GPIOE 0x00000010 // Port E Clock Gating Control.
+#define SYSCTL_RCGC2_GPIOD 0x00000008 // Port D Clock Gating Control.
+#define SYSCTL_RCGC2_GPIOC 0x00000004 // Port C Clock Gating Control.
+#define SYSCTL_RCGC2_GPIOB 0x00000002 // Port B Clock Gating Control.
+#define SYSCTL_RCGC2_GPIOA 0x00000001 // Port A Clock Gating Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control.
+#define SYSCTL_SCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control.
+#define SYSCTL_SCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control.
+#define SYSCTL_SCGC0_PWM 0x00100000 // PWM Clock Gating Control.
+#define SYSCTL_SCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control.
+#define SYSCTL_SCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control.
+#define SYSCTL_SCGC0_ADC1SPD_M 0x00000C00 // ADC1 Sample Speed.
+#define SYSCTL_SCGC0_ADC1SPD_1M 0x00000C00 // 1M samples/second
+#define SYSCTL_SCGC0_ADC0SPD_M 0x00000300 // ADC0 Sample Speed.
+#define SYSCTL_SCGC0_ADC0SPD_1M 0x00000300 // 1M samples/second
+#define SYSCTL_SCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGC1_EPI0 0x40000000 // EPI0 Clock Gating.
+#define SYSCTL_SCGC1_I2S0 0x10000000 // I2S0 Clock Gating.
+#define SYSCTL_SCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock
+ // Gating.
+#define SYSCTL_SCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock
+ // Gating.
+#define SYSCTL_SCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock
+ // Gating.
+#define SYSCTL_SCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control.
+#define SYSCTL_SCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control.
+#define SYSCTL_SCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control.
+#define SYSCTL_SCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control.
+#define SYSCTL_SCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control.
+#define SYSCTL_SCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control.
+#define SYSCTL_SCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control.
+#define SYSCTL_SCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control.
+#define SYSCTL_SCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control.
+#define SYSCTL_SCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control.
+#define SYSCTL_SCGC1_UART2 0x00000004 // UART2 Clock Gating Control.
+#define SYSCTL_SCGC1_UART1 0x00000002 // UART1 Clock Gating Control.
+#define SYSCTL_SCGC1_UART0 0x00000001 // UART0 Clock Gating Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGC2_EPHY0 0x40000000 // PHY0 Clock Gating Control.
+#define SYSCTL_SCGC2_EMAC0 0x10000000 // MAC0 Clock Gating Control.
+#define SYSCTL_SCGC2_USB0 0x00010000 // USB0 Clock Gating Control.
+#define SYSCTL_SCGC2_UDMA 0x00002000 // Micro-DMA Clock Gating Control.
+#define SYSCTL_SCGC2_GPIOJ 0x00000100 // Port J Clock Gating Control.
+#define SYSCTL_SCGC2_GPIOH 0x00000080 // Port H Clock Gating Control.
+#define SYSCTL_SCGC2_GPIOG 0x00000040 // Port G Clock Gating Control.
+#define SYSCTL_SCGC2_GPIOF 0x00000020 // Port F Clock Gating Control.
+#define SYSCTL_SCGC2_GPIOE 0x00000010 // Port E Clock Gating Control.
+#define SYSCTL_SCGC2_GPIOD 0x00000008 // Port D Clock Gating Control.
+#define SYSCTL_SCGC2_GPIOC 0x00000004 // Port C Clock Gating Control.
+#define SYSCTL_SCGC2_GPIOB 0x00000002 // Port B Clock Gating Control.
+#define SYSCTL_SCGC2_GPIOA 0x00000001 // Port A Clock Gating Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control.
+#define SYSCTL_DCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control.
+#define SYSCTL_DCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control.
+#define SYSCTL_DCGC0_PWM 0x00100000 // PWM Clock Gating Control.
+#define SYSCTL_DCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control.
+#define SYSCTL_DCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control.
+#define SYSCTL_DCGC0_ADC1SPD_M 0x00000C00 // ADC1 Sample Speed.
+#define SYSCTL_DCGC0_ADC1SPD_1M 0x00000C00 // 1M samples/second
+#define SYSCTL_DCGC0_ADC0SPD_M 0x00000300 // ADC0 Sample Speed.
+#define SYSCTL_DCGC0_ADC0SPD_1M 0x00000300 // 1M samples/second
+#define SYSCTL_DCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGC1_EPI0 0x40000000 // EPI0 Clock Gating.
+#define SYSCTL_DCGC1_I2S0 0x10000000 // I2S0 Clock Gating.
+#define SYSCTL_DCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock
+ // Gating.
+#define SYSCTL_DCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock
+ // Gating.
+#define SYSCTL_DCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock
+ // Gating.
+#define SYSCTL_DCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control.
+#define SYSCTL_DCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control.
+#define SYSCTL_DCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control.
+#define SYSCTL_DCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control.
+#define SYSCTL_DCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control.
+#define SYSCTL_DCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control.
+#define SYSCTL_DCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control.
+#define SYSCTL_DCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control.
+#define SYSCTL_DCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control.
+#define SYSCTL_DCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control.
+#define SYSCTL_DCGC1_UART2 0x00000004 // UART2 Clock Gating Control.
+#define SYSCTL_DCGC1_UART1 0x00000002 // UART1 Clock Gating Control.
+#define SYSCTL_DCGC1_UART0 0x00000001 // UART0 Clock Gating Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGC2_EPHY0 0x40000000 // PHY0 Clock Gating Control.
+#define SYSCTL_DCGC2_EMAC0 0x10000000 // MAC0 Clock Gating Control.
+#define SYSCTL_DCGC2_USB0 0x00010000 // USB0 Clock Gating Control.
+#define SYSCTL_DCGC2_UDMA 0x00002000 // Micro-DMA Clock Gating Control.
+#define SYSCTL_DCGC2_GPIOJ 0x00000100 // Port J Clock Gating Control.
+#define SYSCTL_DCGC2_GPIOH 0x00000080 // Port H Clock Gating Control.
+#define SYSCTL_DCGC2_GPIOG 0x00000040 // Port G Clock Gating Control.
+#define SYSCTL_DCGC2_GPIOF 0x00000020 // Port F Clock Gating Control.
+#define SYSCTL_DCGC2_GPIOE 0x00000010 // Port E Clock Gating Control.
+#define SYSCTL_DCGC2_GPIOD 0x00000008 // Port D Clock Gating Control.
+#define SYSCTL_DCGC2_GPIOC 0x00000004 // Port C Clock Gating Control.
+#define SYSCTL_DCGC2_GPIOB 0x00000002 // Port B Clock Gating Control.
+#define SYSCTL_DCGC2_GPIOA 0x00000001 // Port A Clock Gating Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DSLPCLKCFG
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DSLPCLKCFG_D_M 0x1F800000 // Divider Field Override.
+#define SYSCTL_DSLPCLKCFG_D_2 0x00800000 // /2
+#define SYSCTL_DSLPCLKCFG_D_3 0x01000000 // /3
+#define SYSCTL_DSLPCLKCFG_D_4 0x01800000 // /4
+#define SYSCTL_DSLPCLKCFG_D_5 0x02000000 // /5
+#define SYSCTL_DSLPCLKCFG_D_6 0x02800000 // /6
+#define SYSCTL_DSLPCLKCFG_D_7 0x03000000 // /7
+#define SYSCTL_DSLPCLKCFG_D_8 0x03800000 // /8
+#define SYSCTL_DSLPCLKCFG_D_9 0x04000000 // /9
+#define SYSCTL_DSLPCLKCFG_D_10 0x04800000 // /10
+#define SYSCTL_DSLPCLKCFG_D_11 0x05000000 // /11
+#define SYSCTL_DSLPCLKCFG_D_12 0x05800000 // /12
+#define SYSCTL_DSLPCLKCFG_D_13 0x06000000 // /13
+#define SYSCTL_DSLPCLKCFG_D_14 0x06800000 // /14
+#define SYSCTL_DSLPCLKCFG_D_15 0x07000000 // /15
+#define SYSCTL_DSLPCLKCFG_D_16 0x07800000 // /16
+#define SYSCTL_DSLPCLKCFG_O_M 0x00000070 // Clock Source.
+#define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000 // MOSC
+#define SYSCTL_DSLPCLKCFG_O_IO 0x00000010 // PIOSC
+#define SYSCTL_DSLPCLKCFG_O_30 0x00000030 // 30 kHz
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DSFLASHCFG
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DSFLASHCFG_SHDWN 0x00000001 // Flash Shutdown.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PIOSCCAL
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PIOSCCAL_UTEN 0x80000000 // Use User Trim Value.
+#define SYSCTL_PIOSCCAL_UPDATE 0x00000100 // Update Trim.
+#define SYSCTL_PIOSCCAL_UT_M 0x0000007F // User Trim Value.
+#define SYSCTL_PIOSCCAL_UT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_I2SMCLKCFG
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_I2SMCLKCFG_RXEN 0x80000000 // RX Clock Enable.
+#define SYSCTL_I2SMCLKCFG_RXI_M 0x0FF00000 // RX Clock Integer Input.
+#define SYSCTL_I2SMCLKCFG_RXF_M 0x000F0000 // RX Clock Fractional Input.
+#define SYSCTL_I2SMCLKCFG_TXEN 0x00008000 // TX Clock Enable.
+#define SYSCTL_I2SMCLKCFG_TXI_M 0x00000FF0 // TX Clock Integer Input.
+#define SYSCTL_I2SMCLKCFG_TXF_M 0x0000000F // TX Clock Fractional Input.
+#define SYSCTL_I2SMCLKCFG_RXI_S 20
+#define SYSCTL_I2SMCLKCFG_RXF_S 16
+#define SYSCTL_I2SMCLKCFG_TXI_S 4
+#define SYSCTL_I2SMCLKCFG_TXF_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC9 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC9_ADC1DC7 0x00800000 // ADC1 DC7 Present.
+#define SYSCTL_DC9_ADC1DC6 0x00400000 // ADC1 DC6 Present.
+#define SYSCTL_DC9_ADC1DC5 0x00200000 // ADC1 DC5 Present.
+#define SYSCTL_DC9_ADC1DC4 0x00100000 // ADC1 DC4 Present.
+#define SYSCTL_DC9_ADC1DC3 0x00080000 // ADC1 DC3 Present.
+#define SYSCTL_DC9_ADC1DC2 0x00040000 // ADC1 DC2 Present.
+#define SYSCTL_DC9_ADC1DC1 0x00020000 // ADC1 DC1 Present.
+#define SYSCTL_DC9_ADC1DC0 0x00010000 // ADC1 DC0 Present.
+#define SYSCTL_DC9_ADC0DC7 0x00000080 // ADC0 DC7 Present.
+#define SYSCTL_DC9_ADC0DC6 0x00000040 // ADC0 DC6 Present.
+#define SYSCTL_DC9_ADC0DC5 0x00000020 // ADC0 DC5 Present.
+#define SYSCTL_DC9_ADC0DC4 0x00000010 // ADC0 DC4 Present.
+#define SYSCTL_DC9_ADC0DC3 0x00000008 // ADC0 DC3 Present.
+#define SYSCTL_DC9_ADC0DC2 0x00000004 // ADC0 DC2 Present.
+#define SYSCTL_DC9_ADC0DC1 0x00000002 // ADC0 DC1 Present.
+#define SYSCTL_DC9_ADC0DC0 0x00000001 // ADC0 DC0 Present.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_NVMSTAT register.
+//
+//*****************************************************************************
+#define SYSCTL_NVMSTAT_FWB 0x00000001 // 32 Word Flash Write Buffer
+ // Active.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_SRCENDP register.
+//
+//*****************************************************************************
+#define UDMA_SRCENDP_ADDR_M 0xFFFFFFFF // Source Address End Pointer.
+#define UDMA_SRCENDP_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_DSTENDP register.
+//
+//*****************************************************************************
+#define UDMA_DSTENDP_ADDR_M 0xFFFFFFFF // Destination Address End Pointer.
+#define UDMA_DSTENDP_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_CHCTL register.
+//
+//*****************************************************************************
+#define UDMA_CHCTL_DSTINC_M 0xC0000000 // Destination Address Increment.
+#define UDMA_CHCTL_DSTINC_8 0x00000000 // Byte
+#define UDMA_CHCTL_DSTINC_16 0x40000000 // Half-word
+#define UDMA_CHCTL_DSTINC_32 0x80000000 // Word
+#define UDMA_CHCTL_DSTINC_NONE 0xC0000000 // No increment
+#define UDMA_CHCTL_DSTSIZE_M 0x30000000 // Destination Data Size.
+#define UDMA_CHCTL_DSTSIZE_8 0x00000000 // Byte
+#define UDMA_CHCTL_DSTSIZE_16 0x10000000 // Half-word
+#define UDMA_CHCTL_DSTSIZE_32 0x20000000 // Word
+#define UDMA_CHCTL_SRCINC_M 0x0C000000 // Source Address Increment.
+#define UDMA_CHCTL_SRCINC_8 0x00000000 // Byte
+#define UDMA_CHCTL_SRCINC_16 0x04000000 // Half-word
+#define UDMA_CHCTL_SRCINC_32 0x08000000 // Word
+#define UDMA_CHCTL_SRCINC_NONE 0x0C000000 // No increment
+#define UDMA_CHCTL_SRCSIZE_M 0x03000000 // Source Data Size.
+#define UDMA_CHCTL_SRCSIZE_8 0x00000000 // Byte
+#define UDMA_CHCTL_SRCSIZE_16 0x01000000 // Half-word
+#define UDMA_CHCTL_SRCSIZE_32 0x02000000 // Word
+#define UDMA_CHCTL_ARBSIZE_M 0x0003C000 // Arbitration Size.
+#define UDMA_CHCTL_ARBSIZE_1 0x00000000 // 1 Transfer
+#define UDMA_CHCTL_ARBSIZE_2 0x00004000 // 2 Transfers
+#define UDMA_CHCTL_ARBSIZE_4 0x00008000 // 4 Transfers
+#define UDMA_CHCTL_ARBSIZE_8 0x0000C000 // 8 Transfers
+#define UDMA_CHCTL_ARBSIZE_16 0x00010000 // 16 Transfers
+#define UDMA_CHCTL_ARBSIZE_32 0x00014000 // 32 Transfers
+#define UDMA_CHCTL_ARBSIZE_64 0x00018000 // 64 Transfers
+#define UDMA_CHCTL_ARBSIZE_128 0x0001C000 // 128 Transfers
+#define UDMA_CHCTL_ARBSIZE_256 0x00020000 // 256 Transfers
+#define UDMA_CHCTL_ARBSIZE_512 0x00024000 // 512 Transfers
+#define UDMA_CHCTL_ARBSIZE_1024 0x00028000 // 1024 Transfers
+#define UDMA_CHCTL_XFERSIZE_M 0x00003FF0 // Transfer Size (minus 1).
+#define UDMA_CHCTL_NXTUSEBURST 0x00000008 // Next Useburst.
+#define UDMA_CHCTL_XFERMODE_M 0x00000007 // DMA Transfer Mode.
+#define UDMA_CHCTL_XFERMODE_STOP \
+ 0x00000000 // Stop
+#define UDMA_CHCTL_XFERMODE_BASIC \
+ 0x00000001 // Basic
+#define UDMA_CHCTL_XFERMODE_AUTO \
+ 0x00000002 // Auto-Request
+#define UDMA_CHCTL_XFERMODE_PINGPONG \
+ 0x00000003 // Ping-Pong
+#define UDMA_CHCTL_XFERMODE_MEM_SG \
+ 0x00000004 // Memory Scatter-Gather
+#define UDMA_CHCTL_XFERMODE_MEM_SGA \
+ 0x00000005 // Alternate Memory Scatter-Gather
+#define UDMA_CHCTL_XFERMODE_PER_SG \
+ 0x00000006 // Peripheral Scatter-Gather
+#define UDMA_CHCTL_XFERMODE_PER_SGA \
+ 0x00000007 // Alternate Peripheral
+ // Scatter-Gather
+#define UDMA_CHCTL_XFERSIZE_S 4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_STAT register.
+//
+//*****************************************************************************
+#define UDMA_STAT_DMACHANS_M 0x001F0000 // Available DMA Channels Minus 1.
+#define UDMA_STAT_STATE_M 0x000000F0 // Control State Machine Status.
+#define UDMA_STAT_STATE_IDLE 0x00000000 // Idle
+#define UDMA_STAT_STATE_RD_CTRL 0x00000010 // Read Chan Control Data
+#define UDMA_STAT_STATE_RD_SRCENDP \
+ 0x00000020 // Read Source End Ptr
+#define UDMA_STAT_STATE_RD_DSTENDP \
+ 0x00000030 // Read Dest End Ptr
+#define UDMA_STAT_STATE_RD_SRCDAT \
+ 0x00000040 // Read Source Data
+#define UDMA_STAT_STATE_WR_DSTDAT \
+ 0x00000050 // Write Dest Data
+#define UDMA_STAT_STATE_WAIT 0x00000060 // Wait for Req Clear
+#define UDMA_STAT_STATE_WR_CTRL 0x00000070 // Write Chan Control Data
+#define UDMA_STAT_STATE_STALL 0x00000080 // Stalled
+#define UDMA_STAT_STATE_DONE 0x00000090 // Done
+#define UDMA_STAT_STATE_UNDEF 0x000000A0 // Undefined
+#define UDMA_STAT_MASTEN 0x00000001 // Master Enable.
+#define UDMA_STAT_DMACHANS_S 16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CFG register.
+//
+//*****************************************************************************
+#define UDMA_CFG_MASTEN 0x00000001 // Controller Master Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CTLBASE register.
+//
+//*****************************************************************************
+#define UDMA_CTLBASE_ADDR_M 0xFFFFFC00 // Channel Control Base Address.
+#define UDMA_CTLBASE_ADDR_S 10
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ALTBASE register.
+//
+//*****************************************************************************
+#define UDMA_ALTBASE_ADDR_M 0xFFFFFFFF // Alternate Channel Address
+ // Pointer.
+#define UDMA_ALTBASE_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_WAITSTAT register.
+//
+//*****************************************************************************
+#define UDMA_WAITSTAT_WAITREQ_M 0xFFFFFFFF // Channel [n] Wait Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_SWREQ register.
+//
+//*****************************************************************************
+#define UDMA_SWREQ_M 0xFFFFFFFF // Channel [n] Software Request.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_USEBURSTSET
+// register.
+//
+//*****************************************************************************
+#define UDMA_USEBURSTSET_SET_M 0xFFFFFFFF // Channel [n] Useburst Set.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_USEBURSTCLR
+// register.
+//
+//*****************************************************************************
+#define UDMA_USEBURSTCLR_CLR_M 0xFFFFFFFF // Channel [n] Useburst Clear.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_REQMASKSET
+// register.
+//
+//*****************************************************************************
+#define UDMA_REQMASKSET_SET_M 0xFFFFFFFF // Channel [n] Request Mask Set.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_REQMASKCLR
+// register.
+//
+//*****************************************************************************
+#define UDMA_REQMASKCLR_CLR_M 0xFFFFFFFF // Channel [n] Request Mask Clear.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ENASET register.
+//
+//*****************************************************************************
+#define UDMA_ENASET_SET_M 0xFFFFFFFF // Channel [n] Enable Set.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ENACLR register.
+//
+//*****************************************************************************
+#define UDMA_ENACLR_CLR_M 0xFFFFFFFF // Clear Channel [n] Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ALTSET register.
+//
+//*****************************************************************************
+#define UDMA_ALTSET_SET_M 0xFFFFFFFF // Channel [n] Alternate Set.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ALTCLR register.
+//
+//*****************************************************************************
+#define UDMA_ALTCLR_CLR_M 0xFFFFFFFF // Channel [n] Alternate Clear.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_PRIOSET register.
+//
+//*****************************************************************************
+#define UDMA_PRIOSET_SET_M 0xFFFFFFFF // Channel [n] Priority Set.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_PRIOCLR register.
+//
+//*****************************************************************************
+#define UDMA_PRIOCLR_CLR_M 0xFFFFFFFF // Channel [n] Priority Clear.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ERRCLR register.
+//
+//*****************************************************************************
+#define UDMA_ERRCLR_ERRCLR 0x00000001 // DMA Bus Error Clear.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CHALT register.
+//
+//*****************************************************************************
+#define UDMA_CHALT_M 0xFFFFFFFF // Channel [n] Alternate Assignment
+ // Select.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CHIS register.
+//
+//*****************************************************************************
+#define UDMA_CHIS_M 0xFFFFFFFF // Channel [n] Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_INT_TYPE register.
+//
+//*****************************************************************************
+#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32)
+#define NVIC_INT_TYPE_LINES_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_ST_CTRL_COUNT 0x00010000 // Count flag
+#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source
+#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt enable
+#define NVIC_ST_CTRL_ENABLE 0x00000001 // Counter mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_RELOAD register.
+//
+//*****************************************************************************
+#define NVIC_ST_RELOAD_M 0x00FFFFFF // Counter load value
+#define NVIC_ST_RELOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_CURRENT
+// register.
+//
+//*****************************************************************************
+#define NVIC_ST_CURRENT_M 0x00FFFFFF // Counter current value
+#define NVIC_ST_CURRENT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_CAL register.
+//
+//*****************************************************************************
+#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock
+#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew
+#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value
+#define NVIC_ST_CAL_ONEMS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN0 register.
+//
+//*****************************************************************************
+#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable
+#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable
+#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable
+#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable
+#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable
+#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable
+#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable
+#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable
+#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable
+#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable
+#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable
+#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable
+#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable
+#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable
+#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable
+#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable
+#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable
+#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable
+#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable
+#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable
+#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable
+#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable
+#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable
+#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable
+#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable
+#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable
+#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable
+#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable
+#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable
+#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable
+#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable
+#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN1 register.
+//
+//*****************************************************************************
+#define NVIC_EN1_INT59 0x08000000 // Interrupt 59 enable
+#define NVIC_EN1_INT58 0x04000000 // Interrupt 58 enable
+#define NVIC_EN1_INT57 0x02000000 // Interrupt 57 enable
+#define NVIC_EN1_INT56 0x01000000 // Interrupt 56 enable
+#define NVIC_EN1_INT55 0x00800000 // Interrupt 55 enable
+#define NVIC_EN1_INT54 0x00400000 // Interrupt 54 enable
+#define NVIC_EN1_INT53 0x00200000 // Interrupt 53 enable
+#define NVIC_EN1_INT52 0x00100000 // Interrupt 52 enable
+#define NVIC_EN1_INT51 0x00080000 // Interrupt 51 enable
+#define NVIC_EN1_INT50 0x00040000 // Interrupt 50 enable
+#define NVIC_EN1_INT49 0x00020000 // Interrupt 49 enable
+#define NVIC_EN1_INT48 0x00010000 // Interrupt 48 enable
+#define NVIC_EN1_INT47 0x00008000 // Interrupt 47 enable
+#define NVIC_EN1_INT46 0x00004000 // Interrupt 46 enable
+#define NVIC_EN1_INT45 0x00002000 // Interrupt 45 enable
+#define NVIC_EN1_INT44 0x00001000 // Interrupt 44 enable
+#define NVIC_EN1_INT43 0x00000800 // Interrupt 43 enable
+#define NVIC_EN1_INT42 0x00000400 // Interrupt 42 enable
+#define NVIC_EN1_INT41 0x00000200 // Interrupt 41 enable
+#define NVIC_EN1_INT40 0x00000100 // Interrupt 40 enable
+#define NVIC_EN1_INT39 0x00000080 // Interrupt 39 enable
+#define NVIC_EN1_INT38 0x00000040 // Interrupt 38 enable
+#define NVIC_EN1_INT37 0x00000020 // Interrupt 37 enable
+#define NVIC_EN1_INT36 0x00000010 // Interrupt 36 enable
+#define NVIC_EN1_INT35 0x00000008 // Interrupt 35 enable
+#define NVIC_EN1_INT34 0x00000004 // Interrupt 34 enable
+#define NVIC_EN1_INT33 0x00000002 // Interrupt 33 enable
+#define NVIC_EN1_INT32 0x00000001 // Interrupt 32 enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS0 register.
+//
+//*****************************************************************************
+#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable
+#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable
+#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable
+#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable
+#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable
+#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable
+#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable
+#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable
+#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable
+#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable
+#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable
+#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable
+#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable
+#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable
+#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable
+#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable
+#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable
+#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable
+#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable
+#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable
+#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable
+#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable
+#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable
+#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable
+#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable
+#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable
+#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable
+#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable
+#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable
+#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable
+#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable
+#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS1 register.
+//
+//*****************************************************************************
+#define NVIC_DIS1_INT59 0x08000000 // Interrupt 59 disable
+#define NVIC_DIS1_INT58 0x04000000 // Interrupt 58 disable
+#define NVIC_DIS1_INT57 0x02000000 // Interrupt 57 disable
+#define NVIC_DIS1_INT56 0x01000000 // Interrupt 56 disable
+#define NVIC_DIS1_INT55 0x00800000 // Interrupt 55 disable
+#define NVIC_DIS1_INT54 0x00400000 // Interrupt 54 disable
+#define NVIC_DIS1_INT53 0x00200000 // Interrupt 53 disable
+#define NVIC_DIS1_INT52 0x00100000 // Interrupt 52 disable
+#define NVIC_DIS1_INT51 0x00080000 // Interrupt 51 disable
+#define NVIC_DIS1_INT50 0x00040000 // Interrupt 50 disable
+#define NVIC_DIS1_INT49 0x00020000 // Interrupt 49 disable
+#define NVIC_DIS1_INT48 0x00010000 // Interrupt 48 disable
+#define NVIC_DIS1_INT47 0x00008000 // Interrupt 47 disable
+#define NVIC_DIS1_INT46 0x00004000 // Interrupt 46 disable
+#define NVIC_DIS1_INT45 0x00002000 // Interrupt 45 disable
+#define NVIC_DIS1_INT44 0x00001000 // Interrupt 44 disable
+#define NVIC_DIS1_INT43 0x00000800 // Interrupt 43 disable
+#define NVIC_DIS1_INT42 0x00000400 // Interrupt 42 disable
+#define NVIC_DIS1_INT41 0x00000200 // Interrupt 41 disable
+#define NVIC_DIS1_INT40 0x00000100 // Interrupt 40 disable
+#define NVIC_DIS1_INT39 0x00000080 // Interrupt 39 disable
+#define NVIC_DIS1_INT38 0x00000040 // Interrupt 38 disable
+#define NVIC_DIS1_INT37 0x00000020 // Interrupt 37 disable
+#define NVIC_DIS1_INT36 0x00000010 // Interrupt 36 disable
+#define NVIC_DIS1_INT35 0x00000008 // Interrupt 35 disable
+#define NVIC_DIS1_INT34 0x00000004 // Interrupt 34 disable
+#define NVIC_DIS1_INT33 0x00000002 // Interrupt 33 disable
+#define NVIC_DIS1_INT32 0x00000001 // Interrupt 32 disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND0 register.
+//
+//*****************************************************************************
+#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend
+#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend
+#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend
+#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend
+#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend
+#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend
+#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend
+#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend
+#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend
+#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend
+#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend
+#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend
+#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend
+#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend
+#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend
+#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend
+#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend
+#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend
+#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend
+#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend
+#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend
+#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend
+#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend
+#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend
+#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend
+#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend
+#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend
+#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend
+#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend
+#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend
+#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend
+#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND1 register.
+//
+//*****************************************************************************
+#define NVIC_PEND1_INT59 0x08000000 // Interrupt 59 pend
+#define NVIC_PEND1_INT58 0x04000000 // Interrupt 58 pend
+#define NVIC_PEND1_INT57 0x02000000 // Interrupt 57 pend
+#define NVIC_PEND1_INT56 0x01000000 // Interrupt 56 pend
+#define NVIC_PEND1_INT55 0x00800000 // Interrupt 55 pend
+#define NVIC_PEND1_INT54 0x00400000 // Interrupt 54 pend
+#define NVIC_PEND1_INT53 0x00200000 // Interrupt 53 pend
+#define NVIC_PEND1_INT52 0x00100000 // Interrupt 52 pend
+#define NVIC_PEND1_INT51 0x00080000 // Interrupt 51 pend
+#define NVIC_PEND1_INT50 0x00040000 // Interrupt 50 pend
+#define NVIC_PEND1_INT49 0x00020000 // Interrupt 49 pend
+#define NVIC_PEND1_INT48 0x00010000 // Interrupt 48 pend
+#define NVIC_PEND1_INT47 0x00008000 // Interrupt 47 pend
+#define NVIC_PEND1_INT46 0x00004000 // Interrupt 46 pend
+#define NVIC_PEND1_INT45 0x00002000 // Interrupt 45 pend
+#define NVIC_PEND1_INT44 0x00001000 // Interrupt 44 pend
+#define NVIC_PEND1_INT43 0x00000800 // Interrupt 43 pend
+#define NVIC_PEND1_INT42 0x00000400 // Interrupt 42 pend
+#define NVIC_PEND1_INT41 0x00000200 // Interrupt 41 pend
+#define NVIC_PEND1_INT40 0x00000100 // Interrupt 40 pend
+#define NVIC_PEND1_INT39 0x00000080 // Interrupt 39 pend
+#define NVIC_PEND1_INT38 0x00000040 // Interrupt 38 pend
+#define NVIC_PEND1_INT37 0x00000020 // Interrupt 37 pend
+#define NVIC_PEND1_INT36 0x00000010 // Interrupt 36 pend
+#define NVIC_PEND1_INT35 0x00000008 // Interrupt 35 pend
+#define NVIC_PEND1_INT34 0x00000004 // Interrupt 34 pend
+#define NVIC_PEND1_INT33 0x00000002 // Interrupt 33 pend
+#define NVIC_PEND1_INT32 0x00000001 // Interrupt 32 pend
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND0 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend
+#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend
+#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend
+#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend
+#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend
+#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend
+#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend
+#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend
+#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend
+#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend
+#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend
+#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend
+#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend
+#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend
+#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend
+#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend
+#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend
+#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend
+#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend
+#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend
+#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend
+#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend
+#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend
+#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend
+#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend
+#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend
+#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend
+#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend
+#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend
+#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend
+#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend
+#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND1 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND1_INT59 0x08000000 // Interrupt 59 unpend
+#define NVIC_UNPEND1_INT58 0x04000000 // Interrupt 58 unpend
+#define NVIC_UNPEND1_INT57 0x02000000 // Interrupt 57 unpend
+#define NVIC_UNPEND1_INT56 0x01000000 // Interrupt 56 unpend
+#define NVIC_UNPEND1_INT55 0x00800000 // Interrupt 55 unpend
+#define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend
+#define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend
+#define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend
+#define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend
+#define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend
+#define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend
+#define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend
+#define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend
+#define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend
+#define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend
+#define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend
+#define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend
+#define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend
+#define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend
+#define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend
+#define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend
+#define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend
+#define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend
+#define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend
+#define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend
+#define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend
+#define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend
+#define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE0 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active
+#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active
+#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active
+#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active
+#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active
+#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active
+#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active
+#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active
+#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active
+#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active
+#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active
+#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active
+#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active
+#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active
+#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active
+#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active
+#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active
+#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active
+#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active
+#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active
+#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active
+#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active
+#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active
+#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active
+#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active
+#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active
+#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active
+#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active
+#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active
+#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active
+#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active
+#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE1 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE1_INT59 0x08000000 // Interrupt 59 active
+#define NVIC_ACTIVE1_INT58 0x04000000 // Interrupt 58 active
+#define NVIC_ACTIVE1_INT57 0x02000000 // Interrupt 57 active
+#define NVIC_ACTIVE1_INT56 0x01000000 // Interrupt 56 active
+#define NVIC_ACTIVE1_INT55 0x00800000 // Interrupt 55 active
+#define NVIC_ACTIVE1_INT54 0x00400000 // Interrupt 54 active
+#define NVIC_ACTIVE1_INT53 0x00200000 // Interrupt 53 active
+#define NVIC_ACTIVE1_INT52 0x00100000 // Interrupt 52 active
+#define NVIC_ACTIVE1_INT51 0x00080000 // Interrupt 51 active
+#define NVIC_ACTIVE1_INT50 0x00040000 // Interrupt 50 active
+#define NVIC_ACTIVE1_INT49 0x00020000 // Interrupt 49 active
+#define NVIC_ACTIVE1_INT48 0x00010000 // Interrupt 48 active
+#define NVIC_ACTIVE1_INT47 0x00008000 // Interrupt 47 active
+#define NVIC_ACTIVE1_INT46 0x00004000 // Interrupt 46 active
+#define NVIC_ACTIVE1_INT45 0x00002000 // Interrupt 45 active
+#define NVIC_ACTIVE1_INT44 0x00001000 // Interrupt 44 active
+#define NVIC_ACTIVE1_INT43 0x00000800 // Interrupt 43 active
+#define NVIC_ACTIVE1_INT42 0x00000400 // Interrupt 42 active
+#define NVIC_ACTIVE1_INT41 0x00000200 // Interrupt 41 active
+#define NVIC_ACTIVE1_INT40 0x00000100 // Interrupt 40 active
+#define NVIC_ACTIVE1_INT39 0x00000080 // Interrupt 39 active
+#define NVIC_ACTIVE1_INT38 0x00000040 // Interrupt 38 active
+#define NVIC_ACTIVE1_INT37 0x00000020 // Interrupt 37 active
+#define NVIC_ACTIVE1_INT36 0x00000010 // Interrupt 36 active
+#define NVIC_ACTIVE1_INT35 0x00000008 // Interrupt 35 active
+#define NVIC_ACTIVE1_INT34 0x00000004 // Interrupt 34 active
+#define NVIC_ACTIVE1_INT33 0x00000002 // Interrupt 33 active
+#define NVIC_ACTIVE1_INT32 0x00000001 // Interrupt 32 active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI0 register.
+//
+//*****************************************************************************
+#define NVIC_PRI0_INT3_M 0xFF000000 // Interrupt 3 priority mask
+#define NVIC_PRI0_INT2_M 0x00FF0000 // Interrupt 2 priority mask
+#define NVIC_PRI0_INT1_M 0x0000FF00 // Interrupt 1 priority mask
+#define NVIC_PRI0_INT0_M 0x000000FF // Interrupt 0 priority mask
+#define NVIC_PRI0_INT3_S 24
+#define NVIC_PRI0_INT2_S 16
+#define NVIC_PRI0_INT1_S 8
+#define NVIC_PRI0_INT0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI1 register.
+//
+//*****************************************************************************
+#define NVIC_PRI1_INT7_M 0xFF000000 // Interrupt 7 priority mask
+#define NVIC_PRI1_INT6_M 0x00FF0000 // Interrupt 6 priority mask
+#define NVIC_PRI1_INT5_M 0x0000FF00 // Interrupt 5 priority mask
+#define NVIC_PRI1_INT4_M 0x000000FF // Interrupt 4 priority mask
+#define NVIC_PRI1_INT7_S 24
+#define NVIC_PRI1_INT6_S 16
+#define NVIC_PRI1_INT5_S 8
+#define NVIC_PRI1_INT4_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI2 register.
+//
+//*****************************************************************************
+#define NVIC_PRI2_INT11_M 0xFF000000 // Interrupt 11 priority mask
+#define NVIC_PRI2_INT10_M 0x00FF0000 // Interrupt 10 priority mask
+#define NVIC_PRI2_INT9_M 0x0000FF00 // Interrupt 9 priority mask
+#define NVIC_PRI2_INT8_M 0x000000FF // Interrupt 8 priority mask
+#define NVIC_PRI2_INT11_S 24
+#define NVIC_PRI2_INT10_S 16
+#define NVIC_PRI2_INT9_S 8
+#define NVIC_PRI2_INT8_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI3 register.
+//
+//*****************************************************************************
+#define NVIC_PRI3_INT15_M 0xFF000000 // Interrupt 15 priority mask
+#define NVIC_PRI3_INT14_M 0x00FF0000 // Interrupt 14 priority mask
+#define NVIC_PRI3_INT13_M 0x0000FF00 // Interrupt 13 priority mask
+#define NVIC_PRI3_INT12_M 0x000000FF // Interrupt 12 priority mask
+#define NVIC_PRI3_INT15_S 24
+#define NVIC_PRI3_INT14_S 16
+#define NVIC_PRI3_INT13_S 8
+#define NVIC_PRI3_INT12_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI4 register.
+//
+//*****************************************************************************
+#define NVIC_PRI4_INT19_M 0xFF000000 // Interrupt 19 priority mask
+#define NVIC_PRI4_INT18_M 0x00FF0000 // Interrupt 18 priority mask
+#define NVIC_PRI4_INT17_M 0x0000FF00 // Interrupt 17 priority mask
+#define NVIC_PRI4_INT16_M 0x000000FF // Interrupt 16 priority mask
+#define NVIC_PRI4_INT19_S 24
+#define NVIC_PRI4_INT18_S 16
+#define NVIC_PRI4_INT17_S 8
+#define NVIC_PRI4_INT16_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI5 register.
+//
+//*****************************************************************************
+#define NVIC_PRI5_INT23_M 0xFF000000 // Interrupt 23 priority mask
+#define NVIC_PRI5_INT22_M 0x00FF0000 // Interrupt 22 priority mask
+#define NVIC_PRI5_INT21_M 0x0000FF00 // Interrupt 21 priority mask
+#define NVIC_PRI5_INT20_M 0x000000FF // Interrupt 20 priority mask
+#define NVIC_PRI5_INT23_S 24
+#define NVIC_PRI5_INT22_S 16
+#define NVIC_PRI5_INT21_S 8
+#define NVIC_PRI5_INT20_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI6 register.
+//
+//*****************************************************************************
+#define NVIC_PRI6_INT27_M 0xFF000000 // Interrupt 27 priority mask
+#define NVIC_PRI6_INT26_M 0x00FF0000 // Interrupt 26 priority mask
+#define NVIC_PRI6_INT25_M 0x0000FF00 // Interrupt 25 priority mask
+#define NVIC_PRI6_INT24_M 0x000000FF // Interrupt 24 priority mask
+#define NVIC_PRI6_INT27_S 24
+#define NVIC_PRI6_INT26_S 16
+#define NVIC_PRI6_INT25_S 8
+#define NVIC_PRI6_INT24_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI7 register.
+//
+//*****************************************************************************
+#define NVIC_PRI7_INT31_M 0xFF000000 // Interrupt 31 priority mask
+#define NVIC_PRI7_INT30_M 0x00FF0000 // Interrupt 30 priority mask
+#define NVIC_PRI7_INT29_M 0x0000FF00 // Interrupt 29 priority mask
+#define NVIC_PRI7_INT28_M 0x000000FF // Interrupt 28 priority mask
+#define NVIC_PRI7_INT31_S 24
+#define NVIC_PRI7_INT30_S 16
+#define NVIC_PRI7_INT29_S 8
+#define NVIC_PRI7_INT28_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI8 register.
+//
+//*****************************************************************************
+#define NVIC_PRI8_INT35_M 0xFF000000 // Interrupt 35 priority mask
+#define NVIC_PRI8_INT34_M 0x00FF0000 // Interrupt 34 priority mask
+#define NVIC_PRI8_INT33_M 0x0000FF00 // Interrupt 33 priority mask
+#define NVIC_PRI8_INT32_M 0x000000FF // Interrupt 32 priority mask
+#define NVIC_PRI8_INT35_S 24
+#define NVIC_PRI8_INT34_S 16
+#define NVIC_PRI8_INT33_S 8
+#define NVIC_PRI8_INT32_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI9 register.
+//
+//*****************************************************************************
+#define NVIC_PRI9_INT39_M 0xFF000000 // Interrupt 39 priority mask
+#define NVIC_PRI9_INT38_M 0x00FF0000 // Interrupt 38 priority mask
+#define NVIC_PRI9_INT37_M 0x0000FF00 // Interrupt 37 priority mask
+#define NVIC_PRI9_INT36_M 0x000000FF // Interrupt 36 priority mask
+#define NVIC_PRI9_INT39_S 24
+#define NVIC_PRI9_INT38_S 16
+#define NVIC_PRI9_INT37_S 8
+#define NVIC_PRI9_INT36_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI10 register.
+//
+//*****************************************************************************
+#define NVIC_PRI10_INT43_M 0xFF000000 // Interrupt 43 priority mask
+#define NVIC_PRI10_INT42_M 0x00FF0000 // Interrupt 42 priority mask
+#define NVIC_PRI10_INT41_M 0x0000FF00 // Interrupt 41 priority mask
+#define NVIC_PRI10_INT40_M 0x000000FF // Interrupt 40 priority mask
+#define NVIC_PRI10_INT43_S 24
+#define NVIC_PRI10_INT42_S 16
+#define NVIC_PRI10_INT41_S 8
+#define NVIC_PRI10_INT40_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_CPUID register.
+//
+//*****************************************************************************
+#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer
+#define NVIC_CPUID_VAR_M 0x00F00000 // Variant
+#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Processor part number
+#define NVIC_CPUID_REV_M 0x0000000F // Revision
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_INT_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_INT_CTRL_NMI_SET 0x80000000 // Pend a NMI
+#define NVIC_INT_CTRL_PEND_SV 0x10000000 // Pend a PendSV
+#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // Unpend a PendSV
+#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug interrupt handling
+#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Debug interrupt pending
+#define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000 // Highest pending exception
+#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to base
+#define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF // Current active exception
+#define NVIC_INT_CTRL_VEC_PEN_S 12
+#define NVIC_INT_CTRL_VEC_ACT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_VTABLE register.
+//
+//*****************************************************************************
+#define NVIC_VTABLE_BASE 0x20000000 // Vector table base
+#define NVIC_VTABLE_OFFSET_M 0x1FFFFF00 // Vector table offset
+#define NVIC_VTABLE_OFFSET_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_APINT register.
+//
+//*****************************************************************************
+#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Vector key mask
+#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key
+#define NVIC_APINT_ENDIANESS 0x00008000 // Data endianess
+#define NVIC_APINT_PRIGROUP_M 0x00000700 // Priority group
+#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split
+#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split
+#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split
+#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split
+#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split
+#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split
+#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split
+#define NVIC_APINT_SYSRESETREQ 0x00000004 // System reset request
+#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear active NMI/fault info
+#define NVIC_APINT_VECT_RESET 0x00000001 // System reset
+#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wakeup on pend
+#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep sleep enable
+#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR exit
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_CFG_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore bus fault in NMI/fault
+#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on divide by 0
+#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on unaligned access
+#define NVIC_CFG_CTRL_DEEP_PEND 0x00000004 // Allow deep interrupt trigger
+#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow main interrupt trigger
+#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread state control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_PRI1 register.
+//
+//*****************************************************************************
+#define NVIC_SYS_PRI1_RES_M 0xFF000000 // Priority of reserved handler
+#define NVIC_SYS_PRI1_USAGE_M 0x00FF0000 // Priority of usage fault handler
+#define NVIC_SYS_PRI1_BUS_M 0x0000FF00 // Priority of bus fault handler
+#define NVIC_SYS_PRI1_MEM_M 0x000000FF // Priority of mem manage handler
+#define NVIC_SYS_PRI1_USAGE_S 16
+#define NVIC_SYS_PRI1_BUS_S 8
+#define NVIC_SYS_PRI1_MEM_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_PRI2 register.
+//
+//*****************************************************************************
+#define NVIC_SYS_PRI2_SVC_M 0xFF000000 // Priority of SVCall handler
+#define NVIC_SYS_PRI2_RES_M 0x00FFFFFF // Priority of reserved handlers
+#define NVIC_SYS_PRI2_SVC_S 24
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_PRI3 register.
+//
+//*****************************************************************************
+#define NVIC_SYS_PRI3_TICK_M 0xFF000000 // Priority of Sys Tick handler
+#define NVIC_SYS_PRI3_PENDSV_M 0x00FF0000 // Priority of PendSV handler
+#define NVIC_SYS_PRI3_RES_M 0x0000FF00 // Priority of reserved handler
+#define NVIC_SYS_PRI3_DEBUG_M 0x000000FF // Priority of debug handler
+#define NVIC_SYS_PRI3_TICK_S 24
+#define NVIC_SYS_PRI3_PENDSV_S 16
+#define NVIC_SYS_PRI3_DEBUG_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_HND_CTRL
+// register.
+//
+//*****************************************************************************
+#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage fault enable
+#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus fault enable
+#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Mem manage fault enable
+#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVCall is pended
+#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus fault is pended
+#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // Sys tick is active
+#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV is active
+#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Monitor is active
+#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVCall is active
+#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage fault is active
+#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus fault is active
+#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Mem manage is active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FAULT_STAT
+// register.
+//
+//*****************************************************************************
+#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide by zero fault
+#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned access fault
+#define NVIC_FAULT_STAT_NOCP 0x00080000 // No coprocessor fault
+#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC fault
+#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid state fault
+#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined instruction fault
+#define NVIC_FAULT_STAT_BFARV 0x00008000 // BFAR is valid
+#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack bus fault
+#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack bus fault
+#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise data bus error
+#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise data bus error
+#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction bus fault
+#define NVIC_FAULT_STAT_MMARV 0x00000080 // MMAR is valid
+#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack access violation
+#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack access violation
+#define NVIC_FAULT_STAT_DERR 0x00000002 // Data access violation
+#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction access violation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_HFAULT_STAT
+// register.
+//
+//*****************************************************************************
+#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug event
+#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Cannot execute fault handler
+#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector table read fault
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DEBUG_STAT
+// register.
+//
+//*****************************************************************************
+#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted
+#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch
+#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match
+#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction
+#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MM_ADDR register.
+//
+//*****************************************************************************
+#define NVIC_MM_ADDR_M 0xFFFFFFFF // Data fault address
+#define NVIC_MM_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FAULT_ADDR
+// register.
+//
+//*****************************************************************************
+#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Data bus fault address
+#define NVIC_FAULT_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_TYPE register.
+//
+//*****************************************************************************
+#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I regions
+#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D regions
+#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or unified MPU
+#define NVIC_MPU_TYPE_IREGION_S 16
+#define NVIC_MPU_TYPE_DREGION_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004 // MPU default region in priv mode
+#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU enabled during faults
+#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_NUMBER
+// register.
+//
+//*****************************************************************************
+#define NVIC_MPU_NUMBER_M 0x000000FF // MPU region to access
+#define NVIC_MPU_NUMBER_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE_ADDR_M 0xFFFFFFE0 // Base address mask
+#define NVIC_MPU_BASE_VALID 0x00000010 // Region number valid
+#define NVIC_MPU_BASE_REGION_M 0x0000000F // Region number
+#define NVIC_MPU_BASE_ADDR_S 8
+#define NVIC_MPU_BASE_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR_M 0xFFFF0000 // Attributes
+#define NVIC_MPU_ATTR_AP_NO_NO 0x00000000 // prv: no access, usr: no access
+#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000 // Bufferable
+#define NVIC_MPU_ATTR_CACHEABLE 0x00020000 // Cacheable
+#define NVIC_MPU_ATTR_SHAREABLE 0x00040000 // Shareable
+#define NVIC_MPU_ATTR_TEX_M 0x00380000 // Type extension mask
+#define NVIC_MPU_ATTR_AP_RW_NO 0x01000000 // prv: rw, usr: none
+#define NVIC_MPU_ATTR_AP_RW_RO 0x02000000 // prv: rw, usr: read-only
+#define NVIC_MPU_ATTR_AP_RW_RW 0x03000000 // prv: rw, usr: rw
+#define NVIC_MPU_ATTR_AP_RO_NO 0x05000000 // prv: ro, usr: none
+#define NVIC_MPU_ATTR_AP_RO_RO 0x06000000 // prv: ro, usr: ro
+#define NVIC_MPU_ATTR_AP_M 0x07000000 // Access permissions mask
+#define NVIC_MPU_ATTR_XN 0x10000000 // Execute disable
+#define NVIC_MPU_ATTR_SRD_M 0x0000FF00 // Sub-region disable mask
+#define NVIC_MPU_ATTR_SRD_0 0x00000100 // Sub-region 0 disable
+#define NVIC_MPU_ATTR_SRD_1 0x00000200 // Sub-region 1 disable
+#define NVIC_MPU_ATTR_SRD_2 0x00000400 // Sub-region 2 disable
+#define NVIC_MPU_ATTR_SRD_3 0x00000800 // Sub-region 3 disable
+#define NVIC_MPU_ATTR_SRD_4 0x00001000 // Sub-region 4 disable
+#define NVIC_MPU_ATTR_SRD_5 0x00002000 // Sub-region 5 disable
+#define NVIC_MPU_ATTR_SRD_6 0x00004000 // Sub-region 6 disable
+#define NVIC_MPU_ATTR_SRD_7 0x00008000 // Sub-region 7 disable
+#define NVIC_MPU_ATTR_SIZE_M 0x0000003E // Region size mask
+#define NVIC_MPU_ATTR_SIZE_32B 0x00000008 // Region size 32 bytes
+#define NVIC_MPU_ATTR_SIZE_64B 0x0000000A // Region size 64 bytes
+#define NVIC_MPU_ATTR_SIZE_128B 0x0000000C // Region size 128 bytes
+#define NVIC_MPU_ATTR_SIZE_256B 0x0000000E // Region size 256 bytes
+#define NVIC_MPU_ATTR_SIZE_512B 0x00000010 // Region size 512 bytes
+#define NVIC_MPU_ATTR_SIZE_1K 0x00000012 // Region size 1 Kbytes
+#define NVIC_MPU_ATTR_SIZE_2K 0x00000014 // Region size 2 Kbytes
+#define NVIC_MPU_ATTR_SIZE_4K 0x00000016 // Region size 4 Kbytes
+#define NVIC_MPU_ATTR_SIZE_8K 0x00000018 // Region size 8 Kbytes
+#define NVIC_MPU_ATTR_SIZE_16K 0x0000001A // Region size 16 Kbytes
+#define NVIC_MPU_ATTR_SIZE_32K 0x0000001C // Region size 32 Kbytes
+#define NVIC_MPU_ATTR_SIZE_64K 0x0000001E // Region size 64 Kbytes
+#define NVIC_MPU_ATTR_SIZE_128K 0x00000020 // Region size 128 Kbytes
+#define NVIC_MPU_ATTR_SIZE_256K 0x00000022 // Region size 256 Kbytes
+#define NVIC_MPU_ATTR_SIZE_512K 0x00000024 // Region size 512 Kbytes
+#define NVIC_MPU_ATTR_SIZE_1M 0x00000026 // Region size 1 Mbytes
+#define NVIC_MPU_ATTR_SIZE_2M 0x00000028 // Region size 2 Mbytes
+#define NVIC_MPU_ATTR_SIZE_4M 0x0000002A // Region size 4 Mbytes
+#define NVIC_MPU_ATTR_SIZE_8M 0x0000002C // Region size 8 Mbytes
+#define NVIC_MPU_ATTR_SIZE_16M 0x0000002E // Region size 16 Mbytes
+#define NVIC_MPU_ATTR_SIZE_32M 0x00000030 // Region size 32 Mbytes
+#define NVIC_MPU_ATTR_SIZE_64M 0x00000032 // Region size 64 Mbytes
+#define NVIC_MPU_ATTR_SIZE_128M 0x00000034 // Region size 128 Mbytes
+#define NVIC_MPU_ATTR_SIZE_256M 0x00000036 // Region size 256 Mbytes
+#define NVIC_MPU_ATTR_SIZE_512M 0x00000038 // Region size 512 Mbytes
+#define NVIC_MPU_ATTR_SIZE_1G 0x0000003A // Region size 1 Gbytes
+#define NVIC_MPU_ATTR_SIZE_2G 0x0000003C // Region size 2 Gbytes
+#define NVIC_MPU_ATTR_SIZE_4G 0x0000003E // Region size 4 Gbytes
+#define NVIC_MPU_ATTR_ENABLE 0x00000001 // Region enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask
+#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key
+#define NVIC_DBG_CTRL_S_RESET_ST \
+ 0x02000000 // Core has reset since last read
+#define NVIC_DBG_CTRL_S_RETIRE_ST \
+ 0x01000000 // Core has executed insruction
+ // since last read
+#define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 // Core is locked up
+#define NVIC_DBG_CTRL_S_SLEEP 0x00040000 // Core is sleeping
+#define NVIC_DBG_CTRL_S_HALT 0x00020000 // Core status on halt
+#define NVIC_DBG_CTRL_S_REGRDY 0x00010000 // Register read/write available
+#define NVIC_DBG_CTRL_C_SNAPSTALL \
+ 0x00000020 // Breaks a stalled load/store
+#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping
+#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core
+#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core
+#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_XFER register.
+//
+//*****************************************************************************
+#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read
+#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register
+#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask
+#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP
+#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP
+#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP
+#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register
+#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15
+#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14
+#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13
+#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12
+#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11
+#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10
+#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9
+#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8
+#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7
+#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6
+#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5
+#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4
+#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3
+#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2
+#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1
+#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_DATA register.
+//
+//*****************************************************************************
+#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache
+#define NVIC_DBG_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_INT register.
+//
+//*****************************************************************************
+#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault
+#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors
+#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error
+#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state
+#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check
+#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error
+#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault
+#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status
+#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset
+#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending
+#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SW_TRIG register.
+//
+//*****************************************************************************
+#define NVIC_SW_TRIG_INTID_M 0x000003FF // Interrupt to trigger
+#define NVIC_SW_TRIG_INTID_S 0
+
+#endif // __LM3S9B92_H__
Property changes on: branches/eagle_mmc/src/platform/lm3s/lm3s9b92.h
___________________________________________________________________
Name: svn:executable
+ *
Modified: branches/eagle_mmc/src/platform/lm3s/platform.c
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/platform.c 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lm3s/platform.c 2009-11-06 02:08:32 UTC (rev 526)
@@ -17,6 +17,9 @@
#include "common.h"
#include "math.h"
#include "diskio.h"
+#include "lua.h"
+#include "lauxlib.h"
+#include "lrotable.h"
// Platform specific includes
#include "hw_ints.h"
@@ -24,11 +27,12 @@
#include "hw_types.h"
#include "hw_pwm.h"
#include "hw_nvic.h"
+#include "hw_ethernet.h"
#include "debug.h"
#include "gpio.h"
#include "interrupt.h"
#include "sysctl.h"
-#include "usart.h"
+#include "uart.h"
#include "ssi.h"
#include "timer.h"
#include "pwm.h"
@@ -44,6 +48,22 @@
#include "disp.h"
#include "adc.h"
+
+#ifdef FORLM3S9B92
+ #define TARGET_IS_TEMPEST_RB1
+
+ #include "lm3s9b92.h"
+#elif FORLM3S8962
+ #include "lm3s8962.h"
+#elif FORLM3S6965
+ #include "lm3s6965.h"
+#elif FORLM3S6918
+ #include "lm3s6918.h"
+#endif
+
+#include "rom.h"
+#include "rom_map.h"
+
// UIP sys tick data
// NOTE: when using virtual timers, SYSTICKHZ and VTMR_FREQ_HZ should have the
// same value, as they're served by the same timer (the systick)
@@ -65,7 +85,11 @@
int platform_init()
{
// Set the clocking to run from PLL
- SysCtlClockSet(SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_8MHZ);
+#ifdef FORLM3S9B92
+ MAP_SysCtlClockSet(SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_16MHZ);
+#else
+ MAP_SysCtlClockSet(SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_8MHZ);
+#endif
// Setup PIO
pios_init();
@@ -95,10 +119,10 @@
// If the ethernet controller is used the timer is already initialized, so skip this sequence
#if VTMR_NUM_TIMERS > 0 && !defined( BUILD_UIP )
// Configure SysTick for a periodic interrupt.
- SysTickPeriodSet( SysCtlClockGet() / SYSTICKHZ );
- SysTickEnable();
- SysTickIntEnable();
- IntMasterEnable();
+ MAP_SysTickPeriodSet( MAP_SysCtlClockGet() / SYSTICKHZ );
+ MAP_SysTickEnable();
+ MAP_SysTickIntEnable();
+ MAP_IntMasterEnable();
#endif
// All done
@@ -108,18 +132,29 @@
// ****************************************************************************
// PIO
// Same configuration on LM3S8962, LM3S6965, LM3S6918 (8 ports)
+// 9B92 has 9 ports (Port J in addition to A-H)
+#ifdef FORLM3S9B92
+ static const u32 pio_base[] = { GPIO_PORTA_BASE, GPIO_PORTB_BASE, GPIO_PORTC_BASE, GPIO_PORTD_BASE,
+ GPIO_PORTE_BASE, GPIO_PORTF_BASE, GPIO_PORTG_BASE, GPIO_PORTH_BASE,
+ GPIO_PORTJ_BASE };
+
+ static const u32 pio_sysctl[] = { SYSCTL_PERIPH_GPIOA, SYSCTL_PERIPH_GPIOB, SYSCTL_PERIPH_GPIOC, SYSCTL_PERIPH_GPIOD,
+ SYSCTL_PERIPH_GPIOE, SYSCTL_PERIPH_GPIOF, SYSCTL_PERIPH_GPIOG, SYSCTL_PERIPH_GPIOH,
+ SYSCTL_PERIPH_GPIOJ };
+#else
+ static const u32 pio_base[] = { GPIO_PORTA_BASE, GPIO_PORTB_BASE, GPIO_PORTC_BASE, GPIO_PORTD_BASE,
+ GPIO_PORTE_BASE, GPIO_PORTF_BASE, GPIO_PORTG_BASE, GPIO_PORTH_BASE };
+
+ static const u32 pio_sysctl[] = { SYSCTL_PERIPH_GPIOA, SYSCTL_PERIPH_GPIOB, SYSCTL_PERIPH_GPIOC, SYSCTL_PERIPH_GPIOD,
+ SYSCTL_PERIPH_GPIOE, SYSCTL_PERIPH_GPIOF, SYSCTL_PERIPH_GPIOG, SYSCTL_PERIPH_GPIOH };
+#endif
-static const u32 pio_base[] = { GPIO_PORTA_BASE, GPIO_PORTB_BASE, GPIO_PORTC_BASE, GPIO_PORTD_BASE,
- GPIO_PORTE_BASE, GPIO_PORTF_BASE, GPIO_PORTG_BASE, GPIO_PORTH_BASE };
-static const u32 pio_sysctl[] = { SYSCTL_PERIPH_GPIOA, SYSCTL_PERIPH_GPIOB, SYSCTL_PERIPH_GPIOC, SYSCTL_PERIPH_GPIOD,
- SYSCTL_PERIPH_GPIOE, SYSCTL_PERIPH_GPIOF, SYSCTL_PERIPH_GPIOG, SYSCTL_PERIPH_GPIOH };
-
static void pios_init()
{
unsigned i;
for( i = 0; i < NUM_PIO; i ++ )
- SysCtlPeripheralEnable(pio_sysctl[ i ]);
+ MAP_SysCtlPeripheralEnable(pio_sysctl[ i ]);
}
pio_type platform_pio_op( unsigned port, pio_type pinmask, int op )
@@ -129,44 +164,44 @@
switch( op )
{
case PLATFORM_IO_PORT_SET_VALUE:
- GPIOPinWrite( base, 0xFF, pinmask );
+ MAP_GPIOPinWrite( base, 0xFF, pinmask );
break;
case PLATFORM_IO_PIN_SET:
- GPIOPinWrite( base, pinmask, pinmask );
+ MAP_GPIOPinWrite( base, pinmask, pinmask );
break;
case PLATFORM_IO_PIN_CLEAR:
- GPIOPinWrite( base, pinmask, 0 );
+ MAP_GPIOPinWrite( base, pinmask, 0 );
break;
case PLATFORM_IO_PORT_DIR_INPUT:
pinmask = 0xFF;
case PLATFORM_IO_PIN_DIR_INPUT:
- GPIOPinTypeGPIOInput( base, pinmask );
+ MAP_GPIOPinTypeGPIOInput( base, pinmask );
break;
case PLATFORM_IO_PORT_DIR_OUTPUT:
pinmask = 0xFF;
case PLATFORM_IO_PIN_DIR_OUTPUT:
- GPIOPinTypeGPIOOutput( base, pinmask );
+ MAP_GPIOPinTypeGPIOOutput( base, pinmask );
break;
case PLATFORM_IO_PORT_GET_VALUE:
- retval = GPIOPinRead( base, 0xFF );
+ retval = MAP_GPIOPinRead( base, 0xFF );
break;
case PLATFORM_IO_PIN_GET:
- retval = GPIOPinRead( base, pinmask ) ? 1 : 0;
+ retval = MAP_GPIOPinRead( base, pinmask ) ? 1 : 0;
break;
case PLATFORM_IO_PIN_PULLUP:
case PLATFORM_IO_PIN_PULLDOWN:
- GPIOPadConfigSet( base, pinmask, GPIO_STRENGTH_8MA, op == PLATFORM_IO_PIN_PULLUP ? GPIO_PIN_TYPE_STD_WPU : GPIO_PIN_TYPE_STD_WPD );
+ MAP_GPIOPadConfigSet( base, pinmask, GPIO_STRENGTH_8MA, op == PLATFORM_IO_PIN_PULLUP ? GPIO_PIN_TYPE_STD_WPU : GPIO_PIN_TYPE_STD_WPD );
break;
case PLATFORM_IO_PIN_NOPULL:
- GPIOPadConfigSet( base, pinmask, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD );
+ MAP_GPIOPadConfigSet( base, pinmask, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD );
break;
default:
@@ -178,7 +213,7 @@
// ****************************************************************************
// SPI
-// Same configuration on LM3S8962, LM3S6965 and LM3S6918 (2 SPI ports)
+// Same configuration on LM3S8962, LM3S6965, LM3S6918 and LM3S9B92 (2 SPI ports)
// All possible LM3S SPIs defs
// FIXME this anticipates support for a platform with 2 SPI port
@@ -196,7 +231,7 @@
unsigned i;
for( i = 0; i < NUM_SPI; i ++ )
- SysCtlPeripheralEnable(spi_sysctl[ i ]);
+ MAP_SysCtlPeripheralEnable(spi_sysctl[ i ]);
}
u32 platform_spi_setup( unsigned id, int mode, u32 clock, unsigned cpol, unsigned cpha, unsigned databits )
@@ -208,22 +243,22 @@
else
protocol = cpha ? SSI_FRF_MOTO_MODE_3 : SSI_FRF_MOTO_MODE_2;
mode = mode == PLATFORM_SPI_MASTER ? SSI_MODE_MASTER : SSI_MODE_SLAVE;
- SSIDisable( spi_base[ id ] );
+ MAP_SSIDisable( spi_base[ id ] );
- GPIOPinTypeSSI( spi_gpio_base[ id ], spi_gpio_pins[ id ] );
+ MAP_GPIOPinTypeSSI( spi_gpio_base[ id ], spi_gpio_pins[ id ] );
// FIXME: not sure this is always "right"
GPIOPadConfigSet(spi_gpio_base[ id ], spi_gpio_pins[ id ], GPIO_STRENGTH_4MA, GPIO_PIN_TYPE_STD_WPU);
- SSIConfigSetExpClk( spi_base[ id ], SysCtlClockGet(), protocol, mode, clock, databits );
- SSIEnable( spi_base[ id ] );
+ MAP_SSIConfigSetExpClk( spi_base[ id ], MAP_SysCtlClockGet(), protocol, mode, clock, databits );
+ MAP_SSIEnable( spi_base[ id ] );
return clock;
}
spi_data_type platform_spi_send_recv( unsigned id, spi_data_type data )
{
- SSIDataPut( spi_base[ id ], data );
- SSIDataGet( spi_base[ id ], &data );
+ MAP_SSIDataPut( spi_base[ id ], data );
+ MAP_SSIDataGet( spi_base[ id ], &data );
return data;
}
@@ -236,7 +271,7 @@
// ****************************************************************************
// UART
-// Different configurations for LM3S8962, LM3S6918 (2 UARTs) and LM3S6965 (3 UARTs)
+// Different configurations for LM3S8962, LM3S6918 (2 UARTs) and LM3S6965, LM3S9B92 (3 UARTs)
// All possible LM3S uarts defs
static const u32 uart_base[] = { UART0_BASE, UART1_BASE, UART2_BASE };
@@ -250,11 +285,11 @@
u32 temp;
int c;
- temp = UARTIntStatus(uart_base[ CON_UART_ID ], true);
- UARTIntClear(uart_base[ CON_UART_ID ], temp);
- while( UARTCharsAvail( uart_base[ CON_UART_ID ] ) )
+ temp = MAP_UARTIntStatus(uart_base[ CON_UART_ID ], true);
+ MAP_UARTIntClear(uart_base[ CON_UART_ID ], temp);
+ while( MAP_UARTCharsAvail( uart_base[ CON_UART_ID ] ) )
{
- c = UARTCharGetNonBlocking( uart_base[ CON_UART_ID ] );
+ c = MAP_UARTCharGetNonBlocking( uart_base[ CON_UART_ID ] );
buf_write( BUF_ID_UART, CON_UART_ID, ( t_buf_data* )&c );
}
}
@@ -266,12 +301,12 @@
unsigned i;
for( i = 0; i < NUM_UART; i ++ )
- SysCtlPeripheralEnable(uart_sysctl[ i ]);
+ MAP_SysCtlPeripheralEnable(uart_sysctl[ i ]);
// Special case for UART 0
// Configure the UART for 115,200, 8-N-1 operation.
- GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1);
- UARTConfigSetExpClk(UART0_BASE, SysCtlClockGet(), CON_UART_SPEED,
+ MAP_GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1);
+ MAP_UARTConfigSetExpClk(UART0_BASE, SysCtlClockGet(), CON_UART_SPEED,
(UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE |
UART_CONFIG_PAR_NONE));
@@ -283,7 +318,7 @@
IntEnable(INT_UART0);
- UARTIntEnable( uart_base[ CON_UART_ID ], UART_INT_RX | UART_INT_RT );
+ MAP_UARTIntEnable( uart_base[ CON_UART_ID ], UART_INT_RX | UART_INT_RT );
#endif
}
@@ -291,7 +326,7 @@
{
u32 config;
- GPIOPinTypeUART(uart_gpio_base [ id ], uart_gpio_pins[ id ]);
+ MAP_GPIOPinTypeUART(uart_gpio_base [ id ], uart_gpio_pins[ id ]);
switch( databits )
{
@@ -316,12 +351,14 @@
else
config |= UART_CONFIG_PAR_NONE;
- return UARTConfigSetExpClk(uart_base[ id ], SysCtlClockGet(), baud, config);
+ MAP_UARTConfigSetExpClk( uart_base[ id ], MAP_SysCtlClockGet(), baud, config );
+ MAP_UARTConfigGetExpClk( uart_base[ id ], MAP_SysCtlClockGet(), &baud, &config );
+ return baud;
}
void platform_uart_send( unsigned id, u8 data )
{
- UARTCharPut( uart_base[ id ], data );
+ MAP_UARTCharPut( uart_base[ id ], data );
}
int platform_s_uart_recv( unsigned id, s32 timeout )
@@ -329,13 +366,13 @@
u32 base = uart_base[ id ];
if( timeout == 0 )
- return UARTCharGetNonBlocking( base );
- return UARTCharGet( base );
+ return MAP_UARTCharGetNonBlocking( base );
+ return MAP_UARTCharGet( base );
}
// ****************************************************************************
// Timers
-// Same on LM3S8962, LM3S6965 and LM3S6918 (4 timers)
+// Same on LM3S8962, LM3S6965, LM3S6918 and LM3S9B92 (4 timers)
// All possible LM3S timers defs
static const u32 timer_base[] = { TIMER0_BASE, TIMER1_BASE, TIMER2_BASE, TIMER3_BASE };
@@ -347,9 +384,9 @@
for( i = 0; i < NUM_TIMER; i ++ )
{
- SysCtlPeripheralEnable(timer_sysctl[ i ]);
- TimerConfigure(timer_base[ i ], TIMER_CFG_32_BIT_PER);
- TimerEnable(timer_base[ i ], TIMER_A);
+ MAP_SysCtlPeripheralEnable(timer_sysctl[ i ]);
+ MAP_TimerConfigure(timer_base[ i ], TIMER_CFG_32_BIT_PER);
+ MAP_TimerEnable(timer_base[ i ], TIMER_A);
}
}
@@ -358,9 +395,9 @@
timer_data_type final;
u32 base = timer_base[ id ];
- final = 0xFFFFFFFF - ( ( ( u64 )delay_us * SysCtlClockGet() ) / 1000000 );
- TimerLoadSet( base, TIMER_A, 0xFFFFFFFF );
- while( TimerValueGet( base, TIMER_A ) > final );
+ final = 0xFFFFFFFF - ( ( ( u64 )delay_us * MAP_SysCtlClockGet() ) / 1000000 );
+ MAP_TimerLoadSet( base, TIMER_A, 0xFFFFFFFF );
+ while( MAP_TimerValueGet( base, TIMER_A ) > final );
}
u32 platform_s_timer_op( unsigned id, int op, u32 data )
@@ -373,12 +410,12 @@
{
case PLATFORM_TIMER_OP_START:
res = 0xFFFFFFFF;
- TimerControlTrigger(base, TIMER_A, false);
- TimerLoadSet( base, TIMER_A, 0xFFFFFFFF );
+ MAP_TimerControlTrigger(base, TIMER_A, false);
+ MAP_TimerLoadSet( base, TIMER_A, 0xFFFFFFFF );
break;
case PLATFORM_TIMER_OP_READ:
- res = TimerValueGet( base, TIMER_A );
+ res = MAP_TimerValueGet( base, TIMER_A );
break;
case PLATFORM_TIMER_OP_GET_MAX_DELAY:
@@ -391,7 +428,7 @@
case PLATFORM_TIMER_OP_SET_CLOCK:
case PLATFORM_TIMER_OP_GET_CLOCK:
- res = SysCtlClockGet();
+ res = MAP_SysCtlClockGet();
break;
}
@@ -409,19 +446,28 @@
// Port/pin information for all channels
#ifdef FORLM3S6965
const static u32 pwm_ports[] = { GPIO_PORTF_BASE, GPIO_PORTD_BASE, GPIO_PORTB_BASE, GPIO_PORTB_BASE, GPIO_PORTE_BASE, GPIO_PORTE_BASE };
+#elif FORLM3S9B92
+ const static u32 pwm_ports[] = { GPIO_PORTD_BASE, GPIO_PORTD_BASE, GPIO_PORTB_BASE, GPIO_PORTB_BASE, GPIO_PORTE_BASE, GPIO_PORTE_BASE };
+ // GPIOPCTL probably needs modification to do PWM for 2&3, Digital Function 2
#else
const static u32 pwm_ports[] = { GPIO_PORTF_BASE, GPIO_PORTG_BASE, GPIO_PORTB_BASE, GPIO_PORTB_BASE, GPIO_PORTE_BASE, GPIO_PORTE_BASE };
#endif
const static u8 pwm_pins[] = { GPIO_PIN_0, GPIO_PIN_1, GPIO_PIN_0, GPIO_PIN_1, GPIO_PIN_0, GPIO_PIN_1 };
+
// PWM generators
-const static u16 pwm_gens[] = { PWM_GEN_0, PWM_GEN_1, PWM_GEN_2 };
+#ifdef FORLM3S9B92
+ const static u16 pwm_gens[] = { PWM_GEN_0, PWM_GEN_1, PWM_GEN_2, PWM_GEN_3 };
+#else
+ const static u16 pwm_gens[] = { PWM_GEN_0, PWM_GEN_1, PWM_GEN_2 };
+#endif
+
// PWM outputs
const static u16 pwm_outs[] = { PWM_OUT_0, PWM_OUT_1, PWM_OUT_2, PWM_OUT_3, PWM_OUT_4, PWM_OUT_5 };
static void pwms_init()
{
- SysCtlPeripheralEnable( SYSCTL_PERIPH_PWM );
- SysCtlPWMClockSet( SYSCTL_PWMDIV_1 );
+ MAP_SysCtlPeripheralEnable( SYSCTL_PERIPH_PWM );
+ MAP_SysCtlPWMClockSet( SYSCTL_PWMDIV_1 );
}
// Helper function: return the PWM clock
@@ -430,11 +476,11 @@
unsigned i;
u32 clk;
- clk = SysCtlPWMClockGet();
+ clk = MAP_SysCtlPWMClockGet();
for( i = 0; i < sizeof( pwm_div_ctl ) / sizeof( u32 ); i ++ )
if( clk == pwm_div_ctl[ i ] )
break;
- return SysCtlClockGet() / pwm_div_data[ i ];
+ return MAP_SysCtlClockGet() / pwm_div_data[ i ];
}
// Helper function: set the PWM clock
@@ -443,11 +489,11 @@
unsigned i, min_i;
u32 sysclk;
- sysclk = SysCtlClockGet();
+ sysclk = MAP_SysCtlClockGet();
for( i = min_i = 0; i < sizeof( pwm_div_data ) / sizeof( u8 ); i ++ )
if( ABSDIFF( clock, sysclk / pwm_div_data[ i ] ) < ABSDIFF( clock, sysclk / pwm_div_data[ min_i ] ) )
min_i = i;
- SysCtlPWMClockSet( pwm_div_ctl[ min_i ] );
+ MAP_SysCtlPWMClockSet( pwm_div_ctl[ min_i ] );
return sysclk / pwm_div_data[ min_i ];
}
@@ -457,14 +503,14 @@
u32 period;
// Set pin as PWM
- GPIOPinTypePWM( pwm_ports[ id ], pwm_pins[ id ] );
+ MAP_GPIOPinTypePWM( pwm_ports[ id ], pwm_pins[ id ] );
// Compute period
period = pwmclk / frequency;
// Set the period
- PWMGenConfigure( PWM_BASE, pwm_gens[ id >> 1 ], PWM_GEN_MODE_UP_DOWN | PWM_GEN_MODE_NO_SYNC );
- PWMGenPeriodSet( PWM_BASE, pwm_gens[ id >> 1 ], period );
+ MAP_PWMGenConfigure( PWM_BASE, pwm_gens[ id >> 1 ], PWM_GEN_MODE_UP_DOWN | PWM_GEN_MODE_NO_SYNC );
+ MAP_PWMGenPeriodSet( PWM_BASE, pwm_gens[ id >> 1 ], period );
// Set duty cycle
- PWMPulseWidthSet( PWM_BASE, pwm_outs[ id ], ( period * duty ) / 100 );
+ MAP_PWMPulseWidthSet( PWM_BASE, pwm_outs[ id ], ( period * duty ) / 100 );
// Return actual frequency
return pwmclk / period;
}
@@ -484,13 +530,13 @@
break;
case PLATFORM_PWM_OP_START:
- PWMOutputState( PWM_BASE, 1 << id, true );
- PWMGenEnable( PWM_BASE, pwm_gens[ id >> 1 ] );
+ MAP_PWMOutputState( PWM_BASE, 1 << id, true );
+ MAP_PWMGenEnable( PWM_BASE, pwm_gens[ id >> 1 ] );
break;
case PLATFORM_PWM_OP_STOP:
- PWMOutputState( PWM_BASE, 1 << id, false );
- PWMGenDisable( PWM_BASE, pwm_gens[ id >> 1 ] );
+ MAP_PWMOutputState( PWM_BASE, 1 << id, false );
+ MAP_PWMGenDisable( PWM_BASE, pwm_gens[ id >> 1 ] );
break;
}
@@ -502,17 +548,31 @@
void platform_cpu_enable_interrupts()
{
- IntMasterEnable();
+ MAP_IntMasterEnable();
}
void platform_cpu_disable_interrupts()
{
- IntMasterDisable();
+ MAP_IntMasterDisable();
}
// *****************************************************************************
// ADC specific functions and variables
+// Pin configuration if necessary
+#ifdef FORLM3S9B92
+ const static u32 adc_ports[] = { GPIO_PORTE_BASE, GPIO_PORTE_BASE, GPIO_PORTE_BASE, GPIO_PORTE_BASE,
+ GPIO_PORTD_BASE, GPIO_PORTD_BASE, GPIO_PORTD_BASE, GPIO_PORTD_BASE,
+ GPIO_PORTE_BASE, GPIO_PORTE_BASE, GPIO_PORTB_BASE, GPIO_PORTB_BASE,
+ GPIO_PORTD_BASE, GPIO_PORTD_BASE, GPIO_PORTD_BASE, GPIO_PORTD_BASE };
+
+ const static u8 adc_pins[] = { GPIO_PIN_7, GPIO_PIN_6, GPIO_PIN_5, GPIO_PIN_4,
+ GPIO_PIN_7, GPIO_PIN_6, GPIO_PIN_5, GPIO_PIN_4,
+ GPIO_PIN_3, GPIO_PIN_2, GPIO_PIN_4, GPIO_PIN_5,
+ GPIO_PIN_3, GPIO_PIN_2, GPIO_PIN_1, GPIO_PIN_0 };
+
+ #define ADC_PIN_CONFIG
+#endif
const static u32 adc_ctls[] = { ADC_CTL_CH0, ADC_CTL_CH1, ADC_CTL_CH2, ADC_CTL_CH3 };
const static u32 adc_ints[] = { INT_ADC0, INT_ADC1, INT_ADC2, INT_ADC3 };
@@ -533,7 +593,7 @@
// If there are no more active channels, stop the sequencer
if( d->ch_active == 0 )
{
- ADCSequenceDisable( ADC_BASE, d->seq_id );
+ MAP_ADCSequenceDisable( ADC_BASE, d->seq_id );
d->running = 0;
}
}
@@ -545,8 +605,8 @@
elua_adc_dev_state *d = adc_get_dev_state( 0 );
elua_adc_ch_state *s;
- ADCIntClear( ADC_BASE, d->seq_id );
- ADCSequenceDataGet( ADC_BASE, d->seq_id, tmpbuff );
+ MAP_ADCIntClear( ADC_BASE, d->seq_id );
+ MAP_ADCSequenceDataGet( ADC_BASE, d->seq_id, tmpbuff );
d->seq_ctr = 0;
@@ -586,7 +646,7 @@
if ( d->clocked == 0 && d->running == 1 )
{
// Need to manually fire off sample request in single sample mode
- ADCProcessorTrigger( ADC_BASE, d->seq_id );
+ MAP_ADCProcessorTrigger( ADC_BASE, d->seq_id );
}
}
@@ -595,21 +655,19 @@
unsigned id;
elua_adc_dev_state *d = adc_get_dev_state( 0 );
- SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC);
+ MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC);
// Try ramping up max sampling rate
- SysCtlADCSpeedSet(SYSCTL_ADCSPEED_500KSPS);
- SysCtlADCSpeedSet(SYSCTL_ADCSPEED_1MSPS);
+ MAP_SysCtlADCSpeedSet(SYSCTL_ADCSPEED_500KSPS);
+ MAP_SysCtlADCSpeedSet(SYSCTL_ADCSPEED_1MSPS);
for( id = 0; id < NUM_ADC; id ++ )
- {
adc_init_ch_state( id );
- }
// Perform sequencer setup
platform_adc_setclock( 0, 0 );
- ADCIntEnable( ADC_BASE, d->seq_id );
- IntEnable( adc_ints[ d->seq_id ] );
+ MAP_ADCIntEnable( ADC_BASE, d->seq_id );
+ MAP_IntEnable( adc_ints[ d->seq_id ] );
}
u32 platform_adc_setclock( unsigned id, u32 frequency )
@@ -617,44 +675,52 @@
elua_adc_dev_state *d = adc_get_dev_state( 0 );
// Make sure sequencer is disabled before making changes
- ADCSequenceDisable( ADC_BASE, d->seq_id );
+ MAP_ADCSequenceDisable( ADC_BASE, d->seq_id );
if ( frequency > 0 )
{
d->clocked = 1;
// Set sequence id to be triggered repeatedly, with priority id
- ADCSequenceConfigure( ADC_BASE, d->seq_id, ADC_TRIGGER_TIMER, d->seq_id );
+ MAP_ADCSequenceConfigure( ADC_BASE, d->seq_id, ADC_TRIGGER_TIMER, d->seq_id );
// Set up timer trigger
- TimerLoadSet( timer_base[ d->timer_id ], TIMER_A, SysCtlClockGet() / frequency );
- frequency = SysCtlClockGet() / TimerLoadGet( timer_base[ d->timer_id ], TIMER_A );
+ MAP_TimerLoadSet( timer_base[ d->timer_id ], TIMER_A, MAP_SysCtlClockGet() / frequency );
+ frequency = MAP_SysCtlClockGet() / MAP_TimerLoadGet( timer_base[ d->timer_id ], TIMER_A );
}
else
{
d->clocked = 0;
// Conversion will run back-to-back until required samples are acquired
- ADCSequenceConfigure( ADC_BASE, d->seq_id, ADC_TRIGGER_PROCESSOR, d->seq_id ) ;
+ MAP_ADCSequenceConfigure( ADC_BASE, d->seq_id, ADC_TRIGGER_PROCESSOR, d->seq_id ) ;
}
return frequency;
}
+
+
int platform_adc_update_sequence( )
{
elua_adc_dev_state *d = adc_get_dev_state( 0 );
- ADCSequenceDisable( ADC_BASE, d->seq_id );
+ MAP_ADCSequenceDisable( ADC_BASE, d->seq_id );
// NOTE: seq ctr should have an incrementer that will wrap appropriately..
d->seq_ctr = 0;
while( d->seq_ctr < d->seq_len-1 )
{
- ADCSequenceStepConfigure( ADC_BASE, d->seq_id, d->seq_ctr, adc_ctls[ d->ch_state[ d->seq_ctr ]->id ] );
+ MAP_ADCSequenceStepConfigure( ADC_BASE, d->seq_id, d->seq_ctr, adc_ctls[ d->ch_state[ d->seq_ctr ]->id ] );
+#ifdef ADC_PIN_CONFIG
+ MAP_GPIOPinTypeADC( adc_ports[ d->ch_state[ d->seq_ctr ]->id ], adc_pins[ d->ch_state[ d->seq_ctr ]->id ] );
+#endif
d->seq_ctr++;
}
- ADCSequenceStepConfigure( ADC_BASE, d->seq_id, d->seq_ctr, ADC_CTL_IE | ADC_CTL_END | adc_ctls[ d->ch_state[ d->seq_ctr ]->id ] );
+ MAP_ADCSequenceStepConfigure( ADC_BASE, d->seq_id, d->seq_ctr, ADC_CTL_IE | ADC_CTL_END | adc_ctls[ d->ch_state[ d->seq_ctr ]->id ] );
+#ifdef ADC_PIN_CONFIG
+ MAP_GPIOPinTypeADC( adc_ports[ d->ch_state[ d->seq_ctr ]->id ], adc_pins[ d->ch_state[ d->seq_ctr ]->id ] );
+#endif
d->seq_ctr = 0;
- ADCSequenceEnable( ADC_BASE, d->seq_id );
+ MAP_ADCSequenceEnable( ADC_BASE, d->seq_id );
return PLATFORM_OK;
}
@@ -668,17 +734,17 @@
{
adc_update_dev_sequence( 0 );
- ADCSequenceEnable( ADC_BASE, d->seq_id );
+ MAP_ADCSequenceEnable( ADC_BASE, d->seq_id );
d->running = 1;
if( d->clocked == 1 )
{
- TimerControlTrigger(timer_base[d->timer_id], TIMER_A, true);
- TimerEnable(timer_base[d->timer_id], TIMER_A);
+ MAP_TimerControlTrigger(timer_base[d->timer_id], TIMER_A, true);
+ MAP_TimerEnable(timer_base[d->timer_id], TIMER_A);
}
else
{
- ADCProcessorTrigger( ADC_BASE, d->seq_id );
+ MAP_ADCProcessorTrigger( ADC_BASE, d->seq_id );
}
}
@@ -743,45 +809,49 @@
static struct uip_eth_addr sTempAddr;
// Enable and reset the controller
- SysCtlPeripheralEnable( SYSCTL_PERIPH_ETH );
- SysCtlPeripheralReset( SYSCTL_PERIPH_ETH );
+ MAP_SysCtlPeripheralEnable( SYSCTL_PERIPH_ETH );
+ MAP_SysCtlPeripheralReset( SYSCTL_PERIPH_ETH );
+#ifdef FORLM3S9B92
+ GPIOPinConfigure(GPIO_PF2_LED1);
+ GPIOPinConfigure(GPIO_PF3_LED0);
+#endif
+
// Enable Ethernet LEDs
- GPIODirModeSet( GPIO_PORTF_BASE, GPIO_PIN_2 | GPIO_PIN_3, GPIO_DIR_MODE_HW );
- GPIOPadConfigSet( GPIO_PORTF_BASE, GPIO_PIN_2 | GPIO_PIN_3, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD );
+ MAP_GPIODirModeSet( GPIO_PORTF_BASE, GPIO_PIN_2 | GPIO_PIN_3, GPIO_DIR_MODE_HW );
+ MAP_GPIOPadConfigSet( GPIO_PORTF_BASE, GPIO_PIN_2 | GPIO_PIN_3, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD );
// Configure SysTick for a periodic interrupt.
- SysTickPeriodSet(SysCtlClockGet() / SYSTICKHZ );
- SysTickEnable();
- SysTickIntEnable();
+ MAP_SysTickPeriodSet( MAP_SysCtlClockGet() / SYSTICKHZ);
+ MAP_SysTickEnable();
+ MAP_SysTickIntEnable();
// Intialize the Ethernet Controller and disable all Ethernet Controller interrupt sources.
- EthernetIntDisable(ETH_BASE, (ETH_INT_PHY | ETH_INT_MDIO | ETH_INT_RXER |
+ MAP_EthernetIntDisable(ETH_BASE, (ETH_INT_PHY | ETH_INT_MDIO | ETH_INT_RXER |
ETH_INT_RXOF | ETH_INT_TX | ETH_INT_TXER | ETH_INT_RX));
- temp = EthernetIntStatus(ETH_BASE, false);
- EthernetIntClear(ETH_BASE, temp);
+ temp = MAP_EthernetIntStatus(ETH_BASE, false);
+ MAP_EthernetIntClear(ETH_BASE, temp);
// Initialize the Ethernet Controller for operation.
- EthernetInitExpClk(ETH_BASE, SysCtlClockGet());
+ MAP_EthernetInitExpClk(ETH_BASE, MAP_SysCtlClockGet());
// Configure the Ethernet Controller for normal operation.
// - Full Duplex
// - TX CRC Auto Generation
// - TX Padding Enabled
- EthernetConfigSet(ETH_BASE, (ETH_CFG_TX_DPLXEN | ETH_CFG_TX_CRCEN |
- ETH_CFG_TX_PADEN));
+ MAP_EthernetConfigSet(ETH_BASE, (ETH_CFG_TX_DPLXEN | ETH_CFG_TX_CRCEN | ETH_CFG_TX_PADEN));
// Enable the Ethernet Controller.
- EthernetEnable(ETH_BASE);
+ MAP_EthernetEnable(ETH_BASE);
// Enable the Ethernet interrupt.
- IntEnable(INT_ETH);
+ MAP_IntEnable(INT_ETH);
// Enable the Ethernet RX Packet interrupt source.
- EthernetIntEnable(ETH_BASE, ETH_INT_RX);
+ MAP_EthernetIntEnable(ETH_BASE, ETH_INT_RX);
// Enable all processor interrupts.
- IntMasterEnable();
+ MAP_IntMasterEnable();
// Configure the hardware MAC address for Ethernet Controller filtering of
// incoming packets.
@@ -789,7 +859,7 @@
// For the Ethernet Eval Kits, the MAC address will be stored in the
// non-volatile USER0 and USER1 registers. These registers can be read
// using the FlashUserGet function, as illustrated below.
- FlashUserGet(&user0, &user1);
+ MAP_FlashUserGet(&user0, &user1);
// Convert the 24/24 split MAC address from NV ram into a 32/16 split MAC
// address needed to program the hardware registers, then program the MAC
@@ -802,7 +872,7 @@
sTempAddr.addr[5] = ((user1 >> 16) & 0xff);
// Program the hardware with it's MAC address (for filtering).
- EthernetMACAddrSet(ETH_BASE, (unsigned char *)&sTempAddr);
+ MAP_EthernetMACAddrSet(ETH_BASE, (unsigned char *)&sTempAddr);
// Initialize the eLua uIP layer
elua_uip_init( &sTempAddr );
@@ -814,12 +884,12 @@
void platform_eth_send_packet( const void* src, u32 size )
{
- EthernetPacketPut( ETH_BASE, uip_buf, uip_len );
+ MAP_EthernetPacketPut( ETH_BASE, uip_buf, uip_len );
}
u32 platform_eth_get_packet_nb( void* buf, u32 maxlen )
{
- return EthernetPacketGetNonBlocking( ETH_BASE, uip_buf, sizeof( uip_buf ) );
+ return MAP_EthernetPacketGetNonBlocking( ETH_BASE, uip_buf, sizeof( uip_buf ) );
}
void platform_eth_force_interrupt()
@@ -882,3 +952,46 @@
{
}
#endif // #ifdef ELUA_UIP
+
+// ****************************************************************************
+// Platform specific modules go here
+
+#ifdef ENABLE_DISP
+
+#define MIN_OPT_LEVEL 2
+#include "lrodefs.h"
+extern const LUA_REG_TYPE disp_map[];
+
+const LUA_REG_TYPE platform_map[] =
+{
+#if LUA_OPTIMIZE_MEMORY > 0
+ { LSTRKEY( "disp" ), LROVAL( disp_map ) },
+#endif
+ { LNILKEY, LNILVAL }
+};
+
+LUALIB_API int luaopen_platform( lua_State *L )
+{
+#if LUA_OPTIMIZE_MEMORY > 0
+ return 0;
+#else // #if LUA_OPTIMIZE_MEMORY > 0
+ luaL_register( L, PS_LIB_TABLE_NAME, platform_map );
+
+ // Setup the new tables inside platform table
+ lua_newtable( L );
+ luaL_register( L, NULL, disp_map );
+ lua_setfield( L, -2, "disp" );
+
+ return 1;
+#endif // #if LUA_OPTIMIZE_MEMORY > 0
+}
+
+#else // #ifdef ENABLE_DISP
+
+LUALIB_API int luaopen_platform( lua_State *L )
+{
+ return 0;
+}
+
+#endif // #ifdef ENABLE_DISP
+
Modified: branches/eagle_mmc/src/platform/lm3s/platform_conf.h
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/platform_conf.h 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lm3s/platform_conf.h 2009-11-06 02:08:32 UTC (rev 526)
@@ -18,7 +18,7 @@
#define BUILD_MMCFS
#define BUILD_TERM
#define BUILD_UIP
-#define BUILD_DHCPC
+//#define BUILD_DHCPC
#define BUILD_DNS
#define BUILD_CON_GENERIC
#define BUILD_ADC
@@ -37,12 +37,10 @@
// *****************************************************************************
// Auxiliary libraries that will be compiled for this platform
+// The name of the platform specific libs table
+// FIXME: should handle partial or no inclusion of platform specific modules per conf.py
#ifdef ENABLE_DISP
-#define AUXLIB_DISP "disp"
-LUALIB_API int ( luaopen_disp )( lua_State* L );
-#define DISPLINE _ROM( AUXLIB_DISP, luaopen_disp, disp_map )
-#else
-#define DISPLINE
+#define PS_LIB_TABLE_NAME "lm3s"
#endif
#ifdef FORLM3S6918
@@ -57,6 +55,12 @@
#define NETLINE
#endif
+#ifdef PS_LIB_TABLE_NAME
+#define PLATLINE _ROM( PS_LIB_TABLE_NAME, luaopen_platform, platform_map )
+#else
+#define PLATLINE
+#endif
+
#define LUA_PLATFORM_LIBS_ROM\
_ROM( AUXLIB_PIO, luaopen_pio, pio_map )\
_ROM( AUXLIB_SPI, luaopen_spi, spi_map )\
@@ -67,22 +71,22 @@
_ROM( AUXLIB_TERM, luaopen_term, term_map )\
_ROM( AUXLIB_PACK, luaopen_pack, pack_map )\
_ROM( AUXLIB_BIT, luaopen_bit, bit_map )\
+ _ROM( AUXLIB_BITARRAY, luaopen_bitarray, bitarray_map )\
NETLINE\
_ROM( AUXLIB_CPU, luaopen_cpu, cpu_map )\
_ROM( AUXLIB_ADC, luaopen_adc, adc_map )\
_ROM( AUXLIB_LUARPC, luaopen_luarpc, rpc_map )\
- DISPLINE\
- _ROM( LUA_MATHLIBNAME, luaopen_math, math_map )
+ _ROM( LUA_MATHLIBNAME, luaopen_math, math_map )\
+ PLATLINE
-
// *****************************************************************************
// Configuration data
// Static TCP/IP configuration
#define ELUA_CONF_IPADDR0 192
#define ELUA_CONF_IPADDR1 168
-#define ELUA_CONF_IPADDR2 1
-#define ELUA_CONF_IPADDR3 218
+#define ELUA_CONF_IPADDR2 0
+#define ELUA_CONF_IPADDR3 5
#define ELUA_CONF_NETMASK0 255
#define ELUA_CONF_NETMASK1 255
@@ -91,12 +95,12 @@
#define ELUA_CONF_DEFGW0 192
#define ELUA_CONF_DEFGW1 168
-#define ELUA_CONF_DEFGW2 1
+#define ELUA_CONF_DEFGW2 0
#define ELUA_CONF_DEFGW3 1
#define ELUA_CONF_DNS0 192
#define ELUA_CONF_DNS1 168
-#define ELUA_CONF_DNS2 1
+#define ELUA_CONF_DNS2 0
#define ELUA_CONF_DNS3 1
// *****************************************************************************
@@ -108,10 +112,16 @@
// Number of resources (0 if not available/not implemented)
-#define NUM_PIO 7
+#ifdef FORLM3S9B92
+ #define NUM_PIO 7
+#else
+ #define NUM_PIO 7
+#endif
#define NUM_SPI 1
#ifdef FORLM3S6965
#define NUM_UART 3
+#elif FORLM3S9B92
+ #define NUM_UART 3
#else
#define NUM_UART 2
#endif
@@ -177,12 +187,23 @@
// #define PIO_PINS_PER_PORT (n) if each port has the same number of pins, or
// #define PIO_PIN_ARRAY { n1, n2, ... } to define pins per port in an array
// Use #define PIO_PINS_PER_PORT 0 if this isn't needed
-#define PIO_PIN_ARRAY { 8, 8, 8, 8, 4, 4, 2 }
+#ifdef FORLM3S9B92
+ #define PIO_PIN_ARRAY { 8, 8, 8, 8, 8, 6, 8, 8, 8 }
+#else
+ #define PIO_PIN_ARRAY { 8, 8, 8, 8, 4, 4, 2 }
+#endif
+// A, B, C, D, E, F, G, H, J
+#ifdef FORLM3S9B92
+ #define SRAM_SIZE ( 0x18000 )
+#else
+ #define SRAM_SIZE ( 0x10000 )
+#endif
+
// Allocator data: define your free memory zones here in two arrays
// (start address and end address)
#define MEM_START_ADDRESS { ( void* )end }
-#define MEM_END_ADDRESS { ( void* )( SRAM_BASE + 0x10000 - STACK_SIZE_TOTAL - 1 ) }
+#define MEM_END_ADDRESS { ( void* )( SRAM_BASE + SRAM_SIZE - STACK_SIZE_TOTAL - 1 ) }
// *****************************************************************************
// CPU constants that should be exposed to the eLua "cpu" module
Modified: branches/eagle_mmc/src/platform/lm3s/pwm.c
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/pwm.c 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lm3s/pwm.c 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,1697 +1,1728 @@
-//*****************************************************************************
-//
-// pwm.c - API for the PWM modules
-//
-// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
-// Software License Agreement
-//
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
-//
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws. All rights are reserved. You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program. Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
-//
-// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-//
-// This is part of revision 3740 of the Stellaris Peripheral Driver Library.
-//
-//*****************************************************************************
-
-//*****************************************************************************
-//
-//! \addtogroup pwm_api
-//! @{
-//
-//*****************************************************************************
-
-#include "hw_ints.h"
-#include "hw_memmap.h"
-#include "hw_pwm.h"
-#include "hw_sysctl.h"
-#include "hw_types.h"
-#include "debug.h"
-#include "interrupt.h"
-#include "pwm.h"
-
-//*****************************************************************************
-//
-// Misc macros for manipulating the encoded generator and output defines used
-// by the API.
-//
-//*****************************************************************************
-#define PWM_GEN_BADDR(_mod_, _gen_) \
- ((_mod_) + (_gen_))
-#define PWM_GEN_EXT_BADDR(_mod_, _gen_) \
- ((_mod_) + PWM_GEN_EXT_0 + \
- ((_gen_) - PWM_GEN_0) * 2)
-#define PWM_OUT_BADDR(_mod_, _out_) \
- ((_mod_) + ((_out_) & 0xFFFFFFC0))
-#define PWM_IS_OUTPUT_ODD(_out_) \
- ((_out_) & 0x00000001)
-
-//*****************************************************************************
-//
-//! \internal
-//! Checks a PWM generator number.
-//!
-//! \param ulGen is the generator number.
-//!
-//! This function determines if a PWM generator number is valid.
-//!
-//! \return Returnes \b true if the generator number is valid and \b false
-//! otherwise.
-//
-//*****************************************************************************
-#ifdef DEBUG
-static tBoolean
-PWMGenValid(unsigned long ulGen)
-{
- return((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) ||
- (ulGen == PWM_GEN_2) || (ulGen == PWM_GEN_3));
-}
-#endif
-
-//*****************************************************************************
-//
-//! \internal
-//! Checks a PWM output number.
-//!
-//! \param ulPWMOut is the output number.
-//!
-//! This function determines if a PWM output number is valid.
-//!
-//! \return Returns \b true if the output number is valid and \b false
-//! otherwise.
-//
-//*****************************************************************************
-#ifdef DEBUG
-static tBoolean
-PWMOutValid(unsigned long ulPWMOut)
-{
- return((ulPWMOut == PWM_OUT_0) || (ulPWMOut == PWM_OUT_1) ||
- (ulPWMOut == PWM_OUT_2) || (ulPWMOut == PWM_OUT_3) ||
- (ulPWMOut == PWM_OUT_4) || (ulPWMOut == PWM_OUT_5) ||
- (ulPWMOut == PWM_OUT_6) || (ulPWMOut == PWM_OUT_7));
-}
-#endif
-
-//*****************************************************************************
-//
-//! Configures a PWM generator.
-//!
-//! \param ulBase is the base address of the PWM module.
-//! \param ulGen is the PWM generator to configure. Must be one of
-//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
-//! \param ulConfig is the configuration for the PWM generator.
-//!
-//! This function is used to set the mode of operation for a PWM generator.
-//! The counting mode, synchronization mode, and debug behavior are all
-//! configured. After configuration, the generator is left in the disabled
-//! state.
-//!
-//! A PWM generator can count in two different modes: count down mode or count
-//! up/down mode. In count down mode, it will count from a value down to zero,
-//! and then reset to the preset value. This will produce left-aligned PWM
-//! signals (that is the rising edge of the two PWM signals produced by the
-//! generator will occur at the same time). In count up/down mode, it will
-//! count up from zero to the preset value, count back down to zero, and then
-//! repeat the process. This will produce center-aligned PWM signals (that is,
-//! the middle of the high/low period of the PWM signals produced by the
-//! generator will occur at the same time).
-//!
-//! When the PWM generator parameters (period and pulse width) are modified,
-//! their affect on the output PWM signals can be delayed. In synchronous
-//! mode, the parameter updates are not applied until a synchronization event
-//! occurs. This allows multiple parameters to be modified and take affect
-//! simultaneously, instead of one at a time. Additionally, parameters to
-//! multiple PWM generators in synchronous mode can be updated simultaneously,
-//! allowing them to be treated as if they were a unified generator. In
-//! non-synchronous mode, the parameter updates are not delayed until a
-//! synchronization event. In either mode, the parameter updates only occur
-//! when the counter is at zero to help prevent oddly formed PWM signals during
-//! the update (that is, a PWM pulse that is too short or too long).
-//!
-//! The PWM generator can either pause or continue running when the processor
-//! is stopped via the debugger. If configured to pause, it will continue to
-//! count until it reaches zero, at which point it will pause until the
-//! processor is restarted. If configured to continue running, it will keep
-//! counting as if nothing had happened.
-//!
-//! The \e ulConfig parameter contains the desired configuration. It is the
-//! logical OR of the following:
-//!
-//! - \b PWM_GEN_MODE_DOWN or \b PWM_GEN_MODE_UP_DOWN to specify the counting
-//! mode
-//! - \b PWM_GEN_MODE_SYNC or \b PWM_GEN_MODE_NO_SYNC to specify the counter
-//! load and comparator update synchronization mode
-//! - \b PWM_GEN_MODE_DBG_RUN or \b PWM_GEN_MODE_DBG_STOP to specify the debug
-//! behavior
-//! - \b PWM_GEN_MODE_GEN_NO_SYNC, \b PWM_GEN_MODE_GEN_SYNC_LOCAL, or
-//! \b PWM_GEN_MODE_GEN_SYNC_GLOBAL to specify the update synchronization
-//! mode for generator counting mode changes
-//! - \b PWM_GEN_MODE_DB_NO_SYNC, \b PWM_GEN_MODE_DB_SYNC_LOCAL, or
-//! \b PWM_GEN_MODE_DB_SYNC_GLOBAL to specify the deadband parameter
-//! synchronization mode
-//! - \b PWM_GEN_MODE_FAULT_LATCHED or \b PWM_GEN_MODE_FAULT_UNLATCHED to
-//! specify whether fault conditions are latched or not
-//! - \b PWM_GEN_MODE_FAULT_MINPER or \b PWM_GEN_MODE_FAULT_NO_MINPER to
-//! specify whether minimum fault period support is required
-//! - \b PWM_GEN_MODE_FAULT_EXT or \b PWM_GEN_MODE_FAULT_LEGACY to specify
-//! whether extended fault source selection support is enabled or not
-//!
-//! Setting \b PWM_GEN_MODE_FAULT_MINPER allows an application to set the
-//! minimum duration of a PWM fault signal. Fault will be signaled for at
-//! least this time even if the external fault pin deasserts earlier. Care
-//! should be taken when using this mode since during the fault signal period,
-//! the fault interrupt from the PWM generator will remain asserted. The fault
-//! interrupt handler may, therefore, reenter immediately if it exits prior to
-//! expiration of the fault timer.
-//!
-//! \note Changes to the counter mode will affect the period of the PWM signals
-//! produced. PWMGenPeriodSet() and PWMPulseWidthSet() should be called after
-//! any changes to the counter mode of a generator.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-PWMGenConfigure(unsigned long ulBase, unsigned long ulGen,
- unsigned long ulConfig)
-{
- //
- // Check the arguments.
- //
- ASSERT(ulBase == PWM_BASE);
- ASSERT(PWMGenValid(ulGen));
-
- //
- // Compute the generator's base address.
- //
- ulGen = PWM_GEN_BADDR(ulBase, ulGen);
-
- //
- // Change the global configuration of the generator.
- //
- HWREG(ulGen + PWM_O_X_CTL) = ((HWREG(ulGen + PWM_O_X_CTL) &
- ~(PWM_X_CTL_MODE | PWM_X_CTL_DEBUG |
- PWM_X_CTL_LATCH | PWM_X_CTL_MINFLTPER |
- PWM_X_CTL_FLTSRC | PWM_X_CTL_DBFALLUPD_M |
- PWM_X_CTL_DBRISEUPD_M |
- PWM_X_CTL_DBCTLUPD_M |
- PWM_X_CTL_GENBUPD_M |
- PWM_X_CTL_GENAUPD_M |
- PWM_X_CTL_LOADUPD | PWM_X_CTL_CMPAUPD |
- PWM_X_CTL_CMPBUPD)) | ulConfig);
-
- //
- // Set the individual PWM generator controls.
- //
- if(ulConfig & PWM_X_CTL_MODE)
- {
- //
- // In up/down count mode, set the signal high on up count comparison
- // and low on down count comparison (that is, center align the
- // signals).
- //
- HWREG(ulGen + PWM_O_X_GENA) = (PWM_X_GENA_ACTCMPAU_ONE |
- PWM_X_GENA_ACTCMPAD_ZERO);
- HWREG(ulGen + PWM_O_X_GENB) = (PWM_X_GENB_ACTCMPBU_ONE |
- PWM_X_GENB_ACTCMPBD_ZERO);
- }
- else
- {
- //
- // In down count mode, set the signal high on load and low on count
- // comparison (that is, left align the signals).
- //
- HWREG(ulGen + PWM_O_X_GENA) = (PWM_X_GENA_ACTLOAD_ONE |
- PWM_X_GENA_ACTCMPAD_ZERO);
- HWREG(ulGen + PWM_O_X_GENB) = (PWM_X_GENB_ACTLOAD_ONE |
- PWM_X_GENB_ACTCMPBD_ZERO);
- }
-}
-
-//*****************************************************************************
-//
-//! Set the period of a PWM generator.
-//!
-//! \param ulBase is the base address of the PWM module.
-//! \param ulGen is the PWM generator to be modified. Must be one of
-//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
-//! \param ulPeriod specifies the period of PWM generator output, measured
-//! in clock ticks.
-//!
-//! This function sets the period of the specified PWM generator block, where
-//! the period of the generator block is defined as the number of PWM clock
-//! ticks between pulses on the generator block zero signal.
-//!
-//! \note Any subsequent calls made to this function before an update occurs
-//! will cause the previous values to be overwritten.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen,
- unsigned long ulPeriod)
-{
- //
- // Check the arguments.
- //
- ASSERT(ulBase == PWM_BASE);
- ASSERT(PWMGenValid(ulGen));
-
- //
- // Compute the generator's base address.
- //
- ulGen = PWM_GEN_BADDR(ulBase, ulGen);
-
- //
- // Set the reload register based on the mode.
- //
- if(HWREG(ulGen + PWM_O_X_CTL) & PWM_X_CTL_MODE)
- {
- //
- // In up/down count mode, set the reload register to half the requested
- // period.
- //
- ASSERT((ulPeriod / 2) < 65536);
- HWREG(ulGen + PWM_O_X_LOAD) = ulPeriod / 2;
- }
- else
- {
- //
- // In down count mode, set the reload register to the requested period
- // minus one.
- //
- ASSERT((ulPeriod <= 65536) && (ulPeriod != 0));
- HWREG(ulGen + PWM_O_X_LOAD) = ulPeriod - 1;
- }
-}
-
-//*****************************************************************************
-//
-//! Gets the period of a PWM generator block.
-//!
-//! \param ulBase is the base address of the PWM module.
-//! \param ulGen is the PWM generator to query. Must be one of
-//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
-//!
-//! This function gets the period of the specified PWM generator block. The
-//! period of the generator block is defined as the number of PWM clock ticks
-//! between pulses on the generator block zero signal.
-//!
-//! If the update of the counter for the specified PWM generator has yet
-//! to be completed, the value returned may not be the active period. The
-//! value returned is the programmed period, measured in PWM clock ticks.
-//!
-//! \return Returns the programmed period of the specified generator block
-//! in PWM clock ticks.
-//
-//*****************************************************************************
-unsigned long
-PWMGenPeriodGet(unsigned long ulBase, unsigned long ulGen)
-{
- //
- // Check the arguments.
- //
- ASSERT(ulBase == PWM_BASE);
- ASSERT(PWMGenValid(ulGen));
-
- //
- // Compute the generator's base address.
- //
- ulGen = PWM_GEN_BADDR(ulBase, ulGen);
-
- //
- // Figure out the counter mode.
- //
- if(HWREG(ulGen + PWM_O_X_CTL) & PWM_X_CTL_MODE)
- {
- //
- // The period is twice the reload register value.
- //
- return(HWREG(ulGen + PWM_O_X_LOAD) * 2);
- }
- else
- {
- //
- // The period is the reload register value plus one.
- //
- return(HWREG(ulGen + PWM_O_X_LOAD) + 1);
- }
-}
-
-//*****************************************************************************
-//
-//! Enables the timer/counter for a PWM generator block.
-//!
-//! \param ulBase is the base address of the PWM module.
-//! \param ulGen is the PWM generator to be enabled. Must be one of
-//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
-//!
-//! This function allows the PWM clock to drive the timer/counter for the
-//! specified generator block.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-PWMGenEnable(unsigned long ulBase, unsigned long ulGen)
-{
- //
- // Check the arguments.
- //
- ASSERT(ulBase == PWM_BASE);
- ASSERT(PWMGenValid(ulGen));
-
- //
- // Enable the PWM generator.
- //
- HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_CTL) |= PWM_X_CTL_ENABLE;
-}
-
-//*****************************************************************************
-//
-//! Disables the timer/counter for a PWM generator block.
-//!
-//! \param ulBase is the base address of the PWM module.
-//! \param ulGen is the PWM generator to be disabled. Must be one of
-//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
-//!
-//! This function blocks the PWM clock from driving the timer/counter for the
-//! specified generator block.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-PWMGenDisable(unsigned long ulBase, unsigned long ulGen)
-{
- //
- // Check the arguments.
- //
- ASSERT(ulBase == PWM_BASE);
- ASSERT(PWMGenValid(ulGen));
-
- //
- // Disable the PWM generator.
- //
- HWREG(PWM_GEN_BADDR(ulBase, + ulGen) + PWM_O_X_CTL) &= ~(PWM_X_CTL_ENABLE);
-}
-
-//*****************************************************************************
-//
-//! Sets the pulse width for the specified PWM output.
-//!
-//! \param ulBase is the base address of the PWM module.
-//! \param ulPWMOut is the PWM output to modify. Must be one of \b PWM_OUT_0,
-//! \b PWM_OUT_1, \b PWM_OUT_2, \b PWM_OUT_3, \b PWM_OUT_4, \b PWM_OUT_5,
-//! \b PWM_OUT_6, or \b PWM_OUT_7.
-//! \param ulWidth specifies the width of the positive portion of the pulse.
-//!
-//! This function sets the pulse width for the specified PWM output, where the
-//! pulse width is defined as the number of PWM clock ticks.
-//!
-//! \note Any subsequent calls made to this function before an update occurs
-//! will cause the previous values to be overwritten.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut,
- unsigned long ulWidth)
-{
- unsigned long ulGenBase, ulReg;
-
- //
- // Check the arguments.
- //
- ASSERT(ulBase == PWM_BASE);
- ASSERT(PWMOutValid(ulPWMOut));
-
- //
- // Compute the generator's base address.
- //
- ulGenBase = PWM_OUT_BADDR(ulBase, ulPWMOut);
-
- //
- // If the counter is in up/down count mode, divide the width by two.
- //
- if(HWREG(ulGenBase + PWM_O_X_CTL) & PWM_X_CTL_MODE)
- {
- ulWidth /= 2;
- }
-
- //
- // Get the period.
- //
- ulReg = HWREG(ulGenBase + PWM_O_X_LOAD);
-
- //
- // Make sure the width is not too large.
- //
- ASSERT(ulWidth < ulReg);
-
- //
- // Compute the compare value.
- //
- ulReg = ulReg - ulWidth;
-
- //
- // Write to the appropriate registers.
- //
- if(PWM_IS_OUTPUT_ODD(ulPWMOut))
- {
- HWREG(ulGenBase + PWM_O_X_CMPB) = ulReg;
- }
- else
- {
- HWREG(ulGenBase + PWM_O_X_CMPA) = ulReg;
- }
-}
-
-//*****************************************************************************
-//
-//! Gets the pulse width of a PWM output.
-//!
-//! \param ulBase is the base address of the PWM module.
-//! \param ulPWMOut is the PWM output to query. Must be one of \b PWM_OUT_0,
-//! \b PWM_OUT_1, \b PWM_OUT_2, \b PWM_OUT_3, \b PWM_OUT_4, \b PWM_OUT_5,
-//! \b PWM_OUT_6, or \b PWM_OUT_7.
-//!
-//! This function gets the currently programmed pulse width for the specified
-//! PWM output. If the update of the comparator for the specified output has
-//! yet to be completed, the value returned may not be the active pulse width.
-//! The value returned is the programmed pulse width, measured in PWM clock
-//! ticks.
-//!
-//! \return Returns the width of the pulse in PWM clock ticks.
-//
-//*****************************************************************************
-unsigned long
-PWMPulseWidthGet(unsigned long ulBase, unsigned long ulPWMOut)
-{
- unsigned long ulGenBase, ulReg, ulLoad;
-
- //
- // Check the arguments.
- //
- ASSERT(ulBase == PWM_BASE);
- ASSERT(PWMOutValid(ulPWMOut));
-
- //
- // Compute the generator's base address.
- //
- ulGenBase = PWM_OUT_BADDR(ulBase, ulPWMOut);
-
- //
- // Then compute the pulse width. If mode is UpDown, set
- // width = (load - compare) * 2. Otherwise, set width = load - compare.
- //
- ulLoad = HWREG(ulGenBase + PWM_O_X_LOAD);
- if(PWM_IS_OUTPUT_ODD(ulPWMOut))
- {
- ulReg = HWREG(ulGenBase + PWM_O_X_CMPB);
- }
- else
- {
- ulReg = HWREG(ulGenBase + PWM_O_X_CMPA);
- }
- ulReg = ulLoad - ulReg;
-
- //
- // If in up/down count mode, double the pulse width.
- //
- if(HWREG(ulGenBase + PWM_O_X_CTL) & PWM_X_CTL_MODE)
- {
- ulReg = ulReg * 2;
- }
-
- //
- // Return the pulse width.
- //
- return(ulReg);
-}
-
-//*****************************************************************************
-//
-//! Enables the PWM dead band output, and sets the dead band delays.
-//!
-//! \param ulBase is the base address of the PWM module.
-//! \param ulGen is the PWM generator to modify. Must be one of
-//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
-//! \param usRise specifies the width of delay from the rising edge.
-//! \param usFall specifies the width of delay from the falling edge.
-//!
-//! This function sets the dead bands for the specified PWM generator,
-//! where the dead bands are defined as the number of \b PWM clock ticks
-//! from the rising or falling edge of the generator's \b OutA signal.
-//! Note that this function causes the coupling of \b OutB to \b OutA.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen,
- unsigned short usRise, unsigned short usFall)
-{
- //
- // Check the arguments.
- //
- ASSERT(ulBase == PWM_BASE);
- ASSERT(PWMGenValid(ulGen));
- ASSERT(usRise < 4096);
- ASSERT(usFall < 4096);
-
- //
- // Compute the generator's base address.
- //
- ulGen = PWM_GEN_BADDR(ulBase, ulGen);
-
- //
- // Write the dead band delay values.
- //
- HWREG(ulGen + PWM_O_X_DBRISE) = usRise;
- HWREG(ulGen + PWM_O_X_DBFALL) = usFall;
-
- //
- // Enable the deadband functionality.
- //
- HWREG(ulGen + PWM_O_X_DBCTL) |= PWM_X_DBCTL_ENABLE;
-}
-
-//*****************************************************************************
-//
-//! Disables the PWM dead band output.
-//!
-//! \param ulBase is the base address of the PWM module.
-//! \param ulGen is the PWM generator to modify. Must be one of
-//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
-//!
-//! This function disables the dead band mode for the specified PWM generator.
-//! Doing so decouples the \b OutA and \b OutB signals.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen)
-{
- //
- // Check the arguments.
- //
- ASSERT(ulBase == PWM_BASE);
- ASSERT(PWMGenValid(ulGen));
-
- //
- // Disable the deadband functionality.
- //
- HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_DBCTL) &=
- ~(PWM_X_DBCTL_ENABLE);
-}
-
-//*****************************************************************************
-//
-//! Synchronizes all pending updates.
-//!
-//! \param ulBase is the base address of the PWM module.
-//! \param ulGenBits are the PWM generator blocks to be updated. Must be the
-//! logical OR of any of \b PWM_GEN_0_BIT, \b PWM_GEN_1_BIT,
-//! \b PWM_GEN_2_BIT, or \b PWM_GEN_3_BIT.
-//!
-//! For the selected PWM generators, this function causes all queued updates to
-//! the period or pulse width to be applied the next time the corresponding
-//! counter becomes zero.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits)
-{
- //
- // Check the arguments.
- //
- ASSERT(ulBase == PWM_BASE);
- ASSERT(!(ulGenBits & ~(PWM_GEN_0_BIT | PWM_GEN_1_BIT | PWM_GEN_2_BIT |
- PWM_GEN_3_BIT)));
-
- //
- // Synchronize pending PWM register changes.
- //
- HWREG(ulBase + PWM_O_CTL) = ulGenBits;
-}
-
-//*****************************************************************************
-//
-//! Synchronizes the counters in one or multiple PWM generator blocks.
-//!
-//! \param ulBase is the base address of the PWM module.
-//! \param ulGenBits are the PWM generator blocks to be synchronized. Must be
-//! the logical OR of any of \b PWM_GEN_0_BIT, \b PWM_GEN_1_BIT,
-//! \b PWM_GEN_2_BIT, or \b PWM_GEN_3_BIT.
-//!
-//! For the selected PWM module, this function synchronizes the time base
-//! of the generator blocks by causing the specified generator counters to be
-//! reset to zero.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits)
-{
- //
- // Check the arguments.
- //
- ASSERT(ulBase == PWM_BASE);
- ASSERT(!(ulGenBits & ~(PWM_GEN_0_BIT | PWM_GEN_1_BIT | PWM_GEN_2_BIT |
- PWM_GEN_3_BIT)));
-
- //
- // Synchronize the counters in the specified generators by writing to the
- // module's synchronization register.
- //
- HWREG(ulBase + PWM_O_SYNC) = ulGenBits;
-}
-
-//*****************************************************************************
-//
-//! Enables or disables PWM outputs.
-//!
-//! \param ulBase is the base address of the PWM module.
-//! \param ulPWMOutBits are the PWM outputs to be modified. Must be the
-//! logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, \b PWM_OUT_2_BIT,
-//! \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, \b PWM_OUT_5_BIT, \b PWM_OUT_6_BIT,
-//! or \b PWM_OUT_7_BIT.
-//! \param bEnable determines if the signal is enabled or disabled.
-//!
-//! This function is used to enable or disable the selected PWM outputs. The
-//! outputs are selected using the parameter \e ulPWMOutBits. The parameter
-//! \e bEnable determines the state of the selected outputs. If \e bEnable is
-//! \b true, then the selected PWM outputs are enabled, or placed in the active
-//! state. If \e bEnable is \b false, then the selected outputs are disabled,
-//! or placed in the inactive state.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits,
- tBoolean bEnable)
-{
- //
- // Check the arguments.
- //
- ASSERT(ulBase == PWM_BASE);
- ASSERT(!(ulPWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT |
- PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT |
- PWM_OUT_6_BIT | PWM_OUT_7_BIT)));
-
- //
- // Read the module's ENABLE output control register, and set or clear the
- // requested bits.
- //
- if(bEnable == true)
- {
- HWREG(ulBase + PWM_O_ENABLE) |= ulPWMOutBits;
- }
- else
- {
- HWREG(ulBase + PWM_O_ENABLE) &= ~(ulPWMOutBits);
- }
-}
-
-//*****************************************************************************
-//
-//! Selects the inversion mode for PWM outputs.
-//!
-//! \param ulBase is the base address of the PWM module.
-//! \param ulPWMOutBits are the PWM outputs to be modified. Must be the
-//! logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, \b PWM_OUT_2_BIT,
-//! \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, \b PWM_OUT_5_BIT, \b PWM_OUT_6_BIT, or
-//! \b PWM_OUT_7_BIT.
-//! \param bInvert determines if the signal is inverted or passed through.
-//!
-//! This function is used to select the inversion mode for the selected PWM
-//! outputs. The outputs are selected using the parameter \e ulPWMOutBits.
-//! The parameter \e bInvert determines the inversion mode for the selected
-//! outputs. If \e bInvert is \b true, this function will cause the specified
-//! PWM output signals to be inverted, or made active low. If \e bInvert is
-//! \b false, the specified output will be passed through as is, or be made
-//! active high.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits,
- tBoolean bInvert)
-{
- //
- // Check the arguments.
- //
- ASSERT(ulBase == PWM_BASE);
- ASSERT(!(ulPWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT |
- PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT |
- PWM_OUT_6_BIT | PWM_OUT_7_BIT)));
-
- //
- // Read the module's INVERT output control register, and set or clear the
- // requested bits.
- //
- if(bInvert == true)
- {
- HWREG(ulBase + PWM_O_INVERT) |= ulPWMOutBits;
- }
- else
- {
- HWREG(ulBase + PWM_O_INVERT) &= ~(ulPWMOutBits);
- }
-}
-
-//*****************************************************************************
-//
-//! Specifies the level of PWM outputs suppressed in response to a fault
-//! condition.
-//!
-//! \param ulBase is the base address of the PWM module.
-//! \param ulPWMOutBits are the PWM outputs to be modified. Must be the
-//! logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, \b PWM_OUT_2_BIT,
-//! \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, \b PWM_OUT_5_BIT, \b PWM_OUT_6_BIT, or
-//! \b PWM_OUT_7_BIT.
-//! \param bDriveHigh determines if the signal is driven high or low during an
-//! active fault condition.
-//!
-//! This function determines whether a PWM output pin that is suppressed in
-//! response to a fault condition will be driven high or low. The affected
-//! outputs are selected using the parameter \e ulPWMOutBits. The parameter
-//! \e bDriveHigh determines the output level for the pins identified by
-//! \e ulPWMOutBits. If \e bDriveHigh is \b true then the selected outputs
-//! will be driven high when a fault is detected. If it is \e false, the pins
-//! will be driven low.
-//!
-//! In a fault condition, pins which have not been configured to be suppressed
-//! via a call to PWMOutputFault() are unaffected by this function.
-//!
-//! \note This function is available only on devices which support extended
-//! PWM fault handling.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-PWMOutputFaultLevel(unsigned long ulBase, unsigned long ulPWMOutBits,
- tBoolean bDriveHigh)
-{
- //
- // Check the arguments.
- //
- ASSERT(HWREG(SYSCTL_DC5) & SYSCTL_DC5_PWMEFLT);
- ASSERT(ulBase == PWM_BASE);
- ASSERT(!(ulPWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT |
- PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT |
- PWM_OUT_6_BIT | PWM_OUT_7_BIT)));
-
- //
- // Read the module's FAULT output control register, and set or clear the
- // requested bits.
- //
- if(bDriveHigh == true)
- {
- HWREG(ulBase + PWM_O_FAULTVAL) |= ulPWMOutBits;
- }
- else
- {
- HWREG(ulBase + PWM_O_FAULTVAL) &= ~(ulPWMOutBits);
- }
-}
-
-//*****************************************************************************
-//
-//! Specifies the state of PWM outputs in response to a fault condition.
-//!
-//! \param ulBase is the base address of the PWM module.
-//! \param ulPWMOutBits are the PWM outputs to be modified. Must be the
-//! logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, \b PWM_OUT_2_BIT,
-//! \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, \b PWM_OUT_5_BIT, \b PWM_OUT_6_BIT, or
-//! \b PWM_OUT_7_BIT.
-//! \param bFaultSuppress determines if the signal is suppressed or passed
-//! through during an active fault condition.
-//!
-//! This function sets the fault handling characteristics of the selected PWM
-//! outputs. The outputs are selected using the parameter \e ulPWMOutBits.
-//! The parameter \e bFaultSuppress determines the fault handling
-//! characteristics for the selected outputs. If \e bFaultSuppress is \b true,
-//! then the selected outputs will be made inactive. If \e bFaultSuppress is
-//! \b false, then the selected outputs are unaffected by the detected fault.
-//!
-//! On devices supporting extended PWM fault handling, the state the affected
-//! output pins are driven to can be configured with PWMOutputFaultLevel(). If
-//! not configured, or if the device does not support extended PWM fault
-//! handling, affected outputs will be driven low on a fault condition.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits,
- tBoolean bFaultSuppress)
-{
- //
- // Check the arguments.
- //
- ASSERT(ulBase == PWM_BASE);
- ASSERT(!(ulPWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT |
- PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT |
- PWM_OUT_6_BIT | PWM_OUT_7_BIT)));
-
- //
- // Read the module's FAULT output control register, and set or clear the
- // requested bits.
- //
- if(bFaultSuppress == true)
- {
- HWREG(ulBase + PWM_O_FAULT) |= ulPWMOutBits;
- }
- else
- {
- HWREG(ulBase + PWM_O_FAULT) &= ~(ulPWMOutBits);
- }
-}
-
-//*****************************************************************************
-//
-//! Registers an interrupt handler for the specified PWM generator block.
-//!
-//! \param ulBase is the base address of the PWM module.
-//! \param ulGen is the PWM generator in question. Must be one of
-//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
-//! \param pfnIntHandler is a pointer to the function to be called when the PWM
-//! generator interrupt occurs.
-//!
-//! This function will ensure that the interrupt handler specified by
-//! \e pfnIntHandler is called when an interrupt is detected for the specified
-//! PWM generator block. This function will also enable the corresponding
-//! PWM generator interrupt in the interrupt controller; individual generator
-//! interrupts and interrupt sources must be enabled with PWMIntEnable() and
-//! PWMGenIntTrigEnable().
-//!
-//! \sa IntRegister() for important information about registering interrupt
-//! handlers.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen,
- void (*pfnIntHandler)(void))
-{
- unsigned long ulInt;
-
- //
- // Check the arguments.
- //
- ASSERT(ulBase == PWM_BASE);
- ASSERT(PWMGenValid(ulGen));
-
- //
- // Get the interrupt number associated with the specified generator.
- //
- if(ulGen == PWM_GEN_3)
- {
- ulInt = INT_PWM3;
- }
- else
- {
- ulInt = INT_PWM0 + (ulGen >> 6) - 1;
- }
-
- //
- // Register the interrupt handler.
- //
- IntRegister(ulInt, pfnIntHandler);
-
- //
- // Enable the PWMx interrupt.
- //
- IntEnable(ulInt);
-}
-
-//*****************************************************************************
-//
-//! Removes an interrupt handler for the specified PWM generator block.
-//!
-//! \param ulBase is the base address of the PWM module.
-//! \param ulGen is the PWM generator in question. Must be one of
-//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
-//!
-//! This function will unregister the interrupt handler for the specified
-//! PWM generator block. This function will also disable the corresponding
-//! PWM generator interrupt in the interrupt controller; individual generator
-//! interrupts and interrupt sources must be disabled with PWMIntDisable() and
-//! PWMGenIntTrigDisable().
-//!
-//! \sa IntRegister() for important information about registering interrupt
-//! handlers.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen)
-{
- unsigned long ulInt;
-
- //
- // Check the arguments.
- //
- ASSERT(ulBase == PWM_BASE);
- ASSERT(PWMGenValid(ulGen));
-
- //
- // Get the interrupt number associated with the specified generator.
- //
- if(ulGen == PWM_GEN_3)
- {
- ulInt = INT_PWM3;
- }
- else
- {
- ulInt = INT_PWM0 + (ulGen >> 6) - 1;
- }
-
- //
- // Disable the PWMx interrupt.
- //
- IntDisable(ulInt);
-
- //
- // Unregister the interrupt handler.
- //
- IntUnregister(ulInt);
-}
-
-//*****************************************************************************
-//
-//! Registers an interrupt handler for a fault condition detected in a PWM
-//! module.
-//!
-//! \param ulBase is the base address of the PWM module.
-//! \param pfnIntHandler is a pointer to the function to be called when the PWM
-//! fault interrupt occurs.
-//!
-//! This function will ensure that the interrupt handler specified by
-//! \e pfnIntHandler is called when a fault interrupt is detected for the
-//! selected PWM module. This function will also enable the PWM fault
-//! interrupt in the NVIC; the PWM fault interrupt must also be enabled at the
-//! module level using PWMIntEnable().
-//!
-//! \sa IntRegister() for important information about registering interrupt
-//! handlers.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-PWMFaultIntRegister(unsigned long ulBase, void (*pfnIntHandler)(void))
-{
- //
- // Check the arguments.
- //
- ASSERT(ulBase == PWM_BASE);
-
- //
- // Register the interrupt handler, returning an error if one occurs.
- //
- IntRegister(INT_PWM_FAULT, pfnIntHandler);
-
- //
- // Enable the PWM fault interrupt.
- //
- IntEnable(INT_PWM_FAULT);
-}
-
-//*****************************************************************************
-//
-//! Removes the PWM fault condition interrupt handler.
-//!
-//! \param ulBase is the base address of the PWM module.
-//!
-//! This function will remove the interrupt handler for a PWM fault interrupt
-//! from the selected PWM module. This function will also disable the PWM
-//! fault interrupt in the NVIC; the PWM fault interrupt must also be disabled
-//! at the module level using PWMIntDisable().
-//!
-//! \sa IntRegister() for important information about registering interrupt
-//! handlers.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-PWMFaultIntUnregister(unsigned long ulBase)
-{
- //
- // Check the arguments.
- //
- ASSERT(ulBase == PWM_BASE);
-
- //
- // Disable the PWM fault interrupt.
- //
- IntDisable(INT_PWM_FAULT);
-
- //
- // Unregister the interrupt handler, returning an error if one occurs.
- //
- IntUnregister(INT_PWM_FAULT);
-}
-
-//*****************************************************************************
-//
-//! Enables interrupts and triggers for the specified PWM generator block.
-//!
-//! \param ulBase is the base address of the PWM module.
-//! \param ulGen is the PWM generator to have interrupts and triggers enabled.
-//! Must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
-//! \param ulIntTrig specifies the interrupts and triggers to be enabled.
-//!
-//! Unmasks the specified interrupt(s) and trigger(s) by setting the
-//! specified bits of the interrupt/trigger enable register for the specified
-//! PWM generator. The \e ulIntTrig parameter is the logical OR of
-//! \b PWM_INT_CNT_ZERO, \b PWM_INT_CNT_LOAD, \b PWM_INT_CNT_AU,
-//! \b PWM_INT_CNT_AD, \b PWM_INT_CNT_BU, \b PWM_INT_CNT_BD,
-//! \b PWM_TR_CNT_ZERO, \b PWM_TR_CNT_LOAD, \b PWM_TR_CNT_AU, \b PWM_TR_CNT_AD,
-//! \b PWM_TR_CNT_BU, or \b PWM_TR_CNT_BD.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen,
- unsigned long ulIntTrig)
-{
- //
- // Check the arguments.
- //
- ASSERT(ulBase == PWM_BASE);
- ASSERT(PWMGenValid(ulGen));
- ASSERT((ulIntTrig & ~(PWM_INT_CNT_ZERO | PWM_INT_CNT_LOAD |
- PWM_INT_CNT_AU | PWM_INT_CNT_AD | PWM_INT_CNT_BU |
- PWM_INT_CNT_BD | PWM_TR_CNT_ZERO | PWM_TR_CNT_LOAD |
- PWM_TR_CNT_AU | PWM_TR_CNT_AD | PWM_TR_CNT_BU |
- PWM_TR_CNT_BD)) == 0);
-
- //
- // Enable the specified interrupts/triggers.
- //
- HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_INTEN) |= ulIntTrig;
-}
-
-//*****************************************************************************
-//
-//! Disables interrupts for the specified PWM generator block.
-//!
-//! \param ulBase is the base address of the PWM module.
-//! \param ulGen is the PWM generator to have interrupts and triggers disabled.
-//! Must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
-//! \param ulIntTrig specifies the interrupts and triggers to be disabled.
-//!
-//! Masks the specified interrupt(s) and trigger(s) by clearing the
-//! specified bits of the interrupt/trigger enable register for the specified
-//! PWM generator. The \e ulIntTrig parameter is the logical OR of
-//! \b PWM_INT_CNT_ZERO, \b PWM_INT_CNT_LOAD, \b PWM_INT_CNT_AU,
-//! \b PWM_INT_CNT_AD, \b PWM_INT_CNT_BU, \b PWM_INT_CNT_BD,
-//! \b PWM_TR_CNT_ZERO, \b PWM_TR_CNT_LOAD, \b PWM_TR_CNT_AU, \b PWM_TR_CNT_AD,
-//! \b PWM_TR_CNT_BU, or \b PWM_TR_CNT_BD.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen,
- unsigned long ulIntTrig)
-{
- //
- // Check the arguments.
- //
- ASSERT(ulBase == PWM_BASE);
- ASSERT(PWMGenValid(ulGen));
- ASSERT((ulIntTrig & ~(PWM_INT_CNT_ZERO | PWM_INT_CNT_LOAD |
- PWM_INT_CNT_AU | PWM_INT_CNT_AD | PWM_INT_CNT_BU |
- PWM_INT_CNT_BD | PWM_TR_CNT_ZERO | PWM_TR_CNT_LOAD |
- PWM_TR_CNT_AU | PWM_TR_CNT_AD | PWM_TR_CNT_BU |
- PWM_TR_CNT_BD)) == 0);
-
- //
- // Disable the specified interrupts/triggers.
- //
- HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_INTEN) &= ~(ulIntTrig);
-}
-
-//*****************************************************************************
-//
-//! Gets interrupt status for the specified PWM generator block.
-//!
-//! \param ulBase is the base address of the PWM module.
-//! \param ulGen is the PWM generator to query. Must be one of \b PWM_GEN_0,
-//! \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
-//! \param bMasked specifies whether masked or raw interrupt status is
-//! returned.
-//!
-//! If \e bMasked is set as \b true, then the masked interrupt status is
-//! returned; otherwise, the raw interrupt status will be returned.
-//!
-//! \return Returns the contents of the interrupt status register, or the
-//! contents of the raw interrupt status register, for the specified
-//! PWM generator.
-//
-//*****************************************************************************
-unsigned long
-PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen, tBoolean bMasked)
-{
- //
- // Check the arguments.
- //
- ASSERT(ulBase == PWM_BASE);
- ASSERT(PWMGenValid(ulGen));
-
- //
- // Compute the generator's base address.
- //
- ulGen = PWM_GEN_BADDR(ulBase, ulGen);
-
- //
- // Read and return the specified generator's raw or enabled interrupt
- // status.
- //
- if(bMasked == true)
- {
- return(HWREG(ulGen + PWM_O_X_ISC));
- }
- else
- {
- return(HWREG(ulGen + PWM_O_X_RIS));
- }
-}
-
-//*****************************************************************************
-//
-//! Clears the specified interrupt(s) for the specified PWM generator block.
-//!
-//! \param ulBase is the base address of the PWM module.
-//! \param ulGen is the PWM generator to query. Must be one of \b PWM_GEN_0,
-//! \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
-//! \param ulInts specifies the interrupts to be cleared.
-//!
-//! Clears the specified interrupt(s) by writing a 1 to the specified bits
-//! of the interrupt status register for the specified PWM generator. The
-//! \e ulInts parameter is the logical OR of \b PWM_INT_CNT_ZERO,
-//! \b PWM_INT_CNT_LOAD, \b PWM_INT_CNT_AU, \b PWM_INT_CNT_AD,
-//! \b PWM_INT_CNT_BU, or \b PWM_INT_CNT_BD.
-//!
-//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
-//! several clock cycles before the interrupt source is actually cleared.
-//! Therefore, it is recommended that the interrupt source be cleared early in
-//! the interrupt handler (as opposed to the very last action) to avoid
-//! returning from the interrupt handler before the interrupt source is
-//! actually cleared. Failure to do so may result in the interrupt handler
-//! being immediately reentered (since NVIC still sees the interrupt source
-//! asserted).
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-PWMGenIntClear(unsigned long ulBase, unsigned long ulGen, unsigned long ulInts)
-{
- //
- // Check the arguments.
- //
- ASSERT(ulBase == PWM_BASE);
- ASSERT(PWMGenValid(ulGen));
- ASSERT((ulInts & ~(PWM_INT_CNT_ZERO | PWM_INT_CNT_LOAD | PWM_INT_CNT_AU |
- PWM_INT_CNT_AD | PWM_INT_CNT_BU | PWM_INT_CNT_BD)) ==
- 0);
-
- //
- // Clear the requested interrupts by writing ones to the specified bit
- // of the module's interrupt enable register.
- //
- HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_ISC) = ulInts;
-}
-
-//*****************************************************************************
-//
-//! Enables generator and fault interrupts for a PWM module.
-//!
-//! \param ulBase is the base address of the PWM module.
-//! \param ulGenFault contains the interrupts to be enabled. Must be a logical
-//! OR of any of \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, \b PWM_INT_GEN_2,
-//! \b PWM_INT_GEN_3, \b PWM_INT_FAULT0, \b PWM_INT_FAULT1, \b PWM_INT_FAULT2,
-//! or \b PWM_INT_FAULT3.
-//!
-//! Unmasks the specified interrupt(s) by setting the specified bits of
-//! the interrupt enable register for the selected PWM module.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault)
-{
- //
- // Check the arguments.
- //
- ASSERT(ulBase == PWM_BASE);
- ASSERT((ulGenFault & ~(PWM_INT_GEN_0 | PWM_INT_GEN_1 | PWM_INT_GEN_2 |
- PWM_INT_GEN_3 | PWM_INT_FAULT0 | PWM_INT_FAULT1 |
- PWM_INT_FAULT2 | PWM_INT_FAULT3)) == 0);
-
- //
- // Read the module's interrupt enable register, and enable interrupts
- // for the specified PWM generators.
- //
- HWREG(ulBase + PWM_O_INTEN) |= ulGenFault;
-}
-
-//*****************************************************************************
-//
-//! Disables generator and fault interrupts for a PWM module.
-//!
-//! \param ulBase is the base address of the PWM module.
-//! \param ulGenFault contains the interrupts to be disabled. Must be a
-//! logical OR of any of \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, \b PWM_INT_GEN_2,
-//! \b PWM_INT_GEN_3, \b PWM_INT_FAULT0, \b PWM_INT_FAULT1, \b PWM_INT_FAULT2,
-//! or \b PWM_INT_FAULT3.
-//!
-//! Masks the specified interrupt(s) by clearing the specified bits of
-//! the interrupt enable register for the selected PWM module.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault)
-{
- //
- // Check the arguments.
- //
- ASSERT(ulBase == PWM_BASE);
- ASSERT((ulGenFault & ~(PWM_INT_GEN_0 | PWM_INT_GEN_1 | PWM_INT_GEN_2 |
- PWM_INT_GEN_3 | PWM_INT_FAULT0 | PWM_INT_FAULT1 |
- PWM_INT_FAULT2 | PWM_INT_FAULT3)) == 0);
-
- //
- // Read the module's interrupt enable register, and disable interrupts
- // for the specified PWM generators.
- //
- HWREG(ulBase + PWM_O_INTEN) &= ~(ulGenFault);
-}
-
-//*****************************************************************************
-//
-//! Clears the fault interrupt for a PWM module.
-//!
-//! \param ulBase is the base address of the PWM module.
-//!
-//! Clears the fault interrupt by writing to the appropriate bit of the
-//! interrupt status register for the selected PWM module.
-//!
-//! This function clears only the FAULT0 interrupt and is retained for
-//! backwards compatibility. It is recommended that PWMFaultIntClearExt() be
-//! used instead since it supports all fault interrupts supported on devices
-//! with and without extended PWM fault handling support.
-//!
-//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
-//! several clock cycles before the interrupt source is actually cleared.
-//! Therefore, it is recommended that the interrupt source be cleared early in
-//! the interrupt handler (as opposed to the very last action) to avoid
-//! returning from the interrupt handler before the interrupt source is
-//! actually cleared. Failure to do so may result in the interrupt handler
-//! being immediately reentered (since NVIC still sees the interrupt source
-//! asserted).
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-PWMFaultIntClear(unsigned long ulBase)
-{
- //
- // Check the arguments.
- //
- ASSERT(ulBase == PWM_BASE);
-
- //
- // Write the only writeable bit in the module's interrupt register.
- //
- HWREG(ulBase + PWM_O_ISC) = PWM_ISC_INTFAULT0;
-}
-
-//*****************************************************************************
-//
-//! Gets the interrupt status for a PWM module.
-//!
-//! \param ulBase is the base address of the PWM module.
-//! \param bMasked specifies whether masked or raw interrupt status is
-//! returned.
-//!
-//! If \e bMasked is set as \b true, then the masked interrupt status is
-//! returned; otherwise, the raw interrupt status will be returned.
-//!
-//! \return The current interrupt status, enumerated as a bit field of
-//! \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, \b PWM_INT_GEN_2, \b PWM_INT_GEN_3,
-//! \b PWM_INT_FAULT0, \b PWM_INT_FAULT1, \b PWM_INT_FAULT2, and
-//! \b PWM_INT_FAULT3.
-//!
-//*****************************************************************************
-unsigned long
-PWMIntStatus(unsigned long ulBase, tBoolean bMasked)
-{
- //
- // Check the arguments.
- //
- ASSERT(ulBase == PWM_BASE);
-
- //
- // Read and return either the module's raw or enabled interrupt status.
- //
- if(bMasked == true)
- {
- return(HWREG(ulBase + PWM_O_ISC));
- }
- else
- {
- return(HWREG(ulBase + PWM_O_RIS));
- }
-}
-
-//*****************************************************************************
-//
-//! Clears the fault interrupt for a PWM module.
-//!
-//! \param ulBase is the base address of the PWM module.
-//! \param ulFaultInts specifies the fault interrupts to clear.
-//!
-//! Clears one or more fault interrupts by writing to the appropriate bit of
-//! the PWM interrupt status register. The parameter \e ulFaultInts must be
-//! the logical OR of any of \b PWM_INT_FAULT0, \b PWM_INT_FAULT1,
-//! \b PWM_INT_FAULT2, or \b PWM_INT_FAULT3.
-//!
-//! When running on a device supporting extended PWM fault handling, the fault
-//! interrupts are derived by performing a logical OR of each of the configured
-//! fault trigger signals for a given generator. Therefore, these interrupts
-//! are not directly related to the four possible FAULTn inputs to the device
-//! but indicate that a fault has been signaled to one of the four possible PWM
-//! generators. On a device without extended PWM fault handling, the interrupt
-//! is directly related to the state of the single FAULT pin.
-//!
-//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
-//! several cycles before the interrupt source is actually cleared. Therefore,
-//! it is recommended that the interrupt source be cleared early in the
-//! interrupt handler (as opposed to the very last action) to avoid returning
-//! from the interrupt handler before the interrupt source is actually cleared.
-//! Failure to do so may result in the interrupt handler being immediately
-//! reentered (since NVIC still sees the interrupt source asserted).
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-PWMFaultIntClearExt(unsigned long ulBase, unsigned long ulFaultInts)
-{
- //
- // Check the arguments.
- //
- ASSERT(ulBase == PWM_BASE);
- ASSERT((ulFaultInts & ~(PWM_INT_FAULT0 | PWM_INT_FAULT1 |
- PWM_INT_FAULT2 | PWM_INT_FAULT3)) == 0);
-
- //
- // Clear the supplied fault bits.
- //
- HWREG(ulBase + PWM_O_ISC) = ulFaultInts;
-}
-
-//*****************************************************************************
-//
-//! Configures the minimum fault period and fault pin senses for a given
-//! PWM generator.
-//!
-//! \param ulBase is the base address of the PWM module.
-//! \param ulGen is the PWM generator whose fault configuration is being set.
-//! Must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
-//! \param ulMinFaultPeriod is the minimum fault active period expressed in
-//! PWM clock cycles.
-//! \param ulFaultSenses indicates which sense of each FAULT input should be
-//! considered the ``asserted'' state. Valid values are logical OR
-//! combinations of \b PWM_FAULTn_SENSE_HIGH and \b PWM_FAULTn_SENSE_LOW.
-//!
-//! This function sets the minimum fault period for a given generator along
-//! with the sense of each of the 4 possible fault inputs. The minimum fault
-//! period is expressed in PWM clock cycles and takes effect only if
-//! PWMGenConfigure() is called with flag \b PWM_GEN_MODE_FAULT_PER set in the
-//! \e ulConfig parameter. When a fault input is asserted, the minimum fault
-//! period timer ensures that it remains asserted for at least the number of
-//! clock cycles specified.
-//!
-//! \note This function is only available on devices supporting extended PWM
-//! fault handling.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-PWMGenFaultConfigure(unsigned long ulBase, unsigned long ulGen,
- unsigned long ulMinFaultPeriod,
- unsigned long ulFaultSenses)
-{
- //
- // Check the arguments.
- //
- ASSERT(HWREG(SYSCTL_DC5) & SYSCTL_DC5_PWMEFLT);
- ASSERT(ulBase == PWM_BASE);
- ASSERT(PWMGenValid(ulGen));
- ASSERT(ulMinFaultPeriod < PWM_X_MINFLTPER_M);
- ASSERT((ulFaultSenses & ~(PWM_FAULT0_SENSE_HIGH | PWM_FAULT0_SENSE_LOW |
- PWM_FAULT1_SENSE_HIGH | PWM_FAULT1_SENSE_LOW |
- PWM_FAULT2_SENSE_HIGH | PWM_FAULT2_SENSE_LOW |
- PWM_FAULT3_SENSE_HIGH | PWM_FAULT3_SENSE_LOW)) ==
- 0);
-
- //
- // Write the minimum fault period.
- //
- HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_MINFLTPER) = ulMinFaultPeriod;
-
- //
- // Write the fault senses.
- //
- HWREG(PWM_GEN_EXT_BADDR(ulBase, ulGen) + PWM_O_X_FLTSEN) = ulFaultSenses;
-}
-
-//*****************************************************************************
-//
-//! Configures the set of fault triggers for a given PWM generator.
-//!
-//! \param ulBase is the base address of the PWM module.
-//! \param ulGen is the PWM generator whose fault triggers are being set. Must
-//! be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
-//! \param ulGroup indicates the subset of possible faults that are to be
-//! configured. This must be \b PWM_FAULT_GROUP_0.
-//! \param ulFaultTriggers defines the set of inputs that are to contribute
-//! towards generation of the fault signal to the given PWM generator. For
-//! \b PWM_FAULT_GROUP_0, this will be the logical OR of \b PWM_FAULT_FAULT0,
-//! \b PWM_FAULT_FAULT1, \b PWM_FAULT_FAULT2, or \b PWM_FAULT_FAULT3.
-//!
-//! This function allows selection of the set of fault inputs that will be
-//! combined to generate a fault condition to a given PWM generator. By
-//! default, all generators use only FAULT0 (for backwards compatibility) but
-//! if PWMGenConfigure() is called with flag \b PWM_GEN_MODE_FAULT_SRC in the
-//! \e ulConfig parameter, extended fault handling is enabled and this function
-//! must be called to configure the fault triggers.
-//!
-//! The fault signal to the PWM generator is generated by ORing together each
-//! of the signals whose inputs are specified in the \e ulFaultTriggers
-//! parameter after having adjusted the sense of each FAULTn input based on the
-//! configuration previously set using a call to PWMGenFaultConfigure().
-//!
-//! \note This function is only available on devices supporting extended PWM
-//! fault handling.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-PWMGenFaultTriggerSet(unsigned long ulBase, unsigned long ulGen,
- unsigned long ulGroup, unsigned long ulFaultTriggers)
-{
- //
- // Check for valid parameters.
- //
- ASSERT(HWREG(SYSCTL_DC5) & SYSCTL_DC5_PWMEFLT);
- ASSERT(ulBase == PWM_BASE);
- ASSERT(PWMGenValid(ulGen));
- ASSERT(ulGroup == PWM_FAULT_GROUP_0);
- ASSERT((ulFaultTriggers & ~(PWM_FAULT_FAULT0 | PWM_FAULT_FAULT1 |
- PWM_FAULT_FAULT2 | PWM_FAULT_FAULT3)) == 0);
-
- //
- // Write the fault triggers to the appropriate register.
- //
- HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_FLTSRC0) = ulFaultTriggers;
-}
-
-//*****************************************************************************
-//
-//! Returns the set of fault triggers currently configured for a given PWM
-//! generator.
-//!
-//! \param ulBase is the base address of the PWM module.
-//! \param ulGen is the PWM generator whose fault triggers are being queried.
-//! Must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
-//! \param ulGroup indicates the subset of faults that are being queried. This
-//! must be \b PWM_FAULT_GROUP_0.
-//!
-//! This function allows an application to query the current set of inputs that
-//! contribute towards the generation of a fault condition to a given PWM
-//! generator.
-//!
-//! \note This function is only available on devices supporting extended PWM
-//! fault handling.
-//!
-//! \return Returns the current fault triggers configured for the fault group
-//! provided. For \b PWM_FAULT_GROUP_0, the returned value will be a logical
-//! OR of \b PWM_FAULT_FAULT0, \b PWM_FAULT_FAULT1, \b PWM_FAULT_FAULT2, or
-//! \b PWM_FAULT_FAULT3.
-//
-//*****************************************************************************
-unsigned long
-PWMGenFaultTriggerGet(unsigned long ulBase, unsigned long ulGen,
- unsigned long ulGroup)
-{
- //
- // Check for valid parameters.
- //
- ASSERT(HWREG(SYSCTL_DC5) & SYSCTL_DC5_PWMEFLT);
- ASSERT(ulBase == PWM_BASE);
- ASSERT(PWMGenValid(ulGen));
- ASSERT(ulGroup == PWM_FAULT_GROUP_0);
-
- //
- // Return the current fault triggers.
- //
- return(HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_FLTSRC0));
-}
-
-//*****************************************************************************
-//
-//! Returns the current state of the fault triggers for a given PWM generator.
-//!
-//! \param ulBase is the base address of the PWM module.
-//! \param ulGen is the PWM generator whose fault trigger states are being
-//! queried. Must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or
-//! \b PWM_GEN_3.
-//! \param ulGroup indicates the subset of faults that are being queried. This
-//! must be \b PWM_FAULT_GROUP_0.
-//!
-//! This function allows an application to query the current state of each of
-//! the fault trigger inputs to a given PWM generator. The current state of
-//! each fault trigger input is returned unless PWMGenConfigure() has
-//! previously been called with flag \b PWM_GEN_MODE_LATCH_FAULT in the
-//! \e ulConfig parameter in which case the returned status is the latched
-//! fault trigger status.
-//!
-//! If latched faults are configured, the application must call
-//! PWMGenFaultClear() to clear each trigger.
-//!
-//! \note This function is only available on devices supporting extended PWM
-//! fault handling.
-//!
-//! \return Returns the current state of the fault triggers for the given PWM
-//! generator. A set bit indicates that the associated trigger is active. For
-//! \b PWM_FAULT_GROUP_0, the returned value will be a logical OR of
-//! \b PWM_FAULT_FAULT0, \b PWM_FAULT_FAULT1, \b PWM_FAULT_FAULT2, or
-//! \b PWM_FAULT_FAULT3.
-//
-//*****************************************************************************
-unsigned long
-PWMGenFaultStatus(unsigned long ulBase, unsigned long ulGen,
- unsigned long ulGroup)
-{
- //
- // Check for valid parameters.
- //
- ASSERT(HWREG(SYSCTL_DC5) & SYSCTL_DC5_PWMEFLT);
- ASSERT(ulBase == PWM_BASE);
- ASSERT(PWMGenValid(ulGen));
- ASSERT(ulGroup == PWM_FAULT_GROUP_0);
-
- //
- // Return the current fault status.
- //
- return(HWREG(PWM_GEN_EXT_BADDR(ulBase, ulGen) + PWM_O_X_FLTSTAT0));
-}
-
-//*****************************************************************************
-//
-//! Clears one or more latched fault triggers for a given PWM generator.
-//!
-//! \param ulBase is the base address of the PWM module.
-//! \param ulGen is the PWM generator whose fault trigger states are being
-//! queried. Must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or
-//! \b PWM_GEN_3.
-//! \param ulGroup indicates the subset of faults that are being queried. This
-//! must be \b PWM_FAULT_GROUP_0.
-//! \param ulFaultTriggers is the set of fault triggers which are to be
-//! cleared.
-//!
-//! This function allows an application to clear the fault triggers for a given
-//! PWM generator. This is only required if PWMGenConfigure() has previously
-//! been called with flag \b PWM_GEN_MODE_LATCH_FAULT in parameter \e ulConfig.
-//!
-//! \note This function is only available on devices supporting extended PWM
-//! fault handling.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-PWMGenFaultClear(unsigned long ulBase, unsigned long ulGen,
- unsigned long ulGroup, unsigned long ulFaultTriggers)
-{
- //
- // Check for valid parameters.
- //
- ASSERT(HWREG(SYSCTL_DC5) & SYSCTL_DC5_PWMEFLT);
- ASSERT(ulBase == PWM_BASE);
- ASSERT(PWMGenValid(ulGen));
- ASSERT(ulGroup == PWM_FAULT_GROUP_0);
- ASSERT((ulFaultTriggers & ~(PWM_FAULT_FAULT0 | PWM_FAULT_FAULT1 |
- PWM_FAULT_FAULT2 | PWM_FAULT_FAULT3)) == 0);
-
- //
- // Clear the given faults.
- //
- HWREG(PWM_GEN_EXT_BADDR(ulBase, ulGen) + PWM_O_X_FLTSTAT0) =
- ulFaultTriggers;
-}
-
-//*****************************************************************************
-//
-// Close the Doxygen group.
-//! @}
-//
-//*****************************************************************************
+//*****************************************************************************
+//
+// pwm.c - API for the PWM modules
+//
+// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup pwm_api
+//! @{
+//
+//*****************************************************************************
+
+#include "hw_ints.h"
+#include "hw_memmap.h"
+#include "hw_pwm.h"
+#include "hw_sysctl.h"
+#include "hw_types.h"
+#include "debug.h"
+#include "interrupt.h"
+#include "pwm.h"
+
+//*****************************************************************************
+//
+// Misc macros for manipulating the encoded generator and output defines used
+// by the API.
+//
+//*****************************************************************************
+#define PWM_GEN_BADDR(_mod_, _gen_) \
+ ((_mod_) + (_gen_))
+#define PWM_GEN_EXT_BADDR(_mod_, _gen_) \
+ ((_mod_) + PWM_GEN_EXT_0 + \
+ ((_gen_) - PWM_GEN_0) * 2)
+#define PWM_OUT_BADDR(_mod_, _out_) \
+ ((_mod_) + ((_out_) & 0xFFFFFFC0))
+#define PWM_IS_OUTPUT_ODD(_out_) \
+ ((_out_) & 0x00000001)
+
+//*****************************************************************************
+//
+//! \internal
+//! Checks a PWM generator number.
+//!
+//! \param ulGen is the generator number.
+//!
+//! This function determines if a PWM generator number is valid.
+//!
+//! \return Returnes \b true if the generator number is valid and \b false
+//! otherwise.
+//
+//*****************************************************************************
+#ifdef DEBUG
+static tBoolean
+PWMGenValid(unsigned long ulGen)
+{
+ return((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) ||
+ (ulGen == PWM_GEN_2) || (ulGen == PWM_GEN_3));
+}
+#endif
+
+//*****************************************************************************
+//
+//! \internal
+//! Checks a PWM output number.
+//!
+//! \param ulPWMOut is the output number.
+//!
+//! This function determines if a PWM output number is valid.
+//!
+//! \return Returns \b true if the output number is valid and \b false
+//! otherwise.
+//
+//*****************************************************************************
+#ifdef DEBUG
+static tBoolean
+PWMOutValid(unsigned long ulPWMOut)
+{
+ return((ulPWMOut == PWM_OUT_0) || (ulPWMOut == PWM_OUT_1) ||
+ (ulPWMOut == PWM_OUT_2) || (ulPWMOut == PWM_OUT_3) ||
+ (ulPWMOut == PWM_OUT_4) || (ulPWMOut == PWM_OUT_5) ||
+ (ulPWMOut == PWM_OUT_6) || (ulPWMOut == PWM_OUT_7));
+}
+#endif
+
+//*****************************************************************************
+//
+//! Configures a PWM generator.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGen is the PWM generator to configure. Must be one of
+//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
+//! \param ulConfig is the configuration for the PWM generator.
+//!
+//! This function is used to set the mode of operation for a PWM generator.
+//! The counting mode, synchronization mode, and debug behavior are all
+//! configured. After configuration, the generator is left in the disabled
+//! state.
+//!
+//! A PWM generator can count in two different modes: count down mode or count
+//! up/down mode. In count down mode, it will count from a value down to zero,
+//! and then reset to the preset value. This will produce left-aligned PWM
+//! signals (that is the rising edge of the two PWM signals produced by the
+//! generator will occur at the same time). In count up/down mode, it will
+//! count up from zero to the preset value, count back down to zero, and then
+//! repeat the process. This will produce center-aligned PWM signals (that is,
+//! the middle of the high/low period of the PWM signals produced by the
+//! generator will occur at the same time).
+//!
+//! When the PWM generator parameters (period and pulse width) are modified,
+//! their affect on the output PWM signals can be delayed. In synchronous
+//! mode, the parameter updates are not applied until a synchronization event
+//! occurs. This allows multiple parameters to be modified and take affect
+//! simultaneously, instead of one at a time. Additionally, parameters to
+//! multiple PWM generators in synchronous mode can be updated simultaneously,
+//! allowing them to be treated as if they were a unified generator. In
+//! non-synchronous mode, the parameter updates are not delayed until a
+//! synchronization event. In either mode, the parameter updates only occur
+//! when the counter is at zero to help prevent oddly formed PWM signals during
+//! the update (that is, a PWM pulse that is too short or too long).
+//!
+//! The PWM generator can either pause or continue running when the processor
+//! is stopped via the debugger. If configured to pause, it will continue to
+//! count until it reaches zero, at which point it will pause until the
+//! processor is restarted. If configured to continue running, it will keep
+//! counting as if nothing had happened.
+//!
+//! The \e ulConfig parameter contains the desired configuration. It is the
+//! logical OR of the following:
+//!
+//! - \b PWM_GEN_MODE_DOWN or \b PWM_GEN_MODE_UP_DOWN to specify the counting
+//! mode
+//! - \b PWM_GEN_MODE_SYNC or \b PWM_GEN_MODE_NO_SYNC to specify the counter
+//! load and comparator update synchronization mode
+//! - \b PWM_GEN_MODE_DBG_RUN or \b PWM_GEN_MODE_DBG_STOP to specify the debug
+//! behavior
+//! - \b PWM_GEN_MODE_GEN_NO_SYNC, \b PWM_GEN_MODE_GEN_SYNC_LOCAL, or
+//! \b PWM_GEN_MODE_GEN_SYNC_GLOBAL to specify the update synchronization
+//! mode for generator counting mode changes
+//! - \b PWM_GEN_MODE_DB_NO_SYNC, \b PWM_GEN_MODE_DB_SYNC_LOCAL, or
+//! \b PWM_GEN_MODE_DB_SYNC_GLOBAL to specify the deadband parameter
+//! synchronization mode
+//! - \b PWM_GEN_MODE_FAULT_LATCHED or \b PWM_GEN_MODE_FAULT_UNLATCHED to
+//! specify whether fault conditions are latched or not
+//! - \b PWM_GEN_MODE_FAULT_MINPER or \b PWM_GEN_MODE_FAULT_NO_MINPER to
+//! specify whether minimum fault period support is required
+//! - \b PWM_GEN_MODE_FAULT_EXT or \b PWM_GEN_MODE_FAULT_LEGACY to specify
+//! whether extended fault source selection support is enabled or not
+//!
+//! Setting \b PWM_GEN_MODE_FAULT_MINPER allows an application to set the
+//! minimum duration of a PWM fault signal. Fault will be signaled for at
+//! least this time even if the external fault pin deasserts earlier. Care
+//! should be taken when using this mode since during the fault signal period,
+//! the fault interrupt from the PWM generator will remain asserted. The fault
+//! interrupt handler may, therefore, reenter immediately if it exits prior to
+//! expiration of the fault timer.
+//!
+//! \note Changes to the counter mode will affect the period of the PWM signals
+//! produced. PWMGenPeriodSet() and PWMPulseWidthSet() should be called after
+//! any changes to the counter mode of a generator.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMGenConfigure(unsigned long ulBase, unsigned long ulGen,
+ unsigned long ulConfig)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(PWMGenValid(ulGen));
+
+ //
+ // Compute the generator's base address.
+ //
+ ulGen = PWM_GEN_BADDR(ulBase, ulGen);
+
+ //
+ // Change the global configuration of the generator.
+ //
+ HWREG(ulGen + PWM_O_X_CTL) = ((HWREG(ulGen + PWM_O_X_CTL) &
+ ~(PWM_X_CTL_MODE | PWM_X_CTL_DEBUG |
+ PWM_X_CTL_LATCH | PWM_X_CTL_MINFLTPER |
+ PWM_X_CTL_FLTSRC | PWM_X_CTL_DBFALLUPD_M |
+ PWM_X_CTL_DBRISEUPD_M |
+ PWM_X_CTL_DBCTLUPD_M |
+ PWM_X_CTL_GENBUPD_M |
+ PWM_X_CTL_GENAUPD_M |
+ PWM_X_CTL_LOADUPD | PWM_X_CTL_CMPAUPD |
+ PWM_X_CTL_CMPBUPD)) | ulConfig);
+
+ //
+ // Set the individual PWM generator controls.
+ //
+ if(ulConfig & PWM_X_CTL_MODE)
+ {
+ //
+ // In up/down count mode, set the signal high on up count comparison
+ // and low on down count comparison (that is, center align the
+ // signals).
+ //
+ HWREG(ulGen + PWM_O_X_GENA) = (PWM_X_GENA_ACTCMPAU_ONE |
+ PWM_X_GENA_ACTCMPAD_ZERO);
+ HWREG(ulGen + PWM_O_X_GENB) = (PWM_X_GENB_ACTCMPBU_ONE |
+ PWM_X_GENB_ACTCMPBD_ZERO);
+ }
+ else
+ {
+ //
+ // In down count mode, set the signal high on load and low on count
+ // comparison (that is, left align the signals).
+ //
+ HWREG(ulGen + PWM_O_X_GENA) = (PWM_X_GENA_ACTLOAD_ONE |
+ PWM_X_GENA_ACTCMPAD_ZERO);
+ HWREG(ulGen + PWM_O_X_GENB) = (PWM_X_GENB_ACTLOAD_ONE |
+ PWM_X_GENB_ACTCMPBD_ZERO);
+ }
+}
+
+//*****************************************************************************
+//
+//! Set the period of a PWM generator.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGen is the PWM generator to be modified. Must be one of
+//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
+//! \param ulPeriod specifies the period of PWM generator output, measured
+//! in clock ticks.
+//!
+//! This function sets the period of the specified PWM generator block, where
+//! the period of the generator block is defined as the number of PWM clock
+//! ticks between pulses on the generator block zero signal.
+//!
+//! \note Any subsequent calls made to this function before an update occurs
+//! will cause the previous values to be overwritten.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen,
+ unsigned long ulPeriod)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(PWMGenValid(ulGen));
+
+ //
+ // Compute the generator's base address.
+ //
+ ulGen = PWM_GEN_BADDR(ulBase, ulGen);
+
+ //
+ // Set the reload register based on the mode.
+ //
+ if(HWREG(ulGen + PWM_O_X_CTL) & PWM_X_CTL_MODE)
+ {
+ //
+ // In up/down count mode, set the reload register to half the requested
+ // period.
+ //
+ ASSERT((ulPeriod / 2) < 65536);
+ HWREG(ulGen + PWM_O_X_LOAD) = ulPeriod / 2;
+ }
+ else
+ {
+ //
+ // In down count mode, set the reload register to the requested period
+ // minus one.
+ //
+ ASSERT((ulPeriod <= 65536) && (ulPeriod != 0));
+ HWREG(ulGen + PWM_O_X_LOAD) = ulPeriod - 1;
+ }
+}
+
+//*****************************************************************************
+//
+//! Gets the period of a PWM generator block.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGen is the PWM generator to query. Must be one of
+//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
+//!
+//! This function gets the period of the specified PWM generator block. The
+//! period of the generator block is defined as the number of PWM clock ticks
+//! between pulses on the generator block zero signal.
+//!
+//! If the update of the counter for the specified PWM generator has yet
+//! to be completed, the value returned may not be the active period. The
+//! value returned is the programmed period, measured in PWM clock ticks.
+//!
+//! \return Returns the programmed period of the specified generator block
+//! in PWM clock ticks.
+//
+//*****************************************************************************
+unsigned long
+PWMGenPeriodGet(unsigned long ulBase, unsigned long ulGen)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(PWMGenValid(ulGen));
+
+ //
+ // Compute the generator's base address.
+ //
+ ulGen = PWM_GEN_BADDR(ulBase, ulGen);
+
+ //
+ // Figure out the counter mode.
+ //
+ if(HWREG(ulGen + PWM_O_X_CTL) & PWM_X_CTL_MODE)
+ {
+ //
+ // The period is twice the reload register value.
+ //
+ return(HWREG(ulGen + PWM_O_X_LOAD) * 2);
+ }
+ else
+ {
+ //
+ // The period is the reload register value plus one.
+ //
+ return(HWREG(ulGen + PWM_O_X_LOAD) + 1);
+ }
+}
+
+//*****************************************************************************
+//
+//! Enables the timer/counter for a PWM generator block.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGen is the PWM generator to be enabled. Must be one of
+//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
+//!
+//! This function allows the PWM clock to drive the timer/counter for the
+//! specified generator block.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMGenEnable(unsigned long ulBase, unsigned long ulGen)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(PWMGenValid(ulGen));
+
+ //
+ // Enable the PWM generator.
+ //
+ HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_CTL) |= PWM_X_CTL_ENABLE;
+}
+
+//*****************************************************************************
+//
+//! Disables the timer/counter for a PWM generator block.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGen is the PWM generator to be disabled. Must be one of
+//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
+//!
+//! This function blocks the PWM clock from driving the timer/counter for the
+//! specified generator block.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMGenDisable(unsigned long ulBase, unsigned long ulGen)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(PWMGenValid(ulGen));
+
+ //
+ // Disable the PWM generator.
+ //
+ HWREG(PWM_GEN_BADDR(ulBase, + ulGen) + PWM_O_X_CTL) &= ~(PWM_X_CTL_ENABLE);
+}
+
+//*****************************************************************************
+//
+//! Sets the pulse width for the specified PWM output.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulPWMOut is the PWM output to modify. Must be one of \b PWM_OUT_0,
+//! \b PWM_OUT_1, \b PWM_OUT_2, \b PWM_OUT_3, \b PWM_OUT_4, \b PWM_OUT_5,
+//! \b PWM_OUT_6, or \b PWM_OUT_7.
+//! \param ulWidth specifies the width of the positive portion of the pulse.
+//!
+//! This function sets the pulse width for the specified PWM output, where the
+//! pulse width is defined as the number of PWM clock ticks.
+//!
+//! \note Any subsequent calls made to this function before an update occurs
+//! will cause the previous values to be overwritten.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut,
+ unsigned long ulWidth)
+{
+ unsigned long ulGenBase, ulReg;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(PWMOutValid(ulPWMOut));
+
+ //
+ // Compute the generator's base address.
+ //
+ ulGenBase = PWM_OUT_BADDR(ulBase, ulPWMOut);
+
+ //
+ // If the counter is in up/down count mode, divide the width by two.
+ //
+ if(HWREG(ulGenBase + PWM_O_X_CTL) & PWM_X_CTL_MODE)
+ {
+ ulWidth /= 2;
+ }
+
+ //
+ // Get the period.
+ //
+ ulReg = HWREG(ulGenBase + PWM_O_X_LOAD);
+
+ //
+ // Make sure the width is not too large.
+ //
+ ASSERT(ulWidth < ulReg);
+
+ //
+ // Compute the compare value.
+ //
+ ulReg = ulReg - ulWidth;
+
+ //
+ // Write to the appropriate registers.
+ //
+ if(PWM_IS_OUTPUT_ODD(ulPWMOut))
+ {
+ HWREG(ulGenBase + PWM_O_X_CMPB) = ulReg;
+ }
+ else
+ {
+ HWREG(ulGenBase + PWM_O_X_CMPA) = ulReg;
+ }
+}
+
+//*****************************************************************************
+//
+//! Gets the pulse width of a PWM output.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulPWMOut is the PWM output to query. Must be one of \b PWM_OUT_0,
+//! \b PWM_OUT_1, \b PWM_OUT_2, \b PWM_OUT_3, \b PWM_OUT_4, \b PWM_OUT_5,
+//! \b PWM_OUT_6, or \b PWM_OUT_7.
+//!
+//! This function gets the currently programmed pulse width for the specified
+//! PWM output. If the update of the comparator for the specified output has
+//! yet to be completed, the value returned may not be the active pulse width.
+//! The value returned is the programmed pulse width, measured in PWM clock
+//! ticks.
+//!
+//! \return Returns the width of the pulse in PWM clock ticks.
+//
+//*****************************************************************************
+unsigned long
+PWMPulseWidthGet(unsigned long ulBase, unsigned long ulPWMOut)
+{
+ unsigned long ulGenBase, ulReg, ulLoad;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(PWMOutValid(ulPWMOut));
+
+ //
+ // Compute the generator's base address.
+ //
+ ulGenBase = PWM_OUT_BADDR(ulBase, ulPWMOut);
+
+ //
+ // Then compute the pulse width. If mode is UpDown, set
+ // width = (load - compare) * 2. Otherwise, set width = load - compare.
+ //
+ ulLoad = HWREG(ulGenBase + PWM_O_X_LOAD);
+ if(PWM_IS_OUTPUT_ODD(ulPWMOut))
+ {
+ ulReg = HWREG(ulGenBase + PWM_O_X_CMPB);
+ }
+ else
+ {
+ ulReg = HWREG(ulGenBase + PWM_O_X_CMPA);
+ }
+ ulReg = ulLoad - ulReg;
+
+ //
+ // If in up/down count mode, double the pulse width.
+ //
+ if(HWREG(ulGenBase + PWM_O_X_CTL) & PWM_X_CTL_MODE)
+ {
+ ulReg = ulReg * 2;
+ }
+
+ //
+ // Return the pulse width.
+ //
+ return(ulReg);
+}
+
+//*****************************************************************************
+//
+//! Enables the PWM dead band output, and sets the dead band delays.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGen is the PWM generator to modify. Must be one of
+//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
+//! \param usRise specifies the width of delay from the rising edge.
+//! \param usFall specifies the width of delay from the falling edge.
+//!
+//! This function sets the dead bands for the specified PWM generator,
+//! where the dead bands are defined as the number of \b PWM clock ticks
+//! from the rising or falling edge of the generator's \b OutA signal.
+//! Note that this function causes the coupling of \b OutB to \b OutA.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen,
+ unsigned short usRise, unsigned short usFall)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(PWMGenValid(ulGen));
+ ASSERT(usRise < 4096);
+ ASSERT(usFall < 4096);
+
+ //
+ // Compute the generator's base address.
+ //
+ ulGen = PWM_GEN_BADDR(ulBase, ulGen);
+
+ //
+ // Write the dead band delay values.
+ //
+ HWREG(ulGen + PWM_O_X_DBRISE) = usRise;
+ HWREG(ulGen + PWM_O_X_DBFALL) = usFall;
+
+ //
+ // Enable the deadband functionality.
+ //
+ HWREG(ulGen + PWM_O_X_DBCTL) |= PWM_X_DBCTL_ENABLE;
+}
+
+//*****************************************************************************
+//
+//! Disables the PWM dead band output.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGen is the PWM generator to modify. Must be one of
+//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
+//!
+//! This function disables the dead band mode for the specified PWM generator.
+//! Doing so decouples the \b OutA and \b OutB signals.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(PWMGenValid(ulGen));
+
+ //
+ // Disable the deadband functionality.
+ //
+ HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_DBCTL) &=
+ ~(PWM_X_DBCTL_ENABLE);
+}
+
+//*****************************************************************************
+//
+//! Synchronizes all pending updates.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGenBits are the PWM generator blocks to be updated. Must be the
+//! logical OR of any of \b PWM_GEN_0_BIT, \b PWM_GEN_1_BIT,
+//! \b PWM_GEN_2_BIT, or \b PWM_GEN_3_BIT.
+//!
+//! For the selected PWM generators, this function causes all queued updates to
+//! the period or pulse width to be applied the next time the corresponding
+//! counter becomes zero.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(!(ulGenBits & ~(PWM_GEN_0_BIT | PWM_GEN_1_BIT | PWM_GEN_2_BIT |
+ PWM_GEN_3_BIT)));
+
+ //
+ // Synchronize pending PWM register changes.
+ //
+ HWREG(ulBase + PWM_O_CTL) = ulGenBits;
+}
+
+//*****************************************************************************
+//
+//! Synchronizes the counters in one or multiple PWM generator blocks.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGenBits are the PWM generator blocks to be synchronized. Must be
+//! the logical OR of any of \b PWM_GEN_0_BIT, \b PWM_GEN_1_BIT,
+//! \b PWM_GEN_2_BIT, or \b PWM_GEN_3_BIT.
+//!
+//! For the selected PWM module, this function synchronizes the time base
+//! of the generator blocks by causing the specified generator counters to be
+//! reset to zero.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(!(ulGenBits & ~(PWM_GEN_0_BIT | PWM_GEN_1_BIT | PWM_GEN_2_BIT |
+ PWM_GEN_3_BIT)));
+
+ //
+ // Synchronize the counters in the specified generators by writing to the
+ // module's synchronization register.
+ //
+ HWREG(ulBase + PWM_O_SYNC) = ulGenBits;
+}
+
+//*****************************************************************************
+//
+//! Enables or disables PWM outputs.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulPWMOutBits are the PWM outputs to be modified. Must be the
+//! logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, \b PWM_OUT_2_BIT,
+//! \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, \b PWM_OUT_5_BIT, \b PWM_OUT_6_BIT,
+//! or \b PWM_OUT_7_BIT.
+//! \param bEnable determines if the signal is enabled or disabled.
+//!
+//! This function is used to enable or disable the selected PWM outputs. The
+//! outputs are selected using the parameter \e ulPWMOutBits. The parameter
+//! \e bEnable determines the state of the selected outputs. If \e bEnable is
+//! \b true, then the selected PWM outputs are enabled, or placed in the active
+//! state. If \e bEnable is \b false, then the selected outputs are disabled,
+//! or placed in the inactive state.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits,
+ tBoolean bEnable)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(!(ulPWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT |
+ PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT |
+ PWM_OUT_6_BIT | PWM_OUT_7_BIT)));
+
+ //
+ // Read the module's ENABLE output control register, and set or clear the
+ // requested bits.
+ //
+ if(bEnable == true)
+ {
+ HWREG(ulBase + PWM_O_ENABLE) |= ulPWMOutBits;
+ }
+ else
+ {
+ HWREG(ulBase + PWM_O_ENABLE) &= ~(ulPWMOutBits);
+ }
+}
+
+//*****************************************************************************
+//
+//! Selects the inversion mode for PWM outputs.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulPWMOutBits are the PWM outputs to be modified. Must be the
+//! logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, \b PWM_OUT_2_BIT,
+//! \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, \b PWM_OUT_5_BIT, \b PWM_OUT_6_BIT, or
+//! \b PWM_OUT_7_BIT.
+//! \param bInvert determines if the signal is inverted or passed through.
+//!
+//! This function is used to select the inversion mode for the selected PWM
+//! outputs. The outputs are selected using the parameter \e ulPWMOutBits.
+//! The parameter \e bInvert determines the inversion mode for the selected
+//! outputs. If \e bInvert is \b true, this function will cause the specified
+//! PWM output signals to be inverted, or made active low. If \e bInvert is
+//! \b false, the specified output will be passed through as is, or be made
+//! active high.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits,
+ tBoolean bInvert)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(!(ulPWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT |
+ PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT |
+ PWM_OUT_6_BIT | PWM_OUT_7_BIT)));
+
+ //
+ // Read the module's INVERT output control register, and set or clear the
+ // requested bits.
+ //
+ if(bInvert == true)
+ {
+ HWREG(ulBase + PWM_O_INVERT) |= ulPWMOutBits;
+ }
+ else
+ {
+ HWREG(ulBase + PWM_O_INVERT) &= ~(ulPWMOutBits);
+ }
+}
+
+//*****************************************************************************
+//
+//! Specifies the level of PWM outputs suppressed in response to a fault
+//! condition.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulPWMOutBits are the PWM outputs to be modified. Must be the
+//! logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, \b PWM_OUT_2_BIT,
+//! \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, \b PWM_OUT_5_BIT, \b PWM_OUT_6_BIT, or
+//! \b PWM_OUT_7_BIT.
+//! \param bDriveHigh determines if the signal is driven high or low during an
+//! active fault condition.
+//!
+//! This function determines whether a PWM output pin that is suppressed in
+//! response to a fault condition will be driven high or low. The affected
+//! outputs are selected using the parameter \e ulPWMOutBits. The parameter
+//! \e bDriveHigh determines the output level for the pins identified by
+//! \e ulPWMOutBits. If \e bDriveHigh is \b true then the selected outputs
+//! will be driven high when a fault is detected. If it is \e false, the pins
+//! will be driven low.
+//!
+//! In a fault condition, pins which have not been configured to be suppressed
+//! via a call to PWMOutputFault() are unaffected by this function.
+//!
+//! \note This function is available only on devices which support extended
+//! PWM fault handling.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMOutputFaultLevel(unsigned long ulBase, unsigned long ulPWMOutBits,
+ tBoolean bDriveHigh)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(HWREG(SYSCTL_DC5) & SYSCTL_DC5_PWMEFLT);
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(!(ulPWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT |
+ PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT |
+ PWM_OUT_6_BIT | PWM_OUT_7_BIT)));
+
+ //
+ // Read the module's FAULT output control register, and set or clear the
+ // requested bits.
+ //
+ if(bDriveHigh == true)
+ {
+ HWREG(ulBase + PWM_O_FAULTVAL) |= ulPWMOutBits;
+ }
+ else
+ {
+ HWREG(ulBase + PWM_O_FAULTVAL) &= ~(ulPWMOutBits);
+ }
+}
+
+//*****************************************************************************
+//
+//! Specifies the state of PWM outputs in response to a fault condition.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulPWMOutBits are the PWM outputs to be modified. Must be the
+//! logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, \b PWM_OUT_2_BIT,
+//! \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, \b PWM_OUT_5_BIT, \b PWM_OUT_6_BIT, or
+//! \b PWM_OUT_7_BIT.
+//! \param bFaultSuppress determines if the signal is suppressed or passed
+//! through during an active fault condition.
+//!
+//! This function sets the fault handling characteristics of the selected PWM
+//! outputs. The outputs are selected using the parameter \e ulPWMOutBits.
+//! The parameter \e bFaultSuppress determines the fault handling
+//! characteristics for the selected outputs. If \e bFaultSuppress is \b true,
+//! then the selected outputs will be made inactive. If \e bFaultSuppress is
+//! \b false, then the selected outputs are unaffected by the detected fault.
+//!
+//! On devices supporting extended PWM fault handling, the state the affected
+//! output pins are driven to can be configured with PWMOutputFaultLevel(). If
+//! not configured, or if the device does not support extended PWM fault
+//! handling, affected outputs will be driven low on a fault condition.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits,
+ tBoolean bFaultSuppress)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(!(ulPWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT |
+ PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT |
+ PWM_OUT_6_BIT | PWM_OUT_7_BIT)));
+
+ //
+ // Read the module's FAULT output control register, and set or clear the
+ // requested bits.
+ //
+ if(bFaultSuppress == true)
+ {
+ HWREG(ulBase + PWM_O_FAULT) |= ulPWMOutBits;
+ }
+ else
+ {
+ HWREG(ulBase + PWM_O_FAULT) &= ~(ulPWMOutBits);
+ }
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the specified PWM generator block.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGen is the PWM generator in question. Must be one of
+//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
+//! \param pfnIntHandler is a pointer to the function to be called when the PWM
+//! generator interrupt occurs.
+//!
+//! This function will ensure that the interrupt handler specified by
+//! \e pfnIntHandler is called when an interrupt is detected for the specified
+//! PWM generator block. This function will also enable the corresponding
+//! PWM generator interrupt in the interrupt controller; individual generator
+//! interrupts and interrupt sources must be enabled with PWMIntEnable() and
+//! PWMGenIntTrigEnable().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen,
+ void (*pfnIntHandler)(void))
+{
+ unsigned long ulInt;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(PWMGenValid(ulGen));
+
+ //
+ // Get the interrupt number associated with the specified generator.
+ //
+ if(ulGen == PWM_GEN_3)
+ {
+ ulInt = INT_PWM3;
+ }
+ else
+ {
+ ulInt = INT_PWM0 + (ulGen >> 6) - 1;
+ }
+
+ //
+ // Register the interrupt handler.
+ //
+ IntRegister(ulInt, pfnIntHandler);
+
+ //
+ // Enable the PWMx interrupt.
+ //
+ IntEnable(ulInt);
+}
+
+//*****************************************************************************
+//
+//! Removes an interrupt handler for the specified PWM generator block.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGen is the PWM generator in question. Must be one of
+//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
+//!
+//! This function will unregister the interrupt handler for the specified
+//! PWM generator block. This function will also disable the corresponding
+//! PWM generator interrupt in the interrupt controller; individual generator
+//! interrupts and interrupt sources must be disabled with PWMIntDisable() and
+//! PWMGenIntTrigDisable().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen)
+{
+ unsigned long ulInt;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(PWMGenValid(ulGen));
+
+ //
+ // Get the interrupt number associated with the specified generator.
+ //
+ if(ulGen == PWM_GEN_3)
+ {
+ ulInt = INT_PWM3;
+ }
+ else
+ {
+ ulInt = INT_PWM0 + (ulGen >> 6) - 1;
+ }
+
+ //
+ // Disable the PWMx interrupt.
+ //
+ IntDisable(ulInt);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(ulInt);
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for a fault condition detected in a PWM
+//! module.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param pfnIntHandler is a pointer to the function to be called when the PWM
+//! fault interrupt occurs.
+//!
+//! This function will ensure that the interrupt handler specified by
+//! \e pfnIntHandler is called when a fault interrupt is detected for the
+//! selected PWM module. This function will also enable the PWM fault
+//! interrupt in the NVIC; the PWM fault interrupt must also be enabled at the
+//! module level using PWMIntEnable().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMFaultIntRegister(unsigned long ulBase, void (*pfnIntHandler)(void))
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+
+ //
+ // Register the interrupt handler, returning an error if one occurs.
+ //
+ IntRegister(INT_PWM_FAULT, pfnIntHandler);
+
+ //
+ // Enable the PWM fault interrupt.
+ //
+ IntEnable(INT_PWM_FAULT);
+}
+
+//*****************************************************************************
+//
+//! Removes the PWM fault condition interrupt handler.
+//!
+//! \param ulBase is the base address of the PWM module.
+//!
+//! This function will remove the interrupt handler for a PWM fault interrupt
+//! from the selected PWM module. This function will also disable the PWM
+//! fault interrupt in the NVIC; the PWM fault interrupt must also be disabled
+//! at the module level using PWMIntDisable().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMFaultIntUnregister(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+
+ //
+ // Disable the PWM fault interrupt.
+ //
+ IntDisable(INT_PWM_FAULT);
+
+ //
+ // Unregister the interrupt handler, returning an error if one occurs.
+ //
+ IntUnregister(INT_PWM_FAULT);
+}
+
+//*****************************************************************************
+//
+//! Enables interrupts and triggers for the specified PWM generator block.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGen is the PWM generator to have interrupts and triggers enabled.
+//! Must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
+//! \param ulIntTrig specifies the interrupts and triggers to be enabled.
+//!
+//! Unmasks the specified interrupt(s) and trigger(s) by setting the
+//! specified bits of the interrupt/trigger enable register for the specified
+//! PWM generator. The \e ulIntTrig parameter is the logical OR of
+//! \b PWM_INT_CNT_ZERO, \b PWM_INT_CNT_LOAD, \b PWM_INT_CNT_AU,
+//! \b PWM_INT_CNT_AD, \b PWM_INT_CNT_BU, \b PWM_INT_CNT_BD,
+//! \b PWM_TR_CNT_ZERO, \b PWM_TR_CNT_LOAD, \b PWM_TR_CNT_AU, \b PWM_TR_CNT_AD,
+//! \b PWM_TR_CNT_BU, or \b PWM_TR_CNT_BD.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen,
+ unsigned long ulIntTrig)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(PWMGenValid(ulGen));
+ ASSERT((ulIntTrig & ~(PWM_INT_CNT_ZERO | PWM_INT_CNT_LOAD |
+ PWM_INT_CNT_AU | PWM_INT_CNT_AD | PWM_INT_CNT_BU |
+ PWM_INT_CNT_BD | PWM_TR_CNT_ZERO | PWM_TR_CNT_LOAD |
+ PWM_TR_CNT_AU | PWM_TR_CNT_AD | PWM_TR_CNT_BU |
+ PWM_TR_CNT_BD)) == 0);
+
+ //
+ // Enable the specified interrupts/triggers.
+ //
+ HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_INTEN) |= ulIntTrig;
+}
+
+//*****************************************************************************
+//
+//! Disables interrupts for the specified PWM generator block.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGen is the PWM generator to have interrupts and triggers disabled.
+//! Must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
+//! \param ulIntTrig specifies the interrupts and triggers to be disabled.
+//!
+//! Masks the specified interrupt(s) and trigger(s) by clearing the
+//! specified bits of the interrupt/trigger enable register for the specified
+//! PWM generator. The \e ulIntTrig parameter is the logical OR of
+//! \b PWM_INT_CNT_ZERO, \b PWM_INT_CNT_LOAD, \b PWM_INT_CNT_AU,
+//! \b PWM_INT_CNT_AD, \b PWM_INT_CNT_BU, \b PWM_INT_CNT_BD,
+//! \b PWM_TR_CNT_ZERO, \b PWM_TR_CNT_LOAD, \b PWM_TR_CNT_AU, \b PWM_TR_CNT_AD,
+//! \b PWM_TR_CNT_BU, or \b PWM_TR_CNT_BD.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen,
+ unsigned long ulIntTrig)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(PWMGenValid(ulGen));
+ ASSERT((ulIntTrig & ~(PWM_INT_CNT_ZERO | PWM_INT_CNT_LOAD |
+ PWM_INT_CNT_AU | PWM_INT_CNT_AD | PWM_INT_CNT_BU |
+ PWM_INT_CNT_BD | PWM_TR_CNT_ZERO | PWM_TR_CNT_LOAD |
+ PWM_TR_CNT_AU | PWM_TR_CNT_AD | PWM_TR_CNT_BU |
+ PWM_TR_CNT_BD)) == 0);
+
+ //
+ // Disable the specified interrupts/triggers.
+ //
+ HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_INTEN) &= ~(ulIntTrig);
+}
+
+//*****************************************************************************
+//
+//! Gets interrupt status for the specified PWM generator block.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGen is the PWM generator to query. Must be one of \b PWM_GEN_0,
+//! \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
+//! \param bMasked specifies whether masked or raw interrupt status is
+//! returned.
+//!
+//! If \e bMasked is set as \b true, then the masked interrupt status is
+//! returned; otherwise, the raw interrupt status will be returned.
+//!
+//! \return Returns the contents of the interrupt status register, or the
+//! contents of the raw interrupt status register, for the specified
+//! PWM generator.
+//
+//*****************************************************************************
+unsigned long
+PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen, tBoolean bMasked)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(PWMGenValid(ulGen));
+
+ //
+ // Compute the generator's base address.
+ //
+ ulGen = PWM_GEN_BADDR(ulBase, ulGen);
+
+ //
+ // Read and return the specified generator's raw or enabled interrupt
+ // status.
+ //
+ if(bMasked == true)
+ {
+ return(HWREG(ulGen + PWM_O_X_ISC));
+ }
+ else
+ {
+ return(HWREG(ulGen + PWM_O_X_RIS));
+ }
+}
+
+//*****************************************************************************
+//
+//! Clears the specified interrupt(s) for the specified PWM generator block.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGen is the PWM generator to query. Must be one of \b PWM_GEN_0,
+//! \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
+//! \param ulInts specifies the interrupts to be cleared.
+//!
+//! Clears the specified interrupt(s) by writing a 1 to the specified bits
+//! of the interrupt status register for the specified PWM generator. The
+//! \e ulInts parameter is the logical OR of \b PWM_INT_CNT_ZERO,
+//! \b PWM_INT_CNT_LOAD, \b PWM_INT_CNT_AU, \b PWM_INT_CNT_AD,
+//! \b PWM_INT_CNT_BU, or \b PWM_INT_CNT_BD.
+//!
+//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
+//! several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared. Failure to do so may result in the interrupt handler
+//! being immediately reentered (since NVIC still sees the interrupt source
+//! asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMGenIntClear(unsigned long ulBase, unsigned long ulGen, unsigned long ulInts)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(PWMGenValid(ulGen));
+ ASSERT((ulInts & ~(PWM_INT_CNT_ZERO | PWM_INT_CNT_LOAD | PWM_INT_CNT_AU |
+ PWM_INT_CNT_AD | PWM_INT_CNT_BU | PWM_INT_CNT_BD)) ==
+ 0);
+
+ //
+ // Clear the requested interrupts by writing ones to the specified bit
+ // of the module's interrupt enable register.
+ //
+ HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_ISC) = ulInts;
+}
+
+//*****************************************************************************
+//
+//! Enables generator and fault interrupts for a PWM module.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGenFault contains the interrupts to be enabled. Must be a logical
+//! OR of any of \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, \b PWM_INT_GEN_2,
+//! \b PWM_INT_GEN_3, \b PWM_INT_FAULT0, \b PWM_INT_FAULT1, \b PWM_INT_FAULT2,
+//! or \b PWM_INT_FAULT3.
+//!
+//! Unmasks the specified interrupt(s) by setting the specified bits of
+//! the interrupt enable register for the selected PWM module.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT((ulGenFault & ~(PWM_INT_GEN_0 | PWM_INT_GEN_1 | PWM_INT_GEN_2 |
+ PWM_INT_GEN_3 | PWM_INT_FAULT0 | PWM_INT_FAULT1 |
+ PWM_INT_FAULT2 | PWM_INT_FAULT3)) == 0);
+
+ //
+ // Read the module's interrupt enable register, and enable interrupts
+ // for the specified PWM generators.
+ //
+ HWREG(ulBase + PWM_O_INTEN) |= ulGenFault;
+}
+
+//*****************************************************************************
+//
+//! Disables generator and fault interrupts for a PWM module.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGenFault contains the interrupts to be disabled. Must be a
+//! logical OR of any of \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, \b PWM_INT_GEN_2,
+//! \b PWM_INT_GEN_3, \b PWM_INT_FAULT0, \b PWM_INT_FAULT1, \b PWM_INT_FAULT2,
+//! or \b PWM_INT_FAULT3.
+//!
+//! Masks the specified interrupt(s) by clearing the specified bits of
+//! the interrupt enable register for the selected PWM module.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT((ulGenFault & ~(PWM_INT_GEN_0 | PWM_INT_GEN_1 | PWM_INT_GEN_2 |
+ PWM_INT_GEN_3 | PWM_INT_FAULT0 | PWM_INT_FAULT1 |
+ PWM_INT_FAULT2 | PWM_INT_FAULT3)) == 0);
+
+ //
+ // Read the module's interrupt enable register, and disable interrupts
+ // for the specified PWM generators.
+ //
+ HWREG(ulBase + PWM_O_INTEN) &= ~(ulGenFault);
+}
+
+//*****************************************************************************
+//
+//! Clears the fault interrupt for a PWM module.
+//!
+//! \param ulBase is the base address of the PWM module.
+//!
+//! Clears the fault interrupt by writing to the appropriate bit of the
+//! interrupt status register for the selected PWM module.
+//!
+//! This function clears only the FAULT0 interrupt and is retained for
+//! backwards compatibility. It is recommended that PWMFaultIntClearExt() be
+//! used instead since it supports all fault interrupts supported on devices
+//! with and without extended PWM fault handling support.
+//!
+//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
+//! several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared. Failure to do so may result in the interrupt handler
+//! being immediately reentered (since NVIC still sees the interrupt source
+//! asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMFaultIntClear(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+
+ //
+ // Write the only writeable bit in the module's interrupt register.
+ //
+ HWREG(ulBase + PWM_O_ISC) = PWM_ISC_INTFAULT0;
+}
+
+//*****************************************************************************
+//
+//! Gets the interrupt status for a PWM module.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param bMasked specifies whether masked or raw interrupt status is
+//! returned.
+//!
+//! If \e bMasked is set as \b true, then the masked interrupt status is
+//! returned; otherwise, the raw interrupt status will be returned.
+//!
+//! \return The current interrupt status, enumerated as a bit field of
+//! \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, \b PWM_INT_GEN_2, \b PWM_INT_GEN_3,
+//! \b PWM_INT_FAULT0, \b PWM_INT_FAULT1, \b PWM_INT_FAULT2, and
+//! \b PWM_INT_FAULT3.
+//!
+//*****************************************************************************
+unsigned long
+PWMIntStatus(unsigned long ulBase, tBoolean bMasked)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+
+ //
+ // Read and return either the module's raw or enabled interrupt status.
+ //
+ if(bMasked == true)
+ {
+ return(HWREG(ulBase + PWM_O_ISC));
+ }
+ else
+ {
+ return(HWREG(ulBase + PWM_O_RIS));
+ }
+}
+
+//*****************************************************************************
+//
+//! Clears the fault interrupt for a PWM module.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulFaultInts specifies the fault interrupts to clear.
+//!
+//! Clears one or more fault interrupts by writing to the appropriate bit of
+//! the PWM interrupt status register. The parameter \e ulFaultInts must be
+//! the logical OR of any of \b PWM_INT_FAULT0, \b PWM_INT_FAULT1,
+//! \b PWM_INT_FAULT2, or \b PWM_INT_FAULT3.
+//!
+//! When running on a device supporting extended PWM fault handling, the fault
+//! interrupts are derived by performing a logical OR of each of the configured
+//! fault trigger signals for a given generator. Therefore, these interrupts
+//! are not directly related to the four possible FAULTn inputs to the device
+//! but indicate that a fault has been signaled to one of the four possible PWM
+//! generators. On a device without extended PWM fault handling, the interrupt
+//! is directly related to the state of the single FAULT pin.
+//!
+//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
+//! several cycles before the interrupt source is actually cleared. Therefore,
+//! it is recommended that the interrupt source be cleared early in the
+//! interrupt handler (as opposed to the very last action) to avoid returning
+//! from the interrupt handler before the interrupt source is actually cleared.
+//! Failure to do so may result in the interrupt handler being immediately
+//! reentered (since NVIC still sees the interrupt source asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMFaultIntClearExt(unsigned long ulBase, unsigned long ulFaultInts)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT((ulFaultInts & ~(PWM_INT_FAULT0 | PWM_INT_FAULT1 |
+ PWM_INT_FAULT2 | PWM_INT_FAULT3)) == 0);
+
+ //
+ // Clear the supplied fault bits.
+ //
+ HWREG(ulBase + PWM_O_ISC) = ulFaultInts;
+}
+
+//*****************************************************************************
+//
+//! Configures the minimum fault period and fault pin senses for a given
+//! PWM generator.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGen is the PWM generator whose fault configuration is being set.
+//! Must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
+//! \param ulMinFaultPeriod is the minimum fault active period expressed in
+//! PWM clock cycles.
+//! \param ulFaultSenses indicates which sense of each FAULT input should be
+//! considered the ``asserted'' state. Valid values are logical OR
+//! combinations of \b PWM_FAULTn_SENSE_HIGH and \b PWM_FAULTn_SENSE_LOW.
+//!
+//! This function sets the minimum fault period for a given generator along
+//! with the sense of each of the 4 possible fault inputs. The minimum fault
+//! period is expressed in PWM clock cycles and takes effect only if
+//! PWMGenConfigure() is called with flag \b PWM_GEN_MODE_FAULT_PER set in the
+//! \e ulConfig parameter. When a fault input is asserted, the minimum fault
+//! period timer ensures that it remains asserted for at least the number of
+//! clock cycles specified.
+//!
+//! \note This function is only available on devices supporting extended PWM
+//! fault handling.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMGenFaultConfigure(unsigned long ulBase, unsigned long ulGen,
+ unsigned long ulMinFaultPeriod,
+ unsigned long ulFaultSenses)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(HWREG(SYSCTL_DC5) & SYSCTL_DC5_PWMEFLT);
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(PWMGenValid(ulGen));
+ ASSERT(ulMinFaultPeriod < PWM_X_MINFLTPER_M);
+ ASSERT((ulFaultSenses & ~(PWM_FAULT0_SENSE_HIGH | PWM_FAULT0_SENSE_LOW |
+ PWM_FAULT1_SENSE_HIGH | PWM_FAULT1_SENSE_LOW |
+ PWM_FAULT2_SENSE_HIGH | PWM_FAULT2_SENSE_LOW |
+ PWM_FAULT3_SENSE_HIGH | PWM_FAULT3_SENSE_LOW)) ==
+ 0);
+
+ //
+ // Write the minimum fault period.
+ //
+ HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_MINFLTPER) = ulMinFaultPeriod;
+
+ //
+ // Write the fault senses.
+ //
+ HWREG(PWM_GEN_EXT_BADDR(ulBase, ulGen) + PWM_O_X_FLTSEN) = ulFaultSenses;
+}
+
+//*****************************************************************************
+//
+//! Configures the set of fault triggers for a given PWM generator.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGen is the PWM generator whose fault triggers are being set. Must
+//! be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
+//! \param ulGroup indicates the subset of possible faults that are to be
+//! configured. This must be \b PWM_FAULT_GROUP_0.
+//! \param ulFaultTriggers defines the set of inputs that are to contribute
+//! towards generation of the fault signal to the given PWM generator. For
+//! \b PWM_FAULT_GROUP_0, this will be the logical OR of \b PWM_FAULT_FAULT0,
+//! \b PWM_FAULT_FAULT1, \b PWM_FAULT_FAULT2, or \b PWM_FAULT_FAULT3.
+//!
+//! This function allows selection of the set of fault inputs that will be
+//! combined to generate a fault condition to a given PWM generator. By
+//! default, all generators use only FAULT0 (for backwards compatibility) but
+//! if PWMGenConfigure() is called with flag \b PWM_GEN_MODE_FAULT_SRC in the
+//! \e ulConfig parameter, extended fault handling is enabled and this function
+//! must be called to configure the fault triggers.
+//!
+//! The fault signal to the PWM generator is generated by ORing together each
+//! of the signals whose inputs are specified in the \e ulFaultTriggers
+//! parameter after having adjusted the sense of each FAULTn input based on the
+//! configuration previously set using a call to PWMGenFaultConfigure().
+//!
+//! \note This function is only available on devices supporting extended PWM
+//! fault handling.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMGenFaultTriggerSet(unsigned long ulBase, unsigned long ulGen,
+ unsigned long ulGroup, unsigned long ulFaultTriggers)
+{
+ //
+ // Check for valid parameters.
+ //
+ ASSERT(HWREG(SYSCTL_DC5) & SYSCTL_DC5_PWMEFLT);
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(PWMGenValid(ulGen));
+ ASSERT((ulGroup == PWM_FAULT_GROUP_0) || (ulGroup == PWM_FAULT_GROUP_1));
+ ASSERT((ulFaultTriggers & ~(PWM_FAULT_FAULT0 | PWM_FAULT_FAULT1 |
+ PWM_FAULT_FAULT2 | PWM_FAULT_FAULT3)) == 0);
+
+ //
+ // Write the fault triggers to the appropriate register.
+ //
+ if(ulGroup == PWM_FAULT_GROUP_0)
+ {
+ HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_FLTSRC0) =
+ ulFaultTriggers;
+ }
+ else
+ {
+ HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_FLTSRC1) =
+ ulFaultTriggers;
+ }
+}
+
+//*****************************************************************************
+//
+//! Returns the set of fault triggers currently configured for a given PWM
+//! generator.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGen is the PWM generator whose fault triggers are being queried.
+//! Must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
+//! \param ulGroup indicates the subset of faults that are being queried. This
+//! must be \b PWM_FAULT_GROUP_0.
+//!
+//! This function allows an application to query the current set of inputs that
+//! contribute towards the generation of a fault condition to a given PWM
+//! generator.
+//!
+//! \note This function is only available on devices supporting extended PWM
+//! fault handling.
+//!
+//! \return Returns the current fault triggers configured for the fault group
+//! provided. For \b PWM_FAULT_GROUP_0, the returned value will be a logical
+//! OR of \b PWM_FAULT_FAULT0, \b PWM_FAULT_FAULT1, \b PWM_FAULT_FAULT2, or
+//! \b PWM_FAULT_FAULT3.
+//
+//*****************************************************************************
+unsigned long
+PWMGenFaultTriggerGet(unsigned long ulBase, unsigned long ulGen,
+ unsigned long ulGroup)
+{
+ //
+ // Check for valid parameters.
+ //
+ ASSERT(HWREG(SYSCTL_DC5) & SYSCTL_DC5_PWMEFLT);
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(PWMGenValid(ulGen));
+ ASSERT((ulGroup == PWM_FAULT_GROUP_0) || (ulGroup == PWM_FAULT_GROUP_1));
+
+ //
+ // Return the current fault triggers.
+ //
+ if(ulGroup == PWM_FAULT_GROUP_0)
+ {
+ return(HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_FLTSRC0));
+ }
+ else
+ {
+ return(HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_FLTSRC1));
+ }
+}
+
+//*****************************************************************************
+//
+//! Returns the current state of the fault triggers for a given PWM generator.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGen is the PWM generator whose fault trigger states are being
+//! queried. Must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or
+//! \b PWM_GEN_3.
+//! \param ulGroup indicates the subset of faults that are being queried. This
+//! must be \b PWM_FAULT_GROUP_0.
+//!
+//! This function allows an application to query the current state of each of
+//! the fault trigger inputs to a given PWM generator. The current state of
+//! each fault trigger input is returned unless PWMGenConfigure() has
+//! previously been called with flag \b PWM_GEN_MODE_LATCH_FAULT in the
+//! \e ulConfig parameter in which case the returned status is the latched
+//! fault trigger status.
+//!
+//! If latched faults are configured, the application must call
+//! PWMGenFaultClear() to clear each trigger.
+//!
+//! \note This function is only available on devices supporting extended PWM
+//! fault handling.
+//!
+//! \return Returns the current state of the fault triggers for the given PWM
+//! generator. A set bit indicates that the associated trigger is active. For
+//! \b PWM_FAULT_GROUP_0, the returned value will be a logical OR of
+//! \b PWM_FAULT_FAULT0, \b PWM_FAULT_FAULT1, \b PWM_FAULT_FAULT2, or
+//! \b PWM_FAULT_FAULT3.
+//
+//*****************************************************************************
+unsigned long
+PWMGenFaultStatus(unsigned long ulBase, unsigned long ulGen,
+ unsigned long ulGroup)
+{
+ //
+ // Check for valid parameters.
+ //
+ ASSERT(HWREG(SYSCTL_DC5) & SYSCTL_DC5_PWMEFLT);
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(PWMGenValid(ulGen));
+ ASSERT((ulGroup == PWM_FAULT_GROUP_0) || (ulGroup == PWM_FAULT_GROUP_1));
+
+ //
+ // Return the current fault status.
+ //
+ if(ulGroup == PWM_FAULT_GROUP_0)
+ {
+ return(HWREG(PWM_GEN_EXT_BADDR(ulBase, ulGen) + PWM_O_X_FLTSTAT0));
+ }
+ else
+ {
+ return(HWREG(PWM_GEN_EXT_BADDR(ulBase, ulGen) + PWM_O_X_FLTSTAT1));
+ }
+}
+
+//*****************************************************************************
+//
+//! Clears one or more latched fault triggers for a given PWM generator.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGen is the PWM generator whose fault trigger states are being
+//! queried. Must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or
+//! \b PWM_GEN_3.
+//! \param ulGroup indicates the subset of faults that are being queried. This
+//! must be \b PWM_FAULT_GROUP_0.
+//! \param ulFaultTriggers is the set of fault triggers which are to be
+//! cleared.
+//!
+//! This function allows an application to clear the fault triggers for a given
+//! PWM generator. This is only required if PWMGenConfigure() has previously
+//! been called with flag \b PWM_GEN_MODE_LATCH_FAULT in parameter \e ulConfig.
+//!
+//! \note This function is only available on devices supporting extended PWM
+//! fault handling.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMGenFaultClear(unsigned long ulBase, unsigned long ulGen,
+ unsigned long ulGroup, unsigned long ulFaultTriggers)
+{
+ //
+ // Check for valid parameters.
+ //
+ ASSERT(HWREG(SYSCTL_DC5) & SYSCTL_DC5_PWMEFLT);
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(PWMGenValid(ulGen));
+ ASSERT((ulGroup == PWM_FAULT_GROUP_0) || (ulGroup == PWM_FAULT_GROUP_1));
+ ASSERT((ulFaultTriggers & ~(PWM_FAULT_FAULT0 | PWM_FAULT_FAULT1 |
+ PWM_FAULT_FAULT2 | PWM_FAULT_FAULT3)) == 0);
+
+ //
+ // Clear the given faults.
+ //
+ if(ulGroup == PWM_FAULT_GROUP_0)
+ {
+ HWREG(PWM_GEN_EXT_BADDR(ulBase, ulGen) + PWM_O_X_FLTSTAT0) =
+ ulFaultTriggers;
+ }
+ else
+ {
+ HWREG(PWM_GEN_EXT_BADDR(ulBase, ulGen) + PWM_O_X_FLTSTAT1) =
+ ulFaultTriggers;
+ }
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
Property changes on: branches/eagle_mmc/src/platform/lm3s/pwm.c
___________________________________________________________________
Name: svn:executable
+ *
Modified: branches/eagle_mmc/src/platform/lm3s/pwm.h
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/pwm.h 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lm3s/pwm.h 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,269 +1,277 @@
-//*****************************************************************************
-//
-// pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports
-//
-// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
-// Software License Agreement
-//
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
-//
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws. All rights are reserved. You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program. Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
-//
-// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-//
-// This is part of revision 3740 of the Stellaris Peripheral Driver Library.
-//
-//*****************************************************************************
-
-#ifndef __PWM_H__
-#define __PWM_H__
-
-//*****************************************************************************
-//
-// If building with a C++ compiler, make all of the definitions in this header
-// have a C binding.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-//*****************************************************************************
-//
-// The following defines are passed to PWMGenConfigure() as the ulConfig
-// parameter and specify the configuration of the PWM generator.
-//
-//*****************************************************************************
-#define PWM_GEN_MODE_DOWN 0x00000000 // Down count mode
-#define PWM_GEN_MODE_UP_DOWN 0x00000002 // Up/Down count mode
-#define PWM_GEN_MODE_SYNC 0x00000038 // Synchronous updates
-#define PWM_GEN_MODE_NO_SYNC 0x00000000 // Immediate updates
-#define PWM_GEN_MODE_DBG_RUN 0x00000004 // Continue running in debug mode
-#define PWM_GEN_MODE_DBG_STOP 0x00000000 // Stop running in debug mode
-#define PWM_GEN_MODE_FAULT_LATCHED \
- 0x00040000 // Fault is latched
-#define PWM_GEN_MODE_FAULT_UNLATCHED \
- 0x00000000 // Fault is not latched
-#define PWM_GEN_MODE_FAULT_MINPER \
- 0x00020000 // Enable min fault period
-#define PWM_GEN_MODE_FAULT_NO_MINPER \
- 0x00000000 // Disable min fault period
-#define PWM_GEN_MODE_FAULT_EXT 0x00010000 // Enable extended fault support
-#define PWM_GEN_MODE_FAULT_LEGACY \
- 0x00000000 // Disable extended fault support
-#define PWM_GEN_MODE_DB_NO_SYNC 0x00000000 // Deadband updates occur
- // immediately
-#define PWM_GEN_MODE_DB_SYNC_LOCAL \
- 0x0000A800 // Deadband updates locally
- // synchronized
-#define PWM_GEN_MODE_DB_SYNC_GLOBAL \
- 0x0000FC00 // Deadband updates globally
- // synchronized
-#define PWM_GEN_MODE_GEN_NO_SYNC \
- 0x00000000 // Generator mode updates occur
- // immediately
-#define PWM_GEN_MODE_GEN_SYNC_LOCAL \
- 0x00000280 // Generator mode updates locally
- // synchronized
-#define PWM_GEN_MODE_GEN_SYNC_GLOBAL \
- 0x000003C0 // Generator mode updates globally
- // synchronized
-
-//*****************************************************************************
-//
-// Defines for enabling, disabling, and clearing PWM generator interrupts and
-// triggers.
-//
-//*****************************************************************************
-#define PWM_INT_CNT_ZERO 0x00000001 // Int if COUNT = 0
-#define PWM_INT_CNT_LOAD 0x00000002 // Int if COUNT = LOAD
-#define PWM_INT_CNT_AU 0x00000004 // Int if COUNT = CMPA U
-#define PWM_INT_CNT_AD 0x00000008 // Int if COUNT = CMPA D
-#define PWM_INT_CNT_BU 0x00000010 // Int if COUNT = CMPA U
-#define PWM_INT_CNT_BD 0x00000020 // Int if COUNT = CMPA D
-#define PWM_TR_CNT_ZERO 0x00000100 // Trig if COUNT = 0
-#define PWM_TR_CNT_LOAD 0x00000200 // Trig if COUNT = LOAD
-#define PWM_TR_CNT_AU 0x00000400 // Trig if COUNT = CMPA U
-#define PWM_TR_CNT_AD 0x00000800 // Trig if COUNT = CMPA D
-#define PWM_TR_CNT_BU 0x00001000 // Trig if COUNT = CMPA U
-#define PWM_TR_CNT_BD 0x00002000 // Trig if COUNT = CMPA D
-
-//*****************************************************************************
-//
-// Defines for enabling, disabling, and clearing PWM interrupts.
-//
-//*****************************************************************************
-#define PWM_INT_GEN_0 0x00000001 // Generator 0 interrupt
-#define PWM_INT_GEN_1 0x00000002 // Generator 1 interrupt
-#define PWM_INT_GEN_2 0x00000004 // Generator 2 interrupt
-#define PWM_INT_GEN_3 0x00000008 // Generator 3 interrupt
-#ifndef DEPRECATED
-#define PWM_INT_FAULT 0x00010000 // Fault interrupt
-#endif
-#define PWM_INT_FAULT0 0x00010000 // Fault0 interrupt
-#define PWM_INT_FAULT1 0x00020000 // Fault1 interrupt
-#define PWM_INT_FAULT2 0x00040000 // Fault2 interrupt
-#define PWM_INT_FAULT3 0x00080000 // Fault3 interrupt
-#define PWM_INT_FAULT_M 0x000F0000 // Fault interrupt source mask
-
-//*****************************************************************************
-//
-// Defines to identify the generators within a module.
-//
-//*****************************************************************************
-#define PWM_GEN_0 0x00000040 // Offset address of Gen0
-#define PWM_GEN_1 0x00000080 // Offset address of Gen1
-#define PWM_GEN_2 0x000000C0 // Offset address of Gen2
-#define PWM_GEN_3 0x00000100 // Offset address of Gen3
-
-#define PWM_GEN_0_BIT 0x00000001 // Bit-wise ID for Gen0
-#define PWM_GEN_1_BIT 0x00000002 // Bit-wise ID for Gen1
-#define PWM_GEN_2_BIT 0x00000004 // Bit-wise ID for Gen2
-#define PWM_GEN_3_BIT 0x00000008 // Bit-wise ID for Gen3
-
-#define PWM_GEN_EXT_0 0x00000800 // Offset of Gen0 ext address range
-#define PWM_GEN_EXT_1 0x00000880 // Offset of Gen1 ext address range
-#define PWM_GEN_EXT_2 0x00000900 // Offset of Gen2 ext address range
-#define PWM_GEN_EXT_3 0x00000980 // Offset of Gen3 ext address range
-
-//*****************************************************************************
-//
-// Defines to identify the outputs within a module.
-//
-//*****************************************************************************
-#define PWM_OUT_0 0x00000040 // Encoded offset address of PWM0
-#define PWM_OUT_1 0x00000041 // Encoded offset address of PWM1
-#define PWM_OUT_2 0x00000082 // Encoded offset address of PWM2
-#define PWM_OUT_3 0x00000083 // Encoded offset address of PWM3
-#define PWM_OUT_4 0x000000C4 // Encoded offset address of PWM4
-#define PWM_OUT_5 0x000000C5 // Encoded offset address of PWM5
-#define PWM_OUT_6 0x00000106 // Encoded offset address of PWM6
-#define PWM_OUT_7 0x00000107 // Encoded offset address of PWM7
-
-#define PWM_OUT_0_BIT 0x00000001 // Bit-wise ID for PWM0
-#define PWM_OUT_1_BIT 0x00000002 // Bit-wise ID for PWM1
-#define PWM_OUT_2_BIT 0x00000004 // Bit-wise ID for PWM2
-#define PWM_OUT_3_BIT 0x00000008 // Bit-wise ID for PWM3
-#define PWM_OUT_4_BIT 0x00000010 // Bit-wise ID for PWM4
-#define PWM_OUT_5_BIT 0x00000020 // Bit-wise ID for PWM5
-#define PWM_OUT_6_BIT 0x00000040 // Bit-wise ID for PWM6
-#define PWM_OUT_7_BIT 0x00000080 // Bit-wise ID for PWM7
-
-//*****************************************************************************
-//
-// Defines to identify each of the possible fault trigger conditions in
-// PWM_FAULT_GROUP_0
-//
-//*****************************************************************************
-#define PWM_FAULT_GROUP_0 0
-
-#define PWM_FAULT_FAULT0 0x00000001
-#define PWM_FAULT_FAULT1 0x00000002
-#define PWM_FAULT_FAULT2 0x00000004
-#define PWM_FAULT_FAULT3 0x00000008
-#define PWM_FAULT_ACMP0 0x00010000
-#define PWM_FAULT_ACMP1 0x00020000
-#define PWM_FAULT_ACMP2 0x00040000
-
-//*****************************************************************************
-//
-// Defines to identify the sense of each of the external FAULTn signals
-//
-//*****************************************************************************
-#define PWM_FAULT0_SENSE_HIGH 0x00000000
-#define PWM_FAULT0_SENSE_LOW 0x00000001
-#define PWM_FAULT1_SENSE_HIGH 0x00000000
-#define PWM_FAULT1_SENSE_LOW 0x00000002
-#define PWM_FAULT2_SENSE_HIGH 0x00000000
-#define PWM_FAULT2_SENSE_LOW 0x00000004
-#define PWM_FAULT3_SENSE_HIGH 0x00000000
-#define PWM_FAULT3_SENSE_LOW 0x00000008
-
-//*****************************************************************************
-//
-// API Function prototypes
-//
-//*****************************************************************************
-extern void PWMGenConfigure(unsigned long ulBase, unsigned long ulGen,
- unsigned long ulConfig);
-extern void PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen,
- unsigned long ulPeriod);
-extern unsigned long PWMGenPeriodGet(unsigned long ulBase,
- unsigned long ulGen);
-extern void PWMGenEnable(unsigned long ulBase, unsigned long ulGen);
-extern void PWMGenDisable(unsigned long ulBase, unsigned long ulGen);
-extern void PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut,
- unsigned long ulWidth);
-extern unsigned long PWMPulseWidthGet(unsigned long ulBase,
- unsigned long ulPWMOut);
-extern void PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen,
- unsigned short usRise, unsigned short usFall);
-extern void PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen);
-extern void PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits);
-extern void PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits);
-extern void PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits,
- tBoolean bEnable);
-extern void PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits,
- tBoolean bInvert);
-extern void PWMOutputFaultLevel(unsigned long ulBase,
- unsigned long ulPWMOutBits,
- tBoolean bDriveHigh);
-extern void PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits,
- tBoolean bFaultSuppress);
-extern void PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen,
- void (*pfnIntHandler)(void));
-extern void PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen);
-extern void PWMFaultIntRegister(unsigned long ulBase,
- void (*pfnIntHandler)(void));
-extern void PWMFaultIntUnregister(unsigned long ulBase);
-extern void PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen,
- unsigned long ulIntTrig);
-extern void PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen,
- unsigned long ulIntTrig);
-extern unsigned long PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen,
- tBoolean bMasked);
-extern void PWMGenIntClear(unsigned long ulBase, unsigned long ulGen,
- unsigned long ulInts);
-extern void PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault);
-extern void PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault);
-extern void PWMFaultIntClear(unsigned long ulBase);
-extern unsigned long PWMIntStatus(unsigned long ulBase, tBoolean bMasked);
-extern void PWMFaultIntClearExt(unsigned long ulBase,
- unsigned long ulFaultInts);
-extern void PWMGenFaultConfigure(unsigned long ulBase, unsigned long ulGen,
- unsigned long ulMinFaultPeriod,
- unsigned long ulFaultSenses);
-extern void PWMGenFaultTriggerSet(unsigned long ulBase, unsigned long ulGen,
- unsigned long ulGroup,
- unsigned long ulFaultTriggers);
-extern unsigned long PWMGenFaultTriggerGet(unsigned long ulBase,
- unsigned long ulGen,
- unsigned long ulGroup);
-extern unsigned long PWMGenFaultStatus(unsigned long ulBase,
- unsigned long ulGen,
- unsigned long ulGroup);
-extern void PWMGenFaultClear(unsigned long ulBase, unsigned long ulGen,
- unsigned long ulGroup,
- unsigned long ulFaultTriggers);
-
-//*****************************************************************************
-//
-// Mark the end of the C bindings section for C++ compilers.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-}
-#endif
-
-#endif // __PWM_H__
+//*****************************************************************************
+//
+// pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports
+//
+// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __PWM_H__
+#define __PWM_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// The following defines are passed to PWMGenConfigure() as the ulConfig
+// parameter and specify the configuration of the PWM generator.
+//
+//*****************************************************************************
+#define PWM_GEN_MODE_DOWN 0x00000000 // Down count mode
+#define PWM_GEN_MODE_UP_DOWN 0x00000002 // Up/Down count mode
+#define PWM_GEN_MODE_SYNC 0x00000038 // Synchronous updates
+#define PWM_GEN_MODE_NO_SYNC 0x00000000 // Immediate updates
+#define PWM_GEN_MODE_DBG_RUN 0x00000004 // Continue running in debug mode
+#define PWM_GEN_MODE_DBG_STOP 0x00000000 // Stop running in debug mode
+#define PWM_GEN_MODE_FAULT_LATCHED \
+ 0x00040000 // Fault is latched
+#define PWM_GEN_MODE_FAULT_UNLATCHED \
+ 0x00000000 // Fault is not latched
+#define PWM_GEN_MODE_FAULT_MINPER \
+ 0x00020000 // Enable min fault period
+#define PWM_GEN_MODE_FAULT_NO_MINPER \
+ 0x00000000 // Disable min fault period
+#define PWM_GEN_MODE_FAULT_EXT 0x00010000 // Enable extended fault support
+#define PWM_GEN_MODE_FAULT_LEGACY \
+ 0x00000000 // Disable extended fault support
+#define PWM_GEN_MODE_DB_NO_SYNC 0x00000000 // Deadband updates occur
+ // immediately
+#define PWM_GEN_MODE_DB_SYNC_LOCAL \
+ 0x0000A800 // Deadband updates locally
+ // synchronized
+#define PWM_GEN_MODE_DB_SYNC_GLOBAL \
+ 0x0000FC00 // Deadband updates globally
+ // synchronized
+#define PWM_GEN_MODE_GEN_NO_SYNC \
+ 0x00000000 // Generator mode updates occur
+ // immediately
+#define PWM_GEN_MODE_GEN_SYNC_LOCAL \
+ 0x00000280 // Generator mode updates locally
+ // synchronized
+#define PWM_GEN_MODE_GEN_SYNC_GLOBAL \
+ 0x000003C0 // Generator mode updates globally
+ // synchronized
+
+//*****************************************************************************
+//
+// Defines for enabling, disabling, and clearing PWM generator interrupts and
+// triggers.
+//
+//*****************************************************************************
+#define PWM_INT_CNT_ZERO 0x00000001 // Int if COUNT = 0
+#define PWM_INT_CNT_LOAD 0x00000002 // Int if COUNT = LOAD
+#define PWM_INT_CNT_AU 0x00000004 // Int if COUNT = CMPA U
+#define PWM_INT_CNT_AD 0x00000008 // Int if COUNT = CMPA D
+#define PWM_INT_CNT_BU 0x00000010 // Int if COUNT = CMPA U
+#define PWM_INT_CNT_BD 0x00000020 // Int if COUNT = CMPA D
+#define PWM_TR_CNT_ZERO 0x00000100 // Trig if COUNT = 0
+#define PWM_TR_CNT_LOAD 0x00000200 // Trig if COUNT = LOAD
+#define PWM_TR_CNT_AU 0x00000400 // Trig if COUNT = CMPA U
+#define PWM_TR_CNT_AD 0x00000800 // Trig if COUNT = CMPA D
+#define PWM_TR_CNT_BU 0x00001000 // Trig if COUNT = CMPA U
+#define PWM_TR_CNT_BD 0x00002000 // Trig if COUNT = CMPA D
+
+//*****************************************************************************
+//
+// Defines for enabling, disabling, and clearing PWM interrupts.
+//
+//*****************************************************************************
+#define PWM_INT_GEN_0 0x00000001 // Generator 0 interrupt
+#define PWM_INT_GEN_1 0x00000002 // Generator 1 interrupt
+#define PWM_INT_GEN_2 0x00000004 // Generator 2 interrupt
+#define PWM_INT_GEN_3 0x00000008 // Generator 3 interrupt
+#ifndef DEPRECATED
+#define PWM_INT_FAULT 0x00010000 // Fault interrupt
+#endif
+#define PWM_INT_FAULT0 0x00010000 // Fault0 interrupt
+#define PWM_INT_FAULT1 0x00020000 // Fault1 interrupt
+#define PWM_INT_FAULT2 0x00040000 // Fault2 interrupt
+#define PWM_INT_FAULT3 0x00080000 // Fault3 interrupt
+#define PWM_INT_FAULT_M 0x000F0000 // Fault interrupt source mask
+
+//*****************************************************************************
+//
+// Defines to identify the generators within a module.
+//
+//*****************************************************************************
+#define PWM_GEN_0 0x00000040 // Offset address of Gen0
+#define PWM_GEN_1 0x00000080 // Offset address of Gen1
+#define PWM_GEN_2 0x000000C0 // Offset address of Gen2
+#define PWM_GEN_3 0x00000100 // Offset address of Gen3
+
+#define PWM_GEN_0_BIT 0x00000001 // Bit-wise ID for Gen0
+#define PWM_GEN_1_BIT 0x00000002 // Bit-wise ID for Gen1
+#define PWM_GEN_2_BIT 0x00000004 // Bit-wise ID for Gen2
+#define PWM_GEN_3_BIT 0x00000008 // Bit-wise ID for Gen3
+
+#define PWM_GEN_EXT_0 0x00000800 // Offset of Gen0 ext address range
+#define PWM_GEN_EXT_1 0x00000880 // Offset of Gen1 ext address range
+#define PWM_GEN_EXT_2 0x00000900 // Offset of Gen2 ext address range
+#define PWM_GEN_EXT_3 0x00000980 // Offset of Gen3 ext address range
+
+//*****************************************************************************
+//
+// Defines to identify the outputs within a module.
+//
+//*****************************************************************************
+#define PWM_OUT_0 0x00000040 // Encoded offset address of PWM0
+#define PWM_OUT_1 0x00000041 // Encoded offset address of PWM1
+#define PWM_OUT_2 0x00000082 // Encoded offset address of PWM2
+#define PWM_OUT_3 0x00000083 // Encoded offset address of PWM3
+#define PWM_OUT_4 0x000000C4 // Encoded offset address of PWM4
+#define PWM_OUT_5 0x000000C5 // Encoded offset address of PWM5
+#define PWM_OUT_6 0x00000106 // Encoded offset address of PWM6
+#define PWM_OUT_7 0x00000107 // Encoded offset address of PWM7
+
+#define PWM_OUT_0_BIT 0x00000001 // Bit-wise ID for PWM0
+#define PWM_OUT_1_BIT 0x00000002 // Bit-wise ID for PWM1
+#define PWM_OUT_2_BIT 0x00000004 // Bit-wise ID for PWM2
+#define PWM_OUT_3_BIT 0x00000008 // Bit-wise ID for PWM3
+#define PWM_OUT_4_BIT 0x00000010 // Bit-wise ID for PWM4
+#define PWM_OUT_5_BIT 0x00000020 // Bit-wise ID for PWM5
+#define PWM_OUT_6_BIT 0x00000040 // Bit-wise ID for PWM6
+#define PWM_OUT_7_BIT 0x00000080 // Bit-wise ID for PWM7
+
+//*****************************************************************************
+//
+// Defines to identify each of the possible fault trigger conditions in
+// PWM_FAULT_GROUP_0.
+//
+//*****************************************************************************
+#define PWM_FAULT_GROUP_0 0
+
+#define PWM_FAULT_FAULT0 0x00000001
+#define PWM_FAULT_FAULT1 0x00000002
+#define PWM_FAULT_FAULT2 0x00000004
+#define PWM_FAULT_FAULT3 0x00000008
+#define PWM_FAULT_ACMP0 0x00010000
+#define PWM_FAULT_ACMP1 0x00020000
+#define PWM_FAULT_ACMP2 0x00040000
+
+//*****************************************************************************
+//
+// Defines to identify each of the possible fault trigger conditions in
+// PWM_FAULT_GROUP_1.
+//
+//*****************************************************************************
+#define PWM_FAULT_GROUP_1 1
+
+//*****************************************************************************
+//
+// Defines to identify the sense of each of the external FAULTn signals
+//
+//*****************************************************************************
+#define PWM_FAULT0_SENSE_HIGH 0x00000000
+#define PWM_FAULT0_SENSE_LOW 0x00000001
+#define PWM_FAULT1_SENSE_HIGH 0x00000000
+#define PWM_FAULT1_SENSE_LOW 0x00000002
+#define PWM_FAULT2_SENSE_HIGH 0x00000000
+#define PWM_FAULT2_SENSE_LOW 0x00000004
+#define PWM_FAULT3_SENSE_HIGH 0x00000000
+#define PWM_FAULT3_SENSE_LOW 0x00000008
+
+//*****************************************************************************
+//
+// API Function prototypes
+//
+//*****************************************************************************
+extern void PWMGenConfigure(unsigned long ulBase, unsigned long ulGen,
+ unsigned long ulConfig);
+extern void PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen,
+ unsigned long ulPeriod);
+extern unsigned long PWMGenPeriodGet(unsigned long ulBase,
+ unsigned long ulGen);
+extern void PWMGenEnable(unsigned long ulBase, unsigned long ulGen);
+extern void PWMGenDisable(unsigned long ulBase, unsigned long ulGen);
+extern void PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut,
+ unsigned long ulWidth);
+extern unsigned long PWMPulseWidthGet(unsigned long ulBase,
+ unsigned long ulPWMOut);
+extern void PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen,
+ unsigned short usRise, unsigned short usFall);
+extern void PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen);
+extern void PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits);
+extern void PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits);
+extern void PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits,
+ tBoolean bEnable);
+extern void PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits,
+ tBoolean bInvert);
+extern void PWMOutputFaultLevel(unsigned long ulBase,
+ unsigned long ulPWMOutBits,
+ tBoolean bDriveHigh);
+extern void PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits,
+ tBoolean bFaultSuppress);
+extern void PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen,
+ void (*pfnIntHandler)(void));
+extern void PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen);
+extern void PWMFaultIntRegister(unsigned long ulBase,
+ void (*pfnIntHandler)(void));
+extern void PWMFaultIntUnregister(unsigned long ulBase);
+extern void PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen,
+ unsigned long ulIntTrig);
+extern void PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen,
+ unsigned long ulIntTrig);
+extern unsigned long PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen,
+ tBoolean bMasked);
+extern void PWMGenIntClear(unsigned long ulBase, unsigned long ulGen,
+ unsigned long ulInts);
+extern void PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault);
+extern void PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault);
+extern void PWMFaultIntClear(unsigned long ulBase);
+extern unsigned long PWMIntStatus(unsigned long ulBase, tBoolean bMasked);
+extern void PWMFaultIntClearExt(unsigned long ulBase,
+ unsigned long ulFaultInts);
+extern void PWMGenFaultConfigure(unsigned long ulBase, unsigned long ulGen,
+ unsigned long ulMinFaultPeriod,
+ unsigned long ulFaultSenses);
+extern void PWMGenFaultTriggerSet(unsigned long ulBase, unsigned long ulGen,
+ unsigned long ulGroup,
+ unsigned long ulFaultTriggers);
+extern unsigned long PWMGenFaultTriggerGet(unsigned long ulBase,
+ unsigned long ulGen,
+ unsigned long ulGroup);
+extern unsigned long PWMGenFaultStatus(unsigned long ulBase,
+ unsigned long ulGen,
+ unsigned long ulGroup);
+extern void PWMGenFaultClear(unsigned long ulBase, unsigned long ulGen,
+ unsigned long ulGroup,
+ unsigned long ulFaultTriggers);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __PWM_H__
Property changes on: branches/eagle_mmc/src/platform/lm3s/pwm.h
___________________________________________________________________
Name: svn:executable
+ *
Added: branches/eagle_mmc/src/platform/lm3s/rom.h
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/rom.h 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lm3s/rom.h 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,2252 @@
+//*****************************************************************************
+//
+// rom.h - Macros to facilitate calling functions in the ROM.
+//
+// Copyright (c) 2007-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __ROM_H__
+#define __ROM_H__
+
+//*****************************************************************************
+//
+// Pointers to the main API tables.
+//
+//*****************************************************************************
+#define ROM_APITABLE ((unsigned long *)0x01000010)
+#define ROM_VERSION (ROM_APITABLE[0])
+#define ROM_UARTTABLE ((unsigned long *)(ROM_APITABLE[1]))
+#define ROM_SSITABLE ((unsigned long *)(ROM_APITABLE[2]))
+#define ROM_I2CTABLE ((unsigned long *)(ROM_APITABLE[3]))
+#define ROM_GPIOTABLE ((unsigned long *)(ROM_APITABLE[4]))
+#define ROM_ADCTABLE ((unsigned long *)(ROM_APITABLE[5]))
+#define ROM_COMPARATORTABLE ((unsigned long *)(ROM_APITABLE[6]))
+#define ROM_FLASHTABLE ((unsigned long *)(ROM_APITABLE[7]))
+#define ROM_PWMTABLE ((unsigned long *)(ROM_APITABLE[8]))
+#define ROM_QEITABLE ((unsigned long *)(ROM_APITABLE[9]))
+#define ROM_SYSTICKTABLE ((unsigned long *)(ROM_APITABLE[10]))
+#define ROM_TIMERTABLE ((unsigned long *)(ROM_APITABLE[11]))
+#define ROM_WATCHDOGTABLE ((unsigned long *)(ROM_APITABLE[12]))
+#define ROM_SYSCTLTABLE ((unsigned long *)(ROM_APITABLE[13]))
+#define ROM_INTERRUPTTABLE ((unsigned long *)(ROM_APITABLE[14]))
+#define ROM_ETHERNETTABLE ((unsigned long *)(ROM_APITABLE[15]))
+#define ROM_USBTABLE ((unsigned long *)(ROM_APITABLE[16]))
+#define ROM_UDMATABLE ((unsigned long *)(ROM_APITABLE[17]))
+#define ROM_CANTABLE ((unsigned long *)(ROM_APITABLE[18]))
+#define ROM_HIBERNATETABLE ((unsigned long *)(ROM_APITABLE[19]))
+#define ROM_MPUTABLE ((unsigned long *)(ROM_APITABLE[20]))
+#define ROM_SOFTWARETABLE ((unsigned long *)(ROM_APITABLE[21]))
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the ADC API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_ADCSequenceDataGet \
+ ((long (*)(unsigned long ulBase, \
+ unsigned long ulSequenceNum, \
+ unsigned long *pulBuffer))ROM_ADCTABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_ADCIntDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulSequenceNum))ROM_ADCTABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_ADCIntEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulSequenceNum))ROM_ADCTABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_ADCIntStatus \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned long ulSequenceNum, \
+ tBoolean bMasked))ROM_ADCTABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_ADCIntClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulSequenceNum))ROM_ADCTABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_ADCSequenceEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulSequenceNum))ROM_ADCTABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_ADCSequenceDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulSequenceNum))ROM_ADCTABLE[6])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_ADCSequenceConfigure \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulSequenceNum, \
+ unsigned long ulTrigger, \
+ unsigned long ulPriority))ROM_ADCTABLE[7])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_ADCSequenceStepConfigure \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulSequenceNum, \
+ unsigned long ulStep, \
+ unsigned long ulConfig))ROM_ADCTABLE[8])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_ADCSequenceOverflow \
+ ((long (*)(unsigned long ulBase, \
+ unsigned long ulSequenceNum))ROM_ADCTABLE[9])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_ADCSequenceOverflowClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulSequenceNum))ROM_ADCTABLE[10])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_ADCSequenceUnderflow \
+ ((long (*)(unsigned long ulBase, \
+ unsigned long ulSequenceNum))ROM_ADCTABLE[11])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_ADCSequenceUnderflowClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulSequenceNum))ROM_ADCTABLE[12])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_ADCProcessorTrigger \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulSequenceNum))ROM_ADCTABLE[13])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_ADCHardwareOversampleConfigure \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulFactor))ROM_ADCTABLE[14])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the CAN API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_CANIntClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntClr))ROM_CANTABLE[0])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_CANInit \
+ ((void (*)(unsigned long ulBase))ROM_CANTABLE[1])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_CANEnable \
+ ((void (*)(unsigned long ulBase))ROM_CANTABLE[2])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_CANDisable \
+ ((void (*)(unsigned long ulBase))ROM_CANTABLE[3])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_CANBitTimingSet \
+ ((void (*)(unsigned long ulBase, \
+ tCANBitClkParms *pClkParms))ROM_CANTABLE[4])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_CANBitTimingGet \
+ ((void (*)(unsigned long ulBase, \
+ tCANBitClkParms *pClkParms))ROM_CANTABLE[5])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_CANMessageSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulObjID, \
+ tCANMsgObject *pMsgObject, \
+ tMsgObjType eMsgType))ROM_CANTABLE[6])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_CANMessageGet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulObjID, \
+ tCANMsgObject *pMsgObject, \
+ tBoolean bClrPendingInt))ROM_CANTABLE[7])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_CANStatusGet \
+ ((unsigned long (*)(unsigned long ulBase, \
+ tCANStsReg eStatusReg))ROM_CANTABLE[8])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_CANMessageClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulObjID))ROM_CANTABLE[9])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_CANIntEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_CANTABLE[10])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_CANIntDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_CANTABLE[11])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_CANIntStatus \
+ ((unsigned long (*)(unsigned long ulBase, \
+ tCANIntStsReg eIntStsReg))ROM_CANTABLE[12])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_CANRetryGet \
+ ((tBoolean (*)(unsigned long ulBase))ROM_CANTABLE[13])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_CANRetrySet \
+ ((void (*)(unsigned long ulBase, \
+ tBoolean bAutoRetry))ROM_CANTABLE[14])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_CANErrCntrGet \
+ ((tBoolean (*)(unsigned long ulBase, \
+ unsigned long *pulRxCount, \
+ unsigned long *pulTxCount))ROM_CANTABLE[15])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the Comparator API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_ComparatorIntClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulComp))ROM_COMPARATORTABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_ComparatorConfigure \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulComp, \
+ unsigned long ulConfig))ROM_COMPARATORTABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_ComparatorRefSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulRef))ROM_COMPARATORTABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_ComparatorValueGet \
+ ((tBoolean (*)(unsigned long ulBase, \
+ unsigned long ulComp))ROM_COMPARATORTABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_ComparatorIntEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulComp))ROM_COMPARATORTABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_ComparatorIntDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulComp))ROM_COMPARATORTABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_ComparatorIntStatus \
+ ((tBoolean (*)(unsigned long ulBase, \
+ unsigned long ulComp, \
+ tBoolean bMasked))ROM_COMPARATORTABLE[6])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the Ethernet API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_EthernetIntClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_ETHERNETTABLE[0])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_EthernetInitExpClk \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulEthClk))ROM_ETHERNETTABLE[1])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_EthernetConfigSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulConfig))ROM_ETHERNETTABLE[2])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_EthernetConfigGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_ETHERNETTABLE[3])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_EthernetMACAddrSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned char *pucMACAddr))ROM_ETHERNETTABLE[4])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_EthernetMACAddrGet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned char *pucMACAddr))ROM_ETHERNETTABLE[5])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_EthernetEnable \
+ ((void (*)(unsigned long ulBase))ROM_ETHERNETTABLE[6])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_EthernetDisable \
+ ((void (*)(unsigned long ulBase))ROM_ETHERNETTABLE[7])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_EthernetPacketAvail \
+ ((tBoolean (*)(unsigned long ulBase))ROM_ETHERNETTABLE[8])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_EthernetSpaceAvail \
+ ((tBoolean (*)(unsigned long ulBase))ROM_ETHERNETTABLE[9])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_EthernetPacketGetNonBlocking \
+ ((long (*)(unsigned long ulBase, \
+ unsigned char *pucBuf, \
+ long lBufLen))ROM_ETHERNETTABLE[10])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_EthernetPacketGet \
+ ((long (*)(unsigned long ulBase, \
+ unsigned char *pucBuf, \
+ long lBufLen))ROM_ETHERNETTABLE[11])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_EthernetPacketPutNonBlocking \
+ ((long (*)(unsigned long ulBase, \
+ unsigned char *pucBuf, \
+ long lBufLen))ROM_ETHERNETTABLE[12])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_EthernetPacketPut \
+ ((long (*)(unsigned long ulBase, \
+ unsigned char *pucBuf, \
+ long lBufLen))ROM_ETHERNETTABLE[13])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_EthernetIntEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_ETHERNETTABLE[14])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_EthernetIntDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_ETHERNETTABLE[15])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_EthernetIntStatus \
+ ((unsigned long (*)(unsigned long ulBase, \
+ tBoolean bMasked))ROM_ETHERNETTABLE[16])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_EthernetPHYWrite \
+ ((void (*)(unsigned long ulBase, \
+ unsigned char ucRegAddr, \
+ unsigned long ulData))ROM_ETHERNETTABLE[17])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_EthernetPHYRead \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned char ucRegAddr))ROM_ETHERNETTABLE[18])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_UpdateEthernet \
+ ((void (*)(unsigned long ulClock))ROM_ETHERNETTABLE[19])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the Flash API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_FlashProgram \
+ ((long (*)(unsigned long *pulData, \
+ unsigned long ulAddress, \
+ unsigned long ulCount))ROM_FLASHTABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_FlashUsecGet \
+ ((unsigned long (*)(void))ROM_FLASHTABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_FlashUsecSet \
+ ((void (*)(unsigned long ulClocks))ROM_FLASHTABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_FlashErase \
+ ((long (*)(unsigned long ulAddress))ROM_FLASHTABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_FlashProtectGet \
+ ((tFlashProtection (*)(unsigned long ulAddress))ROM_FLASHTABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_FlashProtectSet \
+ ((long (*)(unsigned long ulAddress, \
+ tFlashProtection eProtect))ROM_FLASHTABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_FlashProtectSave \
+ ((long (*)(void))ROM_FLASHTABLE[6])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_FlashUserGet \
+ ((long (*)(unsigned long *pulUser0, \
+ unsigned long *pulUser1))ROM_FLASHTABLE[7])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_FlashUserSet \
+ ((long (*)(unsigned long ulUser0, \
+ unsigned long ulUser1))ROM_FLASHTABLE[8])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_FlashUserSave \
+ ((long (*)(void))ROM_FLASHTABLE[9])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_FlashIntEnable \
+ ((void (*)(unsigned long ulIntFlags))ROM_FLASHTABLE[10])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_FlashIntDisable \
+ ((void (*)(unsigned long ulIntFlags))ROM_FLASHTABLE[11])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_FlashIntGetStatus \
+ ((unsigned long (*)(tBoolean bMasked))ROM_FLASHTABLE[12])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_FlashIntClear \
+ ((void (*)(unsigned long ulIntFlags))ROM_FLASHTABLE[13])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the GPIO API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_GPIOPinWrite \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins, \
+ unsigned char ucVal))ROM_GPIOTABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_GPIODirModeSet \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins, \
+ unsigned long ulPinIO))ROM_GPIOTABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_GPIODirModeGet \
+ ((unsigned long (*)(unsigned long ulPort, \
+ unsigned char ucPin))ROM_GPIOTABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_GPIOIntTypeSet \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins, \
+ unsigned long ulIntType))ROM_GPIOTABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_GPIOIntTypeGet \
+ ((unsigned long (*)(unsigned long ulPort, \
+ unsigned char ucPin))ROM_GPIOTABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_GPIOPadConfigSet \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins, \
+ unsigned long ulStrength, \
+ unsigned long ulPadType))ROM_GPIOTABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_GPIOPadConfigGet \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPin, \
+ unsigned long *pulStrength, \
+ unsigned long *pulPadType))ROM_GPIOTABLE[6])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_GPIOPinIntEnable \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins))ROM_GPIOTABLE[7])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_GPIOPinIntDisable \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins))ROM_GPIOTABLE[8])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_GPIOPinIntStatus \
+ ((long (*)(unsigned long ulPort, \
+ tBoolean bMasked))ROM_GPIOTABLE[9])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_GPIOPinIntClear \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins))ROM_GPIOTABLE[10])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_GPIOPinRead \
+ ((long (*)(unsigned long ulPort, \
+ unsigned char ucPins))ROM_GPIOTABLE[11])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_GPIOPinTypeCAN \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins))ROM_GPIOTABLE[12])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_GPIOPinTypeComparator \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins))ROM_GPIOTABLE[13])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_GPIOPinTypeGPIOInput \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins))ROM_GPIOTABLE[14])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_GPIOPinTypeGPIOOutput \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins))ROM_GPIOTABLE[15])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_GPIOPinTypeI2C \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins))ROM_GPIOTABLE[16])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_GPIOPinTypePWM \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins))ROM_GPIOTABLE[17])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_GPIOPinTypeQEI \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins))ROM_GPIOTABLE[18])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_GPIOPinTypeSSI \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins))ROM_GPIOTABLE[19])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_GPIOPinTypeTimer \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins))ROM_GPIOTABLE[20])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_GPIOPinTypeUART \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins))ROM_GPIOTABLE[21])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_GPIOPinTypeGPIOOutputOD \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins))ROM_GPIOTABLE[22])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_GPIOPinTypeADC \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins))ROM_GPIOTABLE[23])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_GPIOPinTypeUSBDigital \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins))ROM_GPIOTABLE[24])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the Hibernate API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_HibernateIntClear \
+ ((void (*)(unsigned long ulIntFlags))ROM_HIBERNATETABLE[0])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_HibernateEnableExpClk \
+ ((void (*)(unsigned long ulHibClk))ROM_HIBERNATETABLE[1])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_HibernateDisable \
+ ((void (*)(void))ROM_HIBERNATETABLE[2])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_HibernateClockSelect \
+ ((void (*)(unsigned long ulClockInput))ROM_HIBERNATETABLE[3])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_HibernateRTCEnable \
+ ((void (*)(void))ROM_HIBERNATETABLE[4])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_HibernateRTCDisable \
+ ((void (*)(void))ROM_HIBERNATETABLE[5])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_HibernateWakeSet \
+ ((void (*)(unsigned long ulWakeFlags))ROM_HIBERNATETABLE[6])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_HibernateWakeGet \
+ ((unsigned long (*)(void))ROM_HIBERNATETABLE[7])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_HibernateLowBatSet \
+ ((void (*)(unsigned long ulLowBatFlags))ROM_HIBERNATETABLE[8])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_HibernateLowBatGet \
+ ((unsigned long (*)(void))ROM_HIBERNATETABLE[9])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_HibernateRTCSet \
+ ((void (*)(unsigned long ulRTCValue))ROM_HIBERNATETABLE[10])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_HibernateRTCGet \
+ ((unsigned long (*)(void))ROM_HIBERNATETABLE[11])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_HibernateRTCMatch0Set \
+ ((void (*)(unsigned long ulMatch))ROM_HIBERNATETABLE[12])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_HibernateRTCMatch0Get \
+ ((unsigned long (*)(void))ROM_HIBERNATETABLE[13])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_HibernateRTCMatch1Set \
+ ((void (*)(unsigned long ulMatch))ROM_HIBERNATETABLE[14])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_HibernateRTCMatch1Get \
+ ((unsigned long (*)(void))ROM_HIBERNATETABLE[15])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_HibernateRTCTrimSet \
+ ((void (*)(unsigned long ulTrim))ROM_HIBERNATETABLE[16])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_HibernateRTCTrimGet \
+ ((unsigned long (*)(void))ROM_HIBERNATETABLE[17])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_HibernateDataSet \
+ ((void (*)(unsigned long *pulData, \
+ unsigned long ulCount))ROM_HIBERNATETABLE[18])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_HibernateDataGet \
+ ((void (*)(unsigned long *pulData, \
+ unsigned long ulCount))ROM_HIBERNATETABLE[19])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_HibernateRequest \
+ ((void (*)(void))ROM_HIBERNATETABLE[20])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_HibernateIntEnable \
+ ((void (*)(unsigned long ulIntFlags))ROM_HIBERNATETABLE[21])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_HibernateIntDisable \
+ ((void (*)(unsigned long ulIntFlags))ROM_HIBERNATETABLE[22])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_HibernateIntStatus \
+ ((unsigned long (*)(tBoolean bMasked))ROM_HIBERNATETABLE[23])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_HibernateIsActive \
+ ((unsigned int (*)(void))ROM_HIBERNATETABLE[24])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the I2C API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_I2CMasterDataPut \
+ ((void (*)(unsigned long ulBase, \
+ unsigned char ucData))ROM_I2CTABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_I2CMasterInitExpClk \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulI2CClk, \
+ tBoolean bFast))ROM_I2CTABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_I2CSlaveInit \
+ ((void (*)(unsigned long ulBase, \
+ unsigned char ucSlaveAddr))ROM_I2CTABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_I2CMasterEnable \
+ ((void (*)(unsigned long ulBase))ROM_I2CTABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_I2CSlaveEnable \
+ ((void (*)(unsigned long ulBase))ROM_I2CTABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_I2CMasterDisable \
+ ((void (*)(unsigned long ulBase))ROM_I2CTABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_I2CSlaveDisable \
+ ((void (*)(unsigned long ulBase))ROM_I2CTABLE[6])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_I2CMasterIntEnable \
+ ((void (*)(unsigned long ulBase))ROM_I2CTABLE[7])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_I2CSlaveIntEnable \
+ ((void (*)(unsigned long ulBase))ROM_I2CTABLE[8])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_I2CMasterIntDisable \
+ ((void (*)(unsigned long ulBase))ROM_I2CTABLE[9])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_I2CSlaveIntDisable \
+ ((void (*)(unsigned long ulBase))ROM_I2CTABLE[10])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_I2CMasterIntStatus \
+ ((tBoolean (*)(unsigned long ulBase, \
+ tBoolean bMasked))ROM_I2CTABLE[11])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_I2CSlaveIntStatus \
+ ((tBoolean (*)(unsigned long ulBase, \
+ tBoolean bMasked))ROM_I2CTABLE[12])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_I2CMasterIntClear \
+ ((void (*)(unsigned long ulBase))ROM_I2CTABLE[13])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_I2CSlaveIntClear \
+ ((void (*)(unsigned long ulBase))ROM_I2CTABLE[14])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_I2CMasterSlaveAddrSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned char ucSlaveAddr, \
+ tBoolean bReceive))ROM_I2CTABLE[15])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_I2CMasterBusy \
+ ((tBoolean (*)(unsigned long ulBase))ROM_I2CTABLE[16])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_I2CMasterBusBusy \
+ ((tBoolean (*)(unsigned long ulBase))ROM_I2CTABLE[17])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_I2CMasterControl \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulCmd))ROM_I2CTABLE[18])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_I2CMasterErr \
+ ((unsigned long (*)(unsigned long ulBase))ROM_I2CTABLE[19])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_I2CMasterDataGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_I2CTABLE[20])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_I2CSlaveStatus \
+ ((unsigned long (*)(unsigned long ulBase))ROM_I2CTABLE[21])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_I2CSlaveDataPut \
+ ((void (*)(unsigned long ulBase, \
+ unsigned char ucData))ROM_I2CTABLE[22])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_I2CSlaveDataGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_I2CTABLE[23])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_UpdateI2C \
+ ((void (*)(void))ROM_I2CTABLE[24])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the Interrupt API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_IntEnable \
+ ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[0])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_IntMasterEnable \
+ ((tBoolean (*)(void))ROM_INTERRUPTTABLE[1])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_IntMasterDisable \
+ ((tBoolean (*)(void))ROM_INTERRUPTTABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_IntDisable \
+ ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_IntPriorityGroupingSet \
+ ((void (*)(unsigned long ulBits))ROM_INTERRUPTTABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_IntPriorityGroupingGet \
+ ((unsigned long (*)(void))ROM_INTERRUPTTABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_IntPrioritySet \
+ ((void (*)(unsigned long ulInterrupt, \
+ unsigned char ucPriority))ROM_INTERRUPTTABLE[6])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_IntPriorityGet \
+ ((long (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[7])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the MPU API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_MPUEnable \
+ ((void (*)(unsigned long ulMPUConfig))ROM_MPUTABLE[0])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_MPUDisable \
+ ((void (*)(void))ROM_MPUTABLE[1])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_MPURegionCountGet \
+ ((unsigned long (*)(void))ROM_MPUTABLE[2])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_MPURegionEnable \
+ ((void (*)(unsigned long ulRegion))ROM_MPUTABLE[3])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_MPURegionDisable \
+ ((void (*)(unsigned long ulRegion))ROM_MPUTABLE[4])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_MPURegionSet \
+ ((void (*)(unsigned long ulRegion, \
+ unsigned long ulAddr, \
+ unsigned long ulFlags))ROM_MPUTABLE[5])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_MPURegionGet \
+ ((void (*)(unsigned long ulRegion, \
+ unsigned long *pulAddr, \
+ unsigned long *pulFlags))ROM_MPUTABLE[6])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the PWM API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_PWMPulseWidthSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulPWMOut, \
+ unsigned long ulWidth))ROM_PWMTABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_PWMGenConfigure \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulGen, \
+ unsigned long ulConfig))ROM_PWMTABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_PWMGenPeriodSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulGen, \
+ unsigned long ulPeriod))ROM_PWMTABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_PWMGenPeriodGet \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned long ulGen))ROM_PWMTABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_PWMGenEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulGen))ROM_PWMTABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_PWMGenDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulGen))ROM_PWMTABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_PWMPulseWidthGet \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned long ulPWMOut))ROM_PWMTABLE[6])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_PWMDeadBandEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulGen, \
+ unsigned short usRise, \
+ unsigned short usFall))ROM_PWMTABLE[7])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_PWMDeadBandDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulGen))ROM_PWMTABLE[8])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_PWMSyncUpdate \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulGenBits))ROM_PWMTABLE[9])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_PWMSyncTimeBase \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulGenBits))ROM_PWMTABLE[10])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_PWMOutputState \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulPWMOutBits, \
+ tBoolean bEnable))ROM_PWMTABLE[11])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_PWMOutputInvert \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulPWMOutBits, \
+ tBoolean bInvert))ROM_PWMTABLE[12])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_PWMOutputFault \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulPWMOutBits, \
+ tBoolean bFaultSuppress))ROM_PWMTABLE[13])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_PWMGenIntTrigEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulGen, \
+ unsigned long ulIntTrig))ROM_PWMTABLE[14])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_PWMGenIntTrigDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulGen, \
+ unsigned long ulIntTrig))ROM_PWMTABLE[15])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_PWMGenIntStatus \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned long ulGen, \
+ tBoolean bMasked))ROM_PWMTABLE[16])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_PWMGenIntClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulGen, \
+ unsigned long ulInts))ROM_PWMTABLE[17])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_PWMIntEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulGenFault))ROM_PWMTABLE[18])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_PWMIntDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulGenFault))ROM_PWMTABLE[19])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_PWMFaultIntClear \
+ ((void (*)(unsigned long ulBase))ROM_PWMTABLE[20])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_PWMIntStatus \
+ ((unsigned long (*)(unsigned long ulBase, \
+ tBoolean bMasked))ROM_PWMTABLE[21])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_PWMOutputFaultLevel \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulPWMOutBits, \
+ tBoolean bDriveHigh))ROM_PWMTABLE[22])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_PWMFaultIntClearExt \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulFaultInts))ROM_PWMTABLE[23])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_PWMGenFaultConfigure \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulGen, \
+ unsigned long ulMinFaultPeriod, \
+ unsigned long ulFaultSenses))ROM_PWMTABLE[24])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_PWMGenFaultTriggerSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulGen, \
+ unsigned long ulGroup, \
+ unsigned long ulFaultTriggers))ROM_PWMTABLE[25])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_PWMGenFaultTriggerGet \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned long ulGen, \
+ unsigned long ulGroup))ROM_PWMTABLE[26])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_PWMGenFaultStatus \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned long ulGen, \
+ unsigned long ulGroup))ROM_PWMTABLE[27])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_PWMGenFaultClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulGen, \
+ unsigned long ulGroup, \
+ unsigned long ulFaultTriggers))ROM_PWMTABLE[28])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the QEI API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_QEIPositionGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_QEITABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_QEIEnable \
+ ((void (*)(unsigned long ulBase))ROM_QEITABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_QEIDisable \
+ ((void (*)(unsigned long ulBase))ROM_QEITABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_QEIConfigure \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulConfig, \
+ unsigned long ulMaxPosition))ROM_QEITABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_QEIPositionSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulPosition))ROM_QEITABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_QEIDirectionGet \
+ ((long (*)(unsigned long ulBase))ROM_QEITABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_QEIErrorGet \
+ ((tBoolean (*)(unsigned long ulBase))ROM_QEITABLE[6])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_QEIVelocityEnable \
+ ((void (*)(unsigned long ulBase))ROM_QEITABLE[7])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_QEIVelocityDisable \
+ ((void (*)(unsigned long ulBase))ROM_QEITABLE[8])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_QEIVelocityConfigure \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulPreDiv, \
+ unsigned long ulPeriod))ROM_QEITABLE[9])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_QEIVelocityGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_QEITABLE[10])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_QEIIntEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_QEITABLE[11])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_QEIIntDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_QEITABLE[12])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_QEIIntStatus \
+ ((unsigned long (*)(unsigned long ulBase, \
+ tBoolean bMasked))ROM_QEITABLE[13])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_QEIIntClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_QEITABLE[14])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the SSI API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SSIDataPut \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulData))ROM_SSITABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SSIConfigSetExpClk \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulSSIClk, \
+ unsigned long ulProtocol, \
+ unsigned long ulMode, \
+ unsigned long ulBitRate, \
+ unsigned long ulDataWidth))ROM_SSITABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SSIEnable \
+ ((void (*)(unsigned long ulBase))ROM_SSITABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SSIDisable \
+ ((void (*)(unsigned long ulBase))ROM_SSITABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SSIIntEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_SSITABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SSIIntDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_SSITABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SSIIntStatus \
+ ((unsigned long (*)(unsigned long ulBase, \
+ tBoolean bMasked))ROM_SSITABLE[6])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SSIIntClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_SSITABLE[7])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SSIDataPutNonBlocking \
+ ((long (*)(unsigned long ulBase, \
+ unsigned long ulData))ROM_SSITABLE[8])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SSIDataGet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long *pulData))ROM_SSITABLE[9])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SSIDataGetNonBlocking \
+ ((long (*)(unsigned long ulBase, \
+ unsigned long *pulData))ROM_SSITABLE[10])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_UpdateSSI \
+ ((void (*)(void))ROM_SSITABLE[11])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SSIDMAEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulDMAFlags))ROM_SSITABLE[12])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SSIDMADisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulDMAFlags))ROM_SSITABLE[13])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the SysCtl API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlSleep \
+ ((void (*)(void))ROM_SYSCTLTABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlSRAMSizeGet \
+ ((unsigned long (*)(void))ROM_SYSCTLTABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlFlashSizeGet \
+ ((unsigned long (*)(void))ROM_SYSCTLTABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlPinPresent \
+ ((tBoolean (*)(unsigned long ulPin))ROM_SYSCTLTABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlPeripheralPresent \
+ ((tBoolean (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlPeripheralReset \
+ ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlPeripheralEnable \
+ ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[6])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlPeripheralDisable \
+ ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[7])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlPeripheralSleepEnable \
+ ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[8])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlPeripheralSleepDisable \
+ ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[9])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlPeripheralDeepSleepEnable \
+ ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[10])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlPeripheralDeepSleepDisable \
+ ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[11])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlPeripheralClockGating \
+ ((void (*)(tBoolean bEnable))ROM_SYSCTLTABLE[12])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlIntEnable \
+ ((void (*)(unsigned long ulInts))ROM_SYSCTLTABLE[13])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlIntDisable \
+ ((void (*)(unsigned long ulInts))ROM_SYSCTLTABLE[14])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlIntClear \
+ ((void (*)(unsigned long ulInts))ROM_SYSCTLTABLE[15])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlIntStatus \
+ ((unsigned long (*)(tBoolean bMasked))ROM_SYSCTLTABLE[16])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlLDOSet \
+ ((void (*)(unsigned long ulVoltage))ROM_SYSCTLTABLE[17])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlLDOGet \
+ ((unsigned long (*)(void))ROM_SYSCTLTABLE[18])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlReset \
+ ((void (*)(void))ROM_SYSCTLTABLE[19])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlDeepSleep \
+ ((void (*)(void))ROM_SYSCTLTABLE[20])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlResetCauseGet \
+ ((unsigned long (*)(void))ROM_SYSCTLTABLE[21])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlResetCauseClear \
+ ((void (*)(unsigned long ulCauses))ROM_SYSCTLTABLE[22])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlClockSet \
+ ((void (*)(unsigned long ulConfig))ROM_SYSCTLTABLE[23])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlClockGet \
+ ((unsigned long (*)(void))ROM_SYSCTLTABLE[24])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlPWMClockSet \
+ ((void (*)(unsigned long ulConfig))ROM_SYSCTLTABLE[25])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlPWMClockGet \
+ ((unsigned long (*)(void))ROM_SYSCTLTABLE[26])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlADCSpeedSet \
+ ((void (*)(unsigned long ulSpeed))ROM_SYSCTLTABLE[27])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlADCSpeedGet \
+ ((unsigned long (*)(void))ROM_SYSCTLTABLE[28])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlGPIOAHBEnable \
+ ((void (*)(unsigned long ulGPIOPeripheral))ROM_SYSCTLTABLE[29])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlGPIOAHBDisable \
+ ((void (*)(unsigned long ulGPIOPeripheral))ROM_SYSCTLTABLE[30])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlUSBPLLEnable \
+ ((void (*)(void))ROM_SYSCTLTABLE[31])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlUSBPLLDisable \
+ ((void (*)(void))ROM_SYSCTLTABLE[32])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the SysTick API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysTickValueGet \
+ ((unsigned long (*)(void))ROM_SYSTICKTABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysTickEnable \
+ ((void (*)(void))ROM_SYSTICKTABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysTickDisable \
+ ((void (*)(void))ROM_SYSTICKTABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysTickIntEnable \
+ ((void (*)(void))ROM_SYSTICKTABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysTickIntDisable \
+ ((void (*)(void))ROM_SYSTICKTABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysTickPeriodSet \
+ ((void (*)(unsigned long ulPeriod))ROM_SYSTICKTABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysTickPeriodGet \
+ ((unsigned long (*)(void))ROM_SYSTICKTABLE[6])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the Timer API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_TimerIntClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_TIMERTABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_TimerEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulTimer))ROM_TIMERTABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_TimerDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulTimer))ROM_TIMERTABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_TimerConfigure \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulConfig))ROM_TIMERTABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_TimerControlLevel \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulTimer, \
+ tBoolean bInvert))ROM_TIMERTABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_TimerControlTrigger \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulTimer, \
+ tBoolean bEnable))ROM_TIMERTABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_TimerControlEvent \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulTimer, \
+ unsigned long ulEvent))ROM_TIMERTABLE[6])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_TimerControlStall \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulTimer, \
+ tBoolean bStall))ROM_TIMERTABLE[7])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_TimerRTCEnable \
+ ((void (*)(unsigned long ulBase))ROM_TIMERTABLE[8])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_TimerRTCDisable \
+ ((void (*)(unsigned long ulBase))ROM_TIMERTABLE[9])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_TimerPrescaleSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulTimer, \
+ unsigned long ulValue))ROM_TIMERTABLE[10])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_TimerPrescaleGet \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned long ulTimer))ROM_TIMERTABLE[11])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_TimerLoadSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulTimer, \
+ unsigned long ulValue))ROM_TIMERTABLE[14])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_TimerLoadGet \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned long ulTimer))ROM_TIMERTABLE[15])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_TimerValueGet \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned long ulTimer))ROM_TIMERTABLE[16])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_TimerMatchSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulTimer, \
+ unsigned long ulValue))ROM_TIMERTABLE[17])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_TimerMatchGet \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned long ulTimer))ROM_TIMERTABLE[18])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_TimerIntEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_TIMERTABLE[19])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_TimerIntDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_TIMERTABLE[20])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_TimerIntStatus \
+ ((unsigned long (*)(unsigned long ulBase, \
+ tBoolean bMasked))ROM_TIMERTABLE[21])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the UART API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_UARTCharPut \
+ ((void (*)(unsigned long ulBase, \
+ unsigned char ucData))ROM_UARTTABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_UARTParityModeSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulParity))ROM_UARTTABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_UARTParityModeGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_UARTFIFOLevelSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulTxLevel, \
+ unsigned long ulRxLevel))ROM_UARTTABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_UARTFIFOLevelGet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long *pulTxLevel, \
+ unsigned long *pulRxLevel))ROM_UARTTABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_UARTConfigSetExpClk \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulUARTClk, \
+ unsigned long ulBaud, \
+ unsigned long ulConfig))ROM_UARTTABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_UARTConfigGetExpClk \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulUARTClk, \
+ unsigned long *pulBaud, \
+ unsigned long *pulConfig))ROM_UARTTABLE[6])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_UARTEnable \
+ ((void (*)(unsigned long ulBase))ROM_UARTTABLE[7])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_UARTDisable \
+ ((void (*)(unsigned long ulBase))ROM_UARTTABLE[8])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_UARTEnableSIR \
+ ((void (*)(unsigned long ulBase, \
+ tBoolean bLowPower))ROM_UARTTABLE[9])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_UARTDisableSIR \
+ ((void (*)(unsigned long ulBase))ROM_UARTTABLE[10])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_UARTCharsAvail \
+ ((tBoolean (*)(unsigned long ulBase))ROM_UARTTABLE[11])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_UARTSpaceAvail \
+ ((tBoolean (*)(unsigned long ulBase))ROM_UARTTABLE[12])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_UARTCharGetNonBlocking \
+ ((long (*)(unsigned long ulBase))ROM_UARTTABLE[13])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_UARTCharGet \
+ ((long (*)(unsigned long ulBase))ROM_UARTTABLE[14])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_UARTCharPutNonBlocking \
+ ((tBoolean (*)(unsigned long ulBase, \
+ unsigned char ucData))ROM_UARTTABLE[15])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_UARTBreakCtl \
+ ((void (*)(unsigned long ulBase, \
+ tBoolean bBreakState))ROM_UARTTABLE[16])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_UARTIntEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_UARTTABLE[17])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_UARTIntDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_UARTTABLE[18])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_UARTIntStatus \
+ ((unsigned long (*)(unsigned long ulBase, \
+ tBoolean bMasked))ROM_UARTTABLE[19])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_UARTIntClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_UARTTABLE[20])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_UpdateUART \
+ ((void (*)(void))ROM_UARTTABLE[21])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_UARTDMAEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulDMAFlags))ROM_UARTTABLE[22])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_UARTDMADisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulDMAFlags))ROM_UARTTABLE[23])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the uDMA API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_uDMAChannelTransferSet \
+ ((void (*)(unsigned long ulChannel, \
+ unsigned long ulMode, \
+ void *pvSrcAddr, \
+ void *pvDstAddr, \
+ unsigned long ulTransferSize))ROM_UDMATABLE[0])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_uDMAEnable \
+ ((void (*)(void))ROM_UDMATABLE[1])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_uDMADisable \
+ ((void (*)(void))ROM_UDMATABLE[2])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_uDMAErrorStatusGet \
+ ((unsigned long (*)(void))ROM_UDMATABLE[3])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_uDMAErrorStatusClear \
+ ((void (*)(void))ROM_UDMATABLE[4])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_uDMAChannelEnable \
+ ((void (*)(unsigned long ulChannel))ROM_UDMATABLE[5])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_uDMAChannelDisable \
+ ((void (*)(unsigned long ulChannel))ROM_UDMATABLE[6])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_uDMAChannelIsEnabled \
+ ((tBoolean (*)(unsigned long ulChannel))ROM_UDMATABLE[7])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_uDMAControlBaseSet \
+ ((void (*)(void *pControlTable))ROM_UDMATABLE[8])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_uDMAControlBaseGet \
+ ((void * (*)(void))ROM_UDMATABLE[9])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_uDMAChannelRequest \
+ ((void (*)(unsigned long ulChannel))ROM_UDMATABLE[10])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_uDMAChannelAttributeEnable \
+ ((void (*)(unsigned long ulChannel, \
+ unsigned long ulAttr))ROM_UDMATABLE[11])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_uDMAChannelAttributeDisable \
+ ((void (*)(unsigned long ulChannel, \
+ unsigned long ulAttr))ROM_UDMATABLE[12])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_uDMAChannelAttributeGet \
+ ((unsigned long (*)(unsigned long ulChannel))ROM_UDMATABLE[13])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_uDMAChannelControlSet \
+ ((void (*)(unsigned long ulChannel, \
+ unsigned long ulControl))ROM_UDMATABLE[14])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_uDMAChannelSizeGet \
+ ((unsigned long (*)(unsigned long ulChannel))ROM_UDMATABLE[15])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_uDMAChannelModeGet \
+ ((unsigned long (*)(unsigned long ulChannel))ROM_UDMATABLE[16])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the USB API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBIntStatus \
+ ((unsigned long (*)(unsigned long ulBase))ROM_USBTABLE[0])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBDevAddrGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_USBTABLE[1])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBDevAddrSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulAddress))ROM_USBTABLE[2])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBDevConnect \
+ ((void (*)(unsigned long ulBase))ROM_USBTABLE[3])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBDevDisconnect \
+ ((void (*)(unsigned long ulBase))ROM_USBTABLE[4])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBDevEndpointConfig \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint, \
+ unsigned long ulMaxPacketSize, \
+ unsigned long ulFlags))ROM_USBTABLE[5])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBDevEndpointDataAck \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint, \
+ tBoolean bIsLastPacket))ROM_USBTABLE[6])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBDevEndpointStall \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint, \
+ unsigned long ulFlags))ROM_USBTABLE[7])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBDevEndpointStallClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint, \
+ unsigned long ulFlags))ROM_USBTABLE[8])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBDevEndpointStatusClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint, \
+ unsigned long ulFlags))ROM_USBTABLE[9])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBEndpointDataGet \
+ ((long (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint, \
+ unsigned char *pucData, \
+ unsigned long *pulSize))ROM_USBTABLE[10])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBEndpointDataPut \
+ ((long (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint, \
+ unsigned char *pucData, \
+ unsigned long ulSize))ROM_USBTABLE[11])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBEndpointDataSend \
+ ((long (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint, \
+ unsigned long ulTransType))ROM_USBTABLE[12])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBEndpointDataToggleClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint, \
+ unsigned long ulFlags))ROM_USBTABLE[13])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBEndpointStatus \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint))ROM_USBTABLE[14])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBFIFOAddrGet \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint))ROM_USBTABLE[15])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBFIFOConfigGet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint, \
+ unsigned long *pulFIFOAddress, \
+ unsigned long *pulFIFOSize, \
+ unsigned long ulFlags))ROM_USBTABLE[16])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBFIFOConfigSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint, \
+ unsigned long ulFIFOAddress, \
+ unsigned long ulFIFOSize, \
+ unsigned long ulFlags))ROM_USBTABLE[17])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBFIFOFlush \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint, \
+ unsigned long ulFlags))ROM_USBTABLE[18])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBFrameNumberGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_USBTABLE[19])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBHostAddrGet \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint, \
+ unsigned long ulFlags))ROM_USBTABLE[20])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBHostAddrSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint, \
+ unsigned long ulAddr, \
+ unsigned long ulFlags))ROM_USBTABLE[21])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBHostEndpointConfig \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint, \
+ unsigned long ulMaxPacketSize, \
+ unsigned long ulNAKPollInterval, \
+ unsigned long ulTargetEndpoint, \
+ unsigned long ulFlags))ROM_USBTABLE[22])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBHostEndpointDataAck \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint))ROM_USBTABLE[23])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBHostEndpointDataToggle \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint, \
+ tBoolean bDataToggle, \
+ unsigned long ulFlags))ROM_USBTABLE[24])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBHostEndpointStatusClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint, \
+ unsigned long ulFlags))ROM_USBTABLE[25])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBHostHubAddrGet \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint, \
+ unsigned long ulFlags))ROM_USBTABLE[26])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBHostHubAddrSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint, \
+ unsigned long ulAddr, \
+ unsigned long ulFlags))ROM_USBTABLE[27])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBHostPwrDisable \
+ ((void (*)(unsigned long ulBase))ROM_USBTABLE[28])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBHostPwrEnable \
+ ((void (*)(unsigned long ulBase))ROM_USBTABLE[29])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBHostPwrFaultConfig \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulFlags))ROM_USBTABLE[30])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBHostPwrFaultDisable \
+ ((void (*)(unsigned long ulBase))ROM_USBTABLE[31])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBHostPwrFaultEnable \
+ ((void (*)(unsigned long ulBase))ROM_USBTABLE[32])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBHostRequestIN \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint))ROM_USBTABLE[33])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBHostRequestStatus \
+ ((void (*)(unsigned long ulBase))ROM_USBTABLE[34])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBHostReset \
+ ((void (*)(unsigned long ulBase, \
+ tBoolean bStart))ROM_USBTABLE[35])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBHostResume \
+ ((void (*)(unsigned long ulBase, \
+ tBoolean bStart))ROM_USBTABLE[36])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBHostSpeedGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_USBTABLE[37])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBHostSuspend \
+ ((void (*)(unsigned long ulBase))ROM_USBTABLE[38])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBIntDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_USBTABLE[39])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBIntEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_USBTABLE[40])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the Watchdog API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_WatchdogIntClear \
+ ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_WatchdogRunning \
+ ((tBoolean (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_WatchdogEnable \
+ ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_WatchdogResetEnable \
+ ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_WatchdogResetDisable \
+ ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_WatchdogLock \
+ ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_WatchdogUnlock \
+ ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[6])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_WatchdogLockState \
+ ((tBoolean (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[7])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_WatchdogReloadSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulLoadVal))ROM_WATCHDOGTABLE[8])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_WatchdogReloadGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[9])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_WatchdogValueGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[10])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_WatchdogIntEnable \
+ ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[11])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_WatchdogIntStatus \
+ ((unsigned long (*)(unsigned long ulBase, \
+ tBoolean bMasked))ROM_WATCHDOGTABLE[12])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_WatchdogStallEnable \
+ ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[13])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_WatchdogStallDisable \
+ ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[14])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the Software API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_Crc16Array \
+ ((unsigned short (*)(unsigned long ulWordLen, \
+ unsigned long *pulData))ROM_SOFTWARETABLE[1])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_Crc16Array3 \
+ ((void (*)(unsigned long ulWordLen, \
+ unsigned long *pulData, \
+ unsigned short *pusCrc3))ROM_SOFTWARETABLE[2])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_pvAESTable \
+ ((void *)&(ROM_SOFTWARETABLE[7]))
+#endif
+
+#endif // __ROM_H__
Property changes on: branches/eagle_mmc/src/platform/lm3s/rom.h
___________________________________________________________________
Name: svn:executable
+ *
Added: branches/eagle_mmc/src/platform/lm3s/rom_map.h
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/rom_map.h 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lm3s/rom_map.h 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,2763 @@
+//*****************************************************************************
+//
+// rom_map.h - Macros to facilitate calling functions in the ROM when they are
+// available and in flash otherwise.
+//
+// Copyright (c) 2008-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __ROM_MAP_H__
+#define __ROM_MAP_H__
+
+//*****************************************************************************
+//
+// Macros for the ADC API.
+//
+//*****************************************************************************
+#ifdef ROM_ADCSequenceDataGet
+#define MAP_ADCSequenceDataGet \
+ ROM_ADCSequenceDataGet
+#else
+#define MAP_ADCSequenceDataGet \
+ ADCSequenceDataGet
+#endif
+#ifdef ROM_ADCIntDisable
+#define MAP_ADCIntDisable \
+ ROM_ADCIntDisable
+#else
+#define MAP_ADCIntDisable \
+ ADCIntDisable
+#endif
+#ifdef ROM_ADCIntEnable
+#define MAP_ADCIntEnable \
+ ROM_ADCIntEnable
+#else
+#define MAP_ADCIntEnable \
+ ADCIntEnable
+#endif
+#ifdef ROM_ADCIntStatus
+#define MAP_ADCIntStatus \
+ ROM_ADCIntStatus
+#else
+#define MAP_ADCIntStatus \
+ ADCIntStatus
+#endif
+#ifdef ROM_ADCIntClear
+#define MAP_ADCIntClear \
+ ROM_ADCIntClear
+#else
+#define MAP_ADCIntClear \
+ ADCIntClear
+#endif
+#ifdef ROM_ADCSequenceEnable
+#define MAP_ADCSequenceEnable \
+ ROM_ADCSequenceEnable
+#else
+#define MAP_ADCSequenceEnable \
+ ADCSequenceEnable
+#endif
+#ifdef ROM_ADCSequenceDisable
+#define MAP_ADCSequenceDisable \
+ ROM_ADCSequenceDisable
+#else
+#define MAP_ADCSequenceDisable \
+ ADCSequenceDisable
+#endif
+#ifdef ROM_ADCSequenceConfigure
+#define MAP_ADCSequenceConfigure \
+ ROM_ADCSequenceConfigure
+#else
+#define MAP_ADCSequenceConfigure \
+ ADCSequenceConfigure
+#endif
+#ifdef ROM_ADCSequenceStepConfigure
+#define MAP_ADCSequenceStepConfigure \
+ ROM_ADCSequenceStepConfigure
+#else
+#define MAP_ADCSequenceStepConfigure \
+ ADCSequenceStepConfigure
+#endif
+#ifdef ROM_ADCSequenceOverflow
+#define MAP_ADCSequenceOverflow \
+ ROM_ADCSequenceOverflow
+#else
+#define MAP_ADCSequenceOverflow \
+ ADCSequenceOverflow
+#endif
+#ifdef ROM_ADCSequenceOverflowClear
+#define MAP_ADCSequenceOverflowClear \
+ ROM_ADCSequenceOverflowClear
+#else
+#define MAP_ADCSequenceOverflowClear \
+ ADCSequenceOverflowClear
+#endif
+#ifdef ROM_ADCSequenceUnderflow
+#define MAP_ADCSequenceUnderflow \
+ ROM_ADCSequenceUnderflow
+#else
+#define MAP_ADCSequenceUnderflow \
+ ADCSequenceUnderflow
+#endif
+#ifdef ROM_ADCSequenceUnderflowClear
+#define MAP_ADCSequenceUnderflowClear \
+ ROM_ADCSequenceUnderflowClear
+#else
+#define MAP_ADCSequenceUnderflowClear \
+ ADCSequenceUnderflowClear
+#endif
+#ifdef ROM_ADCProcessorTrigger
+#define MAP_ADCProcessorTrigger \
+ ROM_ADCProcessorTrigger
+#else
+#define MAP_ADCProcessorTrigger \
+ ADCProcessorTrigger
+#endif
+#ifdef ROM_ADCHardwareOversampleConfigure
+#define MAP_ADCHardwareOversampleConfigure \
+ ROM_ADCHardwareOversampleConfigure
+#else
+#define MAP_ADCHardwareOversampleConfigure \
+ ADCHardwareOversampleConfigure
+#endif
+
+//*****************************************************************************
+//
+// Macros for the CAN API.
+//
+//*****************************************************************************
+#ifdef ROM_CANIntClear
+#define MAP_CANIntClear \
+ ROM_CANIntClear
+#else
+#define MAP_CANIntClear \
+ CANIntClear
+#endif
+#ifdef ROM_CANInit
+#define MAP_CANInit \
+ ROM_CANInit
+#else
+#define MAP_CANInit \
+ CANInit
+#endif
+#ifdef ROM_CANEnable
+#define MAP_CANEnable \
+ ROM_CANEnable
+#else
+#define MAP_CANEnable \
+ CANEnable
+#endif
+#ifdef ROM_CANDisable
+#define MAP_CANDisable \
+ ROM_CANDisable
+#else
+#define MAP_CANDisable \
+ CANDisable
+#endif
+#ifdef ROM_CANBitTimingSet
+#define MAP_CANBitTimingSet \
+ ROM_CANBitTimingSet
+#else
+#define MAP_CANBitTimingSet \
+ CANBitTimingSet
+#endif
+#ifdef ROM_CANBitTimingGet
+#define MAP_CANBitTimingGet \
+ ROM_CANBitTimingGet
+#else
+#define MAP_CANBitTimingGet \
+ CANBitTimingGet
+#endif
+#ifdef ROM_CANMessageSet
+#define MAP_CANMessageSet \
+ ROM_CANMessageSet
+#else
+#define MAP_CANMessageSet \
+ CANMessageSet
+#endif
+#ifdef ROM_CANMessageGet
+#define MAP_CANMessageGet \
+ ROM_CANMessageGet
+#else
+#define MAP_CANMessageGet \
+ CANMessageGet
+#endif
+#ifdef ROM_CANStatusGet
+#define MAP_CANStatusGet \
+ ROM_CANStatusGet
+#else
+#define MAP_CANStatusGet \
+ CANStatusGet
+#endif
+#ifdef ROM_CANMessageClear
+#define MAP_CANMessageClear \
+ ROM_CANMessageClear
+#else
+#define MAP_CANMessageClear \
+ CANMessageClear
+#endif
+#ifdef ROM_CANIntEnable
+#define MAP_CANIntEnable \
+ ROM_CANIntEnable
+#else
+#define MAP_CANIntEnable \
+ CANIntEnable
+#endif
+#ifdef ROM_CANIntDisable
+#define MAP_CANIntDisable \
+ ROM_CANIntDisable
+#else
+#define MAP_CANIntDisable \
+ CANIntDisable
+#endif
+#ifdef ROM_CANIntStatus
+#define MAP_CANIntStatus \
+ ROM_CANIntStatus
+#else
+#define MAP_CANIntStatus \
+ CANIntStatus
+#endif
+#ifdef ROM_CANRetryGet
+#define MAP_CANRetryGet \
+ ROM_CANRetryGet
+#else
+#define MAP_CANRetryGet \
+ CANRetryGet
+#endif
+#ifdef ROM_CANRetrySet
+#define MAP_CANRetrySet \
+ ROM_CANRetrySet
+#else
+#define MAP_CANRetrySet \
+ CANRetrySet
+#endif
+#ifdef ROM_CANErrCntrGet
+#define MAP_CANErrCntrGet \
+ ROM_CANErrCntrGet
+#else
+#define MAP_CANErrCntrGet \
+ CANErrCntrGet
+#endif
+
+//*****************************************************************************
+//
+// Macros for the Comparator API.
+//
+//*****************************************************************************
+#ifdef ROM_ComparatorIntClear
+#define MAP_ComparatorIntClear \
+ ROM_ComparatorIntClear
+#else
+#define MAP_ComparatorIntClear \
+ ComparatorIntClear
+#endif
+#ifdef ROM_ComparatorConfigure
+#define MAP_ComparatorConfigure \
+ ROM_ComparatorConfigure
+#else
+#define MAP_ComparatorConfigure \
+ ComparatorConfigure
+#endif
+#ifdef ROM_ComparatorRefSet
+#define MAP_ComparatorRefSet \
+ ROM_ComparatorRefSet
+#else
+#define MAP_ComparatorRefSet \
+ ComparatorRefSet
+#endif
+#ifdef ROM_ComparatorValueGet
+#define MAP_ComparatorValueGet \
+ ROM_ComparatorValueGet
+#else
+#define MAP_ComparatorValueGet \
+ ComparatorValueGet
+#endif
+#ifdef ROM_ComparatorIntEnable
+#define MAP_ComparatorIntEnable \
+ ROM_ComparatorIntEnable
+#else
+#define MAP_ComparatorIntEnable \
+ ComparatorIntEnable
+#endif
+#ifdef ROM_ComparatorIntDisable
+#define MAP_ComparatorIntDisable \
+ ROM_ComparatorIntDisable
+#else
+#define MAP_ComparatorIntDisable \
+ ComparatorIntDisable
+#endif
+#ifdef ROM_ComparatorIntStatus
+#define MAP_ComparatorIntStatus \
+ ROM_ComparatorIntStatus
+#else
+#define MAP_ComparatorIntStatus \
+ ComparatorIntStatus
+#endif
+
+//*****************************************************************************
+//
+// Macros for the Ethernet API.
+//
+//*****************************************************************************
+#ifdef ROM_EthernetIntClear
+#define MAP_EthernetIntClear \
+ ROM_EthernetIntClear
+#else
+#define MAP_EthernetIntClear \
+ EthernetIntClear
+#endif
+#ifdef ROM_EthernetInitExpClk
+#define MAP_EthernetInitExpClk \
+ ROM_EthernetInitExpClk
+#else
+#define MAP_EthernetInitExpClk \
+ EthernetInitExpClk
+#endif
+#ifdef ROM_EthernetConfigSet
+#define MAP_EthernetConfigSet \
+ ROM_EthernetConfigSet
+#else
+#define MAP_EthernetConfigSet \
+ EthernetConfigSet
+#endif
+#ifdef ROM_EthernetConfigGet
+#define MAP_EthernetConfigGet \
+ ROM_EthernetConfigGet
+#else
+#define MAP_EthernetConfigGet \
+ EthernetConfigGet
+#endif
+#ifdef ROM_EthernetMACAddrSet
+#define MAP_EthernetMACAddrSet \
+ ROM_EthernetMACAddrSet
+#else
+#define MAP_EthernetMACAddrSet \
+ EthernetMACAddrSet
+#endif
+#ifdef ROM_EthernetMACAddrGet
+#define MAP_EthernetMACAddrGet \
+ ROM_EthernetMACAddrGet
+#else
+#define MAP_EthernetMACAddrGet \
+ EthernetMACAddrGet
+#endif
+#ifdef ROM_EthernetEnable
+#define MAP_EthernetEnable \
+ ROM_EthernetEnable
+#else
+#define MAP_EthernetEnable \
+ EthernetEnable
+#endif
+#ifdef ROM_EthernetDisable
+#define MAP_EthernetDisable \
+ ROM_EthernetDisable
+#else
+#define MAP_EthernetDisable \
+ EthernetDisable
+#endif
+#ifdef ROM_EthernetPacketAvail
+#define MAP_EthernetPacketAvail \
+ ROM_EthernetPacketAvail
+#else
+#define MAP_EthernetPacketAvail \
+ EthernetPacketAvail
+#endif
+#ifdef ROM_EthernetSpaceAvail
+#define MAP_EthernetSpaceAvail \
+ ROM_EthernetSpaceAvail
+#else
+#define MAP_EthernetSpaceAvail \
+ EthernetSpaceAvail
+#endif
+#ifdef ROM_EthernetPacketGetNonBlocking
+#define MAP_EthernetPacketGetNonBlocking \
+ ROM_EthernetPacketGetNonBlocking
+#else
+#define MAP_EthernetPacketGetNonBlocking \
+ EthernetPacketGetNonBlocking
+#endif
+#ifdef ROM_EthernetPacketGet
+#define MAP_EthernetPacketGet \
+ ROM_EthernetPacketGet
+#else
+#define MAP_EthernetPacketGet \
+ EthernetPacketGet
+#endif
+#ifdef ROM_EthernetPacketPutNonBlocking
+#define MAP_EthernetPacketPutNonBlocking \
+ ROM_EthernetPacketPutNonBlocking
+#else
+#define MAP_EthernetPacketPutNonBlocking \
+ EthernetPacketPutNonBlocking
+#endif
+#ifdef ROM_EthernetPacketPut
+#define MAP_EthernetPacketPut \
+ ROM_EthernetPacketPut
+#else
+#define MAP_EthernetPacketPut \
+ EthernetPacketPut
+#endif
+#ifdef ROM_EthernetIntEnable
+#define MAP_EthernetIntEnable \
+ ROM_EthernetIntEnable
+#else
+#define MAP_EthernetIntEnable \
+ EthernetIntEnable
+#endif
+#ifdef ROM_EthernetIntDisable
+#define MAP_EthernetIntDisable \
+ ROM_EthernetIntDisable
+#else
+#define MAP_EthernetIntDisable \
+ EthernetIntDisable
+#endif
+#ifdef ROM_EthernetIntStatus
+#define MAP_EthernetIntStatus \
+ ROM_EthernetIntStatus
+#else
+#define MAP_EthernetIntStatus \
+ EthernetIntStatus
+#endif
+#ifdef ROM_EthernetPHYWrite
+#define MAP_EthernetPHYWrite \
+ ROM_EthernetPHYWrite
+#else
+#define MAP_EthernetPHYWrite \
+ EthernetPHYWrite
+#endif
+#ifdef ROM_EthernetPHYRead
+#define MAP_EthernetPHYRead \
+ ROM_EthernetPHYRead
+#else
+#define MAP_EthernetPHYRead \
+ EthernetPHYRead
+#endif
+
+//*****************************************************************************
+//
+// Macros for the Flash API.
+//
+//*****************************************************************************
+#ifdef ROM_FlashProgram
+#define MAP_FlashProgram \
+ ROM_FlashProgram
+#else
+#define MAP_FlashProgram \
+ FlashProgram
+#endif
+#ifdef ROM_FlashUsecGet
+#define MAP_FlashUsecGet \
+ ROM_FlashUsecGet
+#else
+#define MAP_FlashUsecGet \
+ FlashUsecGet
+#endif
+#ifdef ROM_FlashUsecSet
+#define MAP_FlashUsecSet \
+ ROM_FlashUsecSet
+#else
+#define MAP_FlashUsecSet \
+ FlashUsecSet
+#endif
+#ifdef ROM_FlashErase
+#define MAP_FlashErase \
+ ROM_FlashErase
+#else
+#define MAP_FlashErase \
+ FlashErase
+#endif
+#ifdef ROM_FlashProtectGet
+#define MAP_FlashProtectGet \
+ ROM_FlashProtectGet
+#else
+#define MAP_FlashProtectGet \
+ FlashProtectGet
+#endif
+#ifdef ROM_FlashProtectSet
+#define MAP_FlashProtectSet \
+ ROM_FlashProtectSet
+#else
+#define MAP_FlashProtectSet \
+ FlashProtectSet
+#endif
+#ifdef ROM_FlashProtectSave
+#define MAP_FlashProtectSave \
+ ROM_FlashProtectSave
+#else
+#define MAP_FlashProtectSave \
+ FlashProtectSave
+#endif
+#ifdef ROM_FlashUserGet
+#define MAP_FlashUserGet \
+ ROM_FlashUserGet
+#else
+#define MAP_FlashUserGet \
+ FlashUserGet
+#endif
+#ifdef ROM_FlashUserSet
+#define MAP_FlashUserSet \
+ ROM_FlashUserSet
+#else
+#define MAP_FlashUserSet \
+ FlashUserSet
+#endif
+#ifdef ROM_FlashUserSave
+#define MAP_FlashUserSave \
+ ROM_FlashUserSave
+#else
+#define MAP_FlashUserSave \
+ FlashUserSave
+#endif
+#ifdef ROM_FlashIntEnable
+#define MAP_FlashIntEnable \
+ ROM_FlashIntEnable
+#else
+#define MAP_FlashIntEnable \
+ FlashIntEnable
+#endif
+#ifdef ROM_FlashIntDisable
+#define MAP_FlashIntDisable \
+ ROM_FlashIntDisable
+#else
+#define MAP_FlashIntDisable \
+ FlashIntDisable
+#endif
+#ifdef ROM_FlashIntGetStatus
+#define MAP_FlashIntGetStatus \
+ ROM_FlashIntGetStatus
+#else
+#define MAP_FlashIntGetStatus \
+ FlashIntGetStatus
+#endif
+#ifdef ROM_FlashIntClear
+#define MAP_FlashIntClear \
+ ROM_FlashIntClear
+#else
+#define MAP_FlashIntClear \
+ FlashIntClear
+#endif
+
+//*****************************************************************************
+//
+// Macros for the GPIO API.
+//
+//*****************************************************************************
+#ifdef ROM_GPIOPinWrite
+#define MAP_GPIOPinWrite \
+ ROM_GPIOPinWrite
+#else
+#define MAP_GPIOPinWrite \
+ GPIOPinWrite
+#endif
+#ifdef ROM_GPIODirModeSet
+#define MAP_GPIODirModeSet \
+ ROM_GPIODirModeSet
+#else
+#define MAP_GPIODirModeSet \
+ GPIODirModeSet
+#endif
+#ifdef ROM_GPIODirModeGet
+#define MAP_GPIODirModeGet \
+ ROM_GPIODirModeGet
+#else
+#define MAP_GPIODirModeGet \
+ GPIODirModeGet
+#endif
+#ifdef ROM_GPIOIntTypeSet
+#define MAP_GPIOIntTypeSet \
+ ROM_GPIOIntTypeSet
+#else
+#define MAP_GPIOIntTypeSet \
+ GPIOIntTypeSet
+#endif
+#ifdef ROM_GPIOIntTypeGet
+#define MAP_GPIOIntTypeGet \
+ ROM_GPIOIntTypeGet
+#else
+#define MAP_GPIOIntTypeGet \
+ GPIOIntTypeGet
+#endif
+#ifdef ROM_GPIOPadConfigSet
+#define MAP_GPIOPadConfigSet \
+ ROM_GPIOPadConfigSet
+#else
+#define MAP_GPIOPadConfigSet \
+ GPIOPadConfigSet
+#endif
+#ifdef ROM_GPIOPadConfigGet
+#define MAP_GPIOPadConfigGet \
+ ROM_GPIOPadConfigGet
+#else
+#define MAP_GPIOPadConfigGet \
+ GPIOPadConfigGet
+#endif
+#ifdef ROM_GPIOPinIntEnable
+#define MAP_GPIOPinIntEnable \
+ ROM_GPIOPinIntEnable
+#else
+#define MAP_GPIOPinIntEnable \
+ GPIOPinIntEnable
+#endif
+#ifdef ROM_GPIOPinIntDisable
+#define MAP_GPIOPinIntDisable \
+ ROM_GPIOPinIntDisable
+#else
+#define MAP_GPIOPinIntDisable \
+ GPIOPinIntDisable
+#endif
+#ifdef ROM_GPIOPinIntStatus
+#define MAP_GPIOPinIntStatus \
+ ROM_GPIOPinIntStatus
+#else
+#define MAP_GPIOPinIntStatus \
+ GPIOPinIntStatus
+#endif
+#ifdef ROM_GPIOPinIntClear
+#define MAP_GPIOPinIntClear \
+ ROM_GPIOPinIntClear
+#else
+#define MAP_GPIOPinIntClear \
+ GPIOPinIntClear
+#endif
+#ifdef ROM_GPIOPinRead
+#define MAP_GPIOPinRead \
+ ROM_GPIOPinRead
+#else
+#define MAP_GPIOPinRead \
+ GPIOPinRead
+#endif
+#ifdef ROM_GPIOPinTypeCAN
+#define MAP_GPIOPinTypeCAN \
+ ROM_GPIOPinTypeCAN
+#else
+#define MAP_GPIOPinTypeCAN \
+ GPIOPinTypeCAN
+#endif
+#ifdef ROM_GPIOPinTypeComparator
+#define MAP_GPIOPinTypeComparator \
+ ROM_GPIOPinTypeComparator
+#else
+#define MAP_GPIOPinTypeComparator \
+ GPIOPinTypeComparator
+#endif
+#ifdef ROM_GPIOPinTypeGPIOInput
+#define MAP_GPIOPinTypeGPIOInput \
+ ROM_GPIOPinTypeGPIOInput
+#else
+#define MAP_GPIOPinTypeGPIOInput \
+ GPIOPinTypeGPIOInput
+#endif
+#ifdef ROM_GPIOPinTypeGPIOOutput
+#define MAP_GPIOPinTypeGPIOOutput \
+ ROM_GPIOPinTypeGPIOOutput
+#else
+#define MAP_GPIOPinTypeGPIOOutput \
+ GPIOPinTypeGPIOOutput
+#endif
+#ifdef ROM_GPIOPinTypeI2C
+#define MAP_GPIOPinTypeI2C \
+ ROM_GPIOPinTypeI2C
+#else
+#define MAP_GPIOPinTypeI2C \
+ GPIOPinTypeI2C
+#endif
+#ifdef ROM_GPIOPinTypePWM
+#define MAP_GPIOPinTypePWM \
+ ROM_GPIOPinTypePWM
+#else
+#define MAP_GPIOPinTypePWM \
+ GPIOPinTypePWM
+#endif
+#ifdef ROM_GPIOPinTypeQEI
+#define MAP_GPIOPinTypeQEI \
+ ROM_GPIOPinTypeQEI
+#else
+#define MAP_GPIOPinTypeQEI \
+ GPIOPinTypeQEI
+#endif
+#ifdef ROM_GPIOPinTypeSSI
+#define MAP_GPIOPinTypeSSI \
+ ROM_GPIOPinTypeSSI
+#else
+#define MAP_GPIOPinTypeSSI \
+ GPIOPinTypeSSI
+#endif
+#ifdef ROM_GPIOPinTypeTimer
+#define MAP_GPIOPinTypeTimer \
+ ROM_GPIOPinTypeTimer
+#else
+#define MAP_GPIOPinTypeTimer \
+ GPIOPinTypeTimer
+#endif
+#ifdef ROM_GPIOPinTypeUART
+#define MAP_GPIOPinTypeUART \
+ ROM_GPIOPinTypeUART
+#else
+#define MAP_GPIOPinTypeUART \
+ GPIOPinTypeUART
+#endif
+#ifdef ROM_GPIOPinTypeGPIOOutputOD
+#define MAP_GPIOPinTypeGPIOOutputOD \
+ ROM_GPIOPinTypeGPIOOutputOD
+#else
+#define MAP_GPIOPinTypeGPIOOutputOD \
+ GPIOPinTypeGPIOOutputOD
+#endif
+#ifdef ROM_GPIOPinTypeADC
+#define MAP_GPIOPinTypeADC \
+ ROM_GPIOPinTypeADC
+#else
+#define MAP_GPIOPinTypeADC \
+ GPIOPinTypeADC
+#endif
+#ifdef ROM_GPIOPinTypeUSBDigital
+#define MAP_GPIOPinTypeUSBDigital \
+ ROM_GPIOPinTypeUSBDigital
+#else
+#define MAP_GPIOPinTypeUSBDigital \
+ GPIOPinTypeUSBDigital
+#endif
+
+//*****************************************************************************
+//
+// Macros for the Hibernate API.
+//
+//*****************************************************************************
+#ifdef ROM_HibernateIntClear
+#define MAP_HibernateIntClear \
+ ROM_HibernateIntClear
+#else
+#define MAP_HibernateIntClear \
+ HibernateIntClear
+#endif
+#ifdef ROM_HibernateEnableExpClk
+#define MAP_HibernateEnableExpClk \
+ ROM_HibernateEnableExpClk
+#else
+#define MAP_HibernateEnableExpClk \
+ HibernateEnableExpClk
+#endif
+#ifdef ROM_HibernateDisable
+#define MAP_HibernateDisable \
+ ROM_HibernateDisable
+#else
+#define MAP_HibernateDisable \
+ HibernateDisable
+#endif
+#ifdef ROM_HibernateClockSelect
+#define MAP_HibernateClockSelect \
+ ROM_HibernateClockSelect
+#else
+#define MAP_HibernateClockSelect \
+ HibernateClockSelect
+#endif
+#ifdef ROM_HibernateRTCEnable
+#define MAP_HibernateRTCEnable \
+ ROM_HibernateRTCEnable
+#else
+#define MAP_HibernateRTCEnable \
+ HibernateRTCEnable
+#endif
+#ifdef ROM_HibernateRTCDisable
+#define MAP_HibernateRTCDisable \
+ ROM_HibernateRTCDisable
+#else
+#define MAP_HibernateRTCDisable \
+ HibernateRTCDisable
+#endif
+#ifdef ROM_HibernateWakeSet
+#define MAP_HibernateWakeSet \
+ ROM_HibernateWakeSet
+#else
+#define MAP_HibernateWakeSet \
+ HibernateWakeSet
+#endif
+#ifdef ROM_HibernateWakeGet
+#define MAP_HibernateWakeGet \
+ ROM_HibernateWakeGet
+#else
+#define MAP_HibernateWakeGet \
+ HibernateWakeGet
+#endif
+#ifdef ROM_HibernateLowBatSet
+#define MAP_HibernateLowBatSet \
+ ROM_HibernateLowBatSet
+#else
+#define MAP_HibernateLowBatSet \
+ HibernateLowBatSet
+#endif
+#ifdef ROM_HibernateLowBatGet
+#define MAP_HibernateLowBatGet \
+ ROM_HibernateLowBatGet
+#else
+#define MAP_HibernateLowBatGet \
+ HibernateLowBatGet
+#endif
+#ifdef ROM_HibernateRTCSet
+#define MAP_HibernateRTCSet \
+ ROM_HibernateRTCSet
+#else
+#define MAP_HibernateRTCSet \
+ HibernateRTCSet
+#endif
+#ifdef ROM_HibernateRTCGet
+#define MAP_HibernateRTCGet \
+ ROM_HibernateRTCGet
+#else
+#define MAP_HibernateRTCGet \
+ HibernateRTCGet
+#endif
+#ifdef ROM_HibernateRTCMatch0Set
+#define MAP_HibernateRTCMatch0Set \
+ ROM_HibernateRTCMatch0Set
+#else
+#define MAP_HibernateRTCMatch0Set \
+ HibernateRTCMatch0Set
+#endif
+#ifdef ROM_HibernateRTCMatch0Get
+#define MAP_HibernateRTCMatch0Get \
+ ROM_HibernateRTCMatch0Get
+#else
+#define MAP_HibernateRTCMatch0Get \
+ HibernateRTCMatch0Get
+#endif
+#ifdef ROM_HibernateRTCMatch1Set
+#define MAP_HibernateRTCMatch1Set \
+ ROM_HibernateRTCMatch1Set
+#else
+#define MAP_HibernateRTCMatch1Set \
+ HibernateRTCMatch1Set
+#endif
+#ifdef ROM_HibernateRTCMatch1Get
+#define MAP_HibernateRTCMatch1Get \
+ ROM_HibernateRTCMatch1Get
+#else
+#define MAP_HibernateRTCMatch1Get \
+ HibernateRTCMatch1Get
+#endif
+#ifdef ROM_HibernateRTCTrimSet
+#define MAP_HibernateRTCTrimSet \
+ ROM_HibernateRTCTrimSet
+#else
+#define MAP_HibernateRTCTrimSet \
+ HibernateRTCTrimSet
+#endif
+#ifdef ROM_HibernateRTCTrimGet
+#define MAP_HibernateRTCTrimGet \
+ ROM_HibernateRTCTrimGet
+#else
+#define MAP_HibernateRTCTrimGet \
+ HibernateRTCTrimGet
+#endif
+#ifdef ROM_HibernateDataSet
+#define MAP_HibernateDataSet \
+ ROM_HibernateDataSet
+#else
+#define MAP_HibernateDataSet \
+ HibernateDataSet
+#endif
+#ifdef ROM_HibernateDataGet
+#define MAP_HibernateDataGet \
+ ROM_HibernateDataGet
+#else
+#define MAP_HibernateDataGet \
+ HibernateDataGet
+#endif
+#ifdef ROM_HibernateRequest
+#define MAP_HibernateRequest \
+ ROM_HibernateRequest
+#else
+#define MAP_HibernateRequest \
+ HibernateRequest
+#endif
+#ifdef ROM_HibernateIntEnable
+#define MAP_HibernateIntEnable \
+ ROM_HibernateIntEnable
+#else
+#define MAP_HibernateIntEnable \
+ HibernateIntEnable
+#endif
+#ifdef ROM_HibernateIntDisable
+#define MAP_HibernateIntDisable \
+ ROM_HibernateIntDisable
+#else
+#define MAP_HibernateIntDisable \
+ HibernateIntDisable
+#endif
+#ifdef ROM_HibernateIntStatus
+#define MAP_HibernateIntStatus \
+ ROM_HibernateIntStatus
+#else
+#define MAP_HibernateIntStatus \
+ HibernateIntStatus
+#endif
+#ifdef ROM_HibernateIsActive
+#define MAP_HibernateIsActive \
+ ROM_HibernateIsActive
+#else
+#define MAP_HibernateIsActive \
+ HibernateIsActive
+#endif
+
+//*****************************************************************************
+//
+// Macros for the I2C API.
+//
+//*****************************************************************************
+#ifdef ROM_I2CMasterDataPut
+#define MAP_I2CMasterDataPut \
+ ROM_I2CMasterDataPut
+#else
+#define MAP_I2CMasterDataPut \
+ I2CMasterDataPut
+#endif
+#ifdef ROM_I2CMasterInitExpClk
+#define MAP_I2CMasterInitExpClk \
+ ROM_I2CMasterInitExpClk
+#else
+#define MAP_I2CMasterInitExpClk \
+ I2CMasterInitExpClk
+#endif
+#ifdef ROM_I2CSlaveInit
+#define MAP_I2CSlaveInit \
+ ROM_I2CSlaveInit
+#else
+#define MAP_I2CSlaveInit \
+ I2CSlaveInit
+#endif
+#ifdef ROM_I2CMasterEnable
+#define MAP_I2CMasterEnable \
+ ROM_I2CMasterEnable
+#else
+#define MAP_I2CMasterEnable \
+ I2CMasterEnable
+#endif
+#ifdef ROM_I2CSlaveEnable
+#define MAP_I2CSlaveEnable \
+ ROM_I2CSlaveEnable
+#else
+#define MAP_I2CSlaveEnable \
+ I2CSlaveEnable
+#endif
+#ifdef ROM_I2CMasterDisable
+#define MAP_I2CMasterDisable \
+ ROM_I2CMasterDisable
+#else
+#define MAP_I2CMasterDisable \
+ I2CMasterDisable
+#endif
+#ifdef ROM_I2CSlaveDisable
+#define MAP_I2CSlaveDisable \
+ ROM_I2CSlaveDisable
+#else
+#define MAP_I2CSlaveDisable \
+ I2CSlaveDisable
+#endif
+#ifdef ROM_I2CMasterIntEnable
+#define MAP_I2CMasterIntEnable \
+ ROM_I2CMasterIntEnable
+#else
+#define MAP_I2CMasterIntEnable \
+ I2CMasterIntEnable
+#endif
+#ifdef ROM_I2CSlaveIntEnable
+#define MAP_I2CSlaveIntEnable \
+ ROM_I2CSlaveIntEnable
+#else
+#define MAP_I2CSlaveIntEnable \
+ I2CSlaveIntEnable
+#endif
+#ifdef ROM_I2CMasterIntDisable
+#define MAP_I2CMasterIntDisable \
+ ROM_I2CMasterIntDisable
+#else
+#define MAP_I2CMasterIntDisable \
+ I2CMasterIntDisable
+#endif
+#ifdef ROM_I2CSlaveIntDisable
+#define MAP_I2CSlaveIntDisable \
+ ROM_I2CSlaveIntDisable
+#else
+#define MAP_I2CSlaveIntDisable \
+ I2CSlaveIntDisable
+#endif
+#ifdef ROM_I2CMasterIntStatus
+#define MAP_I2CMasterIntStatus \
+ ROM_I2CMasterIntStatus
+#else
+#define MAP_I2CMasterIntStatus \
+ I2CMasterIntStatus
+#endif
+#ifdef ROM_I2CSlaveIntStatus
+#define MAP_I2CSlaveIntStatus \
+ ROM_I2CSlaveIntStatus
+#else
+#define MAP_I2CSlaveIntStatus \
+ I2CSlaveIntStatus
+#endif
+#ifdef ROM_I2CMasterIntClear
+#define MAP_I2CMasterIntClear \
+ ROM_I2CMasterIntClear
+#else
+#define MAP_I2CMasterIntClear \
+ I2CMasterIntClear
+#endif
+#ifdef ROM_I2CSlaveIntClear
+#define MAP_I2CSlaveIntClear \
+ ROM_I2CSlaveIntClear
+#else
+#define MAP_I2CSlaveIntClear \
+ I2CSlaveIntClear
+#endif
+#ifdef ROM_I2CMasterSlaveAddrSet
+#define MAP_I2CMasterSlaveAddrSet \
+ ROM_I2CMasterSlaveAddrSet
+#else
+#define MAP_I2CMasterSlaveAddrSet \
+ I2CMasterSlaveAddrSet
+#endif
+#ifdef ROM_I2CMasterBusy
+#define MAP_I2CMasterBusy \
+ ROM_I2CMasterBusy
+#else
+#define MAP_I2CMasterBusy \
+ I2CMasterBusy
+#endif
+#ifdef ROM_I2CMasterBusBusy
+#define MAP_I2CMasterBusBusy \
+ ROM_I2CMasterBusBusy
+#else
+#define MAP_I2CMasterBusBusy \
+ I2CMasterBusBusy
+#endif
+#ifdef ROM_I2CMasterControl
+#define MAP_I2CMasterControl \
+ ROM_I2CMasterControl
+#else
+#define MAP_I2CMasterControl \
+ I2CMasterControl
+#endif
+#ifdef ROM_I2CMasterErr
+#define MAP_I2CMasterErr \
+ ROM_I2CMasterErr
+#else
+#define MAP_I2CMasterErr \
+ I2CMasterErr
+#endif
+#ifdef ROM_I2CMasterDataGet
+#define MAP_I2CMasterDataGet \
+ ROM_I2CMasterDataGet
+#else
+#define MAP_I2CMasterDataGet \
+ I2CMasterDataGet
+#endif
+#ifdef ROM_I2CSlaveStatus
+#define MAP_I2CSlaveStatus \
+ ROM_I2CSlaveStatus
+#else
+#define MAP_I2CSlaveStatus \
+ I2CSlaveStatus
+#endif
+#ifdef ROM_I2CSlaveDataPut
+#define MAP_I2CSlaveDataPut \
+ ROM_I2CSlaveDataPut
+#else
+#define MAP_I2CSlaveDataPut \
+ I2CSlaveDataPut
+#endif
+#ifdef ROM_I2CSlaveDataGet
+#define MAP_I2CSlaveDataGet \
+ ROM_I2CSlaveDataGet
+#else
+#define MAP_I2CSlaveDataGet \
+ I2CSlaveDataGet
+#endif
+
+//*****************************************************************************
+//
+// Macros for the Interrupt API.
+//
+//*****************************************************************************
+#ifdef ROM_IntEnable
+#define MAP_IntEnable \
+ ROM_IntEnable
+#else
+#define MAP_IntEnable \
+ IntEnable
+#endif
+#ifdef ROM_IntMasterEnable
+#define MAP_IntMasterEnable \
+ ROM_IntMasterEnable
+#else
+#define MAP_IntMasterEnable \
+ IntMasterEnable
+#endif
+#ifdef ROM_IntMasterDisable
+#define MAP_IntMasterDisable \
+ ROM_IntMasterDisable
+#else
+#define MAP_IntMasterDisable \
+ IntMasterDisable
+#endif
+#ifdef ROM_IntDisable
+#define MAP_IntDisable \
+ ROM_IntDisable
+#else
+#define MAP_IntDisable \
+ IntDisable
+#endif
+#ifdef ROM_IntPriorityGroupingSet
+#define MAP_IntPriorityGroupingSet \
+ ROM_IntPriorityGroupingSet
+#else
+#define MAP_IntPriorityGroupingSet \
+ IntPriorityGroupingSet
+#endif
+#ifdef ROM_IntPriorityGroupingGet
+#define MAP_IntPriorityGroupingGet \
+ ROM_IntPriorityGroupingGet
+#else
+#define MAP_IntPriorityGroupingGet \
+ IntPriorityGroupingGet
+#endif
+#ifdef ROM_IntPrioritySet
+#define MAP_IntPrioritySet \
+ ROM_IntPrioritySet
+#else
+#define MAP_IntPrioritySet \
+ IntPrioritySet
+#endif
+#ifdef ROM_IntPriorityGet
+#define MAP_IntPriorityGet \
+ ROM_IntPriorityGet
+#else
+#define MAP_IntPriorityGet \
+ IntPriorityGet
+#endif
+
+//*****************************************************************************
+//
+// Macros for the MPU API.
+//
+//*****************************************************************************
+#ifdef ROM_MPUEnable
+#define MAP_MPUEnable \
+ ROM_MPUEnable
+#else
+#define MAP_MPUEnable \
+ MPUEnable
+#endif
+#ifdef ROM_MPUDisable
+#define MAP_MPUDisable \
+ ROM_MPUDisable
+#else
+#define MAP_MPUDisable \
+ MPUDisable
+#endif
+#ifdef ROM_MPURegionCountGet
+#define MAP_MPURegionCountGet \
+ ROM_MPURegionCountGet
+#else
+#define MAP_MPURegionCountGet \
+ MPURegionCountGet
+#endif
+#ifdef ROM_MPURegionEnable
+#define MAP_MPURegionEnable \
+ ROM_MPURegionEnable
+#else
+#define MAP_MPURegionEnable \
+ MPURegionEnable
+#endif
+#ifdef ROM_MPURegionDisable
+#define MAP_MPURegionDisable \
+ ROM_MPURegionDisable
+#else
+#define MAP_MPURegionDisable \
+ MPURegionDisable
+#endif
+#ifdef ROM_MPURegionSet
+#define MAP_MPURegionSet \
+ ROM_MPURegionSet
+#else
+#define MAP_MPURegionSet \
+ MPURegionSet
+#endif
+#ifdef ROM_MPURegionGet
+#define MAP_MPURegionGet \
+ ROM_MPURegionGet
+#else
+#define MAP_MPURegionGet \
+ MPURegionGet
+#endif
+
+//*****************************************************************************
+//
+// Macros for the PWM API.
+//
+//*****************************************************************************
+#ifdef ROM_PWMPulseWidthSet
+#define MAP_PWMPulseWidthSet \
+ ROM_PWMPulseWidthSet
+#else
+#define MAP_PWMPulseWidthSet \
+ PWMPulseWidthSet
+#endif
+#ifdef ROM_PWMGenConfigure
+#define MAP_PWMGenConfigure \
+ ROM_PWMGenConfigure
+#else
+#define MAP_PWMGenConfigure \
+ PWMGenConfigure
+#endif
+#ifdef ROM_PWMGenPeriodSet
+#define MAP_PWMGenPeriodSet \
+ ROM_PWMGenPeriodSet
+#else
+#define MAP_PWMGenPeriodSet \
+ PWMGenPeriodSet
+#endif
+#ifdef ROM_PWMGenPeriodGet
+#define MAP_PWMGenPeriodGet \
+ ROM_PWMGenPeriodGet
+#else
+#define MAP_PWMGenPeriodGet \
+ PWMGenPeriodGet
+#endif
+#ifdef ROM_PWMGenEnable
+#define MAP_PWMGenEnable \
+ ROM_PWMGenEnable
+#else
+#define MAP_PWMGenEnable \
+ PWMGenEnable
+#endif
+#ifdef ROM_PWMGenDisable
+#define MAP_PWMGenDisable \
+ ROM_PWMGenDisable
+#else
+#define MAP_PWMGenDisable \
+ PWMGenDisable
+#endif
+#ifdef ROM_PWMPulseWidthGet
+#define MAP_PWMPulseWidthGet \
+ ROM_PWMPulseWidthGet
+#else
+#define MAP_PWMPulseWidthGet \
+ PWMPulseWidthGet
+#endif
+#ifdef ROM_PWMDeadBandEnable
+#define MAP_PWMDeadBandEnable \
+ ROM_PWMDeadBandEnable
+#else
+#define MAP_PWMDeadBandEnable \
+ PWMDeadBandEnable
+#endif
+#ifdef ROM_PWMDeadBandDisable
+#define MAP_PWMDeadBandDisable \
+ ROM_PWMDeadBandDisable
+#else
+#define MAP_PWMDeadBandDisable \
+ PWMDeadBandDisable
+#endif
+#ifdef ROM_PWMSyncUpdate
+#define MAP_PWMSyncUpdate \
+ ROM_PWMSyncUpdate
+#else
+#define MAP_PWMSyncUpdate \
+ PWMSyncUpdate
+#endif
+#ifdef ROM_PWMSyncTimeBase
+#define MAP_PWMSyncTimeBase \
+ ROM_PWMSyncTimeBase
+#else
+#define MAP_PWMSyncTimeBase \
+ PWMSyncTimeBase
+#endif
+#ifdef ROM_PWMOutputState
+#define MAP_PWMOutputState \
+ ROM_PWMOutputState
+#else
+#define MAP_PWMOutputState \
+ PWMOutputState
+#endif
+#ifdef ROM_PWMOutputInvert
+#define MAP_PWMOutputInvert \
+ ROM_PWMOutputInvert
+#else
+#define MAP_PWMOutputInvert \
+ PWMOutputInvert
+#endif
+#ifdef ROM_PWMOutputFault
+#define MAP_PWMOutputFault \
+ ROM_PWMOutputFault
+#else
+#define MAP_PWMOutputFault \
+ PWMOutputFault
+#endif
+#ifdef ROM_PWMGenIntTrigEnable
+#define MAP_PWMGenIntTrigEnable \
+ ROM_PWMGenIntTrigEnable
+#else
+#define MAP_PWMGenIntTrigEnable \
+ PWMGenIntTrigEnable
+#endif
+#ifdef ROM_PWMGenIntTrigDisable
+#define MAP_PWMGenIntTrigDisable \
+ ROM_PWMGenIntTrigDisable
+#else
+#define MAP_PWMGenIntTrigDisable \
+ PWMGenIntTrigDisable
+#endif
+#ifdef ROM_PWMGenIntStatus
+#define MAP_PWMGenIntStatus \
+ ROM_PWMGenIntStatus
+#else
+#define MAP_PWMGenIntStatus \
+ PWMGenIntStatus
+#endif
+#ifdef ROM_PWMGenIntClear
+#define MAP_PWMGenIntClear \
+ ROM_PWMGenIntClear
+#else
+#define MAP_PWMGenIntClear \
+ PWMGenIntClear
+#endif
+#ifdef ROM_PWMIntEnable
+#define MAP_PWMIntEnable \
+ ROM_PWMIntEnable
+#else
+#define MAP_PWMIntEnable \
+ PWMIntEnable
+#endif
+#ifdef ROM_PWMIntDisable
+#define MAP_PWMIntDisable \
+ ROM_PWMIntDisable
+#else
+#define MAP_PWMIntDisable \
+ PWMIntDisable
+#endif
+#ifdef ROM_PWMFaultIntClear
+#define MAP_PWMFaultIntClear \
+ ROM_PWMFaultIntClear
+#else
+#define MAP_PWMFaultIntClear \
+ PWMFaultIntClear
+#endif
+#ifdef ROM_PWMIntStatus
+#define MAP_PWMIntStatus \
+ ROM_PWMIntStatus
+#else
+#define MAP_PWMIntStatus \
+ PWMIntStatus
+#endif
+#ifdef ROM_PWMOutputFaultLevel
+#define MAP_PWMOutputFaultLevel \
+ ROM_PWMOutputFaultLevel
+#else
+#define MAP_PWMOutputFaultLevel \
+ PWMOutputFaultLevel
+#endif
+#ifdef ROM_PWMFaultIntClearExt
+#define MAP_PWMFaultIntClearExt \
+ ROM_PWMFaultIntClearExt
+#else
+#define MAP_PWMFaultIntClearExt \
+ PWMFaultIntClearExt
+#endif
+#ifdef ROM_PWMGenFaultConfigure
+#define MAP_PWMGenFaultConfigure \
+ ROM_PWMGenFaultConfigure
+#else
+#define MAP_PWMGenFaultConfigure \
+ PWMGenFaultConfigure
+#endif
+#ifdef ROM_PWMGenFaultTriggerSet
+#define MAP_PWMGenFaultTriggerSet \
+ ROM_PWMGenFaultTriggerSet
+#else
+#define MAP_PWMGenFaultTriggerSet \
+ PWMGenFaultTriggerSet
+#endif
+#ifdef ROM_PWMGenFaultTriggerGet
+#define MAP_PWMGenFaultTriggerGet \
+ ROM_PWMGenFaultTriggerGet
+#else
+#define MAP_PWMGenFaultTriggerGet \
+ PWMGenFaultTriggerGet
+#endif
+#ifdef ROM_PWMGenFaultStatus
+#define MAP_PWMGenFaultStatus \
+ ROM_PWMGenFaultStatus
+#else
+#define MAP_PWMGenFaultStatus \
+ PWMGenFaultStatus
+#endif
+#ifdef ROM_PWMGenFaultClear
+#define MAP_PWMGenFaultClear \
+ ROM_PWMGenFaultClear
+#else
+#define MAP_PWMGenFaultClear \
+ PWMGenFaultClear
+#endif
+
+//*****************************************************************************
+//
+// Macros for the QEI API.
+//
+//*****************************************************************************
+#ifdef ROM_QEIPositionGet
+#define MAP_QEIPositionGet \
+ ROM_QEIPositionGet
+#else
+#define MAP_QEIPositionGet \
+ QEIPositionGet
+#endif
+#ifdef ROM_QEIEnable
+#define MAP_QEIEnable \
+ ROM_QEIEnable
+#else
+#define MAP_QEIEnable \
+ QEIEnable
+#endif
+#ifdef ROM_QEIDisable
+#define MAP_QEIDisable \
+ ROM_QEIDisable
+#else
+#define MAP_QEIDisable \
+ QEIDisable
+#endif
+#ifdef ROM_QEIConfigure
+#define MAP_QEIConfigure \
+ ROM_QEIConfigure
+#else
+#define MAP_QEIConfigure \
+ QEIConfigure
+#endif
+#ifdef ROM_QEIPositionSet
+#define MAP_QEIPositionSet \
+ ROM_QEIPositionSet
+#else
+#define MAP_QEIPositionSet \
+ QEIPositionSet
+#endif
+#ifdef ROM_QEIDirectionGet
+#define MAP_QEIDirectionGet \
+ ROM_QEIDirectionGet
+#else
+#define MAP_QEIDirectionGet \
+ QEIDirectionGet
+#endif
+#ifdef ROM_QEIErrorGet
+#define MAP_QEIErrorGet \
+ ROM_QEIErrorGet
+#else
+#define MAP_QEIErrorGet \
+ QEIErrorGet
+#endif
+#ifdef ROM_QEIVelocityEnable
+#define MAP_QEIVelocityEnable \
+ ROM_QEIVelocityEnable
+#else
+#define MAP_QEIVelocityEnable \
+ QEIVelocityEnable
+#endif
+#ifdef ROM_QEIVelocityDisable
+#define MAP_QEIVelocityDisable \
+ ROM_QEIVelocityDisable
+#else
+#define MAP_QEIVelocityDisable \
+ QEIVelocityDisable
+#endif
+#ifdef ROM_QEIVelocityConfigure
+#define MAP_QEIVelocityConfigure \
+ ROM_QEIVelocityConfigure
+#else
+#define MAP_QEIVelocityConfigure \
+ QEIVelocityConfigure
+#endif
+#ifdef ROM_QEIVelocityGet
+#define MAP_QEIVelocityGet \
+ ROM_QEIVelocityGet
+#else
+#define MAP_QEIVelocityGet \
+ QEIVelocityGet
+#endif
+#ifdef ROM_QEIIntEnable
+#define MAP_QEIIntEnable \
+ ROM_QEIIntEnable
+#else
+#define MAP_QEIIntEnable \
+ QEIIntEnable
+#endif
+#ifdef ROM_QEIIntDisable
+#define MAP_QEIIntDisable \
+ ROM_QEIIntDisable
+#else
+#define MAP_QEIIntDisable \
+ QEIIntDisable
+#endif
+#ifdef ROM_QEIIntStatus
+#define MAP_QEIIntStatus \
+ ROM_QEIIntStatus
+#else
+#define MAP_QEIIntStatus \
+ QEIIntStatus
+#endif
+#ifdef ROM_QEIIntClear
+#define MAP_QEIIntClear \
+ ROM_QEIIntClear
+#else
+#define MAP_QEIIntClear \
+ QEIIntClear
+#endif
+
+//*****************************************************************************
+//
+// Macros for the SSI API.
+//
+//*****************************************************************************
+#ifdef ROM_SSIDataPut
+#define MAP_SSIDataPut \
+ ROM_SSIDataPut
+#else
+#define MAP_SSIDataPut \
+ SSIDataPut
+#endif
+#ifdef ROM_SSIConfigSetExpClk
+#define MAP_SSIConfigSetExpClk \
+ ROM_SSIConfigSetExpClk
+#else
+#define MAP_SSIConfigSetExpClk \
+ SSIConfigSetExpClk
+#endif
+#ifdef ROM_SSIEnable
+#define MAP_SSIEnable \
+ ROM_SSIEnable
+#else
+#define MAP_SSIEnable \
+ SSIEnable
+#endif
+#ifdef ROM_SSIDisable
+#define MAP_SSIDisable \
+ ROM_SSIDisable
+#else
+#define MAP_SSIDisable \
+ SSIDisable
+#endif
+#ifdef ROM_SSIIntEnable
+#define MAP_SSIIntEnable \
+ ROM_SSIIntEnable
+#else
+#define MAP_SSIIntEnable \
+ SSIIntEnable
+#endif
+#ifdef ROM_SSIIntDisable
+#define MAP_SSIIntDisable \
+ ROM_SSIIntDisable
+#else
+#define MAP_SSIIntDisable \
+ SSIIntDisable
+#endif
+#ifdef ROM_SSIIntStatus
+#define MAP_SSIIntStatus \
+ ROM_SSIIntStatus
+#else
+#define MAP_SSIIntStatus \
+ SSIIntStatus
+#endif
+#ifdef ROM_SSIIntClear
+#define MAP_SSIIntClear \
+ ROM_SSIIntClear
+#else
+#define MAP_SSIIntClear \
+ SSIIntClear
+#endif
+#ifdef ROM_SSIDataPutNonBlocking
+#define MAP_SSIDataPutNonBlocking \
+ ROM_SSIDataPutNonBlocking
+#else
+#define MAP_SSIDataPutNonBlocking \
+ SSIDataPutNonBlocking
+#endif
+#ifdef ROM_SSIDataGet
+#define MAP_SSIDataGet \
+ ROM_SSIDataGet
+#else
+#define MAP_SSIDataGet \
+ SSIDataGet
+#endif
+#ifdef ROM_SSIDataGetNonBlocking
+#define MAP_SSIDataGetNonBlocking \
+ ROM_SSIDataGetNonBlocking
+#else
+#define MAP_SSIDataGetNonBlocking \
+ SSIDataGetNonBlocking
+#endif
+#ifdef ROM_SSIDMAEnable
+#define MAP_SSIDMAEnable \
+ ROM_SSIDMAEnable
+#else
+#define MAP_SSIDMAEnable \
+ SSIDMAEnable
+#endif
+#ifdef ROM_SSIDMADisable
+#define MAP_SSIDMADisable \
+ ROM_SSIDMADisable
+#else
+#define MAP_SSIDMADisable \
+ SSIDMADisable
+#endif
+
+//*****************************************************************************
+//
+// Macros for the SysCtl API.
+//
+//*****************************************************************************
+#ifdef ROM_SysCtlSleep
+#define MAP_SysCtlSleep \
+ ROM_SysCtlSleep
+#else
+#define MAP_SysCtlSleep \
+ SysCtlSleep
+#endif
+#ifdef ROM_SysCtlSRAMSizeGet
+#define MAP_SysCtlSRAMSizeGet \
+ ROM_SysCtlSRAMSizeGet
+#else
+#define MAP_SysCtlSRAMSizeGet \
+ SysCtlSRAMSizeGet
+#endif
+#ifdef ROM_SysCtlFlashSizeGet
+#define MAP_SysCtlFlashSizeGet \
+ ROM_SysCtlFlashSizeGet
+#else
+#define MAP_SysCtlFlashSizeGet \
+ SysCtlFlashSizeGet
+#endif
+#ifdef ROM_SysCtlPinPresent
+#define MAP_SysCtlPinPresent \
+ ROM_SysCtlPinPresent
+#else
+#define MAP_SysCtlPinPresent \
+ SysCtlPinPresent
+#endif
+#ifdef ROM_SysCtlPeripheralPresent
+#define MAP_SysCtlPeripheralPresent \
+ ROM_SysCtlPeripheralPresent
+#else
+#define MAP_SysCtlPeripheralPresent \
+ SysCtlPeripheralPresent
+#endif
+#ifdef ROM_SysCtlPeripheralReset
+#define MAP_SysCtlPeripheralReset \
+ ROM_SysCtlPeripheralReset
+#else
+#define MAP_SysCtlPeripheralReset \
+ SysCtlPeripheralReset
+#endif
+#ifdef ROM_SysCtlPeripheralEnable
+#define MAP_SysCtlPeripheralEnable \
+ ROM_SysCtlPeripheralEnable
+#else
+#define MAP_SysCtlPeripheralEnable \
+ SysCtlPeripheralEnable
+#endif
+#ifdef ROM_SysCtlPeripheralDisable
+#define MAP_SysCtlPeripheralDisable \
+ ROM_SysCtlPeripheralDisable
+#else
+#define MAP_SysCtlPeripheralDisable \
+ SysCtlPeripheralDisable
+#endif
+#ifdef ROM_SysCtlPeripheralSleepEnable
+#define MAP_SysCtlPeripheralSleepEnable \
+ ROM_SysCtlPeripheralSleepEnable
+#else
+#define MAP_SysCtlPeripheralSleepEnable \
+ SysCtlPeripheralSleepEnable
+#endif
+#ifdef ROM_SysCtlPeripheralSleepDisable
+#define MAP_SysCtlPeripheralSleepDisable \
+ ROM_SysCtlPeripheralSleepDisable
+#else
+#define MAP_SysCtlPeripheralSleepDisable \
+ SysCtlPeripheralSleepDisable
+#endif
+#ifdef ROM_SysCtlPeripheralDeepSleepEnable
+#define MAP_SysCtlPeripheralDeepSleepEnable \
+ ROM_SysCtlPeripheralDeepSleepEnable
+#else
+#define MAP_SysCtlPeripheralDeepSleepEnable \
+ SysCtlPeripheralDeepSleepEnable
+#endif
+#ifdef ROM_SysCtlPeripheralDeepSleepDisable
+#define MAP_SysCtlPeripheralDeepSleepDisable \
+ ROM_SysCtlPeripheralDeepSleepDisable
+#else
+#define MAP_SysCtlPeripheralDeepSleepDisable \
+ SysCtlPeripheralDeepSleepDisable
+#endif
+#ifdef ROM_SysCtlPeripheralClockGating
+#define MAP_SysCtlPeripheralClockGating \
+ ROM_SysCtlPeripheralClockGating
+#else
+#define MAP_SysCtlPeripheralClockGating \
+ SysCtlPeripheralClockGating
+#endif
+#ifdef ROM_SysCtlIntEnable
+#define MAP_SysCtlIntEnable \
+ ROM_SysCtlIntEnable
+#else
+#define MAP_SysCtlIntEnable \
+ SysCtlIntEnable
+#endif
+#ifdef ROM_SysCtlIntDisable
+#define MAP_SysCtlIntDisable \
+ ROM_SysCtlIntDisable
+#else
+#define MAP_SysCtlIntDisable \
+ SysCtlIntDisable
+#endif
+#ifdef ROM_SysCtlIntClear
+#define MAP_SysCtlIntClear \
+ ROM_SysCtlIntClear
+#else
+#define MAP_SysCtlIntClear \
+ SysCtlIntClear
+#endif
+#ifdef ROM_SysCtlIntStatus
+#define MAP_SysCtlIntStatus \
+ ROM_SysCtlIntStatus
+#else
+#define MAP_SysCtlIntStatus \
+ SysCtlIntStatus
+#endif
+#ifdef ROM_SysCtlLDOSet
+#define MAP_SysCtlLDOSet \
+ ROM_SysCtlLDOSet
+#else
+#define MAP_SysCtlLDOSet \
+ SysCtlLDOSet
+#endif
+#ifdef ROM_SysCtlLDOGet
+#define MAP_SysCtlLDOGet \
+ ROM_SysCtlLDOGet
+#else
+#define MAP_SysCtlLDOGet \
+ SysCtlLDOGet
+#endif
+#ifdef ROM_SysCtlReset
+#define MAP_SysCtlReset \
+ ROM_SysCtlReset
+#else
+#define MAP_SysCtlReset \
+ SysCtlReset
+#endif
+#ifdef ROM_SysCtlDeepSleep
+#define MAP_SysCtlDeepSleep \
+ ROM_SysCtlDeepSleep
+#else
+#define MAP_SysCtlDeepSleep \
+ SysCtlDeepSleep
+#endif
+#ifdef ROM_SysCtlResetCauseGet
+#define MAP_SysCtlResetCauseGet \
+ ROM_SysCtlResetCauseGet
+#else
+#define MAP_SysCtlResetCauseGet \
+ SysCtlResetCauseGet
+#endif
+#ifdef ROM_SysCtlResetCauseClear
+#define MAP_SysCtlResetCauseClear \
+ ROM_SysCtlResetCauseClear
+#else
+#define MAP_SysCtlResetCauseClear \
+ SysCtlResetCauseClear
+#endif
+#ifdef ROM_SysCtlClockSet
+#define MAP_SysCtlClockSet \
+ ROM_SysCtlClockSet
+#else
+#define MAP_SysCtlClockSet \
+ SysCtlClockSet
+#endif
+#ifdef ROM_SysCtlClockGet
+#define MAP_SysCtlClockGet \
+ ROM_SysCtlClockGet
+#else
+#define MAP_SysCtlClockGet \
+ SysCtlClockGet
+#endif
+#ifdef ROM_SysCtlPWMClockSet
+#define MAP_SysCtlPWMClockSet \
+ ROM_SysCtlPWMClockSet
+#else
+#define MAP_SysCtlPWMClockSet \
+ SysCtlPWMClockSet
+#endif
+#ifdef ROM_SysCtlPWMClockGet
+#define MAP_SysCtlPWMClockGet \
+ ROM_SysCtlPWMClockGet
+#else
+#define MAP_SysCtlPWMClockGet \
+ SysCtlPWMClockGet
+#endif
+#ifdef ROM_SysCtlADCSpeedSet
+#define MAP_SysCtlADCSpeedSet \
+ ROM_SysCtlADCSpeedSet
+#else
+#define MAP_SysCtlADCSpeedSet \
+ SysCtlADCSpeedSet
+#endif
+#ifdef ROM_SysCtlADCSpeedGet
+#define MAP_SysCtlADCSpeedGet \
+ ROM_SysCtlADCSpeedGet
+#else
+#define MAP_SysCtlADCSpeedGet \
+ SysCtlADCSpeedGet
+#endif
+#ifdef ROM_SysCtlGPIOAHBEnable
+#define MAP_SysCtlGPIOAHBEnable \
+ ROM_SysCtlGPIOAHBEnable
+#else
+#define MAP_SysCtlGPIOAHBEnable \
+ SysCtlGPIOAHBEnable
+#endif
+#ifdef ROM_SysCtlGPIOAHBDisable
+#define MAP_SysCtlGPIOAHBDisable \
+ ROM_SysCtlGPIOAHBDisable
+#else
+#define MAP_SysCtlGPIOAHBDisable \
+ SysCtlGPIOAHBDisable
+#endif
+#ifdef ROM_SysCtlUSBPLLEnable
+#define MAP_SysCtlUSBPLLEnable \
+ ROM_SysCtlUSBPLLEnable
+#else
+#define MAP_SysCtlUSBPLLEnable \
+ SysCtlUSBPLLEnable
+#endif
+#ifdef ROM_SysCtlUSBPLLDisable
+#define MAP_SysCtlUSBPLLDisable \
+ ROM_SysCtlUSBPLLDisable
+#else
+#define MAP_SysCtlUSBPLLDisable \
+ SysCtlUSBPLLDisable
+#endif
+
+//*****************************************************************************
+//
+// Macros for the SysTick API.
+//
+//*****************************************************************************
+#ifdef ROM_SysTickValueGet
+#define MAP_SysTickValueGet \
+ ROM_SysTickValueGet
+#else
+#define MAP_SysTickValueGet \
+ SysTickValueGet
+#endif
+#ifdef ROM_SysTickEnable
+#define MAP_SysTickEnable \
+ ROM_SysTickEnable
+#else
+#define MAP_SysTickEnable \
+ SysTickEnable
+#endif
+#ifdef ROM_SysTickDisable
+#define MAP_SysTickDisable \
+ ROM_SysTickDisable
+#else
+#define MAP_SysTickDisable \
+ SysTickDisable
+#endif
+#ifdef ROM_SysTickIntEnable
+#define MAP_SysTickIntEnable \
+ ROM_SysTickIntEnable
+#else
+#define MAP_SysTickIntEnable \
+ SysTickIntEnable
+#endif
+#ifdef ROM_SysTickIntDisable
+#define MAP_SysTickIntDisable \
+ ROM_SysTickIntDisable
+#else
+#define MAP_SysTickIntDisable \
+ SysTickIntDisable
+#endif
+#ifdef ROM_SysTickPeriodSet
+#define MAP_SysTickPeriodSet \
+ ROM_SysTickPeriodSet
+#else
+#define MAP_SysTickPeriodSet \
+ SysTickPeriodSet
+#endif
+#ifdef ROM_SysTickPeriodGet
+#define MAP_SysTickPeriodGet \
+ ROM_SysTickPeriodGet
+#else
+#define MAP_SysTickPeriodGet \
+ SysTickPeriodGet
+#endif
+
+//*****************************************************************************
+//
+// Macros for the Timer API.
+//
+//*****************************************************************************
+#ifdef ROM_TimerIntClear
+#define MAP_TimerIntClear \
+ ROM_TimerIntClear
+#else
+#define MAP_TimerIntClear \
+ TimerIntClear
+#endif
+#ifdef ROM_TimerEnable
+#define MAP_TimerEnable \
+ ROM_TimerEnable
+#else
+#define MAP_TimerEnable \
+ TimerEnable
+#endif
+#ifdef ROM_TimerDisable
+#define MAP_TimerDisable \
+ ROM_TimerDisable
+#else
+#define MAP_TimerDisable \
+ TimerDisable
+#endif
+#ifdef ROM_TimerConfigure
+#define MAP_TimerConfigure \
+ ROM_TimerConfigure
+#else
+#define MAP_TimerConfigure \
+ TimerConfigure
+#endif
+#ifdef ROM_TimerControlLevel
+#define MAP_TimerControlLevel \
+ ROM_TimerControlLevel
+#else
+#define MAP_TimerControlLevel \
+ TimerControlLevel
+#endif
+#ifdef ROM_TimerControlTrigger
+#define MAP_TimerControlTrigger \
+ ROM_TimerControlTrigger
+#else
+#define MAP_TimerControlTrigger \
+ TimerControlTrigger
+#endif
+#ifdef ROM_TimerControlEvent
+#define MAP_TimerControlEvent \
+ ROM_TimerControlEvent
+#else
+#define MAP_TimerControlEvent \
+ TimerControlEvent
+#endif
+#ifdef ROM_TimerControlStall
+#define MAP_TimerControlStall \
+ ROM_TimerControlStall
+#else
+#define MAP_TimerControlStall \
+ TimerControlStall
+#endif
+#ifdef ROM_TimerRTCEnable
+#define MAP_TimerRTCEnable \
+ ROM_TimerRTCEnable
+#else
+#define MAP_TimerRTCEnable \
+ TimerRTCEnable
+#endif
+#ifdef ROM_TimerRTCDisable
+#define MAP_TimerRTCDisable \
+ ROM_TimerRTCDisable
+#else
+#define MAP_TimerRTCDisable \
+ TimerRTCDisable
+#endif
+#ifdef ROM_TimerPrescaleSet
+#define MAP_TimerPrescaleSet \
+ ROM_TimerPrescaleSet
+#else
+#define MAP_TimerPrescaleSet \
+ TimerPrescaleSet
+#endif
+#ifdef ROM_TimerPrescaleGet
+#define MAP_TimerPrescaleGet \
+ ROM_TimerPrescaleGet
+#else
+#define MAP_TimerPrescaleGet \
+ TimerPrescaleGet
+#endif
+#ifdef ROM_TimerLoadSet
+#define MAP_TimerLoadSet \
+ ROM_TimerLoadSet
+#else
+#define MAP_TimerLoadSet \
+ TimerLoadSet
+#endif
+#ifdef ROM_TimerLoadGet
+#define MAP_TimerLoadGet \
+ ROM_TimerLoadGet
+#else
+#define MAP_TimerLoadGet \
+ TimerLoadGet
+#endif
+#ifdef ROM_TimerValueGet
+#define MAP_TimerValueGet \
+ ROM_TimerValueGet
+#else
+#define MAP_TimerValueGet \
+ TimerValueGet
+#endif
+#ifdef ROM_TimerMatchSet
+#define MAP_TimerMatchSet \
+ ROM_TimerMatchSet
+#else
+#define MAP_TimerMatchSet \
+ TimerMatchSet
+#endif
+#ifdef ROM_TimerMatchGet
+#define MAP_TimerMatchGet \
+ ROM_TimerMatchGet
+#else
+#define MAP_TimerMatchGet \
+ TimerMatchGet
+#endif
+#ifdef ROM_TimerIntEnable
+#define MAP_TimerIntEnable \
+ ROM_TimerIntEnable
+#else
+#define MAP_TimerIntEnable \
+ TimerIntEnable
+#endif
+#ifdef ROM_TimerIntDisable
+#define MAP_TimerIntDisable \
+ ROM_TimerIntDisable
+#else
+#define MAP_TimerIntDisable \
+ TimerIntDisable
+#endif
+#ifdef ROM_TimerIntStatus
+#define MAP_TimerIntStatus \
+ ROM_TimerIntStatus
+#else
+#define MAP_TimerIntStatus \
+ TimerIntStatus
+#endif
+
+//*****************************************************************************
+//
+// Macros for the UART API.
+//
+//*****************************************************************************
+#ifdef ROM_UARTCharPut
+#define MAP_UARTCharPut \
+ ROM_UARTCharPut
+#else
+#define MAP_UARTCharPut \
+ UARTCharPut
+#endif
+#ifdef ROM_UARTParityModeSet
+#define MAP_UARTParityModeSet \
+ ROM_UARTParityModeSet
+#else
+#define MAP_UARTParityModeSet \
+ UARTParityModeSet
+#endif
+#ifdef ROM_UARTParityModeGet
+#define MAP_UARTParityModeGet \
+ ROM_UARTParityModeGet
+#else
+#define MAP_UARTParityModeGet \
+ UARTParityModeGet
+#endif
+#ifdef ROM_UARTFIFOLevelSet
+#define MAP_UARTFIFOLevelSet \
+ ROM_UARTFIFOLevelSet
+#else
+#define MAP_UARTFIFOLevelSet \
+ UARTFIFOLevelSet
+#endif
+#ifdef ROM_UARTFIFOLevelGet
+#define MAP_UARTFIFOLevelGet \
+ ROM_UARTFIFOLevelGet
+#else
+#define MAP_UARTFIFOLevelGet \
+ UARTFIFOLevelGet
+#endif
+#ifdef ROM_UARTConfigSetExpClk
+#define MAP_UARTConfigSetExpClk \
+ ROM_UARTConfigSetExpClk
+#else
+#define MAP_UARTConfigSetExpClk \
+ UARTConfigSetExpClk
+#endif
+#ifdef ROM_UARTConfigGetExpClk
+#define MAP_UARTConfigGetExpClk \
+ ROM_UARTConfigGetExpClk
+#else
+#define MAP_UARTConfigGetExpClk \
+ UARTConfigGetExpClk
+#endif
+#ifdef ROM_UARTEnable
+#define MAP_UARTEnable \
+ ROM_UARTEnable
+#else
+#define MAP_UARTEnable \
+ UARTEnable
+#endif
+#ifdef ROM_UARTDisable
+#define MAP_UARTDisable \
+ ROM_UARTDisable
+#else
+#define MAP_UARTDisable \
+ UARTDisable
+#endif
+#ifdef ROM_UARTEnableSIR
+#define MAP_UARTEnableSIR \
+ ROM_UARTEnableSIR
+#else
+#define MAP_UARTEnableSIR \
+ UARTEnableSIR
+#endif
+#ifdef ROM_UARTDisableSIR
+#define MAP_UARTDisableSIR \
+ ROM_UARTDisableSIR
+#else
+#define MAP_UARTDisableSIR \
+ UARTDisableSIR
+#endif
+#ifdef ROM_UARTCharsAvail
+#define MAP_UARTCharsAvail \
+ ROM_UARTCharsAvail
+#else
+#define MAP_UARTCharsAvail \
+ UARTCharsAvail
+#endif
+#ifdef ROM_UARTSpaceAvail
+#define MAP_UARTSpaceAvail \
+ ROM_UARTSpaceAvail
+#else
+#define MAP_UARTSpaceAvail \
+ UARTSpaceAvail
+#endif
+#ifdef ROM_UARTCharGetNonBlocking
+#define MAP_UARTCharGetNonBlocking \
+ ROM_UARTCharGetNonBlocking
+#else
+#define MAP_UARTCharGetNonBlocking \
+ UARTCharGetNonBlocking
+#endif
+#ifdef ROM_UARTCharGet
+#define MAP_UARTCharGet \
+ ROM_UARTCharGet
+#else
+#define MAP_UARTCharGet \
+ UARTCharGet
+#endif
+#ifdef ROM_UARTCharPutNonBlocking
+#define MAP_UARTCharPutNonBlocking \
+ ROM_UARTCharPutNonBlocking
+#else
+#define MAP_UARTCharPutNonBlocking \
+ UARTCharPutNonBlocking
+#endif
+#ifdef ROM_UARTBreakCtl
+#define MAP_UARTBreakCtl \
+ ROM_UARTBreakCtl
+#else
+#define MAP_UARTBreakCtl \
+ UARTBreakCtl
+#endif
+#ifdef ROM_UARTIntEnable
+#define MAP_UARTIntEnable \
+ ROM_UARTIntEnable
+#else
+#define MAP_UARTIntEnable \
+ UARTIntEnable
+#endif
+#ifdef ROM_UARTIntDisable
+#define MAP_UARTIntDisable \
+ ROM_UARTIntDisable
+#else
+#define MAP_UARTIntDisable \
+ UARTIntDisable
+#endif
+#ifdef ROM_UARTIntStatus
+#define MAP_UARTIntStatus \
+ ROM_UARTIntStatus
+#else
+#define MAP_UARTIntStatus \
+ UARTIntStatus
+#endif
+#ifdef ROM_UARTIntClear
+#define MAP_UARTIntClear \
+ ROM_UARTIntClear
+#else
+#define MAP_UARTIntClear \
+ UARTIntClear
+#endif
+#ifdef ROM_UARTDMAEnable
+#define MAP_UARTDMAEnable \
+ ROM_UARTDMAEnable
+#else
+#define MAP_UARTDMAEnable \
+ UARTDMAEnable
+#endif
+#ifdef ROM_UARTDMADisable
+#define MAP_UARTDMADisable \
+ ROM_UARTDMADisable
+#else
+#define MAP_UARTDMADisable \
+ UARTDMADisable
+#endif
+
+//*****************************************************************************
+//
+// Macros for the uDMA API.
+//
+//*****************************************************************************
+#ifdef ROM_uDMAChannelTransferSet
+#define MAP_uDMAChannelTransferSet \
+ ROM_uDMAChannelTransferSet
+#else
+#define MAP_uDMAChannelTransferSet \
+ uDMAChannelTransferSet
+#endif
+#ifdef ROM_uDMAEnable
+#define MAP_uDMAEnable \
+ ROM_uDMAEnable
+#else
+#define MAP_uDMAEnable \
+ uDMAEnable
+#endif
+#ifdef ROM_uDMADisable
+#define MAP_uDMADisable \
+ ROM_uDMADisable
+#else
+#define MAP_uDMADisable \
+ uDMADisable
+#endif
+#ifdef ROM_uDMAErrorStatusGet
+#define MAP_uDMAErrorStatusGet \
+ ROM_uDMAErrorStatusGet
+#else
+#define MAP_uDMAErrorStatusGet \
+ uDMAErrorStatusGet
+#endif
+#ifdef ROM_uDMAErrorStatusClear
+#define MAP_uDMAErrorStatusClear \
+ ROM_uDMAErrorStatusClear
+#else
+#define MAP_uDMAErrorStatusClear \
+ uDMAErrorStatusClear
+#endif
+#ifdef ROM_uDMAChannelEnable
+#define MAP_uDMAChannelEnable \
+ ROM_uDMAChannelEnable
+#else
+#define MAP_uDMAChannelEnable \
+ uDMAChannelEnable
+#endif
+#ifdef ROM_uDMAChannelDisable
+#define MAP_uDMAChannelDisable \
+ ROM_uDMAChannelDisable
+#else
+#define MAP_uDMAChannelDisable \
+ uDMAChannelDisable
+#endif
+#ifdef ROM_uDMAChannelIsEnabled
+#define MAP_uDMAChannelIsEnabled \
+ ROM_uDMAChannelIsEnabled
+#else
+#define MAP_uDMAChannelIsEnabled \
+ uDMAChannelIsEnabled
+#endif
+#ifdef ROM_uDMAControlBaseSet
+#define MAP_uDMAControlBaseSet \
+ ROM_uDMAControlBaseSet
+#else
+#define MAP_uDMAControlBaseSet \
+ uDMAControlBaseSet
+#endif
+#ifdef ROM_uDMAControlBaseGet
+#define MAP_uDMAControlBaseGet \
+ ROM_uDMAControlBaseGet
+#else
+#define MAP_uDMAControlBaseGet \
+ uDMAControlBaseGet
+#endif
+#ifdef ROM_uDMAChannelRequest
+#define MAP_uDMAChannelRequest \
+ ROM_uDMAChannelRequest
+#else
+#define MAP_uDMAChannelRequest \
+ uDMAChannelRequest
+#endif
+#ifdef ROM_uDMAChannelAttributeEnable
+#define MAP_uDMAChannelAttributeEnable \
+ ROM_uDMAChannelAttributeEnable
+#else
+#define MAP_uDMAChannelAttributeEnable \
+ uDMAChannelAttributeEnable
+#endif
+#ifdef ROM_uDMAChannelAttributeDisable
+#define MAP_uDMAChannelAttributeDisable \
+ ROM_uDMAChannelAttributeDisable
+#else
+#define MAP_uDMAChannelAttributeDisable \
+ uDMAChannelAttributeDisable
+#endif
+#ifdef ROM_uDMAChannelAttributeGet
+#define MAP_uDMAChannelAttributeGet \
+ ROM_uDMAChannelAttributeGet
+#else
+#define MAP_uDMAChannelAttributeGet \
+ uDMAChannelAttributeGet
+#endif
+#ifdef ROM_uDMAChannelControlSet
+#define MAP_uDMAChannelControlSet \
+ ROM_uDMAChannelControlSet
+#else
+#define MAP_uDMAChannelControlSet \
+ uDMAChannelControlSet
+#endif
+#ifdef ROM_uDMAChannelSizeGet
+#define MAP_uDMAChannelSizeGet \
+ ROM_uDMAChannelSizeGet
+#else
+#define MAP_uDMAChannelSizeGet \
+ uDMAChannelSizeGet
+#endif
+#ifdef ROM_uDMAChannelModeGet
+#define MAP_uDMAChannelModeGet \
+ ROM_uDMAChannelModeGet
+#else
+#define MAP_uDMAChannelModeGet \
+ uDMAChannelModeGet
+#endif
+
+//*****************************************************************************
+//
+// Macros for the USB API.
+//
+//*****************************************************************************
+#ifdef ROM_USBIntStatus
+#define MAP_USBIntStatus \
+ ROM_USBIntStatus
+#else
+#define MAP_USBIntStatus \
+ USBIntStatus
+#endif
+#ifdef ROM_USBDevAddrGet
+#define MAP_USBDevAddrGet \
+ ROM_USBDevAddrGet
+#else
+#define MAP_USBDevAddrGet \
+ USBDevAddrGet
+#endif
+#ifdef ROM_USBDevAddrSet
+#define MAP_USBDevAddrSet \
+ ROM_USBDevAddrSet
+#else
+#define MAP_USBDevAddrSet \
+ USBDevAddrSet
+#endif
+#ifdef ROM_USBDevConnect
+#define MAP_USBDevConnect \
+ ROM_USBDevConnect
+#else
+#define MAP_USBDevConnect \
+ USBDevConnect
+#endif
+#ifdef ROM_USBDevDisconnect
+#define MAP_USBDevDisconnect \
+ ROM_USBDevDisconnect
+#else
+#define MAP_USBDevDisconnect \
+ USBDevDisconnect
+#endif
+#ifdef ROM_USBDevEndpointConfig
+#define MAP_USBDevEndpointConfig \
+ ROM_USBDevEndpointConfig
+#else
+#define MAP_USBDevEndpointConfig \
+ USBDevEndpointConfig
+#endif
+#ifdef ROM_USBDevEndpointDataAck
+#define MAP_USBDevEndpointDataAck \
+ ROM_USBDevEndpointDataAck
+#else
+#define MAP_USBDevEndpointDataAck \
+ USBDevEndpointDataAck
+#endif
+#ifdef ROM_USBDevEndpointStall
+#define MAP_USBDevEndpointStall \
+ ROM_USBDevEndpointStall
+#else
+#define MAP_USBDevEndpointStall \
+ USBDevEndpointStall
+#endif
+#ifdef ROM_USBDevEndpointStallClear
+#define MAP_USBDevEndpointStallClear \
+ ROM_USBDevEndpointStallClear
+#else
+#define MAP_USBDevEndpointStallClear \
+ USBDevEndpointStallClear
+#endif
+#ifdef ROM_USBDevEndpointStatusClear
+#define MAP_USBDevEndpointStatusClear \
+ ROM_USBDevEndpointStatusClear
+#else
+#define MAP_USBDevEndpointStatusClear \
+ USBDevEndpointStatusClear
+#endif
+#ifdef ROM_USBEndpointDataGet
+#define MAP_USBEndpointDataGet \
+ ROM_USBEndpointDataGet
+#else
+#define MAP_USBEndpointDataGet \
+ USBEndpointDataGet
+#endif
+#ifdef ROM_USBEndpointDataPut
+#define MAP_USBEndpointDataPut \
+ ROM_USBEndpointDataPut
+#else
+#define MAP_USBEndpointDataPut \
+ USBEndpointDataPut
+#endif
+#ifdef ROM_USBEndpointDataSend
+#define MAP_USBEndpointDataSend \
+ ROM_USBEndpointDataSend
+#else
+#define MAP_USBEndpointDataSend \
+ USBEndpointDataSend
+#endif
+#ifdef ROM_USBEndpointDataToggleClear
+#define MAP_USBEndpointDataToggleClear \
+ ROM_USBEndpointDataToggleClear
+#else
+#define MAP_USBEndpointDataToggleClear \
+ USBEndpointDataToggleClear
+#endif
+#ifdef ROM_USBEndpointStatus
+#define MAP_USBEndpointStatus \
+ ROM_USBEndpointStatus
+#else
+#define MAP_USBEndpointStatus \
+ USBEndpointStatus
+#endif
+#ifdef ROM_USBFIFOAddrGet
+#define MAP_USBFIFOAddrGet \
+ ROM_USBFIFOAddrGet
+#else
+#define MAP_USBFIFOAddrGet \
+ USBFIFOAddrGet
+#endif
+#ifdef ROM_USBFIFOConfigGet
+#define MAP_USBFIFOConfigGet \
+ ROM_USBFIFOConfigGet
+#else
+#define MAP_USBFIFOConfigGet \
+ USBFIFOConfigGet
+#endif
+#ifdef ROM_USBFIFOConfigSet
+#define MAP_USBFIFOConfigSet \
+ ROM_USBFIFOConfigSet
+#else
+#define MAP_USBFIFOConfigSet \
+ USBFIFOConfigSet
+#endif
+#ifdef ROM_USBFIFOFlush
+#define MAP_USBFIFOFlush \
+ ROM_USBFIFOFlush
+#else
+#define MAP_USBFIFOFlush \
+ USBFIFOFlush
+#endif
+#ifdef ROM_USBFrameNumberGet
+#define MAP_USBFrameNumberGet \
+ ROM_USBFrameNumberGet
+#else
+#define MAP_USBFrameNumberGet \
+ USBFrameNumberGet
+#endif
+#ifdef ROM_USBHostAddrGet
+#define MAP_USBHostAddrGet \
+ ROM_USBHostAddrGet
+#else
+#define MAP_USBHostAddrGet \
+ USBHostAddrGet
+#endif
+#ifdef ROM_USBHostAddrSet
+#define MAP_USBHostAddrSet \
+ ROM_USBHostAddrSet
+#else
+#define MAP_USBHostAddrSet \
+ USBHostAddrSet
+#endif
+#ifdef ROM_USBHostEndpointConfig
+#define MAP_USBHostEndpointConfig \
+ ROM_USBHostEndpointConfig
+#else
+#define MAP_USBHostEndpointConfig \
+ USBHostEndpointConfig
+#endif
+#ifdef ROM_USBHostEndpointDataAck
+#define MAP_USBHostEndpointDataAck \
+ ROM_USBHostEndpointDataAck
+#else
+#define MAP_USBHostEndpointDataAck \
+ USBHostEndpointDataAck
+#endif
+#ifdef ROM_USBHostEndpointDataToggle
+#define MAP_USBHostEndpointDataToggle \
+ ROM_USBHostEndpointDataToggle
+#else
+#define MAP_USBHostEndpointDataToggle \
+ USBHostEndpointDataToggle
+#endif
+#ifdef ROM_USBHostEndpointStatusClear
+#define MAP_USBHostEndpointStatusClear \
+ ROM_USBHostEndpointStatusClear
+#else
+#define MAP_USBHostEndpointStatusClear \
+ USBHostEndpointStatusClear
+#endif
+#ifdef ROM_USBHostHubAddrGet
+#define MAP_USBHostHubAddrGet \
+ ROM_USBHostHubAddrGet
+#else
+#define MAP_USBHostHubAddrGet \
+ USBHostHubAddrGet
+#endif
+#ifdef ROM_USBHostHubAddrSet
+#define MAP_USBHostHubAddrSet \
+ ROM_USBHostHubAddrSet
+#else
+#define MAP_USBHostHubAddrSet \
+ USBHostHubAddrSet
+#endif
+#ifdef ROM_USBHostPwrDisable
+#define MAP_USBHostPwrDisable \
+ ROM_USBHostPwrDisable
+#else
+#define MAP_USBHostPwrDisable \
+ USBHostPwrDisable
+#endif
+#ifdef ROM_USBHostPwrEnable
+#define MAP_USBHostPwrEnable \
+ ROM_USBHostPwrEnable
+#else
+#define MAP_USBHostPwrEnable \
+ USBHostPwrEnable
+#endif
+#ifdef ROM_USBHostPwrFaultConfig
+#define MAP_USBHostPwrFaultConfig \
+ ROM_USBHostPwrFaultConfig
+#else
+#define MAP_USBHostPwrFaultConfig \
+ USBHostPwrFaultConfig
+#endif
+#ifdef ROM_USBHostPwrFaultDisable
+#define MAP_USBHostPwrFaultDisable \
+ ROM_USBHostPwrFaultDisable
+#else
+#define MAP_USBHostPwrFaultDisable \
+ USBHostPwrFaultDisable
+#endif
+#ifdef ROM_USBHostPwrFaultEnable
+#define MAP_USBHostPwrFaultEnable \
+ ROM_USBHostPwrFaultEnable
+#else
+#define MAP_USBHostPwrFaultEnable \
+ USBHostPwrFaultEnable
+#endif
+#ifdef ROM_USBHostRequestIN
+#define MAP_USBHostRequestIN \
+ ROM_USBHostRequestIN
+#else
+#define MAP_USBHostRequestIN \
+ USBHostRequestIN
+#endif
+#ifdef ROM_USBHostRequestStatus
+#define MAP_USBHostRequestStatus \
+ ROM_USBHostRequestStatus
+#else
+#define MAP_USBHostRequestStatus \
+ USBHostRequestStatus
+#endif
+#ifdef ROM_USBHostReset
+#define MAP_USBHostReset \
+ ROM_USBHostReset
+#else
+#define MAP_USBHostReset \
+ USBHostReset
+#endif
+#ifdef ROM_USBHostResume
+#define MAP_USBHostResume \
+ ROM_USBHostResume
+#else
+#define MAP_USBHostResume \
+ USBHostResume
+#endif
+#ifdef ROM_USBHostSpeedGet
+#define MAP_USBHostSpeedGet \
+ ROM_USBHostSpeedGet
+#else
+#define MAP_USBHostSpeedGet \
+ USBHostSpeedGet
+#endif
+#ifdef ROM_USBHostSuspend
+#define MAP_USBHostSuspend \
+ ROM_USBHostSuspend
+#else
+#define MAP_USBHostSuspend \
+ USBHostSuspend
+#endif
+#ifdef ROM_USBIntDisable
+#define MAP_USBIntDisable \
+ ROM_USBIntDisable
+#else
+#define MAP_USBIntDisable \
+ USBIntDisable
+#endif
+#ifdef ROM_USBIntEnable
+#define MAP_USBIntEnable \
+ ROM_USBIntEnable
+#else
+#define MAP_USBIntEnable \
+ USBIntEnable
+#endif
+
+//*****************************************************************************
+//
+// Macros for the Watchdog API.
+//
+//*****************************************************************************
+#ifdef ROM_WatchdogIntClear
+#define MAP_WatchdogIntClear \
+ ROM_WatchdogIntClear
+#else
+#define MAP_WatchdogIntClear \
+ WatchdogIntClear
+#endif
+#ifdef ROM_WatchdogRunning
+#define MAP_WatchdogRunning \
+ ROM_WatchdogRunning
+#else
+#define MAP_WatchdogRunning \
+ WatchdogRunning
+#endif
+#ifdef ROM_WatchdogEnable
+#define MAP_WatchdogEnable \
+ ROM_WatchdogEnable
+#else
+#define MAP_WatchdogEnable \
+ WatchdogEnable
+#endif
+#ifdef ROM_WatchdogResetEnable
+#define MAP_WatchdogResetEnable \
+ ROM_WatchdogResetEnable
+#else
+#define MAP_WatchdogResetEnable \
+ WatchdogResetEnable
+#endif
+#ifdef ROM_WatchdogResetDisable
+#define MAP_WatchdogResetDisable \
+ ROM_WatchdogResetDisable
+#else
+#define MAP_WatchdogResetDisable \
+ WatchdogResetDisable
+#endif
+#ifdef ROM_WatchdogLock
+#define MAP_WatchdogLock \
+ ROM_WatchdogLock
+#else
+#define MAP_WatchdogLock \
+ WatchdogLock
+#endif
+#ifdef ROM_WatchdogUnlock
+#define MAP_WatchdogUnlock \
+ ROM_WatchdogUnlock
+#else
+#define MAP_WatchdogUnlock \
+ WatchdogUnlock
+#endif
+#ifdef ROM_WatchdogLockState
+#define MAP_WatchdogLockState \
+ ROM_WatchdogLockState
+#else
+#define MAP_WatchdogLockState \
+ WatchdogLockState
+#endif
+#ifdef ROM_WatchdogReloadSet
+#define MAP_WatchdogReloadSet \
+ ROM_WatchdogReloadSet
+#else
+#define MAP_WatchdogReloadSet \
+ WatchdogReloadSet
+#endif
+#ifdef ROM_WatchdogReloadGet
+#define MAP_WatchdogReloadGet \
+ ROM_WatchdogReloadGet
+#else
+#define MAP_WatchdogReloadGet \
+ WatchdogReloadGet
+#endif
+#ifdef ROM_WatchdogValueGet
+#define MAP_WatchdogValueGet \
+ ROM_WatchdogValueGet
+#else
+#define MAP_WatchdogValueGet \
+ WatchdogValueGet
+#endif
+#ifdef ROM_WatchdogIntEnable
+#define MAP_WatchdogIntEnable \
+ ROM_WatchdogIntEnable
+#else
+#define MAP_WatchdogIntEnable \
+ WatchdogIntEnable
+#endif
+#ifdef ROM_WatchdogIntStatus
+#define MAP_WatchdogIntStatus \
+ ROM_WatchdogIntStatus
+#else
+#define MAP_WatchdogIntStatus \
+ WatchdogIntStatus
+#endif
+#ifdef ROM_WatchdogStallEnable
+#define MAP_WatchdogStallEnable \
+ ROM_WatchdogStallEnable
+#else
+#define MAP_WatchdogStallEnable \
+ WatchdogStallEnable
+#endif
+#ifdef ROM_WatchdogStallDisable
+#define MAP_WatchdogStallDisable \
+ ROM_WatchdogStallDisable
+#else
+#define MAP_WatchdogStallDisable \
+ WatchdogStallDisable
+#endif
+
+#endif // __ROM_MAP_H__
Property changes on: branches/eagle_mmc/src/platform/lm3s/rom_map.h
___________________________________________________________________
Name: svn:executable
+ *
Modified: branches/eagle_mmc/src/platform/lm3s/ssi.c
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/ssi.c 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lm3s/ssi.c 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,681 +1,680 @@
-//*****************************************************************************
-//
-// ssi.c - Driver for Synchronous Serial Interface.
-//
-// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
-// Software License Agreement
-//
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
-//
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws. All rights are reserved. You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program. Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
-//
-// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-//
-// This is part of revision 3740 of the Stellaris Peripheral Driver Library.
-//
-//*****************************************************************************
-
-//*****************************************************************************
-//
-//! \addtogroup ssi_api
-//! @{
-//
-//*****************************************************************************
-
-#include "hw_ints.h"
-#include "hw_memmap.h"
-#include "hw_ssi.h"
-#include "hw_types.h"
-#include "debug.h"
-#include "interrupt.h"
-#include "ssi.h"
-#include "sysctl.h"
-
-//*****************************************************************************
-//
-//! Configures the synchronous serial interface.
-//!
-//! \param ulBase specifies the SSI module base address.
-//! \param ulSSIClk is the rate of the clock supplied to the SSI module.
-//! \param ulProtocol specifies the data transfer protocol.
-//! \param ulMode specifies the mode of operation.
-//! \param ulBitRate specifies the clock rate.
-//! \param ulDataWidth specifies number of bits transferred per frame.
-//!
-//! This function configures the synchronous serial interface. It sets
-//! the SSI protocol, mode of operation, bit rate, and data width.
-//!
-//! The \e ulProtocol parameter defines the data frame format. The
-//! \e ulProtocol parameter can be one of the following values:
-//! \b SSI_FRF_MOTO_MODE_0, \b SSI_FRF_MOTO_MODE_1, \b SSI_FRF_MOTO_MODE_2,
-//! \b SSI_FRF_MOTO_MODE_3, \b SSI_FRF_TI, or \b SSI_FRF_NMW. The Motorola
-//! frame formats imply the following polarity and phase configurations:
-//!
-//! <pre>
-//! Polarity Phase Mode
-//! 0 0 SSI_FRF_MOTO_MODE_0
-//! 0 1 SSI_FRF_MOTO_MODE_1
-//! 1 0 SSI_FRF_MOTO_MODE_2
-//! 1 1 SSI_FRF_MOTO_MODE_3
-//! </pre>
-//!
-//! The \e ulMode parameter defines the operating mode of the SSI module. The
-//! SSI module can operate as a master or slave; if a slave, the SSI can be
-//! configured to disable output on its serial output line. The \e ulMode
-//! parameter can be one of the following values: \b SSI_MODE_MASTER,
-//! \b SSI_MODE_SLAVE, or \b SSI_MODE_SLAVE_OD.
-//!
-//! The \e ulBitRate parameter defines the bit rate for the SSI. This bit rate
-//! must satisfy the following clock ratio criteria:
-//!
-//! - FSSI >= 2 * bit rate (master mode)
-//! - FSSI >= 12 * bit rate (slave modes)
-//!
-//! where FSSI is the frequency of the clock supplied to the SSI module.
-//!
-//! The \e ulDataWidth parameter defines the width of the data transfers, and
-//! can be a value between 4 and 16, inclusive.
-//!
-//! The peripheral clock will be the same as the processor clock. This will be
-//! the value returned by SysCtlClockGet(), or it can be explicitly hard coded
-//! if it is constant and known (to save the code/execution overhead of a call
-//! to SysCtlClockGet()).
-//!
-//! This function replaces the original SSIConfig() API and performs the same
-//! actions. A macro is provided in <tt>ssi.h</tt> to map the original API to
-//! this API.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SSIConfigSetExpClk(unsigned long ulBase, unsigned long ulSSIClk,
- unsigned long ulProtocol, unsigned long ulMode,
- unsigned long ulBitRate, unsigned long ulDataWidth)
-{
- unsigned long ulMaxBitRate;
- unsigned long ulRegVal;
- unsigned long ulPreDiv;
- unsigned long ulSCR;
- unsigned long ulSPH_SPO;
-
- //
- // Check the arguments.
- //
- ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
- ASSERT((ulProtocol == SSI_FRF_MOTO_MODE_0) ||
- (ulProtocol == SSI_FRF_MOTO_MODE_1) ||
- (ulProtocol == SSI_FRF_MOTO_MODE_2) ||
- (ulProtocol == SSI_FRF_MOTO_MODE_3) ||
- (ulProtocol == SSI_FRF_TI) ||
- (ulProtocol == SSI_FRF_NMW));
- ASSERT((ulMode == SSI_MODE_MASTER) ||
- (ulMode == SSI_MODE_SLAVE) ||
- (ulMode == SSI_MODE_SLAVE_OD));
- ASSERT(((ulMode == SSI_MODE_MASTER) && (ulBitRate <= (ulSSIClk / 2))) ||
- ((ulMode != SSI_MODE_MASTER) && (ulBitRate <= (ulSSIClk / 12))));
- ASSERT((ulSSIClk / ulBitRate) <= (254 * 256));
- ASSERT((ulDataWidth >= 4) && (ulDataWidth <= 16));
-
- //
- // Set the mode.
- //
- ulRegVal = (ulMode == SSI_MODE_SLAVE_OD) ? SSI_CR1_SOD : 0;
- ulRegVal |= (ulMode == SSI_MODE_MASTER) ? 0 : SSI_CR1_MS;
- HWREG(ulBase + SSI_O_CR1) = ulRegVal;
-
- //
- // Set the clock predivider.
- //
- ulMaxBitRate = ulSSIClk / ulBitRate;
- ulPreDiv = 0;
- do
- {
- ulPreDiv += 2;
- ulSCR = (ulMaxBitRate / ulPreDiv) - 1;
- }
- while(ulSCR > 255);
- HWREG(ulBase + SSI_O_CPSR) = ulPreDiv;
-
- //
- // Set protocol and clock rate.
- //
- ulSPH_SPO = ulProtocol << 6;
- ulProtocol &= SSI_CR0_FRF_M;
- ulRegVal = (ulSCR << 8) | ulSPH_SPO | ulProtocol | (ulDataWidth - 1);
- HWREG(ulBase + SSI_O_CR0) = ulRegVal;
-}
-
-//*****************************************************************************
-//
-//! Enables the synchronous serial interface.
-//!
-//! \param ulBase specifies the SSI module base address.
-//!
-//! This will enable operation of the synchronous serial interface. It must be
-//! configured before it is enabled.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SSIEnable(unsigned long ulBase)
-{
- //
- // Check the arguments.
- //
- ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
-
- //
- // Read-modify-write the enable bit.
- //
- HWREG(ulBase + SSI_O_CR1) |= SSI_CR1_SSE;
-}
-
-//*****************************************************************************
-//
-//! Disables the synchronous serial interface.
-//!
-//! \param ulBase specifies the SSI module base address.
-//!
-//! This will disable operation of the synchronous serial interface.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SSIDisable(unsigned long ulBase)
-{
- //
- // Check the arguments.
- //
- ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
-
- //
- // Read-modify-write the enable bit.
- //
- HWREG(ulBase + SSI_O_CR1) &= ~(SSI_CR1_SSE);
-}
-
-//*****************************************************************************
-//
-//! Registers an interrupt handler for the synchronous serial interface.
-//!
-//! \param ulBase specifies the SSI module base address.
-//! \param pfnHandler is a pointer to the function to be called when the
-//! synchronous serial interface interrupt occurs.
-//!
-//! This sets the handler to be called when an SSI interrupt
-//! occurs. This will enable the global interrupt in the interrupt controller;
-//! specific SSI interrupts must be enabled via SSIIntEnable(). If necessary,
-//! it is the interrupt handler's responsibility to clear the interrupt source
-//! via SSIIntClear().
-//!
-//! \sa IntRegister() for important information about registering interrupt
-//! handlers.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SSIIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
-{
- unsigned long ulInt;
-
- //
- // Check the arguments.
- //
- ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
-
- //
- // Determine the interrupt number based on the SSI port.
- //
- ulInt = (ulBase == SSI0_BASE) ? INT_SSI0 : INT_SSI1;
-
- //
- // Register the interrupt handler, returning an error if an error occurs.
- //
- IntRegister(ulInt, pfnHandler);
-
- //
- // Enable the synchronous serial interface interrupt.
- //
- IntEnable(ulInt);
-}
-
-//*****************************************************************************
-//
-//! Unregisters an interrupt handler for the synchronous serial interface.
-//!
-//! \param ulBase specifies the SSI module base address.
-//!
-//! This function will clear the handler to be called when a SSI
-//! interrupt occurs. This will also mask off the interrupt in the interrupt
-//! controller so that the interrupt handler no longer is called.
-//!
-//! \sa IntRegister() for important information about registering interrupt
-//! handlers.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SSIIntUnregister(unsigned long ulBase)
-{
- unsigned long ulInt;
-
- //
- // Check the arguments.
- //
- ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
-
- //
- // Determine the interrupt number based on the SSI port.
- //
- ulInt = (ulBase == SSI0_BASE) ? INT_SSI0 : INT_SSI1;
-
- //
- // Disable the interrupt.
- //
- IntDisable(ulInt);
-
- //
- // Unregister the interrupt handler.
- //
- IntUnregister(ulInt);
-}
-
-//*****************************************************************************
-//
-//! Enables individual SSI interrupt sources.
-//!
-//! \param ulBase specifies the SSI module base address.
-//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled.
-//!
-//! Enables the indicated SSI interrupt sources. Only the sources that are
-//! enabled can be reflected to the processor interrupt; disabled sources have
-//! no effect on the processor. The \e ulIntFlags parameter can be any of the
-//! \b SSI_TXFF, \b SSI_RXFF, \b SSI_RXTO, or \b SSI_RXOR values.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
-{
- //
- // Check the arguments.
- //
- ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
-
- //
- // Enable the specified interrupts.
- //
- HWREG(ulBase + SSI_O_IM) |= ulIntFlags;
-}
-
-//*****************************************************************************
-//
-//! Disables individual SSI interrupt sources.
-//!
-//! \param ulBase specifies the SSI module base address.
-//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled.
-//!
-//! Disables the indicated SSI interrupt sources. The \e ulIntFlags parameter
-//! can be any of the \b SSI_TXFF, \b SSI_RXFF, \b SSI_RXTO, or \b SSI_RXOR
-//! values.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
-{
- //
- // Check the arguments.
- //
- ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
-
- //
- // Disable the specified interrupts.
- //
- HWREG(ulBase + SSI_O_IM) &= ~(ulIntFlags);
-}
-
-//*****************************************************************************
-//
-//! Gets the current interrupt status.
-//!
-//! \param ulBase specifies the SSI module base address.
-//! \param bMasked is \b false if the raw interrupt status is required and
-//! \b true if the masked interrupt status is required.
-//!
-//! This returns the interrupt status for the SSI module. Either the raw
-//! interrupt status or the status of interrupts that are allowed to reflect to
-//! the processor can be returned.
-//!
-//! \return The current interrupt status, enumerated as a bit field of
-//! \b SSI_TXFF, \b SSI_RXFF, \b SSI_RXTO, and \b SSI_RXOR.
-//
-//*****************************************************************************
-unsigned long
-SSIIntStatus(unsigned long ulBase, tBoolean bMasked)
-{
- //
- // Check the arguments.
- //
- ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
-
- //
- // Return either the interrupt status or the raw interrupt status as
- // requested.
- //
- if(bMasked)
- {
- return(HWREG(ulBase + SSI_O_MIS));
- }
- else
- {
- return(HWREG(ulBase + SSI_O_RIS));
- }
-}
-
-//*****************************************************************************
-//
-//! Clears SSI interrupt sources.
-//!
-//! \param ulBase specifies the SSI module base address.
-//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
-//!
-//! The specified SSI interrupt sources are cleared, so that
-//! they no longer assert. This must be done in the interrupt handler to
-//! keep it from being called again immediately upon exit.
-//! The \e ulIntFlags parameter can consist of either or both the \b SSI_RXTO
-//! and \b SSI_RXOR values.
-//!
-//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
-//! several clock cycles before the interrupt source is actually cleared.
-//! Therefore, it is recommended that the interrupt source be cleared early in
-//! the interrupt handler (as opposed to the very last action) to avoid
-//! returning from the interrupt handler before the interrupt source is
-//! actually cleared. Failure to do so may result in the interrupt handler
-//! being immediately reentered (since NVIC still sees the interrupt source
-//! asserted).
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags)
-{
- //
- // Check the arguments.
- //
- ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
-
- //
- // Clear the requested interrupt sources.
- //
- HWREG(ulBase + SSI_O_ICR) = ulIntFlags;
-}
-
-//*****************************************************************************
-//
-//! Puts a data element into the SSI transmit FIFO.
-//!
-//! \param ulBase specifies the SSI module base address.
-//! \param ulData data to be transmitted over the SSI interface.
-//!
-//! This function will place the supplied data into the transmit FIFO of
-//! the specified SSI module.
-//!
-//! \note The upper 32 - N bits of the \e ulData will be discarded by the
-//! hardware, where N is the data width as configured by SSIConfigSetExpClk().
-//! For example, if the interface is configured for 8-bit data width, the upper
-//! 24 bits of \e ulData will be discarded.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SSIDataPut(unsigned long ulBase, unsigned long ulData)
-{
- //
- // Check the arguments.
- //
- ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
- ASSERT((ulData & (0xfffffffe << (HWREG(ulBase + SSI_O_CR0) &
- SSI_CR0_DSS_M))) == 0);
-
- //
- // Wait until there is space.
- //
- while(!(HWREG(ulBase + SSI_O_SR) & SSI_SR_TNF))
- {
- }
-
- //
- // Write the data to the SSI.
- //
- HWREG(ulBase + SSI_O_DR) = ulData;
-}
-
-//*****************************************************************************
-//
-//! Puts a data element into the SSI transmit FIFO.
-//!
-//! \param ulBase specifies the SSI module base address.
-//! \param ulData data to be transmitted over the SSI interface.
-//!
-//! This function will place the supplied data into the transmit FIFO of
-//! the specified SSI module. If there is no space in the FIFO, then this
-//! function will return a zero.
-//!
-//! This function replaces the original SSIDataNonBlockingPut() API and
-//! performs the same actions. A macro is provided in <tt>ssi.h</tt> to map
-//! the original API to this API.
-//!
-//! \note The upper 32 - N bits of the \e ulData will be discarded by the
-//! hardware, where N is the data width as configured by SSIConfigSetExpClk().
-//! For example, if the interface is configured for 8-bit data width, the upper
-//! 24 bits of \e ulData will be discarded.
-//!
-//! \return Returns the number of elements written to the SSI transmit FIFO.
-//
-//*****************************************************************************
-long
-SSIDataPutNonBlocking(unsigned long ulBase, unsigned long ulData)
-{
- //
- // Check the arguments.
- //
- ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
- ASSERT((ulData & (0xfffffffe << (HWREG(ulBase + SSI_O_CR0) &
- SSI_CR0_DSS_M))) == 0);
-
- //
- // Check for space to write.
- //
- if(HWREG(ulBase + SSI_O_SR) & SSI_SR_TNF)
- {
- HWREG(ulBase + SSI_O_DR) = ulData;
- return(1);
- }
- else
- {
- return(0);
- }
-}
-
-//*****************************************************************************
-//
-//! Gets a data element from the SSI receive FIFO.
-//!
-//! \param ulBase specifies the SSI module base address.
-//! \param pulData pointer to a storage location for data that was received
-//! over the SSI interface.
-//!
-//! This function will get received data from the receive FIFO of the specified
-//! SSI module, and place that data into the location specified by the
-//! \e pulData parameter.
-//!
-//! \note Only the lower N bits of the value written to \e pulData will contain
-//! valid data, where N is the data width as configured by
-//! SSIConfigSetExpClk(). For example, if the interface is configured for
-//! 8-bit data width, only the lower 8 bits of the value written to \e pulData
-//! will contain valid data.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SSIDataGet(unsigned long ulBase, unsigned long *pulData)
-{
- //
- // Check the arguments.
- //
- ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
-
- //
- // Wait until there is data to be read.
- //
- while(!(HWREG(ulBase + SSI_O_SR) & SSI_SR_RNE))
- {
- }
-
- //
- // Read data from SSI.
- //
- *pulData = HWREG(ulBase + SSI_O_DR);
-}
-
-//*****************************************************************************
-//
-//! Gets a data element from the SSI receive FIFO.
-//!
-//! \param ulBase specifies the SSI module base address.
-//! \param pulData pointer to a storage location for data that was received
-//! over the SSI interface.
-//!
-//! This function will get received data from the receive FIFO of
-//! the specified SSI module, and place that data into the location specified
-//! by the \e ulData parameter. If there is no data in the FIFO, then this
-//! function will return a zero.
-//!
-//! This function replaces the original SSIDataNonBlockingGet() API and
-//! performs the same actions. A macro is provided in <tt>ssi.h</tt> to map
-//! the original API to this API.
-//!
-//! \note Only the lower N bits of the value written to \e pulData will contain
-//! valid data, where N is the data width as configured by
-//! SSIConfigSetExpClk(). For example, if the interface is configured for
-//! 8-bit data width, only the lower 8 bits of the value written to \e pulData
-//! will contain valid data.
-//!
-//! \return Returns the number of elements read from the SSI receive FIFO.
-//
-//*****************************************************************************
-long
-SSIDataGetNonBlocking(unsigned long ulBase, unsigned long *pulData)
-{
- //
- // Check the arguments.
- //
- ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
-
- //
- // Check for data to read.
- //
- if(HWREG(ulBase + SSI_O_SR) & SSI_SR_RNE)
- {
- *pulData = HWREG(ulBase + SSI_O_DR);
- return(1);
- }
- else
- {
- return(0);
- }
-}
-
-//*****************************************************************************
-//
-//! Enable SSI DMA operation.
-//!
-//! \param ulBase is the base address of the SSI port.
-//! \param ulDMAFlags is a bit mask of the DMA features to enable.
-//!
-//! The specified SSI DMA features are enabled. The SSI can be
-//! configured to use DMA for transmit and/or receive data transfers.
-//! The \e ulDMAFlags parameter is the logical OR of any of the following
-//! values:
-//!
-//! - SSI_DMA_RX - enable DMA for receive
-//! - SSI_DMA_TX - enable DMA for transmit
-//!
-//! \note The uDMA controller must also be set up before DMA can be used
-//! with the SSI.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SSIDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags)
-{
- //
- // Check the arguments.
- //
- ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
-
- //
- // Set the requested bits in the UART DMA control register.
- //
- HWREG(ulBase + SSI_O_DMACTL) |= ulDMAFlags;
-}
-
-//*****************************************************************************
-//
-//! Disable SSI DMA operation.
-//!
-//! \param ulBase is the base address of the SSI port.
-//! \param ulDMAFlags is a bit mask of the DMA features to disable.
-//!
-//! This function is used to disable SSI DMA features that were enabled
-//! by SSIDMAEnable(). The specified SSI DMA features are disabled. The
-//! \e ulDMAFlags parameter is the logical OR of any of the following values:
-//!
-//! - SSI_DMA_RX - disable DMA for receive
-//! - SSI_DMA_TX - disable DMA for transmit
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SSIDMADisable(unsigned long ulBase, unsigned long ulDMAFlags)
-{
- //
- // Check the arguments.
- //
- ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
-
- //
- // Clear the requested bits in the UART DMA control register.
- //
- HWREG(ulBase + SSI_O_DMACTL) &= ~ulDMAFlags;
-}
-
-//*****************************************************************************
-//
-// Close the Doxygen group.
-//! @}
-//
-//*****************************************************************************
+//*****************************************************************************
+//
+// ssi.c - Driver for Synchronous Serial Interface.
+//
+// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup ssi_api
+//! @{
+//
+//*****************************************************************************
+
+#include "hw_ints.h"
+#include "hw_memmap.h"
+#include "hw_ssi.h"
+#include "hw_types.h"
+#include "debug.h"
+#include "interrupt.h"
+#include "ssi.h"
+
+//*****************************************************************************
+//
+//! Configures the synchronous serial interface.
+//!
+//! \param ulBase specifies the SSI module base address.
+//! \param ulSSIClk is the rate of the clock supplied to the SSI module.
+//! \param ulProtocol specifies the data transfer protocol.
+//! \param ulMode specifies the mode of operation.
+//! \param ulBitRate specifies the clock rate.
+//! \param ulDataWidth specifies number of bits transferred per frame.
+//!
+//! This function configures the synchronous serial interface. It sets
+//! the SSI protocol, mode of operation, bit rate, and data width.
+//!
+//! The \e ulProtocol parameter defines the data frame format. The
+//! \e ulProtocol parameter can be one of the following values:
+//! \b SSI_FRF_MOTO_MODE_0, \b SSI_FRF_MOTO_MODE_1, \b SSI_FRF_MOTO_MODE_2,
+//! \b SSI_FRF_MOTO_MODE_3, \b SSI_FRF_TI, or \b SSI_FRF_NMW. The Motorola
+//! frame formats imply the following polarity and phase configurations:
+//!
+//! <pre>
+//! Polarity Phase Mode
+//! 0 0 SSI_FRF_MOTO_MODE_0
+//! 0 1 SSI_FRF_MOTO_MODE_1
+//! 1 0 SSI_FRF_MOTO_MODE_2
+//! 1 1 SSI_FRF_MOTO_MODE_3
+//! </pre>
+//!
+//! The \e ulMode parameter defines the operating mode of the SSI module. The
+//! SSI module can operate as a master or slave; if a slave, the SSI can be
+//! configured to disable output on its serial output line. The \e ulMode
+//! parameter can be one of the following values: \b SSI_MODE_MASTER,
+//! \b SSI_MODE_SLAVE, or \b SSI_MODE_SLAVE_OD.
+//!
+//! The \e ulBitRate parameter defines the bit rate for the SSI. This bit rate
+//! must satisfy the following clock ratio criteria:
+//!
+//! - FSSI >= 2 * bit rate (master mode)
+//! - FSSI >= 12 * bit rate (slave modes)
+//!
+//! where FSSI is the frequency of the clock supplied to the SSI module.
+//!
+//! The \e ulDataWidth parameter defines the width of the data transfers, and
+//! can be a value between 4 and 16, inclusive.
+//!
+//! The peripheral clock will be the same as the processor clock. This will be
+//! the value returned by SysCtlClockGet(), or it can be explicitly hard coded
+//! if it is constant and known (to save the code/execution overhead of a call
+//! to SysCtlClockGet()).
+//!
+//! This function replaces the original SSIConfig() API and performs the same
+//! actions. A macro is provided in <tt>ssi.h</tt> to map the original API to
+//! this API.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIConfigSetExpClk(unsigned long ulBase, unsigned long ulSSIClk,
+ unsigned long ulProtocol, unsigned long ulMode,
+ unsigned long ulBitRate, unsigned long ulDataWidth)
+{
+ unsigned long ulMaxBitRate;
+ unsigned long ulRegVal;
+ unsigned long ulPreDiv;
+ unsigned long ulSCR;
+ unsigned long ulSPH_SPO;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
+ ASSERT((ulProtocol == SSI_FRF_MOTO_MODE_0) ||
+ (ulProtocol == SSI_FRF_MOTO_MODE_1) ||
+ (ulProtocol == SSI_FRF_MOTO_MODE_2) ||
+ (ulProtocol == SSI_FRF_MOTO_MODE_3) ||
+ (ulProtocol == SSI_FRF_TI) ||
+ (ulProtocol == SSI_FRF_NMW));
+ ASSERT((ulMode == SSI_MODE_MASTER) ||
+ (ulMode == SSI_MODE_SLAVE) ||
+ (ulMode == SSI_MODE_SLAVE_OD));
+ ASSERT(((ulMode == SSI_MODE_MASTER) && (ulBitRate <= (ulSSIClk / 2))) ||
+ ((ulMode != SSI_MODE_MASTER) && (ulBitRate <= (ulSSIClk / 12))));
+ ASSERT((ulSSIClk / ulBitRate) <= (254 * 256));
+ ASSERT((ulDataWidth >= 4) && (ulDataWidth <= 16));
+
+ //
+ // Set the mode.
+ //
+ ulRegVal = (ulMode == SSI_MODE_SLAVE_OD) ? SSI_CR1_SOD : 0;
+ ulRegVal |= (ulMode == SSI_MODE_MASTER) ? 0 : SSI_CR1_MS;
+ HWREG(ulBase + SSI_O_CR1) = ulRegVal;
+
+ //
+ // Set the clock predivider.
+ //
+ ulMaxBitRate = ulSSIClk / ulBitRate;
+ ulPreDiv = 0;
+ do
+ {
+ ulPreDiv += 2;
+ ulSCR = (ulMaxBitRate / ulPreDiv) - 1;
+ }
+ while(ulSCR > 255);
+ HWREG(ulBase + SSI_O_CPSR) = ulPreDiv;
+
+ //
+ // Set protocol and clock rate.
+ //
+ ulSPH_SPO = ulProtocol << 6;
+ ulProtocol &= SSI_CR0_FRF_M;
+ ulRegVal = (ulSCR << 8) | ulSPH_SPO | ulProtocol | (ulDataWidth - 1);
+ HWREG(ulBase + SSI_O_CR0) = ulRegVal;
+}
+
+//*****************************************************************************
+//
+//! Enables the synchronous serial interface.
+//!
+//! \param ulBase specifies the SSI module base address.
+//!
+//! This will enable operation of the synchronous serial interface. It must be
+//! configured before it is enabled.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIEnable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
+
+ //
+ // Read-modify-write the enable bit.
+ //
+ HWREG(ulBase + SSI_O_CR1) |= SSI_CR1_SSE;
+}
+
+//*****************************************************************************
+//
+//! Disables the synchronous serial interface.
+//!
+//! \param ulBase specifies the SSI module base address.
+//!
+//! This will disable operation of the synchronous serial interface.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIDisable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
+
+ //
+ // Read-modify-write the enable bit.
+ //
+ HWREG(ulBase + SSI_O_CR1) &= ~(SSI_CR1_SSE);
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the synchronous serial interface.
+//!
+//! \param ulBase specifies the SSI module base address.
+//! \param pfnHandler is a pointer to the function to be called when the
+//! synchronous serial interface interrupt occurs.
+//!
+//! This sets the handler to be called when an SSI interrupt
+//! occurs. This will enable the global interrupt in the interrupt controller;
+//! specific SSI interrupts must be enabled via SSIIntEnable(). If necessary,
+//! it is the interrupt handler's responsibility to clear the interrupt source
+//! via SSIIntClear().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
+{
+ unsigned long ulInt;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
+
+ //
+ // Determine the interrupt number based on the SSI port.
+ //
+ ulInt = (ulBase == SSI0_BASE) ? INT_SSI0 : INT_SSI1;
+
+ //
+ // Register the interrupt handler, returning an error if an error occurs.
+ //
+ IntRegister(ulInt, pfnHandler);
+
+ //
+ // Enable the synchronous serial interface interrupt.
+ //
+ IntEnable(ulInt);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for the synchronous serial interface.
+//!
+//! \param ulBase specifies the SSI module base address.
+//!
+//! This function will clear the handler to be called when a SSI
+//! interrupt occurs. This will also mask off the interrupt in the interrupt
+//! controller so that the interrupt handler no longer is called.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIIntUnregister(unsigned long ulBase)
+{
+ unsigned long ulInt;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
+
+ //
+ // Determine the interrupt number based on the SSI port.
+ //
+ ulInt = (ulBase == SSI0_BASE) ? INT_SSI0 : INT_SSI1;
+
+ //
+ // Disable the interrupt.
+ //
+ IntDisable(ulInt);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(ulInt);
+}
+
+//*****************************************************************************
+//
+//! Enables individual SSI interrupt sources.
+//!
+//! \param ulBase specifies the SSI module base address.
+//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled.
+//!
+//! Enables the indicated SSI interrupt sources. Only the sources that are
+//! enabled can be reflected to the processor interrupt; disabled sources have
+//! no effect on the processor. The \e ulIntFlags parameter can be any of the
+//! \b SSI_TXFF, \b SSI_RXFF, \b SSI_RXTO, or \b SSI_RXOR values.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
+
+ //
+ // Enable the specified interrupts.
+ //
+ HWREG(ulBase + SSI_O_IM) |= ulIntFlags;
+}
+
+//*****************************************************************************
+//
+//! Disables individual SSI interrupt sources.
+//!
+//! \param ulBase specifies the SSI module base address.
+//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled.
+//!
+//! Disables the indicated SSI interrupt sources. The \e ulIntFlags parameter
+//! can be any of the \b SSI_TXFF, \b SSI_RXFF, \b SSI_RXTO, or \b SSI_RXOR
+//! values.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
+
+ //
+ // Disable the specified interrupts.
+ //
+ HWREG(ulBase + SSI_O_IM) &= ~(ulIntFlags);
+}
+
+//*****************************************************************************
+//
+//! Gets the current interrupt status.
+//!
+//! \param ulBase specifies the SSI module base address.
+//! \param bMasked is \b false if the raw interrupt status is required and
+//! \b true if the masked interrupt status is required.
+//!
+//! This returns the interrupt status for the SSI module. Either the raw
+//! interrupt status or the status of interrupts that are allowed to reflect to
+//! the processor can be returned.
+//!
+//! \return The current interrupt status, enumerated as a bit field of
+//! \b SSI_TXFF, \b SSI_RXFF, \b SSI_RXTO, and \b SSI_RXOR.
+//
+//*****************************************************************************
+unsigned long
+SSIIntStatus(unsigned long ulBase, tBoolean bMasked)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
+
+ //
+ // Return either the interrupt status or the raw interrupt status as
+ // requested.
+ //
+ if(bMasked)
+ {
+ return(HWREG(ulBase + SSI_O_MIS));
+ }
+ else
+ {
+ return(HWREG(ulBase + SSI_O_RIS));
+ }
+}
+
+//*****************************************************************************
+//
+//! Clears SSI interrupt sources.
+//!
+//! \param ulBase specifies the SSI module base address.
+//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
+//!
+//! The specified SSI interrupt sources are cleared, so that
+//! they no longer assert. This must be done in the interrupt handler to
+//! keep it from being called again immediately upon exit.
+//! The \e ulIntFlags parameter can consist of either or both the \b SSI_RXTO
+//! and \b SSI_RXOR values.
+//!
+//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
+//! several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared. Failure to do so may result in the interrupt handler
+//! being immediately reentered (since NVIC still sees the interrupt source
+//! asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
+
+ //
+ // Clear the requested interrupt sources.
+ //
+ HWREG(ulBase + SSI_O_ICR) = ulIntFlags;
+}
+
+//*****************************************************************************
+//
+//! Puts a data element into the SSI transmit FIFO.
+//!
+//! \param ulBase specifies the SSI module base address.
+//! \param ulData data to be transmitted over the SSI interface.
+//!
+//! This function will place the supplied data into the transmit FIFO of
+//! the specified SSI module.
+//!
+//! \note The upper 32 - N bits of the \e ulData will be discarded by the
+//! hardware, where N is the data width as configured by SSIConfigSetExpClk().
+//! For example, if the interface is configured for 8-bit data width, the upper
+//! 24 bits of \e ulData will be discarded.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIDataPut(unsigned long ulBase, unsigned long ulData)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
+ ASSERT((ulData & (0xfffffffe << (HWREG(ulBase + SSI_O_CR0) &
+ SSI_CR0_DSS_M))) == 0);
+
+ //
+ // Wait until there is space.
+ //
+ while(!(HWREG(ulBase + SSI_O_SR) & SSI_SR_TNF))
+ {
+ }
+
+ //
+ // Write the data to the SSI.
+ //
+ HWREG(ulBase + SSI_O_DR) = ulData;
+}
+
+//*****************************************************************************
+//
+//! Puts a data element into the SSI transmit FIFO.
+//!
+//! \param ulBase specifies the SSI module base address.
+//! \param ulData data to be transmitted over the SSI interface.
+//!
+//! This function will place the supplied data into the transmit FIFO of
+//! the specified SSI module. If there is no space in the FIFO, then this
+//! function will return a zero.
+//!
+//! This function replaces the original SSIDataNonBlockingPut() API and
+//! performs the same actions. A macro is provided in <tt>ssi.h</tt> to map
+//! the original API to this API.
+//!
+//! \note The upper 32 - N bits of the \e ulData will be discarded by the
+//! hardware, where N is the data width as configured by SSIConfigSetExpClk().
+//! For example, if the interface is configured for 8-bit data width, the upper
+//! 24 bits of \e ulData will be discarded.
+//!
+//! \return Returns the number of elements written to the SSI transmit FIFO.
+//
+//*****************************************************************************
+long
+SSIDataPutNonBlocking(unsigned long ulBase, unsigned long ulData)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
+ ASSERT((ulData & (0xfffffffe << (HWREG(ulBase + SSI_O_CR0) &
+ SSI_CR0_DSS_M))) == 0);
+
+ //
+ // Check for space to write.
+ //
+ if(HWREG(ulBase + SSI_O_SR) & SSI_SR_TNF)
+ {
+ HWREG(ulBase + SSI_O_DR) = ulData;
+ return(1);
+ }
+ else
+ {
+ return(0);
+ }
+}
+
+//*****************************************************************************
+//
+//! Gets a data element from the SSI receive FIFO.
+//!
+//! \param ulBase specifies the SSI module base address.
+//! \param pulData pointer to a storage location for data that was received
+//! over the SSI interface.
+//!
+//! This function will get received data from the receive FIFO of the specified
+//! SSI module, and place that data into the location specified by the
+//! \e pulData parameter.
+//!
+//! \note Only the lower N bits of the value written to \e pulData will contain
+//! valid data, where N is the data width as configured by
+//! SSIConfigSetExpClk(). For example, if the interface is configured for
+//! 8-bit data width, only the lower 8 bits of the value written to \e pulData
+//! will contain valid data.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIDataGet(unsigned long ulBase, unsigned long *pulData)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
+
+ //
+ // Wait until there is data to be read.
+ //
+ while(!(HWREG(ulBase + SSI_O_SR) & SSI_SR_RNE))
+ {
+ }
+
+ //
+ // Read data from SSI.
+ //
+ *pulData = HWREG(ulBase + SSI_O_DR);
+}
+
+//*****************************************************************************
+//
+//! Gets a data element from the SSI receive FIFO.
+//!
+//! \param ulBase specifies the SSI module base address.
+//! \param pulData pointer to a storage location for data that was received
+//! over the SSI interface.
+//!
+//! This function will get received data from the receive FIFO of
+//! the specified SSI module, and place that data into the location specified
+//! by the \e ulData parameter. If there is no data in the FIFO, then this
+//! function will return a zero.
+//!
+//! This function replaces the original SSIDataNonBlockingGet() API and
+//! performs the same actions. A macro is provided in <tt>ssi.h</tt> to map
+//! the original API to this API.
+//!
+//! \note Only the lower N bits of the value written to \e pulData will contain
+//! valid data, where N is the data width as configured by
+//! SSIConfigSetExpClk(). For example, if the interface is configured for
+//! 8-bit data width, only the lower 8 bits of the value written to \e pulData
+//! will contain valid data.
+//!
+//! \return Returns the number of elements read from the SSI receive FIFO.
+//
+//*****************************************************************************
+long
+SSIDataGetNonBlocking(unsigned long ulBase, unsigned long *pulData)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
+
+ //
+ // Check for data to read.
+ //
+ if(HWREG(ulBase + SSI_O_SR) & SSI_SR_RNE)
+ {
+ *pulData = HWREG(ulBase + SSI_O_DR);
+ return(1);
+ }
+ else
+ {
+ return(0);
+ }
+}
+
+//*****************************************************************************
+//
+//! Enable SSI DMA operation.
+//!
+//! \param ulBase is the base address of the SSI port.
+//! \param ulDMAFlags is a bit mask of the DMA features to enable.
+//!
+//! The specified SSI DMA features are enabled. The SSI can be
+//! configured to use DMA for transmit and/or receive data transfers.
+//! The \e ulDMAFlags parameter is the logical OR of any of the following
+//! values:
+//!
+//! - SSI_DMA_RX - enable DMA for receive
+//! - SSI_DMA_TX - enable DMA for transmit
+//!
+//! \note The uDMA controller must also be set up before DMA can be used
+//! with the SSI.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
+
+ //
+ // Set the requested bits in the UART DMA control register.
+ //
+ HWREG(ulBase + SSI_O_DMACTL) |= ulDMAFlags;
+}
+
+//*****************************************************************************
+//
+//! Disable SSI DMA operation.
+//!
+//! \param ulBase is the base address of the SSI port.
+//! \param ulDMAFlags is a bit mask of the DMA features to disable.
+//!
+//! This function is used to disable SSI DMA features that were enabled
+//! by SSIDMAEnable(). The specified SSI DMA features are disabled. The
+//! \e ulDMAFlags parameter is the logical OR of any of the following values:
+//!
+//! - SSI_DMA_RX - disable DMA for receive
+//! - SSI_DMA_TX - disable DMA for transmit
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIDMADisable(unsigned long ulBase, unsigned long ulDMAFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
+
+ //
+ // Clear the requested bits in the UART DMA control register.
+ //
+ HWREG(ulBase + SSI_O_DMACTL) &= ~ulDMAFlags;
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
Property changes on: branches/eagle_mmc/src/platform/lm3s/ssi.c
___________________________________________________________________
Name: svn:executable
+ *
Modified: branches/eagle_mmc/src/platform/lm3s/ssi.h
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/ssi.h 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lm3s/ssi.h 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,127 +1,127 @@
-//*****************************************************************************
-//
-// ssi.h - Prototypes for the Synchronous Serial Interface Driver.
-//
-// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
-// Software License Agreement
-//
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
-//
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws. All rights are reserved. You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program. Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
-//
-// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-//
-// This is part of revision 3740 of the Stellaris Peripheral Driver Library.
-//
-//*****************************************************************************
-
-#ifndef __SSI_H__
-#define __SSI_H__
-
-//*****************************************************************************
-//
-// If building with a C++ compiler, make all of the definitions in this header
-// have a C binding.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-//*****************************************************************************
-//
-// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear
-// as the ulIntFlags parameter, and returned by SSIIntStatus.
-//
-//*****************************************************************************
-#define SSI_TXFF 0x00000008 // TX FIFO half empty or less
-#define SSI_RXFF 0x00000004 // RX FIFO half full or less
-#define SSI_RXTO 0x00000002 // RX timeout
-#define SSI_RXOR 0x00000001 // RX overrun
-
-//*****************************************************************************
-//
-// Values that can be passed to SSIConfigSetExpClk.
-//
-//*****************************************************************************
-#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0
-#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1
-#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0
-#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1
-#define SSI_FRF_TI 0x00000010 // TI frame format
-#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format
-
-#define SSI_MODE_MASTER 0x00000000 // SSI master
-#define SSI_MODE_SLAVE 0x00000001 // SSI slave
-#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled
-
-//*****************************************************************************
-//
-// Values that can be passed to SSIDMAEnable() and SSIDMADisable().
-//
-//*****************************************************************************
-#define SSI_DMA_TX 0x00000002 // Enable DMA for transmit
-#define SSI_DMA_RX 0x00000001 // Enable DMA for receive
-
-//*****************************************************************************
-//
-// Prototypes for the APIs.
-//
-//*****************************************************************************
-extern void SSIConfigSetExpClk(unsigned long ulBase, unsigned long ulSSIClk,
- unsigned long ulProtocol, unsigned long ulMode,
- unsigned long ulBitRate,
- unsigned long ulDataWidth);
-extern void SSIDataGet(unsigned long ulBase, unsigned long *pulData);
-extern long SSIDataGetNonBlocking(unsigned long ulBase,
- unsigned long *pulData);
-extern void SSIDataPut(unsigned long ulBase, unsigned long ulData);
-extern long SSIDataPutNonBlocking(unsigned long ulBase, unsigned long ulData);
-extern void SSIDisable(unsigned long ulBase);
-extern void SSIEnable(unsigned long ulBase);
-extern void SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags);
-extern void SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
-extern void SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
-extern void SSIIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
-extern unsigned long SSIIntStatus(unsigned long ulBase, tBoolean bMasked);
-extern void SSIIntUnregister(unsigned long ulBase);
-extern void SSIDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags);
-extern void SSIDMADisable(unsigned long ulBase, unsigned long ulDMAFlags);
-
-//*****************************************************************************
-//
-// Several SSI APIs have been renamed, with the original function name being
-// deprecated. These defines provide backward compatibility.
-//
-//*****************************************************************************
-#ifndef DEPRECATED
-#include "sysctl.h"
-#define SSIConfig(a, b, c, d, e) \
- SSIConfigSetExpClk(a, SysCtlClockGet(), b, c, d, e)
-#define SSIDataNonBlockingGet(a, b) \
- SSIDataGetNonBlocking(a, b)
-#define SSIDataNonBlockingPut(a, b) \
- SSIDataPutNonBlocking(a, b)
-#endif
-
-//*****************************************************************************
-//
-// Mark the end of the C bindings section for C++ compilers.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-}
-#endif
-
-#endif // __SSI_H__
+//*****************************************************************************
+//
+// ssi.h - Prototypes for the Synchronous Serial Interface Driver.
+//
+// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __SSI_H__
+#define __SSI_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear
+// as the ulIntFlags parameter, and returned by SSIIntStatus.
+//
+//*****************************************************************************
+#define SSI_TXFF 0x00000008 // TX FIFO half empty or less
+#define SSI_RXFF 0x00000004 // RX FIFO half full or less
+#define SSI_RXTO 0x00000002 // RX timeout
+#define SSI_RXOR 0x00000001 // RX overrun
+
+//*****************************************************************************
+//
+// Values that can be passed to SSIConfigSetExpClk.
+//
+//*****************************************************************************
+#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0
+#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1
+#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0
+#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1
+#define SSI_FRF_TI 0x00000010 // TI frame format
+#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format
+
+#define SSI_MODE_MASTER 0x00000000 // SSI master
+#define SSI_MODE_SLAVE 0x00000001 // SSI slave
+#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled
+
+//*****************************************************************************
+//
+// Values that can be passed to SSIDMAEnable() and SSIDMADisable().
+//
+//*****************************************************************************
+#define SSI_DMA_TX 0x00000002 // Enable DMA for transmit
+#define SSI_DMA_RX 0x00000001 // Enable DMA for receive
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern void SSIConfigSetExpClk(unsigned long ulBase, unsigned long ulSSIClk,
+ unsigned long ulProtocol, unsigned long ulMode,
+ unsigned long ulBitRate,
+ unsigned long ulDataWidth);
+extern void SSIDataGet(unsigned long ulBase, unsigned long *pulData);
+extern long SSIDataGetNonBlocking(unsigned long ulBase,
+ unsigned long *pulData);
+extern void SSIDataPut(unsigned long ulBase, unsigned long ulData);
+extern long SSIDataPutNonBlocking(unsigned long ulBase, unsigned long ulData);
+extern void SSIDisable(unsigned long ulBase);
+extern void SSIEnable(unsigned long ulBase);
+extern void SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags);
+extern void SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
+extern void SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
+extern void SSIIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
+extern unsigned long SSIIntStatus(unsigned long ulBase, tBoolean bMasked);
+extern void SSIIntUnregister(unsigned long ulBase);
+extern void SSIDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags);
+extern void SSIDMADisable(unsigned long ulBase, unsigned long ulDMAFlags);
+
+//*****************************************************************************
+//
+// Several SSI APIs have been renamed, with the original function name being
+// deprecated. These defines provide backward compatibility.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+#include "sysctl.h"
+#define SSIConfig(a, b, c, d, e) \
+ SSIConfigSetExpClk(a, SysCtlClockGet(), b, c, d, e)
+#define SSIDataNonBlockingGet(a, b) \
+ SSIDataGetNonBlocking(a, b)
+#define SSIDataNonBlockingPut(a, b) \
+ SSIDataPutNonBlocking(a, b)
+#endif
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __SSI_H__
Property changes on: branches/eagle_mmc/src/platform/lm3s/ssi.h
___________________________________________________________________
Name: svn:executable
+ *
Modified: branches/eagle_mmc/src/platform/lm3s/startup_gcc.c
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/startup_gcc.c 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lm3s/startup_gcc.c 2009-11-06 02:08:32 UTC (rev 526)
@@ -61,8 +61,7 @@
__attribute__ ((section(".isr_vector")))
void (* const g_pfnVectors[])(void) =
{
- //(void (*)(void))((unsigned long)pulStack + sizeof(pulStack)),
- (void (*) (void))(SRAM_BASE + 64*1024),
+ (void (*) (void))( SRAM_BASE + SRAM_SIZE ),
// The initial stack pointer
ResetISR, // The reset handler
NmiSR, // The NMI handler
@@ -196,7 +195,7 @@
#include "gpio.h"
#include "interrupt.h"
#include "sysctl.h"
-#include "usart.h"
+#include "uart.h"
//*****************************************************************************
//
Modified: branches/eagle_mmc/src/platform/lm3s/sysctl.c
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/sysctl.c 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lm3s/sysctl.c 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,2125 +1,2339 @@
-//*****************************************************************************
-//
-// sysctl.c - Driver for the system controller.
-//
-// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
-// Software License Agreement
-//
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
-//
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws. All rights are reserved. You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program. Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
-//
-// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-//
-// This is part of revision 3740 of the Stellaris Peripheral Driver Library.
-//
-//*****************************************************************************
-
-//*****************************************************************************
-//
-//! \addtogroup sysctl_api
-//! @{
-//
-//*****************************************************************************
-
-#include "hw_ints.h"
-#include "hw_memmap.h"
-#include "hw_nvic.h"
-#include "hw_sysctl.h"
-#include "hw_types.h"
-#include "cpu.h"
-#include "debug.h"
-#include "interrupt.h"
-#include "sysctl.h"
-
-//*****************************************************************************
-//
-// This macro extracts the array index out of the peripheral number.
-//
-//*****************************************************************************
-#define SYSCTL_PERIPH_INDEX(a) (((a) >> 28) & 0xf)
-
-//*****************************************************************************
-//
-// This macro constructs the peripheral bit mask from the peripheral number.
-//
-//*****************************************************************************
-#define SYSCTL_PERIPH_MASK(a) (((a) & 0xffff) << (((a) & 0x001f0000) >> 16))
-
-//*****************************************************************************
-//
-// An array that maps the "peripheral set" number (which is stored in the upper
-// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL DC? register that
-// contains the peripheral present bit for that peripheral.
-//
-//*****************************************************************************
-static const unsigned long g_pulDCRegs[] =
-{
- SYSCTL_DC1,
- SYSCTL_DC2,
- SYSCTL_DC4,
- SYSCTL_DC1
-};
-
-//*****************************************************************************
-//
-// An array that maps the "peripheral set" number (which is stored in the upper
-// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL_SRCR? register that
-// controls the software reset for that peripheral.
-//
-//*****************************************************************************
-static const unsigned long g_pulSRCRRegs[] =
-{
- SYSCTL_SRCR0,
- SYSCTL_SRCR1,
- SYSCTL_SRCR2
-};
-
-//*****************************************************************************
-//
-// An array that maps the "peripheral set" number (which is stored in the upper
-// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL_RCGC? register that
-// controls the run-mode enable for that peripheral.
-//
-//*****************************************************************************
-static const unsigned long g_pulRCGCRegs[] =
-{
- SYSCTL_RCGC0,
- SYSCTL_RCGC1,
- SYSCTL_RCGC2
-};
-
-//*****************************************************************************
-//
-// An array that maps the "peripheral set" number (which is stored in the upper
-// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL_SCGC? register that
-// controls the sleep-mode enable for that peripheral.
-//
-//*****************************************************************************
-static const unsigned long g_pulSCGCRegs[] =
-{
- SYSCTL_SCGC0,
- SYSCTL_SCGC1,
- SYSCTL_SCGC2
-};
-
-//*****************************************************************************
-//
-// An array that maps the "peripheral set" number (which is stored in the upper
-// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL_DCGC? register that
-// controls the deep-sleep-mode enable for that peripheral.
-//
-//*****************************************************************************
-static const unsigned long g_pulDCGCRegs[] =
-{
- SYSCTL_DCGC0,
- SYSCTL_DCGC1,
- SYSCTL_DCGC2
-};
-
-//*****************************************************************************
-//
-// An array that maps the crystal number in RCC to a frequency.
-//
-//*****************************************************************************
-static const unsigned long g_pulXtals[] =
-{
- 1000000,
- 1843200,
- 2000000,
- 2457600,
- 3579545,
- 3686400,
- 4000000,
- 4096000,
- 4915200,
- 5000000,
- 5120000,
- 6000000,
- 6144000,
- 7372800,
- 8000000,
- 8192000,
- 10000000,
- 12000000,
- 12288000,
- 13560000,
- 14318180,
- 16000000,
- 16384000
-};
-
-//*****************************************************************************
-//
-//! \internal
-//! Checks a peripheral identifier.
-//!
-//! \param ulPeripheral is the peripheral identifier.
-//!
-//! This function determines if a peripheral identifier is valid.
-//!
-//! \return Returns \b true if the peripheral identifier is valid and \b false
-//! otherwise.
-//
-//*****************************************************************************
-#ifdef DEBUG
-static tBoolean
-SysCtlPeripheralValid(unsigned long ulPeripheral)
-{
- return((ulPeripheral == SYSCTL_PERIPH_ADC) ||
- (ulPeripheral == SYSCTL_PERIPH_CAN0) ||
- (ulPeripheral == SYSCTL_PERIPH_CAN1) ||
- (ulPeripheral == SYSCTL_PERIPH_CAN2) ||
- (ulPeripheral == SYSCTL_PERIPH_COMP0) ||
- (ulPeripheral == SYSCTL_PERIPH_COMP1) ||
- (ulPeripheral == SYSCTL_PERIPH_COMP2) ||
- (ulPeripheral == SYSCTL_PERIPH_ETH) ||
- (ulPeripheral == SYSCTL_PERIPH_GPIOA) ||
- (ulPeripheral == SYSCTL_PERIPH_GPIOB) ||
- (ulPeripheral == SYSCTL_PERIPH_GPIOC) ||
- (ulPeripheral == SYSCTL_PERIPH_GPIOD) ||
- (ulPeripheral == SYSCTL_PERIPH_GPIOE) ||
- (ulPeripheral == SYSCTL_PERIPH_GPIOF) ||
- (ulPeripheral == SYSCTL_PERIPH_GPIOG) ||
- (ulPeripheral == SYSCTL_PERIPH_GPIOH) ||
- (ulPeripheral == SYSCTL_PERIPH_HIBERNATE) ||
- (ulPeripheral == SYSCTL_PERIPH_I2C0) ||
- (ulPeripheral == SYSCTL_PERIPH_I2C1) ||
- (ulPeripheral == SYSCTL_PERIPH_IEEE1588) ||
- (ulPeripheral == SYSCTL_PERIPH_MPU) ||
- (ulPeripheral == SYSCTL_PERIPH_PLL) ||
- (ulPeripheral == SYSCTL_PERIPH_PWM) ||
- (ulPeripheral == SYSCTL_PERIPH_QEI0) ||
- (ulPeripheral == SYSCTL_PERIPH_QEI1) ||
- (ulPeripheral == SYSCTL_PERIPH_SSI0) ||
- (ulPeripheral == SYSCTL_PERIPH_SSI1) ||
- (ulPeripheral == SYSCTL_PERIPH_TEMP) ||
- (ulPeripheral == SYSCTL_PERIPH_TIMER0) ||
- (ulPeripheral == SYSCTL_PERIPH_TIMER1) ||
- (ulPeripheral == SYSCTL_PERIPH_TIMER2) ||
- (ulPeripheral == SYSCTL_PERIPH_TIMER3) ||
- (ulPeripheral == SYSCTL_PERIPH_UART0) ||
- (ulPeripheral == SYSCTL_PERIPH_UART1) ||
- (ulPeripheral == SYSCTL_PERIPH_UART2) ||
- (ulPeripheral == SYSCTL_PERIPH_UDMA) ||
- (ulPeripheral == SYSCTL_PERIPH_USB0) ||
- (ulPeripheral == SYSCTL_PERIPH_WDOG));
-}
-#endif
-
-//*****************************************************************************
-//
-//! Gets the size of the SRAM.
-//!
-//! This function determines the size of the SRAM on the Stellaris device.
-//!
-//! \return The total number of bytes of SRAM.
-//
-//*****************************************************************************
-unsigned long
-SysCtlSRAMSizeGet(void)
-{
- //
- // Compute the size of the SRAM.
- //
- return(((HWREG(SYSCTL_DC0) & SYSCTL_DC0_SRAMSZ_M) >> 8) + 0x100);
-}
-
-//*****************************************************************************
-//
-//! Gets the size of the flash.
-//!
-//! This function determines the size of the flash on the Stellaris device.
-//!
-//! \return The total number of bytes of flash.
-//
-//*****************************************************************************
-unsigned long
-SysCtlFlashSizeGet(void)
-{
- //
- // Compute the size of the flash.
- //
- return(((HWREG(SYSCTL_DC0) & SYSCTL_DC0_FLASHSZ_M) << 11) + 0x800);
-}
-
-//*****************************************************************************
-//
-//! Determines if a pin is present.
-//!
-//! \param ulPin is the pin in question.
-//!
-//! Determines if a particular pin is present in the device. The PWM, analog
-//! comparators, ADC, and timers have a varying number of pins across members
-//! of the Stellaris family; this will determine which are present on this
-//! device.
-//!
-//! The \e ulPin argument must be only one of the following values:
-//! \b SYSCTL_PIN_PWM0, \b SYSCTL_PIN_PWM1, \b SYSCTL_PIN_PWM2,
-//! \b SYSCTL_PIN_PWM3, \b SYSCTL_PIN_PWM4, \b SYSCTL_PIN_PWM5,
-//! \b SYSCTL_PIN_C0MINUS, \b SYSCTL_PIN_C0PLUS, \b SYSCTL_PIN_C0O,
-//! \b SYSCTL_PIN_C1MINUS, \b SYSCTL_PIN_C1PLUS, \b SYSCTL_PIN_C1O,
-//! \b SYSCTL_PIN_C2MINUS, \b SYSCTL_PIN_C2PLUS, \b SYSCTL_PIN_C2O,
-//! \b SYSCTL_PIN_ADC0, \b SYSCTL_PIN_ADC1, \b SYSCTL_PIN_ADC2,
-//! \b SYSCTL_PIN_ADC3, \b SYSCTL_PIN_ADC4, \b SYSCTL_PIN_ADC5,
-//! \b SYSCTL_PIN_ADC6, \b SYSCTL_PIN_ADC7, \b SYSCTL_PIN_CCP0,
-//! \b SYSCTL_PIN_CCP1, \b SYSCTL_PIN_CCP2, \b SYSCTL_PIN_CCP3,
-//! \b SYSCTL_PIN_CCP4, \b SYSCTL_PIN_CCP5, \b SYSCTL_PIN_CCP6,
-//! \b SYSCTL_PIN_CCP7, \b SYSCTL_PIN_32KHZ, or \b SYSCTL_PIN_MC_FAULT0.
-//!
-//! \return Returns \b true if the specified pin is present and \b false if it
-//! is not.
-//
-//*****************************************************************************
-tBoolean
-SysCtlPinPresent(unsigned long ulPin)
-{
- //
- // Check the arguments.
- //
- ASSERT((ulPin == SYSCTL_PIN_PWM0) ||
- (ulPin == SYSCTL_PIN_PWM1) ||
- (ulPin == SYSCTL_PIN_PWM2) ||
- (ulPin == SYSCTL_PIN_PWM3) ||
- (ulPin == SYSCTL_PIN_PWM4) ||
- (ulPin == SYSCTL_PIN_PWM5) ||
- (ulPin == SYSCTL_PIN_C0MINUS) ||
- (ulPin == SYSCTL_PIN_C0PLUS) ||
- (ulPin == SYSCTL_PIN_C0O) ||
- (ulPin == SYSCTL_PIN_C1MINUS) ||
- (ulPin == SYSCTL_PIN_C1PLUS) ||
- (ulPin == SYSCTL_PIN_C1O) ||
- (ulPin == SYSCTL_PIN_C2MINUS) ||
- (ulPin == SYSCTL_PIN_C2PLUS) ||
- (ulPin == SYSCTL_PIN_C2O) ||
- (ulPin == SYSCTL_PIN_MC_FAULT0) ||
- (ulPin == SYSCTL_PIN_ADC0) ||
- (ulPin == SYSCTL_PIN_ADC1) ||
- (ulPin == SYSCTL_PIN_ADC2) ||
- (ulPin == SYSCTL_PIN_ADC3) ||
- (ulPin == SYSCTL_PIN_ADC4) ||
- (ulPin == SYSCTL_PIN_ADC5) ||
- (ulPin == SYSCTL_PIN_ADC6) ||
- (ulPin == SYSCTL_PIN_ADC7) ||
- (ulPin == SYSCTL_PIN_CCP0) ||
- (ulPin == SYSCTL_PIN_CCP1) ||
- (ulPin == SYSCTL_PIN_CCP2) ||
- (ulPin == SYSCTL_PIN_CCP3) ||
- (ulPin == SYSCTL_PIN_CCP4) ||
- (ulPin == SYSCTL_PIN_CCP5) ||
- (ulPin == SYSCTL_PIN_32KHZ));
-
- //
- // Determine if this pin is present.
- //
- if(HWREG(SYSCTL_DC3) & ulPin)
- {
- return(true);
- }
- else
- {
- return(false);
- }
-}
-
-//*****************************************************************************
-//
-//! Determines if a peripheral is present.
-//!
-//! \param ulPeripheral is the peripheral in question.
-//!
-//! Determines if a particular peripheral is present in the device. Each
-//! member of the Stellaris family has a different peripheral set; this will
-//! determine which are present on this device.
-//!
-//! The \e ulPeripheral parameter must be only one of the following values:
-//! \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_CAN0, \b SYSCTL_PERIPH_CAN1,
-//! \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, \b SYSCTL_PERIPH_COMP1,
-//! \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA,
-//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD,
-//! \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG,
-//! \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
-//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_IEEE1588, \b SYSCTL_PERIPH_MPU,
-//! \b SYSCTL_PERIPH_PLL, \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_QEI0,
-//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1,
-//! \b SYSCTL_PERIPH_TEMP, \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1,
-//! \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_UART0,
-//! \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UDMA,
-//! \b SYSCTL_PERIPH_USB0, or \b SYSCTL_PERIPH_WDOG.
-//!
-//! \return Returns \b true if the specified peripheral is present and \b false
-//! if it is not.
-//
-//*****************************************************************************
-tBoolean
-SysCtlPeripheralPresent(unsigned long ulPeripheral)
-{
- //
- // Check the arguments.
- //
- ASSERT(SysCtlPeripheralValid(ulPeripheral));
-
- //
- // Read the correct DC register and determine if this peripheral exists.
- //
- if(HWREG(g_pulDCRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) &
- SYSCTL_PERIPH_MASK(ulPeripheral))
- {
- return(true);
- }
- else
- {
- return(false);
- }
-}
-
-//*****************************************************************************
-//
-//! Performs a software reset of a peripheral.
-//!
-//! \param ulPeripheral is the peripheral to reset.
-//!
-//! This function performs a software reset of the specified peripheral. An
-//! individual peripheral reset signal is asserted for a brief period and then
-//! deasserted, leaving the peripheral in a operating state but in its reset
-//! condition.
-//!
-//! The \e ulPeripheral parameter must be only one of the following values:
-//! \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_CAN0, \b SYSCTL_PERIPH_CAN1,
-//! \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, \b SYSCTL_PERIPH_COMP1,
-//! \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA,
-//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD,
-//! \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG,
-//! \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
-//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_QEI0,
-//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1,
-//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2,
-//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1,
-//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, or
-//! \b SYSCTL_PERIPH_WDOG.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SysCtlPeripheralReset(unsigned long ulPeripheral)
-{
- volatile unsigned long ulDelay;
-
- //
- // Check the arguments.
- //
- ASSERT(SysCtlPeripheralValid(ulPeripheral));
-
- //
- // Put the peripheral into the reset state.
- //
- HWREG(g_pulSRCRRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) |=
- SYSCTL_PERIPH_MASK(ulPeripheral);
-
- //
- // Delay for a little bit.
- //
- for(ulDelay = 0; ulDelay < 16; ulDelay++)
- {
- }
-
- //
- // Take the peripheral out of the reset state.
- //
- HWREG(g_pulSRCRRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) &=
- ~SYSCTL_PERIPH_MASK(ulPeripheral);
-}
-
-//*****************************************************************************
-//
-//! Enables a peripheral.
-//!
-//! \param ulPeripheral is the peripheral to enable.
-//!
-//! Peripherals are enabled with this function. At power-up, all peripherals
-//! are disabled; they must be enabled in order to operate or respond to
-//! register reads/writes.
-//!
-//! The \e ulPeripheral parameter must be only one of the following values:
-//! \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_CAN0, \b SYSCTL_PERIPH_CAN1,
-//! \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, \b SYSCTL_PERIPH_COMP1,
-//! \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA,
-//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD,
-//! \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG,
-//! \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
-//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_QEI0,
-//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1,
-//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2,
-//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1,
-//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, or
-//! \b SYSCTL_PERIPH_WDOG.
-//!
-//! \note It takes five clock cycles after the write to enable a peripheral
-//! before the the peripheral is actually enabled. During this time, attempts
-//! to access the peripheral will result in a bus fault. Care should be taken
-//! to ensure that the peripheral is not accessed during this brief time
-//! period.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SysCtlPeripheralEnable(unsigned long ulPeripheral)
-{
- //
- // Check the arguments.
- //
- ASSERT(SysCtlPeripheralValid(ulPeripheral));
-
- //
- // Enable this peripheral.
- //
- HWREG(g_pulRCGCRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) |=
- SYSCTL_PERIPH_MASK(ulPeripheral);
-}
-
-//*****************************************************************************
-//
-//! Disables a peripheral.
-//!
-//! \param ulPeripheral is the peripheral to disable.
-//!
-//! Peripherals are disabled with this function. Once disabled, they will not
-//! operate or respond to register reads/writes.
-//!
-//! The \e ulPeripheral parameter must be only one of the following values:
-//! \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_CAN0, \b SYSCTL_PERIPH_CAN1,
-//! \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, \b SYSCTL_PERIPH_COMP1,
-//! \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA,
-//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD,
-//! \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG,
-//! \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
-//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_QEI0,
-//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1,
-//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2,
-//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1,
-//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, or
-//! \b SYSCTL_PERIPH_WDOG.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SysCtlPeripheralDisable(unsigned long ulPeripheral)
-{
- //
- // Check the arguments.
- //
- ASSERT(SysCtlPeripheralValid(ulPeripheral));
-
- //
- // Disable this peripheral.
- //
- HWREG(g_pulRCGCRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) &=
- ~SYSCTL_PERIPH_MASK(ulPeripheral);
-}
-
-//*****************************************************************************
-//
-//! Enables a peripheral in sleep mode.
-//!
-//! \param ulPeripheral is the peripheral to enable in sleep mode.
-//!
-//! This function allows a peripheral to continue operating when the processor
-//! goes into sleep mode. Since the clocking configuration of the device does
-//! not change, any peripheral can safely continue operating while the
-//! processor is in sleep mode, and can therefore wake the processor from sleep
-//! mode.
-//!
-//! Sleep mode clocking of peripherals must be enabled via
-//! SysCtlPeripheralClockGating(); if disabled, the peripheral sleep mode
-//! configuration is maintained but has no effect when sleep mode is entered.
-//!
-//! The \e ulPeripheral parameter must be only one of the following values:
-//! \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_CAN0, \b SYSCTL_PERIPH_CAN1,
-//! \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, \b SYSCTL_PERIPH_COMP1,
-//! \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA,
-//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD,
-//! \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG,
-//! \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
-//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_QEI0,
-//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1,
-//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2,
-//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1,
-//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, or
-//! \b SYSCTL_PERIPH_WDOG.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SysCtlPeripheralSleepEnable(unsigned long ulPeripheral)
-{
- //
- // Check the arguments.
- //
- ASSERT(SysCtlPeripheralValid(ulPeripheral));
-
- //
- // Enable this peripheral in sleep mode.
- //
- HWREG(g_pulSCGCRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) |=
- SYSCTL_PERIPH_MASK(ulPeripheral);
-}
-
-//*****************************************************************************
-//
-//! Disables a peripheral in sleep mode.
-//!
-//! \param ulPeripheral is the peripheral to disable in sleep mode.
-//!
-//! This function causes a peripheral to stop operating when the processor goes
-//! into sleep mode. Disabling peripherals while in sleep mode helps to lower
-//! the current draw of the device. If enabled (via SysCtlPeripheralEnable()),
-//! the peripheral will automatically resume operation when the processor
-//! leaves sleep mode, maintaining its entire state from before sleep mode was
-//! entered.
-//!
-//! Sleep mode clocking of peripherals must be enabled via
-//! SysCtlPeripheralClockGating(); if disabled, the peripheral sleep mode
-//! configuration is maintained but has no effect when sleep mode is entered.
-//!
-//! The \e ulPeripheral parameter must be only one of the following values:
-//! \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_CAN0, \b SYSCTL_PERIPH_CAN1,
-//! \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, \b SYSCTL_PERIPH_COMP1,
-//! \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA,
-//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD,
-//! \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG,
-//! \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
-//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_QEI0,
-//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1,
-//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2,
-//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1,
-//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, or
-//! \b SYSCTL_PERIPH_WDOG.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SysCtlPeripheralSleepDisable(unsigned long ulPeripheral)
-{
- //
- // Check the arguments.
- //
- ASSERT(SysCtlPeripheralValid(ulPeripheral));
-
- //
- // Disable this peripheral in sleep mode.
- //
- HWREG(g_pulSCGCRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) &=
- ~SYSCTL_PERIPH_MASK(ulPeripheral);
-}
-
-//*****************************************************************************
-//
-//! Enables a peripheral in deep-sleep mode.
-//!
-//! \param ulPeripheral is the peripheral to enable in deep-sleep mode.
-//!
-//! This function allows a peripheral to continue operating when the processor
-//! goes into deep-sleep mode. Since the clocking configuration of the device
-//! may change, not all peripherals can safely continue operating while the
-//! processor is in sleep mode. Those that must run at a particular frequency
-//! (such as a UART) will not work as expected if the clock changes. It is the
-//! responsibility of the caller to make sensible choices.
-//!
-//! Deep-sleep mode clocking of peripherals must be enabled via
-//! SysCtlPeripheralClockGating(); if disabled, the peripheral deep-sleep mode
-//! configuration is maintained but has no effect when deep-sleep mode is
-//! entered.
-//!
-//! The \e ulPeripheral parameter must be one of the following values:
-//! \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_CAN0, \b SYSCTL_PERIPH_CAN1,
-//! \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, \b SYSCTL_PERIPH_COMP1,
-//! \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA,
-//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD,
-//! \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG,
-//! \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
-//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_QEI0,
-//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1,
-//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2,
-//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1,
-//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, or
-//! \b SYSCTL_PERIPH_WDOG.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral)
-{
- //
- // Check the arguments.
- //
- ASSERT(SysCtlPeripheralValid(ulPeripheral));
-
- //
- // Enable this peripheral in deep-sleep mode.
- //
- HWREG(g_pulDCGCRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) |=
- SYSCTL_PERIPH_MASK(ulPeripheral);
-}
-
-//*****************************************************************************
-//
-//! Disables a peripheral in deep-sleep mode.
-//!
-//! \param ulPeripheral is the peripheral to disable in deep-sleep mode.
-//!
-//! This function causes a peripheral to stop operating when the processor goes
-//! into deep-sleep mode. Disabling peripherals while in deep-sleep mode helps
-//! to lower the current draw of the device, and can keep peripherals that
-//! require a particular clock frequency from operating when the clock changes
-//! as a result of entering deep-sleep mode. If enabled (via
-//! SysCtlPeripheralEnable()), the peripheral will automatically resume
-//! operation when the processor leaves deep-sleep mode, maintaining its entire
-//! state from before deep-sleep mode was entered.
-//!
-//! Deep-sleep mode clocking of peripherals must be enabled via
-//! SysCtlPeripheralClockGating(); if disabled, the peripheral deep-sleep mode
-//! configuration is maintained but has no effect when deep-sleep mode is
-//! entered.
-//!
-//! The \e ulPeripheral parameter must be one of the following values:
-//! \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_CAN0, \b SYSCTL_PERIPH_CAN1,
-//! \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, \b SYSCTL_PERIPH_COMP1,
-//! \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA,
-//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD,
-//! \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG,
-//! \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
-//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_QEI0,
-//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1,
-//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2,
-//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1,
-//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, or
-//! \b SYSCTL_PERIPH_WDOG.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral)
-{
- //
- // Check the arguments.
- //
- ASSERT(SysCtlPeripheralValid(ulPeripheral));
-
- //
- // Disable this peripheral in deep-sleep mode.
- //
- HWREG(g_pulDCGCRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) &=
- ~SYSCTL_PERIPH_MASK(ulPeripheral);
-}
-
-//*****************************************************************************
-//
-//! Controls peripheral clock gating in sleep and deep-sleep mode.
-//!
-//! \param bEnable is a boolean that is \b true if the sleep and deep-sleep
-//! peripheral configuration should be used and \b false if not.
-//!
-//! This function controls how peripherals are clocked when the processor goes
-//! into sleep or deep-sleep mode. By default, the peripherals are clocked the
-//! same as in run mode; if peripheral clock gating is enabled they are clocked
-//! according to the configuration set by SysCtlPeripheralSleepEnable(),
-//! SysCtlPeripheralSleepDisable(), SysCtlPeripheralDeepSleepEnable(), and
-//! SysCtlPeripheralDeepSleepDisable().
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SysCtlPeripheralClockGating(tBoolean bEnable)
-{
- //
- // Enable peripheral clock gating as requested.
- //
- if(bEnable)
- {
- HWREG(SYSCTL_RCC) |= SYSCTL_RCC_ACG;
- }
- else
- {
- HWREG(SYSCTL_RCC) &= ~(SYSCTL_RCC_ACG);
- }
-}
-
-//*****************************************************************************
-//
-//! Registers an interrupt handler for the system control interrupt.
-//!
-//! \param pfnHandler is a pointer to the function to be called when the system
-//! control interrupt occurs.
-//!
-//! This sets the handler to be called when a system control interrupt occurs.
-//! This will enable the global interrupt in the interrupt controller; specific
-//! system control interrupts must be enabled via SysCtlIntEnable(). It is the
-//! interrupt handler's responsibility to clear the interrupt source via
-//! SysCtlIntClear().
-//!
-//! System control can generate interrupts when the PLL achieves lock, if the
-//! internal LDO current limit is exceeded, if the internal oscillator fails,
-//! if the main oscillator fails, if the internal LDO output voltage droops too
-//! much, if the external voltage droops too much, or if the PLL fails.
-//!
-//! \sa IntRegister() for important information about registering interrupt
-//! handlers.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SysCtlIntRegister(void (*pfnHandler)(void))
-{
- //
- // Register the interrupt handler, returning an error if an error occurs.
- //
- IntRegister(INT_SYSCTL, pfnHandler);
-
- //
- // Enable the system control interrupt.
- //
- IntEnable(INT_SYSCTL);
-}
-
-//*****************************************************************************
-//
-//! Unregisters the interrupt handler for the system control interrupt.
-//!
-//! This function will clear the handler to be called when a system control
-//! interrupt occurs. This will also mask off the interrupt in the interrupt
-//! controller so that the interrupt handler no longer is called.
-//!
-//! \sa IntRegister() for important information about registering interrupt
-//! handlers.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SysCtlIntUnregister(void)
-{
- //
- // Disable the interrupt.
- //
- IntDisable(INT_SYSCTL);
-
- //
- // Unregister the interrupt handler.
- //
- IntUnregister(INT_SYSCTL);
-}
-
-//*****************************************************************************
-//
-//! Enables individual system control interrupt sources.
-//!
-//! \param ulInts is a bit mask of the interrupt sources to be enabled. Must
-//! be a logical OR of \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_CUR_LIMIT,
-//! \b SYSCTL_INT_IOSC_FAIL, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR,
-//! \b SYSCTL_INT_BOR, and/or \b SYSCTL_INT_PLL_FAIL.
-//!
-//! Enables the indicated system control interrupt sources. Only the sources
-//! that are enabled can be reflected to the processor interrupt; disabled
-//! sources have no effect on the processor.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SysCtlIntEnable(unsigned long ulInts)
-{
- //
- // Enable the specified interrupts.
- //
- HWREG(SYSCTL_IMC) |= ulInts;
-}
-
-//*****************************************************************************
-//
-//! Disables individual system control interrupt sources.
-//!
-//! \param ulInts is a bit mask of the interrupt sources to be disabled. Must
-//! be a logical OR of \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_CUR_LIMIT,
-//! \b SYSCTL_INT_IOSC_FAIL, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR,
-//! \b SYSCTL_INT_BOR, and/or \b SYSCTL_INT_PLL_FAIL.
-//!
-//! Disables the indicated system control interrupt sources. Only the sources
-//! that are enabled can be reflected to the processor interrupt; disabled
-//! sources have no effect on the processor.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SysCtlIntDisable(unsigned long ulInts)
-{
- //
- // Disable the specified interrupts.
- //
- HWREG(SYSCTL_IMC) &= ~(ulInts);
-}
-
-//*****************************************************************************
-//
-//! Clears system control interrupt sources.
-//!
-//! \param ulInts is a bit mask of the interrupt sources to be cleared. Must
-//! be a logical OR of \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_CUR_LIMIT,
-//! \b SYSCTL_INT_IOSC_FAIL, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR,
-//! \b SYSCTL_INT_BOR, and/or \b SYSCTL_INT_PLL_FAIL.
-//!
-//! The specified system control interrupt sources are cleared, so that they no
-//! longer assert. This must be done in the interrupt handler to keep it from
-//! being called again immediately upon exit.
-//!
-//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
-//! several clock cycles before the interrupt source is actually cleared.
-//! Therefore, it is recommended that the interrupt source be cleared early in
-//! the interrupt handler (as opposed to the very last action) to avoid
-//! returning from the interrupt handler before the interrupt source is
-//! actually cleared. Failure to do so may result in the interrupt handler
-//! being immediately reentered (since NVIC still sees the interrupt source
-//! asserted).
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SysCtlIntClear(unsigned long ulInts)
-{
- //
- // Clear the requested interrupt sources.
- //
- HWREG(SYSCTL_MISC) = ulInts;
-}
-
-//*****************************************************************************
-//
-//! Gets the current interrupt status.
-//!
-//! \param bMasked is false if the raw interrupt status is required and true if
-//! the masked interrupt status is required.
-//!
-//! This returns the interrupt status for the system controller. Either the
-//! raw interrupt status or the status of interrupts that are allowed to
-//! reflect to the processor can be returned.
-//!
-//! \return The current interrupt status, enumerated as a bit field of
-//! \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_CUR_LIMIT, \b SYSCTL_INT_IOSC_FAIL,
-//! \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR, \b SYSCTL_INT_BOR, and
-//! \b SYSCTL_INT_PLL_FAIL.
-//
-//*****************************************************************************
-unsigned long
-SysCtlIntStatus(tBoolean bMasked)
-{
- //
- // Return either the interrupt status or the raw interrupt status as
- // requested.
- //
- if(bMasked)
- {
- return(HWREG(SYSCTL_MISC));
- }
- else
- {
- return(HWREG(SYSCTL_RIS));
- }
-}
-
-//*****************************************************************************
-//
-//! Sets the output voltage of the LDO.
-//!
-//! \param ulVoltage is the required output voltage from the LDO. Must be one
-//! of \b SYSCTL_LDO_2_25V, \b SYSCTL_LDO_2_30V, \b SYSCTL_LDO_2_35V,
-//! \b SYSCTL_LDO_2_40V, \b SYSCTL_LDO_2_45V, \b SYSCTL_LDO_2_50V,
-//! \b SYSCTL_LDO_2_55V, \b SYSCTL_LDO_2_60V, \b SYSCTL_LDO_2_65V,
-//! \b SYSCTL_LDO_2_70V, or \b SYSCTL_LDO_2_75V.
-//!
-//! This function sets the output voltage of the LDO. The default voltage is
-//! 2.5 V; it can be adjusted +/- 10%.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SysCtlLDOSet(unsigned long ulVoltage)
-{
- //
- // Check the arguments.
- //
- ASSERT((ulVoltage == SYSCTL_LDO_2_25V) ||
- (ulVoltage == SYSCTL_LDO_2_30V) ||
- (ulVoltage == SYSCTL_LDO_2_35V) ||
- (ulVoltage == SYSCTL_LDO_2_40V) ||
- (ulVoltage == SYSCTL_LDO_2_45V) ||
- (ulVoltage == SYSCTL_LDO_2_50V) ||
- (ulVoltage == SYSCTL_LDO_2_55V) ||
- (ulVoltage == SYSCTL_LDO_2_60V) ||
- (ulVoltage == SYSCTL_LDO_2_65V) ||
- (ulVoltage == SYSCTL_LDO_2_70V) ||
- (ulVoltage == SYSCTL_LDO_2_75V));
-
- //
- // Set the LDO voltage to the requested value.
- //
- HWREG(SYSCTL_LDOPCTL) = ulVoltage;
-}
-
-//*****************************************************************************
-//
-//! Gets the output voltage of the LDO.
-//!
-//! This function determines the output voltage of the LDO, as specified by the
-//! control register.
-//!
-//! \return Returns the current voltage of the LDO; will be one of
-//! \b SYSCTL_LDO_2_25V, \b SYSCTL_LDO_2_30V, \b SYSCTL_LDO_2_35V,
-//! \b SYSCTL_LDO_2_40V, \b SYSCTL_LDO_2_45V, \b SYSCTL_LDO_2_50V,
-//! \b SYSCTL_LDO_2_55V, \b SYSCTL_LDO_2_60V, \b SYSCTL_LDO_2_65V,
-//! \b SYSCTL_LDO_2_70V, or \b SYSCTL_LDO_2_75V.
-//
-//*****************************************************************************
-unsigned long
-SysCtlLDOGet(void)
-{
- //
- // Return the LDO voltage setting.
- //
- return(HWREG(SYSCTL_LDOPCTL));
-}
-
-//*****************************************************************************
-//
-//! Configures the LDO failure control.
-//!
-//! \param ulConfig is the required LDO failure control setting; can be either
-//! \b SYSCTL_LDOCFG_ARST or \b SYSCTL_LDOCFG_NORST.
-//!
-//! This function allows the LDO to be configured to cause a processor reset
-//! when the output voltage becomes unregulated.
-//!
-//! The LDO failure control is only available on Sandstorm-class devices.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SysCtlLDOConfigSet(unsigned long ulConfig)
-{
- //
- // Check the arguments.
- //
- ASSERT((ulConfig == SYSCTL_LDOCFG_ARST) ||
- (ulConfig == SYSCTL_LDOCFG_NORST));
-
- //
- // Set the reset control as requested.
- //
- HWREG(SYSCTL_LDOARST) = ulConfig;
-}
-
-//*****************************************************************************
-//
-//! Resets the device.
-//!
-//! This function will perform a software reset of the entire device. The
-//! processor and all peripherals will be reset and all device registers will
-//! return to their default values (with the exception of the reset cause
-//! register, which will maintain its current value but have the software reset
-//! bit set as well).
-//!
-//! \return This function does not return.
-//
-//*****************************************************************************
-void
-SysCtlReset(void)
-{
- //
- // Perform a software reset request. This will cause the device to reset,
- // no further code will be executed.
- //
- HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | NVIC_APINT_SYSRESETREQ;
-
- //
- // The device should have reset, so this should never be reached. Just in
- // case, loop forever.
- //
- while(1)
- {
- }
-}
-
-//*****************************************************************************
-//
-//! Puts the processor into sleep mode.
-//!
-//! This function places the processor into sleep mode; it will not return
-//! until the processor returns to run mode. The peripherals that are enabled
-//! via SysCtlPeripheralSleepEnable() continue to operate and can wake up the
-//! processor (if automatic clock gating is enabled with
-//! SysCtlPeripheralClockGating(), otherwise all peripherals continue to
-//! operate).
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SysCtlSleep(void)
-{
- //
- // Wait for an interrupt.
- //
- CPUwfi();
-}
-
-//*****************************************************************************
-//
-//! Puts the processor into deep-sleep mode.
-//!
-//! This function places the processor into deep-sleep mode; it will not return
-//! until the processor returns to run mode. The peripherals that are enabled
-//! via SysCtlPeripheralDeepSleepEnable() continue to operate and can wake up
-//! the processor (if automatic clock gating is enabled with
-//! SysCtlPeripheralClockGating(), otherwise all peripherals continue to
-//! operate).
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SysCtlDeepSleep(void)
-{
- //
- // Enable deep-sleep.
- //
- HWREG(NVIC_SYS_CTRL) |= NVIC_SYS_CTRL_SLEEPDEEP;
-
- //
- // Wait for an interrupt.
- //
- CPUwfi();
-
- //
- // Disable deep-sleep so that a future sleep will work correctly.
- //
- HWREG(NVIC_SYS_CTRL) &= ~(NVIC_SYS_CTRL_SLEEPDEEP);
-}
-
-//*****************************************************************************
-//
-//! Gets the reason for a reset.
-//!
-//! This function will return the reason(s) for a reset. Since the reset
-//! reasons are sticky until either cleared by software or an external reset,
-//! multiple reset reasons may be returned if multiple resets have occurred.
-//! The reset reason will be a logical OR of \b SYSCTL_CAUSE_LDO,
-//! \b SYSCTL_CAUSE_SW, \b SYSCTL_CAUSE_WDOG, \b SYSCTL_CAUSE_BOR,
-//! \b SYSCTL_CAUSE_POR, and/or \b SYSCTL_CAUSE_EXT.
-//!
-//! \return Returns the reason(s) for a reset.
-//
-//*****************************************************************************
-unsigned long
-SysCtlResetCauseGet(void)
-{
- //
- // Return the reset reasons.
- //
- return(HWREG(SYSCTL_RESC));
-}
-
-//*****************************************************************************
-//
-//! Clears reset reasons.
-//!
-//! \param ulCauses are the reset causes to be cleared; must be a logical OR of
-//! \b SYSCTL_CAUSE_LDO, \b SYSCTL_CAUSE_SW, \b SYSCTL_CAUSE_WDOG,
-//! \b SYSCTL_CAUSE_BOR, \b SYSCTL_CAUSE_POR, and/or \b SYSCTL_CAUSE_EXT.
-//!
-//! This function clears the specified sticky reset reasons. Once cleared,
-//! another reset for the same reason can be detected, and a reset for a
-//! different reason can be distinguished (instead of having two reset causes
-//! set). If the reset reason is used by an application, all reset causes
-//! should be cleared after they are retrieved with SysCtlResetCauseGet().
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SysCtlResetCauseClear(unsigned long ulCauses)
-{
- //
- // Clear the given reset reasons.
- //
- HWREG(SYSCTL_RESC) &= ~(ulCauses);
-}
-
-//*****************************************************************************
-//
-//! Configures the brown-out control.
-//!
-//! \param ulConfig is the desired configuration of the brown-out control.
-//! Must be the logical OR of \b SYSCTL_BOR_RESET and/or
-//! \b SYSCTL_BOR_RESAMPLE.
-//! \param ulDelay is the number of internal oscillator cycles to wait before
-//! resampling an asserted brown-out signal. This value only has meaning when
-//! \b SYSCTL_BOR_RESAMPLE is set and must be less than 8192.
-//!
-//! This function configures how the brown-out control operates. It can detect
-//! a brown-out by looking at only the brown-out output, or it can wait for it
-//! to be active for two consecutive samples separated by a configurable time.
-//! When it detects a brown-out condition, it can either reset the device or
-//! generate a processor interrupt.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SysCtlBrownOutConfigSet(unsigned long ulConfig, unsigned long ulDelay)
-{
- //
- // Check the arguments.
- //
- ASSERT(!(ulConfig & ~(SYSCTL_BOR_RESET | SYSCTL_BOR_RESAMPLE)));
- ASSERT(ulDelay < 8192);
-
- //
- // Configure the brown-out reset control.
- //
- HWREG(SYSCTL_PBORCTL) = (ulDelay << SYSCTL_PBORCTL_BORTIM_S) | ulConfig;
-}
-
-//*****************************************************************************
-//
-//! Provides a small delay.
-//!
-//! \param ulCount is the number of delay loop iterations to perform.
-//!
-//! This function provides a means of generating a constant length delay. It
-//! is written in assembly to keep the delay consistent across tool chains,
-//! avoiding the need to tune the delay based on the tool chain in use.
-//!
-//! The loop takes 3 cycles/loop.
-//!
-//! \return None.
-//
-//*****************************************************************************
-#if defined(ewarm) || defined(DOXYGEN)
-void
-SysCtlDelay(unsigned long ulCount)
-{
- __asm(" subs r0, #1\n"
- " bne.n SysCtlDelay\n"
- " bx lr");
-}
-#endif
-#if defined(codered) || defined(gcc) || defined(sourcerygxx)
-void __attribute__((naked))
-SysCtlDelay(unsigned long ulCount)
-{
- __asm(" subs r0, #1\n"
- " bne SysCtlDelay\n"
- " bx lr");
-}
-#endif
-#if defined(rvmdk) || defined(__ARMCC_VERSION)
-__asm void
-SysCtlDelay(unsigned long ulCount)
-{
- subs r0, #1;
- bne SysCtlDelay;
- bx lr;
-}
-#endif
-
-//*****************************************************************************
-//
-//! Sets the clocking of the device.
-//!
-//! \param ulConfig is the required configuration of the device clocking.
-//!
-//! This function configures the clocking of the device. The input crystal
-//! frequency, oscillator to be used, use of the PLL, and the system clock
-//! divider are all configured with this function.
-//!
-//! The \e ulConfig parameter is the logical OR of several different values,
-//! many of which are grouped into sets where only one can be chosen.
-//!
-//! The system clock divider is chosen with one of the following values:
-//! \b SYSCTL_SYSDIV_1, \b SYSCTL_SYSDIV_2, \b SYSCTL_SYSDIV_3, ...
-//! \b SYSCTL_SYSDIV_64. Only \b SYSCTL_SYSDIV_1 through \b SYSCTL_SYSDIV_16
-//! are valid on Sandstorm-class devices.
-//!
-//! The use of the PLL is chosen with either \b SYSCTL_USE_PLL or
-//! \b SYSCTL_USE_OSC.
-//!
-//! The external crystal frequency is chosen with one of the following values:
-//! \b SYSCTL_XTAL_1MHZ, \b SYSCTL_XTAL_1_84MHZ, \b SYSCTL_XTAL_2MHZ,
-//! \b SYSCTL_XTAL_2_45MHZ, \b SYSCTL_XTAL_3_57MHZ, \b SYSCTL_XTAL_3_68MHZ,
-//! \b SYSCTL_XTAL_4MHZ, \b SYSCTL_XTAL_4_09MHZ, \b SYSCTL_XTAL_4_91MHZ,
-//! \b SYSCTL_XTAL_5MHZ, \b SYSCTL_XTAL_5_12MHZ, \b SYSCTL_XTAL_6MHZ,
-//! \b SYSCTL_XTAL_6_14MHZ, \b SYSCTL_XTAL_7_37MHZ, \b SYSCTL_XTAL_8MHZ,
-//! \b SYSCTL_XTAL_8_19MHZ, \b SYSCTL_XTAL_10MHZ, \b SYSCTL_XTAL_12MHZ,
-//! \b SYSCTL_XTAL_12_2MHZ, \b SYSCTL_XTAL_13_5MHZ, \b SYSCTL_XTAL_14_3MHZ,
-//! \b SYSCTL_XTAL_16MHZ, or \b SYSCTL_XTAL_16_3MHZ. Values below
-//! \b SYSCTL_XTAL_3_57MHZ are not valid when the PLL is in operation. On
-//! Sandstorm- and Fury-class devices, values above \b SYSCTL_XTAL_8_19MHZ are
-//! not valid.
-//!
-//! The oscillator source is chosen with one of the following values:
-//! \b SYSCTL_OSC_MAIN, \b SYSCTL_OSC_INT, \b SYSCTL_OSC_INT4,
-//! \b SYSCTL_OSC_INT30, or \b SYSCTL_OSC_EXT32. On Sandstorm-class devices,
-//! \b SYSCTL_OSC_INT30 and \b SYSCTL_OSC_EXT32 are not valid.
-//! \b SYSCTL_OSC_EXT32 is only available on devices with the hibernate module,
-//! and then only when the hibernate module has been enabled.
-//!
-//! The internal and main oscillators are disabled with the
-//! \b SYSCTL_INT_OSC_DIS and \b SYSCTL_MAIN_OSC_DIS flags, respectively.
-//! The external oscillator must be enabled in order to use an external clock
-//! source. Note that attempts to disable the oscillator used to clock the
-//! device will be prevented by the hardware.
-//!
-//! To clock the system from an external source (such as an external crystal
-//! oscillator), use \b SYSCTL_USE_OSC \b | \b SYSCTL_OSC_MAIN. To clock the
-//! system from the main oscillator, use \b SYSCTL_USE_OSC \b |
-//! \b SYSCTL_OSC_MAIN. To clock the system from the PLL, use
-//! \b SYSCTL_USE_PLL \b | \b SYSCTL_OSC_MAIN, and select the appropriate
-//! crystal with one of the \b SYSCTL_XTAL_xxx values.
-//!
-//! \note If selecting the PLL as the system clock source (that is, via
-//! \b SYSCTL_USE_PLL), this function will poll the PLL lock interrupt to
-//! determine when the PLL has locked. If an interrupt handler for the
-//! system control interrupt is in place, and it responds to and clears the
-//! PLL lock interrupt, this function will delay until its timeout has occurred
-//! instead of completing as soon as PLL lock is achieved.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SysCtlClockSet(unsigned long ulConfig)
-{
- unsigned long ulDelay, ulRCC, ulRCC2;
-
- //
- // See if this is a Sandstorm-class device and clocking features from newer
- // devices were requested.
- //
- if(CLASS_IS_SANDSTORM && (ulConfig & SYSCTL_RCC2_USERCC2))
- {
- //
- // Return without changing the clocking since the requested
- // configuration can not be achieved.
- //
- return;
- }
-
- //
- // Get the current value of the RCC and RCC2 registers. If using a
- // Sandstorm-class device, the RCC2 register will read back as zero and the
- // writes to it from within this function will be ignored.
- //
- ulRCC = HWREG(SYSCTL_RCC);
- ulRCC2 = HWREG(SYSCTL_RCC2);
-
- //
- // Bypass the PLL and system clock dividers for now.
- //
- ulRCC |= SYSCTL_RCC_BYPASS;
- ulRCC &= ~(SYSCTL_RCC_USESYSDIV);
- ulRCC2 |= SYSCTL_RCC2_BYPASS2;
-
- //
- // Write the new RCC value.
- //
- HWREG(SYSCTL_RCC) = ulRCC;
- HWREG(SYSCTL_RCC2) = ulRCC2;
-
- //
- // See if either oscillator needs to be enabled.
- //
- if(((ulRCC & SYSCTL_RCC_IOSCDIS) && !(ulConfig & SYSCTL_RCC_IOSCDIS)) ||
- ((ulRCC & SYSCTL_RCC_MOSCDIS) && !(ulConfig & SYSCTL_RCC_MOSCDIS)))
- {
- //
- // Make sure that the required oscillators are enabled. For now, the
- // previously enabled oscillators must be enabled along with the newly
- // requested oscillators.
- //
- ulRCC &= (~(SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS) |
- (ulConfig & (SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS)));
-
- //
- // Write the new RCC value.
- //
- HWREG(SYSCTL_RCC) = ulRCC;
-
- //
- // Wait for a bit, giving the oscillator time to stabilize. The number
- // of iterations is adjusted based on the current clock source; a
- // smaller number of iterations is required for slower clock rates.
- //
- if(((ulRCC2 & SYSCTL_RCC2_USERCC2) &&
- (((ulRCC2 & SYSCTL_RCC2_OSCSRC2_M) == SYSCTL_RCC2_OSCSRC2_30) ||
- ((ulRCC2 & SYSCTL_RCC2_OSCSRC2_M) == SYSCTL_RCC2_OSCSRC2_32))) ||
- (!(ulRCC2 & SYSCTL_RCC2_USERCC2) &&
- ((ulRCC & SYSCTL_RCC_OSCSRC_M) == SYSCTL_RCC_OSCSRC_30)))
- {
- //
- // Delay for 4096 iterations.
- //
- SysCtlDelay(4096);
- }
- else
- {
- //
- // Delay for 524,288 iterations.
- //
- SysCtlDelay(524288);
- }
- }
-
- //
- // Set the new crystal value, oscillator source, and PLL configuration.
- // Since the OSCSRC2 field in RCC2 overlaps the XTAL field in RCC, the
- // OSCSRC field has a special encoding within ulConfig to avoid the
- // overlap.
- //
- ulRCC &= ~(SYSCTL_RCC_XTAL_M | SYSCTL_RCC_OSCSRC_M |
- SYSCTL_RCC_PWRDN | SYSCTL_RCC_OEN);
- ulRCC |= ulConfig & (SYSCTL_RCC_XTAL_M | SYSCTL_RCC_OSCSRC_M |
- SYSCTL_RCC_PWRDN | SYSCTL_RCC_OEN);
- ulRCC2 &= ~(SYSCTL_RCC2_USERCC2 | SYSCTL_RCC2_OSCSRC2_M |
- SYSCTL_RCC2_PWRDN2);
- ulRCC2 |= ulConfig & (SYSCTL_RCC2_USERCC2 | SYSCTL_RCC_OSCSRC_M |
- SYSCTL_RCC2_PWRDN2);
- ulRCC2 |= (ulConfig & 0x00000008) << 3;
-
- //
- // Clear the PLL lock interrupt.
- //
- HWREG(SYSCTL_MISC) = SYSCTL_INT_PLL_LOCK;
-
- //
- // Write the new RCC value.
- //
- if(ulRCC2 & SYSCTL_RCC2_USERCC2)
- {
- HWREG(SYSCTL_RCC2) = ulRCC2;
- HWREG(SYSCTL_RCC) = ulRCC;
- }
- else
- {
- HWREG(SYSCTL_RCC) = ulRCC;
- HWREG(SYSCTL_RCC2) = ulRCC2;
- }
-
- //
- // Wait for a bit so that new crystal value and oscillator source can take
- // effect.
- //
- SysCtlDelay(16);
-
- //
- // Set the requested system divider and disable the appropriate
- // oscillators. This will not get written immediately.
- //
- ulRCC &= ~(SYSCTL_RCC_SYSDIV_M | SYSCTL_RCC_USESYSDIV |
- SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS);
- ulRCC |= ulConfig & (SYSCTL_RCC_SYSDIV_M | SYSCTL_RCC_USESYSDIV |
- SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS);
- ulRCC2 &= ~(SYSCTL_RCC2_SYSDIV2_M);
- ulRCC2 |= ulConfig & SYSCTL_RCC2_SYSDIV2_M;
-
- //
- // See if the PLL output is being used to clock the system.
- //
- if(!(ulConfig & SYSCTL_RCC_BYPASS))
- {
- //
- // Wait until the PLL has locked.
- //
- for(ulDelay = 32768; ulDelay > 0; ulDelay--)
- {
- if(HWREG(SYSCTL_RIS) & SYSCTL_INT_PLL_LOCK)
- {
- break;
- }
- }
-
- //
- // Enable use of the PLL.
- //
- ulRCC &= ~(SYSCTL_RCC_BYPASS);
- ulRCC2 &= ~(SYSCTL_RCC2_BYPASS2);
- }
-
- //
- // Write the final RCC value.
- //
- HWREG(SYSCTL_RCC) = ulRCC;
- HWREG(SYSCTL_RCC2) = ulRCC2;
-
- //
- // Delay for a little bit so that the system divider takes effect.
- //
- SysCtlDelay(16);
-}
-
-//*****************************************************************************
-//
-//! Gets the processor clock rate.
-//!
-//! This function determines the clock rate of the processor clock. This is
-//! also the clock rate of all the peripheral modules (with the exception of
-//! PWM, which has its own clock divider).
-//!
-//! \note This will not return accurate results if SysCtlClockSet() has not
-//! been called to configure the clocking of the device, or if the device is
-//! directly clocked from a crystal (or a clock source) that is not one of the
-//! supported crystal frequencies. In the later case, this function should be
-//! modified to directly return the correct system clock rate.
-//!
-//! \return The processor clock rate.
-//
-//*****************************************************************************
-unsigned long
-SysCtlClockGet(void)
-{
- unsigned long ulRCC, ulRCC2, ulPLL, ulClk;
-
- //
- // Read RCC and RCC2. For Sandstorm-class devices (which do not have
- // RCC2), the RCC2 read will return 0, which indicates that RCC2 is
- // disabled (since the SYSCTL_RCC2_USERCC2 bit is clear).
- //
- ulRCC = HWREG(SYSCTL_RCC);
- ulRCC2 = HWREG(SYSCTL_RCC2);
-
- //
- // Get the base clock rate.
- //
- switch((ulRCC2 & SYSCTL_RCC2_USERCC2) ?
- (ulRCC2 & SYSCTL_RCC2_OSCSRC2_M) :
- (ulRCC & SYSCTL_RCC_OSCSRC_M))
- {
- //
- // The main oscillator is the clock source. Determine its rate from
- // the crystal setting field.
- //
- case SYSCTL_RCC_OSCSRC_MAIN:
- {
- ulClk = g_pulXtals[(ulRCC & SYSCTL_RCC_XTAL_M) >>
- SYSCTL_RCC_XTAL_S];
- break;
- }
-
- //
- // The internal oscillator is the source clock.
- //
- case SYSCTL_RCC_OSCSRC_INT:
- {
- //
- // See if this is a Sandstorm-class or Fury-class device.
- //
- if(CLASS_IS_SANDSTORM)
- {
- //
- // The internal oscillator on a Sandstorm-class device is
- // 15 MHz +/- 50%.
- //
- ulClk = 15000000;
- }
- else
- {
- //
- // The internal oscillator on a Fury-class device is 12 MHz
- // +/- 30%.
- //
- ulClk = 12000000;
- }
- break;
- }
-
- //
- // The internal oscillator divided by four is the source clock.
- //
- case SYSCTL_RCC_OSCSRC_INT4:
- {
- //
- // See if this is a Sandstorm-class or Fury-class device.
- //
- if(CLASS_IS_SANDSTORM)
- {
- //
- // The internal oscillator on a Sandstorm-class device is
- // 15 MHz +/- 50%.
- //
- ulClk = 15000000 / 4;
- }
- else
- {
- //
- // The internal oscillator on a Fury-class device is 12 MHz
- // +/- 30%.
- //
- ulClk = 12000000 / 4;
- }
- break;
- }
-
- //
- // The internal 30 KHz oscillator is the source clock.
- //
- case SYSCTL_RCC_OSCSRC_30:
- {
- //
- // The internal 30 KHz oscillator has an accuracy of +/- 30%.
- //
- ulClk = 30000;
- break;
- }
-
- //
- // The 32 KHz clock from the hibernate module is the source clock.
- //
- case SYSCTL_RCC2_OSCSRC2_32:
- {
- ulClk = 32768;
- break;
- }
-
- //
- // An unknown setting, so return a zero clock (that is, an unknown
- // clock rate).
- //
- default:
- {
- return(0);
- }
- }
-
- //
- // See if the PLL is being used.
- //
- if(((ulRCC2 & SYSCTL_RCC2_USERCC2) && !(ulRCC2 & SYSCTL_RCC2_BYPASS2)) ||
- (!(ulRCC2 & SYSCTL_RCC2_USERCC2) && !(ulRCC & SYSCTL_RCC_BYPASS)))
- {
- //
- // Get the PLL configuration.
- //
- ulPLL = HWREG(SYSCTL_PLLCFG);
-
- //
- // See if this is a Sandstorm-class or Fury-class device.
- //
- if(CLASS_IS_SANDSTORM)
- {
- //
- // Compute the PLL output frequency based on its input frequency.
- // The formula for a Sandstorm-class devices is
- // "(xtal * (f + 2)) / (r + 2)".
- //
- ulClk = ((ulClk * (((ulPLL & SYSCTL_PLLCFG_F_M) >>
- SYSCTL_PLLCFG_F_S) + 2)) /
- (((ulPLL & SYSCTL_PLLCFG_R_M) >>
- SYSCTL_PLLCFG_R_S) + 2));
- }
- else
- {
- //
- // Compute the PLL output frequency based on its input frequency.
- // The formula for a Fury-class device is
- // "(xtal * f) / ((r + 1) * 2)".
- //
- ulClk = ((ulClk * ((ulPLL & SYSCTL_PLLCFG_F_M) >>
- SYSCTL_PLLCFG_F_S)) /
- ((((ulPLL & SYSCTL_PLLCFG_R_M) >>
- SYSCTL_PLLCFG_R_S) + 1) * 2));
- }
-
- //
- // See if the optional output divide by 2 is being used.
- //
- if(ulPLL & SYSCTL_PLLCFG_OD_2)
- {
- ulClk /= 2;
- }
-
- //
- // See if the optional output divide by 4 is being used.
- //
- if(ulPLL & SYSCTL_PLLCFG_OD_4)
- {
- ulClk /= 4;
- }
- }
-
- //
- // See if the system divider is being used.
- //
- if(ulRCC & SYSCTL_RCC_USESYSDIV)
- {
- //
- // Adjust the clock rate by the system clock divider.
- //
- if(ulRCC2 & SYSCTL_RCC2_USERCC2)
- {
- ulClk /= (((ulRCC2 & SYSCTL_RCC2_SYSDIV2_M) >>
- SYSCTL_RCC2_SYSDIV2_S) + 1);
- }
- else
- {
- ulClk /= (((ulRCC & SYSCTL_RCC_SYSDIV_M) >> SYSCTL_RCC_SYSDIV_S) +
- 1);
- }
- }
-
- //
- // Return the computed clock rate.
- //
- return(ulClk);
-}
-
-//*****************************************************************************
-//
-//! Sets the PWM clock configuration.
-//!
-//! \param ulConfig is the configuration for the PWM clock; it must be one of
-//! \b SYSCTL_PWMDIV_1, \b SYSCTL_PWMDIV_2, \b SYSCTL_PWMDIV_4,
-//! \b SYSCTL_PWMDIV_8, \b SYSCTL_PWMDIV_16, \b SYSCTL_PWMDIV_32, or
-//! \b SYSCTL_PWMDIV_64.
-//!
-//! This function sets the rate of the clock provided to the PWM module as a
-//! ratio of the processor clock. This clock is used by the PWM module to
-//! generate PWM signals; its rate forms the basis for all PWM signals.
-//!
-//! \note The clocking of the PWM is dependent upon the system clock rate as
-//! configured by SysCtlClockSet().
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SysCtlPWMClockSet(unsigned long ulConfig)
-{
- //
- // Check the arguments.
- //
- ASSERT((ulConfig == SYSCTL_PWMDIV_1) ||
- (ulConfig == SYSCTL_PWMDIV_2) ||
- (ulConfig == SYSCTL_PWMDIV_4) ||
- (ulConfig == SYSCTL_PWMDIV_8) ||
- (ulConfig == SYSCTL_PWMDIV_16) ||
- (ulConfig == SYSCTL_PWMDIV_32) ||
- (ulConfig == SYSCTL_PWMDIV_64));
-
- //
- // Check that there is a PWM block on this part.
- //
- ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_PWM);
-
- //
- // Set the PWM clock configuration into the run-mode clock configuration
- // register.
- //
- HWREG(SYSCTL_RCC) = ((HWREG(SYSCTL_RCC) &
- ~(SYSCTL_RCC_USEPWMDIV | SYSCTL_RCC_PWMDIV_M)) |
- ulConfig);
-}
-
-//*****************************************************************************
-//
-//! Gets the current PWM clock configuration.
-//!
-//! This function returns the current PWM clock configuration.
-//!
-//! \return Returns the current PWM clock configuration; will be one of
-//! \b SYSCTL_PWMDIV_1, \b SYSCTL_PWMDIV_2, \b SYSCTL_PWMDIV_4,
-//! \b SYSCTL_PWMDIV_8, \b SYSCTL_PWMDIV_16, \b SYSCTL_PWMDIV_32, or
-//! \b SYSCTL_PWMDIV_64.
-//
-//*****************************************************************************
-unsigned long
-SysCtlPWMClockGet(void)
-{
- //
- // Check that there is a PWM block on this part.
- //
- ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_PWM);
-
- //
- // Return the current PWM clock configuration. Make sure that
- // SYSCTL_PWMDIV_1 is returned in all cases where the divider is disabled.
- //
- if(!(HWREG(SYSCTL_RCC) & SYSCTL_RCC_USEPWMDIV))
- {
- //
- // The divider is not active so reflect this in the value we return.
- //
- return(SYSCTL_PWMDIV_1);
- }
- else
- {
- //
- // The divider is active so directly return the masked register value.
- //
- return(HWREG(SYSCTL_RCC) &
- (SYSCTL_RCC_USEPWMDIV | SYSCTL_RCC_PWMDIV_M));
- }
-}
-
-//*****************************************************************************
-//
-//! Sets the sample rate of the ADC.
-//!
-//! \param ulSpeed is the desired sample rate of the ADC; must be one of
-//! \b SYSCTL_ADCSPEED_1MSPS, \b SYSCTL_ADCSPEED_500KSPS,
-//! \b SYSCTL_ADCSPEED_250KSPS, or \b SYSCTL_ADCSPEED_125KSPS.
-//!
-//! This function sets the rate at which the ADC samples are captured by the
-//! ADC block. The sampling speed may be limited by the hardware, so the
-//! sample rate may end up being slower than requested. SysCtlADCSpeedGet()
-//! will return the actual speed in use.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SysCtlADCSpeedSet(unsigned long ulSpeed)
-{
- //
- // Check the arguments.
- //
- ASSERT((ulSpeed == SYSCTL_ADCSPEED_1MSPS) ||
- (ulSpeed == SYSCTL_ADCSPEED_500KSPS) ||
- (ulSpeed == SYSCTL_ADCSPEED_250KSPS) ||
- (ulSpeed == SYSCTL_ADCSPEED_125KSPS));
-
- //
- // Check that there is an ADC block on this part.
- //
- ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_ADC);
-
- //
- // Set the ADC speed in run, sleep, and deep-sleep mode.
- //
- HWREG(SYSCTL_RCGC0) = ((HWREG(SYSCTL_RCGC0) & ~(SYSCTL_RCGC0_ADCSPD_M)) |
- ulSpeed);
- HWREG(SYSCTL_SCGC0) = ((HWREG(SYSCTL_SCGC0) & ~(SYSCTL_SCGC0_ADCSPD_M)) |
- ulSpeed);
- HWREG(SYSCTL_DCGC0) = ((HWREG(SYSCTL_DCGC0) & ~(SYSCTL_DCGC0_ADCSPD_M)) |
- ulSpeed);
-}
-
-//*****************************************************************************
-//
-//! Gets the sample rate of the ADC.
-//!
-//! This function gets the current sample rate of the ADC.
-//!
-//! \return Returns the current ADC sample rate; will be one of
-//! \b SYSCTL_ADCSPEED_1MSPS, \b SYSCTL_ADCSPEED_500KSPS,
-//! \b SYSCTL_ADCSPEED_250KSPS, or \b SYSCTL_ADCSPEED_125KSPS.
-//
-//*****************************************************************************
-unsigned long
-SysCtlADCSpeedGet(void)
-{
- //
- // Check that there is an ADC block on this part.
- //
- ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_ADC);
-
- //
- // Return the current ADC speed.
- //
- return(HWREG(SYSCTL_RCGC0) & SYSCTL_RCGC0_ADCSPD_M);
-}
-
-//*****************************************************************************
-//
-//! Configures the internal oscillator verification timer.
-//!
-//! \param bEnable is a boolean that is \b true if the internal oscillator
-//! verification timer should be enabled.
-//!
-//! This function allows the internal oscillator verification timer to be
-//! enabled or disabled. When enabled, an interrupt will be generated if the
-//! internal oscillator ceases to operate.
-//!
-//! The internal oscillator verification timer is only available on
-//! Sandstorm-class devices.
-//!
-//! \note Both oscillators (main and internal) must be enabled for this
-//! verification timer to operate as the main oscillator will verify the
-//! internal oscillator.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SysCtlIOSCVerificationSet(tBoolean bEnable)
-{
- //
- // Enable or disable the internal oscillator verification timer as
- // requested.
- //
- if(bEnable)
- {
- HWREG(SYSCTL_RCC) |= SYSCTL_RCC_IOSCVER;
- }
- else
- {
- HWREG(SYSCTL_RCC) &= ~(SYSCTL_RCC_IOSCVER);
- }
-}
-
-//*****************************************************************************
-//
-//! Configures the main oscillator verification timer.
-//!
-//! \param bEnable is a boolean that is \b true if the main oscillator
-//! verification timer should be enabled.
-//!
-//! This function allows the main oscillator verification timer to be enabled
-//! or disabled. When enabled, an interrupt will be generated if the main
-//! oscillator ceases to operate.
-//!
-//! The main oscillator verification timer is only available on
-//! Sandstorm-class devices.
-//!
-//! \note Both oscillators (main and internal) must be enabled for this
-//! verification timer to operate as the internal oscillator will verify the
-//! main oscillator.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SysCtlMOSCVerificationSet(tBoolean bEnable)
-{
- //
- // Enable or disable the main oscillator verification timer as requested.
- //
- if(bEnable)
- {
- HWREG(SYSCTL_RCC) |= SYSCTL_RCC_MOSCVER;
- }
- else
- {
- HWREG(SYSCTL_RCC) &= ~(SYSCTL_RCC_MOSCVER);
- }
-}
-
-//*****************************************************************************
-//
-//! Configures the PLL verification timer.
-//!
-//! \param bEnable is a boolean that is \b true if the PLL verification timer
-//! should be enabled.
-//!
-//! This function allows the PLL verification timer to be enabled or disabled.
-//! When enabled, an interrupt will be generated if the PLL ceases to operate.
-//!
-//! The PLL verification timer is only available on Sandstorm-class devices.
-//!
-//! \note The main oscillator must be enabled for this verification timer to
-//! operate as it is used to check the PLL. Also, the verification timer
-//! should be disabled while the PLL is being reconfigured via
-//! SysCtlClockSet().
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SysCtlPLLVerificationSet(tBoolean bEnable)
-{
- //
- // Enable or disable the PLL verification timer as requested.
- //
- if(bEnable)
- {
- HWREG(SYSCTL_RCC) |= SYSCTL_RCC_PLLVER;
- }
- else
- {
- HWREG(SYSCTL_RCC) &= ~(SYSCTL_RCC_PLLVER);
- }
-}
-
-//*****************************************************************************
-//
-//! Clears the clock verification status.
-//!
-//! This function clears the status of the clock verification timers, allowing
-//! them to assert another failure if detected.
-//!
-//! The clock verification timers are only available on Sandstorm-class
-//! devices.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SysCtlClkVerificationClear(void)
-{
- //
- // Clear the clock verification.
- //
- HWREG(SYSCTL_CLKVCLR) = SYSCTL_CLKVCLR_VERCLR;
-
- //
- // The bit does not self-reset, so clear it.
- //
- HWREG(SYSCTL_CLKVCLR) = 0;
-}
-
-//*****************************************************************************
-//
-//! Enables a GPIO peripheral for access from the high speed bus.
-//!
-//! \param ulGPIOPeripheral is the GPIO peripheral to enable.
-//!
-//! This function is used to enable the specified GPIO peripherals to be
-//! accessed from the high speed bus instead of the peripheral bus. When
-//! a GPIO peripheral is enabled for high speed access, the \b _AHB_BASE
-//! form of the base address should be used for GPIO functions. For example,
-//! instead of using \b GPIO_PORTA_BASE as the base address for GPIO functions,
-//! use \b GPIO_PORTA_AHB_BASE instead.
-//!
-//! The \e ulGPIOPeripheral argument must be only one of the following values:
-//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC,
-//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF,
-//! \b SYSCTL_PERIPH_GPIOG, or \b SYSCTL_PERIPH_GPIOH.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SysCtlGPIOAHBEnable(unsigned long ulGPIOPeripheral)
-{
- //
- // Check the arguments.
- //
- ASSERT((ulGPIOPeripheral == SYSCTL_PERIPH_GPIOA) ||
- (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOB) ||
- (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOC) ||
- (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOD) ||
- (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOE) ||
- (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOF) ||
- (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOG) ||
- (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOH));
-
- //
- // Enable this GPIO for AHB access.
- //
- HWREG(SYSCTL_GPIOHSCTL) |= ulGPIOPeripheral & 0xFFFF;
-}
-
-//*****************************************************************************
-//
-//! Disables a GPIO peripheral for access from the high speed bus.
-//!
-//! \param ulGPIOPeripheral is the GPIO peripheral to disable.
-//!
-//! This function will disable the specified GPIO peripherals for access
-//! from the high speed bus. Once disabled, the GPIO peripheral is accessed
-//! from the peripheral bus.
-//!
-//! The \b ulGPIOPeripheral argument must be only one of the following values:
-//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC,
-//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF,
-//! \b SYSCTL_PERIPH_GPIOG, or \b SYSCTL_PERIPH_GPIOH.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SysCtlGPIOAHBDisable(unsigned long ulGPIOPeripheral)
-{
- //
- // Check the arguments.
- //
- ASSERT((ulGPIOPeripheral == SYSCTL_PERIPH_GPIOA) ||
- (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOB) ||
- (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOC) ||
- (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOD) ||
- (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOE) ||
- (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOF) ||
- (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOG) ||
- (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOH));
-
- //
- // Disable this GPIO for AHB access.
- //
- HWREG(SYSCTL_GPIOHSCTL) &= ~(ulGPIOPeripheral & 0xFFFF);
-}
-
-//*****************************************************************************
-//
-//! Powers up the USB PLL.
-//!
-//! This function will enable the USB controller's PLL which is used by it's
-//! physical layer. This call is necessary before connecting to any external
-//! devices.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SysCtlUSBPLLEnable(void)
-{
- //
- // Turn on the USB PLL.
- //
- HWREG(SYSCTL_RCC2) &= ~SYSCTL_RCC2_USBPWRDN;
-}
-
-//*****************************************************************************
-//
-//! Powers down the USB PLL.
-//!
-//! This function will disable the USB controller's PLL which is used by it's
-//! physical layer. The USB registers are still accessible, but the physical
-//! layer will no longer function.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SysCtlUSBPLLDisable(void)
-{
- //
- // Turn of USB PLL.
- //
- HWREG(SYSCTL_RCC2) |= SYSCTL_RCC2_USBPWRDN;
-}
-
-//*****************************************************************************
-//
-// Close the Doxygen group.
-//! @}
-//
-//*****************************************************************************
+//*****************************************************************************
+//
+// sysctl.c - Driver for the system controller.
+//
+// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup sysctl_api
+//! @{
+//
+//*****************************************************************************
+
+#include "hw_ints.h"
+#include "hw_nvic.h"
+#include "hw_sysctl.h"
+#include "hw_types.h"
+#include "cpu.h"
+#include "debug.h"
+#include "interrupt.h"
+#include "sysctl.h"
+
+//*****************************************************************************
+//
+// This macro extracts the array index out of the peripheral number.
+//
+//*****************************************************************************
+#define SYSCTL_PERIPH_INDEX(a) (((a) >> 28) & 0xf)
+
+//*****************************************************************************
+//
+// This macro constructs the peripheral bit mask from the peripheral number.
+//
+//*****************************************************************************
+#define SYSCTL_PERIPH_MASK(a) (((a) & 0xffff) << (((a) & 0x001f0000) >> 16))
+
+//*****************************************************************************
+//
+// An array that maps the "peripheral set" number (which is stored in the upper
+// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL DC? register that
+// contains the peripheral present bit for that peripheral.
+//
+//*****************************************************************************
+static const unsigned long g_pulDCRegs[] =
+{
+ SYSCTL_DC1,
+ SYSCTL_DC2,
+ SYSCTL_DC4,
+ SYSCTL_DC1
+};
+
+//*****************************************************************************
+//
+// An array that maps the "peripheral set" number (which is stored in the upper
+// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL_SRCR? register that
+// controls the software reset for that peripheral.
+//
+//*****************************************************************************
+static const unsigned long g_pulSRCRRegs[] =
+{
+ SYSCTL_SRCR0,
+ SYSCTL_SRCR1,
+ SYSCTL_SRCR2
+};
+
+//*****************************************************************************
+//
+// An array that maps the "peripheral set" number (which is stored in the upper
+// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL_RCGC? register that
+// controls the run-mode enable for that peripheral.
+//
+//*****************************************************************************
+static const unsigned long g_pulRCGCRegs[] =
+{
+ SYSCTL_RCGC0,
+ SYSCTL_RCGC1,
+ SYSCTL_RCGC2
+};
+
+//*****************************************************************************
+//
+// An array that maps the "peripheral set" number (which is stored in the upper
+// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL_SCGC? register that
+// controls the sleep-mode enable for that peripheral.
+//
+//*****************************************************************************
+static const unsigned long g_pulSCGCRegs[] =
+{
+ SYSCTL_SCGC0,
+ SYSCTL_SCGC1,
+ SYSCTL_SCGC2
+};
+
+//*****************************************************************************
+//
+// An array that maps the "peripheral set" number (which is stored in the upper
+// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL_DCGC? register that
+// controls the deep-sleep-mode enable for that peripheral.
+//
+//*****************************************************************************
+static const unsigned long g_pulDCGCRegs[] =
+{
+ SYSCTL_DCGC0,
+ SYSCTL_DCGC1,
+ SYSCTL_DCGC2
+};
+
+//*****************************************************************************
+//
+// An array that maps the crystal number in RCC to a frequency.
+//
+//*****************************************************************************
+static const unsigned long g_pulXtals[] =
+{
+ 1000000,
+ 1843200,
+ 2000000,
+ 2457600,
+ 3579545,
+ 3686400,
+ 4000000,
+ 4096000,
+ 4915200,
+ 5000000,
+ 5120000,
+ 6000000,
+ 6144000,
+ 7372800,
+ 8000000,
+ 8192000,
+ 10000000,
+ 12000000,
+ 12288000,
+ 13560000,
+ 14318180,
+ 16000000,
+ 16384000
+};
+
+//*****************************************************************************
+//
+//! \internal
+//! Checks a peripheral identifier.
+//!
+//! \param ulPeripheral is the peripheral identifier.
+//!
+//! This function determines if a peripheral identifier is valid.
+//!
+//! \return Returns \b true if the peripheral identifier is valid and \b false
+//! otherwise.
+//
+//*****************************************************************************
+#ifdef DEBUG
+static tBoolean
+SysCtlPeripheralValid(unsigned long ulPeripheral)
+{
+ return((ulPeripheral == SYSCTL_PERIPH_ADC0) ||
+ (ulPeripheral == SYSCTL_PERIPH_ADC1) ||
+ (ulPeripheral == SYSCTL_PERIPH_CAN0) ||
+ (ulPeripheral == SYSCTL_PERIPH_CAN1) ||
+ (ulPeripheral == SYSCTL_PERIPH_CAN2) ||
+ (ulPeripheral == SYSCTL_PERIPH_COMP0) ||
+ (ulPeripheral == SYSCTL_PERIPH_COMP1) ||
+ (ulPeripheral == SYSCTL_PERIPH_COMP2) ||
+ (ulPeripheral == SYSCTL_PERIPH_EPI0) ||
+ (ulPeripheral == SYSCTL_PERIPH_ETH) ||
+ (ulPeripheral == SYSCTL_PERIPH_GPIOA) ||
+ (ulPeripheral == SYSCTL_PERIPH_GPIOB) ||
+ (ulPeripheral == SYSCTL_PERIPH_GPIOC) ||
+ (ulPeripheral == SYSCTL_PERIPH_GPIOD) ||
+ (ulPeripheral == SYSCTL_PERIPH_GPIOE) ||
+ (ulPeripheral == SYSCTL_PERIPH_GPIOF) ||
+ (ulPeripheral == SYSCTL_PERIPH_GPIOG) ||
+ (ulPeripheral == SYSCTL_PERIPH_GPIOH) ||
+ (ulPeripheral == SYSCTL_PERIPH_GPIOJ) ||
+ (ulPeripheral == SYSCTL_PERIPH_HIBERNATE) ||
+ (ulPeripheral == SYSCTL_PERIPH_I2C0) ||
+ (ulPeripheral == SYSCTL_PERIPH_I2C1) ||
+ (ulPeripheral == SYSCTL_PERIPH_I2S0) ||
+ (ulPeripheral == SYSCTL_PERIPH_IEEE1588) ||
+ (ulPeripheral == SYSCTL_PERIPH_MPU) ||
+ (ulPeripheral == SYSCTL_PERIPH_PLL) ||
+ (ulPeripheral == SYSCTL_PERIPH_PWM) ||
+ (ulPeripheral == SYSCTL_PERIPH_QEI0) ||
+ (ulPeripheral == SYSCTL_PERIPH_QEI1) ||
+ (ulPeripheral == SYSCTL_PERIPH_SSI0) ||
+ (ulPeripheral == SYSCTL_PERIPH_SSI1) ||
+ (ulPeripheral == SYSCTL_PERIPH_TEMP) ||
+ (ulPeripheral == SYSCTL_PERIPH_TIMER0) ||
+ (ulPeripheral == SYSCTL_PERIPH_TIMER1) ||
+ (ulPeripheral == SYSCTL_PERIPH_TIMER2) ||
+ (ulPeripheral == SYSCTL_PERIPH_TIMER3) ||
+ (ulPeripheral == SYSCTL_PERIPH_UART0) ||
+ (ulPeripheral == SYSCTL_PERIPH_UART1) ||
+ (ulPeripheral == SYSCTL_PERIPH_UART2) ||
+ (ulPeripheral == SYSCTL_PERIPH_UDMA) ||
+ (ulPeripheral == SYSCTL_PERIPH_USB0) ||
+ (ulPeripheral == SYSCTL_PERIPH_WDOG0) ||
+ (ulPeripheral == SYSCTL_PERIPH_WDOG1));
+}
+#endif
+
+//*****************************************************************************
+//
+//! Gets the size of the SRAM.
+//!
+//! This function determines the size of the SRAM on the Stellaris device.
+//!
+//! \return The total number of bytes of SRAM.
+//
+//*****************************************************************************
+unsigned long
+SysCtlSRAMSizeGet(void)
+{
+ //
+ // Compute the size of the SRAM.
+ //
+ return(((HWREG(SYSCTL_DC0) & SYSCTL_DC0_SRAMSZ_M) >> 8) + 0x100);
+}
+
+//*****************************************************************************
+//
+//! Gets the size of the flash.
+//!
+//! This function determines the size of the flash on the Stellaris device.
+//!
+//! \return The total number of bytes of flash.
+//
+//*****************************************************************************
+unsigned long
+SysCtlFlashSizeGet(void)
+{
+ //
+ // Compute the size of the flash.
+ //
+ return(((HWREG(SYSCTL_DC0) & SYSCTL_DC0_FLASHSZ_M) << 11) + 0x800);
+}
+
+//*****************************************************************************
+//
+//! Determines if a pin is present.
+//!
+//! \param ulPin is the pin in question.
+//!
+//! Determines if a particular pin is present in the device. The PWM, analog
+//! comparators, ADC, and timers have a varying number of pins across members
+//! of the Stellaris family; this will determine which are present on this
+//! device.
+//!
+//! The \e ulPin argument must be only one of the following values:
+//! \b SYSCTL_PIN_PWM0, \b SYSCTL_PIN_PWM1, \b SYSCTL_PIN_PWM2,
+//! \b SYSCTL_PIN_PWM3, \b SYSCTL_PIN_PWM4, \b SYSCTL_PIN_PWM5,
+//! \b SYSCTL_PIN_C0MINUS, \b SYSCTL_PIN_C0PLUS, \b SYSCTL_PIN_C0O,
+//! \b SYSCTL_PIN_C1MINUS, \b SYSCTL_PIN_C1PLUS, \b SYSCTL_PIN_C1O,
+//! \b SYSCTL_PIN_C2MINUS, \b SYSCTL_PIN_C2PLUS, \b SYSCTL_PIN_C2O,
+//! \b SYSCTL_PIN_ADC0, \b SYSCTL_PIN_ADC1, \b SYSCTL_PIN_ADC2,
+//! \b SYSCTL_PIN_ADC3, \b SYSCTL_PIN_ADC4, \b SYSCTL_PIN_ADC5,
+//! \b SYSCTL_PIN_ADC6, \b SYSCTL_PIN_ADC7, \b SYSCTL_PIN_CCP0,
+//! \b SYSCTL_PIN_CCP1, \b SYSCTL_PIN_CCP2, \b SYSCTL_PIN_CCP3,
+//! \b SYSCTL_PIN_CCP4, \b SYSCTL_PIN_CCP5, \b SYSCTL_PIN_CCP6,
+//! \b SYSCTL_PIN_CCP7, \b SYSCTL_PIN_32KHZ, or \b SYSCTL_PIN_MC_FAULT0.
+//!
+//! \return Returns \b true if the specified pin is present and \b false if it
+//! is not.
+//
+//*****************************************************************************
+tBoolean
+SysCtlPinPresent(unsigned long ulPin)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulPin == SYSCTL_PIN_PWM0) ||
+ (ulPin == SYSCTL_PIN_PWM1) ||
+ (ulPin == SYSCTL_PIN_PWM2) ||
+ (ulPin == SYSCTL_PIN_PWM3) ||
+ (ulPin == SYSCTL_PIN_PWM4) ||
+ (ulPin == SYSCTL_PIN_PWM5) ||
+ (ulPin == SYSCTL_PIN_C0MINUS) ||
+ (ulPin == SYSCTL_PIN_C0PLUS) ||
+ (ulPin == SYSCTL_PIN_C0O) ||
+ (ulPin == SYSCTL_PIN_C1MINUS) ||
+ (ulPin == SYSCTL_PIN_C1PLUS) ||
+ (ulPin == SYSCTL_PIN_C1O) ||
+ (ulPin == SYSCTL_PIN_C2MINUS) ||
+ (ulPin == SYSCTL_PIN_C2PLUS) ||
+ (ulPin == SYSCTL_PIN_C2O) ||
+ (ulPin == SYSCTL_PIN_MC_FAULT0) ||
+ (ulPin == SYSCTL_PIN_ADC0) ||
+ (ulPin == SYSCTL_PIN_ADC1) ||
+ (ulPin == SYSCTL_PIN_ADC2) ||
+ (ulPin == SYSCTL_PIN_ADC3) ||
+ (ulPin == SYSCTL_PIN_ADC4) ||
+ (ulPin == SYSCTL_PIN_ADC5) ||
+ (ulPin == SYSCTL_PIN_ADC6) ||
+ (ulPin == SYSCTL_PIN_ADC7) ||
+ (ulPin == SYSCTL_PIN_CCP0) ||
+ (ulPin == SYSCTL_PIN_CCP1) ||
+ (ulPin == SYSCTL_PIN_CCP2) ||
+ (ulPin == SYSCTL_PIN_CCP3) ||
+ (ulPin == SYSCTL_PIN_CCP4) ||
+ (ulPin == SYSCTL_PIN_CCP5) ||
+ (ulPin == SYSCTL_PIN_32KHZ));
+
+ //
+ // Determine if this pin is present.
+ //
+ if(HWREG(SYSCTL_DC3) & ulPin)
+ {
+ return(true);
+ }
+ else
+ {
+ return(false);
+ }
+}
+
+//*****************************************************************************
+//
+//! Determines if a peripheral is present.
+//!
+//! \param ulPeripheral is the peripheral in question.
+//!
+//! Determines if a particular peripheral is present in the device. Each
+//! member of the Stellaris family has a different peripheral set; this will
+//! determine which are present on this device.
+//!
+//! The \e ulPeripheral parameter must be only one of the following values:
+//! \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_CAN0, \b SYSCTL_PERIPH_CAN1,
+//! \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, \b SYSCTL_PERIPH_COMP1,
+//! \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA,
+//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD,
+//! \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG,
+//! \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
+//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_IEEE1588, \b SYSCTL_PERIPH_MPU,
+//! \b SYSCTL_PERIPH_PLL, \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_QEI0,
+//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1,
+//! \b SYSCTL_PERIPH_TEMP, \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1,
+//! \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_UART0,
+//! \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UDMA,
+//! \b SYSCTL_PERIPH_USB0, or \b SYSCTL_PERIPH_WDOG.
+//!
+//! \return Returns \b true if the specified peripheral is present and \b false
+//! if it is not.
+//
+//*****************************************************************************
+tBoolean
+SysCtlPeripheralPresent(unsigned long ulPeripheral)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(SysCtlPeripheralValid(ulPeripheral));
+
+ //
+ // Read the correct DC register and determine if this peripheral exists.
+ //
+ if(ulPeripheral == SYSCTL_PERIPH_USB0)
+ {
+ //
+ // USB is a special case since the DC bit is missing for USB0.
+ //
+ if(HWREG(SYSCTL_DC6) && SYSCTL_DC6_USB0_M)
+ {
+ return(true);
+ }
+ else
+ {
+ return(false);
+ }
+ }
+ else if(HWREG(g_pulDCRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) &
+ SYSCTL_PERIPH_MASK(ulPeripheral))
+ {
+ return(true);
+ }
+ else
+ {
+ return(false);
+ }
+}
+
+//*****************************************************************************
+//
+//! Performs a software reset of a peripheral.
+//!
+//! \param ulPeripheral is the peripheral to reset.
+//!
+//! This function performs a software reset of the specified peripheral. An
+//! individual peripheral reset signal is asserted for a brief period and then
+//! deasserted, leaving the peripheral in a operating state but in its reset
+//! condition.
+//!
+//! The \e ulPeripheral parameter must be only one of the following values:
+//! \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_CAN0, \b SYSCTL_PERIPH_CAN1,
+//! \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, \b SYSCTL_PERIPH_COMP1,
+//! \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA,
+//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD,
+//! \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG,
+//! \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
+//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_QEI0,
+//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1,
+//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2,
+//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1,
+//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, or
+//! \b SYSCTL_PERIPH_WDOG.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlPeripheralReset(unsigned long ulPeripheral)
+{
+ volatile unsigned long ulDelay;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(SysCtlPeripheralValid(ulPeripheral));
+
+ //
+ // Put the peripheral into the reset state.
+ //
+ HWREG(g_pulSRCRRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) |=
+ SYSCTL_PERIPH_MASK(ulPeripheral);
+
+ //
+ // Delay for a little bit.
+ //
+ for(ulDelay = 0; ulDelay < 16; ulDelay++)
+ {
+ }
+
+ //
+ // Take the peripheral out of the reset state.
+ //
+ HWREG(g_pulSRCRRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) &=
+ ~SYSCTL_PERIPH_MASK(ulPeripheral);
+}
+
+//*****************************************************************************
+//
+//! Enables a peripheral.
+//!
+//! \param ulPeripheral is the peripheral to enable.
+//!
+//! Peripherals are enabled with this function. At power-up, all peripherals
+//! are disabled; they must be enabled in order to operate or respond to
+//! register reads/writes.
+//!
+//! The \e ulPeripheral parameter must be only one of the following values:
+//! \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_CAN0, \b SYSCTL_PERIPH_CAN1,
+//! \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, \b SYSCTL_PERIPH_COMP1,
+//! \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA,
+//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD,
+//! \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG,
+//! \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
+//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_QEI0,
+//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1,
+//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2,
+//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1,
+//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, or
+//! \b SYSCTL_PERIPH_WDOG.
+//!
+//! \note It takes five clock cycles after the write to enable a peripheral
+//! before the the peripheral is actually enabled. During this time, attempts
+//! to access the peripheral will result in a bus fault. Care should be taken
+//! to ensure that the peripheral is not accessed during this brief time
+//! period.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlPeripheralEnable(unsigned long ulPeripheral)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(SysCtlPeripheralValid(ulPeripheral));
+
+ //
+ // Enable this peripheral.
+ //
+ HWREG(g_pulRCGCRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) |=
+ SYSCTL_PERIPH_MASK(ulPeripheral);
+}
+
+//*****************************************************************************
+//
+//! Disables a peripheral.
+//!
+//! \param ulPeripheral is the peripheral to disable.
+//!
+//! Peripherals are disabled with this function. Once disabled, they will not
+//! operate or respond to register reads/writes.
+//!
+//! The \e ulPeripheral parameter must be only one of the following values:
+//! \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_CAN0, \b SYSCTL_PERIPH_CAN1,
+//! \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, \b SYSCTL_PERIPH_COMP1,
+//! \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA,
+//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD,
+//! \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG,
+//! \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
+//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_QEI0,
+//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1,
+//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2,
+//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1,
+//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, or
+//! \b SYSCTL_PERIPH_WDOG.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlPeripheralDisable(unsigned long ulPeripheral)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(SysCtlPeripheralValid(ulPeripheral));
+
+ //
+ // Disable this peripheral.
+ //
+ HWREG(g_pulRCGCRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) &=
+ ~SYSCTL_PERIPH_MASK(ulPeripheral);
+}
+
+//*****************************************************************************
+//
+//! Enables a peripheral in sleep mode.
+//!
+//! \param ulPeripheral is the peripheral to enable in sleep mode.
+//!
+//! This function allows a peripheral to continue operating when the processor
+//! goes into sleep mode. Since the clocking configuration of the device does
+//! not change, any peripheral can safely continue operating while the
+//! processor is in sleep mode, and can therefore wake the processor from sleep
+//! mode.
+//!
+//! Sleep mode clocking of peripherals must be enabled via
+//! SysCtlPeripheralClockGating(); if disabled, the peripheral sleep mode
+//! configuration is maintained but has no effect when sleep mode is entered.
+//!
+//! The \e ulPeripheral parameter must be only one of the following values:
+//! \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_CAN0, \b SYSCTL_PERIPH_CAN1,
+//! \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, \b SYSCTL_PERIPH_COMP1,
+//! \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA,
+//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD,
+//! \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG,
+//! \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
+//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_QEI0,
+//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1,
+//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2,
+//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1,
+//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, or
+//! \b SYSCTL_PERIPH_WDOG.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlPeripheralSleepEnable(unsigned long ulPeripheral)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(SysCtlPeripheralValid(ulPeripheral));
+
+ //
+ // Enable this peripheral in sleep mode.
+ //
+ HWREG(g_pulSCGCRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) |=
+ SYSCTL_PERIPH_MASK(ulPeripheral);
+}
+
+//*****************************************************************************
+//
+//! Disables a peripheral in sleep mode.
+//!
+//! \param ulPeripheral is the peripheral to disable in sleep mode.
+//!
+//! This function causes a peripheral to stop operating when the processor goes
+//! into sleep mode. Disabling peripherals while in sleep mode helps to lower
+//! the current draw of the device. If enabled (via SysCtlPeripheralEnable()),
+//! the peripheral will automatically resume operation when the processor
+//! leaves sleep mode, maintaining its entire state from before sleep mode was
+//! entered.
+//!
+//! Sleep mode clocking of peripherals must be enabled via
+//! SysCtlPeripheralClockGating(); if disabled, the peripheral sleep mode
+//! configuration is maintained but has no effect when sleep mode is entered.
+//!
+//! The \e ulPeripheral parameter must be only one of the following values:
+//! \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_CAN0, \b SYSCTL_PERIPH_CAN1,
+//! \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, \b SYSCTL_PERIPH_COMP1,
+//! \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA,
+//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD,
+//! \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG,
+//! \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
+//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_QEI0,
+//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1,
+//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2,
+//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1,
+//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, or
+//! \b SYSCTL_PERIPH_WDOG.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlPeripheralSleepDisable(unsigned long ulPeripheral)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(SysCtlPeripheralValid(ulPeripheral));
+
+ //
+ // Disable this peripheral in sleep mode.
+ //
+ HWREG(g_pulSCGCRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) &=
+ ~SYSCTL_PERIPH_MASK(ulPeripheral);
+}
+
+//*****************************************************************************
+//
+//! Enables a peripheral in deep-sleep mode.
+//!
+//! \param ulPeripheral is the peripheral to enable in deep-sleep mode.
+//!
+//! This function allows a peripheral to continue operating when the processor
+//! goes into deep-sleep mode. Since the clocking configuration of the device
+//! may change, not all peripherals can safely continue operating while the
+//! processor is in sleep mode. Those that must run at a particular frequency
+//! (such as a UART) will not work as expected if the clock changes. It is the
+//! responsibility of the caller to make sensible choices.
+//!
+//! Deep-sleep mode clocking of peripherals must be enabled via
+//! SysCtlPeripheralClockGating(); if disabled, the peripheral deep-sleep mode
+//! configuration is maintained but has no effect when deep-sleep mode is
+//! entered.
+//!
+//! The \e ulPeripheral parameter must be one of the following values:
+//! \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_CAN0, \b SYSCTL_PERIPH_CAN1,
+//! \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, \b SYSCTL_PERIPH_COMP1,
+//! \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA,
+//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD,
+//! \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG,
+//! \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
+//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_QEI0,
+//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1,
+//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2,
+//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1,
+//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, or
+//! \b SYSCTL_PERIPH_WDOG.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(SysCtlPeripheralValid(ulPeripheral));
+
+ //
+ // Enable this peripheral in deep-sleep mode.
+ //
+ HWREG(g_pulDCGCRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) |=
+ SYSCTL_PERIPH_MASK(ulPeripheral);
+}
+
+//*****************************************************************************
+//
+//! Disables a peripheral in deep-sleep mode.
+//!
+//! \param ulPeripheral is the peripheral to disable in deep-sleep mode.
+//!
+//! This function causes a peripheral to stop operating when the processor goes
+//! into deep-sleep mode. Disabling peripherals while in deep-sleep mode helps
+//! to lower the current draw of the device, and can keep peripherals that
+//! require a particular clock frequency from operating when the clock changes
+//! as a result of entering deep-sleep mode. If enabled (via
+//! SysCtlPeripheralEnable()), the peripheral will automatically resume
+//! operation when the processor leaves deep-sleep mode, maintaining its entire
+//! state from before deep-sleep mode was entered.
+//!
+//! Deep-sleep mode clocking of peripherals must be enabled via
+//! SysCtlPeripheralClockGating(); if disabled, the peripheral deep-sleep mode
+//! configuration is maintained but has no effect when deep-sleep mode is
+//! entered.
+//!
+//! The \e ulPeripheral parameter must be one of the following values:
+//! \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_CAN0, \b SYSCTL_PERIPH_CAN1,
+//! \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, \b SYSCTL_PERIPH_COMP1,
+//! \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA,
+//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD,
+//! \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG,
+//! \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
+//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_QEI0,
+//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1,
+//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2,
+//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1,
+//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, or
+//! \b SYSCTL_PERIPH_WDOG.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(SysCtlPeripheralValid(ulPeripheral));
+
+ //
+ // Disable this peripheral in deep-sleep mode.
+ //
+ HWREG(g_pulDCGCRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) &=
+ ~SYSCTL_PERIPH_MASK(ulPeripheral);
+}
+
+//*****************************************************************************
+//
+//! Controls peripheral clock gating in sleep and deep-sleep mode.
+//!
+//! \param bEnable is a boolean that is \b true if the sleep and deep-sleep
+//! peripheral configuration should be used and \b false if not.
+//!
+//! This function controls how peripherals are clocked when the processor goes
+//! into sleep or deep-sleep mode. By default, the peripherals are clocked the
+//! same as in run mode; if peripheral clock gating is enabled they are clocked
+//! according to the configuration set by SysCtlPeripheralSleepEnable(),
+//! SysCtlPeripheralSleepDisable(), SysCtlPeripheralDeepSleepEnable(), and
+//! SysCtlPeripheralDeepSleepDisable().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlPeripheralClockGating(tBoolean bEnable)
+{
+ //
+ // Enable peripheral clock gating as requested.
+ //
+ if(bEnable)
+ {
+ HWREG(SYSCTL_RCC) |= SYSCTL_RCC_ACG;
+ }
+ else
+ {
+ HWREG(SYSCTL_RCC) &= ~(SYSCTL_RCC_ACG);
+ }
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the system control interrupt.
+//!
+//! \param pfnHandler is a pointer to the function to be called when the system
+//! control interrupt occurs.
+//!
+//! This sets the handler to be called when a system control interrupt occurs.
+//! This will enable the global interrupt in the interrupt controller; specific
+//! system control interrupts must be enabled via SysCtlIntEnable(). It is the
+//! interrupt handler's responsibility to clear the interrupt source via
+//! SysCtlIntClear().
+//!
+//! System control can generate interrupts when the PLL achieves lock, if the
+//! internal LDO current limit is exceeded, if the internal oscillator fails,
+//! if the main oscillator fails, if the internal LDO output voltage droops too
+//! much, if the external voltage droops too much, or if the PLL fails.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlIntRegister(void (*pfnHandler)(void))
+{
+ //
+ // Register the interrupt handler, returning an error if an error occurs.
+ //
+ IntRegister(INT_SYSCTL, pfnHandler);
+
+ //
+ // Enable the system control interrupt.
+ //
+ IntEnable(INT_SYSCTL);
+}
+
+//*****************************************************************************
+//
+//! Unregisters the interrupt handler for the system control interrupt.
+//!
+//! This function will clear the handler to be called when a system control
+//! interrupt occurs. This will also mask off the interrupt in the interrupt
+//! controller so that the interrupt handler no longer is called.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlIntUnregister(void)
+{
+ //
+ // Disable the interrupt.
+ //
+ IntDisable(INT_SYSCTL);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(INT_SYSCTL);
+}
+
+//*****************************************************************************
+//
+//! Enables individual system control interrupt sources.
+//!
+//! \param ulInts is a bit mask of the interrupt sources to be enabled. Must
+//! be a logical OR of \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_CUR_LIMIT,
+//! \b SYSCTL_INT_IOSC_FAIL, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR,
+//! \b SYSCTL_INT_BOR, and/or \b SYSCTL_INT_PLL_FAIL.
+//!
+//! Enables the indicated system control interrupt sources. Only the sources
+//! that are enabled can be reflected to the processor interrupt; disabled
+//! sources have no effect on the processor.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlIntEnable(unsigned long ulInts)
+{
+ //
+ // Enable the specified interrupts.
+ //
+ HWREG(SYSCTL_IMC) |= ulInts;
+}
+
+//*****************************************************************************
+//
+//! Disables individual system control interrupt sources.
+//!
+//! \param ulInts is a bit mask of the interrupt sources to be disabled. Must
+//! be a logical OR of \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_CUR_LIMIT,
+//! \b SYSCTL_INT_IOSC_FAIL, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR,
+//! \b SYSCTL_INT_BOR, and/or \b SYSCTL_INT_PLL_FAIL.
+//!
+//! Disables the indicated system control interrupt sources. Only the sources
+//! that are enabled can be reflected to the processor interrupt; disabled
+//! sources have no effect on the processor.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlIntDisable(unsigned long ulInts)
+{
+ //
+ // Disable the specified interrupts.
+ //
+ HWREG(SYSCTL_IMC) &= ~(ulInts);
+}
+
+//*****************************************************************************
+//
+//! Clears system control interrupt sources.
+//!
+//! \param ulInts is a bit mask of the interrupt sources to be cleared. Must
+//! be a logical OR of \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_CUR_LIMIT,
+//! \b SYSCTL_INT_IOSC_FAIL, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR,
+//! \b SYSCTL_INT_BOR, and/or \b SYSCTL_INT_PLL_FAIL.
+//!
+//! The specified system control interrupt sources are cleared, so that they no
+//! longer assert. This must be done in the interrupt handler to keep it from
+//! being called again immediately upon exit.
+//!
+//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
+//! several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared. Failure to do so may result in the interrupt handler
+//! being immediately reentered (since NVIC still sees the interrupt source
+//! asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlIntClear(unsigned long ulInts)
+{
+ //
+ // Clear the requested interrupt sources.
+ //
+ HWREG(SYSCTL_MISC) = ulInts;
+}
+
+//*****************************************************************************
+//
+//! Gets the current interrupt status.
+//!
+//! \param bMasked is false if the raw interrupt status is required and true if
+//! the masked interrupt status is required.
+//!
+//! This returns the interrupt status for the system controller. Either the
+//! raw interrupt status or the status of interrupts that are allowed to
+//! reflect to the processor can be returned.
+//!
+//! \return The current interrupt status, enumerated as a bit field of
+//! \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_CUR_LIMIT, \b SYSCTL_INT_IOSC_FAIL,
+//! \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR, \b SYSCTL_INT_BOR, and
+//! \b SYSCTL_INT_PLL_FAIL.
+//
+//*****************************************************************************
+unsigned long
+SysCtlIntStatus(tBoolean bMasked)
+{
+ //
+ // Return either the interrupt status or the raw interrupt status as
+ // requested.
+ //
+ if(bMasked)
+ {
+ return(HWREG(SYSCTL_MISC));
+ }
+ else
+ {
+ return(HWREG(SYSCTL_RIS));
+ }
+}
+
+//*****************************************************************************
+//
+//! Sets the output voltage of the LDO.
+//!
+//! \param ulVoltage is the required output voltage from the LDO. Must be one
+//! of \b SYSCTL_LDO_2_25V, \b SYSCTL_LDO_2_30V, \b SYSCTL_LDO_2_35V,
+//! \b SYSCTL_LDO_2_40V, \b SYSCTL_LDO_2_45V, \b SYSCTL_LDO_2_50V,
+//! \b SYSCTL_LDO_2_55V, \b SYSCTL_LDO_2_60V, \b SYSCTL_LDO_2_65V,
+//! \b SYSCTL_LDO_2_70V, or \b SYSCTL_LDO_2_75V.
+//!
+//! This function sets the output voltage of the LDO. The default voltage is
+//! 2.5 V; it can be adjusted +/- 10%.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlLDOSet(unsigned long ulVoltage)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulVoltage == SYSCTL_LDO_2_25V) ||
+ (ulVoltage == SYSCTL_LDO_2_30V) ||
+ (ulVoltage == SYSCTL_LDO_2_35V) ||
+ (ulVoltage == SYSCTL_LDO_2_40V) ||
+ (ulVoltage == SYSCTL_LDO_2_45V) ||
+ (ulVoltage == SYSCTL_LDO_2_50V) ||
+ (ulVoltage == SYSCTL_LDO_2_55V) ||
+ (ulVoltage == SYSCTL_LDO_2_60V) ||
+ (ulVoltage == SYSCTL_LDO_2_65V) ||
+ (ulVoltage == SYSCTL_LDO_2_70V) ||
+ (ulVoltage == SYSCTL_LDO_2_75V));
+
+ //
+ // Set the LDO voltage to the requested value.
+ //
+ HWREG(SYSCTL_LDOPCTL) = ulVoltage;
+}
+
+//*****************************************************************************
+//
+//! Gets the output voltage of the LDO.
+//!
+//! This function determines the output voltage of the LDO, as specified by the
+//! control register.
+//!
+//! \return Returns the current voltage of the LDO; will be one of
+//! \b SYSCTL_LDO_2_25V, \b SYSCTL_LDO_2_30V, \b SYSCTL_LDO_2_35V,
+//! \b SYSCTL_LDO_2_40V, \b SYSCTL_LDO_2_45V, \b SYSCTL_LDO_2_50V,
+//! \b SYSCTL_LDO_2_55V, \b SYSCTL_LDO_2_60V, \b SYSCTL_LDO_2_65V,
+//! \b SYSCTL_LDO_2_70V, or \b SYSCTL_LDO_2_75V.
+//
+//*****************************************************************************
+unsigned long
+SysCtlLDOGet(void)
+{
+ //
+ // Return the LDO voltage setting.
+ //
+ return(HWREG(SYSCTL_LDOPCTL));
+}
+
+//*****************************************************************************
+//
+//! Configures the LDO failure control.
+//!
+//! \param ulConfig is the required LDO failure control setting; can be either
+//! \b SYSCTL_LDOCFG_ARST or \b SYSCTL_LDOCFG_NORST.
+//!
+//! This function allows the LDO to be configured to cause a processor reset
+//! when the output voltage becomes unregulated.
+//!
+//! The LDO failure control is only available on Sandstorm-class devices.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlLDOConfigSet(unsigned long ulConfig)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulConfig == SYSCTL_LDOCFG_ARST) ||
+ (ulConfig == SYSCTL_LDOCFG_NORST));
+
+ //
+ // Set the reset control as requested.
+ //
+ HWREG(SYSCTL_LDOARST) = ulConfig;
+}
+
+//*****************************************************************************
+//
+//! Resets the device.
+//!
+//! This function will perform a software reset of the entire device. The
+//! processor and all peripherals will be reset and all device registers will
+//! return to their default values (with the exception of the reset cause
+//! register, which will maintain its current value but have the software reset
+//! bit set as well).
+//!
+//! \return This function does not return.
+//
+//*****************************************************************************
+void
+SysCtlReset(void)
+{
+ //
+ // Perform a software reset request. This will cause the device to reset,
+ // no further code will be executed.
+ //
+ HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | NVIC_APINT_SYSRESETREQ;
+
+ //
+ // The device should have reset, so this should never be reached. Just in
+ // case, loop forever.
+ //
+ while(1)
+ {
+ }
+}
+
+//*****************************************************************************
+//
+//! Puts the processor into sleep mode.
+//!
+//! This function places the processor into sleep mode; it will not return
+//! until the processor returns to run mode. The peripherals that are enabled
+//! via SysCtlPeripheralSleepEnable() continue to operate and can wake up the
+//! processor (if automatic clock gating is enabled with
+//! SysCtlPeripheralClockGating(), otherwise all peripherals continue to
+//! operate).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlSleep(void)
+{
+ //
+ // Wait for an interrupt.
+ //
+ CPUwfi();
+}
+
+//*****************************************************************************
+//
+//! Puts the processor into deep-sleep mode.
+//!
+//! This function places the processor into deep-sleep mode; it will not return
+//! until the processor returns to run mode. The peripherals that are enabled
+//! via SysCtlPeripheralDeepSleepEnable() continue to operate and can wake up
+//! the processor (if automatic clock gating is enabled with
+//! SysCtlPeripheralClockGating(), otherwise all peripherals continue to
+//! operate).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlDeepSleep(void)
+{
+ //
+ // Enable deep-sleep.
+ //
+ HWREG(NVIC_SYS_CTRL) |= NVIC_SYS_CTRL_SLEEPDEEP;
+
+ //
+ // Wait for an interrupt.
+ //
+ CPUwfi();
+
+ //
+ // Disable deep-sleep so that a future sleep will work correctly.
+ //
+ HWREG(NVIC_SYS_CTRL) &= ~(NVIC_SYS_CTRL_SLEEPDEEP);
+}
+
+//*****************************************************************************
+//
+//! Gets the reason for a reset.
+//!
+//! This function will return the reason(s) for a reset. Since the reset
+//! reasons are sticky until either cleared by software or an external reset,
+//! multiple reset reasons may be returned if multiple resets have occurred.
+//! The reset reason will be a logical OR of \b SYSCTL_CAUSE_LDO,
+//! \b SYSCTL_CAUSE_SW, \b SYSCTL_CAUSE_WDOG, \b SYSCTL_CAUSE_BOR,
+//! \b SYSCTL_CAUSE_POR, and/or \b SYSCTL_CAUSE_EXT.
+//!
+//! \return Returns the reason(s) for a reset.
+//
+//*****************************************************************************
+unsigned long
+SysCtlResetCauseGet(void)
+{
+ //
+ // Return the reset reasons.
+ //
+ return(HWREG(SYSCTL_RESC));
+}
+
+//*****************************************************************************
+//
+//! Clears reset reasons.
+//!
+//! \param ulCauses are the reset causes to be cleared; must be a logical OR of
+//! \b SYSCTL_CAUSE_LDO, \b SYSCTL_CAUSE_SW, \b SYSCTL_CAUSE_WDOG,
+//! \b SYSCTL_CAUSE_BOR, \b SYSCTL_CAUSE_POR, and/or \b SYSCTL_CAUSE_EXT.
+//!
+//! This function clears the specified sticky reset reasons. Once cleared,
+//! another reset for the same reason can be detected, and a reset for a
+//! different reason can be distinguished (instead of having two reset causes
+//! set). If the reset reason is used by an application, all reset causes
+//! should be cleared after they are retrieved with SysCtlResetCauseGet().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlResetCauseClear(unsigned long ulCauses)
+{
+ //
+ // Clear the given reset reasons.
+ //
+ HWREG(SYSCTL_RESC) &= ~(ulCauses);
+}
+
+//*****************************************************************************
+//
+//! Configures the brown-out control.
+//!
+//! \param ulConfig is the desired configuration of the brown-out control.
+//! Must be the logical OR of \b SYSCTL_BOR_RESET and/or
+//! \b SYSCTL_BOR_RESAMPLE.
+//! \param ulDelay is the number of internal oscillator cycles to wait before
+//! resampling an asserted brown-out signal. This value only has meaning when
+//! \b SYSCTL_BOR_RESAMPLE is set and must be less than 8192.
+//!
+//! This function configures how the brown-out control operates. It can detect
+//! a brown-out by looking at only the brown-out output, or it can wait for it
+//! to be active for two consecutive samples separated by a configurable time.
+//! When it detects a brown-out condition, it can either reset the device or
+//! generate a processor interrupt.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlBrownOutConfigSet(unsigned long ulConfig, unsigned long ulDelay)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(!(ulConfig & ~(SYSCTL_BOR_RESET | SYSCTL_BOR_RESAMPLE)));
+ ASSERT(ulDelay < 8192);
+
+ //
+ // Configure the brown-out reset control.
+ //
+ HWREG(SYSCTL_PBORCTL) = (ulDelay << SYSCTL_PBORCTL_BORTIM_S) | ulConfig;
+}
+
+//*****************************************************************************
+//
+//! Provides a small delay.
+//!
+//! \param ulCount is the number of delay loop iterations to perform.
+//!
+//! This function provides a means of generating a constant length delay. It
+//! is written in assembly to keep the delay consistent across tool chains,
+//! avoiding the need to tune the delay based on the tool chain in use.
+//!
+//! The loop takes 3 cycles/loop.
+//!
+//! \return None.
+//
+//*****************************************************************************
+#if defined(ewarm) || defined(DOXYGEN)
+void
+SysCtlDelay(unsigned long ulCount)
+{
+ __asm(" subs r0, #1\n"
+ " bne.n SysCtlDelay\n"
+ " bx lr");
+}
+#endif
+#if defined(codered) || defined(gcc) || defined(sourcerygxx)
+void __attribute__((naked))
+SysCtlDelay(unsigned long ulCount)
+{
+ __asm(" subs r0, #1\n"
+ " bne SysCtlDelay\n"
+ " bx lr");
+}
+#endif
+#if defined(rvmdk) || defined(__ARMCC_VERSION)
+__asm void
+SysCtlDelay(unsigned long ulCount)
+{
+ subs r0, #1;
+ bne SysCtlDelay;
+ bx lr;
+}
+#endif
+
+//*****************************************************************************
+//
+//! Sets the clocking of the device.
+//!
+//! \param ulConfig is the required configuration of the device clocking.
+//!
+//! This function configures the clocking of the device. The input crystal
+//! frequency, oscillator to be used, use of the PLL, and the system clock
+//! divider are all configured with this function.
+//!
+//! The \e ulConfig parameter is the logical OR of several different values,
+//! many of which are grouped into sets where only one can be chosen.
+//!
+//! The system clock divider is chosen with one of the following values:
+//! \b SYSCTL_SYSDIV_1, \b SYSCTL_SYSDIV_2, \b SYSCTL_SYSDIV_3, ...
+//! \b SYSCTL_SYSDIV_64. Only \b SYSCTL_SYSDIV_1 through \b SYSCTL_SYSDIV_16
+//! are valid on Sandstorm-class devices.
+//!
+//! The use of the PLL is chosen with either \b SYSCTL_USE_PLL or
+//! \b SYSCTL_USE_OSC.
+//!
+//! The external crystal frequency is chosen with one of the following values:
+//! \b SYSCTL_XTAL_1MHZ, \b SYSCTL_XTAL_1_84MHZ, \b SYSCTL_XTAL_2MHZ,
+//! \b SYSCTL_XTAL_2_45MHZ, \b SYSCTL_XTAL_3_57MHZ, \b SYSCTL_XTAL_3_68MHZ,
+//! \b SYSCTL_XTAL_4MHZ, \b SYSCTL_XTAL_4_09MHZ, \b SYSCTL_XTAL_4_91MHZ,
+//! \b SYSCTL_XTAL_5MHZ, \b SYSCTL_XTAL_5_12MHZ, \b SYSCTL_XTAL_6MHZ,
+//! \b SYSCTL_XTAL_6_14MHZ, \b SYSCTL_XTAL_7_37MHZ, \b SYSCTL_XTAL_8MHZ,
+//! \b SYSCTL_XTAL_8_19MHZ, \b SYSCTL_XTAL_10MHZ, \b SYSCTL_XTAL_12MHZ,
+//! \b SYSCTL_XTAL_12_2MHZ, \b SYSCTL_XTAL_13_5MHZ, \b SYSCTL_XTAL_14_3MHZ,
+//! \b SYSCTL_XTAL_16MHZ, or \b SYSCTL_XTAL_16_3MHZ. Values below
+//! \b SYSCTL_XTAL_3_57MHZ are not valid when the PLL is in operation. On
+//! Sandstorm- and Fury-class devices, values above \b SYSCTL_XTAL_8_19MHZ are
+//! not valid.
+//!
+//! The oscillator source is chosen with one of the following values:
+//! \b SYSCTL_OSC_MAIN, \b SYSCTL_OSC_INT, \b SYSCTL_OSC_INT4,
+//! \b SYSCTL_OSC_INT30, or \b SYSCTL_OSC_EXT32. On Sandstorm-class devices,
+//! \b SYSCTL_OSC_INT30 and \b SYSCTL_OSC_EXT32 are not valid.
+//! \b SYSCTL_OSC_EXT32 is only available on devices with the hibernate module,
+//! and then only when the hibernate module has been enabled.
+//!
+//! The internal and main oscillators are disabled with the
+//! \b SYSCTL_INT_OSC_DIS and \b SYSCTL_MAIN_OSC_DIS flags, respectively.
+//! The external oscillator must be enabled in order to use an external clock
+//! source. Note that attempts to disable the oscillator used to clock the
+//! device will be prevented by the hardware.
+//!
+//! To clock the system from an external source (such as an external crystal
+//! oscillator), use \b SYSCTL_USE_OSC \b | \b SYSCTL_OSC_MAIN. To clock the
+//! system from the main oscillator, use \b SYSCTL_USE_OSC \b |
+//! \b SYSCTL_OSC_MAIN. To clock the system from the PLL, use
+//! \b SYSCTL_USE_PLL \b | \b SYSCTL_OSC_MAIN, and select the appropriate
+//! crystal with one of the \b SYSCTL_XTAL_xxx values.
+//!
+//! \note If selecting the PLL as the system clock source (that is, via
+//! \b SYSCTL_USE_PLL), this function will poll the PLL lock interrupt to
+//! determine when the PLL has locked. If an interrupt handler for the
+//! system control interrupt is in place, and it responds to and clears the
+//! PLL lock interrupt, this function will delay until its timeout has occurred
+//! instead of completing as soon as PLL lock is achieved.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlClockSet(unsigned long ulConfig)
+{
+ unsigned long ulDelay, ulRCC, ulRCC2;
+
+ //
+ // See if this is a Sandstorm-class device and clocking features from newer
+ // devices were requested.
+ //
+ if(CLASS_IS_SANDSTORM && (ulConfig & SYSCTL_RCC2_USERCC2))
+ {
+ //
+ // Return without changing the clocking since the requested
+ // configuration can not be achieved.
+ //
+ return;
+ }
+
+ //
+ // Get the current value of the RCC and RCC2 registers. If using a
+ // Sandstorm-class device, the RCC2 register will read back as zero and the
+ // writes to it from within this function will be ignored.
+ //
+ ulRCC = HWREG(SYSCTL_RCC);
+ ulRCC2 = HWREG(SYSCTL_RCC2);
+
+ //
+ // Bypass the PLL and system clock dividers for now.
+ //
+ ulRCC |= SYSCTL_RCC_BYPASS;
+ ulRCC &= ~(SYSCTL_RCC_USESYSDIV);
+ ulRCC2 |= SYSCTL_RCC2_BYPASS2;
+
+ //
+ // Write the new RCC value.
+ //
+ HWREG(SYSCTL_RCC) = ulRCC;
+ HWREG(SYSCTL_RCC2) = ulRCC2;
+
+ //
+ // See if either oscillator needs to be enabled.
+ //
+ if(((ulRCC & SYSCTL_RCC_IOSCDIS) && !(ulConfig & SYSCTL_RCC_IOSCDIS)) ||
+ ((ulRCC & SYSCTL_RCC_MOSCDIS) && !(ulConfig & SYSCTL_RCC_MOSCDIS)))
+ {
+ //
+ // Make sure that the required oscillators are enabled. For now, the
+ // previously enabled oscillators must be enabled along with the newly
+ // requested oscillators.
+ //
+ ulRCC &= (~(SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS) |
+ (ulConfig & (SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS)));
+
+ //
+ // Write the new RCC value.
+ //
+ HWREG(SYSCTL_RCC) = ulRCC;
+
+ //
+ // Wait for a bit, giving the oscillator time to stabilize. The number
+ // of iterations is adjusted based on the current clock source; a
+ // smaller number of iterations is required for slower clock rates.
+ //
+ if(((ulRCC2 & SYSCTL_RCC2_USERCC2) &&
+ (((ulRCC2 & SYSCTL_RCC2_OSCSRC2_M) == SYSCTL_RCC2_OSCSRC2_30) ||
+ ((ulRCC2 & SYSCTL_RCC2_OSCSRC2_M) == SYSCTL_RCC2_OSCSRC2_32))) ||
+ (!(ulRCC2 & SYSCTL_RCC2_USERCC2) &&
+ ((ulRCC & SYSCTL_RCC_OSCSRC_M) == SYSCTL_RCC_OSCSRC_30)))
+ {
+ //
+ // Delay for 4096 iterations.
+ //
+ SysCtlDelay(4096);
+ }
+ else
+ {
+ //
+ // Delay for 524,288 iterations.
+ //
+ SysCtlDelay(524288);
+ }
+ }
+
+ //
+ // Set the new crystal value, oscillator source, and PLL configuration.
+ // Since the OSCSRC2 field in RCC2 overlaps the XTAL field in RCC, the
+ // OSCSRC field has a special encoding within ulConfig to avoid the
+ // overlap.
+ //
+ ulRCC &= ~(SYSCTL_RCC_XTAL_M | SYSCTL_RCC_OSCSRC_M |
+ SYSCTL_RCC_PWRDN | SYSCTL_RCC_OEN);
+ ulRCC |= ulConfig & (SYSCTL_RCC_XTAL_M | SYSCTL_RCC_OSCSRC_M |
+ SYSCTL_RCC_PWRDN | SYSCTL_RCC_OEN);
+ ulRCC2 &= ~(SYSCTL_RCC2_USERCC2 | SYSCTL_RCC2_OSCSRC2_M |
+ SYSCTL_RCC2_PWRDN2);
+ ulRCC2 |= ulConfig & (SYSCTL_RCC2_USERCC2 | SYSCTL_RCC_OSCSRC_M |
+ SYSCTL_RCC2_PWRDN2);
+ ulRCC2 |= (ulConfig & 0x00000008) << 3;
+
+ //
+ // Clear the PLL lock interrupt.
+ //
+ HWREG(SYSCTL_MISC) = SYSCTL_INT_PLL_LOCK;
+
+ //
+ // Write the new RCC value.
+ //
+ if(ulRCC2 & SYSCTL_RCC2_USERCC2)
+ {
+ HWREG(SYSCTL_RCC2) = ulRCC2;
+ HWREG(SYSCTL_RCC) = ulRCC;
+ }
+ else
+ {
+ HWREG(SYSCTL_RCC) = ulRCC;
+ HWREG(SYSCTL_RCC2) = ulRCC2;
+ }
+
+ //
+ // Wait for a bit so that new crystal value and oscillator source can take
+ // effect.
+ //
+ SysCtlDelay(16);
+
+ //
+ // Set the requested system divider and disable the appropriate
+ // oscillators. This will not get written immediately.
+ //
+ ulRCC &= ~(SYSCTL_RCC_SYSDIV_M | SYSCTL_RCC_USESYSDIV |
+ SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS);
+ ulRCC |= ulConfig & (SYSCTL_RCC_SYSDIV_M | SYSCTL_RCC_USESYSDIV |
+ SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS);
+ ulRCC2 &= ~(SYSCTL_RCC2_SYSDIV2_M);
+ ulRCC2 |= ulConfig & SYSCTL_RCC2_SYSDIV2_M;
+ if(ulConfig & SYSCTL_RCC2_USEFRACT)
+ {
+ ulRCC |= SYSCTL_RCC_USESYSDIV;
+ ulRCC2 &= ~(SYSCTL_RCC_USESYSDIV);
+ ulRCC2 |= ulConfig & (SYSCTL_RCC2_USEFRACT | SYSCTL_RCC2_FRACT);
+ }
+ else
+ {
+ ulRCC2 &= ~(SYSCTL_RCC2_USEFRACT);
+ }
+
+ //
+ // See if the PLL output is being used to clock the system.
+ //
+ if(!(ulConfig & SYSCTL_RCC_BYPASS))
+ {
+ //
+ // Wait until the PLL has locked.
+ //
+ for(ulDelay = 32768; ulDelay > 0; ulDelay--)
+ {
+ if(HWREG(SYSCTL_RIS) & SYSCTL_INT_PLL_LOCK)
+ {
+ break;
+ }
+ }
+
+ //
+ // Enable use of the PLL.
+ //
+ ulRCC &= ~(SYSCTL_RCC_BYPASS);
+ ulRCC2 &= ~(SYSCTL_RCC2_BYPASS2);
+ }
+
+ //
+ // Write the final RCC value.
+ //
+ HWREG(SYSCTL_RCC) = ulRCC;
+ HWREG(SYSCTL_RCC2) = ulRCC2;
+
+ //
+ // Delay for a little bit so that the system divider takes effect.
+ //
+ SysCtlDelay(16);
+}
+
+//*****************************************************************************
+//
+//! Gets the processor clock rate.
+//!
+//! This function determines the clock rate of the processor clock. This is
+//! also the clock rate of all the peripheral modules (with the exception of
+//! PWM, which has its own clock divider).
+//!
+//! \note This will not return accurate results if SysCtlClockSet() has not
+//! been called to configure the clocking of the device, or if the device is
+//! directly clocked from a crystal (or a clock source) that is not one of the
+//! supported crystal frequencies. In the later case, this function should be
+//! modified to directly return the correct system clock rate.
+//!
+//! \return The processor clock rate.
+//
+//*****************************************************************************
+unsigned long
+SysCtlClockGet(void)
+{
+ unsigned long ulRCC, ulRCC2, ulPLL, ulClk;
+
+ //
+ // Read RCC and RCC2. For Sandstorm-class devices (which do not have
+ // RCC2), the RCC2 read will return 0, which indicates that RCC2 is
+ // disabled (since the SYSCTL_RCC2_USERCC2 bit is clear).
+ //
+ ulRCC = HWREG(SYSCTL_RCC);
+ ulRCC2 = HWREG(SYSCTL_RCC2);
+
+ //
+ // Get the base clock rate.
+ //
+ switch((ulRCC2 & SYSCTL_RCC2_USERCC2) ?
+ (ulRCC2 & SYSCTL_RCC2_OSCSRC2_M) :
+ (ulRCC & SYSCTL_RCC_OSCSRC_M))
+ {
+ //
+ // The main oscillator is the clock source. Determine its rate from
+ // the crystal setting field.
+ //
+ case SYSCTL_RCC_OSCSRC_MAIN:
+ {
+ ulClk = g_pulXtals[(ulRCC & SYSCTL_RCC_XTAL_M) >>
+ SYSCTL_RCC_XTAL_S];
+ break;
+ }
+
+ //
+ // The internal oscillator is the source clock.
+ //
+ case SYSCTL_RCC_OSCSRC_INT:
+ {
+ //
+ // See if this is a Sandstorm-class or Fury-class device.
+ //
+ if(CLASS_IS_SANDSTORM)
+ {
+ //
+ // The internal oscillator on a Sandstorm-class device is
+ // 15 MHz +/- 50%.
+ //
+ ulClk = 15000000;
+ }
+ else if((CLASS_IS_FURY && REVISION_IS_A2) ||
+ (CLASS_IS_DUSTDEVIL && REVISION_IS_A0))
+ {
+ //
+ // The internal oscillator on a rev A2 Fury-class device and a
+ // rev A0 Dustdevil-class device is 12 MHz +/- 30%.
+ //
+ ulClk = 12000000;
+ }
+ else
+ {
+ //
+ // The internal oscillator on all other devices is 16 MHz.
+ //
+ ulClk = 16000000;
+ }
+ break;
+ }
+
+ //
+ // The internal oscillator divided by four is the source clock.
+ //
+ case SYSCTL_RCC_OSCSRC_INT4:
+ {
+ //
+ // See if this is a Sandstorm-class or Fury-class device.
+ //
+ if(CLASS_IS_SANDSTORM)
+ {
+ //
+ // The internal oscillator on a Sandstorm-class device is
+ // 15 MHz +/- 50%.
+ //
+ ulClk = 15000000 / 4;
+ }
+ else if((CLASS_IS_FURY && REVISION_IS_A2) ||
+ (CLASS_IS_DUSTDEVIL && REVISION_IS_A0))
+ {
+ //
+ // The internal oscillator on a rev A2 Fury-class device and a
+ // rev A0 Dustdevil-class device is 12 MHz +/- 30%.
+ //
+ ulClk = 12000000 / 4;
+ }
+ else
+ {
+ //
+ // The internal oscillator on a Tempest-class device is 16 MHz.
+ //
+ ulClk = 16000000 / 4;
+ }
+ break;
+ }
+
+ //
+ // The internal 30 KHz oscillator is the source clock.
+ //
+ case SYSCTL_RCC_OSCSRC_30:
+ {
+ //
+ // The internal 30 KHz oscillator has an accuracy of +/- 30%.
+ //
+ ulClk = 30000;
+ break;
+ }
+
+ //
+ // The 4.19 MHz clock from the hibernate module is the clock source.
+ //
+ case SYSCTL_RCC2_OSCSRC2_419:
+ {
+ ulClk = 4194304;
+ break;
+ }
+
+ //
+ // The 32 KHz clock from the hibernate module is the source clock.
+ //
+ case SYSCTL_RCC2_OSCSRC2_32:
+ {
+ ulClk = 32768;
+ break;
+ }
+
+ //
+ // An unknown setting, so return a zero clock (that is, an unknown
+ // clock rate).
+ //
+ default:
+ {
+ return(0);
+ }
+ }
+
+ //
+ // See if the PLL is being used.
+ //
+ if(((ulRCC2 & SYSCTL_RCC2_USERCC2) && !(ulRCC2 & SYSCTL_RCC2_BYPASS2)) ||
+ (!(ulRCC2 & SYSCTL_RCC2_USERCC2) && !(ulRCC & SYSCTL_RCC_BYPASS)))
+ {
+ //
+ // Get the PLL configuration.
+ //
+ ulPLL = HWREG(SYSCTL_PLLCFG);
+
+ //
+ // See if this is a Sandstorm-class or Fury-class device.
+ //
+ if(CLASS_IS_SANDSTORM)
+ {
+ //
+ // Compute the PLL output frequency based on its input frequency.
+ // The formula for a Sandstorm-class devices is
+ // "(xtal * (f + 2)) / (r + 2)".
+ //
+ ulClk = ((ulClk * (((ulPLL & SYSCTL_PLLCFG_F_M) >>
+ SYSCTL_PLLCFG_F_S) + 2)) /
+ (((ulPLL & SYSCTL_PLLCFG_R_M) >>
+ SYSCTL_PLLCFG_R_S) + 2));
+ }
+ else
+ {
+ //
+ // Compute the PLL output frequency based on its input frequency.
+ // The formula for a Fury-class device is
+ // "(xtal * f) / ((r + 1) * 2)".
+ //
+ ulClk = ((ulClk * ((ulPLL & SYSCTL_PLLCFG_F_M) >>
+ SYSCTL_PLLCFG_F_S)) /
+ ((((ulPLL & SYSCTL_PLLCFG_R_M) >>
+ SYSCTL_PLLCFG_R_S) + 1) * 2));
+ }
+
+ //
+ // See if the optional output divide by 2 is being used.
+ //
+ if(ulPLL & SYSCTL_PLLCFG_OD_2)
+ {
+ ulClk /= 2;
+ }
+
+ //
+ // See if the optional output divide by 4 is being used.
+ //
+ if(ulPLL & SYSCTL_PLLCFG_OD_4)
+ {
+ ulClk /= 4;
+ }
+
+ //
+ // Force the system divider to be enabled. It is always used when
+ // using the PLL, but in some cases it will not read as being enabled.
+ //
+ ulRCC |= SYSCTL_RCC_USESYSDIV;
+ }
+
+ //
+ // See if the system divider is being used.
+ //
+ if(ulRCC & SYSCTL_RCC_USESYSDIV)
+ {
+ //
+ // Adjust the clock rate by the system clock divider.
+ //
+ if(ulRCC2 & SYSCTL_RCC2_USERCC2)
+ {
+ if((ulRCC2 & SYSCTL_RCC2_USEFRACT) &&
+ (((ulRCC2 & SYSCTL_RCC2_USERCC2) &&
+ !(ulRCC2 & SYSCTL_RCC2_BYPASS2)) ||
+ (!(ulRCC2 & SYSCTL_RCC2_USERCC2) &&
+ !(ulRCC & SYSCTL_RCC_BYPASS))))
+
+ {
+ ulClk = ((ulClk * 2) / (((ulRCC2 & (SYSCTL_RCC2_SYSDIV2_M |
+ SYSCTL_RCC2_FRACT)) >>
+ (SYSCTL_RCC2_SYSDIV2_S - 1)) + 1));
+ }
+ else
+ {
+ ulClk /= (((ulRCC2 & SYSCTL_RCC2_SYSDIV2_M) >>
+ SYSCTL_RCC2_SYSDIV2_S) + 1);
+ }
+ }
+ else
+ {
+ ulClk /= (((ulRCC & SYSCTL_RCC_SYSDIV_M) >> SYSCTL_RCC_SYSDIV_S) +
+ 1);
+ }
+ }
+
+ //
+ // Return the computed clock rate.
+ //
+ return(ulClk);
+}
+
+//*****************************************************************************
+//
+//! Sets the PWM clock configuration.
+//!
+//! \param ulConfig is the configuration for the PWM clock; it must be one of
+//! \b SYSCTL_PWMDIV_1, \b SYSCTL_PWMDIV_2, \b SYSCTL_PWMDIV_4,
+//! \b SYSCTL_PWMDIV_8, \b SYSCTL_PWMDIV_16, \b SYSCTL_PWMDIV_32, or
+//! \b SYSCTL_PWMDIV_64.
+//!
+//! This function sets the rate of the clock provided to the PWM module as a
+//! ratio of the processor clock. This clock is used by the PWM module to
+//! generate PWM signals; its rate forms the basis for all PWM signals.
+//!
+//! \note The clocking of the PWM is dependent upon the system clock rate as
+//! configured by SysCtlClockSet().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlPWMClockSet(unsigned long ulConfig)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulConfig == SYSCTL_PWMDIV_1) ||
+ (ulConfig == SYSCTL_PWMDIV_2) ||
+ (ulConfig == SYSCTL_PWMDIV_4) ||
+ (ulConfig == SYSCTL_PWMDIV_8) ||
+ (ulConfig == SYSCTL_PWMDIV_16) ||
+ (ulConfig == SYSCTL_PWMDIV_32) ||
+ (ulConfig == SYSCTL_PWMDIV_64));
+
+ //
+ // Check that there is a PWM block on this part.
+ //
+ ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_PWM);
+
+ //
+ // Set the PWM clock configuration into the run-mode clock configuration
+ // register.
+ //
+ HWREG(SYSCTL_RCC) = ((HWREG(SYSCTL_RCC) &
+ ~(SYSCTL_RCC_USEPWMDIV | SYSCTL_RCC_PWMDIV_M)) |
+ ulConfig);
+}
+
+//*****************************************************************************
+//
+//! Gets the current PWM clock configuration.
+//!
+//! This function returns the current PWM clock configuration.
+//!
+//! \return Returns the current PWM clock configuration; will be one of
+//! \b SYSCTL_PWMDIV_1, \b SYSCTL_PWMDIV_2, \b SYSCTL_PWMDIV_4,
+//! \b SYSCTL_PWMDIV_8, \b SYSCTL_PWMDIV_16, \b SYSCTL_PWMDIV_32, or
+//! \b SYSCTL_PWMDIV_64.
+//
+//*****************************************************************************
+unsigned long
+SysCtlPWMClockGet(void)
+{
+ //
+ // Check that there is a PWM block on this part.
+ //
+ ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_PWM);
+
+ //
+ // Return the current PWM clock configuration. Make sure that
+ // SYSCTL_PWMDIV_1 is returned in all cases where the divider is disabled.
+ //
+ if(!(HWREG(SYSCTL_RCC) & SYSCTL_RCC_USEPWMDIV))
+ {
+ //
+ // The divider is not active so reflect this in the value we return.
+ //
+ return(SYSCTL_PWMDIV_1);
+ }
+ else
+ {
+ //
+ // The divider is active so directly return the masked register value.
+ //
+ return(HWREG(SYSCTL_RCC) &
+ (SYSCTL_RCC_USEPWMDIV | SYSCTL_RCC_PWMDIV_M));
+ }
+}
+
+//*****************************************************************************
+//
+//! Sets the sample rate of the ADC.
+//!
+//! \param ulSpeed is the desired sample rate of the ADC; must be one of
+//! \b SYSCTL_ADCSPEED_1MSPS, \b SYSCTL_ADCSPEED_500KSPS,
+//! \b SYSCTL_ADCSPEED_250KSPS, or \b SYSCTL_ADCSPEED_125KSPS.
+//!
+//! This function sets the rate at which the ADC samples are captured by the
+//! ADC block. The sampling speed may be limited by the hardware, so the
+//! sample rate may end up being slower than requested. SysCtlADCSpeedGet()
+//! will return the actual speed in use.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlADCSpeedSet(unsigned long ulSpeed)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulSpeed == SYSCTL_ADCSPEED_1MSPS) ||
+ (ulSpeed == SYSCTL_ADCSPEED_500KSPS) ||
+ (ulSpeed == SYSCTL_ADCSPEED_250KSPS) ||
+ (ulSpeed == SYSCTL_ADCSPEED_125KSPS));
+
+ //
+ // Check that there is an ADC block on this part.
+ //
+ ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_ADC0);
+
+ //
+ // Set the ADC speed in run, sleep, and deep-sleep mode.
+ //
+ HWREG(SYSCTL_RCGC0) = ((HWREG(SYSCTL_RCGC0) & ~(SYSCTL_RCGC0_ADCSPD_M)) |
+ ulSpeed);
+ HWREG(SYSCTL_SCGC0) = ((HWREG(SYSCTL_SCGC0) & ~(SYSCTL_SCGC0_ADCSPD_M)) |
+ ulSpeed);
+ HWREG(SYSCTL_DCGC0) = ((HWREG(SYSCTL_DCGC0) & ~(SYSCTL_DCGC0_ADCSPD_M)) |
+ ulSpeed);
+}
+
+//*****************************************************************************
+//
+//! Gets the sample rate of the ADC.
+//!
+//! This function gets the current sample rate of the ADC.
+//!
+//! \return Returns the current ADC sample rate; will be one of
+//! \b SYSCTL_ADCSPEED_1MSPS, \b SYSCTL_ADCSPEED_500KSPS,
+//! \b SYSCTL_ADCSPEED_250KSPS, or \b SYSCTL_ADCSPEED_125KSPS.
+//
+//*****************************************************************************
+unsigned long
+SysCtlADCSpeedGet(void)
+{
+ //
+ // Check that there is an ADC block on this part.
+ //
+ ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_ADC0);
+
+ //
+ // Return the current ADC speed.
+ //
+ return(HWREG(SYSCTL_RCGC0) & SYSCTL_RCGC0_ADCSPD_M);
+}
+
+//*****************************************************************************
+//
+//! Configures the internal oscillator verification timer.
+//!
+//! \param bEnable is a boolean that is \b true if the internal oscillator
+//! verification timer should be enabled.
+//!
+//! This function allows the internal oscillator verification timer to be
+//! enabled or disabled. When enabled, an interrupt will be generated if the
+//! internal oscillator ceases to operate.
+//!
+//! The internal oscillator verification timer is only available on
+//! Sandstorm-class devices.
+//!
+//! \note Both oscillators (main and internal) must be enabled for this
+//! verification timer to operate as the main oscillator will verify the
+//! internal oscillator.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlIOSCVerificationSet(tBoolean bEnable)
+{
+ //
+ // Enable or disable the internal oscillator verification timer as
+ // requested.
+ //
+ if(bEnable)
+ {
+ HWREG(SYSCTL_RCC) |= SYSCTL_RCC_IOSCVER;
+ }
+ else
+ {
+ HWREG(SYSCTL_RCC) &= ~(SYSCTL_RCC_IOSCVER);
+ }
+}
+
+//*****************************************************************************
+//
+//! Configures the main oscillator verification timer.
+//!
+//! \param bEnable is a boolean that is \b true if the main oscillator
+//! verification timer should be enabled.
+//!
+//! This function allows the main oscillator verification timer to be enabled
+//! or disabled. When enabled, an interrupt will be generated if the main
+//! oscillator ceases to operate.
+//!
+//! The main oscillator verification timer is only available on
+//! Sandstorm-class devices.
+//!
+//! \note Both oscillators (main and internal) must be enabled for this
+//! verification timer to operate as the internal oscillator will verify the
+//! main oscillator.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlMOSCVerificationSet(tBoolean bEnable)
+{
+ //
+ // Enable or disable the main oscillator verification timer as requested.
+ //
+ if(bEnable)
+ {
+ HWREG(SYSCTL_RCC) |= SYSCTL_RCC_MOSCVER;
+ }
+ else
+ {
+ HWREG(SYSCTL_RCC) &= ~(SYSCTL_RCC_MOSCVER);
+ }
+}
+
+//*****************************************************************************
+//
+//! Configures the PLL verification timer.
+//!
+//! \param bEnable is a boolean that is \b true if the PLL verification timer
+//! should be enabled.
+//!
+//! This function allows the PLL verification timer to be enabled or disabled.
+//! When enabled, an interrupt will be generated if the PLL ceases to operate.
+//!
+//! The PLL verification timer is only available on Sandstorm-class devices.
+//!
+//! \note The main oscillator must be enabled for this verification timer to
+//! operate as it is used to check the PLL. Also, the verification timer
+//! should be disabled while the PLL is being reconfigured via
+//! SysCtlClockSet().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlPLLVerificationSet(tBoolean bEnable)
+{
+ //
+ // Enable or disable the PLL verification timer as requested.
+ //
+ if(bEnable)
+ {
+ HWREG(SYSCTL_RCC) |= SYSCTL_RCC_PLLVER;
+ }
+ else
+ {
+ HWREG(SYSCTL_RCC) &= ~(SYSCTL_RCC_PLLVER);
+ }
+}
+
+//*****************************************************************************
+//
+//! Clears the clock verification status.
+//!
+//! This function clears the status of the clock verification timers, allowing
+//! them to assert another failure if detected.
+//!
+//! The clock verification timers are only available on Sandstorm-class
+//! devices.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlClkVerificationClear(void)
+{
+ //
+ // Clear the clock verification.
+ //
+ HWREG(SYSCTL_CLKVCLR) = SYSCTL_CLKVCLR_VERCLR;
+
+ //
+ // The bit does not self-reset, so clear it.
+ //
+ HWREG(SYSCTL_CLKVCLR) = 0;
+}
+
+//*****************************************************************************
+//
+//! Enables a GPIO peripheral for access from the AHB.
+//!
+//! \param ulGPIOPeripheral is the GPIO peripheral to enable.
+//!
+//! This function is used to enable the specified GPIO peripheral to be
+//! accessed from the Advanced Host Bus (AHB) instead of the legacy Advanced
+//! Peripheral Bus (APB). When a GPIO peripheral is enabled for AHB access,
+//! the \b _AHB_BASE form of the base address should be used for GPIO
+//! functions. For example, instead of using \b GPIO_PORTA_BASE as the base
+//! address for GPIO functions, use \b GPIO_PORTA_AHB_BASE instead.
+//!
+//! The \e ulGPIOPeripheral argument must be only one of the following values:
+//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC,
+//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF,
+//! \b SYSCTL_PERIPH_GPIOG, or \b SYSCTL_PERIPH_GPIOH.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlGPIOAHBEnable(unsigned long ulGPIOPeripheral)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulGPIOPeripheral == SYSCTL_PERIPH_GPIOA) ||
+ (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOB) ||
+ (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOC) ||
+ (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOD) ||
+ (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOE) ||
+ (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOF) ||
+ (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOG) ||
+ (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOH) ||
+ (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOJ));
+
+ //
+ // Enable this GPIO for AHB access.
+ //
+ HWREG(SYSCTL_GPIOHSCTL) |= ulGPIOPeripheral & 0xFFFF;
+}
+
+//*****************************************************************************
+//
+//! Disables a GPIO peripheral for access from the AHB.
+//!
+//! \param ulGPIOPeripheral is the GPIO peripheral to disable.
+//!
+//! This function disables the specified GPIO peripheral for access from the
+//! Advanced Host Bus (AHB). Once disabled, the GPIO peripheral is accessed
+//! from the legacy Advanced Peripheral Bus (AHB).
+//!
+//! The \b ulGPIOPeripheral argument must be only one of the following values:
+//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC,
+//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF,
+//! \b SYSCTL_PERIPH_GPIOG, or \b SYSCTL_PERIPH_GPIOH.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlGPIOAHBDisable(unsigned long ulGPIOPeripheral)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulGPIOPeripheral == SYSCTL_PERIPH_GPIOA) ||
+ (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOB) ||
+ (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOC) ||
+ (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOD) ||
+ (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOE) ||
+ (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOF) ||
+ (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOG) ||
+ (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOH) ||
+ (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOJ));
+
+ //
+ // Disable this GPIO for AHB access.
+ //
+ HWREG(SYSCTL_GPIOHSCTL) &= ~(ulGPIOPeripheral & 0xFFFF);
+}
+
+//*****************************************************************************
+//
+//! Powers up the USB PLL.
+//!
+//! This function will enable the USB controller's PLL which is used by it's
+//! physical layer. This call is necessary before connecting to any external
+//! devices.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlUSBPLLEnable(void)
+{
+ //
+ // Turn on the USB PLL.
+ //
+ HWREG(SYSCTL_RCC2) &= ~SYSCTL_RCC2_USBPWRDN;
+}
+
+//*****************************************************************************
+//
+//! Powers down the USB PLL.
+//!
+//! This function will disable the USB controller's PLL which is used by it's
+//! physical layer. The USB registers are still accessible, but the physical
+//! layer will no longer function.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlUSBPLLDisable(void)
+{
+ //
+ // Turn of USB PLL.
+ //
+ HWREG(SYSCTL_RCC2) |= SYSCTL_RCC2_USBPWRDN;
+}
+
+//*****************************************************************************
+//
+//! Sets the MCLK frequency provided to the I2S module.
+//!
+//! \param ulInputClock is the input clock to the MCLK divider. If this is
+//! zero, the value is computed from the current PLL configuration.
+//! \param ulMClk is the desired MCLK frequency. If this is zero, MCLK output
+//! is disabled.
+//!
+//! This function sets the dividers to provide MCLK to the I2S module. A MCLK
+//! divider will be chosen that produces the MCLK frequency that is the closest
+//! possible to the requested frequency, which may be above or below the
+//! requested frequency.
+//!
+//! The actual MCLK frequency will be returned. It is the responsibility of
+//! the application to determine if the selected MCLK is acceptable; in general
+//! the human ear can not discern the frequency difference if it is within 0.3%
+//! of the desired frequency (though there is a very small percentage of the
+//! population that can discern lower frequency deviations).
+//!
+//! \return Returns the actual MCLK frequency.
+//
+//*****************************************************************************
+unsigned long
+SysCtlI2SMClkSet(unsigned long ulInputClock, unsigned long ulMClk)
+{
+ unsigned long ulDivInt, ulDivFrac, ulPLL;
+
+ //
+ // See if the I2S MCLK should be disabled.
+ //
+ if(ulMClk == 0)
+ {
+ //
+ // Disable the I2S MCLK and return.
+ //
+ HWREG(SYSCTL_I2SMCLKCFG) = 0;
+ return(0);
+ }
+
+ //
+ // See if the input clock was specified.
+ //
+ if(ulInputClock == 0)
+ {
+ //
+ // The input clock was not specified, so compute the output frequency
+ // of the PLL. Get the current PLL configuration.
+ //
+ ulPLL = HWREG(SYSCTL_PLLCFG);
+
+ //
+ // Get the frequency of the crystal in use.
+ //
+ ulInputClock = g_pulXtals[(HWREG(SYSCTL_RCC) & SYSCTL_RCC_XTAL_M) >>
+ SYSCTL_RCC_XTAL_S];
+
+ //
+ // Calculate the PLL output frequency.
+ //
+ ulInputClock = ((ulInputClock * ((ulPLL & SYSCTL_PLLCFG_F_M) >>
+ SYSCTL_PLLCFG_F_S)) /
+ ((((ulPLL & SYSCTL_PLLCFG_R_M) >>
+ SYSCTL_PLLCFG_R_S) + 1)));
+
+ //
+ // See if the optional output divide by 2 is being used.
+ //
+ if(ulPLL & SYSCTL_PLLCFG_OD_2)
+ {
+ ulInputClock /= 2;
+ }
+
+ //
+ // See if the optional output divide by 4 is being used.
+ //
+ if(ulPLL & SYSCTL_PLLCFG_OD_4)
+ {
+ ulInputClock /= 4;
+ }
+ }
+
+ //
+ // Verify that the requested MCLK frequency is attainable.
+ //
+ ASSERT(ulMClk < ulInputClock);
+
+ //
+ // Add a rounding factor to the input clock, so that the MCLK frequency
+ // that is closest to the desire value is selected.
+ //
+ ulInputClock += (ulMClk / 32) - 1;
+
+ //
+ // Compute the integer portion of the MCLK divider.
+ //
+ ulDivInt = ulInputClock / ulMClk;
+
+ //
+ // If the divisor is too large, then simply use the maximum divisor.
+ //
+ if(CLASS_IS_TEMPEST && REVISION_IS_B1 && (ulDivInt > 255))
+ {
+ ulDivInt = 255;
+ ulDivFrac = 15;
+ }
+ else if(ulDivInt > 1023)
+ {
+ ulDivInt = 1023;
+ ulDivFrac = 15;
+ }
+ else
+ {
+ //
+ // Compute the fractional portion of the MCLK divider.
+ //
+ ulDivFrac = ((ulInputClock - (ulDivInt * ulMClk)) * 16) / ulMClk;
+ }
+
+ //
+ // Set the divisor for the Tx and Rx MCLK generators and enable the clocks.
+ //
+ HWREG(SYSCTL_I2SMCLKCFG) = (SYSCTL_I2SMCLKCFG_RXEN |
+ (ulDivInt << SYSCTL_I2SMCLKCFG_RXI_S) |
+ (ulDivFrac << SYSCTL_I2SMCLKCFG_RXF_S) |
+ SYSCTL_I2SMCLKCFG_TXEN |
+ (ulDivInt << SYSCTL_I2SMCLKCFG_TXI_S) |
+ (ulDivFrac << SYSCTL_I2SMCLKCFG_TXF_S));
+
+ //
+ // Return the actual MCLK frequency.
+ //
+ ulInputClock -= (ulMClk / 32) - 1;
+ ulDivInt = (ulDivInt * 16) + ulDivFrac;
+ ulMClk = (ulInputClock / ulDivInt) * 16;
+ ulMClk += ((ulInputClock - ((ulMClk / 16) * ulDivInt)) * 16) / ulDivInt;
+ return(ulMClk);
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
Property changes on: branches/eagle_mmc/src/platform/lm3s/sysctl.c
___________________________________________________________________
Name: svn:executable
+ *
Modified: branches/eagle_mmc/src/platform/lm3s/sysctl.h
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/sysctl.h 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lm3s/sysctl.h 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,392 +1,469 @@
-//*****************************************************************************
-//
-// sysctl.h - Prototypes for the system control driver.
-//
-// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
-// Software License Agreement
-//
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
-//
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws. All rights are reserved. You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program. Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
-//
-// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-//
-// This is part of revision 3740 of the Stellaris Peripheral Driver Library.
-//
-//*****************************************************************************
-
-#ifndef __SYSCTL_H__
-#define __SYSCTL_H__
-
-//*****************************************************************************
-//
-// If building with a C++ compiler, make all of the definitions in this header
-// have a C binding.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-//*****************************************************************************
-//
-// The following are values that can be passed to the
-// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(),
-// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the
-// ulPeripheral parameter. The peripherals in the fourth group (upper nibble
-// is 3) can only be used with the SysCtlPeripheralPresent() API.
-//
-//*****************************************************************************
-#define SYSCTL_PERIPH_WDOG 0x00000008 // Watchdog
-#define SYSCTL_PERIPH_HIBERNATE 0x00000040 // Hibernation module
-#define SYSCTL_PERIPH_ADC 0x00100001 // ADC
-#define SYSCTL_PERIPH_PWM 0x00100010 // PWM
-#define SYSCTL_PERIPH_CAN0 0x00100100 // CAN 0
-#define SYSCTL_PERIPH_CAN1 0x00100200 // CAN 1
-#define SYSCTL_PERIPH_CAN2 0x00100400 // CAN 2
-#define SYSCTL_PERIPH_UART0 0x10000001 // UART 0
-#define SYSCTL_PERIPH_UART1 0x10000002 // UART 1
-#define SYSCTL_PERIPH_UART2 0x10000004 // UART 2
-#ifndef DEPRECATED
-#define SYSCTL_PERIPH_SSI 0x10000010 // SSI
-#endif
-#define SYSCTL_PERIPH_SSI0 0x10000010 // SSI 0
-#define SYSCTL_PERIPH_SSI1 0x10000020 // SSI 1
-#ifndef DEPRECATED
-#define SYSCTL_PERIPH_QEI 0x10000100 // QEI
-#endif
-#define SYSCTL_PERIPH_QEI0 0x10000100 // QEI 0
-#define SYSCTL_PERIPH_QEI1 0x10000200 // QEI 1
-#ifndef DEPRECATED
-#define SYSCTL_PERIPH_I2C 0x10001000 // I2C
-#endif
-#define SYSCTL_PERIPH_I2C0 0x10001000 // I2C 0
-#define SYSCTL_PERIPH_I2C1 0x10004000 // I2C 1
-#define SYSCTL_PERIPH_TIMER0 0x10100001 // Timer 0
-#define SYSCTL_PERIPH_TIMER1 0x10100002 // Timer 1
-#define SYSCTL_PERIPH_TIMER2 0x10100004 // Timer 2
-#define SYSCTL_PERIPH_TIMER3 0x10100008 // Timer 3
-#define SYSCTL_PERIPH_COMP0 0x10100100 // Analog comparator 0
-#define SYSCTL_PERIPH_COMP1 0x10100200 // Analog comparator 1
-#define SYSCTL_PERIPH_COMP2 0x10100400 // Analog comparator 2
-#define SYSCTL_PERIPH_GPIOA 0x20000001 // GPIO A
-#define SYSCTL_PERIPH_GPIOB 0x20000002 // GPIO B
-#define SYSCTL_PERIPH_GPIOC 0x20000004 // GPIO C
-#define SYSCTL_PERIPH_GPIOD 0x20000008 // GPIO D
-#define SYSCTL_PERIPH_GPIOE 0x20000010 // GPIO E
-#define SYSCTL_PERIPH_GPIOF 0x20000020 // GPIO F
-#define SYSCTL_PERIPH_GPIOG 0x20000040 // GPIO G
-#define SYSCTL_PERIPH_GPIOH 0x20000080 // GPIO H
-#define SYSCTL_PERIPH_UDMA 0x20002000 // uDMA
-#define SYSCTL_PERIPH_USB0 0x20100001 // USB0
-#define SYSCTL_PERIPH_ETH 0x20105000 // ETH
-#define SYSCTL_PERIPH_IEEE1588 0x20100100 // IEEE1588
-#define SYSCTL_PERIPH_PLL 0x30000010 // PLL
-#define SYSCTL_PERIPH_TEMP 0x30000020 // Temperature sensor
-#define SYSCTL_PERIPH_MPU 0x30000080 // Cortex M3 MPU
-
-//*****************************************************************************
-//
-// The following are values that can be passed to the SysCtlPinPresent() API
-// as the ulPin parameter.
-//
-//*****************************************************************************
-#define SYSCTL_PIN_PWM0 0x00000001 // PWM0 pin
-#define SYSCTL_PIN_PWM1 0x00000002 // PWM1 pin
-#define SYSCTL_PIN_PWM2 0x00000004 // PWM2 pin
-#define SYSCTL_PIN_PWM3 0x00000008 // PWM3 pin
-#define SYSCTL_PIN_PWM4 0x00000010 // PWM4 pin
-#define SYSCTL_PIN_PWM5 0x00000020 // PWM5 pin
-#define SYSCTL_PIN_PWM6 0x00000040 // PWM6 pin
-#define SYSCTL_PIN_PWM7 0x00000080 // PWM7 pin
-#define SYSCTL_PIN_C0MINUS 0x00000040 // C0- pin
-#define SYSCTL_PIN_C0PLUS 0x00000080 // C0+ pin
-#define SYSCTL_PIN_C0O 0x00000100 // C0o pin
-#define SYSCTL_PIN_C1MINUS 0x00000200 // C1- pin
-#define SYSCTL_PIN_C1PLUS 0x00000400 // C1+ pin
-#define SYSCTL_PIN_C1O 0x00000800 // C1o pin
-#define SYSCTL_PIN_C2MINUS 0x00001000 // C2- pin
-#define SYSCTL_PIN_C2PLUS 0x00002000 // C2+ pin
-#define SYSCTL_PIN_C2O 0x00004000 // C2o pin
-#define SYSCTL_PIN_MC_FAULT0 0x00008000 // MC0 Fault pin
-#define SYSCTL_PIN_ADC0 0x00010000 // ADC0 pin
-#define SYSCTL_PIN_ADC1 0x00020000 // ADC1 pin
-#define SYSCTL_PIN_ADC2 0x00040000 // ADC2 pin
-#define SYSCTL_PIN_ADC3 0x00080000 // ADC3 pin
-#define SYSCTL_PIN_ADC4 0x00100000 // ADC4 pin
-#define SYSCTL_PIN_ADC5 0x00200000 // ADC5 pin
-#define SYSCTL_PIN_ADC6 0x00400000 // ADC6 pin
-#define SYSCTL_PIN_ADC7 0x00800000 // ADC7 pin
-#define SYSCTL_PIN_CCP0 0x01000000 // CCP0 pin
-#define SYSCTL_PIN_CCP1 0x02000000 // CCP1 pin
-#define SYSCTL_PIN_CCP2 0x04000000 // CCP2 pin
-#define SYSCTL_PIN_CCP3 0x08000000 // CCP3 pin
-#define SYSCTL_PIN_CCP4 0x10000000 // CCP4 pin
-#define SYSCTL_PIN_CCP5 0x20000000 // CCP5 pin
-#define SYSCTL_PIN_32KHZ 0x80000000 // 32kHz pin
-
-//*****************************************************************************
-//
-// The following are values that can be passed to the SysCtlLDOSet() API as
-// the ulVoltage value, or returned by the SysCtlLDOGet() API.
-//
-//*****************************************************************************
-#define SYSCTL_LDO_2_25V 0x00000005 // LDO output of 2.25V
-#define SYSCTL_LDO_2_30V 0x00000004 // LDO output of 2.30V
-#define SYSCTL_LDO_2_35V 0x00000003 // LDO output of 2.35V
-#define SYSCTL_LDO_2_40V 0x00000002 // LDO output of 2.40V
-#define SYSCTL_LDO_2_45V 0x00000001 // LDO output of 2.45V
-#define SYSCTL_LDO_2_50V 0x00000000 // LDO output of 2.50V
-#define SYSCTL_LDO_2_55V 0x0000001f // LDO output of 2.55V
-#define SYSCTL_LDO_2_60V 0x0000001e // LDO output of 2.60V
-#define SYSCTL_LDO_2_65V 0x0000001d // LDO output of 2.65V
-#define SYSCTL_LDO_2_70V 0x0000001c // LDO output of 2.70V
-#define SYSCTL_LDO_2_75V 0x0000001b // LDO output of 2.75V
-
-//*****************************************************************************
-//
-// The following are values that can be passed to the SysCtlLDOConfigSet() API.
-//
-//*****************************************************************************
-#define SYSCTL_LDOCFG_ARST 0x00000001 // Allow LDO failure to reset
-#define SYSCTL_LDOCFG_NORST 0x00000000 // Do not reset on LDO failure
-
-//*****************************************************************************
-//
-// The following are values that can be passed to the SysCtlIntEnable(),
-// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask
-// by the SysCtlIntStatus() API.
-//
-//*****************************************************************************
-#define SYSCTL_INT_MOSC_PUP 0x00000100 // MOSC power-up interrupt
-#define SYSCTL_INT_USBPLL_LOCK 0x00000080 // USB PLL lock interrupt
-#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt
-#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt
-#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int
-#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int
-#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt
-#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt
-#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt
-
-//*****************************************************************************
-//
-// The following are values that can be passed to the SysCtlResetCauseClear()
-// API or returned by the SysCtlResetCauseGet() API.
-//
-//*****************************************************************************
-#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset
-#define SYSCTL_CAUSE_SW 0x00000010 // Software reset
-#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset
-#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset
-#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset
-#define SYSCTL_CAUSE_EXT 0x00000001 // External reset
-
-//*****************************************************************************
-//
-// The following are values that can be passed to the SysCtlBrownOutConfigSet()
-// API as the ulConfig parameter.
-//
-//*****************************************************************************
-#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting
-#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting
-
-//*****************************************************************************
-//
-// The following are values that can be passed to the SysCtlPWMClockSet() API
-// as the ulConfig parameter, and can be returned by the SysCtlPWMClockGet()
-// API.
-//
-//*****************************************************************************
-#define SYSCTL_PWMDIV_1 0x00000000 // PWM clock is processor clock /1
-#define SYSCTL_PWMDIV_2 0x00100000 // PWM clock is processor clock /2
-#define SYSCTL_PWMDIV_4 0x00120000 // PWM clock is processor clock /4
-#define SYSCTL_PWMDIV_8 0x00140000 // PWM clock is processor clock /8
-#define SYSCTL_PWMDIV_16 0x00160000 // PWM clock is processor clock /16
-#define SYSCTL_PWMDIV_32 0x00180000 // PWM clock is processor clock /32
-#define SYSCTL_PWMDIV_64 0x001A0000 // PWM clock is processor clock /64
-
-//*****************************************************************************
-//
-// The following are values that can be passed to the SysCtlADCSpeedSet() API
-// as the ulSpeed parameter, and can be returned by the SyCtlADCSpeedGet()
-// API.
-//
-//*****************************************************************************
-#define SYSCTL_ADCSPEED_1MSPS 0x00000300 // 1,000,000 samples per second
-#define SYSCTL_ADCSPEED_500KSPS 0x00000200 // 500,000 samples per second
-#define SYSCTL_ADCSPEED_250KSPS 0x00000100 // 250,000 samples per second
-#define SYSCTL_ADCSPEED_125KSPS 0x00000000 // 125,000 samples per second
-
-//*****************************************************************************
-//
-// The following are values that can be passed to the SysCtlClockSet() API as
-// the ulConfig parameter.
-//
-//*****************************************************************************
-#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1
-#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2
-#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3
-#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4
-#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5
-#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6
-#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7
-#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8
-#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9
-#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10
-#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11
-#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12
-#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13
-#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14
-#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15
-#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16
-#define SYSCTL_SYSDIV_17 0x88400000 // Processor clock is osc/pll /17
-#define SYSCTL_SYSDIV_18 0x88C00000 // Processor clock is osc/pll /18
-#define SYSCTL_SYSDIV_19 0x89400000 // Processor clock is osc/pll /19
-#define SYSCTL_SYSDIV_20 0x89C00000 // Processor clock is osc/pll /20
-#define SYSCTL_SYSDIV_21 0x8A400000 // Processor clock is osc/pll /21
-#define SYSCTL_SYSDIV_22 0x8AC00000 // Processor clock is osc/pll /22
-#define SYSCTL_SYSDIV_23 0x8B400000 // Processor clock is osc/pll /23
-#define SYSCTL_SYSDIV_24 0x8BC00000 // Processor clock is osc/pll /24
-#define SYSCTL_SYSDIV_25 0x8C400000 // Processor clock is osc/pll /25
-#define SYSCTL_SYSDIV_26 0x8CC00000 // Processor clock is osc/pll /26
-#define SYSCTL_SYSDIV_27 0x8D400000 // Processor clock is osc/pll /27
-#define SYSCTL_SYSDIV_28 0x8DC00000 // Processor clock is osc/pll /28
-#define SYSCTL_SYSDIV_29 0x8E400000 // Processor clock is osc/pll /29
-#define SYSCTL_SYSDIV_30 0x8EC00000 // Processor clock is osc/pll /30
-#define SYSCTL_SYSDIV_31 0x8F400000 // Processor clock is osc/pll /31
-#define SYSCTL_SYSDIV_32 0x8FC00000 // Processor clock is osc/pll /32
-#define SYSCTL_SYSDIV_33 0x90400000 // Processor clock is osc/pll /33
-#define SYSCTL_SYSDIV_34 0x90C00000 // Processor clock is osc/pll /34
-#define SYSCTL_SYSDIV_35 0x91400000 // Processor clock is osc/pll /35
-#define SYSCTL_SYSDIV_36 0x91C00000 // Processor clock is osc/pll /36
-#define SYSCTL_SYSDIV_37 0x92400000 // Processor clock is osc/pll /37
-#define SYSCTL_SYSDIV_38 0x92C00000 // Processor clock is osc/pll /38
-#define SYSCTL_SYSDIV_39 0x93400000 // Processor clock is osc/pll /39
-#define SYSCTL_SYSDIV_40 0x93C00000 // Processor clock is osc/pll /40
-#define SYSCTL_SYSDIV_41 0x94400000 // Processor clock is osc/pll /41
-#define SYSCTL_SYSDIV_42 0x94C00000 // Processor clock is osc/pll /42
-#define SYSCTL_SYSDIV_43 0x95400000 // Processor clock is osc/pll /43
-#define SYSCTL_SYSDIV_44 0x95C00000 // Processor clock is osc/pll /44
-#define SYSCTL_SYSDIV_45 0x96400000 // Processor clock is osc/pll /45
-#define SYSCTL_SYSDIV_46 0x96C00000 // Processor clock is osc/pll /46
-#define SYSCTL_SYSDIV_47 0x97400000 // Processor clock is osc/pll /47
-#define SYSCTL_SYSDIV_48 0x97C00000 // Processor clock is osc/pll /48
-#define SYSCTL_SYSDIV_49 0x98400000 // Processor clock is osc/pll /49
-#define SYSCTL_SYSDIV_50 0x98C00000 // Processor clock is osc/pll /50
-#define SYSCTL_SYSDIV_51 0x99400000 // Processor clock is osc/pll /51
-#define SYSCTL_SYSDIV_52 0x99C00000 // Processor clock is osc/pll /52
-#define SYSCTL_SYSDIV_53 0x9A400000 // Processor clock is osc/pll /53
-#define SYSCTL_SYSDIV_54 0x9AC00000 // Processor clock is osc/pll /54
-#define SYSCTL_SYSDIV_55 0x9B400000 // Processor clock is osc/pll /55
-#define SYSCTL_SYSDIV_56 0x9BC00000 // Processor clock is osc/pll /56
-#define SYSCTL_SYSDIV_57 0x9C400000 // Processor clock is osc/pll /57
-#define SYSCTL_SYSDIV_58 0x9CC00000 // Processor clock is osc/pll /58
-#define SYSCTL_SYSDIV_59 0x9D400000 // Processor clock is osc/pll /59
-#define SYSCTL_SYSDIV_60 0x9DC00000 // Processor clock is osc/pll /60
-#define SYSCTL_SYSDIV_61 0x9E400000 // Processor clock is osc/pll /61
-#define SYSCTL_SYSDIV_62 0x9EC00000 // Processor clock is osc/pll /62
-#define SYSCTL_SYSDIV_63 0x9F400000 // Processor clock is osc/pll /63
-#define SYSCTL_SYSDIV_64 0x9FC00000 // Processor clock is osc/pll /64
-#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock
-#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock
-#define SYSCTL_XTAL_1MHZ 0x00000000 // External crystal is 1MHz
-#define SYSCTL_XTAL_1_84MHZ 0x00000040 // External crystal is 1.8432MHz
-#define SYSCTL_XTAL_2MHZ 0x00000080 // External crystal is 2MHz
-#define SYSCTL_XTAL_2_45MHZ 0x000000C0 // External crystal is 2.4576MHz
-#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz
-#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz
-#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz
-#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz
-#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz
-#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz
-#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz
-#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz
-#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz
-#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz
-#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz
-#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz
-#define SYSCTL_XTAL_10MHZ 0x00000400 // External crystal is 10 MHz
-#define SYSCTL_XTAL_12MHZ 0x00000440 // External crystal is 12 MHz
-#define SYSCTL_XTAL_12_2MHZ 0x00000480 // External crystal is 12.288 MHz
-#define SYSCTL_XTAL_13_5MHZ 0x000004C0 // External crystal is 13.56 MHz
-#define SYSCTL_XTAL_14_3MHZ 0x00000500 // External crystal is 14.31818 MHz
-#define SYSCTL_XTAL_16MHZ 0x00000540 // External crystal is 16 MHz
-#define SYSCTL_XTAL_16_3MHZ 0x00000580 // External crystal is 16.384 MHz
-#define SYSCTL_OSC_MAIN 0x00000000 // Osc source is main osc
-#define SYSCTL_OSC_INT 0x00000010 // Osc source is int. osc
-#define SYSCTL_OSC_INT4 0x00000020 // Osc source is int. osc /4
-#define SYSCTL_OSC_INT30 0x00000030 // Osc source is int. 30 KHz
-#define SYSCTL_OSC_EXT32 0x80000038 // Osc source is ext. 32 KHz
-#define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator
-#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator
-
-//*****************************************************************************
-//
-// Prototypes for the APIs.
-//
-//*****************************************************************************
-extern unsigned long SysCtlSRAMSizeGet(void);
-extern unsigned long SysCtlFlashSizeGet(void);
-extern tBoolean SysCtlPinPresent(unsigned long ulPin);
-extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral);
-extern void SysCtlPeripheralReset(unsigned long ulPeripheral);
-extern void SysCtlPeripheralEnable(unsigned long ulPeripheral);
-extern void SysCtlPeripheralDisable(unsigned long ulPeripheral);
-extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral);
-extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral);
-extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral);
-extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral);
-extern void SysCtlPeripheralClockGating(tBoolean bEnable);
-extern void SysCtlIntRegister(void (*pfnHandler)(void));
-extern void SysCtlIntUnregister(void);
-extern void SysCtlIntEnable(unsigned long ulInts);
-extern void SysCtlIntDisable(unsigned long ulInts);
-extern void SysCtlIntClear(unsigned long ulInts);
-extern unsigned long SysCtlIntStatus(tBoolean bMasked);
-extern void SysCtlLDOSet(unsigned long ulVoltage);
-extern unsigned long SysCtlLDOGet(void);
-extern void SysCtlLDOConfigSet(unsigned long ulConfig);
-extern void SysCtlReset(void);
-extern void SysCtlSleep(void);
-extern void SysCtlDeepSleep(void);
-extern unsigned long SysCtlResetCauseGet(void);
-extern void SysCtlResetCauseClear(unsigned long ulCauses);
-extern void SysCtlBrownOutConfigSet(unsigned long ulConfig,
- unsigned long ulDelay);
-extern void SysCtlDelay(unsigned long ulCount);
-extern void SysCtlClockSet(unsigned long ulConfig);
-extern unsigned long SysCtlClockGet(void);
-extern void SysCtlPWMClockSet(unsigned long ulConfig);
-extern unsigned long SysCtlPWMClockGet(void);
-extern void SysCtlADCSpeedSet(unsigned long ulSpeed);
-extern unsigned long SysCtlADCSpeedGet(void);
-extern void SysCtlIOSCVerificationSet(tBoolean bEnable);
-extern void SysCtlMOSCVerificationSet(tBoolean bEnable);
-extern void SysCtlPLLVerificationSet(tBoolean bEnable);
-extern void SysCtlClkVerificationClear(void);
-extern void SysCtlGPIOAHBEnable(unsigned long ulGPIOPeripheral);
-extern void SysCtlGPIOAHBDisable(unsigned long ulGPIOPeripheral);
-extern void SysCtlUSBPLLEnable(void);
-extern void SysCtlUSBPLLDisable(void);
-
-//*****************************************************************************
-//
-// Mark the end of the C bindings section for C++ compilers.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-}
-#endif
-
-#endif // __SYSCTL_H__
+//*****************************************************************************
+//
+// sysctl.h - Prototypes for the system control driver.
+//
+// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __SYSCTL_H__
+#define __SYSCTL_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the
+// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(),
+// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the
+// ulPeripheral parameter. The peripherals in the fourth group (upper nibble
+// is 3) can only be used with the SysCtlPeripheralPresent() API.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+#define SYSCTL_PERIPH_WDOG 0x00000008 // Watchdog
+#endif
+#define SYSCTL_PERIPH_WDOG0 0x00000008 // Watchdog 0
+#define SYSCTL_PERIPH_HIBERNATE 0x00000040 // Hibernation module
+#ifndef DEPRECATED
+#define SYSCTL_PERIPH_ADC 0x00100001 // ADC
+#endif
+#define SYSCTL_PERIPH_ADC0 0x00100001 // ADC0
+#define SYSCTL_PERIPH_ADC1 0x00100002 // ADC1
+#define SYSCTL_PERIPH_PWM 0x00100010 // PWM
+#define SYSCTL_PERIPH_CAN0 0x00100100 // CAN 0
+#define SYSCTL_PERIPH_CAN1 0x00100200 // CAN 1
+#define SYSCTL_PERIPH_CAN2 0x00100400 // CAN 2
+#define SYSCTL_PERIPH_WDOG1 0x00101000 // Watchdog 1
+#define SYSCTL_PERIPH_UART0 0x10000001 // UART 0
+#define SYSCTL_PERIPH_UART1 0x10000002 // UART 1
+#define SYSCTL_PERIPH_UART2 0x10000004 // UART 2
+#ifndef DEPRECATED
+#define SYSCTL_PERIPH_SSI 0x10000010 // SSI
+#endif
+#define SYSCTL_PERIPH_SSI0 0x10000010 // SSI 0
+#define SYSCTL_PERIPH_SSI1 0x10000020 // SSI 1
+#ifndef DEPRECATED
+#define SYSCTL_PERIPH_QEI 0x10000100 // QEI
+#endif
+#define SYSCTL_PERIPH_QEI0 0x10000100 // QEI 0
+#define SYSCTL_PERIPH_QEI1 0x10000200 // QEI 1
+#ifndef DEPRECATED
+#define SYSCTL_PERIPH_I2C 0x10001000 // I2C
+#endif
+#define SYSCTL_PERIPH_I2C0 0x10001000 // I2C 0
+#define SYSCTL_PERIPH_I2C1 0x10004000 // I2C 1
+#define SYSCTL_PERIPH_TIMER0 0x10100001 // Timer 0
+#define SYSCTL_PERIPH_TIMER1 0x10100002 // Timer 1
+#define SYSCTL_PERIPH_TIMER2 0x10100004 // Timer 2
+#define SYSCTL_PERIPH_TIMER3 0x10100008 // Timer 3
+#define SYSCTL_PERIPH_COMP0 0x10100100 // Analog comparator 0
+#define SYSCTL_PERIPH_COMP1 0x10100200 // Analog comparator 1
+#define SYSCTL_PERIPH_COMP2 0x10100400 // Analog comparator 2
+#define SYSCTL_PERIPH_I2S0 0x10101000 // I2S0
+#define SYSCTL_PERIPH_EPI0 0x10104000 // EPI0
+#define SYSCTL_PERIPH_GPIOA 0x20000001 // GPIO A
+#define SYSCTL_PERIPH_GPIOB 0x20000002 // GPIO B
+#define SYSCTL_PERIPH_GPIOC 0x20000004 // GPIO C
+#define SYSCTL_PERIPH_GPIOD 0x20000008 // GPIO D
+#define SYSCTL_PERIPH_GPIOE 0x20000010 // GPIO E
+#define SYSCTL_PERIPH_GPIOF 0x20000020 // GPIO F
+#define SYSCTL_PERIPH_GPIOG 0x20000040 // GPIO G
+#define SYSCTL_PERIPH_GPIOH 0x20000080 // GPIO H
+#define SYSCTL_PERIPH_GPIOJ 0x20000100 // GPIO J
+#define SYSCTL_PERIPH_UDMA 0x20002000 // uDMA
+#define SYSCTL_PERIPH_USB0 0x20100001 // USB0
+#define SYSCTL_PERIPH_ETH 0x20105000 // ETH
+#define SYSCTL_PERIPH_IEEE1588 0x20100100 // IEEE1588
+#define SYSCTL_PERIPH_PLL 0x30000010 // PLL
+#define SYSCTL_PERIPH_TEMP 0x30000020 // Temperature sensor
+#define SYSCTL_PERIPH_MPU 0x30000080 // Cortex M3 MPU
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the SysCtlPinPresent() API
+// as the ulPin parameter.
+//
+//*****************************************************************************
+#define SYSCTL_PIN_PWM0 0x00000001 // PWM0 pin
+#define SYSCTL_PIN_PWM1 0x00000002 // PWM1 pin
+#define SYSCTL_PIN_PWM2 0x00000004 // PWM2 pin
+#define SYSCTL_PIN_PWM3 0x00000008 // PWM3 pin
+#define SYSCTL_PIN_PWM4 0x00000010 // PWM4 pin
+#define SYSCTL_PIN_PWM5 0x00000020 // PWM5 pin
+#define SYSCTL_PIN_PWM6 0x00000040 // PWM6 pin
+#define SYSCTL_PIN_PWM7 0x00000080 // PWM7 pin
+#define SYSCTL_PIN_C0MINUS 0x00000040 // C0- pin
+#define SYSCTL_PIN_C0PLUS 0x00000080 // C0+ pin
+#define SYSCTL_PIN_C0O 0x00000100 // C0o pin
+#define SYSCTL_PIN_C1MINUS 0x00000200 // C1- pin
+#define SYSCTL_PIN_C1PLUS 0x00000400 // C1+ pin
+#define SYSCTL_PIN_C1O 0x00000800 // C1o pin
+#define SYSCTL_PIN_C2MINUS 0x00001000 // C2- pin
+#define SYSCTL_PIN_C2PLUS 0x00002000 // C2+ pin
+#define SYSCTL_PIN_C2O 0x00004000 // C2o pin
+#define SYSCTL_PIN_MC_FAULT0 0x00008000 // MC0 Fault pin
+#define SYSCTL_PIN_ADC0 0x00010000 // ADC0 pin
+#define SYSCTL_PIN_ADC1 0x00020000 // ADC1 pin
+#define SYSCTL_PIN_ADC2 0x00040000 // ADC2 pin
+#define SYSCTL_PIN_ADC3 0x00080000 // ADC3 pin
+#define SYSCTL_PIN_ADC4 0x00100000 // ADC4 pin
+#define SYSCTL_PIN_ADC5 0x00200000 // ADC5 pin
+#define SYSCTL_PIN_ADC6 0x00400000 // ADC6 pin
+#define SYSCTL_PIN_ADC7 0x00800000 // ADC7 pin
+#define SYSCTL_PIN_CCP0 0x01000000 // CCP0 pin
+#define SYSCTL_PIN_CCP1 0x02000000 // CCP1 pin
+#define SYSCTL_PIN_CCP2 0x04000000 // CCP2 pin
+#define SYSCTL_PIN_CCP3 0x08000000 // CCP3 pin
+#define SYSCTL_PIN_CCP4 0x10000000 // CCP4 pin
+#define SYSCTL_PIN_CCP5 0x20000000 // CCP5 pin
+#define SYSCTL_PIN_32KHZ 0x80000000 // 32kHz pin
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the SysCtlLDOSet() API as
+// the ulVoltage value, or returned by the SysCtlLDOGet() API.
+//
+//*****************************************************************************
+#define SYSCTL_LDO_2_25V 0x00000005 // LDO output of 2.25V
+#define SYSCTL_LDO_2_30V 0x00000004 // LDO output of 2.30V
+#define SYSCTL_LDO_2_35V 0x00000003 // LDO output of 2.35V
+#define SYSCTL_LDO_2_40V 0x00000002 // LDO output of 2.40V
+#define SYSCTL_LDO_2_45V 0x00000001 // LDO output of 2.45V
+#define SYSCTL_LDO_2_50V 0x00000000 // LDO output of 2.50V
+#define SYSCTL_LDO_2_55V 0x0000001f // LDO output of 2.55V
+#define SYSCTL_LDO_2_60V 0x0000001e // LDO output of 2.60V
+#define SYSCTL_LDO_2_65V 0x0000001d // LDO output of 2.65V
+#define SYSCTL_LDO_2_70V 0x0000001c // LDO output of 2.70V
+#define SYSCTL_LDO_2_75V 0x0000001b // LDO output of 2.75V
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the SysCtlLDOConfigSet() API.
+//
+//*****************************************************************************
+#define SYSCTL_LDOCFG_ARST 0x00000001 // Allow LDO failure to reset
+#define SYSCTL_LDOCFG_NORST 0x00000000 // Do not reset on LDO failure
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the SysCtlIntEnable(),
+// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask
+// by the SysCtlIntStatus() API.
+//
+//*****************************************************************************
+#define SYSCTL_INT_MOSC_PUP 0x00000100 // MOSC power-up interrupt
+#define SYSCTL_INT_USBPLL_LOCK 0x00000080 // USB PLL lock interrupt
+#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt
+#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt
+#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int
+#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int
+#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt
+#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt
+#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the SysCtlResetCauseClear()
+// API or returned by the SysCtlResetCauseGet() API.
+//
+//*****************************************************************************
+#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset
+#define SYSCTL_CAUSE_SW 0x00000010 // Software reset
+#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset
+#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset
+#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset
+#define SYSCTL_CAUSE_EXT 0x00000001 // External reset
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the SysCtlBrownOutConfigSet()
+// API as the ulConfig parameter.
+//
+//*****************************************************************************
+#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting
+#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the SysCtlPWMClockSet() API
+// as the ulConfig parameter, and can be returned by the SysCtlPWMClockGet()
+// API.
+//
+//*****************************************************************************
+#define SYSCTL_PWMDIV_1 0x00000000 // PWM clock is processor clock /1
+#define SYSCTL_PWMDIV_2 0x00100000 // PWM clock is processor clock /2
+#define SYSCTL_PWMDIV_4 0x00120000 // PWM clock is processor clock /4
+#define SYSCTL_PWMDIV_8 0x00140000 // PWM clock is processor clock /8
+#define SYSCTL_PWMDIV_16 0x00160000 // PWM clock is processor clock /16
+#define SYSCTL_PWMDIV_32 0x00180000 // PWM clock is processor clock /32
+#define SYSCTL_PWMDIV_64 0x001A0000 // PWM clock is processor clock /64
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the SysCtlADCSpeedSet() API
+// as the ulSpeed parameter, and can be returned by the SyCtlADCSpeedGet()
+// API.
+//
+//*****************************************************************************
+#define SYSCTL_ADCSPEED_1MSPS 0x00000300 // 1,000,000 samples per second
+#define SYSCTL_ADCSPEED_500KSPS 0x00000200 // 500,000 samples per second
+#define SYSCTL_ADCSPEED_250KSPS 0x00000100 // 250,000 samples per second
+#define SYSCTL_ADCSPEED_125KSPS 0x00000000 // 125,000 samples per second
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the SysCtlClockSet() API as
+// the ulConfig parameter.
+//
+//*****************************************************************************
+#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1
+#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2
+#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3
+#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4
+#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5
+#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6
+#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7
+#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8
+#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9
+#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10
+#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11
+#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12
+#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13
+#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14
+#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15
+#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16
+#define SYSCTL_SYSDIV_17 0x88400000 // Processor clock is osc/pll /17
+#define SYSCTL_SYSDIV_18 0x88C00000 // Processor clock is osc/pll /18
+#define SYSCTL_SYSDIV_19 0x89400000 // Processor clock is osc/pll /19
+#define SYSCTL_SYSDIV_20 0x89C00000 // Processor clock is osc/pll /20
+#define SYSCTL_SYSDIV_21 0x8A400000 // Processor clock is osc/pll /21
+#define SYSCTL_SYSDIV_22 0x8AC00000 // Processor clock is osc/pll /22
+#define SYSCTL_SYSDIV_23 0x8B400000 // Processor clock is osc/pll /23
+#define SYSCTL_SYSDIV_24 0x8BC00000 // Processor clock is osc/pll /24
+#define SYSCTL_SYSDIV_25 0x8C400000 // Processor clock is osc/pll /25
+#define SYSCTL_SYSDIV_26 0x8CC00000 // Processor clock is osc/pll /26
+#define SYSCTL_SYSDIV_27 0x8D400000 // Processor clock is osc/pll /27
+#define SYSCTL_SYSDIV_28 0x8DC00000 // Processor clock is osc/pll /28
+#define SYSCTL_SYSDIV_29 0x8E400000 // Processor clock is osc/pll /29
+#define SYSCTL_SYSDIV_30 0x8EC00000 // Processor clock is osc/pll /30
+#define SYSCTL_SYSDIV_31 0x8F400000 // Processor clock is osc/pll /31
+#define SYSCTL_SYSDIV_32 0x8FC00000 // Processor clock is osc/pll /32
+#define SYSCTL_SYSDIV_33 0x90400000 // Processor clock is osc/pll /33
+#define SYSCTL_SYSDIV_34 0x90C00000 // Processor clock is osc/pll /34
+#define SYSCTL_SYSDIV_35 0x91400000 // Processor clock is osc/pll /35
+#define SYSCTL_SYSDIV_36 0x91C00000 // Processor clock is osc/pll /36
+#define SYSCTL_SYSDIV_37 0x92400000 // Processor clock is osc/pll /37
+#define SYSCTL_SYSDIV_38 0x92C00000 // Processor clock is osc/pll /38
+#define SYSCTL_SYSDIV_39 0x93400000 // Processor clock is osc/pll /39
+#define SYSCTL_SYSDIV_40 0x93C00000 // Processor clock is osc/pll /40
+#define SYSCTL_SYSDIV_41 0x94400000 // Processor clock is osc/pll /41
+#define SYSCTL_SYSDIV_42 0x94C00000 // Processor clock is osc/pll /42
+#define SYSCTL_SYSDIV_43 0x95400000 // Processor clock is osc/pll /43
+#define SYSCTL_SYSDIV_44 0x95C00000 // Processor clock is osc/pll /44
+#define SYSCTL_SYSDIV_45 0x96400000 // Processor clock is osc/pll /45
+#define SYSCTL_SYSDIV_46 0x96C00000 // Processor clock is osc/pll /46
+#define SYSCTL_SYSDIV_47 0x97400000 // Processor clock is osc/pll /47
+#define SYSCTL_SYSDIV_48 0x97C00000 // Processor clock is osc/pll /48
+#define SYSCTL_SYSDIV_49 0x98400000 // Processor clock is osc/pll /49
+#define SYSCTL_SYSDIV_50 0x98C00000 // Processor clock is osc/pll /50
+#define SYSCTL_SYSDIV_51 0x99400000 // Processor clock is osc/pll /51
+#define SYSCTL_SYSDIV_52 0x99C00000 // Processor clock is osc/pll /52
+#define SYSCTL_SYSDIV_53 0x9A400000 // Processor clock is osc/pll /53
+#define SYSCTL_SYSDIV_54 0x9AC00000 // Processor clock is osc/pll /54
+#define SYSCTL_SYSDIV_55 0x9B400000 // Processor clock is osc/pll /55
+#define SYSCTL_SYSDIV_56 0x9BC00000 // Processor clock is osc/pll /56
+#define SYSCTL_SYSDIV_57 0x9C400000 // Processor clock is osc/pll /57
+#define SYSCTL_SYSDIV_58 0x9CC00000 // Processor clock is osc/pll /58
+#define SYSCTL_SYSDIV_59 0x9D400000 // Processor clock is osc/pll /59
+#define SYSCTL_SYSDIV_60 0x9DC00000 // Processor clock is osc/pll /60
+#define SYSCTL_SYSDIV_61 0x9E400000 // Processor clock is osc/pll /61
+#define SYSCTL_SYSDIV_62 0x9EC00000 // Processor clock is osc/pll /62
+#define SYSCTL_SYSDIV_63 0x9F400000 // Processor clock is osc/pll /63
+#define SYSCTL_SYSDIV_64 0x9FC00000 // Processor clock is osc/pll /64
+#define SYSCTL_SYSDIV_2_5 0xC1000000 // Processor clock is pll / 2.5
+#define SYSCTL_SYSDIV_3_5 0xC1800000 // Processor clock is pll / 3.5
+#define SYSCTL_SYSDIV_4_5 0xC2000000 // Processor clock is pll / 4.5
+#define SYSCTL_SYSDIV_5_5 0xC2800000 // Processor clock is pll / 5.5
+#define SYSCTL_SYSDIV_6_5 0xC3000000 // Processor clock is pll / 6.5
+#define SYSCTL_SYSDIV_7_5 0xC3800000 // Processor clock is pll / 7.5
+#define SYSCTL_SYSDIV_8_5 0xC4000000 // Processor clock is pll / 8.5
+#define SYSCTL_SYSDIV_9_5 0xC4800000 // Processor clock is pll / 9.5
+#define SYSCTL_SYSDIV_10_5 0xC5000000 // Processor clock is pll / 10.5
+#define SYSCTL_SYSDIV_11_5 0xC5800000 // Processor clock is pll / 11.5
+#define SYSCTL_SYSDIV_12_5 0xC6000000 // Processor clock is pll / 12.5
+#define SYSCTL_SYSDIV_13_5 0xC6800000 // Processor clock is pll / 13.5
+#define SYSCTL_SYSDIV_14_5 0xC7000000 // Processor clock is pll / 14.5
+#define SYSCTL_SYSDIV_15_5 0xC7800000 // Processor clock is pll / 15.5
+#define SYSCTL_SYSDIV_16_5 0xC8000000 // Processor clock is pll / 16.5
+#define SYSCTL_SYSDIV_17_5 0xC8800000 // Processor clock is pll / 17.5
+#define SYSCTL_SYSDIV_18_5 0xC9000000 // Processor clock is pll / 18.5
+#define SYSCTL_SYSDIV_19_5 0xC9800000 // Processor clock is pll / 19.5
+#define SYSCTL_SYSDIV_20_5 0xCA000000 // Processor clock is pll / 20.5
+#define SYSCTL_SYSDIV_21_5 0xCA800000 // Processor clock is pll / 21.5
+#define SYSCTL_SYSDIV_22_5 0xCB000000 // Processor clock is pll / 22.5
+#define SYSCTL_SYSDIV_23_5 0xCB800000 // Processor clock is pll / 23.5
+#define SYSCTL_SYSDIV_24_5 0xCC000000 // Processor clock is pll / 24.5
+#define SYSCTL_SYSDIV_25_5 0xCC800000 // Processor clock is pll / 25.5
+#define SYSCTL_SYSDIV_26_5 0xCD000000 // Processor clock is pll / 26.5
+#define SYSCTL_SYSDIV_27_5 0xCD800000 // Processor clock is pll / 27.5
+#define SYSCTL_SYSDIV_28_5 0xCE000000 // Processor clock is pll / 28.5
+#define SYSCTL_SYSDIV_29_5 0xCE800000 // Processor clock is pll / 29.5
+#define SYSCTL_SYSDIV_30_5 0xCF000000 // Processor clock is pll / 30.5
+#define SYSCTL_SYSDIV_31_5 0xCF800000 // Processor clock is pll / 31.5
+#define SYSCTL_SYSDIV_32_5 0xD0000000 // Processor clock is pll / 32.5
+#define SYSCTL_SYSDIV_33_5 0xD0800000 // Processor clock is pll / 33.5
+#define SYSCTL_SYSDIV_34_5 0xD1000000 // Processor clock is pll / 34.5
+#define SYSCTL_SYSDIV_35_5 0xD1800000 // Processor clock is pll / 35.5
+#define SYSCTL_SYSDIV_36_5 0xD2000000 // Processor clock is pll / 36.5
+#define SYSCTL_SYSDIV_37_5 0xD2800000 // Processor clock is pll / 37.5
+#define SYSCTL_SYSDIV_38_5 0xD3000000 // Processor clock is pll / 38.5
+#define SYSCTL_SYSDIV_39_5 0xD3800000 // Processor clock is pll / 39.5
+#define SYSCTL_SYSDIV_40_5 0xD4000000 // Processor clock is pll / 40.5
+#define SYSCTL_SYSDIV_41_5 0xD4800000 // Processor clock is pll / 41.5
+#define SYSCTL_SYSDIV_42_5 0xD5000000 // Processor clock is pll / 42.5
+#define SYSCTL_SYSDIV_43_5 0xD5800000 // Processor clock is pll / 43.5
+#define SYSCTL_SYSDIV_44_5 0xD6000000 // Processor clock is pll / 44.5
+#define SYSCTL_SYSDIV_45_5 0xD6800000 // Processor clock is pll / 45.5
+#define SYSCTL_SYSDIV_46_5 0xD7000000 // Processor clock is pll / 46.5
+#define SYSCTL_SYSDIV_47_5 0xD7800000 // Processor clock is pll / 47.5
+#define SYSCTL_SYSDIV_48_5 0xD8000000 // Processor clock is pll / 48.5
+#define SYSCTL_SYSDIV_49_5 0xD8800000 // Processor clock is pll / 49.5
+#define SYSCTL_SYSDIV_50_5 0xD9000000 // Processor clock is pll / 50.5
+#define SYSCTL_SYSDIV_51_5 0xD9800000 // Processor clock is pll / 51.5
+#define SYSCTL_SYSDIV_52_5 0xDA000000 // Processor clock is pll / 52.5
+#define SYSCTL_SYSDIV_53_5 0xDA800000 // Processor clock is pll / 53.5
+#define SYSCTL_SYSDIV_54_5 0xDB000000 // Processor clock is pll / 54.5
+#define SYSCTL_SYSDIV_55_5 0xDB800000 // Processor clock is pll / 55.5
+#define SYSCTL_SYSDIV_56_5 0xDC000000 // Processor clock is pll / 56.5
+#define SYSCTL_SYSDIV_57_5 0xDC800000 // Processor clock is pll / 57.5
+#define SYSCTL_SYSDIV_58_5 0xDD000000 // Processor clock is pll / 58.5
+#define SYSCTL_SYSDIV_59_5 0xDD800000 // Processor clock is pll / 59.5
+#define SYSCTL_SYSDIV_60_5 0xDE000000 // Processor clock is pll / 60.5
+#define SYSCTL_SYSDIV_61_5 0xDE800000 // Processor clock is pll / 61.5
+#define SYSCTL_SYSDIV_62_5 0xDF000000 // Processor clock is pll / 62.5
+#define SYSCTL_SYSDIV_63_5 0xDF800000 // Processor clock is pll / 63.5
+#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock
+#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock
+#define SYSCTL_XTAL_1MHZ 0x00000000 // External crystal is 1MHz
+#define SYSCTL_XTAL_1_84MHZ 0x00000040 // External crystal is 1.8432MHz
+#define SYSCTL_XTAL_2MHZ 0x00000080 // External crystal is 2MHz
+#define SYSCTL_XTAL_2_45MHZ 0x000000C0 // External crystal is 2.4576MHz
+#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz
+#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz
+#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz
+#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz
+#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz
+#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz
+#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz
+#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz
+#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz
+#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz
+#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz
+#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz
+#define SYSCTL_XTAL_10MHZ 0x00000400 // External crystal is 10 MHz
+#define SYSCTL_XTAL_12MHZ 0x00000440 // External crystal is 12 MHz
+#define SYSCTL_XTAL_12_2MHZ 0x00000480 // External crystal is 12.288 MHz
+#define SYSCTL_XTAL_13_5MHZ 0x000004C0 // External crystal is 13.56 MHz
+#define SYSCTL_XTAL_14_3MHZ 0x00000500 // External crystal is 14.31818 MHz
+#define SYSCTL_XTAL_16MHZ 0x00000540 // External crystal is 16 MHz
+#define SYSCTL_XTAL_16_3MHZ 0x00000580 // External crystal is 16.384 MHz
+#define SYSCTL_OSC_MAIN 0x00000000 // Osc source is main osc
+#define SYSCTL_OSC_INT 0x00000010 // Osc source is int. osc
+#define SYSCTL_OSC_INT4 0x00000020 // Osc source is int. osc /4
+#define SYSCTL_OSC_INT30 0x00000030 // Osc source is int. 30 KHz
+#define SYSCTL_OSC_EXT4_19 0x80000028 // Osc source is ext. 4.19 MHz
+#define SYSCTL_OSC_EXT32 0x80000038 // Osc source is ext. 32 KHz
+#define SYSCTL_INT_PIOSC_DIS 0x00000004 // Disable interal precision osc.
+#define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator
+#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern unsigned long SysCtlSRAMSizeGet(void);
+extern unsigned long SysCtlFlashSizeGet(void);
+extern tBoolean SysCtlPinPresent(unsigned long ulPin);
+extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral);
+extern void SysCtlPeripheralReset(unsigned long ulPeripheral);
+extern void SysCtlPeripheralEnable(unsigned long ulPeripheral);
+extern void SysCtlPeripheralDisable(unsigned long ulPeripheral);
+extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral);
+extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral);
+extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral);
+extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral);
+extern void SysCtlPeripheralClockGating(tBoolean bEnable);
+extern void SysCtlIntRegister(void (*pfnHandler)(void));
+extern void SysCtlIntUnregister(void);
+extern void SysCtlIntEnable(unsigned long ulInts);
+extern void SysCtlIntDisable(unsigned long ulInts);
+extern void SysCtlIntClear(unsigned long ulInts);
+extern unsigned long SysCtlIntStatus(tBoolean bMasked);
+extern void SysCtlLDOSet(unsigned long ulVoltage);
+extern unsigned long SysCtlLDOGet(void);
+extern void SysCtlLDOConfigSet(unsigned long ulConfig);
+extern void SysCtlReset(void);
+extern void SysCtlSleep(void);
+extern void SysCtlDeepSleep(void);
+extern unsigned long SysCtlResetCauseGet(void);
+extern void SysCtlResetCauseClear(unsigned long ulCauses);
+extern void SysCtlBrownOutConfigSet(unsigned long ulConfig,
+ unsigned long ulDelay);
+extern void SysCtlDelay(unsigned long ulCount);
+extern void SysCtlClockSet(unsigned long ulConfig);
+extern unsigned long SysCtlClockGet(void);
+extern void SysCtlPWMClockSet(unsigned long ulConfig);
+extern unsigned long SysCtlPWMClockGet(void);
+extern void SysCtlADCSpeedSet(unsigned long ulSpeed);
+extern unsigned long SysCtlADCSpeedGet(void);
+extern void SysCtlIOSCVerificationSet(tBoolean bEnable);
+extern void SysCtlMOSCVerificationSet(tBoolean bEnable);
+extern void SysCtlPLLVerificationSet(tBoolean bEnable);
+extern void SysCtlClkVerificationClear(void);
+extern void SysCtlGPIOAHBEnable(unsigned long ulGPIOPeripheral);
+extern void SysCtlGPIOAHBDisable(unsigned long ulGPIOPeripheral);
+extern void SysCtlUSBPLLEnable(void);
+extern void SysCtlUSBPLLDisable(void);
+extern unsigned long SysCtlI2SMClkSet(unsigned long ulInputClock,
+ unsigned long ulMClk);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __SYSCTL_H__
Property changes on: branches/eagle_mmc/src/platform/lm3s/sysctl.h
___________________________________________________________________
Name: svn:executable
+ *
Modified: branches/eagle_mmc/src/platform/lm3s/systick.c
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/systick.c 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lm3s/systick.c 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,262 +1,262 @@
-//*****************************************************************************
-//
-// systick.c - Driver for the SysTick timer in NVIC.
-//
-// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
-// Software License Agreement
-//
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
-//
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws. All rights are reserved. You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program. Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
-//
-// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-//
-// This is part of revision 3740 of the Stellaris Peripheral Driver Library.
-//
-//*****************************************************************************
-
-//*****************************************************************************
-//
-//! \addtogroup systick_api
-//! @{
-//
-//*****************************************************************************
-
-#include "hw_ints.h"
-#include "hw_nvic.h"
-#include "hw_types.h"
-#include "debug.h"
-#include "interrupt.h"
-#include "systick.h"
-
-//*****************************************************************************
-//
-//! Enables the SysTick counter.
-//!
-//! This will start the SysTick counter. If an interrupt handler has been
-//! registered, it will be called when the SysTick counter rolls over.
-//!
-//! \note Calling this function will cause the SysTick counter to (re)commence
-//! counting from its current value. The counter is not automatically reloaded
-//! with the period as specified in a previous call to SysTickPeriodSet(). If
-//! an immediate reload is required, the \b NVIC_ST_CURRENT register must be
-//! written to force this. Any write to this register clears the SysTick
-//! counter to 0 and will cause a reload with the supplied period on the next
-//! clock.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SysTickEnable(void)
-{
- //
- // Enable SysTick.
- //
- HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_CLK_SRC | NVIC_ST_CTRL_ENABLE;
-}
-
-//*****************************************************************************
-//
-//! Disables the SysTick counter.
-//!
-//! This will stop the SysTick counter. If an interrupt handler has been
-//! registered, it will no longer be called until SysTick is restarted.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SysTickDisable(void)
-{
- //
- // Disable SysTick.
- //
- HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_ENABLE);
-}
-
-//*****************************************************************************
-//
-//! Registers an interrupt handler for the SysTick interrupt.
-//!
-//! \param pfnHandler is a pointer to the function to be called when the
-//! SysTick interrupt occurs.
-//!
-//! This sets the handler to be called when a SysTick interrupt occurs.
-//!
-//! \sa IntRegister() for important information about registering interrupt
-//! handlers.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SysTickIntRegister(void (*pfnHandler)(void))
-{
- //
- // Register the interrupt handler, returning an error if an error occurs.
- //
- IntRegister(FAULT_SYSTICK, pfnHandler);
-
- //
- // Enable the SysTick interrupt.
- //
- HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN;
-}
-
-//*****************************************************************************
-//
-//! Unregisters the interrupt handler for the SysTick interrupt.
-//!
-//! This function will clear the handler to be called when a SysTick interrupt
-//! occurs.
-//!
-//! \sa IntRegister() for important information about registering interrupt
-//! handlers.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SysTickIntUnregister(void)
-{
- //
- // Disable the SysTick interrupt.
- //
- HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN);
-
- //
- // Unregister the interrupt handler.
- //
- IntUnregister(FAULT_SYSTICK);
-}
-
-//*****************************************************************************
-//
-//! Enables the SysTick interrupt.
-//!
-//! This function will enable the SysTick interrupt, allowing it to be
-//! reflected to the processor.
-//!
-//! \note The SysTick interrupt handler does not need to clear the SysTick
-//! interrupt source as this is done automatically by NVIC when the interrupt
-//! handler is called.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SysTickIntEnable(void)
-{
- //
- // Enable the SysTick interrupt.
- //
- HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN;
-}
-
-//*****************************************************************************
-//
-//! Disables the SysTick interrupt.
-//!
-//! This function will disable the SysTick interrupt, preventing it from being
-//! reflected to the processor.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SysTickIntDisable(void)
-{
- //
- // Disable the SysTick interrupt.
- //
- HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN);
-}
-
-//*****************************************************************************
-//
-//! Sets the period of the SysTick counter.
-//!
-//! \param ulPeriod is the number of clock ticks in each period of the SysTick
-//! counter; must be between 1 and 16,777,216, inclusive.
-//!
-//! This function sets the rate at which the SysTick counter wraps; this
-//! equates to the number of processor clocks between interrupts.
-//!
-//! \note Calling this function does not cause the SysTick counter to reload
-//! immediately. If an immediate reload is required, the \b NVIC_ST_CURRENT
-//! register must be written. Any write to this register clears the SysTick
-//! counter to 0 and will cause a reload with the \e ulPeriod supplied here on
-//! the next clock after the SysTick is enabled.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SysTickPeriodSet(unsigned long ulPeriod)
-{
- //
- // Check the arguments.
- //
- ASSERT((ulPeriod > 0) && (ulPeriod <= 16777216));
-
- //
- // Set the period of the SysTick counter.
- //
- HWREG(NVIC_ST_RELOAD) = ulPeriod - 1;
-}
-
-//*****************************************************************************
-//
-//! Gets the period of the SysTick counter.
-//!
-//! This function returns the rate at which the SysTick counter wraps; this
-//! equates to the number of processor clocks between interrupts.
-//!
-//! \return Returns the period of the SysTick counter.
-//
-//*****************************************************************************
-unsigned long
-SysTickPeriodGet(void)
-{
- //
- // Return the period of the SysTick counter.
- //
- return(HWREG(NVIC_ST_RELOAD) + 1);
-}
-
-//*****************************************************************************
-//
-//! Gets the current value of the SysTick counter.
-//!
-//! This function returns the current value of the SysTick counter; this will
-//! be a value between the period - 1 and zero, inclusive.
-//!
-//! \return Returns the current value of the SysTick counter.
-//
-//*****************************************************************************
-unsigned long
-SysTickValueGet(void)
-{
- //
- // Return the current value of the SysTick counter.
- //
- return(HWREG(NVIC_ST_CURRENT));
-}
-
-//*****************************************************************************
-//
-// Close the Doxygen group.
-//! @}
-//
-//*****************************************************************************
+//*****************************************************************************
+//
+// systick.c - Driver for the SysTick timer in NVIC.
+//
+// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup systick_api
+//! @{
+//
+//*****************************************************************************
+
+#include "hw_ints.h"
+#include "hw_nvic.h"
+#include "hw_types.h"
+#include "debug.h"
+#include "interrupt.h"
+#include "systick.h"
+
+//*****************************************************************************
+//
+//! Enables the SysTick counter.
+//!
+//! This will start the SysTick counter. If an interrupt handler has been
+//! registered, it will be called when the SysTick counter rolls over.
+//!
+//! \note Calling this function will cause the SysTick counter to (re)commence
+//! counting from its current value. The counter is not automatically reloaded
+//! with the period as specified in a previous call to SysTickPeriodSet(). If
+//! an immediate reload is required, the \b NVIC_ST_CURRENT register must be
+//! written to force this. Any write to this register clears the SysTick
+//! counter to 0 and will cause a reload with the supplied period on the next
+//! clock.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysTickEnable(void)
+{
+ //
+ // Enable SysTick.
+ //
+ HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_CLK_SRC | NVIC_ST_CTRL_ENABLE;
+}
+
+//*****************************************************************************
+//
+//! Disables the SysTick counter.
+//!
+//! This will stop the SysTick counter. If an interrupt handler has been
+//! registered, it will no longer be called until SysTick is restarted.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysTickDisable(void)
+{
+ //
+ // Disable SysTick.
+ //
+ HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_ENABLE);
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the SysTick interrupt.
+//!
+//! \param pfnHandler is a pointer to the function to be called when the
+//! SysTick interrupt occurs.
+//!
+//! This sets the handler to be called when a SysTick interrupt occurs.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysTickIntRegister(void (*pfnHandler)(void))
+{
+ //
+ // Register the interrupt handler, returning an error if an error occurs.
+ //
+ IntRegister(FAULT_SYSTICK, pfnHandler);
+
+ //
+ // Enable the SysTick interrupt.
+ //
+ HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN;
+}
+
+//*****************************************************************************
+//
+//! Unregisters the interrupt handler for the SysTick interrupt.
+//!
+//! This function will clear the handler to be called when a SysTick interrupt
+//! occurs.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysTickIntUnregister(void)
+{
+ //
+ // Disable the SysTick interrupt.
+ //
+ HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(FAULT_SYSTICK);
+}
+
+//*****************************************************************************
+//
+//! Enables the SysTick interrupt.
+//!
+//! This function will enable the SysTick interrupt, allowing it to be
+//! reflected to the processor.
+//!
+//! \note The SysTick interrupt handler does not need to clear the SysTick
+//! interrupt source as this is done automatically by NVIC when the interrupt
+//! handler is called.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysTickIntEnable(void)
+{
+ //
+ // Enable the SysTick interrupt.
+ //
+ HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN;
+}
+
+//*****************************************************************************
+//
+//! Disables the SysTick interrupt.
+//!
+//! This function will disable the SysTick interrupt, preventing it from being
+//! reflected to the processor.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysTickIntDisable(void)
+{
+ //
+ // Disable the SysTick interrupt.
+ //
+ HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN);
+}
+
+//*****************************************************************************
+//
+//! Sets the period of the SysTick counter.
+//!
+//! \param ulPeriod is the number of clock ticks in each period of the SysTick
+//! counter; must be between 1 and 16,777,216, inclusive.
+//!
+//! This function sets the rate at which the SysTick counter wraps; this
+//! equates to the number of processor clocks between interrupts.
+//!
+//! \note Calling this function does not cause the SysTick counter to reload
+//! immediately. If an immediate reload is required, the \b NVIC_ST_CURRENT
+//! register must be written. Any write to this register clears the SysTick
+//! counter to 0 and will cause a reload with the \e ulPeriod supplied here on
+//! the next clock after the SysTick is enabled.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysTickPeriodSet(unsigned long ulPeriod)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulPeriod > 0) && (ulPeriod <= 16777216));
+
+ //
+ // Set the period of the SysTick counter.
+ //
+ HWREG(NVIC_ST_RELOAD) = ulPeriod - 1;
+}
+
+//*****************************************************************************
+//
+//! Gets the period of the SysTick counter.
+//!
+//! This function returns the rate at which the SysTick counter wraps; this
+//! equates to the number of processor clocks between interrupts.
+//!
+//! \return Returns the period of the SysTick counter.
+//
+//*****************************************************************************
+unsigned long
+SysTickPeriodGet(void)
+{
+ //
+ // Return the period of the SysTick counter.
+ //
+ return(HWREG(NVIC_ST_RELOAD) + 1);
+}
+
+//*****************************************************************************
+//
+//! Gets the current value of the SysTick counter.
+//!
+//! This function returns the current value of the SysTick counter; this will
+//! be a value between the period - 1 and zero, inclusive.
+//!
+//! \return Returns the current value of the SysTick counter.
+//
+//*****************************************************************************
+unsigned long
+SysTickValueGet(void)
+{
+ //
+ // Return the current value of the SysTick counter.
+ //
+ return(HWREG(NVIC_ST_CURRENT));
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
Property changes on: branches/eagle_mmc/src/platform/lm3s/systick.c
___________________________________________________________________
Name: svn:executable
+ *
Modified: branches/eagle_mmc/src/platform/lm3s/systick.h
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/systick.h 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lm3s/systick.h 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,66 +1,66 @@
-//*****************************************************************************
-//
-// systick.h - Prototypes for the SysTick driver.
-//
-// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
-// Software License Agreement
-//
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
-//
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws. All rights are reserved. You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program. Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
-//
-// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-//
-// This is part of revision 3740 of the Stellaris Peripheral Driver Library.
-//
-//*****************************************************************************
-
-#ifndef __SYSTICK_H__
-#define __SYSTICK_H__
-
-//*****************************************************************************
-//
-// If building with a C++ compiler, make all of the definitions in this header
-// have a C binding.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-//*****************************************************************************
-//
-// Prototypes for the APIs.
-//
-//*****************************************************************************
-extern void SysTickEnable(void);
-extern void SysTickDisable(void);
-extern void SysTickIntRegister(void (*pfnHandler)(void));
-extern void SysTickIntUnregister(void);
-extern void SysTickIntEnable(void);
-extern void SysTickIntDisable(void);
-extern void SysTickPeriodSet(unsigned long ulPeriod);
-extern unsigned long SysTickPeriodGet(void);
-extern unsigned long SysTickValueGet(void);
-
-//*****************************************************************************
-//
-// Mark the end of the C bindings section for C++ compilers.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-}
-#endif
-
-#endif // __SYSTICK_H__
+//*****************************************************************************
+//
+// systick.h - Prototypes for the SysTick driver.
+//
+// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __SYSTICK_H__
+#define __SYSTICK_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern void SysTickEnable(void);
+extern void SysTickDisable(void);
+extern void SysTickIntRegister(void (*pfnHandler)(void));
+extern void SysTickIntUnregister(void);
+extern void SysTickIntEnable(void);
+extern void SysTickIntDisable(void);
+extern void SysTickPeriodSet(unsigned long ulPeriod);
+extern unsigned long SysTickPeriodGet(void);
+extern unsigned long SysTickValueGet(void);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __SYSTICK_H__
Property changes on: branches/eagle_mmc/src/platform/lm3s/systick.h
___________________________________________________________________
Name: svn:executable
+ *
Modified: branches/eagle_mmc/src/platform/lm3s/timer.c
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/timer.c 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lm3s/timer.c 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,1007 +1,1007 @@
-//*****************************************************************************
-//
-// timer.c - Driver for the timer module.
-//
-// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
-// Software License Agreement
-//
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
-//
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws. All rights are reserved. You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program. Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
-//
-// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-//
-// This is part of revision 3740 of the Stellaris Peripheral Driver Library.
-//
-//*****************************************************************************
-
-//*****************************************************************************
-//
-//! \addtogroup timer_api
-//! @{
-//
-//*****************************************************************************
-
-#include "hw_ints.h"
-#include "hw_memmap.h"
-#include "hw_timer.h"
-#include "hw_types.h"
-#include "debug.h"
-#include "interrupt.h"
-#include "timer.h"
-
-//*****************************************************************************
-//
-//! \internal
-//! Checks a timer base address.
-//!
-//! \param ulBase is the base address of the timer module.
-//!
-//! This function determines if a timer module base address is valid.
-//!
-//! \return Returns \b true if the base address is valid and \b false
-//! otherwise.
-//
-//*****************************************************************************
-#ifdef DEBUG
-static tBoolean
-TimerBaseValid(unsigned long ulBase)
-{
- return((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) ||
- (ulBase == TIMER2_BASE) || (ulBase == TIMER3_BASE));
-}
-#endif
-
-//*****************************************************************************
-//
-//! Enables the timer(s).
-//!
-//! \param ulBase is the base address of the timer module.
-//! \param ulTimer specifies the timer(s) to enable; must be one of \b TIMER_A,
-//! \b TIMER_B, or \b TIMER_BOTH.
-//!
-//! This will enable operation of the timer module. The timer must be
-//! configured before it is enabled.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-TimerEnable(unsigned long ulBase, unsigned long ulTimer)
-{
- //
- // Check the arguments.
- //
- ASSERT(TimerBaseValid(ulBase));
- ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
- (ulTimer == TIMER_BOTH));
-
- //
- // Enable the timer(s) module.
- //
- HWREG(ulBase + TIMER_O_CTL) |= ulTimer & (TIMER_CTL_TAEN | TIMER_CTL_TBEN);
-}
-
-//*****************************************************************************
-//
-//! Disables the timer(s).
-//!
-//! \param ulBase is the base address of the timer module.
-//! \param ulTimer specifies the timer(s) to disable; must be one of
-//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH.
-//!
-//! This will disable operation of the timer module.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-TimerDisable(unsigned long ulBase, unsigned long ulTimer)
-{
- //
- // Check the arguments.
- //
- ASSERT(TimerBaseValid(ulBase));
- ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
- (ulTimer == TIMER_BOTH));
-
- //
- // Disable the timer module.
- //
- HWREG(ulBase + TIMER_O_CTL) &= ~(ulTimer &
- (TIMER_CTL_TAEN | TIMER_CTL_TBEN));
-}
-
-//*****************************************************************************
-//
-//! Configures the timer(s).
-//!
-//! \param ulBase is the base address of the timer module.
-//! \param ulConfig is the configuration for the timer.
-//!
-//! This function configures the operating mode of the timer(s). The timer
-//! module is disabled before being configured, and is left in the disabled
-//! state. The configuration is specified in \e ulConfig as one of the
-//! following values:
-//!
-//! - \b TIMER_CFG_32_BIT_OS - 32-bit one shot timer
-//! - \b TIMER_CFG_32_BIT_PER - 32-bit periodic timer
-//! - \b TIMER_CFG_32_RTC - 32-bit real time clock timer
-//! - \b TIMER_CFG_16_BIT_PAIR - Two 16-bit timers
-//!
-//! When configured for a pair of 16-bit timers, each timer is separately
-//! configured. The first timer is configured by setting \e ulConfig to
-//! the result of a logical OR operation between one of the following values
-//! and \e ulConfig:
-//!
-//! - \b TIMER_CFG_A_ONE_SHOT - 16-bit one shot timer
-//! - \b TIMER_CFG_A_PERIODIC - 16-bit periodic timer
-//! - \b TIMER_CFG_A_CAP_COUNT - 16-bit edge count capture
-//! - \b TIMER_CFG_A_CAP_TIME - 16-bit edge time capture
-//! - \b TIMER_CFG_A_PWM - 16-bit PWM output
-//!
-//! Similarly, the second timer is configured by setting \e ulConfig to
-//! the result of a logical OR operation between one of the corresponding
-//! \b TIMER_CFG_B_* values and \e ulConfig.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-TimerConfigure(unsigned long ulBase, unsigned long ulConfig)
-{
- //
- // Check the arguments.
- //
- ASSERT(TimerBaseValid(ulBase));
- ASSERT((ulConfig == TIMER_CFG_32_BIT_OS) ||
- (ulConfig == TIMER_CFG_32_BIT_PER) ||
- (ulConfig == TIMER_CFG_32_RTC) ||
- ((ulConfig & 0xff000000) == TIMER_CFG_16_BIT_PAIR));
- ASSERT(((ulConfig & 0xff000000) != TIMER_CFG_16_BIT_PAIR) ||
- ((((ulConfig & 0x000000ff) == TIMER_CFG_A_ONE_SHOT) ||
- ((ulConfig & 0x000000ff) == TIMER_CFG_A_PERIODIC) ||
- ((ulConfig & 0x000000ff) == TIMER_CFG_A_CAP_COUNT) ||
- ((ulConfig & 0x000000ff) == TIMER_CFG_A_CAP_TIME) ||
- ((ulConfig & 0x000000ff) == TIMER_CFG_A_PWM)) &&
- (((ulConfig & 0x0000ff00) == TIMER_CFG_B_ONE_SHOT) ||
- ((ulConfig & 0x0000ff00) == TIMER_CFG_B_PERIODIC) ||
- ((ulConfig & 0x0000ff00) == TIMER_CFG_B_CAP_COUNT) ||
- ((ulConfig & 0x0000ff00) == TIMER_CFG_B_CAP_TIME) ||
- ((ulConfig & 0x0000ff00) == TIMER_CFG_B_PWM))));
-
- //
- // Disable the timers.
- //
- HWREG(ulBase + TIMER_O_CTL) &= ~(TIMER_CTL_TAEN | TIMER_CTL_TBEN);
-
- //
- // Set the global timer configuration.
- //
- HWREG(ulBase + TIMER_O_CFG) = ulConfig >> 24;
-
- //
- // Set the configuration of the A and B timers. Note that the B timer
- // configuration is ignored by the hardware in 32-bit modes.
- //
- HWREG(ulBase + TIMER_O_TAMR) = ulConfig & 255;
- HWREG(ulBase + TIMER_O_TBMR) = (ulConfig >> 8) & 255;
-}
-
-//*****************************************************************************
-//
-//! Controls the output level.
-//!
-//! \param ulBase is the base address of the timer module.
-//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A,
-//! \b TIMER_B, or \b TIMER_BOTH.
-//! \param bInvert specifies the output level.
-//!
-//! This function sets the PWM output level for the specified timer. If the
-//! \e bInvert parameter is \b true, then the timer's output will be made
-//! active low; otherwise, it will be made active high.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-TimerControlLevel(unsigned long ulBase, unsigned long ulTimer,
- tBoolean bInvert)
-{
- //
- // Check the arguments.
- //
- ASSERT(TimerBaseValid(ulBase));
- ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
- (ulTimer == TIMER_BOTH));
-
- //
- // Set the output levels as requested.
- //
- ulTimer &= TIMER_CTL_TAPWML | TIMER_CTL_TBPWML;
- HWREG(ulBase + TIMER_O_CTL) = (bInvert ?
- (HWREG(ulBase + TIMER_O_CTL) | ulTimer) :
- (HWREG(ulBase + TIMER_O_CTL) & ~(ulTimer)));
-}
-
-//*****************************************************************************
-//
-//! Enables or disables the trigger output.
-//!
-//! \param ulBase is the base address of the timer module.
-//! \param ulTimer specifies the timer to adjust; must be one of \b TIMER_A,
-//! \b TIMER_B, or \b TIMER_BOTH.
-//! \param bEnable specifies the desired trigger state.
-//!
-//! This function controls the trigger output for the specified timer. If the
-//! \e bEnable parameter is \b true, then the timer's output trigger is
-//! enabled; otherwise it is disabled.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer,
- tBoolean bEnable)
-{
- //
- // Check the arguments.
- //
- ASSERT(TimerBaseValid(ulBase));
- ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
- (ulTimer == TIMER_BOTH));
-
- //
- // Set the trigger output as requested.
- //
- ulTimer &= TIMER_CTL_TAOTE | TIMER_CTL_TBOTE;
- HWREG(ulBase + TIMER_O_CTL) = (bEnable ?
- (HWREG(ulBase + TIMER_O_CTL) | ulTimer) :
- (HWREG(ulBase + TIMER_O_CTL) & ~(ulTimer)));
-}
-
-//*****************************************************************************
-//
-//! Controls the event type.
-//!
-//! \param ulBase is the base address of the timer module.
-//! \param ulTimer specifies the timer(s) to be adjusted; must be one of
-//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH.
-//! \param ulEvent specifies the type of event; must be one of
-//! \b TIMER_EVENT_POS_EDGE, \b TIMER_EVENT_NEG_EDGE, or
-//! \b TIMER_EVENT_BOTH_EDGES.
-//!
-//! This function sets the signal edge(s) that will trigger the timer when in
-//! capture mode.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-TimerControlEvent(unsigned long ulBase, unsigned long ulTimer,
- unsigned long ulEvent)
-{
- //
- // Check the arguments.
- //
- ASSERT(TimerBaseValid(ulBase));
- ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
- (ulTimer == TIMER_BOTH));
-
- //
- // Set the event type.
- //
- ulEvent &= ulTimer & (TIMER_CTL_TAEVENT_M | TIMER_CTL_TBEVENT_M);
- HWREG(ulBase + TIMER_O_CTL) = ((HWREG(ulBase + TIMER_O_CTL) &
- ~(TIMER_CTL_TAEVENT_M |
- TIMER_CTL_TBEVENT_M)) | ulEvent);
-}
-
-//*****************************************************************************
-//
-//! Controls the stall handling.
-//!
-//! \param ulBase is the base address of the timer module.
-//! \param ulTimer specifies the timer(s) to be adjusted; must be one of
-//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH.
-//! \param bStall specifies the response to a stall signal.
-//!
-//! This function controls the stall response for the specified timer. If the
-//! \e bStall parameter is \b true, then the timer will stop counting if the
-//! processor enters debug mode; otherwise the timer will keep running while in
-//! debug mode.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-TimerControlStall(unsigned long ulBase, unsigned long ulTimer,
- tBoolean bStall)
-{
- //
- // Check the arguments.
- //
- ASSERT(TimerBaseValid(ulBase));
- ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
- (ulTimer == TIMER_BOTH));
-
- //
- // Set the stall mode.
- //
- ulTimer &= TIMER_CTL_TASTALL | TIMER_CTL_TBSTALL;
- HWREG(ulBase + TIMER_O_CTL) = (bStall ?
- (HWREG(ulBase + TIMER_O_CTL) | ulTimer) :
- (HWREG(ulBase + TIMER_O_CTL) & ~(ulTimer)));
-}
-
-//*****************************************************************************
-//
-//! Enable RTC counting.
-//!
-//! \param ulBase is the base address of the timer module.
-//!
-//! This function causes the timer to start counting when in RTC mode. If not
-//! configured for RTC mode, this will do nothing.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-TimerRTCEnable(unsigned long ulBase)
-{
- //
- // Check the arguments.
- //
- ASSERT(TimerBaseValid(ulBase));
-
- //
- // Enable RTC counting.
- //
- HWREG(ulBase + TIMER_O_CTL) |= TIMER_CTL_RTCEN;
-}
-
-//*****************************************************************************
-//
-//! Disable RTC counting.
-//!
-//! \param ulBase is the base address of the timer module.
-//!
-//! This function causes the timer to stop counting when in RTC mode.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-TimerRTCDisable(unsigned long ulBase)
-{
- //
- // Check the arguments.
- //
- ASSERT(TimerBaseValid(ulBase));
-
- //
- // Disable RTC counting.
- //
- HWREG(ulBase + TIMER_O_CTL) &= ~(TIMER_CTL_RTCEN);
-}
-
-//*****************************************************************************
-//
-//! Set the timer prescale value.
-//!
-//! \param ulBase is the base address of the timer module.
-//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A,
-//! \b TIMER_B, or \b TIMER_BOTH.
-//! \param ulValue is the timer prescale value; must be between 0 and 255,
-//! inclusive.
-//!
-//! This function sets the value of the input clock prescaler. The prescaler
-//! is only operational when in 16-bit mode and is used to extend the range of
-//! the 16-bit timer modes.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer,
- unsigned long ulValue)
-{
- //
- // Check the arguments.
- //
- ASSERT(TimerBaseValid(ulBase));
- ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
- (ulTimer == TIMER_BOTH));
- ASSERT(ulValue < 256);
-
- //
- // Set the timer A prescaler if requested.
- //
- if(ulTimer & TIMER_A)
- {
- HWREG(ulBase + TIMER_O_TAPR) = ulValue;
- }
-
- //
- // Set the timer B prescaler if requested.
- //
- if(ulTimer & TIMER_B)
- {
- HWREG(ulBase + TIMER_O_TBPR) = ulValue;
- }
-}
-
-//*****************************************************************************
-//
-//! Get the timer prescale value.
-//!
-//! \param ulBase is the base address of the timer module.
-//! \param ulTimer specifies the timer; must be one of \b TIMER_A or
-//! \b TIMER_B.
-//!
-//! This function gets the value of the input clock prescaler. The prescaler
-//! is only operational when in 16-bit mode and is used to extend the range of
-//! the 16-bit timer modes.
-//!
-//! \return The value of the timer prescaler.
-//
-//*****************************************************************************
-unsigned long
-TimerPrescaleGet(unsigned long ulBase, unsigned long ulTimer)
-{
- //
- // Check the arguments.
- //
- ASSERT(TimerBaseValid(ulBase));
- ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
- (ulTimer == TIMER_BOTH));
-
- //
- // Return the appropriate prescale value.
- //
- return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAPR) :
- HWREG(ulBase + TIMER_O_TBPR));
-}
-
-//*****************************************************************************
-//
-//! Sets the timer load value.
-//!
-//! \param ulBase is the base address of the timer module.
-//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A,
-//! \b TIMER_B, or \b TIMER_BOTH. Only \b TIMER_A should be used when the
-//! timer is configured for 32-bit operation.
-//! \param ulValue is the load value.
-//!
-//! This function sets the timer load value; if the timer is running then the
-//! value will be immediately loaded into the timer.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-TimerLoadSet(unsigned long ulBase, unsigned long ulTimer,
- unsigned long ulValue)
-{
- //
- // Check the arguments.
- //
- ASSERT(TimerBaseValid(ulBase));
- ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
- (ulTimer == TIMER_BOTH));
-
- //
- // Set the timer A load value if requested.
- //
- if(ulTimer & TIMER_A)
- {
- HWREG(ulBase + TIMER_O_TAILR) = ulValue;
- }
-
- //
- // Set the timer B load value if requested.
- //
- if(ulTimer & TIMER_B)
- {
- HWREG(ulBase + TIMER_O_TBILR) = ulValue;
- }
-}
-
-//*****************************************************************************
-//
-//! Gets the timer load value.
-//!
-//! \param ulBase is the base address of the timer module.
-//! \param ulTimer specifies the timer; must be one of \b TIMER_A or
-//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured
-//! for 32-bit operation.
-//!
-//! This function gets the currently programmed interval load value for the
-//! specified timer.
-//!
-//! \return Returns the load value for the timer.
-//
-//*****************************************************************************
-unsigned long
-TimerLoadGet(unsigned long ulBase, unsigned long ulTimer)
-{
- //
- // Check the arguments.
- //
- ASSERT(TimerBaseValid(ulBase));
- ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B));
-
- //
- // Return the appropriate load value.
- //
- return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAILR) :
- HWREG(ulBase + TIMER_O_TBILR));
-}
-
-//*****************************************************************************
-//
-//! Gets the current timer value.
-//!
-//! \param ulBase is the base address of the timer module.
-//! \param ulTimer specifies the timer; must be one of \b TIMER_A or
-//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured
-//! for 32-bit operation.
-//!
-//! This function reads the current value of the specified timer.
-//!
-//! \return Returns the current value of the timer.
-//
-//*****************************************************************************
-unsigned long
-TimerValueGet(unsigned long ulBase, unsigned long ulTimer)
-{
- //
- // Check the arguments.
- //
- ASSERT(TimerBaseValid(ulBase));
- ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B));
-
- //
- // Return the appropriate timer value.
- //
- return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAR) :
- HWREG(ulBase + TIMER_O_TBR));
-}
-
-//*****************************************************************************
-//
-//! Sets the timer match value.
-//!
-//! \param ulBase is the base address of the timer module.
-//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A,
-//! \b TIMER_B, or \b TIMER_BOTH. Only \b TIMER_A should be used when the
-//! timer is configured for 32-bit operation.
-//! \param ulValue is the match value.
-//!
-//! This function sets the match value for a timer. This is used in capture
-//! count mode to determine when to interrupt the processor and in PWM mode to
-//! determine the duty cycle of the output signal.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-TimerMatchSet(unsigned long ulBase, unsigned long ulTimer,
- unsigned long ulValue)
-{
- //
- // Check the arguments.
- //
- ASSERT(TimerBaseValid(ulBase));
- ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
- (ulTimer == TIMER_BOTH));
-
- //
- // Set the timer A match value if requested.
- //
- if(ulTimer & TIMER_A)
- {
- HWREG(ulBase + TIMER_O_TAMATCHR) = ulValue;
- }
-
- //
- // Set the timer B match value if requested.
- //
- if(ulTimer & TIMER_B)
- {
- HWREG(ulBase + TIMER_O_TBMATCHR) = ulValue;
- }
-}
-
-//*****************************************************************************
-//
-//! Gets the timer match value.
-//!
-//! \param ulBase is the base address of the timer module.
-//! \param ulTimer specifies the timer; must be one of \b TIMER_A or
-//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured
-//! for 32-bit operation.
-//!
-//! This function gets the match value for the specified timer.
-//!
-//! \return Returns the match value for the timer.
-//
-//*****************************************************************************
-unsigned long
-TimerMatchGet(unsigned long ulBase, unsigned long ulTimer)
-{
- //
- // Check the arguments.
- //
- ASSERT(TimerBaseValid(ulBase));
- ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B));
-
- //
- // Return the appropriate match value.
- //
- return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAMATCHR) :
- HWREG(ulBase + TIMER_O_TBMATCHR));
-}
-
-//*****************************************************************************
-//
-//! Registers an interrupt handler for the timer interrupt.
-//!
-//! \param ulBase is the base address of the timer module.
-//! \param ulTimer specifies the timer(s); must be one of \b TIMER_A,
-//! \b TIMER_B, or \b TIMER_BOTH.
-//! \param pfnHandler is a pointer to the function to be called when the timer
-//! interrupt occurs.
-//!
-//! This sets the handler to be called when a timer interrupt occurs. This
-//! will enable the global interrupt in the interrupt controller; specific
-//! timer interrupts must be enabled via TimerIntEnable(). It is the interrupt
-//! handler's responsibility to clear the interrupt source via TimerIntClear().
-//!
-//! \sa IntRegister() for important information about registering interrupt
-//! handlers.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-TimerIntRegister(unsigned long ulBase, unsigned long ulTimer,
- void (*pfnHandler)(void))
-{
- //
- // Check the arguments.
- //
- ASSERT(TimerBaseValid(ulBase));
- ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
- (ulTimer == TIMER_BOTH));
-
- //
- // Get the interrupt number for this timer module.
- //
- ulBase = ((ulBase == TIMER0_BASE) ? INT_TIMER0A :
- ((ulBase == TIMER1_BASE) ? INT_TIMER1A :
- ((ulBase == TIMER2_BASE) ? INT_TIMER2A : INT_TIMER3A)));
-
- //
- // Register an interrupt handler for timer A if requested.
- //
- if(ulTimer & TIMER_A)
- {
- //
- // Register the interrupt handler.
- //
- IntRegister(ulBase, pfnHandler);
-
- //
- // Enable the interrupt.
- //
- IntEnable(ulBase);
- }
-
- //
- // Register an interrupt handler for timer B if requested.
- //
- if(ulTimer & TIMER_B)
- {
- //
- // Register the interrupt handler.
- //
- IntRegister(ulBase + 1, pfnHandler);
-
- //
- // Enable the interrupt.
- //
- IntEnable(ulBase + 1);
- }
-}
-
-//*****************************************************************************
-//
-//! Unregisters an interrupt handler for the timer interrupt.
-//!
-//! \param ulBase is the base address of the timer module.
-//! \param ulTimer specifies the timer(s); must be one of \b TIMER_A,
-//! \b TIMER_B, or \b TIMER_BOTH.
-//!
-//! This function will clear the handler to be called when a timer interrupt
-//! occurs. This will also mask off the interrupt in the interrupt controller
-//! so that the interrupt handler no longer is called.
-//!
-//! \sa IntRegister() for important information about registering interrupt
-//! handlers.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer)
-{
- //
- // Check the arguments.
- //
- ASSERT(TimerBaseValid(ulBase));
- ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
- (ulTimer == TIMER_BOTH));
-
- //
- // Get the interrupt number for this timer module.
- //
- ulBase = ((ulBase == TIMER0_BASE) ? INT_TIMER0A :
- ((ulBase == TIMER1_BASE) ? INT_TIMER1A :
- ((ulBase == TIMER2_BASE) ? INT_TIMER2A : INT_TIMER3A)));
-
- //
- // Unregister the interrupt handler for timer A if requested.
- //
- if(ulTimer & TIMER_A)
- {
- //
- // Disable the interrupt.
- //
- IntDisable(ulBase);
-
- //
- // Unregister the interrupt handler.
- //
- IntUnregister(ulBase);
- }
-
- //
- // Unregister the interrupt handler for timer B if requested.
- //
- if(ulTimer & TIMER_B)
- {
- //
- // Disable the interrupt.
- //
- IntDisable(ulBase + 1);
-
- //
- // Unregister the interrupt handler.
- //
- IntUnregister(ulBase + 1);
- }
-}
-
-//*****************************************************************************
-//
-//! Enables individual timer interrupt sources.
-//!
-//! \param ulBase is the base address of the timer module.
-//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.
-//!
-//! Enables the indicated timer interrupt sources. Only the sources that are
-//! enabled can be reflected to the processor interrupt; disabled sources have
-//! no effect on the processor.
-//!
-//! The \e ulIntFlags parameter must be the logical OR of any combination of
-//! the following:
-//!
-//! - \b TIMER_CAPB_EVENT - Capture B event interrupt
-//! - \b TIMER_CAPB_MATCH - Capture B match interrupt
-//! - \b TIMER_TIMB_TIMEOUT - Timer B timeout interrupt
-//! - \b TIMER_RTC_MATCH - RTC interrupt mask
-//! - \b TIMER_CAPA_EVENT - Capture A event interrupt
-//! - \b TIMER_CAPA_MATCH - Capture A match interrupt
-//! - \b TIMER_TIMA_TIMEOUT - Timer A timeout interrupt
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
-{
- //
- // Check the arguments.
- //
- ASSERT(TimerBaseValid(ulBase));
-
- //
- // Enable the specified interrupts.
- //
- HWREG(ulBase + TIMER_O_IMR) |= ulIntFlags;
-}
-
-//*****************************************************************************
-//
-//! Disables individual timer interrupt sources.
-//!
-//! \param ulBase is the base address of the timer module.
-//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled.
-//!
-//! Disables the indicated timer interrupt sources. Only the sources that are
-//! enabled can be reflected to the processor interrupt; disabled sources have
-//! no effect on the processor.
-//!
-//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
-//! parameter to TimerIntEnable().
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
-{
- //
- // Check the arguments.
- //
- ASSERT(TimerBaseValid(ulBase));
-
- //
- // Disable the specified interrupts.
- //
- HWREG(ulBase + TIMER_O_IMR) &= ~(ulIntFlags);
-}
-
-//*****************************************************************************
-//
-//! Gets the current interrupt status.
-//!
-//! \param ulBase is the base address of the timer module.
-//! \param bMasked is false if the raw interrupt status is required and true if
-//! the masked interrupt status is required.
-//!
-//! This returns the interrupt status for the timer module. Either the raw
-//! interrupt status or the status of interrupts that are allowed to reflect to
-//! the processor can be returned.
-//!
-//! \return The current interrupt status, enumerated as a bit field of
-//! values described in TimerIntEnable().
-//
-//*****************************************************************************
-unsigned long
-TimerIntStatus(unsigned long ulBase, tBoolean bMasked)
-{
- //
- // Check the arguments.
- //
- ASSERT(TimerBaseValid(ulBase));
-
- //
- // Return either the interrupt status or the raw interrupt status as
- // requested.
- //
- return(bMasked ? HWREG(ulBase + TIMER_O_MIS) :
- HWREG(ulBase + TIMER_O_RIS));
-}
-
-//*****************************************************************************
-//
-//! Clears timer interrupt sources.
-//!
-//! \param ulBase is the base address of the timer module.
-//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
-//!
-//! The specified timer interrupt sources are cleared, so that they no longer
-//! assert. This must be done in the interrupt handler to keep it from being
-//! called again immediately upon exit.
-//!
-//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
-//! parameter to TimerIntEnable().
-//!
-//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
-//! several clock cycles before the interrupt source is actually cleared.
-//! Therefore, it is recommended that the interrupt source be cleared early in
-//! the interrupt handler (as opposed to the very last action) to avoid
-//! returning from the interrupt handler before the interrupt source is
-//! actually cleared. Failure to do so may result in the interrupt handler
-//! being immediately reentered (since NVIC still sees the interrupt source
-//! asserted).
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags)
-{
- //
- // Check the arguments.
- //
- ASSERT(TimerBaseValid(ulBase));
-
- //
- // Clear the requested interrupt sources.
- //
- HWREG(ulBase + TIMER_O_ICR) = ulIntFlags;
-}
-
-//*****************************************************************************
-//
-// Puts the timer into its reset state.
-//
-// \param ulBase is the base address of the timer module.
-//
-// The specified timer is disabled, and all its interrupts are disabled,
-// cleared, and unregistered. Then the timer registers are set to their reset
-// value.
-//
-// \return None.
-//
-//*****************************************************************************
-#ifndef DEPRECATED
-void
-TimerQuiesce(unsigned long ulBase)
-{
- //
- // Check the arguments.
- //
- ASSERT(TimerBaseValid(ulBase));
-
- //
- // Disable the timer.
- //
- HWREG(ulBase + TIMER_O_CTL) = TIMER_RV_CTL;
-
- //
- // Disable all the timer interrupts.
- //
- HWREG(ulBase + TIMER_O_IMR) = TIMER_RV_IMR;
-
- //
- // Clear all the timer interrupts.
- //
- HWREG(ulBase + TIMER_O_ICR) = 0xFFFFFFFF;
-
- //
- // Unregister the interrupt handler. This also disables interrupts to the
- // core.
- //
- TimerIntUnregister(ulBase, TIMER_BOTH);
-
- //
- // Set all the registers to their reset value.
- //
- HWREG(ulBase + TIMER_O_CFG) = TIMER_RV_CFG;
- HWREG(ulBase + TIMER_O_TAMR) = TIMER_RV_TAMR;
- HWREG(ulBase + TIMER_O_TBMR) = TIMER_RV_TBMR;
- HWREG(ulBase + TIMER_O_RIS) = TIMER_RV_RIS;
- HWREG(ulBase + TIMER_O_MIS) = TIMER_RV_MIS;
- HWREG(ulBase + TIMER_O_TAILR) = TIMER_RV_TAILR;
- HWREG(ulBase + TIMER_O_TBILR) = TIMER_RV_TBILR;
- HWREG(ulBase + TIMER_O_TAMATCHR) = TIMER_RV_TAMATCHR;
- HWREG(ulBase + TIMER_O_TBMATCHR) = TIMER_RV_TBMATCHR;
- HWREG(ulBase + TIMER_O_TAPR) = TIMER_RV_TAPR;
- HWREG(ulBase + TIMER_O_TBPR) = TIMER_RV_TBPR;
- HWREG(ulBase + TIMER_O_TAPMR) = TIMER_RV_TAPMR;
- HWREG(ulBase + TIMER_O_TBPMR) = TIMER_RV_TBPMR;
- HWREG(ulBase + TIMER_O_TAR) = TIMER_RV_TAR;
- HWREG(ulBase + TIMER_O_TBR) = TIMER_RV_TBR;
-}
-#endif // DEPRECATED
-
-//*****************************************************************************
-//
-// Close the Doxygen group.
-//! @}
-//
-//*****************************************************************************
+//*****************************************************************************
+//
+// timer.c - Driver for the timer module.
+//
+// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup timer_api
+//! @{
+//
+//*****************************************************************************
+
+#include "hw_ints.h"
+#include "hw_memmap.h"
+#include "hw_timer.h"
+#include "hw_types.h"
+#include "debug.h"
+#include "interrupt.h"
+#include "timer.h"
+
+//*****************************************************************************
+//
+//! \internal
+//! Checks a timer base address.
+//!
+//! \param ulBase is the base address of the timer module.
+//!
+//! This function determines if a timer module base address is valid.
+//!
+//! \return Returns \b true if the base address is valid and \b false
+//! otherwise.
+//
+//*****************************************************************************
+#ifdef DEBUG
+static tBoolean
+TimerBaseValid(unsigned long ulBase)
+{
+ return((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) ||
+ (ulBase == TIMER2_BASE) || (ulBase == TIMER3_BASE));
+}
+#endif
+
+//*****************************************************************************
+//
+//! Enables the timer(s).
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer(s) to enable; must be one of \b TIMER_A,
+//! \b TIMER_B, or \b TIMER_BOTH.
+//!
+//! This will enable operation of the timer module. The timer must be
+//! configured before it is enabled.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerEnable(unsigned long ulBase, unsigned long ulTimer)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
+ (ulTimer == TIMER_BOTH));
+
+ //
+ // Enable the timer(s) module.
+ //
+ HWREG(ulBase + TIMER_O_CTL) |= ulTimer & (TIMER_CTL_TAEN | TIMER_CTL_TBEN);
+}
+
+//*****************************************************************************
+//
+//! Disables the timer(s).
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer(s) to disable; must be one of
+//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH.
+//!
+//! This will disable operation of the timer module.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerDisable(unsigned long ulBase, unsigned long ulTimer)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
+ (ulTimer == TIMER_BOTH));
+
+ //
+ // Disable the timer module.
+ //
+ HWREG(ulBase + TIMER_O_CTL) &= ~(ulTimer &
+ (TIMER_CTL_TAEN | TIMER_CTL_TBEN));
+}
+
+//*****************************************************************************
+//
+//! Configures the timer(s).
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulConfig is the configuration for the timer.
+//!
+//! This function configures the operating mode of the timer(s). The timer
+//! module is disabled before being configured, and is left in the disabled
+//! state. The configuration is specified in \e ulConfig as one of the
+//! following values:
+//!
+//! - \b TIMER_CFG_32_BIT_OS - 32-bit one shot timer
+//! - \b TIMER_CFG_32_BIT_PER - 32-bit periodic timer
+//! - \b TIMER_CFG_32_RTC - 32-bit real time clock timer
+//! - \b TIMER_CFG_16_BIT_PAIR - Two 16-bit timers
+//!
+//! When configured for a pair of 16-bit timers, each timer is separately
+//! configured. The first timer is configured by setting \e ulConfig to
+//! the result of a logical OR operation between one of the following values
+//! and \e ulConfig:
+//!
+//! - \b TIMER_CFG_A_ONE_SHOT - 16-bit one shot timer
+//! - \b TIMER_CFG_A_PERIODIC - 16-bit periodic timer
+//! - \b TIMER_CFG_A_CAP_COUNT - 16-bit edge count capture
+//! - \b TIMER_CFG_A_CAP_TIME - 16-bit edge time capture
+//! - \b TIMER_CFG_A_PWM - 16-bit PWM output
+//!
+//! Similarly, the second timer is configured by setting \e ulConfig to
+//! the result of a logical OR operation between one of the corresponding
+//! \b TIMER_CFG_B_* values and \e ulConfig.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerConfigure(unsigned long ulBase, unsigned long ulConfig)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulConfig == TIMER_CFG_32_BIT_OS) ||
+ (ulConfig == TIMER_CFG_32_BIT_PER) ||
+ (ulConfig == TIMER_CFG_32_RTC) ||
+ ((ulConfig & 0xff000000) == TIMER_CFG_16_BIT_PAIR));
+ ASSERT(((ulConfig & 0xff000000) != TIMER_CFG_16_BIT_PAIR) ||
+ ((((ulConfig & 0x000000ff) == TIMER_CFG_A_ONE_SHOT) ||
+ ((ulConfig & 0x000000ff) == TIMER_CFG_A_PERIODIC) ||
+ ((ulConfig & 0x000000ff) == TIMER_CFG_A_CAP_COUNT) ||
+ ((ulConfig & 0x000000ff) == TIMER_CFG_A_CAP_TIME) ||
+ ((ulConfig & 0x000000ff) == TIMER_CFG_A_PWM)) &&
+ (((ulConfig & 0x0000ff00) == TIMER_CFG_B_ONE_SHOT) ||
+ ((ulConfig & 0x0000ff00) == TIMER_CFG_B_PERIODIC) ||
+ ((ulConfig & 0x0000ff00) == TIMER_CFG_B_CAP_COUNT) ||
+ ((ulConfig & 0x0000ff00) == TIMER_CFG_B_CAP_TIME) ||
+ ((ulConfig & 0x0000ff00) == TIMER_CFG_B_PWM))));
+
+ //
+ // Disable the timers.
+ //
+ HWREG(ulBase + TIMER_O_CTL) &= ~(TIMER_CTL_TAEN | TIMER_CTL_TBEN);
+
+ //
+ // Set the global timer configuration.
+ //
+ HWREG(ulBase + TIMER_O_CFG) = ulConfig >> 24;
+
+ //
+ // Set the configuration of the A and B timers. Note that the B timer
+ // configuration is ignored by the hardware in 32-bit modes.
+ //
+ HWREG(ulBase + TIMER_O_TAMR) = ulConfig & 255;
+ HWREG(ulBase + TIMER_O_TBMR) = (ulConfig >> 8) & 255;
+}
+
+//*****************************************************************************
+//
+//! Controls the output level.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A,
+//! \b TIMER_B, or \b TIMER_BOTH.
+//! \param bInvert specifies the output level.
+//!
+//! This function sets the PWM output level for the specified timer. If the
+//! \e bInvert parameter is \b true, then the timer's output will be made
+//! active low; otherwise, it will be made active high.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerControlLevel(unsigned long ulBase, unsigned long ulTimer,
+ tBoolean bInvert)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
+ (ulTimer == TIMER_BOTH));
+
+ //
+ // Set the output levels as requested.
+ //
+ ulTimer &= TIMER_CTL_TAPWML | TIMER_CTL_TBPWML;
+ HWREG(ulBase + TIMER_O_CTL) = (bInvert ?
+ (HWREG(ulBase + TIMER_O_CTL) | ulTimer) :
+ (HWREG(ulBase + TIMER_O_CTL) & ~(ulTimer)));
+}
+
+//*****************************************************************************
+//
+//! Enables or disables the trigger output.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer to adjust; must be one of \b TIMER_A,
+//! \b TIMER_B, or \b TIMER_BOTH.
+//! \param bEnable specifies the desired trigger state.
+//!
+//! This function controls the trigger output for the specified timer. If the
+//! \e bEnable parameter is \b true, then the timer's output trigger is
+//! enabled; otherwise it is disabled.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer,
+ tBoolean bEnable)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
+ (ulTimer == TIMER_BOTH));
+
+ //
+ // Set the trigger output as requested.
+ //
+ ulTimer &= TIMER_CTL_TAOTE | TIMER_CTL_TBOTE;
+ HWREG(ulBase + TIMER_O_CTL) = (bEnable ?
+ (HWREG(ulBase + TIMER_O_CTL) | ulTimer) :
+ (HWREG(ulBase + TIMER_O_CTL) & ~(ulTimer)));
+}
+
+//*****************************************************************************
+//
+//! Controls the event type.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer(s) to be adjusted; must be one of
+//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH.
+//! \param ulEvent specifies the type of event; must be one of
+//! \b TIMER_EVENT_POS_EDGE, \b TIMER_EVENT_NEG_EDGE, or
+//! \b TIMER_EVENT_BOTH_EDGES.
+//!
+//! This function sets the signal edge(s) that will trigger the timer when in
+//! capture mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerControlEvent(unsigned long ulBase, unsigned long ulTimer,
+ unsigned long ulEvent)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
+ (ulTimer == TIMER_BOTH));
+
+ //
+ // Set the event type.
+ //
+ ulEvent &= ulTimer & (TIMER_CTL_TAEVENT_M | TIMER_CTL_TBEVENT_M);
+ HWREG(ulBase + TIMER_O_CTL) = ((HWREG(ulBase + TIMER_O_CTL) &
+ ~(TIMER_CTL_TAEVENT_M |
+ TIMER_CTL_TBEVENT_M)) | ulEvent);
+}
+
+//*****************************************************************************
+//
+//! Controls the stall handling.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer(s) to be adjusted; must be one of
+//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH.
+//! \param bStall specifies the response to a stall signal.
+//!
+//! This function controls the stall response for the specified timer. If the
+//! \e bStall parameter is \b true, then the timer will stop counting if the
+//! processor enters debug mode; otherwise the timer will keep running while in
+//! debug mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerControlStall(unsigned long ulBase, unsigned long ulTimer,
+ tBoolean bStall)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
+ (ulTimer == TIMER_BOTH));
+
+ //
+ // Set the stall mode.
+ //
+ ulTimer &= TIMER_CTL_TASTALL | TIMER_CTL_TBSTALL;
+ HWREG(ulBase + TIMER_O_CTL) = (bStall ?
+ (HWREG(ulBase + TIMER_O_CTL) | ulTimer) :
+ (HWREG(ulBase + TIMER_O_CTL) & ~(ulTimer)));
+}
+
+//*****************************************************************************
+//
+//! Enable RTC counting.
+//!
+//! \param ulBase is the base address of the timer module.
+//!
+//! This function causes the timer to start counting when in RTC mode. If not
+//! configured for RTC mode, this will do nothing.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerRTCEnable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+
+ //
+ // Enable RTC counting.
+ //
+ HWREG(ulBase + TIMER_O_CTL) |= TIMER_CTL_RTCEN;
+}
+
+//*****************************************************************************
+//
+//! Disable RTC counting.
+//!
+//! \param ulBase is the base address of the timer module.
+//!
+//! This function causes the timer to stop counting when in RTC mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerRTCDisable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+
+ //
+ // Disable RTC counting.
+ //
+ HWREG(ulBase + TIMER_O_CTL) &= ~(TIMER_CTL_RTCEN);
+}
+
+//*****************************************************************************
+//
+//! Set the timer prescale value.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A,
+//! \b TIMER_B, or \b TIMER_BOTH.
+//! \param ulValue is the timer prescale value; must be between 0 and 255,
+//! inclusive.
+//!
+//! This function sets the value of the input clock prescaler. The prescaler
+//! is only operational when in 16-bit mode and is used to extend the range of
+//! the 16-bit timer modes.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer,
+ unsigned long ulValue)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
+ (ulTimer == TIMER_BOTH));
+ ASSERT(ulValue < 256);
+
+ //
+ // Set the timer A prescaler if requested.
+ //
+ if(ulTimer & TIMER_A)
+ {
+ HWREG(ulBase + TIMER_O_TAPR) = ulValue;
+ }
+
+ //
+ // Set the timer B prescaler if requested.
+ //
+ if(ulTimer & TIMER_B)
+ {
+ HWREG(ulBase + TIMER_O_TBPR) = ulValue;
+ }
+}
+
+//*****************************************************************************
+//
+//! Get the timer prescale value.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer; must be one of \b TIMER_A or
+//! \b TIMER_B.
+//!
+//! This function gets the value of the input clock prescaler. The prescaler
+//! is only operational when in 16-bit mode and is used to extend the range of
+//! the 16-bit timer modes.
+//!
+//! \return The value of the timer prescaler.
+//
+//*****************************************************************************
+unsigned long
+TimerPrescaleGet(unsigned long ulBase, unsigned long ulTimer)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
+ (ulTimer == TIMER_BOTH));
+
+ //
+ // Return the appropriate prescale value.
+ //
+ return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAPR) :
+ HWREG(ulBase + TIMER_O_TBPR));
+}
+
+//*****************************************************************************
+//
+//! Sets the timer load value.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A,
+//! \b TIMER_B, or \b TIMER_BOTH. Only \b TIMER_A should be used when the
+//! timer is configured for 32-bit operation.
+//! \param ulValue is the load value.
+//!
+//! This function sets the timer load value; if the timer is running then the
+//! value will be immediately loaded into the timer.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerLoadSet(unsigned long ulBase, unsigned long ulTimer,
+ unsigned long ulValue)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
+ (ulTimer == TIMER_BOTH));
+
+ //
+ // Set the timer A load value if requested.
+ //
+ if(ulTimer & TIMER_A)
+ {
+ HWREG(ulBase + TIMER_O_TAILR) = ulValue;
+ }
+
+ //
+ // Set the timer B load value if requested.
+ //
+ if(ulTimer & TIMER_B)
+ {
+ HWREG(ulBase + TIMER_O_TBILR) = ulValue;
+ }
+}
+
+//*****************************************************************************
+//
+//! Gets the timer load value.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer; must be one of \b TIMER_A or
+//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured
+//! for 32-bit operation.
+//!
+//! This function gets the currently programmed interval load value for the
+//! specified timer.
+//!
+//! \return Returns the load value for the timer.
+//
+//*****************************************************************************
+unsigned long
+TimerLoadGet(unsigned long ulBase, unsigned long ulTimer)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B));
+
+ //
+ // Return the appropriate load value.
+ //
+ return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAILR) :
+ HWREG(ulBase + TIMER_O_TBILR));
+}
+
+//*****************************************************************************
+//
+//! Gets the current timer value.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer; must be one of \b TIMER_A or
+//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured
+//! for 32-bit operation.
+//!
+//! This function reads the current value of the specified timer.
+//!
+//! \return Returns the current value of the timer.
+//
+//*****************************************************************************
+unsigned long
+TimerValueGet(unsigned long ulBase, unsigned long ulTimer)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B));
+
+ //
+ // Return the appropriate timer value.
+ //
+ return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAR) :
+ HWREG(ulBase + TIMER_O_TBR));
+}
+
+//*****************************************************************************
+//
+//! Sets the timer match value.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A,
+//! \b TIMER_B, or \b TIMER_BOTH. Only \b TIMER_A should be used when the
+//! timer is configured for 32-bit operation.
+//! \param ulValue is the match value.
+//!
+//! This function sets the match value for a timer. This is used in capture
+//! count mode to determine when to interrupt the processor and in PWM mode to
+//! determine the duty cycle of the output signal.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerMatchSet(unsigned long ulBase, unsigned long ulTimer,
+ unsigned long ulValue)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
+ (ulTimer == TIMER_BOTH));
+
+ //
+ // Set the timer A match value if requested.
+ //
+ if(ulTimer & TIMER_A)
+ {
+ HWREG(ulBase + TIMER_O_TAMATCHR) = ulValue;
+ }
+
+ //
+ // Set the timer B match value if requested.
+ //
+ if(ulTimer & TIMER_B)
+ {
+ HWREG(ulBase + TIMER_O_TBMATCHR) = ulValue;
+ }
+}
+
+//*****************************************************************************
+//
+//! Gets the timer match value.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer; must be one of \b TIMER_A or
+//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured
+//! for 32-bit operation.
+//!
+//! This function gets the match value for the specified timer.
+//!
+//! \return Returns the match value for the timer.
+//
+//*****************************************************************************
+unsigned long
+TimerMatchGet(unsigned long ulBase, unsigned long ulTimer)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B));
+
+ //
+ // Return the appropriate match value.
+ //
+ return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAMATCHR) :
+ HWREG(ulBase + TIMER_O_TBMATCHR));
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the timer interrupt.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer(s); must be one of \b TIMER_A,
+//! \b TIMER_B, or \b TIMER_BOTH.
+//! \param pfnHandler is a pointer to the function to be called when the timer
+//! interrupt occurs.
+//!
+//! This sets the handler to be called when a timer interrupt occurs. This
+//! will enable the global interrupt in the interrupt controller; specific
+//! timer interrupts must be enabled via TimerIntEnable(). It is the interrupt
+//! handler's responsibility to clear the interrupt source via TimerIntClear().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerIntRegister(unsigned long ulBase, unsigned long ulTimer,
+ void (*pfnHandler)(void))
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
+ (ulTimer == TIMER_BOTH));
+
+ //
+ // Get the interrupt number for this timer module.
+ //
+ ulBase = ((ulBase == TIMER0_BASE) ? INT_TIMER0A :
+ ((ulBase == TIMER1_BASE) ? INT_TIMER1A :
+ ((ulBase == TIMER2_BASE) ? INT_TIMER2A : INT_TIMER3A)));
+
+ //
+ // Register an interrupt handler for timer A if requested.
+ //
+ if(ulTimer & TIMER_A)
+ {
+ //
+ // Register the interrupt handler.
+ //
+ IntRegister(ulBase, pfnHandler);
+
+ //
+ // Enable the interrupt.
+ //
+ IntEnable(ulBase);
+ }
+
+ //
+ // Register an interrupt handler for timer B if requested.
+ //
+ if(ulTimer & TIMER_B)
+ {
+ //
+ // Register the interrupt handler.
+ //
+ IntRegister(ulBase + 1, pfnHandler);
+
+ //
+ // Enable the interrupt.
+ //
+ IntEnable(ulBase + 1);
+ }
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for the timer interrupt.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer(s); must be one of \b TIMER_A,
+//! \b TIMER_B, or \b TIMER_BOTH.
+//!
+//! This function will clear the handler to be called when a timer interrupt
+//! occurs. This will also mask off the interrupt in the interrupt controller
+//! so that the interrupt handler no longer is called.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
+ (ulTimer == TIMER_BOTH));
+
+ //
+ // Get the interrupt number for this timer module.
+ //
+ ulBase = ((ulBase == TIMER0_BASE) ? INT_TIMER0A :
+ ((ulBase == TIMER1_BASE) ? INT_TIMER1A :
+ ((ulBase == TIMER2_BASE) ? INT_TIMER2A : INT_TIMER3A)));
+
+ //
+ // Unregister the interrupt handler for timer A if requested.
+ //
+ if(ulTimer & TIMER_A)
+ {
+ //
+ // Disable the interrupt.
+ //
+ IntDisable(ulBase);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(ulBase);
+ }
+
+ //
+ // Unregister the interrupt handler for timer B if requested.
+ //
+ if(ulTimer & TIMER_B)
+ {
+ //
+ // Disable the interrupt.
+ //
+ IntDisable(ulBase + 1);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(ulBase + 1);
+ }
+}
+
+//*****************************************************************************
+//
+//! Enables individual timer interrupt sources.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.
+//!
+//! Enables the indicated timer interrupt sources. Only the sources that are
+//! enabled can be reflected to the processor interrupt; disabled sources have
+//! no effect on the processor.
+//!
+//! The \e ulIntFlags parameter must be the logical OR of any combination of
+//! the following:
+//!
+//! - \b TIMER_CAPB_EVENT - Capture B event interrupt
+//! - \b TIMER_CAPB_MATCH - Capture B match interrupt
+//! - \b TIMER_TIMB_TIMEOUT - Timer B timeout interrupt
+//! - \b TIMER_RTC_MATCH - RTC interrupt mask
+//! - \b TIMER_CAPA_EVENT - Capture A event interrupt
+//! - \b TIMER_CAPA_MATCH - Capture A match interrupt
+//! - \b TIMER_TIMA_TIMEOUT - Timer A timeout interrupt
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+
+ //
+ // Enable the specified interrupts.
+ //
+ HWREG(ulBase + TIMER_O_IMR) |= ulIntFlags;
+}
+
+//*****************************************************************************
+//
+//! Disables individual timer interrupt sources.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled.
+//!
+//! Disables the indicated timer interrupt sources. Only the sources that are
+//! enabled can be reflected to the processor interrupt; disabled sources have
+//! no effect on the processor.
+//!
+//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
+//! parameter to TimerIntEnable().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+
+ //
+ // Disable the specified interrupts.
+ //
+ HWREG(ulBase + TIMER_O_IMR) &= ~(ulIntFlags);
+}
+
+//*****************************************************************************
+//
+//! Gets the current interrupt status.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param bMasked is false if the raw interrupt status is required and true if
+//! the masked interrupt status is required.
+//!
+//! This returns the interrupt status for the timer module. Either the raw
+//! interrupt status or the status of interrupts that are allowed to reflect to
+//! the processor can be returned.
+//!
+//! \return The current interrupt status, enumerated as a bit field of
+//! values described in TimerIntEnable().
+//
+//*****************************************************************************
+unsigned long
+TimerIntStatus(unsigned long ulBase, tBoolean bMasked)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+
+ //
+ // Return either the interrupt status or the raw interrupt status as
+ // requested.
+ //
+ return(bMasked ? HWREG(ulBase + TIMER_O_MIS) :
+ HWREG(ulBase + TIMER_O_RIS));
+}
+
+//*****************************************************************************
+//
+//! Clears timer interrupt sources.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
+//!
+//! The specified timer interrupt sources are cleared, so that they no longer
+//! assert. This must be done in the interrupt handler to keep it from being
+//! called again immediately upon exit.
+//!
+//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
+//! parameter to TimerIntEnable().
+//!
+//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
+//! several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared. Failure to do so may result in the interrupt handler
+//! being immediately reentered (since NVIC still sees the interrupt source
+//! asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+
+ //
+ // Clear the requested interrupt sources.
+ //
+ HWREG(ulBase + TIMER_O_ICR) = ulIntFlags;
+}
+
+//*****************************************************************************
+//
+// Puts the timer into its reset state.
+//
+// \param ulBase is the base address of the timer module.
+//
+// The specified timer is disabled, and all its interrupts are disabled,
+// cleared, and unregistered. Then the timer registers are set to their reset
+// value.
+//
+// \return None.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+void
+TimerQuiesce(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+
+ //
+ // Disable the timer.
+ //
+ HWREG(ulBase + TIMER_O_CTL) = TIMER_RV_CTL;
+
+ //
+ // Disable all the timer interrupts.
+ //
+ HWREG(ulBase + TIMER_O_IMR) = TIMER_RV_IMR;
+
+ //
+ // Clear all the timer interrupts.
+ //
+ HWREG(ulBase + TIMER_O_ICR) = 0xFFFFFFFF;
+
+ //
+ // Unregister the interrupt handler. This also disables interrupts to the
+ // core.
+ //
+ TimerIntUnregister(ulBase, TIMER_BOTH);
+
+ //
+ // Set all the registers to their reset value.
+ //
+ HWREG(ulBase + TIMER_O_CFG) = TIMER_RV_CFG;
+ HWREG(ulBase + TIMER_O_TAMR) = TIMER_RV_TAMR;
+ HWREG(ulBase + TIMER_O_TBMR) = TIMER_RV_TBMR;
+ HWREG(ulBase + TIMER_O_RIS) = TIMER_RV_RIS;
+ HWREG(ulBase + TIMER_O_MIS) = TIMER_RV_MIS;
+ HWREG(ulBase + TIMER_O_TAILR) = TIMER_RV_TAILR;
+ HWREG(ulBase + TIMER_O_TBILR) = TIMER_RV_TBILR;
+ HWREG(ulBase + TIMER_O_TAMATCHR) = TIMER_RV_TAMATCHR;
+ HWREG(ulBase + TIMER_O_TBMATCHR) = TIMER_RV_TBMATCHR;
+ HWREG(ulBase + TIMER_O_TAPR) = TIMER_RV_TAPR;
+ HWREG(ulBase + TIMER_O_TBPR) = TIMER_RV_TBPR;
+ HWREG(ulBase + TIMER_O_TAPMR) = TIMER_RV_TAPMR;
+ HWREG(ulBase + TIMER_O_TBPMR) = TIMER_RV_TBPMR;
+ HWREG(ulBase + TIMER_O_TAR) = TIMER_RV_TAR;
+ HWREG(ulBase + TIMER_O_TBR) = TIMER_RV_TBR;
+}
+#endif // DEPRECATED
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
Property changes on: branches/eagle_mmc/src/platform/lm3s/timer.c
___________________________________________________________________
Name: svn:executable
+ *
Modified: branches/eagle_mmc/src/platform/lm3s/timer.h
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/timer.h 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lm3s/timer.h 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,153 +1,153 @@
-//*****************************************************************************
-//
-// timer.h - Prototypes for the timer module
-//
-// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
-// Software License Agreement
-//
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
-//
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws. All rights are reserved. You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program. Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
-//
-// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-//
-// This is part of revision 3740 of the Stellaris Peripheral Driver Library.
-//
-//*****************************************************************************
-
-#ifndef __TIMER_H__
-#define __TIMER_H__
-
-//*****************************************************************************
-//
-// If building with a C++ compiler, make all of the definitions in this header
-// have a C binding.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-//*****************************************************************************
-//
-// Values that can be passed to TimerConfigure as the ulConfig parameter.
-//
-//*****************************************************************************
-#define TIMER_CFG_32_BIT_OS 0x00000001 // 32-bit one-shot timer
-#define TIMER_CFG_32_BIT_PER 0x00000002 // 32-bit periodic timer
-#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer
-#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers
-#define TIMER_CFG_A_ONE_SHOT 0x00000001 // Timer A one-shot timer
-#define TIMER_CFG_A_PERIODIC 0x00000002 // Timer A periodic timer
-#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter
-#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer
-#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output
-#define TIMER_CFG_B_ONE_SHOT 0x00000100 // Timer B one-shot timer
-#define TIMER_CFG_B_PERIODIC 0x00000200 // Timer B periodic timer
-#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter
-#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer
-#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output
-
-//*****************************************************************************
-//
-// Values that can be passed to TimerIntEnable, TimerIntDisable, and
-// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus.
-//
-//*****************************************************************************
-#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt
-#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt
-#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt
-#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask
-#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt
-#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt
-#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt
-
-//*****************************************************************************
-//
-// Values that can be passed to TimerControlEvent as the ulEvent parameter.
-//
-//*****************************************************************************
-#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges
-#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges
-#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges
-
-//*****************************************************************************
-//
-// Values that can be passed to most of the timer APIs as the ulTimer
-// parameter.
-//
-//*****************************************************************************
-#define TIMER_A 0x000000ff // Timer A
-#define TIMER_B 0x0000ff00 // Timer B
-#define TIMER_BOTH 0x0000ffff // Timer Both
-
-//*****************************************************************************
-//
-// Prototypes for the APIs.
-//
-//*****************************************************************************
-extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer);
-extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer);
-extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig);
-extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer,
- tBoolean bInvert);
-extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer,
- tBoolean bEnable);
-extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer,
- unsigned long ulEvent);
-extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer,
- tBoolean bStall);
-extern void TimerRTCEnable(unsigned long ulBase);
-extern void TimerRTCDisable(unsigned long ulBase);
-extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer,
- unsigned long ulValue);
-extern unsigned long TimerPrescaleGet(unsigned long ulBase,
- unsigned long ulTimer);
-extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer,
- unsigned long ulValue);
-extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer);
-extern unsigned long TimerValueGet(unsigned long ulBase,
- unsigned long ulTimer);
-extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer,
- unsigned long ulValue);
-extern unsigned long TimerMatchGet(unsigned long ulBase,
- unsigned long ulTimer);
-extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer,
- void (*pfnHandler)(void));
-extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer);
-extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
-extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
-extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked);
-extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags);
-
-//*****************************************************************************
-//
-// TimerQuiesce() has been deprecated. SysCtlPeripheralReset() should be used
-// instead to return the timer to its reset state.
-//
-//*****************************************************************************
-#ifndef DEPRECATED
-extern void TimerQuiesce(unsigned long ulBase);
-#endif
-
-//*****************************************************************************
-//
-// Mark the end of the C bindings section for C++ compilers.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-}
-#endif
-
-#endif // __TIMER_H__
+//*****************************************************************************
+//
+// timer.h - Prototypes for the timer module
+//
+// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __TIMER_H__
+#define __TIMER_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to TimerConfigure as the ulConfig parameter.
+//
+//*****************************************************************************
+#define TIMER_CFG_32_BIT_OS 0x00000001 // 32-bit one-shot timer
+#define TIMER_CFG_32_BIT_PER 0x00000002 // 32-bit periodic timer
+#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer
+#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers
+#define TIMER_CFG_A_ONE_SHOT 0x00000001 // Timer A one-shot timer
+#define TIMER_CFG_A_PERIODIC 0x00000002 // Timer A periodic timer
+#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter
+#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer
+#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output
+#define TIMER_CFG_B_ONE_SHOT 0x00000100 // Timer B one-shot timer
+#define TIMER_CFG_B_PERIODIC 0x00000200 // Timer B periodic timer
+#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter
+#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer
+#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output
+
+//*****************************************************************************
+//
+// Values that can be passed to TimerIntEnable, TimerIntDisable, and
+// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus.
+//
+//*****************************************************************************
+#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt
+#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt
+#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt
+#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask
+#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt
+#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt
+#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt
+
+//*****************************************************************************
+//
+// Values that can be passed to TimerControlEvent as the ulEvent parameter.
+//
+//*****************************************************************************
+#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges
+#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges
+#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges
+
+//*****************************************************************************
+//
+// Values that can be passed to most of the timer APIs as the ulTimer
+// parameter.
+//
+//*****************************************************************************
+#define TIMER_A 0x000000ff // Timer A
+#define TIMER_B 0x0000ff00 // Timer B
+#define TIMER_BOTH 0x0000ffff // Timer Both
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer);
+extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer);
+extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig);
+extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer,
+ tBoolean bInvert);
+extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer,
+ tBoolean bEnable);
+extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer,
+ unsigned long ulEvent);
+extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer,
+ tBoolean bStall);
+extern void TimerRTCEnable(unsigned long ulBase);
+extern void TimerRTCDisable(unsigned long ulBase);
+extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer,
+ unsigned long ulValue);
+extern unsigned long TimerPrescaleGet(unsigned long ulBase,
+ unsigned long ulTimer);
+extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer,
+ unsigned long ulValue);
+extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer);
+extern unsigned long TimerValueGet(unsigned long ulBase,
+ unsigned long ulTimer);
+extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer,
+ unsigned long ulValue);
+extern unsigned long TimerMatchGet(unsigned long ulBase,
+ unsigned long ulTimer);
+extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer,
+ void (*pfnHandler)(void));
+extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer);
+extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
+extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
+extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked);
+extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags);
+
+//*****************************************************************************
+//
+// TimerQuiesce() has been deprecated. SysCtlPeripheralReset() should be used
+// instead to return the timer to its reset state.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+extern void TimerQuiesce(unsigned long ulBase);
+#endif
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __TIMER_H__
Property changes on: branches/eagle_mmc/src/platform/lm3s/timer.h
___________________________________________________________________
Name: svn:executable
+ *
Added: branches/eagle_mmc/src/platform/lm3s/uart.c
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/uart.c 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lm3s/uart.c 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,1621 @@
+//*****************************************************************************
+//
+// uart.c - Driver for the UART.
+//
+// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup uart_api
+//! @{
+//
+//*****************************************************************************
+
+#include "hw_ints.h"
+#include "hw_memmap.h"
+#include "hw_sysctl.h"
+#include "hw_types.h"
+#include "hw_uart.h"
+#include "debug.h"
+#include "interrupt.h"
+#include "uart.h"
+
+//*****************************************************************************
+//
+// The system clock divider defining the maximum baud rate supported by the
+// UART.
+//
+//*****************************************************************************
+#define UART_CLK_DIVIDER ((CLASS_IS_SANDSTORM || \
+ (CLASS_IS_FURY && REVISION_IS_A2) || \
+ (CLASS_IS_DUSTDEVIL && REVISION_IS_A0)) ? \
+ 16 : 8)
+
+//*****************************************************************************
+//
+//! \internal
+//! Checks a UART base address.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! This function determines if a UART port base address is valid.
+//!
+//! \return Returns \b true if the base address is valid and \b false
+//! otherwise.
+//
+//*****************************************************************************
+#ifdef DEBUG
+static tBoolean
+UARTBaseValid(unsigned long ulBase)
+{
+ return((ulBase == UART0_BASE) || (ulBase == UART1_BASE) ||
+ (ulBase == UART2_BASE));
+}
+#endif
+
+//*****************************************************************************
+//
+//! Sets the type of parity.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param ulParity specifies the type of parity to use.
+//!
+//! Sets the type of parity to use for transmitting and expect when receiving.
+//! The \e ulParity parameter must be one of \b UART_CONFIG_PAR_NONE,
+//! \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD, \b UART_CONFIG_PAR_ONE,
+//! or \b UART_CONFIG_PAR_ZERO. The last two allow direct control of the
+//! parity bit; it will always be either be one or zero based on the mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTParityModeSet(unsigned long ulBase, unsigned long ulParity)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+ ASSERT((ulParity == UART_CONFIG_PAR_NONE) ||
+ (ulParity == UART_CONFIG_PAR_EVEN) ||
+ (ulParity == UART_CONFIG_PAR_ODD) ||
+ (ulParity == UART_CONFIG_PAR_ONE) ||
+ (ulParity == UART_CONFIG_PAR_ZERO));
+
+ //
+ // Set the parity mode.
+ //
+ HWREG(ulBase + UART_O_LCRH) = ((HWREG(ulBase + UART_O_LCRH) &
+ ~(UART_LCRH_SPS | UART_LCRH_EPS |
+ UART_LCRH_PEN)) | ulParity);
+}
+
+//*****************************************************************************
+//
+//! Gets the type of parity currently being used.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! This function gets the type of parity used for transmitting data, and
+//! expected when receiving data.
+//!
+//! \return Returns the current parity settings, specified as one of
+//! \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD,
+//! \b UART_CONFIG_PAR_ONE, or \b UART_CONFIG_PAR_ZERO.
+//
+//*****************************************************************************
+unsigned long
+UARTParityModeGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Return the current parity setting.
+ //
+ return(HWREG(ulBase + UART_O_LCRH) &
+ (UART_LCRH_SPS | UART_LCRH_EPS | UART_LCRH_PEN));
+}
+
+//*****************************************************************************
+//
+//! Sets the FIFO level at which interrupts are generated.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param ulTxLevel is the transmit FIFO interrupt level, specified as one of
+//! \b UART_FIFO_TX1_8, \b UART_FIFO_TX2_8, \b UART_FIFO_TX4_8,
+//! \b UART_FIFO_TX6_8, or \b UART_FIFO_TX7_8.
+//! \param ulRxLevel is the receive FIFO interrupt level, specified as one of
+//! \b UART_FIFO_RX1_8, \b UART_FIFO_RX2_8, \b UART_FIFO_RX4_8,
+//! \b UART_FIFO_RX6_8, or \b UART_FIFO_RX7_8.
+//!
+//! This function sets the FIFO level at which transmit and receive interrupts
+//! will be generated.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel,
+ unsigned long ulRxLevel)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+ ASSERT((ulTxLevel == UART_FIFO_TX1_8) ||
+ (ulTxLevel == UART_FIFO_TX2_8) ||
+ (ulTxLevel == UART_FIFO_TX4_8) ||
+ (ulTxLevel == UART_FIFO_TX6_8) ||
+ (ulTxLevel == UART_FIFO_TX7_8));
+ ASSERT((ulRxLevel == UART_FIFO_RX1_8) ||
+ (ulRxLevel == UART_FIFO_RX2_8) ||
+ (ulRxLevel == UART_FIFO_RX4_8) ||
+ (ulRxLevel == UART_FIFO_RX6_8) ||
+ (ulRxLevel == UART_FIFO_RX7_8));
+
+ //
+ // Set the FIFO interrupt levels.
+ //
+ HWREG(ulBase + UART_O_IFLS) = ulTxLevel | ulRxLevel;
+}
+
+//*****************************************************************************
+//
+//! Gets the FIFO level at which interrupts are generated.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param pulTxLevel is a pointer to storage for the transmit FIFO level,
+//! returned as one of \b UART_FIFO_TX1_8, \b UART_FIFO_TX2_8,
+//! \b UART_FIFO_TX4_8, \b UART_FIFO_TX6_8, or UART_FIFO_TX7_8.
+//! \param pulRxLevel is a pointer to storage for the receive FIFO level,
+//! returned as one of \b UART_FIFO_RX1_8, \b UART_FIFO_RX2_8,
+//! \b UART_FIFO_RX4_8, \b UART_FIFO_RX6_8, or \b UART_FIFO_RX7_8.
+//!
+//! This function gets the FIFO level at which transmit and receive interrupts
+//! will be generated.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel,
+ unsigned long *pulRxLevel)
+{
+ unsigned long ulTemp;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Read the FIFO level register.
+ //
+ ulTemp = HWREG(ulBase + UART_O_IFLS);
+
+ //
+ // Extract the transmit and receive FIFO levels.
+ //
+ *pulTxLevel = ulTemp & UART_IFLS_TX_M;
+ *pulRxLevel = ulTemp & UART_IFLS_RX_M;
+}
+
+//*****************************************************************************
+//
+//! Sets the configuration of a UART.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param ulUARTClk is the rate of the clock supplied to the UART module.
+//! \param ulBaud is the desired baud rate.
+//! \param ulConfig is the data format for the port (number of data bits,
+//! number of stop bits, and parity).
+//!
+//! This function will configure the UART for operation in the specified data
+//! format. The baud rate is provided in the \e ulBaud parameter and the data
+//! format in the \e ulConfig parameter.
+//!
+//! The \e ulConfig parameter is the logical OR of three values: the number of
+//! data bits, the number of stop bits, and the parity. \b UART_CONFIG_WLEN_8,
+//! \b UART_CONFIG_WLEN_7, \b UART_CONFIG_WLEN_6, and \b UART_CONFIG_WLEN_5
+//! select from eight to five data bits per byte (respectively).
+//! \b UART_CONFIG_STOP_ONE and \b UART_CONFIG_STOP_TWO select one or two stop
+//! bits (respectively). \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN,
+//! \b UART_CONFIG_PAR_ODD, \b UART_CONFIG_PAR_ONE, and \b UART_CONFIG_PAR_ZERO
+//! select the parity mode (no parity bit, even parity bit, odd parity bit,
+//! parity bit always one, and parity bit always zero, respectively).
+//!
+//! The peripheral clock will be the same as the processor clock. This will be
+//! the value returned by SysCtlClockGet(), or it can be explicitly hard coded
+//! if it is constant and known (to save the code/execution overhead of a call
+//! to SysCtlClockGet()).
+//!
+//! This function replaces the original UARTConfigSet() API and performs the
+//! same actions. A macro is provided in <tt>uart.h</tt> to map the original
+//! API to this API.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTConfigSetExpClk(unsigned long ulBase, unsigned long ulUARTClk,
+ unsigned long ulBaud, unsigned long ulConfig)
+{
+ unsigned long ulDiv;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+ ASSERT(ulBaud != 0);
+ ASSERT(ulUARTClk >= (ulBaud * UART_CLK_DIVIDER));
+
+ //
+ // Stop the UART.
+ //
+ UARTDisable(ulBase);
+
+ //
+ // Is the required baud rate greater than the maximum rate supported
+ // without the use of high speed mode?
+ //
+ if((ulBaud * 16) > ulUARTClk)
+ {
+ //
+ // Enable high speed mode.
+ //
+ HWREG(ulBase + UART_O_CTL) |= UART_CTL_HSE;
+
+ //
+ // Half the supplied baud rate to compensate for enabling high speed
+ // mode. This allows the following code to be common to both cases.
+ //
+ ulBaud /= 2;
+ }
+ else
+ {
+ //
+ // Disable high speed mode.
+ //
+ HWREG(ulBase + UART_O_CTL) &= ~(UART_CTL_HSE);
+ }
+
+ //
+ // Compute the fractional baud rate divider.
+ //
+ ulDiv = (((ulUARTClk * 8) / ulBaud) + 1) / 2;
+
+ //
+ // Set the baud rate.
+ //
+ HWREG(ulBase + UART_O_IBRD) = ulDiv / 64;
+ HWREG(ulBase + UART_O_FBRD) = ulDiv % 64;
+
+ //
+ // Set parity, data length, and number of stop bits.
+ //
+ HWREG(ulBase + UART_O_LCRH) = ulConfig;
+
+ //
+ // Clear the flags register.
+ //
+ HWREG(ulBase + UART_O_FR) = 0;
+
+ //
+ // Start the UART.
+ //
+ UARTEnable(ulBase);
+}
+
+//*****************************************************************************
+//
+//! Gets the current configuration of a UART.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param ulUARTClk is the rate of the clock supplied to the UART module.
+//! \param pulBaud is a pointer to storage for the baud rate.
+//! \param pulConfig is a pointer to storage for the data format.
+//!
+//! The baud rate and data format for the UART is determined, given an
+//! explicitly provided peripheral clock (hence the ExpClk suffix). The
+//! returned baud rate is the actual baud rate; it may not be the exact baud
+//! rate requested or an ``official'' baud rate. The data format returned in
+//! \e pulConfig is enumerated the same as the \e ulConfig parameter of
+//! UARTConfigSetExpClk().
+//!
+//! The peripheral clock will be the same as the processor clock. This will be
+//! the value returned by SysCtlClockGet(), or it can be explicitly hard coded
+//! if it is constant and known (to save the code/execution overhead of a call
+//! to SysCtlClockGet()).
+//!
+//! This function replaces the original UARTConfigGet() API and performs the
+//! same actions. A macro is provided in <tt>uart.h</tt> to map the original
+//! API to this API.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTConfigGetExpClk(unsigned long ulBase, unsigned long ulUARTClk,
+ unsigned long *pulBaud, unsigned long *pulConfig)
+{
+ unsigned long ulInt, ulFrac;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Compute the baud rate.
+ //
+ ulInt = HWREG(ulBase + UART_O_IBRD);
+ ulFrac = HWREG(ulBase + UART_O_FBRD);
+ *pulBaud = (ulUARTClk * 4) / ((64 * ulInt) + ulFrac);
+
+ //
+ // See if high speed mode enabled.
+ //
+ if(HWREG(ulBase + UART_O_CTL) & UART_CTL_HSE)
+ {
+ //
+ // High speed mode is enabled so the actual baud rate is actually
+ // double what was just calculated.
+ //
+ *pulBaud *= 2;
+ }
+
+ //
+ // Get the parity, data length, and number of stop bits.
+ //
+ *pulConfig = (HWREG(ulBase + UART_O_LCRH) &
+ (UART_LCRH_SPS | UART_LCRH_WLEN_M | UART_LCRH_STP2 |
+ UART_LCRH_EPS | UART_LCRH_PEN));
+}
+
+//*****************************************************************************
+//
+//! Enables transmitting and receiving.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! Sets the UARTEN, TXE, and RXE bits, and enables the transmit and receive
+//! FIFOs.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTEnable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Enable the FIFO.
+ //
+ HWREG(ulBase + UART_O_LCRH) |= UART_LCRH_FEN;
+
+ //
+ // Enable RX, TX, and the UART.
+ //
+ HWREG(ulBase + UART_O_CTL) |= (UART_CTL_UARTEN | UART_CTL_TXE |
+ UART_CTL_RXE);
+}
+
+//*****************************************************************************
+//
+//! Disables transmitting and receiving.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! Clears the UARTEN, TXE, and RXE bits, then waits for the end of
+//! transmission of the current character, and flushes the transmit FIFO.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTDisable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Wait for end of TX.
+ //
+ while(HWREG(ulBase + UART_O_FR) & UART_FR_BUSY)
+ {
+ }
+
+ //
+ // Disable the FIFO.
+ //
+ HWREG(ulBase + UART_O_LCRH) &= ~(UART_LCRH_FEN);
+
+ //
+ // Disable the UART.
+ //
+ HWREG(ulBase + UART_O_CTL) &= ~(UART_CTL_UARTEN | UART_CTL_TXE |
+ UART_CTL_RXE);
+}
+
+//*****************************************************************************
+//
+//! Enables the transmit and receive FIFOs.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! This functions enables the transmit and receive FIFOs in the UART.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTFIFOEnable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Enable the FIFO.
+ //
+ HWREG(ulBase + UART_O_LCRH) |= UART_LCRH_FEN;
+}
+
+//*****************************************************************************
+//
+//! Disables the transmit and receive FIFOs.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! This functions disables the transmit and receive FIFOs in the UART.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTFIFODisable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Disable the FIFO.
+ //
+ HWREG(ulBase + UART_O_LCRH) &= ~(UART_LCRH_FEN);
+}
+
+//*****************************************************************************
+//
+//! Enables SIR (IrDA) mode on the specified UART.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param bLowPower indicates if SIR Low Power Mode is to be used.
+//!
+//! Enables the SIREN control bit for IrDA mode on the UART. If the
+//! \e bLowPower flag is set, then SIRLP bit will also be set.
+//!
+//! \note SIR (IrDA) operation is not supported on Sandstorm-class devices.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTEnableSIR(unsigned long ulBase, tBoolean bLowPower)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Enable SIR and SIRLP (if appropriate).
+ //
+ if(bLowPower)
+ {
+ HWREG(ulBase + UART_O_CTL) |= (UART_CTL_SIREN | UART_CTL_SIRLP);
+ }
+ else
+ {
+ HWREG(ulBase + UART_O_CTL) |= (UART_CTL_SIREN);
+ }
+}
+
+//*****************************************************************************
+//
+//! Disables SIR (IrDA) mode on the specified UART.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! Clears the SIREN (IrDA) and SIRLP (Low Power) bits.
+//!
+//! \note SIR (IrDA) operation is not supported on Sandstorm-class devices.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTDisableSIR(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Disable SIR and SIRLP (if appropriate).
+ //
+ HWREG(ulBase + UART_O_CTL) &= ~(UART_CTL_SIREN | UART_CTL_SIRLP);
+}
+
+//*****************************************************************************
+//
+//! Enables ISO 7816 smart card mode on the specified UART.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! Enables the SMART control bit for ISO 7816 smart card mode on the UART.
+//! This call also sets 8 bit word length and even parity as required by ISO
+//! 7816.
+//!
+//! \note The availability of ISO 7816 smart card mode varies with the
+//! Stellaris part and UART in use. Please consult the datasheet for the part
+//! you are using to determine whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTSmartCardEnable(unsigned long ulBase)
+{
+ unsigned long ulVal;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL);
+ ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE) ||
+ (ulBase == UART2_BASE));
+
+ //
+ // Set 8 bit word length, even parity, 2 stop bits (even though the STP2
+ // bit is ignored when in smartcard mode, this lets the caller read back
+ // the actual setting in use).
+ //
+ ulVal = HWREG(ulBase + UART_O_LCRH);
+ ulVal &= ~(UART_LCRH_SPS | UART_LCRH_EPS | UART_LCRH_PEN |
+ UART_LCRH_WLEN_M);
+ ulVal |= UART_LCRH_WLEN_8 | UART_LCRH_PEN | UART_LCRH_EPS | UART_LCRH_STP2;
+ HWREG(ulBase + UART_O_LCRH) = ulVal;
+
+ //
+ // Enable SMART mode.
+ //
+ HWREG(ulBase + UART_O_CTL) |= UART_CTL_SMART;
+}
+
+//*****************************************************************************
+//
+//! Disables ISO 7816 smart card mode on the specified UART.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! Clears the SMART (ISO 7816 smart card) bits in the UART control register.
+//!
+//! \note The availability of ISO 7816 smart card mode varies with the
+//! Stellaris part and UART in use. Please consult the datasheet for the part
+//! you are using to determine whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTSmartCardDisable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL);
+ ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE) ||
+ (ulBase == UART2_BASE));
+
+ //
+ // Disable the SMART bit.
+ //
+ HWREG(ulBase + UART_O_CTL) &= ~UART_CTL_SMART;
+}
+
+//*****************************************************************************
+//
+//! Sets the states of the DTR and/or RTS modem control signals.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param ulControl is a bit-mapped flag indicating which modem control bits
+//! should be set.
+//!
+//! Sets the states of the DTR or RTS modem handshake outputs from the UART.
+//!
+//! The \e ulControl parameter is the logical OR of any of the following:
+//!
+//! - \b UART_OUTPUT_DTR - The Modem Control DTR signal
+//! - \b UART_OUTPUT_RTS - The Modem Control RTS signal
+//!
+//! \note The availability of hardware modem handshake signals varies with the
+//! Stellaris part and UART in use. Please consult the datasheet for the part
+//! you are using to determine whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTModemControlSet(unsigned long ulBase, unsigned long ulControl)
+{
+ unsigned long ulTemp;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL);
+ ASSERT(ulBase == UART1_BASE);
+ ASSERT((ulControl & ~(UART_OUTPUT_RTS | UART_OUTPUT_DTR)) == 0);
+
+ //
+ // Set the appropriate modem control output bits.
+ //
+ ulTemp = HWREG(ulBase + UART_O_CTL);
+ ulTemp |= (ulControl & (UART_OUTPUT_RTS | UART_OUTPUT_DTR));
+ HWREG(ulBase + UART_O_CTL) = ulTemp;
+}
+
+//*****************************************************************************
+//
+//! Clears the states of the DTR and/or RTS modem control signals.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param ulControl is a bit-mapped flag indicating which modem control bits
+//! should be set.
+//!
+//! Clears the states of the DTR or RTS modem handshake outputs from the UART.
+//!
+//! The \e ulControl parameter is the logical OR of any of the following:
+//!
+//! - \b UART_OUTPUT_DTR - The Modem Control DTR signal
+//! - \b UART_OUTPUT_RTS - The Modem Control RTS signal
+//!
+//! \note The availability of hardware modem handshake signals varies with the
+//! Stellaris part and UART in use. Please consult the datasheet for the part
+//! you are using to determine whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTModemControlClear(unsigned long ulBase, unsigned long ulControl)
+{
+ unsigned long ulTemp;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL);
+ ASSERT(ulBase == UART1_BASE);
+ ASSERT((ulControl & ~(UART_OUTPUT_RTS | UART_OUTPUT_DTR)) == 0);
+
+ //
+ // Set the appropriate modem control output bits.
+ //
+ ulTemp = HWREG(ulBase + UART_O_CTL);
+ ulTemp &= ~(ulControl & (UART_OUTPUT_RTS | UART_OUTPUT_DTR));
+ HWREG(ulBase + UART_O_CTL) = ulTemp;
+}
+
+//*****************************************************************************
+//
+//! Gets the states of the DTR and RTS modem control signals.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! Returns the current states of each of the two UART modem control signals,
+//! DTR and RTS.
+//!
+//! \note The availability of hardware modem handshake signals varies with the
+//! Stellaris part and UART in use. Please consult the datasheet for the part
+//! you are using to determine whether this support is available.
+//!
+//! \return Returns the states of the handshake output signals. This will be a
+//! logical logical OR combination of values \b UART_OUTPUT_RTS and
+//! \b UART_OUTPUT_DTR where the presence of each flag indicates that the
+//! associated signal is asserted.
+//
+//*****************************************************************************
+unsigned long
+UARTModemControlGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL);
+ ASSERT(ulBase == UART1_BASE);
+
+ return(HWREG(ulBase + UART_O_CTL) & (UART_OUTPUT_RTS | UART_OUTPUT_DTR));
+}
+
+//*****************************************************************************
+//
+//! Gets the states of the RI, DCD, DSR and CTS modem status signals.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! Returns the current states of each of the four UART modem status signals,
+//! RI, DCD, DSR and CTS.
+//!
+//! \note The availability of hardware modem handshake signals varies with the
+//! Stellaris part and UART in use. Please consult the datasheet for the part
+//! you are using to determine whether this support is available.
+//!
+//! \return Returns the states of the handshake output signals. This will be a
+//! logical logical OR combination of values \b UART_INPUT_RI, \b
+//! UART_INPUT_DCD, \b UART_INPUT_CTS and \b UART_INPUT_DSR where the
+//! presence of each flag indicates that the associated signal is asserted.
+//
+//*****************************************************************************
+unsigned long
+UARTModemStatusGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL);
+ ASSERT(ulBase == UART1_BASE);
+
+ return(HWREG(ulBase + UART_O_FR) & (UART_INPUT_RI | UART_INPUT_DCD |
+ UART_INPUT_CTS | UART_INPUT_DSR));
+}
+
+//*****************************************************************************
+//
+//! Sets the UART hardware flow control mode to be used.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param ulMode indicates the flow control modes to be used. This is a
+//! logical OR combination of values \b UART_FLOWCONTROL_TX and \b
+//! UART_FLOWCONTROL_RX to enable hardware transmit (CTS) and receive (RTS)
+//! flow control or \b UART_FLOWCONTROL_NONE to disable hardware flow control.
+//!
+//! Sets the required hardware flow control modes. If \e ulMode contains
+//! flag \b UART_FLOWCONTROL_TX, data is only transmitted if the incoming CTS
+//! signal is asserted. If \e ulMode contains flag \b UART_FLOWCONTROL_RX,
+//! the RTS output is controlled by the hardware and is asserted only when
+//! there is space available in the receive FIFO. If no hardware flow control
+//! is required, UART_FLOWCONTROL_NONE should be passed.
+//!
+//! \note The availability of hardware flow control varies with the Stellaris
+//! part and UART in use. Please consult the datasheet for the part you are
+//! using to determine whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTFlowControlSet(unsigned long ulBase, unsigned long ulMode)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL);
+ ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE) ||
+ (ulBase == UART2_BASE));
+ ASSERT((ulMode & ~(UART_FLOWCONTROL_TX | UART_FLOWCONTROL_RX)) == 0);
+
+ //
+ // Set the flow control mode as requested.
+ //
+ HWREG(ulBase + UART_O_CTL) = ((HWREG(ulBase + UART_O_CTL) &
+ ~(UART_FLOWCONTROL_TX |
+ UART_FLOWCONTROL_RX)) | ulMode);
+}
+
+//*****************************************************************************
+//
+//! Returns the UART hardware flow control mode currently in use.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! Returns the current hardware flow control mode.
+//!
+//! \note The availability of hardware flow control varies with the Stellaris
+//! part and UART in use. Please consult the datasheet for the part you are
+//! using to determine whether this support is available.
+//!
+//! \return Returns the current flow control mode in use. This is a
+//! logical OR combination of values \b UART_FLOWCONTROL_TX if transmit
+//! (CTS) flow control is enabled and \b UART_FLOWCONTROL_RX if receive (RTS)
+//! flow control is in use. If hardware flow control is disabled, \b
+//! UART_FLOWCONTROL_NONE will be returned.
+//
+//*****************************************************************************
+unsigned long
+UARTFlowControlGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL);
+ ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE) ||
+ (ulBase == UART2_BASE));
+
+ return(HWREG(ulBase + UART_O_CTL) & (UART_FLOWCONTROL_TX |
+ UART_FLOWCONTROL_RX));
+}
+
+//*****************************************************************************
+//
+//! Sets the operating mode for the UART transmit interrupt.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param ulMode is the operating mode for the transmit interrupt. It may be
+//! \b UART_TXINT_MODE_EOT to trigger interrupts when the transmitter is idle
+//! or \b UART_TXINT_MODE_FIFO to trigger based on the current transmit FIFO
+//! level.
+//!
+//! This function allows the mode of the UART transmit interrupt to be set. By
+//! default, the transmit interrupt is asserted when the FIFO level falls past
+//! a threshold set via a call to UARTFIFOLevelSet(). Alternatively, if this
+//! function is called with \e ulMode set to \b UART_TXINT_MODE_EOT, the
+//! transmit interrupt will only be asserted once the transmitter is completely
+//! idle - the transmit FIFO is empty and all bits, including any stop bits,
+//! have cleared the transmitter.
+//!
+//! \note The availability of end-of-transmission mode varies with the
+//! Stellaris part in use. Please consult the datasheet for the part you are
+//! using to determine whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTTxIntModeSet(unsigned long ulBase, unsigned long ulMode)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE) ||
+ (ulBase == UART2_BASE));
+ ASSERT((ulMode == UART_TXINT_MODE_EOT) ||
+ (ulMode == UART_TXINT_MODE_FIFO));
+
+ //
+ // Set or clear the EOT bit of the UART control register as appropriate.
+ //
+ HWREG(ulBase + UART_O_CTL) = ((HWREG(ulBase + UART_O_CTL) &
+ ~(UART_TXINT_MODE_EOT |
+ UART_TXINT_MODE_FIFO)) | ulMode);
+}
+
+//*****************************************************************************
+//
+//! Returns the current operating mode for the UART transmit interrupt.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! This function returns the current operating mode for the UART transmit
+//! interrupt. The return value will be \b UART_TXINT_MODE_EOT if the
+//! transmit interrupt is currently set to be asserted once the transmitter is
+//! completely idle - the transmit FIFO is empty and all bits, including any
+//! stop bits, have cleared the transmitter. The return value will be \b
+//! UART_TXINT_MODE_FIFO if the interrupt is set to be asserted based upon the
+//! level of the transmit FIFO.
+//!
+//! \note The availability of end-of-transmission mode varies with the
+//! Stellaris part in use. Please consult the datasheet for the part you are
+//! using to determine whether this support is available.
+//!
+//! \return Returns \b UART_TXINT_MODE_FIFO or \b UART_TXINT_MODE_EOT.
+//
+//*****************************************************************************
+unsigned long
+UARTTxIntModeGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE) ||
+ (ulBase == UART2_BASE));
+
+ //
+ // Return the current transmit interrupt mode.
+ //
+ return(HWREG(ulBase + UART_O_CTL) & (UART_TXINT_MODE_EOT |
+ UART_TXINT_MODE_FIFO));
+}
+
+//*****************************************************************************
+//
+//! Determines if there are any characters in the receive FIFO.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! This function returns a flag indicating whether or not there is data
+//! available in the receive FIFO.
+//!
+//! \return Returns \b true if there is data in the receive FIFO, and \b false
+//! if there is no data in the receive FIFO.
+//
+//*****************************************************************************
+tBoolean
+UARTCharsAvail(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Return the availability of characters.
+ //
+ return((HWREG(ulBase + UART_O_FR) & UART_FR_RXFE) ? false : true);
+}
+
+//*****************************************************************************
+//
+//! Determines if there is any space in the transmit FIFO.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! This function returns a flag indicating whether or not there is space
+//! available in the transmit FIFO.
+//!
+//! \return Returns \b true if there is space available in the transmit FIFO,
+//! and \b false if there is no space available in the transmit FIFO.
+//
+//*****************************************************************************
+tBoolean
+UARTSpaceAvail(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Return the availability of space.
+ //
+ return((HWREG(ulBase + UART_O_FR) & UART_FR_TXFF) ? false : true);
+}
+
+//*****************************************************************************
+//
+//! Receives a character from the specified port.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! Gets a character from the receive FIFO for the specified port.
+//!
+//! This function replaces the original UARTCharNonBlockingGet() API and
+//! performs the same actions. A macro is provided in <tt>uart.h</tt> to map
+//! the original API to this API.
+//!
+//! \return Returns the character read from the specified port, cast as a
+//! \e long. A \b -1 will be returned if there are no characters present in
+//! the receive FIFO. The UARTCharsAvail() function should be called before
+//! attempting to call this function.
+//
+//*****************************************************************************
+long
+UARTCharGetNonBlocking(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // See if there are any characters in the receive FIFO.
+ //
+ if(!(HWREG(ulBase + UART_O_FR) & UART_FR_RXFE))
+ {
+ //
+ // Read and return the next character.
+ //
+ return(HWREG(ulBase + UART_O_DR));
+ }
+ else
+ {
+ //
+ // There are no characters, so return a failure.
+ //
+ return(-1);
+ }
+}
+
+//*****************************************************************************
+//
+//! Waits for a character from the specified port.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! Gets a character from the receive FIFO for the specified port. If there
+//! are no characters available, this function will wait until a character is
+//! received before returning.
+//!
+//! \return Returns the character read from the specified port, cast as an
+//! \e long.
+//
+//*****************************************************************************
+long
+UARTCharGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Wait until a char is available.
+ //
+ while(HWREG(ulBase + UART_O_FR) & UART_FR_RXFE)
+ {
+ }
+
+ //
+ // Now get the char.
+ //
+ return(HWREG(ulBase + UART_O_DR));
+}
+
+//*****************************************************************************
+//
+//! Sends a character to the specified port.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param ucData is the character to be transmitted.
+//!
+//! Writes the character \e ucData to the transmit FIFO for the specified port.
+//! This function does not block, so if there is no space available, then a
+//! \b false is returned, and the application will have to retry the function
+//! later.
+//!
+//! This function replaces the original UARTCharNonBlockingPut() API and
+//! performs the same actions. A macro is provided in <tt>uart.h</tt> to map
+//! the original API to this API.
+//!
+//! \return Returns \b true if the character was successfully placed in the
+//! transmit FIFO, and \b false if there was no space available in the transmit
+//! FIFO.
+//
+//*****************************************************************************
+tBoolean
+UARTCharPutNonBlocking(unsigned long ulBase, unsigned char ucData)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // See if there is space in the transmit FIFO.
+ //
+ if(!(HWREG(ulBase + UART_O_FR) & UART_FR_TXFF))
+ {
+ //
+ // Write this character to the transmit FIFO.
+ //
+ HWREG(ulBase + UART_O_DR) = ucData;
+
+ //
+ // Success.
+ //
+ return(true);
+ }
+ else
+ {
+ //
+ // There is no space in the transmit FIFO, so return a failure.
+ //
+ return(false);
+ }
+}
+
+//*****************************************************************************
+//
+//! Waits to send a character from the specified port.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param ucData is the character to be transmitted.
+//!
+//! Sends the character \e ucData to the transmit FIFO for the specified port.
+//! If there is no space available in the transmit FIFO, this function will
+//! wait until there is space available before returning.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTCharPut(unsigned long ulBase, unsigned char ucData)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Wait until space is available.
+ //
+ while(HWREG(ulBase + UART_O_FR) & UART_FR_TXFF)
+ {
+ }
+
+ //
+ // Send the char.
+ //
+ HWREG(ulBase + UART_O_DR) = ucData;
+}
+
+//*****************************************************************************
+//
+//! Causes a BREAK to be sent.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param bBreakState controls the output level.
+//!
+//! Calling this function with \e bBreakState set to \b true will assert a
+//! break condition on the UART. Calling this function with \e bBreakState set
+//! to \b false will remove the break condition. For proper transmission of a
+//! break command, the break must be asserted for at least two complete frames.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Set the break condition as requested.
+ //
+ HWREG(ulBase + UART_O_LCRH) =
+ (bBreakState ?
+ (HWREG(ulBase + UART_O_LCRH) | UART_LCRH_BRK) :
+ (HWREG(ulBase + UART_O_LCRH) & ~(UART_LCRH_BRK)));
+}
+
+//*****************************************************************************
+//
+//! Determines whether the UART transmitter is busy or not.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! Allows the caller to determine whether all transmitted bytes have cleared
+//! the transmitter hardware. If \b false is returned, the transmit FIFO is
+//! empty and all bits of the last transmitted character, including all stop
+//! bits, have left the hardware shift register.
+//!
+//! \return Returns \b true if the UART is transmitting or \b false if all
+//! transmissions are complete.
+//
+//*****************************************************************************
+tBoolean
+UARTBusy(unsigned long ulBase)
+{
+ //
+ // Check the argument.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Determine if the UART is busy.
+ //
+ return((HWREG(ulBase + UART_O_FR) & UART_FR_BUSY) ? true : false);
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for a UART interrupt.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param pfnHandler is a pointer to the function to be called when the
+//! UART interrupt occurs.
+//!
+//! This function does the actual registering of the interrupt handler. This
+//! will enable the global interrupt in the interrupt controller; specific UART
+//! interrupts must be enabled via UARTIntEnable(). It is the interrupt
+//! handler's responsibility to clear the interrupt source.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
+{
+ unsigned long ulInt;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Determine the interrupt number based on the UART port.
+ //
+ ulInt = ((ulBase == UART0_BASE) ? INT_UART0 :
+ ((ulBase == UART1_BASE) ? INT_UART1 : INT_UART2));
+
+ //
+ // Register the interrupt handler.
+ //
+ IntRegister(ulInt, pfnHandler);
+
+ //
+ // Enable the UART interrupt.
+ //
+ IntEnable(ulInt);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for a UART interrupt.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! This function does the actual unregistering of the interrupt handler. It
+//! will clear the handler to be called when a UART interrupt occurs. This
+//! will also mask off the interrupt in the interrupt controller so that the
+//! interrupt handler no longer is called.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTIntUnregister(unsigned long ulBase)
+{
+ unsigned long ulInt;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Determine the interrupt number based on the UART port.
+ //
+ ulInt = ((ulBase == UART0_BASE) ? INT_UART0 :
+ ((ulBase == UART1_BASE) ? INT_UART1 : INT_UART2));
+
+ //
+ // Disable the interrupt.
+ //
+ IntDisable(ulInt);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(ulInt);
+}
+
+//*****************************************************************************
+//
+//! Enables individual UART interrupt sources.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.
+//!
+//! Enables the indicated UART interrupt sources. Only the sources that are
+//! enabled can be reflected to the processor interrupt; disabled sources have
+//! no effect on the processor.
+//!
+//! The \e ulIntFlags parameter is the logical OR of any of the following:
+//!
+//! - \b UART_INT_OE - Overrun Error interrupt
+//! - \b UART_INT_BE - Break Error interrupt
+//! - \b UART_INT_PE - Parity Error interrupt
+//! - \b UART_INT_FE - Framing Error interrupt
+//! - \b UART_INT_RT - Receive Timeout interrupt
+//! - \b UART_INT_TX - Transmit interrupt
+//! - \b UART_INT_RX - Receive interrupt
+//! - \b UART_INT_DSR - DSR interrupt
+//! - \b UART_INT_DCD - DCD interrupt
+//! - \b UART_INT_CTS - CTS interrupt
+//! - \b UART_INT_RI - RI interrupt
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Enable the specified interrupts.
+ //
+ HWREG(ulBase + UART_O_IM) |= ulIntFlags;
+}
+
+//*****************************************************************************
+//
+//! Disables individual UART interrupt sources.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled.
+//!
+//! Disables the indicated UART interrupt sources. Only the sources that are
+//! enabled can be reflected to the processor interrupt; disabled sources have
+//! no effect on the processor.
+//!
+//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
+//! parameter to UARTIntEnable().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Disable the specified interrupts.
+ //
+ HWREG(ulBase + UART_O_IM) &= ~(ulIntFlags);
+}
+
+//*****************************************************************************
+//
+//! Gets the current interrupt status.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param bMasked is false if the raw interrupt status is required and true
+//! if the masked interrupt status is required.
+//!
+//! This returns the interrupt status for the specified UART. Either the raw
+//! interrupt status or the status of interrupts that are allowed to reflect to
+//! the processor can be returned.
+//!
+//! \return Returns the current interrupt status, enumerated as a bit field of
+//! values described in UARTIntEnable().
+//
+//*****************************************************************************
+unsigned long
+UARTIntStatus(unsigned long ulBase, tBoolean bMasked)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Return either the interrupt status or the raw interrupt status as
+ // requested.
+ //
+ if(bMasked)
+ {
+ return(HWREG(ulBase + UART_O_MIS));
+ }
+ else
+ {
+ return(HWREG(ulBase + UART_O_RIS));
+ }
+}
+
+//*****************************************************************************
+//
+//! Clears UART interrupt sources.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
+//!
+//! The specified UART interrupt sources are cleared, so that they no longer
+//! assert. This must be done in the interrupt handler to keep it from being
+//! called again immediately upon exit.
+//!
+//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
+//! parameter to UARTIntEnable().
+//!
+//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
+//! several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared. Failure to do so may result in the interrupt handler
+//! being immediately reentered (since NVIC still sees the interrupt source
+//! asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Clear the requested interrupt sources.
+ //
+ HWREG(ulBase + UART_O_ICR) = ulIntFlags;
+}
+
+//*****************************************************************************
+//
+//! Enable UART DMA operation.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param ulDMAFlags is a bit mask of the DMA features to enable.
+//!
+//! The specified UART DMA features are enabled. The UART can be
+//! configured to use DMA for transmit or receive, and to disable
+//! receive if an error occurs. The \e ulDMAFlags parameter is the
+//! logical OR of any of the following values:
+//!
+//! - UART_DMA_RX - enable DMA for receive
+//! - UART_DMA_TX - enable DMA for transmit
+//! - UART_DMA_ERR_RXSTOP - disable DMA receive on UART error
+//!
+//! \note The uDMA controller must also be set up before DMA can be used
+//! with the UART.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Set the requested bits in the UART DMA control register.
+ //
+ HWREG(ulBase + UART_O_DMACTL) |= ulDMAFlags;
+}
+
+//*****************************************************************************
+//
+//! Disable UART DMA operation.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param ulDMAFlags is a bit mask of the DMA features to disable.
+//!
+//! This function is used to disable UART DMA features that were enabled
+//! by UARTDMAEnable(). The specified UART DMA features are disabled. The
+//! \e ulDMAFlags parameter is the logical OR of any of the following values:
+//!
+//! - UART_DMA_RX - disable DMA for receive
+//! - UART_DMA_TX - disable DMA for transmit
+//! - UART_DMA_ERR_RXSTOP - do not disable DMA receive on UART error
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTDMADisable(unsigned long ulBase, unsigned long ulDMAFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Clear the requested bits in the UART DMA control register.
+ //
+ HWREG(ulBase + UART_O_DMACTL) &= ~ulDMAFlags;
+}
+
+//*****************************************************************************
+//
+//! Gets current receiver errors.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! This function returns the current state of each of the 4 receiver error
+//! sources. The returned errors are equivalent to the four error bits
+//! returned via the previous call to UARTCharGet() or UARTCharGetNonBlocking()
+//! with the exception that the overrun error is set immediately the overrun
+//! occurs rather than when a character is next read.
+//!
+//! \return Returns a logical OR combination of the receiver error flags,
+//! \b UART_RXERROR_FRAMING, \b UART_RXERROR_PARITY, \b UART_RXERROR_BREAK
+//! and \b UART_RXERROR_OVERRUN.
+//
+//*****************************************************************************
+unsigned long
+UARTRxErrorGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Return the current value of the receive status register.
+ //
+ return(HWREG(ulBase + UART_O_RSR) & 0x0000000F);
+}
+
+//*****************************************************************************
+//
+//! Clears all reported receiver errors.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! This function is used to clear all receiver error conditions reported via
+//! UARTRxErrorGet(). If using the overrun, framing error, parity error or
+//! break interrupts, this function must be called after clearing the interrupt
+//! to ensure that later errors of the same type trigger another interrupt.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTRxErrorClear(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Any write to the Error Clear Register will clear all bits which are
+ // currently set.
+ //
+ HWREG(ulBase + UART_O_ECR) = 0;
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
Property changes on: branches/eagle_mmc/src/platform/lm3s/uart.c
___________________________________________________________________
Name: svn:executable
+ *
Copied: branches/eagle_mmc/src/platform/lm3s/uart.h (from rev 525, branches/eagle_mmc/src/platform/lm3s/usart.h)
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/usart.h 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lm3s/uart.h 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,246 @@
+//*****************************************************************************
+//
+// uart.h - Defines and Macros for the UART.
+//
+// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __UART_H__
+#define __UART_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear
+// as the ulIntFlags parameter, and returned from UARTIntStatus.
+//
+//*****************************************************************************
+#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask
+#define UART_INT_BE 0x200 // Break Error Interrupt Mask
+#define UART_INT_PE 0x100 // Parity Error Interrupt Mask
+#define UART_INT_FE 0x080 // Framing Error Interrupt Mask
+#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask
+#define UART_INT_TX 0x020 // Transmit Interrupt Mask
+#define UART_INT_RX 0x010 // Receive Interrupt Mask
+#define UART_INT_DSR 0x008 // DSR Modem Interrupt Mask
+#define UART_INT_DCD 0x004 // DCD Modem Interrupt Mask
+#define UART_INT_CTS 0x002 // CTS Modem Interrupt Mask
+#define UART_INT_RI 0x001 // RI Modem Interrupt Mask
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTConfigSetExpClk as the ulConfig parameter
+// and returned by UARTConfigGetExpClk in the pulConfig parameter.
+// Additionally, the UART_CONFIG_PAR_* subset can be passed to
+// UARTParityModeSet as the ulParity parameter, and are returned by
+// UARTParityModeGet.
+//
+//*****************************************************************************
+#define UART_CONFIG_WLEN_MASK 0x00000060 // Mask for extracting word length
+#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data
+#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data
+#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data
+#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data
+#define UART_CONFIG_STOP_MASK 0x00000008 // Mask for extracting stop bits
+#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit
+#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits
+#define UART_CONFIG_PAR_MASK 0x00000086 // Mask for extracting parity
+#define UART_CONFIG_PAR_NONE 0x00000000 // No parity
+#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity
+#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity
+#define UART_CONFIG_PAR_ONE 0x00000082 // Parity bit is one
+#define UART_CONFIG_PAR_ZERO 0x00000086 // Parity bit is zero
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTFIFOLevelSet as the ulTxLevel parameter and
+// returned by UARTFIFOLevelGet in the pulTxLevel.
+//
+//*****************************************************************************
+#define UART_FIFO_TX1_8 0x00000000 // Transmit interrupt at 1/8 Full
+#define UART_FIFO_TX2_8 0x00000001 // Transmit interrupt at 1/4 Full
+#define UART_FIFO_TX4_8 0x00000002 // Transmit interrupt at 1/2 Full
+#define UART_FIFO_TX6_8 0x00000003 // Transmit interrupt at 3/4 Full
+#define UART_FIFO_TX7_8 0x00000004 // Transmit interrupt at 7/8 Full
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTFIFOLevelSet as the ulRxLevel parameter and
+// returned by UARTFIFOLevelGet in the pulRxLevel.
+//
+//*****************************************************************************
+#define UART_FIFO_RX1_8 0x00000000 // Receive interrupt at 1/8 Full
+#define UART_FIFO_RX2_8 0x00000008 // Receive interrupt at 1/4 Full
+#define UART_FIFO_RX4_8 0x00000010 // Receive interrupt at 1/2 Full
+#define UART_FIFO_RX6_8 0x00000018 // Receive interrupt at 3/4 Full
+#define UART_FIFO_RX7_8 0x00000020 // Receive interrupt at 7/8 Full
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTDMAEnable() and UARTDMADisable().
+//
+//*****************************************************************************
+#define UART_DMA_ERR_RXSTOP 0x00000004 // Stop DMA receive if UART error
+#define UART_DMA_TX 0x00000002 // Enable DMA for transmit
+#define UART_DMA_RX 0x00000001 // Enable DMA for receive
+
+//*****************************************************************************
+//
+// Values returned from UARTRxErrorGet().
+//
+//*****************************************************************************
+#define UART_RXERROR_OVERRUN 0x00000008
+#define UART_RXERROR_BREAK 0x00000004
+#define UART_RXERROR_PARITY 0x00000002
+#define UART_RXERROR_FRAMING 0x00000001
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTHandshakeOutputsSet() or returned from
+// UARTHandshakeOutputGet().
+//
+//*****************************************************************************
+#define UART_OUTPUT_RTS 0x00000800
+#define UART_OUTPUT_DTR 0x00000400
+
+//*****************************************************************************
+//
+// Values that can be returned from UARTHandshakeInputsGet().
+//
+//*****************************************************************************
+#define UART_INPUT_RI 0x00000100
+#define UART_INPUT_DCD 0x00000004
+#define UART_INPUT_DSR 0x00000002
+#define UART_INPUT_CTS 0x00000001
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTFlowControl() or returned from
+// UARTFlowControlGet().
+//
+//*****************************************************************************
+#define UART_FLOWCONTROL_TX 0x00008000
+#define UART_FLOWCONTROL_RX 0x00004000
+#define UART_FLOWCONTROL_NONE 0x00000000
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTTxIntModeSet() or returned from
+// UARTTxIntModeGet().
+//
+//*****************************************************************************
+#define UART_TXINT_MODE_FIFO 0x00000000
+#define UART_TXINT_MODE_EOT 0x00000010
+
+//*****************************************************************************
+//
+// API Function prototypes
+//
+//*****************************************************************************
+extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity);
+extern unsigned long UARTParityModeGet(unsigned long ulBase);
+extern void UARTFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel,
+ unsigned long ulRxLevel);
+extern void UARTFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel,
+ unsigned long *pulRxLevel);
+extern void UARTConfigSetExpClk(unsigned long ulBase, unsigned long ulUARTClk,
+ unsigned long ulBaud, unsigned long ulConfig);
+extern void UARTConfigGetExpClk(unsigned long ulBase, unsigned long ulUARTClk,
+ unsigned long *pulBaud,
+ unsigned long *pulConfig);
+extern void UARTEnable(unsigned long ulBase);
+extern void UARTDisable(unsigned long ulBase);
+extern void UARTFIFOEnable(unsigned long ulBase);
+extern void UARTFIFODisable(unsigned long ulBase);
+extern void UARTEnableSIR(unsigned long ulBase, tBoolean bLowPower);
+extern void UARTDisableSIR(unsigned long ulBase);
+extern tBoolean UARTCharsAvail(unsigned long ulBase);
+extern tBoolean UARTSpaceAvail(unsigned long ulBase);
+extern long UARTCharGetNonBlocking(unsigned long ulBase);
+extern long UARTCharGet(unsigned long ulBase);
+extern tBoolean UARTCharPutNonBlocking(unsigned long ulBase,
+ unsigned char ucData);
+extern void UARTCharPut(unsigned long ulBase, unsigned char ucData);
+extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState);
+extern tBoolean UARTBusy(unsigned long ulBase);
+extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
+extern void UARTIntUnregister(unsigned long ulBase);
+extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
+extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
+extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked);
+extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags);
+extern void UARTDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags);
+extern void UARTDMADisable(unsigned long ulBase, unsigned long ulDMAFlags);
+extern unsigned long UARTRxErrorGet(unsigned long ulBase);
+extern void UARTRxErrorClear(unsigned long ulBase);
+extern void UARTSmartCardEnable(unsigned long ulBase);
+extern void UARTSmartCardDisable(unsigned long ulBase);
+extern void UARTModemControlSet(unsigned long ulBase,
+ unsigned long ulControl);
+extern void UARTModemControlClear(unsigned long ulBase,
+ unsigned long ulControl);
+extern unsigned long UARTModemControlGet(unsigned long ulBase);
+extern unsigned long UARTModemStatusGet(unsigned long ulBase);
+extern void UARTFlowControlSet(unsigned long ulBase, unsigned long ulMode);
+extern unsigned long UARTFlowControlGet(unsigned long ulBase);
+extern void UARTTxIntModeSet(unsigned long ulBase, unsigned long ulMode);
+extern unsigned long UARTTxIntModeGet(unsigned long ulBase);
+
+//*****************************************************************************
+//
+// Several UART APIs have been renamed, with the original function name being
+// deprecated. These defines provide backward compatibility.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+#include "sysctl.h"
+#define UARTConfigSet(a, b, c) \
+ UARTConfigSetExpClk(a, SysCtlClockGet(), b, c)
+#define UARTConfigGet(a, b, c) \
+ UARTConfigGetExpClk(a, SysCtlClockGet(), b, c)
+#define UARTCharNonBlockingGet(a) \
+ UARTCharGetNonBlocking(a)
+#define UARTCharNonBlockingPut(a, b) \
+ UARTCharPutNonBlocking(a, b)
+#endif
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __UART_H__
Property changes on: branches/eagle_mmc/src/platform/lm3s/uart.h
___________________________________________________________________
Name: svn:executable
+ *
Deleted: branches/eagle_mmc/src/platform/lm3s/usart.c
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/usart.c 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lm3s/usart.c 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,1157 +0,0 @@
-//*****************************************************************************
-//
-// uart.c - Driver for the UART.
-//
-// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
-// Software License Agreement
-//
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
-//
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws. All rights are reserved. You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program. Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
-//
-// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-//
-// This is part of revision 3740 of the Stellaris Peripheral Driver Library.
-//
-//*****************************************************************************
-
-//*****************************************************************************
-//
-//! \addtogroup uart_api
-//! @{
-//
-//*****************************************************************************
-
-#include "hw_ints.h"
-#include "hw_memmap.h"
-#include "hw_types.h"
-#include "hw_uart.h"
-#include "hw_sysctl.h"
-#include "debug.h"
-#include "interrupt.h"
-#include "sysctl.h"
-#include "usart.h"
-
-//*****************************************************************************
-//
-// The system clock divider defining the maximum baud rate supported by the
-// UART.
-//
-//*****************************************************************************
-#define UART_CLK_DIVIDER 16
-
-//*****************************************************************************
-//
-//! \internal
-//! Checks a UART base address.
-//!
-//! \param ulBase is the base address of the UART port.
-//!
-//! This function determines if a UART port base address is valid.
-//!
-//! \return Returns \b true if the base address is valid and \b false
-//! otherwise.
-//
-//*****************************************************************************
-#ifdef DEBUG
-static tBoolean
-UARTBaseValid(unsigned long ulBase)
-{
- return((ulBase == UART0_BASE) || (ulBase == UART1_BASE) ||
- (ulBase == UART2_BASE));
-}
-#endif
-
-//*****************************************************************************
-//
-//! Sets the type of parity.
-//!
-//! \param ulBase is the base address of the UART port.
-//! \param ulParity specifies the type of parity to use.
-//!
-//! Sets the type of parity to use for transmitting and expect when receiving.
-//! The \e ulParity parameter must be one of \b UART_CONFIG_PAR_NONE,
-//! \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD, \b UART_CONFIG_PAR_ONE,
-//! or \b UART_CONFIG_PAR_ZERO. The last two allow direct control of the
-//! parity bit; it will always be either be one or zero based on the mode.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-UARTParityModeSet(unsigned long ulBase, unsigned long ulParity)
-{
- //
- // Check the arguments.
- //
- ASSERT(UARTBaseValid(ulBase));
- ASSERT((ulParity == UART_CONFIG_PAR_NONE) ||
- (ulParity == UART_CONFIG_PAR_EVEN) ||
- (ulParity == UART_CONFIG_PAR_ODD) ||
- (ulParity == UART_CONFIG_PAR_ONE) ||
- (ulParity == UART_CONFIG_PAR_ZERO));
-
- //
- // Set the parity mode.
- //
- HWREG(ulBase + UART_O_LCRH) = ((HWREG(ulBase + UART_O_LCRH) &
- ~(UART_LCRH_SPS | UART_LCRH_EPS |
- UART_LCRH_PEN)) | ulParity);
-}
-
-//*****************************************************************************
-//
-//! Gets the type of parity currently being used.
-//!
-//! \param ulBase is the base address of the UART port.
-//!
-//! This function gets the type of parity used for transmitting data, and
-//! expected when receiving data.
-//!
-//! \return Returns the current parity settings, specified as one of
-//! \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD,
-//! \b UART_CONFIG_PAR_ONE, or \b UART_CONFIG_PAR_ZERO.
-//
-//*****************************************************************************
-unsigned long
-UARTParityModeGet(unsigned long ulBase)
-{
- //
- // Check the arguments.
- //
- ASSERT(UARTBaseValid(ulBase));
-
- //
- // Return the current parity setting.
- //
- return(HWREG(ulBase + UART_O_LCRH) &
- (UART_LCRH_SPS | UART_LCRH_EPS | UART_LCRH_PEN));
-}
-
-//*****************************************************************************
-//
-//! Sets the FIFO level at which interrupts are generated.
-//!
-//! \param ulBase is the base address of the UART port.
-//! \param ulTxLevel is the transmit FIFO interrupt level, specified as one of
-//! \b UART_FIFO_TX1_8, \b UART_FIFO_TX2_8, \b UART_FIFO_TX4_8,
-//! \b UART_FIFO_TX6_8, or \b UART_FIFO_TX7_8.
-//! \param ulRxLevel is the receive FIFO interrupt level, specified as one of
-//! \b UART_FIFO_RX1_8, \b UART_FIFO_RX2_8, \b UART_FIFO_RX4_8,
-//! \b UART_FIFO_RX6_8, or \b UART_FIFO_RX7_8.
-//!
-//! This function sets the FIFO level at which transmit and receive interrupts
-//! will be generated.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-UARTFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel,
- unsigned long ulRxLevel)
-{
- //
- // Check the arguments.
- //
- ASSERT(UARTBaseValid(ulBase));
- ASSERT((ulTxLevel == UART_FIFO_TX1_8) ||
- (ulTxLevel == UART_FIFO_TX2_8) ||
- (ulTxLevel == UART_FIFO_TX4_8) ||
- (ulTxLevel == UART_FIFO_TX6_8) ||
- (ulTxLevel == UART_FIFO_TX7_8));
- ASSERT((ulRxLevel == UART_FIFO_RX1_8) ||
- (ulRxLevel == UART_FIFO_RX2_8) ||
- (ulRxLevel == UART_FIFO_RX4_8) ||
- (ulRxLevel == UART_FIFO_RX6_8) ||
- (ulRxLevel == UART_FIFO_RX7_8));
-
- //
- // Set the FIFO interrupt levels.
- //
- HWREG(ulBase + UART_O_IFLS) = ulTxLevel | ulRxLevel;
-}
-
-//*****************************************************************************
-//
-//! Gets the FIFO level at which interrupts are generated.
-//!
-//! \param ulBase is the base address of the UART port.
-//! \param pulTxLevel is a pointer to storage for the transmit FIFO level,
-//! returned as one of \b UART_FIFO_TX1_8, \b UART_FIFO_TX2_8,
-//! \b UART_FIFO_TX4_8, \b UART_FIFO_TX6_8, or UART_FIFO_TX7_8.
-//! \param pulRxLevel is a pointer to storage for the receive FIFO level,
-//! returned as one of \b UART_FIFO_RX1_8, \b UART_FIFO_RX2_8,
-//! \b UART_FIFO_RX4_8, \b UART_FIFO_RX6_8, or \b UART_FIFO_RX7_8.
-//!
-//! This function gets the FIFO level at which transmit and receive interrupts
-//! will be generated.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-UARTFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel,
- unsigned long *pulRxLevel)
-{
- unsigned long ulTemp;
-
- //
- // Check the arguments.
- //
- ASSERT(UARTBaseValid(ulBase));
-
- //
- // Read the FIFO level register.
- //
- ulTemp = HWREG(ulBase + UART_O_IFLS);
-
- //
- // Extract the transmit and receive FIFO levels.
- //
- *pulTxLevel = ulTemp & UART_IFLS_TX_M;
- *pulRxLevel = ulTemp & UART_IFLS_RX_M;
-}
-
-//*****************************************************************************
-//
-//! Sets the configuration of a UART.
-//!
-//! \param ulBase is the base address of the UART port.
-//! \param ulUARTClk is the rate of the clock supplied to the UART module.
-//! \param ulBaud is the desired baud rate.
-//! \param ulConfig is the data format for the port (number of data bits,
-//! number of stop bits, and parity).
-//!
-//! This function will configure the UART for operation in the specified data
-//! format. The baud rate is provided in the \e ulBaud parameter and the data
-//! format in the \e ulConfig parameter.
-//!
-//! The \e ulConfig parameter is the logical OR of three values: the number of
-//! data bits, the number of stop bits, and the parity. \b UART_CONFIG_WLEN_8,
-//! \b UART_CONFIG_WLEN_7, \b UART_CONFIG_WLEN_6, and \b UART_CONFIG_WLEN_5
-//! select from eight to five data bits per byte (respectively).
-//! \b UART_CONFIG_STOP_ONE and \b UART_CONFIG_STOP_TWO select one or two stop
-//! bits (respectively). \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN,
-//! \b UART_CONFIG_PAR_ODD, \b UART_CONFIG_PAR_ONE, and \b UART_CONFIG_PAR_ZERO
-//! select the parity mode (no parity bit, even parity bit, odd parity bit,
-//! parity bit always one, and parity bit always zero, respectively).
-//!
-//! The peripheral clock will be the same as the processor clock. This will be
-//! the value returned by SysCtlClockGet(), or it can be explicitly hard coded
-//! if it is constant and known (to save the code/execution overhead of a call
-//! to SysCtlClockGet()).
-//!
-//! This function replaces the original UARTConfigSet() API and performs the
-//! same actions. A macro is provided in <tt>uart.h</tt> to map the original
-//! API to this API.
-//!
-//! \return The actual baud, or 0 for error.
-//
-//*****************************************************************************
-unsigned long
-UARTConfigSetExpClk(unsigned long ulBase, unsigned long ulUARTClk,
- unsigned long ulBaud, unsigned long ulConfig)
-{
- unsigned long ulDiv;
- unsigned long ulInt, ulFrac;
-
- if(!(ulUARTClk >= (ulBaud * UART_CLK_DIVIDER)))
- return 0;
- if(ulBaud == 0)
- return 0;
-
- //
- // Check the arguments.
- //
- ASSERT(UARTBaseValid(ulBase));
-
- //
- // Stop the UART.
- //
- UARTDisable(ulBase);
-
- //
- // Compute the fractional baud rate divider.
- //
- ulDiv = (((ulUARTClk * 8) / ulBaud) + 1) / 2;
-
- //
- // Set the baud rate.
- //
- HWREG(ulBase + UART_O_IBRD) = ulDiv / 64;
- HWREG(ulBase + UART_O_FBRD) = ulDiv % 64;
-
- //
- // Set parity, data length, and number of stop bits.
- //
- HWREG(ulBase + UART_O_LCRH) = ulConfig;
-
- //
- // Clear the flags register.
- //
- HWREG(ulBase + UART_O_FR) = 0;
-
- //
- // Start the UART.
- //
- UARTEnable(ulBase);
-
- // Return the actual baud
- ulInt = HWREG(ulBase + UART_O_IBRD);
- ulFrac = HWREG(ulBase + UART_O_FBRD);
- return (ulUARTClk * 4) / ((64 * ulInt) + ulFrac);
-}
-
-//*****************************************************************************
-//
-//! Gets the current configuration of a UART.
-//!
-//! \param ulBase is the base address of the UART port.
-//! \param ulUARTClk is the rate of the clock supplied to the UART module.
-//! \param pulBaud is a pointer to storage for the baud rate.
-//! \param pulConfig is a pointer to storage for the data format.
-//!
-//! The baud rate and data format for the UART is determined, given an
-//! explicitly provided peripheral clock (hence the ExpClk suffix). The
-//! returned baud rate is the actual baud rate; it may not be the exact baud
-//! rate requested or an ``official'' baud rate. The data format returned in
-//! \e pulConfig is enumerated the same as the \e ulConfig parameter of
-//! UARTConfigSetExpClk().
-//!
-//! The peripheral clock will be the same as the processor clock. This will be
-//! the value returned by SysCtlClockGet(), or it can be explicitly hard coded
-//! if it is constant and known (to save the code/execution overhead of a call
-//! to SysCtlClockGet()).
-//!
-//! This function replaces the original UARTConfigGet() API and performs the
-//! same actions. A macro is provided in <tt>uart.h</tt> to map the original
-//! API to this API.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-UARTConfigGetExpClk(unsigned long ulBase, unsigned long ulUARTClk,
- unsigned long *pulBaud, unsigned long *pulConfig)
-{
- unsigned long ulInt, ulFrac;
-
- //
- // Check the arguments.
- //
- ASSERT(UARTBaseValid(ulBase));
-
- //
- // Compute the baud rate.
- //
- ulInt = HWREG(ulBase + UART_O_IBRD);
- ulFrac = HWREG(ulBase + UART_O_FBRD);
- *pulBaud = (ulUARTClk * 4) / ((64 * ulInt) + ulFrac);
-
- //
- // Get the parity, data length, and number of stop bits.
- //
- *pulConfig = (HWREG(ulBase + UART_O_LCRH) &
- (UART_LCRH_SPS | UART_LCRH_WLEN_M | UART_LCRH_STP2 |
- UART_LCRH_EPS | UART_LCRH_PEN));
-}
-
-//*****************************************************************************
-//
-//! Enables transmitting and receiving.
-//!
-//! \param ulBase is the base address of the UART port.
-//!
-//! Sets the UARTEN, TXE, and RXE bits, and enables the transmit and receive
-//! FIFOs.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-UARTEnable(unsigned long ulBase)
-{
- //
- // Check the arguments.
- //
- ASSERT(UARTBaseValid(ulBase));
-
- //
- // Enable the FIFO.
- //
- HWREG(ulBase + UART_O_LCRH) |= UART_LCRH_FEN;
-
- //
- // Enable RX, TX, and the UART.
- //
- HWREG(ulBase + UART_O_CTL) |= (UART_CTL_UARTEN | UART_CTL_TXE |
- UART_CTL_RXE);
-}
-
-//*****************************************************************************
-//
-//! Disables transmitting and receiving.
-//!
-//! \param ulBase is the base address of the UART port.
-//!
-//! Clears the UARTEN, TXE, and RXE bits, then waits for the end of
-//! transmission of the current character, and flushes the transmit FIFO.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-UARTDisable(unsigned long ulBase)
-{
- //
- // Check the arguments.
- //
- ASSERT(UARTBaseValid(ulBase));
-
- //
- // Wait for end of TX.
- //
- while(HWREG(ulBase + UART_O_FR) & UART_FR_BUSY)
- {
- }
-
- //
- // Disable the FIFO.
- //
- HWREG(ulBase + UART_O_LCRH) &= ~(UART_LCRH_FEN);
-
- //
- // Disable the UART.
- //
- HWREG(ulBase + UART_O_CTL) &= ~(UART_CTL_UARTEN | UART_CTL_TXE |
- UART_CTL_RXE);
-}
-
-//*****************************************************************************
-//
-//! Enables SIR (IrDA) mode on the specified UART.
-//!
-//! \param ulBase is the base address of the UART port.
-//! \param bLowPower indicates if SIR Low Power Mode is to be used.
-//!
-//! Enables the SIREN control bit for IrDA mode on the UART. If the
-//! \e bLowPower flag is set, then SIRLP bit will also be set.
-//!
-//! \note SIR (IrDA) operation is not supported on Sandstorm-class devices.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-UARTEnableSIR(unsigned long ulBase, tBoolean bLowPower)
-{
- //
- // Check the arguments.
- //
- ASSERT(UARTBaseValid(ulBase));
-
- //
- // Enable SIR and SIRLP (if appropriate).
- //
- if(bLowPower)
- {
- HWREG(ulBase + UART_O_CTL) |= (UART_CTL_SIREN | UART_CTL_SIRLP);
- }
- else
- {
- HWREG(ulBase + UART_O_CTL) |= (UART_CTL_SIREN);
- }
-}
-
-//*****************************************************************************
-//
-//! Disables SIR (IrDA) mode on the specified UART.
-//!
-//! \param ulBase is the base address of the UART port.
-//!
-//! Clears the SIREN (IrDA) and SIRLP (Low Power) bits.
-//!
-//! \note SIR (IrDA) operation is not supported on Sandstorm-class devices.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-UARTDisableSIR(unsigned long ulBase)
-{
- //
- // Check the arguments.
- //
- ASSERT(UARTBaseValid(ulBase));
-
- //
- // Disable SIR and SIRLP (if appropriate).
- //
- HWREG(ulBase + UART_O_CTL) &= ~(UART_CTL_SIREN | UART_CTL_SIRLP);
-}
-
-//*****************************************************************************
-//
-//! Determines if there are any characters in the receive FIFO.
-//!
-//! \param ulBase is the base address of the UART port.
-//!
-//! This function returns a flag indicating whether or not there is data
-//! available in the receive FIFO.
-//!
-//! \return Returns \b true if there is data in the receive FIFO, and \b false
-//! if there is no data in the receive FIFO.
-//
-//*****************************************************************************
-tBoolean
-UARTCharsAvail(unsigned long ulBase)
-{
- //
- // Check the arguments.
- //
- ASSERT(UARTBaseValid(ulBase));
-
- //
- // Return the availability of characters.
- //
- return((HWREG(ulBase + UART_O_FR) & UART_FR_RXFE) ? false : true);
-}
-
-//*****************************************************************************
-//
-//! Determines if there is any space in the transmit FIFO.
-//!
-//! \param ulBase is the base address of the UART port.
-//!
-//! This function returns a flag indicating whether or not there is space
-//! available in the transmit FIFO.
-//!
-//! \return Returns \b true if there is space available in the transmit FIFO,
-//! and \b false if there is no space available in the transmit FIFO.
-//
-//*****************************************************************************
-tBoolean
-UARTSpaceAvail(unsigned long ulBase)
-{
- //
- // Check the arguments.
- //
- ASSERT(UARTBaseValid(ulBase));
-
- //
- // Return the availability of space.
- //
- return((HWREG(ulBase + UART_O_FR) & UART_FR_TXFF) ? false : true);
-}
-
-//*****************************************************************************
-//
-//! Receives a character from the specified port.
-//!
-//! \param ulBase is the base address of the UART port.
-//!
-//! Gets a character from the receive FIFO for the specified port.
-//!
-//! This function replaces the original UARTCharNonBlockingGet() API and
-//! performs the same actions. A macro is provided in <tt>uart.h</tt> to map
-//! the original API to this API.
-//!
-//! \return Returns the character read from the specified port, cast as a
-//! \e long. A \b -1 will be returned if there are no characters present in
-//! the receive FIFO. The UARTCharsAvail() function should be called before
-//! attempting to call this function.
-//
-//*****************************************************************************
-long
-UARTCharGetNonBlocking(unsigned long ulBase)
-{
- //
- // Check the arguments.
- //
- ASSERT(UARTBaseValid(ulBase));
-
- //
- // See if there are any characters in the receive FIFO.
- //
- if(!(HWREG(ulBase + UART_O_FR) & UART_FR_RXFE))
- {
- //
- // Read and return the next character.
- //
- return(HWREG(ulBase + UART_O_DR));
- }
- else
- {
- //
- // There are no characters, so return a failure.
- //
- return(-1);
- }
-}
-
-//*****************************************************************************
-//
-//! Waits for a character from the specified port.
-//!
-//! \param ulBase is the base address of the UART port.
-//!
-//! Gets a character from the receive FIFO for the specified port. If there
-//! are no characters available, this function will wait until a character is
-//! received before returning.
-//!
-//! \return Returns the character read from the specified port, cast as an
-//! \e long.
-//
-//*****************************************************************************
-long
-UARTCharGet(unsigned long ulBase)
-{
- //
- // Check the arguments.
- //
- ASSERT(UARTBaseValid(ulBase));
-
- //
- // Wait until a char is available.
- //
- while(HWREG(ulBase + UART_O_FR) & UART_FR_RXFE)
- {
- }
-
- //
- // Now get the char.
- //
- return(HWREG(ulBase + UART_O_DR));
-}
-
-//*****************************************************************************
-//
-//! Sends a character to the specified port.
-//!
-//! \param ulBase is the base address of the UART port.
-//! \param ucData is the character to be transmitted.
-//!
-//! Writes the character \e ucData to the transmit FIFO for the specified port.
-//! This function does not block, so if there is no space available, then a
-//! \b false is returned, and the application will have to retry the function
-//! later.
-//!
-//! This function replaces the original UARTCharNonBlockingPut() API and
-//! performs the same actions. A macro is provided in <tt>uart.h</tt> to map
-//! the original API to this API.
-//!
-//! \return Returns \b true if the character was successfully placed in the
-//! transmit FIFO, and \b false if there was no space available in the transmit
-//! FIFO.
-//
-//*****************************************************************************
-tBoolean
-UARTCharPutNonBlocking(unsigned long ulBase, unsigned char ucData)
-{
- //
- // Check the arguments.
- //
- ASSERT(UARTBaseValid(ulBase));
-
- //
- // See if there is space in the transmit FIFO.
- //
- if(!(HWREG(ulBase + UART_O_FR) & UART_FR_TXFF))
- {
- //
- // Write this character to the transmit FIFO.
- //
- HWREG(ulBase + UART_O_DR) = ucData;
-
- //
- // Success.
- //
- return(true);
- }
- else
- {
- //
- // There is no space in the transmit FIFO, so return a failure.
- //
- return(false);
- }
-}
-
-//*****************************************************************************
-//
-//! Waits to send a character from the specified port.
-//!
-//! \param ulBase is the base address of the UART port.
-//! \param ucData is the character to be transmitted.
-//!
-//! Sends the character \e ucData to the transmit FIFO for the specified port.
-//! If there is no space available in the transmit FIFO, this function will
-//! wait until there is space available before returning.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-UARTCharPut(unsigned long ulBase, unsigned char ucData)
-{
- //
- // Check the arguments.
- //
- ASSERT(UARTBaseValid(ulBase));
-
- //
- // Wait until space is available.
- //
- while(HWREG(ulBase + UART_O_FR) & UART_FR_TXFF)
- {
- }
-
- //
- // Send the char.
- //
- HWREG(ulBase + UART_O_DR) = ucData;
-}
-
-//*****************************************************************************
-//
-//! Causes a BREAK to be sent.
-//!
-//! \param ulBase is the base address of the UART port.
-//! \param bBreakState controls the output level.
-//!
-//! Calling this function with \e bBreakState set to \b true will assert a
-//! break condition on the UART. Calling this function with \e bBreakState set
-//! to \b false will remove the break condition. For proper transmission of a
-//! break command, the break must be asserted for at least two complete frames.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState)
-{
- //
- // Check the arguments.
- //
- ASSERT(UARTBaseValid(ulBase));
-
- //
- // Set the break condition as requested.
- //
- HWREG(ulBase + UART_O_LCRH) =
- (bBreakState ?
- (HWREG(ulBase + UART_O_LCRH) | UART_LCRH_BRK) :
- (HWREG(ulBase + UART_O_LCRH) & ~(UART_LCRH_BRK)));
-}
-
-//*****************************************************************************
-//
-//! Determines whether the UART transmitter is busy or not.
-//!
-//! \param ulBase is the base address of the UART port.
-//!
-//! Allows the caller to determine whether all transmitted bytes have cleared
-//! the transmitter hardware. If \b false is returned, the transmit FIFO is
-//! empty and all bits of the last transmitted character, including all stop
-//! bits, have left the hardware shift register.
-//!
-//! \return Returns \b true if the UART is transmitting or \b false if all
-//! transmissions are complete.
-//
-//*****************************************************************************
-tBoolean
-UARTBusy(unsigned long ulBase)
-{
- //
- // Check the argument.
- //
- ASSERT(UARTBaseValid(ulBase));
-
- //
- // Determine if the UART is busy.
- //
- return((HWREG(ulBase + UART_O_FR) & UART_FR_BUSY) ? true : false);
-}
-
-//*****************************************************************************
-//
-//! Registers an interrupt handler for a UART interrupt.
-//!
-//! \param ulBase is the base address of the UART port.
-//! \param pfnHandler is a pointer to the function to be called when the
-//! UART interrupt occurs.
-//!
-//! This function does the actual registering of the interrupt handler. This
-//! will enable the global interrupt in the interrupt controller; specific UART
-//! interrupts must be enabled via UARTIntEnable(). It is the interrupt
-//! handler's responsibility to clear the interrupt source.
-//!
-//! \sa IntRegister() for important information about registering interrupt
-//! handlers.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-UARTIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
-{
- unsigned long ulInt;
-
- //
- // Check the arguments.
- //
- ASSERT(UARTBaseValid(ulBase));
-
- //
- // Determine the interrupt number based on the UART port.
- //
- ulInt = ((ulBase == UART0_BASE) ? INT_UART0 :
- ((ulBase == UART1_BASE) ? INT_UART1 : INT_UART2));
-
- //
- // Register the interrupt handler.
- //
- IntRegister(ulInt, pfnHandler);
-
- //
- // Enable the UART interrupt.
- //
- IntEnable(ulInt);
-}
-
-//*****************************************************************************
-//
-//! Unregisters an interrupt handler for a UART interrupt.
-//!
-//! \param ulBase is the base address of the UART port.
-//!
-//! This function does the actual unregistering of the interrupt handler. It
-//! will clear the handler to be called when a UART interrupt occurs. This
-//! will also mask off the interrupt in the interrupt controller so that the
-//! interrupt handler no longer is called.
-//!
-//! \sa IntRegister() for important information about registering interrupt
-//! handlers.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-UARTIntUnregister(unsigned long ulBase)
-{
- unsigned long ulInt;
-
- //
- // Check the arguments.
- //
- ASSERT(UARTBaseValid(ulBase));
-
- //
- // Determine the interrupt number based on the UART port.
- //
- ulInt = ((ulBase == UART0_BASE) ? INT_UART0 :
- ((ulBase == UART1_BASE) ? INT_UART1 : INT_UART2));
-
- //
- // Disable the interrupt.
- //
- IntDisable(ulInt);
-
- //
- // Unregister the interrupt handler.
- //
- IntUnregister(ulInt);
-}
-
-//*****************************************************************************
-//
-//! Enables individual UART interrupt sources.
-//!
-//! \param ulBase is the base address of the UART port.
-//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.
-//!
-//! Enables the indicated UART interrupt sources. Only the sources that are
-//! enabled can be reflected to the processor interrupt; disabled sources have
-//! no effect on the processor.
-//!
-//! The \e ulIntFlags parameter is the logical OR of any of the following:
-//!
-//! - \b UART_INT_OE - Overrun Error interrupt
-//! - \b UART_INT_BE - Break Error interrupt
-//! - \b UART_INT_PE - Parity Error interrupt
-//! - \b UART_INT_FE - Framing Error interrupt
-//! - \b UART_INT_RT - Receive Timeout interrupt
-//! - \b UART_INT_TX - Transmit interrupt
-//! - \b UART_INT_RX - Receive interrupt
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
-{
- //
- // Check the arguments.
- //
- ASSERT(UARTBaseValid(ulBase));
-
- //
- // Enable the specified interrupts.
- //
- HWREG(ulBase + UART_O_IM) |= ulIntFlags;
-}
-
-//*****************************************************************************
-//
-//! Disables individual UART interrupt sources.
-//!
-//! \param ulBase is the base address of the UART port.
-//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled.
-//!
-//! Disables the indicated UART interrupt sources. Only the sources that are
-//! enabled can be reflected to the processor interrupt; disabled sources have
-//! no effect on the processor.
-//!
-//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
-//! parameter to UARTIntEnable().
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
-{
- //
- // Check the arguments.
- //
- ASSERT(UARTBaseValid(ulBase));
-
- //
- // Disable the specified interrupts.
- //
- HWREG(ulBase + UART_O_IM) &= ~(ulIntFlags);
-}
-
-//*****************************************************************************
-//
-//! Gets the current interrupt status.
-//!
-//! \param ulBase is the base address of the UART port.
-//! \param bMasked is false if the raw interrupt status is required and true
-//! if the masked interrupt status is required.
-//!
-//! This returns the interrupt status for the specified UART. Either the raw
-//! interrupt status or the status of interrupts that are allowed to reflect to
-//! the processor can be returned.
-//!
-//! \return Returns the current interrupt status, enumerated as a bit field of
-//! values described in UARTIntEnable().
-//
-//*****************************************************************************
-unsigned long
-UARTIntStatus(unsigned long ulBase, tBoolean bMasked)
-{
- //
- // Check the arguments.
- //
- ASSERT(UARTBaseValid(ulBase));
-
- //
- // Return either the interrupt status or the raw interrupt status as
- // requested.
- //
- if(bMasked)
- {
- return(HWREG(ulBase + UART_O_MIS));
- }
- else
- {
- return(HWREG(ulBase + UART_O_RIS));
- }
-}
-
-//*****************************************************************************
-//
-//! Clears UART interrupt sources.
-//!
-//! \param ulBase is the base address of the UART port.
-//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
-//!
-//! The specified UART interrupt sources are cleared, so that they no longer
-//! assert. This must be done in the interrupt handler to keep it from being
-//! called again immediately upon exit.
-//!
-//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
-//! parameter to UARTIntEnable().
-//!
-//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
-//! several clock cycles before the interrupt source is actually cleared.
-//! Therefore, it is recommended that the interrupt source be cleared early in
-//! the interrupt handler (as opposed to the very last action) to avoid
-//! returning from the interrupt handler before the interrupt source is
-//! actually cleared. Failure to do so may result in the interrupt handler
-//! being immediately reentered (since NVIC still sees the interrupt source
-//! asserted).
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags)
-{
- //
- // Check the arguments.
- //
- ASSERT(UARTBaseValid(ulBase));
-
- //
- // Clear the requested interrupt sources.
- //
- HWREG(ulBase + UART_O_ICR) = ulIntFlags;
-}
-
-//*****************************************************************************
-//
-//! Enable UART DMA operation.
-//!
-//! \param ulBase is the base address of the UART port.
-//! \param ulDMAFlags is a bit mask of the DMA features to enable.
-//!
-//! The specified UART DMA features are enabled. The UART can be
-//! configured to use DMA for transmit or receive, and to disable
-//! receive if an error occurs. The \e ulDMAFlags parameter is the
-//! logical OR of any of the following values:
-//!
-//! - UART_DMA_RX - enable DMA for receive
-//! - UART_DMA_TX - enable DMA for transmit
-//! - UART_DMA_ERR_RXSTOP - disable DMA receive on UART error
-//!
-//! \note The uDMA controller must also be set up before DMA can be used
-//! with the UART.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-UARTDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags)
-{
- //
- // Check the arguments.
- //
- ASSERT(UARTBaseValid(ulBase));
-
- //
- // Set the requested bits in the UART DMA control register.
- //
- HWREG(ulBase + UART_O_DMACTL) |= ulDMAFlags;
-}
-
-//*****************************************************************************
-//
-//! Disable UART DMA operation.
-//!
-//! \param ulBase is the base address of the UART port.
-//! \param ulDMAFlags is a bit mask of the DMA features to disable.
-//!
-//! This function is used to disable UART DMA features that were enabled
-//! by UARTDMAEnable(). The specified UART DMA features are disabled. The
-//! \e ulDMAFlags parameter is the logical OR of any of the following values:
-//!
-//! - UART_DMA_RX - disable DMA for receive
-//! - UART_DMA_TX - disable DMA for transmit
-//! - UART_DMA_ERR_RXSTOP - do not disable DMA receive on UART error
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-UARTDMADisable(unsigned long ulBase, unsigned long ulDMAFlags)
-{
- //
- // Check the arguments.
- //
- ASSERT(UARTBaseValid(ulBase));
-
- //
- // Clear the requested bits in the UART DMA control register.
- //
- HWREG(ulBase + UART_O_DMACTL) &= ~ulDMAFlags;
-}
-
-//*****************************************************************************
-//
-//! Gets current receiver errors.
-//!
-//! \param ulBase is the base address of the UART port.
-//!
-//! This function returns the current state of each of the 4 receiver error
-//! sources. The returned errors are equivalent to the four error bits
-//! returned via the previous call to UARTCharGet() or UARTCharGetNonBlocking()
-//! with the exception that the overrun error is set immediately the overrun
-//! occurs rather than when a character is next read.
-//!
-//! \return Returns a logical OR combination of the receiver error flags,
-//! \b UART_RXERROR_FRAMING, \b UART_RXERROR_PARITY, \b UART_RXERROR_BREAK
-//! and \b UART_RXERROR_OVERRUN.
-//
-//*****************************************************************************
-unsigned long
-UARTRxErrorGet(unsigned long ulBase)
-{
- //
- // Check the arguments.
- //
- ASSERT(UARTBaseValid(ulBase));
-
- //
- // Return the current value of the receive status register.
- //
- return(HWREG(ulBase + UART_O_RSR) & 0x0000000F);
-
-}
-
-//*****************************************************************************
-//
-//! Clears all reported receiver errors.
-//!
-//! \param ulBase is the base address of the UART port.
-//!
-//! This function is used to clear all receiver error conditions reported via
-//! UARTRxErrorGet(). If using the overrun, framing error, parity error or
-//! break interrupts, this function must be called after clearing the interrupt
-//! to ensure that later errors of the same type trigger another interrupt.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-UARTRxErrorClear(unsigned long ulBase)
-{
- //
- // Check the arguments.
- //
- ASSERT(UARTBaseValid(ulBase));
-
- //
- // Any write to the Error Clear Register will clear all bits which are
- // currently set.
- //
- HWREG(ulBase + UART_O_ECR) = 0;
-}
-
-//*****************************************************************************
-//
-// Close the Doxygen group.
-//! @}
-//
-//*****************************************************************************
Deleted: branches/eagle_mmc/src/platform/lm3s/usart.h
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/usart.h 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lm3s/usart.h 2009-11-06 02:08:32 UTC (rev 526)
@@ -1,190 +0,0 @@
-//*****************************************************************************
-//
-// uart.h - Defines and Macros for the UART.
-//
-// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
-// Software License Agreement
-//
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
-//
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws. All rights are reserved. You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program. Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
-//
-// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-//
-// This is part of revision 3740 of the Stellaris Peripheral Driver Library.
-//
-//*****************************************************************************
-
-#ifndef __USART_H__
-#define __USART_H__
-
-//*****************************************************************************
-//
-// If building with a C++ compiler, make all of the definitions in this header
-// have a C binding.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-//*****************************************************************************
-//
-// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear
-// as the ulIntFlags parameter, and returned from UARTIntStatus.
-//
-//*****************************************************************************
-#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask
-#define UART_INT_BE 0x200 // Break Error Interrupt Mask
-#define UART_INT_PE 0x100 // Parity Error Interrupt Mask
-#define UART_INT_FE 0x080 // Framing Error Interrupt Mask
-#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask
-#define UART_INT_TX 0x020 // Transmit Interrupt Mask
-#define UART_INT_RX 0x010 // Receive Interrupt Mask
-
-//*****************************************************************************
-//
-// Values that can be passed to UARTConfigSetExpClk as the ulConfig parameter
-// and returned by UARTConfigGetExpClk in the pulConfig parameter.
-// Additionally, the UART_CONFIG_PAR_* subset can be passed to
-// UARTParityModeSet as the ulParity parameter, and are returned by
-// UARTParityModeGet.
-//
-//*****************************************************************************
-#define UART_CONFIG_WLEN_MASK 0x00000060 // Mask for extracting word length
-#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data
-#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data
-#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data
-#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data
-#define UART_CONFIG_STOP_MASK 0x00000008 // Mask for extracting stop bits
-#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit
-#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits
-#define UART_CONFIG_PAR_MASK 0x00000086 // Mask for extracting parity
-#define UART_CONFIG_PAR_NONE 0x00000000 // No parity
-#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity
-#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity
-#define UART_CONFIG_PAR_ONE 0x00000086 // Parity bit is one
-#define UART_CONFIG_PAR_ZERO 0x00000082 // Parity bit is zero
-
-//*****************************************************************************
-//
-// Values that can be passed to UARTFIFOLevelSet as the ulTxLevel parameter and
-// returned by UARTFIFOLevelGet in the pulTxLevel.
-//
-//*****************************************************************************
-#define UART_FIFO_TX1_8 0x00000000 // Transmit interrupt at 1/8 Full
-#define UART_FIFO_TX2_8 0x00000001 // Transmit interrupt at 1/4 Full
-#define UART_FIFO_TX4_8 0x00000002 // Transmit interrupt at 1/2 Full
-#define UART_FIFO_TX6_8 0x00000003 // Transmit interrupt at 3/4 Full
-#define UART_FIFO_TX7_8 0x00000004 // Transmit interrupt at 7/8 Full
-
-//*****************************************************************************
-//
-// Values that can be passed to UARTFIFOLevelSet as the ulRxLevel parameter and
-// returned by UARTFIFOLevelGet in the pulRxLevel.
-//
-//*****************************************************************************
-#define UART_FIFO_RX1_8 0x00000000 // Receive interrupt at 1/8 Full
-#define UART_FIFO_RX2_8 0x00000008 // Receive interrupt at 1/4 Full
-#define UART_FIFO_RX4_8 0x00000010 // Receive interrupt at 1/2 Full
-#define UART_FIFO_RX6_8 0x00000018 // Receive interrupt at 3/4 Full
-#define UART_FIFO_RX7_8 0x00000020 // Receive interrupt at 7/8 Full
-
-//*****************************************************************************
-//
-// Values that can be passed to UARTDMAEnable() and UARTDMADisable().
-//
-//*****************************************************************************
-#define UART_DMA_ERR_RXSTOP 0x00000004 // Stop DMA receive if UART error
-#define UART_DMA_TX 0x00000002 // Enable DMA for transmit
-#define UART_DMA_RX 0x00000001 // Enable DMA for receive
-
-//*****************************************************************************
-//
-// Values returned from UARTRxErrorGet().
-//
-//*****************************************************************************
-#define UART_RXERROR_OVERRUN 0x00000008
-#define UART_RXERROR_BREAK 0x00000004
-#define UART_RXERROR_PARITY 0x00000002
-#define UART_RXERROR_FRAMING 0x00000001
-
-//*****************************************************************************
-//
-// API Function prototypes
-//
-//*****************************************************************************
-extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity);
-extern unsigned long UARTParityModeGet(unsigned long ulBase);
-extern void UARTFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel,
- unsigned long ulRxLevel);
-extern void UARTFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel,
- unsigned long *pulRxLevel);
-extern unsigned long UARTConfigSetExpClk(unsigned long ulBase, unsigned long ulUARTClk,
- unsigned long ulBaud, unsigned long ulConfig);
-extern void UARTConfigGetExpClk(unsigned long ulBase, unsigned long ulUARTClk,
- unsigned long *pulBaud,
- unsigned long *pulConfig);
-extern void UARTEnable(unsigned long ulBase);
-extern void UARTDisable(unsigned long ulBase);
-extern void UARTEnableSIR(unsigned long ulBase, tBoolean bLowPower);
-extern void UARTDisableSIR(unsigned long ulBase);
-extern tBoolean UARTCharsAvail(unsigned long ulBase);
-extern tBoolean UARTSpaceAvail(unsigned long ulBase);
-extern long UARTCharGetNonBlocking(unsigned long ulBase);
-extern long UARTCharGet(unsigned long ulBase);
-extern tBoolean UARTCharPutNonBlocking(unsigned long ulBase,
- unsigned char ucData);
-extern void UARTCharPut(unsigned long ulBase, unsigned char ucData);
-extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState);
-extern tBoolean UARTBusy(unsigned long ulBase);
-extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
-extern void UARTIntUnregister(unsigned long ulBase);
-extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
-extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
-extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked);
-extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags);
-extern void UARTDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags);
-extern void UARTDMADisable(unsigned long ulBase, unsigned long ulDMAFlags);
-extern unsigned long UARTRxErrorGet(unsigned long ulBase);
-extern void UARTRxErrorClear(unsigned long ulBase);
-
-//*****************************************************************************
-//
-// Several UART APIs have been renamed, with the original function name being
-// deprecated. These defines provide backward compatibility.
-//
-//*****************************************************************************
-#ifndef DEPRECATED
-#include "sysctl.h"
-#define UARTConfigSet(a, b, c) \
- UARTConfigSetExpClk(a, SysCtlClockGet(), b, c)
-#define UARTConfigGet(a, b, c) \
- UARTConfigGetExpClk(a, SysCtlClockGet(), b, c)
-#define UARTCharNonBlockingGet(a) \
- UARTCharGetNonBlocking(a)
-#define UARTCharNonBlockingPut(a, b) \
- UARTCharPutNonBlocking(a, b)
-#endif
-
-//*****************************************************************************
-//
-// Mark the end of the C bindings section for C++ compilers.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-}
-#endif
-
-#endif // __USART_H__
Added: branches/eagle_mmc/src/platform/lpc24xx/LPC23xx.h
===================================================================
--- branches/eagle_mmc/src/platform/lpc24xx/LPC23xx.h 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lpc24xx/LPC23xx.h 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,1167 @@
+/******************************************************************************
+ * LPC23xx.h: Header file for NXP LPC23xx/24xx Family Microprocessors
+ * The header file is the super set of all hardware definition of the
+ * peripherals for the LPC23xx/24xx family microprocessor.
+ *
+ * Copyright(C) 2006, NXP Semiconductor
+ * All rights reserved.
+ *
+ * History
+ * 2005.10.01 ver 1.00 Prelimnary version, first Release
+ * 2007.05.17 ver 1.01 several corrections
+ * 2007.09.05 ver 1.02 added VICVectPriorityx symbols
+ * 2007.09.05 ver 1.03 FIO1PIN1 value corrected
+ *
+******************************************************************************/
+
+#ifndef __LPC23xx_H
+#define __LPC23xx_H
+
+/* Vectored Interrupt Controller (VIC) */
+#define VIC_BASE_ADDR 0xFFFFF000
+#define VICIRQStatus (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x000))
+#define VICFIQStatus (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x004))
+#define VICRawIntr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x008))
+#define VICIntSelect (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x00C))
+#define VICIntEnable (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x010))
+#define VICIntEnClr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x014))
+#define VICSoftInt (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x018))
+#define VICSoftIntClr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x01C))
+#define VICProtection (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x020))
+#define VICSWPrioMask (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x024))
+
+#define VICVectAddr0 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x100))
+#define VICVectAddr1 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x104))
+#define VICVectAddr2 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x108))
+#define VICVectAddr3 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x10C))
+#define VICVectAddr4 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x110))
+#define VICVectAddr5 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x114))
+#define VICVectAddr6 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x118))
+#define VICVectAddr7 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x11C))
+#define VICVectAddr8 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x120))
+#define VICVectAddr9 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x124))
+#define VICVectAddr10 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x128))
+#define VICVectAddr11 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x12C))
+#define VICVectAddr12 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x130))
+#define VICVectAddr13 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x134))
+#define VICVectAddr14 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x138))
+#define VICVectAddr15 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x13C))
+#define VICVectAddr16 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x140))
+#define VICVectAddr17 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x144))
+#define VICVectAddr18 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x148))
+#define VICVectAddr19 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x14C))
+#define VICVectAddr20 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x150))
+#define VICVectAddr21 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x154))
+#define VICVectAddr22 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x158))
+#define VICVectAddr23 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x15C))
+#define VICVectAddr24 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x160))
+#define VICVectAddr25 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x164))
+#define VICVectAddr26 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x168))
+#define VICVectAddr27 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x16C))
+#define VICVectAddr28 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x170))
+#define VICVectAddr29 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x174))
+#define VICVectAddr30 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x178))
+#define VICVectAddr31 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x17C))
+
+/* The name convention below is from previous LPC2000 family MCUs, in LPC23xx/24xx,
+these registers are known as "VICVectPriority(x)". */
+#define VICVectCntl0 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x200))
+#define VICVectCntl1 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x204))
+#define VICVectCntl2 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x208))
+#define VICVectCntl3 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x20C))
+#define VICVectCntl4 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x210))
+#define VICVectCntl5 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x214))
+#define VICVectCntl6 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x218))
+#define VICVectCntl7 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x21C))
+#define VICVectCntl8 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x220))
+#define VICVectCntl9 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x224))
+#define VICVectCntl10 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x228))
+#define VICVectCntl11 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x22C))
+#define VICVectCntl12 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x230))
+#define VICVectCntl13 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x234))
+#define VICVectCntl14 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x238))
+#define VICVectCntl15 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x23C))
+#define VICVectCntl16 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x240))
+#define VICVectCntl17 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x244))
+#define VICVectCntl18 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x248))
+#define VICVectCntl19 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x24C))
+#define VICVectCntl20 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x250))
+#define VICVectCntl21 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x254))
+#define VICVectCntl22 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x258))
+#define VICVectCntl23 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x25C))
+#define VICVectCntl24 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x260))
+#define VICVectCntl25 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x264))
+#define VICVectCntl26 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x268))
+#define VICVectCntl27 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x26C))
+#define VICVectCntl28 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x270))
+#define VICVectCntl29 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x274))
+#define VICVectCntl30 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x278))
+#define VICVectCntl31 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x27C))
+
+/* LPC23xx/24xx VICVectPriority(x)". */
+#define VICVectPriority0 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x200))
+#define VICVectPriority1 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x204))
+#define VICVectPriority2 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x208))
+#define VICVectPriority3 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x20C))
+#define VICVectPriority4 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x210))
+#define VICVectPriority5 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x214))
+#define VICVectPriority6 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x218))
+#define VICVectPriority7 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x21C))
+#define VICVectPriority8 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x220))
+#define VICVectPriority9 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x224))
+#define VICVectPriority10 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x228))
+#define VICVectPriority11 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x22C))
+#define VICVectPriority12 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x230))
+#define VICVectPriority13 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x234))
+#define VICVectPriority14 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x238))
+#define VICVectPriority15 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x23C))
+#define VICVectPriority16 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x240))
+#define VICVectPriority17 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x244))
+#define VICVectPriority18 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x248))
+#define VICVectPriority19 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x24C))
+#define VICVectPriority20 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x250))
+#define VICVectPriority21 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x254))
+#define VICVectPriority22 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x258))
+#define VICVectPriority23 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x25C))
+#define VICVectPriority24 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x260))
+#define VICVectPriority25 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x264))
+#define VICVectPriority26 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x268))
+#define VICVectPriority27 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x26C))
+#define VICVectPriority28 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x270))
+#define VICVectPriority29 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x274))
+#define VICVectPriority30 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x278))
+#define VICVectPriority31 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x27C))
+
+#define VICVectAddr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0xF00))
+
+
+/* Pin Connect Block */
+#define PINSEL_BASE_ADDR 0xE002C000
+#define PINSEL0 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x00))
+#define PINSEL1 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x04))
+#define PINSEL2 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x08))
+#define PINSEL3 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x0C))
+#define PINSEL4 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x10))
+#define PINSEL5 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x14))
+#define PINSEL6 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x18))
+#define PINSEL7 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x1C))
+#define PINSEL8 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x20))
+#define PINSEL9 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x24))
+#define PINSEL10 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x28))
+
+#define PINMODE0 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x40))
+#define PINMODE1 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x44))
+#define PINMODE2 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x48))
+#define PINMODE3 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x4C))
+#define PINMODE4 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x50))
+#define PINMODE5 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x54))
+#define PINMODE6 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x58))
+#define PINMODE7 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x5C))
+#define PINMODE8 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x60))
+#define PINMODE9 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x64))
+
+/* General Purpose Input/Output (GPIO) */
+#define GPIO_BASE_ADDR 0xE0028000
+#define IOPIN0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x00))
+#define IOSET0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x04))
+#define IODIR0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x08))
+#define IOCLR0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x0C))
+#define IOPIN1 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x10))
+#define IOSET1 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x14))
+#define IODIR1 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x18))
+#define IOCLR1 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x1C))
+
+/* GPIO Interrupt Registers */
+#define IO0_INT_EN_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x90))
+#define IO0_INT_EN_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x94))
+#define IO0_INT_STAT_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x84))
+#define IO0_INT_STAT_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x88))
+#define IO0_INT_CLR (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x8C))
+
+#define IO2_INT_EN_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xB0))
+#define IO2_INT_EN_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xB4))
+#define IO2_INT_STAT_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xA4))
+#define IO2_INT_STAT_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xA8))
+#define IO2_INT_CLR (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xAC))
+
+#define IO_INT_STAT (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x80))
+
+#define PARTCFG_BASE_ADDR 0x3FFF8000
+#define PARTCFG (*(volatile unsigned long *)(PARTCFG_BASE_ADDR + 0x00))
+
+/* Fast I/O setup */
+#define FIO_BASE_ADDR 0x3FFFC000
+#define FIO0DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x00))
+#define FIO0MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x10))
+#define FIO0PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x14))
+#define FIO0SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x18))
+#define FIO0CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x1C))
+
+#define FIO1DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x20))
+#define FIO1MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x30))
+#define FIO1PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x34))
+#define FIO1SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x38))
+#define FIO1CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x3C))
+
+#define FIO2DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x40))
+#define FIO2MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x50))
+#define FIO2PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x54))
+#define FIO2SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x58))
+#define FIO2CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x5C))
+
+#define FIO3DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x60))
+#define FIO3MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x70))
+#define FIO3PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x74))
+#define FIO3SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x78))
+#define FIO3CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x7C))
+
+#define FIO4DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x80))
+#define FIO4MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x90))
+#define FIO4PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x94))
+#define FIO4SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x98))
+#define FIO4CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x9C))
+
+/* FIOs can be accessed through WORD, HALF-WORD or BYTE. */
+#define FIO0DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x00))
+#define FIO1DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x20))
+#define FIO2DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x40))
+#define FIO3DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x60))
+#define FIO4DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x80))
+
+#define FIO0DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x01))
+#define FIO1DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x21))
+#define FIO2DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x41))
+#define FIO3DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x61))
+#define FIO4DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x81))
+
+#define FIO0DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x02))
+#define FIO1DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x22))
+#define FIO2DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x42))
+#define FIO3DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x62))
+#define FIO4DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x82))
+
+#define FIO0DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x03))
+#define FIO1DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x23))
+#define FIO2DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x43))
+#define FIO3DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x63))
+#define FIO4DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x83))
+
+#define FIO0DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x00))
+#define FIO1DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x20))
+#define FIO2DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x40))
+#define FIO3DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x60))
+#define FIO4DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x80))
+
+#define FIO0DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x02))
+#define FIO1DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x22))
+#define FIO2DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x42))
+#define FIO3DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x62))
+#define FIO4DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x82))
+
+#define FIO0MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x10))
+#define FIO1MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x30))
+#define FIO2MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x50))
+#define FIO3MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x70))
+#define FIO4MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x90))
+
+#define FIO0MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x11))
+#define FIO1MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x31))
+#define FIO2MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x51))
+#define FIO3MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x71))
+#define FIO4MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x91))
+
+#define FIO0MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x12))
+#define FIO1MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x32))
+#define FIO2MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x52))
+#define FIO3MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x72))
+#define FIO4MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x92))
+
+#define FIO0MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x13))
+#define FIO1MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x33))
+#define FIO2MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x53))
+#define FIO3MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x73))
+#define FIO4MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x93))
+
+#define FIO0MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x10))
+#define FIO1MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x30))
+#define FIO2MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x50))
+#define FIO3MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x70))
+#define FIO4MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x90))
+
+#define FIO0MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x12))
+#define FIO1MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x32))
+#define FIO2MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x52))
+#define FIO3MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x72))
+#define FIO4MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x92))
+
+#define FIO0PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x14))
+#define FIO1PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x34))
+#define FIO2PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x54))
+#define FIO3PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x74))
+#define FIO4PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x94))
+
+#define FIO0PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x15))
+#define FIO1PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x35))
+#define FIO2PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x55))
+#define FIO3PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x75))
+#define FIO4PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x95))
+
+#define FIO0PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x16))
+#define FIO1PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x36))
+#define FIO2PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x56))
+#define FIO3PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x76))
+#define FIO4PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x96))
+
+#define FIO0PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x17))
+#define FIO1PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x37))
+#define FIO2PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x57))
+#define FIO3PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x77))
+#define FIO4PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x97))
+
+#define FIO0PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x14))
+#define FIO1PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x34))
+#define FIO2PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x54))
+#define FIO3PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x74))
+#define FIO4PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x94))
+
+#define FIO0PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x16))
+#define FIO1PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x36))
+#define FIO2PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x56))
+#define FIO3PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x76))
+#define FIO4PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x96))
+
+#define FIO0SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x18))
+#define FIO1SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x38))
+#define FIO2SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x58))
+#define FIO3SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x78))
+#define FIO4SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x98))
+
+#define FIO0SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x19))
+#define FIO1SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x39))
+#define FIO2SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x59))
+#define FIO3SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x79))
+#define FIO4SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x99))
+
+#define FIO0SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1A))
+#define FIO1SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3A))
+#define FIO2SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5A))
+#define FIO3SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7A))
+#define FIO4SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9A))
+
+#define FIO0SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1B))
+#define FIO1SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3B))
+#define FIO2SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5B))
+#define FIO3SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7B))
+#define FIO4SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9B))
+
+#define FIO0SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x18))
+#define FIO1SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x38))
+#define FIO2SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x58))
+#define FIO3SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x78))
+#define FIO4SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x98))
+
+#define FIO0SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1A))
+#define FIO1SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3A))
+#define FIO2SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5A))
+#define FIO3SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7A))
+#define FIO4SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9A))
+
+#define FIO0CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1C))
+#define FIO1CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3C))
+#define FIO2CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5C))
+#define FIO3CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7C))
+#define FIO4CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9C))
+
+#define FIO0CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1D))
+#define FIO1CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3D))
+#define FIO2CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5D))
+#define FIO3CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7D))
+#define FIO4CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9D))
+
+#define FIO0CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1E))
+#define FIO1CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3E))
+#define FIO2CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5E))
+#define FIO3CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7E))
+#define FIO4CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9E))
+
+#define FIO0CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1F))
+#define FIO1CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3F))
+#define FIO2CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5F))
+#define FIO3CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7F))
+#define FIO4CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9F))
+
+#define FIO0CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1C))
+#define FIO1CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3C))
+#define FIO2CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5C))
+#define FIO3CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7C))
+#define FIO4CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9C))
+
+#define FIO0CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1E))
+#define FIO1CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3E))
+#define FIO2CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5E))
+#define FIO3CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7E))
+#define FIO4CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9E))
+
+
+/* System Control Block(SCB) modules include Memory Accelerator Module,
+Phase Locked Loop, VPB divider, Power Control, External Interrupt,
+Reset, and Code Security/Debugging */
+#define SCB_BASE_ADDR 0xE01FC000
+
+/* Memory Accelerator Module (MAM) */
+#define MAMCR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x000))
+#define MAMTIM (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x004))
+#define MEMMAP (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x040))
+
+/* Phase Locked Loop (PLL) */
+#define PLLCON (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x080))
+#define PLLCFG (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x084))
+#define PLLSTAT (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x088))
+#define PLLFEED (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x08C))
+
+/* Power Control */
+#define PCON (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0C0))
+#define PCONP (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0C4))
+
+/* Clock Divider */
+// #define APBDIV (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x100))
+#define CCLKCFG (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x104))
+#define USBCLKCFG (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x108))
+#define CLKSRCSEL (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x10C))
+#define PCLKSEL0 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A8))
+#define PCLKSEL1 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1AC))
+
+/* External Interrupts */
+#define EXTINT (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x140))
+#define INTWAKE (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x144))
+#define EXTMODE (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x148))
+#define EXTPOLAR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x14C))
+
+/* Reset, reset source identification */
+#define RSIR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x180))
+
+/* RSID, code security protection */
+#define CSPR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x184))
+
+/* AHB configuration */
+#define AHBCFG1 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x188))
+#define AHBCFG2 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x18C))
+
+/* System Controls and Status */
+#define SCS (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A0))
+
+/* MPMC(EMC) registers, note: all the external memory controller(EMC) registers
+are for LPC24xx only. */
+#define STATIC_MEM0_BASE 0x80000000
+#define STATIC_MEM1_BASE 0x81000000
+#define STATIC_MEM2_BASE 0x82000000
+#define STATIC_MEM3_BASE 0x83000000
+
+#define DYNAMIC_MEM0_BASE 0xA0000000
+#define DYNAMIC_MEM1_BASE 0xB0000000
+#define DYNAMIC_MEM2_BASE 0xC0000000
+#define DYNAMIC_MEM3_BASE 0xD0000000
+
+/* External Memory Controller (EMC) */
+#define EMC_BASE_ADDR 0xFFE08000
+#define EMC_CTRL (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x000))
+#define EMC_STAT (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x004))
+#define EMC_CONFIG (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x008))
+
+/* Dynamic RAM access registers */
+#define EMC_DYN_CTRL (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x020))
+#define EMC_DYN_RFSH (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x024))
+#define EMC_DYN_RD_CFG (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x028))
+#define EMC_DYN_RP (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x030))
+#define EMC_DYN_RAS (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x034))
+#define EMC_DYN_SREX (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x038))
+#define EMC_DYN_APR (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x03C))
+#define EMC_DYN_DAL (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x040))
+#define EMC_DYN_WR (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x044))
+#define EMC_DYN_RC (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x048))
+#define EMC_DYN_RFC (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x04C))
+#define EMC_DYN_XSR (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x050))
+#define EMC_DYN_RRD (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x054))
+#define EMC_DYN_MRD (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x058))
+
+#define EMC_DYN_CFG0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x100))
+#define EMC_DYN_RASCAS0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x104))
+#define EMC_DYN_CFG1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x120))
+#define EMC_DYN_RASCAS1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x124))
+#define EMC_DYN_CFG2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x140))
+#define EMC_DYN_RASCAS2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x144))
+#define EMC_DYN_CFG3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x160))
+#define EMC_DYN_RASCAS3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x164))
+
+/* static RAM access registers */
+#define EMC_STA_CFG0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x200))
+#define EMC_STA_WAITWEN0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x204))
+#define EMC_STA_WAITOEN0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x208))
+#define EMC_STA_WAITRD0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x20C))
+#define EMC_STA_WAITPAGE0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x210))
+#define EMC_STA_WAITWR0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x214))
+#define EMC_STA_WAITTURN0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x218))
+
+#define EMC_STA_CFG1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x220))
+#define EMC_STA_WAITWEN1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x224))
+#define EMC_STA_WAITOEN1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x228))
+#define EMC_STA_WAITRD1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x22C))
+#define EMC_STA_WAITPAGE1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x230))
+#define EMC_STA_WAITWR1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x234))
+#define EMC_STA_WAITTURN1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x238))
+
+#define EMC_STA_CFG2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x240))
+#define EMC_STA_WAITWEN2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x244))
+#define EMC_STA_WAITOEN2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x248))
+#define EMC_STA_WAITRD2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x24C))
+#define EMC_STA_WAITPAGE2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x250))
+#define EMC_STA_WAITWR2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x254))
+#define EMC_STA_WAITTURN2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x258))
+
+#define EMC_STA_CFG3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x260))
+#define EMC_STA_WAITWEN3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x264))
+#define EMC_STA_WAITOEN3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x268))
+#define EMC_STA_WAITRD3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x26C))
+#define EMC_STA_WAITPAGE3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x270))
+#define EMC_STA_WAITWR3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x274))
+#define EMC_STA_WAITTURN3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x278))
+
+#define EMC_STA_EXT_WAIT (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x080))
+
+
+/* Timer 0 */
+#define TMR0_BASE_ADDR 0xE0004000
+#define T0IR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x00))
+#define T0TCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x04))
+#define T0TC (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x08))
+#define T0PR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x0C))
+#define T0PC (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x10))
+#define T0MCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x14))
+#define T0MR0 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x18))
+#define T0MR1 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x1C))
+#define T0MR2 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x20))
+#define T0MR3 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x24))
+#define T0CCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x28))
+#define T0CR0 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x2C))
+#define T0CR1 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x30))
+#define T0CR2 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x34))
+#define T0CR3 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x38))
+#define T0EMR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x3C))
+#define T0CTCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x70))
+
+/* Timer 1 */
+#define TMR1_BASE_ADDR 0xE0008000
+#define T1IR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x00))
+#define T1TCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x04))
+#define T1TC (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x08))
+#define T1PR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x0C))
+#define T1PC (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x10))
+#define T1MCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x14))
+#define T1MR0 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x18))
+#define T1MR1 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x1C))
+#define T1MR2 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x20))
+#define T1MR3 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x24))
+#define T1CCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x28))
+#define T1CR0 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x2C))
+#define T1CR1 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x30))
+#define T1CR2 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x34))
+#define T1CR3 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x38))
+#define T1EMR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x3C))
+#define T1CTCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x70))
+
+/* Timer 2 */
+#define TMR2_BASE_ADDR 0xE0070000
+#define T2IR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x00))
+#define T2TCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x04))
+#define T2TC (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x08))
+#define T2PR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x0C))
+#define T2PC (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x10))
+#define T2MCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x14))
+#define T2MR0 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x18))
+#define T2MR1 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x1C))
+#define T2MR2 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x20))
+#define T2MR3 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x24))
+#define T2CCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x28))
+#define T2CR0 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x2C))
+#define T2CR1 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x30))
+#define T2CR2 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x34))
+#define T2CR3 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x38))
+#define T2EMR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x3C))
+#define T2CTCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x70))
+
+/* Timer 3 */
+#define TMR3_BASE_ADDR 0xE0074000
+#define T3IR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x00))
+#define T3TCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x04))
+#define T3TC (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x08))
+#define T3PR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x0C))
+#define T3PC (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x10))
+#define T3MCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x14))
+#define T3MR0 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x18))
+#define T3MR1 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x1C))
+#define T3MR2 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x20))
+#define T3MR3 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x24))
+#define T3CCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x28))
+#define T3CR0 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x2C))
+#define T3CR1 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x30))
+#define T3CR2 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x34))
+#define T3CR3 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x38))
+#define T3EMR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x3C))
+#define T3CTCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x70))
+
+
+/* Pulse Width Modulator (PWM) */
+#define PWM0_BASE_ADDR 0xE0014000
+#define PWM0IR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x00))
+#define PWM0TCR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x04))
+#define PWM0TC (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x08))
+#define PWM0PR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x0C))
+#define PWM0PC (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x10))
+#define PWM0MCR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x14))
+#define PWM0MR0 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x18))
+#define PWM0MR1 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x1C))
+#define PWM0MR2 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x20))
+#define PWM0MR3 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x24))
+#define PWM0CCR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x28))
+#define PWM0CR0 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x2C))
+#define PWM0CR1 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x30))
+#define PWM0CR2 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x34))
+#define PWM0CR3 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x38))
+#define PWM0EMR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x3C))
+#define PWM0MR4 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x40))
+#define PWM0MR5 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x44))
+#define PWM0MR6 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x48))
+#define PWM0PCR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x4C))
+#define PWM0LER (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x50))
+#define PWM0CTCR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x70))
+
+#define PWM1_BASE_ADDR 0xE0018000
+#define PWM1IR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x00))
+#define PWM1TCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x04))
+#define PWM1TC (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x08))
+#define PWM1PR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x0C))
+#define PWM1PC (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x10))
+#define PWM1MCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x14))
+#define PWM1MR0 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x18))
+#define PWM1MR1 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x1C))
+#define PWM1MR2 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x20))
+#define PWM1MR3 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x24))
+#define PWM1CCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x28))
+#define PWM1CR0 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x2C))
+#define PWM1CR1 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x30))
+#define PWM1CR2 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x34))
+#define PWM1CR3 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x38))
+#define PWM1EMR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x3C))
+#define PWM1MR4 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x40))
+#define PWM1MR5 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x44))
+#define PWM1MR6 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x48))
+#define PWM1PCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x4C))
+#define PWM1LER (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x50))
+#define PWM1CTCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x70))
+
+
+/* Universal Asynchronous Receiver Transmitter 0 (UART0) */
+#define UART0_BASE_ADDR 0xE000C000
+#define U0RBR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00))
+#define U0THR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00))
+#define U0DLL (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00))
+#define U0DLM (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x04))
+#define U0IER (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x04))
+#define U0IIR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x08))
+#define U0FCR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x08))
+#define U0LCR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x0C))
+#define U0LSR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x14))
+#define U0SCR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x1C))
+#define U0ACR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x20))
+#define U0ICR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x24))
+#define U0FDR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x28))
+#define U0TER (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x30))
+
+/* Universal Asynchronous Receiver Transmitter 1 (UART1) */
+#define UART1_BASE_ADDR 0xE0010000
+#define U1RBR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00))
+#define U1THR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00))
+#define U1DLL (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00))
+#define U1DLM (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x04))
+#define U1IER (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x04))
+#define U1IIR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x08))
+#define U1FCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x08))
+#define U1LCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x0C))
+#define U1MCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x10))
+#define U1LSR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x14))
+#define U1MSR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x18))
+#define U1SCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x1C))
+#define U1ACR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x20))
+#define U1FDR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x28))
+#define U1TER (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x30))
+
+/* Universal Asynchronous Receiver Transmitter 2 (UART2) */
+#define UART2_BASE_ADDR 0xE0078000
+#define U2RBR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00))
+#define U2THR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00))
+#define U2DLL (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00))
+#define U2DLM (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x04))
+#define U2IER (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x04))
+#define U2IIR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x08))
+#define U2FCR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x08))
+#define U2LCR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x0C))
+#define U2LSR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x14))
+#define U2SCR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x1C))
+#define U2ACR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x20))
+#define U2ICR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x24))
+#define U2FDR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x28))
+#define U2TER (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x30))
+
+/* Universal Asynchronous Receiver Transmitter 3 (UART3) */
+#define UART3_BASE_ADDR 0xE007C000
+#define U3RBR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00))
+#define U3THR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00))
+#define U3DLL (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00))
+#define U3DLM (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x04))
+#define U3IER (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x04))
+#define U3IIR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x08))
+#define U3FCR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x08))
+#define U3LCR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x0C))
+#define U3LSR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x14))
+#define U3SCR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x1C))
+#define U3ACR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x20))
+#define U3ICR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x24))
+#define U3FDR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x28))
+#define U3TER (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x30))
+
+/* I2C Interface 0 */
+#define I2C0_BASE_ADDR 0xE001C000
+#define I20CONSET (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x00))
+#define I20STAT (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x04))
+#define I20DAT (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x08))
+#define I20ADR (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x0C))
+#define I20SCLH (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x10))
+#define I20SCLL (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x14))
+#define I20CONCLR (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x18))
+
+/* I2C Interface 1 */
+#define I2C1_BASE_ADDR 0xE005C000
+#define I21CONSET (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x00))
+#define I21STAT (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x04))
+#define I21DAT (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x08))
+#define I21ADR (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x0C))
+#define I21SCLH (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x10))
+#define I21SCLL (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x14))
+#define I21CONCLR (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x18))
+
+/* I2C Interface 2 */
+#define I2C2_BASE_ADDR 0xE0080000
+#define I22CONSET (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x00))
+#define I22STAT (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x04))
+#define I22DAT (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x08))
+#define I22ADR (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x0C))
+#define I22SCLH (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x10))
+#define I22SCLL (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x14))
+#define I22CONCLR (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x18))
+
+/* SPI0 (Serial Peripheral Interface 0) */
+#define SPI0_BASE_ADDR 0xE0020000
+#define S0SPCR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x00))
+#define S0SPSR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x04))
+#define S0SPDR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x08))
+#define S0SPCCR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x0C))
+#define S0SPINT (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x1C))
+
+/* SSP0 Controller */
+#define SSP0_BASE_ADDR 0xE0068000
+#define SSP0CR0 (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x00))
+#define SSP0CR1 (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x04))
+#define SSP0DR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x08))
+#define SSP0SR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x0C))
+#define SSP0CPSR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x10))
+#define SSP0IMSC (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x14))
+#define SSP0RIS (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x18))
+#define SSP0MIS (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x1C))
+#define SSP0ICR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x20))
+#define SSP0DMACR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x24))
+
+/* SSP1 Controller */
+#define SSP1_BASE_ADDR 0xE0030000
+#define SSP1CR0 (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x00))
+#define SSP1CR1 (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x04))
+#define SSP1DR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x08))
+#define SSP1SR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x0C))
+#define SSP1CPSR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x10))
+#define SSP1IMSC (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x14))
+#define SSP1RIS (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x18))
+#define SSP1MIS (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x1C))
+#define SSP1ICR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x20))
+#define SSP1DMACR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x24))
+
+
+/* Real Time Clock */
+#define RTC_BASE_ADDR 0xE0024000
+#define RTC_ILR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x00))
+#define RTC_CTC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x04))
+#define RTC_CCR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x08))
+#define RTC_CIIR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x0C))
+#define RTC_AMR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x10))
+#define RTC_CTIME0 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x14))
+#define RTC_CTIME1 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x18))
+#define RTC_CTIME2 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x1C))
+#define RTC_SEC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x20))
+#define RTC_MIN (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x24))
+#define RTC_HOUR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x28))
+#define RTC_DOM (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x2C))
+#define RTC_DOW (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x30))
+#define RTC_DOY (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x34))
+#define RTC_MONTH (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x38))
+#define RTC_YEAR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x3C))
+#define RTC_CISS (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x40))
+#define RTC_ALSEC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x60))
+#define RTC_ALMIN (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x64))
+#define RTC_ALHOUR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x68))
+#define RTC_ALDOM (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x6C))
+#define RTC_ALDOW (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x70))
+#define RTC_ALDOY (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x74))
+#define RTC_ALMON (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x78))
+#define RTC_ALYEAR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x7C))
+#define RTC_PREINT (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x80))
+#define RTC_PREFRAC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x84))
+
+
+/* A/D Converter 0 (AD0) */
+#define AD0_BASE_ADDR 0xE0034000
+#define AD0CR (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x00))
+#define AD0GDR (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x04))
+#define AD0INTEN (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x0C))
+#define AD0DR0 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x10))
+#define AD0DR1 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x14))
+#define AD0DR2 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x18))
+#define AD0DR3 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x1C))
+#define AD0DR4 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x20))
+#define AD0DR5 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x24))
+#define AD0DR6 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x28))
+#define AD0DR7 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x2C))
+#define AD0STAT (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x30))
+
+
+/* D/A Converter */
+#define DAC_BASE_ADDR 0xE006C000
+#define DACR (*(volatile unsigned long *)(DAC_BASE_ADDR + 0x00))
+
+
+/* Watchdog */
+#define WDG_BASE_ADDR 0xE0000000
+#define WDMOD (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x00))
+#define WDTC (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x04))
+#define WDFEED (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x08))
+#define WDTV (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x0C))
+#define WDCLKSEL (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x10))
+
+/* CAN CONTROLLERS AND ACCEPTANCE FILTER */
+#define CAN_ACCEPT_BASE_ADDR 0xE003C000
+#define CAN_AFMR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x00))
+#define CAN_SFF_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x04))
+#define CAN_SFF_GRP_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x08))
+#define CAN_EFF_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x0C))
+#define CAN_EFF_GRP_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x10))
+#define CAN_EOT (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x14))
+#define CAN_LUT_ERR_ADR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x18))
+#define CAN_LUT_ERR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x1C))
+
+#define CAN_CENTRAL_BASE_ADDR 0xE0040000
+#define CAN_TX_SR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x00))
+#define CAN_RX_SR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x04))
+#define CAN_MSR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x08))
+
+#define CAN1_BASE_ADDR 0xE0044000
+#define CAN1MOD (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x00))
+#define CAN1CMR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x04))
+#define CAN1GSR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x08))
+#define CAN1ICR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x0C))
+#define CAN1IER (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x10))
+#define CAN1BTR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x14))
+#define CAN1EWL (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x18))
+#define CAN1SR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x1C))
+#define CAN1RFS (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x20))
+#define CAN1RID (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x24))
+#define CAN1RDA (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x28))
+#define CAN1RDB (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x2C))
+
+#define CAN1TFI1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x30))
+#define CAN1TID1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x34))
+#define CAN1TDA1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x38))
+#define CAN1TDB1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x3C))
+#define CAN1TFI2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x40))
+#define CAN1TID2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x44))
+#define CAN1TDA2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x48))
+#define CAN1TDB2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x4C))
+#define CAN1TFI3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x50))
+#define CAN1TID3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x54))
+#define CAN1TDA3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x58))
+#define CAN1TDB3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x5C))
+
+#define CAN2_BASE_ADDR 0xE0048000
+#define CAN2MOD (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x00))
+#define CAN2CMR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x04))
+#define CAN2GSR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x08))
+#define CAN2ICR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x0C))
+#define CAN2IER (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x10))
+#define CAN2BTR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x14))
+#define CAN2EWL (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x18))
+#define CAN2SR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x1C))
+#define CAN2RFS (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x20))
+#define CAN2RID (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x24))
+#define CAN2RDA (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x28))
+#define CAN2RDB (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x2C))
+
+#define CAN2TFI1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x30))
+#define CAN2TID1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x34))
+#define CAN2TDA1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x38))
+#define CAN2TDB1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x3C))
+#define CAN2TFI2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x40))
+#define CAN2TID2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x44))
+#define CAN2TDA2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x48))
+#define CAN2TDB2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x4C))
+#define CAN2TFI3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x50))
+#define CAN2TID3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x54))
+#define CAN2TDA3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x58))
+#define CAN2TDB3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x5C))
+
+
+/* MultiMedia Card Interface(MCI) Controller */
+#define MCI_BASE_ADDR 0xE008C000
+#define MCI_POWER (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x00))
+#define MCI_CLOCK (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x04))
+#define MCI_ARGUMENT (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x08))
+#define MCI_COMMAND (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x0C))
+#define MCI_RESP_CMD (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x10))
+#define MCI_RESP0 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x14))
+#define MCI_RESP1 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x18))
+#define MCI_RESP2 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x1C))
+#define MCI_RESP3 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x20))
+#define MCI_DATA_TMR (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x24))
+#define MCI_DATA_LEN (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x28))
+#define MCI_DATA_CTRL (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x2C))
+#define MCI_DATA_CNT (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x30))
+#define MCI_STATUS (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x34))
+#define MCI_CLEAR (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x38))
+#define MCI_MASK0 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x3C))
+#define MCI_MASK1 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x40))
+#define MCI_FIFO_CNT (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x48))
+#define MCI_FIFO (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x80))
+
+
+/* I2S Interface Controller (I2S) */
+#define I2S_BASE_ADDR 0xE0088000
+#define I2S_DAO (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x00))
+#define I2S_DAI (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x04))
+#define I2S_TX_FIFO (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x08))
+#define I2S_RX_FIFO (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x0C))
+#define I2S_STATE (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x10))
+#define I2S_DMA1 (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x14))
+#define I2S_DMA2 (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x18))
+#define I2S_IRQ (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x1C))
+#define I2S_TXRATE (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x20))
+#define I2S_RXRATE (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x24))
+
+
+/* General-purpose DMA Controller */
+#define DMA_BASE_ADDR 0xFFE04000
+#define GPDMA_INT_STAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x000))
+#define GPDMA_INT_TCSTAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x004))
+#define GPDMA_INT_TCCLR (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x008))
+#define GPDMA_INT_ERR_STAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x00C))
+#define GPDMA_INT_ERR_CLR (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x010))
+#define GPDMA_RAW_INT_TCSTAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x014))
+#define GPDMA_RAW_INT_ERR_STAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x018))
+#define GPDMA_ENABLED_CHNS (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x01C))
+#define GPDMA_SOFT_BREQ (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x020))
+#define GPDMA_SOFT_SREQ (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x024))
+#define GPDMA_SOFT_LBREQ (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x028))
+#define GPDMA_SOFT_LSREQ (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x02C))
+#define GPDMA_CONFIG (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x030))
+#define GPDMA_SYNC (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x034))
+
+/* DMA channel 0 registers */
+#define GPDMA_CH0_SRC (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x100))
+#define GPDMA_CH0_DEST (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x104))
+#define GPDMA_CH0_LLI (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x108))
+#define GPDMA_CH0_CTRL (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x10C))
+#define GPDMA_CH0_CFG (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x110))
+
+/* DMA channel 1 registers */
+#define GPDMA_CH1_SRC (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x120))
+#define GPDMA_CH1_DEST (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x124))
+#define GPDMA_CH1_LLI (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x128))
+#define GPDMA_CH1_CTRL (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x12C))
+#define GPDMA_CH1_CFG (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x130))
+
+
+/* USB Controller */
+#define USB_INT_BASE_ADDR 0xE01FC1C0
+#define USB_BASE_ADDR 0xFFE0C200 /* USB Base Address */
+
+#define USB_INT_STAT (*(volatile unsigned long *)(USB_INT_BASE_ADDR + 0x00))
+
+/* USB Device Interrupt Registers */
+#define DEV_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x00))
+#define DEV_INT_EN (*(volatile unsigned long *)(USB_BASE_ADDR + 0x04))
+#define DEV_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0x08))
+#define DEV_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0x0C))
+#define DEV_INT_PRIO (*(volatile unsigned long *)(USB_BASE_ADDR + 0x2C))
+
+/* USB Device Endpoint Interrupt Registers */
+#define EP_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x30))
+#define EP_INT_EN (*(volatile unsigned long *)(USB_BASE_ADDR + 0x34))
+#define EP_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0x38))
+#define EP_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0x3C))
+#define EP_INT_PRIO (*(volatile unsigned long *)(USB_BASE_ADDR + 0x40))
+
+/* USB Device Endpoint Realization Registers */
+#define REALIZE_EP (*(volatile unsigned long *)(USB_BASE_ADDR + 0x44))
+#define EP_INDEX (*(volatile unsigned long *)(USB_BASE_ADDR + 0x48))
+#define MAXPACKET_SIZE (*(volatile unsigned long *)(USB_BASE_ADDR + 0x4C))
+
+/* USB Device Command Reagisters */
+#define CMD_CODE (*(volatile unsigned long *)(USB_BASE_ADDR + 0x10))
+#define CMD_DATA (*(volatile unsigned long *)(USB_BASE_ADDR + 0x14))
+
+/* USB Device Data Transfer Registers */
+#define RX_DATA (*(volatile unsigned long *)(USB_BASE_ADDR + 0x18))
+#define TX_DATA (*(volatile unsigned long *)(USB_BASE_ADDR + 0x1C))
+#define RX_PLENGTH (*(volatile unsigned long *)(USB_BASE_ADDR + 0x20))
+#define TX_PLENGTH (*(volatile unsigned long *)(USB_BASE_ADDR + 0x24))
+#define USB_CTRL (*(volatile unsigned long *)(USB_BASE_ADDR + 0x28))
+
+/* USB Device DMA Registers */
+#define DMA_REQ_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x50))
+#define DMA_REQ_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0x54))
+#define DMA_REQ_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0x58))
+#define UDCA_HEAD (*(volatile unsigned long *)(USB_BASE_ADDR + 0x80))
+#define EP_DMA_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x84))
+#define EP_DMA_EN (*(volatile unsigned long *)(USB_BASE_ADDR + 0x88))
+#define EP_DMA_DIS (*(volatile unsigned long *)(USB_BASE_ADDR + 0x8C))
+#define DMA_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x90))
+#define DMA_INT_EN (*(volatile unsigned long *)(USB_BASE_ADDR + 0x94))
+#define EOT_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0xA0))
+#define EOT_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0xA4))
+#define EOT_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0xA8))
+#define NDD_REQ_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0xAC))
+#define NDD_REQ_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0xB0))
+#define NDD_REQ_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0xB4))
+#define SYS_ERR_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0xB8))
+#define SYS_ERR_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0xBC))
+#define SYS_ERR_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0xC0))
+
+/* USB Host and OTG registers are for LPC24xx only */
+/* USB Host Controller */
+#define USBHC_BASE_ADDR 0xFFE0C000
+#define HC_REVISION (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x00))
+#define HC_CONTROL (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x04))
+#define HC_CMD_STAT (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x08))
+#define HC_INT_STAT (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x0C))
+#define HC_INT_EN (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x10))
+#define HC_INT_DIS (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x14))
+#define HC_HCCA (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x18))
+#define HC_PERIOD_CUR_ED (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x1C))
+#define HC_CTRL_HEAD_ED (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x20))
+#define HC_CTRL_CUR_ED (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x24))
+#define HC_BULK_HEAD_ED (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x28))
+#define HC_BULK_CUR_ED (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x2C))
+#define HC_DONE_HEAD (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x30))
+#define HC_FM_INTERVAL (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x34))
+#define HC_FM_REMAINING (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x38))
+#define HC_FM_NUMBER (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x3C))
+#define HC_PERIOD_START (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x40))
+#define HC_LS_THRHLD (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x44))
+#define HC_RH_DESCA (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x48))
+#define HC_RH_DESCB (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x4C))
+#define HC_RH_STAT (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x50))
+#define HC_RH_PORT_STAT1 (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x54))
+#define HC_RH_PORT_STAT2 (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x58))
+
+/* USB OTG Controller */
+#define USBOTG_BASE_ADDR 0xFFE0C100
+#define OTG_INT_STAT (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x00))
+#define OTG_INT_EN (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x04))
+#define OTG_INT_SET (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x08))
+#define OTG_INT_CLR (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x0C))
+/* On LPC23xx, the name is USBPortSel, on LPC24xx, the name is OTG_STAT_CTRL */
+#define OTG_STAT_CTRL (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x10))
+#define OTG_TIMER (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x14))
+
+#define USBOTG_I2C_BASE_ADDR 0xFFE0C300
+#define OTG_I2C_RX (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x00))
+#define OTG_I2C_TX (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x00))
+#define OTG_I2C_STS (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x04))
+#define OTG_I2C_CTL (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x08))
+#define OTG_I2C_CLKHI (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x0C))
+#define OTG_I2C_CLKLO (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x10))
+
+/* On LPC23xx, the names are USBClkCtrl and USBClkSt; on LPC24xx, the names are
+OTG_CLK_CTRL and OTG_CLK_STAT respectively. */
+#define USBOTG_CLK_BASE_ADDR 0xFFE0CFF0
+#define OTG_CLK_CTRL (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x04))
+#define OTG_CLK_STAT (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x08))
+
+/* Note: below three register name convention is for LPC23xx USB device only, match
+with the spec. update in USB Device Section. */
+#define USBPortSel (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x10))
+#define USBClkCtrl (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x04))
+#define USBClkSt (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x08))
+
+/* Ethernet MAC (32 bit data bus) -- all registers are RW unless indicated in parentheses */
+#define MAC_BASE_ADDR 0xFFE00000 /* AHB Peripheral # 0 */
+#define MAC_MAC1 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x000)) /* MAC config reg 1 */
+#define MAC_MAC2 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x004)) /* MAC config reg 2 */
+#define MAC_IPGT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x008)) /* b2b InterPacketGap reg */
+#define MAC_IPGR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x00C)) /* non b2b InterPacketGap reg */
+#define MAC_CLRT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x010)) /* CoLlision window/ReTry reg */
+#define MAC_MAXF (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x014)) /* MAXimum Frame reg */
+#define MAC_SUPP (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x018)) /* PHY SUPPort reg */
+#define MAC_TEST (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x01C)) /* TEST reg */
+#define MAC_MCFG (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x020)) /* MII Mgmt ConFiG reg */
+#define MAC_MCMD (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x024)) /* MII Mgmt CoMmanD reg */
+#define MAC_MADR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x028)) /* MII Mgmt ADdRess reg */
+#define MAC_MWTD (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x02C)) /* MII Mgmt WriTe Data reg (WO) */
+#define MAC_MRDD (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x030)) /* MII Mgmt ReaD Data reg (RO) */
+#define MAC_MIND (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x034)) /* MII Mgmt INDicators reg (RO) */
+
+#define MAC_SA0 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x040)) /* Station Address 0 reg */
+#define MAC_SA1 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x044)) /* Station Address 1 reg */
+#define MAC_SA2 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x048)) /* Station Address 2 reg */
+
+#define MAC_COMMAND (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x100)) /* Command reg */
+#define MAC_STATUS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x104)) /* Status reg (RO) */
+#define MAC_RXDESCRIPTOR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x108)) /* Rx descriptor base address reg */
+#define MAC_RXSTATUS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x10C)) /* Rx status base address reg */
+#define MAC_RXDESCRIPTORNUM (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x110)) /* Rx number of descriptors reg */
+#define MAC_RXPRODUCEINDEX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x114)) /* Rx produce index reg (RO) */
+#define MAC_RXCONSUMEINDEX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x118)) /* Rx consume index reg */
+#define MAC_TXDESCRIPTOR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x11C)) /* Tx descriptor base address reg */
+#define MAC_TXSTATUS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x120)) /* Tx status base address reg */
+#define MAC_TXDESCRIPTORNUM (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x124)) /* Tx number of descriptors reg */
+#define MAC_TXPRODUCEINDEX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x128)) /* Tx produce index reg */
+#define MAC_TXCONSUMEINDEX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x12C)) /* Tx consume index reg (RO) */
+
+#define MAC_TSV0 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x158)) /* Tx status vector 0 reg (RO) */
+#define MAC_TSV1 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x15C)) /* Tx status vector 1 reg (RO) */
+#define MAC_RSV (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x160)) /* Rx status vector reg (RO) */
+
+#define MAC_FLOWCONTROLCNT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x170)) /* Flow control counter reg */
+#define MAC_FLOWCONTROLSTS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x174)) /* Flow control status reg */
+
+#define MAC_RXFILTERCTRL (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x200)) /* Rx filter ctrl reg */
+#define MAC_RXFILTERWOLSTS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x204)) /* Rx filter WoL status reg (RO) */
+#define MAC_RXFILTERWOLCLR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x208)) /* Rx filter WoL clear reg (WO) */
+
+#define MAC_HASHFILTERL (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x210)) /* Hash filter LSBs reg */
+#define MAC_HASHFILTERH (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x214)) /* Hash filter MSBs reg */
+
+#define MAC_INTSTATUS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE0)) /* Interrupt status reg (RO) */
+#define MAC_INTENABLE (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE4)) /* Interrupt enable reg */
+#define MAC_INTCLEAR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE8)) /* Interrupt clear reg (WO) */
+#define MAC_INTSET (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFEC)) /* Interrupt set reg (WO) */
+
+#define MAC_POWERDOWN (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFF4)) /* Power-down reg */
+#define MAC_MODULEID (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFFC)) /* Module ID reg (RO) */
+
+#endif // __LPC23xx_H
+
Added: branches/eagle_mmc/src/platform/lpc24xx/conf.py
===================================================================
--- branches/eagle_mmc/src/platform/lpc24xx/conf.py 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lpc24xx/conf.py 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,39 @@
+# Configuration file for the LPC24xx backend
+
+cpumode = ARGUMENTS.get( 'cpumode', 'arm' ).lower()
+
+specific_files = "startup.s irq.c target.c platform.c"
+if cputype == 'LPC2468':
+ ldscript = "lpc2468.lds"
+else:
+ print "Invalid CPU %s" % cputype
+ sys.exit( -1 )
+
+# Check CPU mode
+if cpumode == 'arm':
+ modeflag = ''
+elif cpumode == 'thumb':
+ modeflag = '-mthumb'
+else:
+ print "Invalid CPU mode %s", cpumode
+ sys.exit( -1 )
+
+# Prepend with path
+specific_files = " ".join( [ "src/platform/%s/%s" % ( platform, f ) for f in specific_files.split() ] )
+ldscript = "src/platform/%s/%s" % ( platform, ldscript )
+
+# Toolset data
+tools[ 'lpc24xx' ] = {}
+tools[ 'lpc24xx' ][ 'cccom' ] = "%s -mcpu=arm7tdmi %s %s $_CPPINCFLAGS -ffunction-sections -fdata-sections %s -Wall -c $SOURCE -o $TARGET" % ( toolset[ 'compile' ], modeflag, opt, cdefs )
+tools[ 'lpc24xx' ][ 'linkcom' ] = "%s -nostartfiles -nostdlib %s -T %s -Wl,--gc-sections -Wl,-e,entry -Wl,--allow-multiple-definition -o $TARGET $SOURCES %s -lc -lgcc -lm" % ( toolset[ 'compile' ], modeflag, ldscript, local_libs )
+tools[ 'lpc24xx' ][ 'ascom' ] = "%s -x assembler-with-cpp $_CPPINCFLAGS -mcpu=arm7tdmi %s %s -D__ASSEMBLY__ -Wall -c $SOURCE -o $TARGET" % ( toolset[ 'compile' ], modeflag, cdefs )
+
+# Programming function for LPC24xx
+def progfunc_lpx24xx( target, source, env ):
+ outname = output + ".elf"
+ os.system( "%s %s" % ( toolset[ 'size' ], outname ) )
+ print "Generating binary image..."
+ os.system( "%s -O ihex %s %s.hex" % ( toolset[ 'bin' ], outname, output ) )
+
+tools[ 'lpc24xx' ][ 'progfunc' ] = progfunc_lpx24xx
+
Added: branches/eagle_mmc/src/platform/lpc24xx/irq.c
===================================================================
--- branches/eagle_mmc/src/platform/lpc24xx/irq.c 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lpc24xx/irq.c 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,108 @@
+/*****************************************************************************
+ * irq.c: Interrupt handler C file for NXP LPC23xx/24xx Family Microprocessors
+ *
+ * Copyright(C) 2006, NXP Semiconductor
+ * All rights reserved.
+ *
+ * History
+ * 2006.07.13 ver 1.00 Prelimnary version, first Release
+ *
+******************************************************************************/
+#include "LPC23xx.h" /* LPC23XX/24xx Peripheral Registers */
+#include "type.h"
+#include "irq.h"
+#if FIQ
+#include "timer.h"
+#endif
+
+/******************************************************************************
+** Function name: FIQ_Handler
+**
+** Descriptions: FIQ interrupt handler called in startup
+** parameters:
+**
+** Returned value:
+**
+******************************************************************************/
+// [TODO] make this GCC compatible if needed
+#if FIQ
+void FIQ_Handler( void ) __irq
+{
+//#if FIQ
+ if ( VICFIQStatus & (0x1<<4) && VICIntEnable & (0x1<<4) )
+ {
+ Timer0FIQHandler();
+ }
+ if ( VICFIQStatus & (0x1<<5) && VICIntEnable & (0x1<<5) )
+ {
+ Timer1FIQHandler();
+ }
+ return;
+//#endif
+}
+#endif
+
+/* Initialize the interrupt controller */
+/******************************************************************************
+** Function name: init_VIC
+**
+** Descriptions: Initialize VIC interrupt controller.
+** parameters: None
+** Returned value: None
+**
+******************************************************************************/
+void init_VIC(void)
+{
+ DWORD i = 0;
+ DWORD *vect_addr, *vect_prio;
+
+ /* initialize VIC*/
+ VICIntEnClr = 0xffffffff;
+ VICVectAddr = 0;
+ VICIntSelect = 0;
+
+ /* set all the vector and vector control register to 0 */
+ for ( i = 0; i < VIC_SIZE; i++ )
+ {
+ vect_addr = (DWORD *)(VIC_BASE_ADDR + VECT_ADDR_INDEX + i*4);
+ vect_prio = (DWORD *)(VIC_BASE_ADDR + VECT_PRIO_INDEX + i*4);
+ *vect_addr = 0x0;
+ *vect_prio = 0xF;
+ }
+ return;
+}
+
+/******************************************************************************
+** Function name: install_irq
+**
+** Descriptions: Install interrupt handler
+** parameters: Interrupt number, interrupt handler address,
+** interrupt priority
+** Returned value: true or false, return false if IntNum is out of range
+**
+******************************************************************************/
+DWORD install_irq( DWORD IntNumber, void *HandlerAddr, DWORD Priority )
+{
+ DWORD *vect_addr;
+ DWORD *vect_prio;
+
+ VICIntEnClr = 1 << IntNumber; /* Disable Interrupt */
+ if ( IntNumber >= VIC_SIZE )
+ {
+ return ( FALSE );
+ }
+ else
+ {
+ /* find first un-assigned VIC address for the handler */
+ vect_addr = (DWORD *)(VIC_BASE_ADDR + VECT_ADDR_INDEX + IntNumber*4);
+ vect_prio = (DWORD *)(VIC_BASE_ADDR + VECT_PRIO_INDEX + IntNumber*4);
+ *vect_addr = (DWORD)HandlerAddr; /* set interrupt vector */
+ *vect_prio = Priority;
+ VICIntEnable = 1 << IntNumber; /* Enable Interrupt */
+ return( TRUE );
+ }
+}
+
+/******************************************************************************
+** End Of File
+******************************************************************************/
Added: branches/eagle_mmc/src/platform/lpc24xx/irq.h
===================================================================
--- branches/eagle_mmc/src/platform/lpc24xx/irq.h 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lpc24xx/irq.h 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,79 @@
+/******************************************************************************
+ * irq.h: Interrupt related Header file for NXP LPC23xx/24xx Family
+ * Microprocessors
+ *
+ * Copyright(C) 2006, NXP Semiconductor
+ * All rights reserved.
+ *
+ * History
+ * 2006.09.01 ver 1.00 Prelimnary version, first Release
+ *
+******************************************************************************/
+#ifndef __IRQ_H
+#define __IRQ_H
+
+#define I_Bit 0x80
+#define F_Bit 0x40
+
+#define SYS32Mode 0x1F
+#define IRQ32Mode 0x12
+#define FIQ32Mode 0x11
+
+/* Use FIQ, set below to 1, otherwise, it's 0 */
+#define FIQ 0
+
+#define HIGHEST_PRIORITY 0x01
+#define LOWEST_PRIORITY 0x0F
+
+#define WDT_INT 0
+#define SWI_INT 1
+#define ARM_CORE0_INT 2
+#define ARM_CORE1_INT 3
+#define TIMER0_INT 4
+#define TIMER1_INT 5
+#define UART0_INT 6
+#define UART1_INT 7
+#define PWM0_1_INT 8
+#define I2C0_INT 9
+#define SPI0_INT 10 /* SPI and SSP0 share VIC slot */
+#define SSP0_INT 10
+#define SSP1_INT 11
+#define PLL_INT 12
+#define RTC_INT 13
+#define EINT0_INT 14
+#define EINT1_INT 15
+#define EINT2_INT 16
+#define EINT3_INT 17
+#define ADC0_INT 18
+#define I2C1_INT 19
+#define BOD_INT 20
+#define EMAC_INT 21
+#define USB_INT 22
+#define CAN_INT 23
+#define MCI_INT 24
+#define GPDMA_INT 25
+#define TIMER2_INT 26
+#define TIMER3_INT 27
+#define UART2_INT 28
+#define UART3_INT 29
+#define I2C2_INT 30
+#define I2S_INT 31
+
+#define VIC_SIZE 32
+
+#define VECT_ADDR_INDEX 0x100
+#define VECT_PRIO_INDEX 0x200
+
+/* Be aware that, from compiler to compiler, nested interrupt will have to
+be handled differently. More details can be found in Philips LPC2000
+family app-note AN10381 */
+
+void init_VIC( void );
+DWORD install_irq( DWORD IntNumber, void *HandlerAddr, DWORD Priority );
+
+#endif /* end __IRQ_H */
+
+/******************************************************************************
+** End Of File
+******************************************************************************/
+
Added: branches/eagle_mmc/src/platform/lpc24xx/lpc2468.lds
===================================================================
--- branches/eagle_mmc/src/platform/lpc24xx/lpc2468.lds 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lpc24xx/lpc2468.lds 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,63 @@
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+
+MEMORY
+{
+ sram (W!RX) : ORIGIN = 0x40000000, LENGTH = 96k
+ flash (RX) : ORIGIN = 0x0, LENGTH = 512k
+}
+
+SECTIONS
+{
+ .fixed :
+ {
+ . = ALIGN(4);
+ _sfixed = .;
+ PROVIDE(stext = .);
+ KEEP(*(.vectors))
+ *(.text .text.*)
+ *(.rodata .rodata.*)
+ *(.gnu.linkonce.t.*)
+ *(.glue_7)
+ *(.glue_7t)
+ *(.gcc_except_table)
+ *(.gnu.linkonce.r.*)
+ . = ALIGN(4);
+ _efixed = .;
+ PROVIDE(etext = .);
+ _fini = .;
+ *(.fini)
+ } >flash
+
+ .relocate : AT (_efixed)
+ {
+ . = ALIGN(4);
+ _srelocate = .;
+ *(.data .data.*)
+ *(.gnu.linkonce.d.*)
+ . = ALIGN(4);
+ _erelocate = .;
+ } >sram
+
+ .ARM.extab :
+ {
+ *(.ARM.extab*)
+ } >sram
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx*)
+ } >sram
+ __exidx_end = .;
+
+ .bss (NOLOAD) : {
+ _szero = .;
+ *(.bss .bss.*)
+ *(.gnu.linkonce.b.*)
+ *(COMMON)
+ _ezero = .;
+ } >sram
+
+ end = .;
+}
Added: branches/eagle_mmc/src/platform/lpc24xx/platform.c
===================================================================
--- branches/eagle_mmc/src/platform/lpc24xx/platform.c 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lpc24xx/platform.c 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,498 @@
+// Platform-dependent functions
+
+#include "platform.h"
+#include "type.h"
+#include "devman.h"
+#include "genstd.h"
+#include "stacks.h"
+#include <reent.h>
+#include <errno.h>
+#include <string.h>
+#include <ctype.h>
+#include <stdio.h>
+#include "utils.h"
+#include "common.h"
+#include "platform_conf.h"
+
+// Platform includes
+#include "LPC23xx.h" /* LPC23xx/24xx definitions */
+#include "target.h"
+#include "irq.h"
+#include "uart.h"
+
+extern void enable_ints();
+extern void disable_ints();
+
+// ****************************************************************************
+// Platform initialization
+
+static void platform_setup_timers();
+static void platform_setup_pwm();
+
+// Power management definitions
+enum
+{
+ PCUART2 = 1ULL << 24,
+ PCUART3 = 1ULL << 25,
+ PCTIM2 = 1ULL << 22,
+ PCTIM3 = 1ULL << 23
+};
+
+// CPU initialization
+static void platform_setup_cpu()
+{
+ // Enable clock for UART2 and UART3
+ PCONP |= PCUART2 | PCUART3;
+
+ // Set clock for all the UARTs to the system clock (helps in baud generation)
+ PCLKSEL0 = ( PCLKSEL0 & 0xFFFFFC3F ) | 0x00000140;
+ PCLKSEL1 = ( PCLKSEL1 & 0xFFF0FFFF ) | 0x00050000;
+
+ // Enable clock for Timer 2 and Timer 3
+ PCONP |= PCTIM2 | PCTIM3;
+
+ // Setup GPIO0 and GPIO1 in fast mode
+ SCS |= 1;
+}
+
+int platform_init()
+{
+ // Complete CPU initialization
+ platform_setup_cpu();
+
+ // Setup peripherals
+ platform_setup_timers();
+ platform_setup_pwm();
+
+ // Initialize console UART
+ platform_uart_setup( CON_UART_ID, CON_UART_SPEED, 8, PLATFORM_UART_PARITY_NONE, PLATFORM_UART_STOPBITS_1 );
+
+ // Common platform initialization code
+ cmn_platform_init();
+
+ return PLATFORM_OK;
+}
+
+// ****************************************************************************
+// PIO section
+
+static const u32 pio_fiodir[ NUM_PIO ] = { ( u32 )&FIO0DIR, ( u32 )&FIO1DIR, ( u32 )&FIO2DIR, ( u32 )&FIO3DIR, ( u32 )&FIO4DIR };
+static const u32 pio_fiopin[ NUM_PIO ] = { ( u32 )&FIO0PIN, ( u32 )&FIO1PIN, ( u32 )&FIO2PIN, ( u32 )&FIO3PIN, ( u32 )&FIO4PIN };
+static const u32 pio_fioset[ NUM_PIO ] = { ( u32 )&FIO0SET, ( u32 )&FIO1SET, ( u32 )&FIO2SET, ( u32 )&FIO3SET, ( u32 )&FIO4SET };
+static const u32 pio_fioclr[ NUM_PIO ] = { ( u32 )&FIO0CLR, ( u32 )&FIO1CLR, ( u32 )&FIO2CLR, ( u32 )&FIO3CLR, ( u32 )&FIO4CLR };
+
+// The platform I/O functions
+pio_type platform_pio_op( unsigned port, pio_type pinmask, int op )
+{
+ pio_type retval = 1;
+ PREG FIOxDIR = ( PREG )pio_fiodir[ port ];
+ PREG FIOxPIN = ( PREG )pio_fiopin[ port ];
+ PREG FIOxSET = ( PREG )pio_fioset[ port ];
+ PREG FIOxCLR = ( PREG )pio_fioclr[ port ];
+
+ switch( op )
+ {
+ case PLATFORM_IO_PORT_SET_VALUE:
+ *FIOxPIN = pinmask;
+ break;
+
+ case PLATFORM_IO_PIN_SET:
+ *FIOxSET = pinmask;
+ break;
+
+ case PLATFORM_IO_PIN_CLEAR:
+ *FIOxCLR = pinmask;
+ break;
+
+ case PLATFORM_IO_PORT_DIR_OUTPUT:
+ *FIOxDIR = 0xFFFFFFFF;
+ break;
+
+ case PLATFORM_IO_PIN_DIR_OUTPUT:
+ *FIOxDIR |= pinmask;
+ break;
+
+ case PLATFORM_IO_PORT_DIR_INPUT:
+ *FIOxDIR = 0;
+ break;
+
+ case PLATFORM_IO_PIN_DIR_INPUT:
+ *FIOxDIR &= ~pinmask;
+ break;
+
+ case PLATFORM_IO_PORT_GET_VALUE:
+ retval = *FIOxPIN;
+ break;
+
+ case PLATFORM_IO_PIN_GET:
+ retval =( *FIOxPIN & pinmask ) ? 1 : 0;
+ break;
+
+ default:
+ retval = 0;
+ break;
+ }
+ return retval;
+}
+
+// ****************************************************************************
+// UART section
+
+// UART0: Rx = P0.3, Tx = P0.2
+// The other UARTs have assignable Rx/Tx pins and thus have to be configured
+// by the user
+static const u32 uart_lcr[ NUM_UART ] = { ( u32 )&U0LCR, ( u32 )&U1LCR, ( u32 )&U2LCR, ( u32 )&U3LCR };
+static const u32 uart_dlm[ NUM_UART ] = { ( u32 )&U0DLM, ( u32 )&U1DLM, ( u32 )&U2DLM, ( u32 )&U3DLM };
+static const u32 uart_dll[ NUM_UART ] = { ( u32 )&U0DLL, ( u32 )&U1DLL, ( u32 )&U2DLL, ( u32 )&U3DLL };
+static const u32 uart_fcr[ NUM_UART ] = { ( u32 )&U0FCR, ( u32 )&U1FCR, ( u32 )&U2FCR, ( u32 )&U3FCR };
+static const u32 uart_thr[ NUM_UART ] = { ( u32 )&U0THR, ( u32 )&U1THR, ( u32 )&U2THR, ( u32 )&U3THR };
+static const u32 uart_lsr[ NUM_UART ] = { ( u32 )&U0LSR, ( u32 )&U1LSR, ( u32 )&U2LSR, ( u32 )&U3LSR };
+static const u32 uart_rbr[ NUM_UART ] = { ( u32 )&U0RBR, ( u32 )&U1RBR, ( u32 )&U2RBR, ( u32 )&U3RBR };
+
+u32 platform_uart_setup( unsigned id, u32 baud, int databits, int parity, int stopbits )
+{
+ u32 temp;
+
+ PREG UxLCR = ( PREG )uart_lcr[ id ];
+ PREG UxDLM = ( PREG )uart_dlm[ id ];
+ PREG UxDLL = ( PREG )uart_dll[ id ];
+ PREG UxFCR = ( PREG )uart_fcr[ id ];
+
+ // Set data bits, parity, stop bit
+ temp = 0;
+ switch( databits )
+ {
+ case 5:
+ temp |= UART_DATABITS_5;
+ break;
+
+ case 6:
+ temp |= UART_DATABITS_6;
+ break;
+
+ case 7:
+ temp |= UART_DATABITS_7;
+ break;
+
+ case 8:
+ temp |= UART_DATABITS_8;
+ break;
+ }
+ if( stopbits == PLATFORM_UART_STOPBITS_2 )
+ temp |= UART_STOPBITS_2;
+ else
+ temp |= UART_STOPBITS_1;
+ if( parity != PLATFORM_UART_PARITY_NONE )
+ {
+ temp |= UART_PARITY_ENABLE;
+ if( parity == PLATFORM_UART_PARITY_ODD )
+ temp |= UART_PARITY_ODD;
+ else
+ temp |= UART_PARITY_EVEN;
+ }
+ *UxLCR = temp;
+
+ // Divisor computation
+ temp = ( Fpclk_UART >> 4 ) / baud;
+ // Set baud and divisors
+ *UxLCR |= UART_DLAB_ENABLE;
+ *UxDLM = temp >> 8;
+ *UxDLL = temp & 0xFF;
+ *UxLCR &= ~UART_DLAB_ENABLE;
+
+ // Enable and reset Tx and Rx FIFOs
+ *UxFCR = UART_FIFO_ENABLE | UART_RXFIFO_RESET | UART_TXFIFO_RESET;
+
+ // Setup PIOs for UART0. For the other ports, the user needs to specify what pin(s)
+ // are allocated for UART Rx/Tx.
+ if( id == 0 )
+ PINSEL0 = ( PINSEL0 & 0xFFFFFF0F ) | 0x00000050;
+
+ // Return the actual baud
+ return ( Fpclk_UART >> 4 ) / temp;
+}
+
+void platform_uart_send( unsigned id, u8 data )
+{
+ PREG UxTHR = ( PREG )uart_thr[ id ];
+ PREG UxLSR = ( PREG )uart_lsr[ id ];
+
+ while( ( *UxLSR & LSR_THRE ) == 0 );
+ *UxTHR = data;
+}
+
+int platform_s_uart_recv( unsigned id, s32 timeout )
+{
+ PREG UxLSR = ( PREG )uart_lsr[ id ];
+ PREG UxRBR = ( PREG )uart_rbr[ id ];
+
+ if( timeout == 0 )
+ {
+ // Return data only if already available
+ if( *UxLSR & LSR_RDR )
+ return *UxRBR;
+ else
+ return -1;
+ }
+ while( ( *UxLSR & LSR_RDR ) == 0 );
+ return *UxRBR;
+}
+
+// ****************************************************************************
+// Timer section
+
+static const u32 tmr_tcr[] = { ( u32 )&T0TCR, ( u32 )&T1TCR, ( u32 )&T2TCR, ( u32 )&T3TCR };
+static const u32 tmr_tc[] = { ( u32 )&T0TC, ( u32 )&T1TC, ( u32 )&T2TC, ( u32 )&T3TC };
+static const u32 tmr_pr[] = { ( u32 )&T0PR, ( u32 )&T1PR, ( u32 )&T2PR, ( u32 )&T3PR };
+static const u32 tmr_pc[] = { ( u32 )&T0PC, ( u32 )&T1PC, ( u32 )&T2PC, ( u32 )&T3PC };
+
+// Timer register definitions
+enum
+{
+ TMR_ENABLE = 1,
+ TMR_RESET = 2
+};
+
+// Helper function: get timer clock
+static u32 platform_timer_get_clock( unsigned id )
+{
+ PREG TxPR = ( PREG )tmr_pr[ id ];
+
+ return Fpclk / ( *TxPR + 1 );
+}
+
+// Helper function: set timer clock
+static u32 platform_timer_set_clock( unsigned id, u32 clock )
+{
+ u32 div = Fpclk / clock, prevtc;
+ PREG TxPR = ( PREG )tmr_pr[ id ];
+ PREG TxPC = ( PREG )tmr_pc[ id ];
+ PREG TxTCR = ( PREG )tmr_tcr[ id ];
+
+ prevtc = *TxTCR;
+ *TxTCR = 0;
+ *TxPC = 0;
+ *TxPR = div - 1;
+ *TxTCR = prevtc;
+ return Fpclk / div;
+}
+
+#if VTMR_NUM_TIMERS > 0
+static void __attribute__((interrupt ("IRQ"))) tmr_int_handler()
+{
+ T3IR = 1; // clear interrupt
+ cmn_virtual_timer_cb();
+ VICVectAddr = 0; // ACK interrupt
+}
+#endif
+
+// Helper function: setup timers
+static void platform_setup_timers()
+{
+ unsigned i;
+ PREG TxTCR;
+
+ // Set base frequency to 1MHz, as we can't use a better resolution anyway
+ for( i = 0; i < 4; i ++ )
+ {
+ TxTCR = ( PREG )tmr_tcr[ i ];
+ *TxTCR = 0;
+ platform_timer_set_clock( i, 1000000ULL );
+ }
+#if VTMR_NUM_TIMERS > 0
+ // Setup virtual timers here
+ // Timer 3 is allocated for virtual timers and nothing else in this case
+ T3TCR = TMR_RESET;
+ T3MR0 = 1000000ULL / VTMR_FREQ_HZ - 1;
+ T3IR = 0xFF;
+ // Set interrupt handle and eanble timer interrupt (and global interrupts)
+ T3MCR = 0x03; // interrupt on match with MR0 and clear on match
+ install_irq( TIMER3_INT, tmr_int_handler, HIGHEST_PRIORITY );
+ platform_cpu_enable_interrupts();
+ // Start timer
+ T3TCR = TMR_ENABLE;
+#endif
+}
+
+void platform_s_timer_delay( unsigned id, u32 delay_us )
+{
+ PREG TxTCR = ( PREG )tmr_tcr[ id ];
+ PREG TxTC = ( PREG )tmr_tc[ id ];
+ u32 last;
+
+ last = ( ( u64 )delay_us * platform_timer_get_clock( id ) ) / 1000000;
+ *TxTCR = TMR_ENABLE | TMR_RESET;
+ *TxTCR = TMR_ENABLE;
+ while( *TxTC < last );
+}
+
+u32 platform_s_timer_op( unsigned id, int op, u32 data )
+{
+ u32 res = 0;
+ PREG TxTCR = ( PREG )tmr_tcr[ id ];
+ PREG TxTC = ( PREG )tmr_tc[ id ];
+
+ switch( op )
+ {
+ case PLATFORM_TIMER_OP_START:
+ *TxTCR = TMR_ENABLE | TMR_RESET;
+ *TxTCR = TMR_ENABLE;
+ break;
+
+ case PLATFORM_TIMER_OP_READ:
+ res = *TxTC;
+ break;
+
+ case PLATFORM_TIMER_OP_GET_MAX_DELAY:
+ res = platform_timer_get_diff_us( id, 0, 0xFFFFFFFF );
+ break;
+
+ case PLATFORM_TIMER_OP_GET_MIN_DELAY:
+ res = platform_timer_get_diff_us( id, 0, 1 );
+ break;
+
+ case PLATFORM_TIMER_OP_SET_CLOCK:
+ res = platform_timer_set_clock( id, data );
+ break;
+
+ case PLATFORM_TIMER_OP_GET_CLOCK:
+ res = platform_timer_get_clock( id );
+ break;
+ }
+ return res;
+}
+
+// ****************************************************************************
+// CPU functions
+
+void platform_cpu_enable_interrupts()
+{
+ enable_ints();
+}
+
+void platform_cpu_disable_interrupts()
+{
+ disable_ints();
+}
+
+// ****************************************************************************
+// PWM functions
+
+static const u32 pwm_tcr[] = { ( u32 )&PWM0TCR, ( u32 )&PWM1TCR };
+static const u32 pwm_pr[] = { ( u32 )&PWM0PR, ( u32 )&PWM1PR };
+static const u32 pwm_pc[] = { ( u32 )&PWM0PC, ( u32 )&PWM1PC };
+static const u32 pwm_pcr[] = { ( u32 )&PWM0PCR, ( u32 )&PWM1PCR };
+static const u32 pwm_mcr[] = { ( u32 )&PWM0MCR, ( u32 )&PWM1MCR };
+static const u32 pwm_ler[] = { ( u32 )&PWM0LER, ( u32 )&PWM1LER };
+static const u32 pwm_channels[ 2 ][ 6 ] =
+{
+ { ( u32 )&PWM0MR1, ( u32 )&PWM0MR2, ( u32 )&PWM0MR3, ( u32 )&PWM0MR4, ( u32 )&PWM0MR5, ( u32 )&PWM0MR6 },
+ { ( u32 )&PWM1MR1, ( u32 )&PWM1MR2, ( u32 )&PWM1MR3, ( u32 )&PWM1MR4, ( u32 )&PWM1MR5, ( u32 )&PWM1MR6 },
+};
+
+// Timer register definitions
+enum
+{
+ PWM_ENABLE = 1,
+ PWM_RESET = 2,
+ PWM_MODE = 8,
+ PWM_ENABLE_1 = 1 << 9,
+ PWM_ENABLE_2 = 1 << 10,
+ PWM_ENABLE_3 = 1 << 11,
+ PWM_ENABLE_4 = 1 << 12,
+ PWM_ENABLE_5 = 1 << 13,
+ PWM_ENABLE_6 = 1 << 14,
+};
+
+// Helper function: get timer clock
+static u32 platform_pwm_get_clock( unsigned id )
+{
+ unsigned pwmid = id / 6;
+ PREG PWMxPR = ( PREG )pwm_pr[ pwmid ];
+
+ return Fpclk / ( *PWMxPR + 1 );
+}
+
+// Helper function: set timer clock
+static u32 platform_pwm_set_clock( unsigned id, u32 clock )
+{
+ u32 div = Fpclk / clock, prevtc;
+ unsigned pwmid = id / 6;
+ PREG PWMxPR = ( PREG )pwm_pr[ pwmid ];
+ PREG PWMxPC = ( PREG )pwm_pc[ pwmid ];
+ PREG PWMxTCR = ( PREG )pwm_tcr[ pwmid ];
+
+ prevtc = *PWMxTCR;
+ *PWMxTCR = 0;
+ *PWMxPC = 0;
+ *PWMxPR = div - 1;
+ *PWMxTCR = prevtc;
+ return Fpclk / div;
+}
+
+// Setup all PWM channels
+static void platform_setup_pwm()
+{
+ unsigned i;
+ PREG temp;
+
+ for( i = 0; i < 2; i ++ )
+ {
+ // Keep clock in reset, set PWM code
+ temp = ( PREG )pwm_tcr[ i ];
+ *temp = PWM_RESET;
+ // Set match mode (reset on MR0 match)
+ temp = ( PREG )pwm_mcr[ i ];
+ *temp = 0x02;
+ // Set base frequency to 1MHz
+ platform_pwm_set_clock( i * 6, 1000000 );
+ }
+}
+
+u32 platform_pwm_setup( unsigned id, u32 frequency, unsigned duty )
+{
+ unsigned pwmid = id / 6, chid = id % 6;
+ PREG PWMxMR0 = pwmid == 0 ? ( PREG )&PWM0MR0 : ( PREG )&PWM1MR0;
+ PREG PWMxMRc = ( PREG )pwm_channels[ pwmid ][ chid ];
+ PREG PWMxLER = ( PREG )pwm_ler[ pwmid ];
+ u32 divisor;
+
+ divisor = platform_pwm_get_clock( id ) / frequency - 1;
+ *PWMxMR0 = divisor;
+ *PWMxMRc = ( divisor * duty ) / 100;
+ *PWMxLER = 1 | ( 1 << ( chid + 1 ) );
+
+ return platform_pwm_get_clock( id ) / divisor;
+}
+
+u32 platform_pwm_op( unsigned id, int op, u32 data )
+{
+ u32 res = 0;
+ unsigned pwmid = id / 6;
+ PREG PWMxTCR = ( PREG )pwm_tcr[ pwmid ];
+ PREG PWMxPCR = ( PREG )pwm_pcr[ pwmid ];
+
+ switch( op )
+ {
+ case PLATFORM_PWM_OP_START:
+ *PWMxPCR = PWM_ENABLE_1 | PWM_ENABLE_2 | PWM_ENABLE_3 | PWM_ENABLE_4 | PWM_ENABLE_5 | PWM_ENABLE_6;
+ *PWMxTCR = PWM_ENABLE | PWM_MODE;
+ break;
+
+ case PLATFORM_PWM_OP_STOP:
+ *PWMxPCR = 0;
+ *PWMxTCR = PWM_RESET;
+ break;
+
+ case PLATFORM_PWM_OP_SET_CLOCK:
+ res = platform_pwm_set_clock( id, data );
+ break;
+
+ case PLATFORM_PWM_OP_GET_CLOCK:
+ res = platform_pwm_get_clock( id );
+ break;
+ }
+
+ return res;
+}
+
Added: branches/eagle_mmc/src/platform/lpc24xx/platform_conf.h
===================================================================
--- branches/eagle_mmc/src/platform/lpc24xx/platform_conf.h 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lpc24xx/platform_conf.h 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,118 @@
+// eLua platform configuration
+
+#ifndef __PLATFORM_CONF_H__
+#define __PLATFORM_CONF_H__
+
+#include "auxmods.h"
+#include "stacks.h"
+#include "target.h"
+
+// *****************************************************************************
+// Define here what components you want for this platform
+
+#define BUILD_XMODEM
+#define BUILD_SHELL
+#define BUILD_ROMFS
+#define BUILD_TERM
+#define BUILD_CON_GENERIC
+
+// *****************************************************************************
+// UART/Timer IDs configuration data (used in main.c)
+
+#define CON_UART_ID 0
+#define CON_UART_SPEED 115200
+#define CON_TIMER_ID 0
+#define TERM_LINES 25
+#define TERM_COLS 80
+
+// *****************************************************************************
+// Auxiliary libraries that will be compiled for this platform
+
+#define LUA_PLATFORM_LIBS_ROM\
+ _ROM( AUXLIB_PIO, luaopen_pio, pio_map )\
+ _ROM( AUXLIB_TMR, luaopen_tmr, tmr_map )\
+ _ROM( AUXLIB_UART, luaopen_uart, uart_map )\
+ _ROM( AUXLIB_PIO, luaopen_pio, pio_map )\
+ _ROM( AUXLIB_PD, luaopen_pd, pd_map )\
+ _ROM( AUXLIB_TERM, luaopen_term, term_map )\
+ _ROM( AUXLIB_PACK, luaopen_pack, pack_map )\
+ _ROM( AUXLIB_BIT, luaopen_bit, bit_map )\
+ _ROM( AUXLIB_CPU, luaopen_cpu, cpu_map )\
+ _ROM( AUXLIB_PWM, luaopen_pwm, pwm_map )\
+ _ROM( LUA_MATHLIBNAME, luaopen_math, math_map )
+
+// *****************************************************************************
+// Configuration data
+
+// Virtual timers (0 if not used)
+#define VTMR_NUM_TIMERS 4
+#define VTMR_FREQ_HZ 4
+
+// Number of resources (0 if not available/not implemented)
+#define NUM_PIO 5
+#define NUM_SPI 0
+#define NUM_UART 4
+#define NUM_PWM 12
+#define NUM_ADC 0
+#define NUM_CAN 0
+// If virtual timers are enabled, the last timer will be used only for them
+#if VTMR_NUM_TIMERS == 0
+#define NUM_TIMER 4
+#else
+#define NUM_TIMER 3
+#endif
+
+// Enable RX buffering on UART
+// [TODO] make this happen
+//#define BUF_ENABLE_UART
+//#define CON_BUF_SIZE BUF_SIZE_128
+
+// CPU frequency (needed by the CPU module, 0 if not used)
+#define CPU_FREQUENCY Fcclk
+
+// PIO prefix ('0' for P0, P1, ... or 'A' for PA, PB, ...)
+#define PIO_PREFIX '0'
+// Pins per port configuration:
+// #define PIO_PINS_PER_PORT (n) if each port has the same number of pins, or
+// #define PIO_PIN_ARRAY { n1, n2, ... } to define pins per port in an array
+// Use #define PIO_PINS_PER_PORT 0 if this isn't needed
+#define PIO_PINS_PER_PORT 31
+
+// Allocator data: define your free memory zones here in two arrays
+// (start address and end address)
+#define SRAM_ORIGIN 0x40000000
+#define SRAM_SIZE 0x10000 // [TODO]: make this 96k?
+#define MEM_START_ADDRESS { ( void* )end }
+#define MEM_END_ADDRESS { ( void* )( SRAM_ORIGIN + SRAM_SIZE - STACK_SIZE_TOTAL - 1 ) }
+
+// *****************************************************************************
+// CPU constants that should be exposed to the eLua "cpu" module
+
+#define PINSEL_BASE_ADDR 0xE002C000
+#define IO_PINSEL0 ( PINSEL_BASE_ADDR + 0x00 )
+#define IO_PINSEL1 ( PINSEL_BASE_ADDR + 0x04 )
+#define IO_PINSEL2 ( PINSEL_BASE_ADDR + 0x08 )
+#define IO_PINSEL3 ( PINSEL_BASE_ADDR + 0x0C )
+#define IO_PINSEL4 ( PINSEL_BASE_ADDR + 0x10 )
+#define IO_PINSEL5 ( PINSEL_BASE_ADDR + 0x14 )
+#define IO_PINSEL6 ( PINSEL_BASE_ADDR + 0x18 )
+#define IO_PINSEL7 ( PINSEL_BASE_ADDR + 0x1C )
+#define IO_PINSEL8 ( PINSEL_BASE_ADDR + 0x20 )
+#define IO_PINSEL9 ( PINSEL_BASE_ADDR + 0x24 )
+#define IO_PINSEL10 ( PINSEL_BASE_ADDR + 0x28 )
+
+#define PLATFORM_CPU_CONSTANTS\
+ _C( IO_PINSEL0 ),\
+ _C( IO_PINSEL1 ),\
+ _C( IO_PINSEL2 ),\
+ _C( IO_PINSEL3 ),\
+ _C( IO_PINSEL4 ),\
+ _C( IO_PINSEL5 ),\
+ _C( IO_PINSEL6 ),\
+ _C( IO_PINSEL7 ),\
+ _C( IO_PINSEL8 ),\
+ _C( IO_PINSEL9 ),\
+ _C( IO_PINSEL10 )
+
+#endif // #ifndef __PLATFORM_CONF_H__
+
Added: branches/eagle_mmc/src/platform/lpc24xx/stacks.h
===================================================================
--- branches/eagle_mmc/src/platform/lpc24xx/stacks.h 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lpc24xx/stacks.h 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,11 @@
+// Stack size definitions
+
+#ifndef __STACKS_H__
+#define __STACKS_H__
+
+#define STACK_SIZE_USR 8192
+#define STACK_SIZE_IRQ 64
+#define STACK_SIZE_TOTAL ( STACK_SIZE_USR + STACK_SIZE_IRQ )
+
+#endif
+
Added: branches/eagle_mmc/src/platform/lpc24xx/startup.s
===================================================================
--- branches/eagle_mmc/src/platform/lpc24xx/startup.s 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lpc24xx/startup.s 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,127 @@
+#include "stacks.h"
+
+//------------------------------------------------------------------------------
+// Definitions
+//------------------------------------------------------------------------------
+
+#define ARM_MODE_ABT 0x17
+#define ARM_MODE_FIQ 0x11
+#define ARM_MODE_IRQ 0x12
+#define ARM_MODE_SVC 0x13
+
+#define I_BIT 0x80
+#define F_BIT 0x40
+
+
+#define RAM_Base 0x40000000
+#define RAM_Size 0x10000 // [TODO] make this 96k?
+#define Top_Stack (RAM_Base + RAM_Size)
+
+//------------------------------------------------------------------------------
+// Startup routine
+//------------------------------------------------------------------------------
+
+ .align 4
+ .arm
+
+/* Exception vectors
+ *******************/
+ .section .vectors, "a"
+
+resetVector:
+ ldr pc, =resetHandler /* Reset */
+undefVector:
+ b undefVector /* Undefined instruction */
+swiVector:
+ b swiVector /* Software interrupt */
+prefetchAbortVector:
+ b prefetchAbortVector /* Prefetch abort */
+dataAbortVector:
+ b dataAbortVector /* Data abort */
+reservedVector:
+ b reservedVector /* Reserved for future use */
+irqVector:
+ ldr pc, [pc, #-0x0120] /* Vector from VicVectAddr */
+fiqVector:
+ b fiqVector /* Fast interrupt */
+
+//------------------------------------------------------------------------------
+/// Initializes the chip and branches to the main() function.
+//------------------------------------------------------------------------------
+ .section .text
+ .global entry
+ .extern main
+ .extern TargetResetInit
+
+entry:
+resetHandler:
+
+// [TODO] enable interrupts
+/* Setup stacks for each mode */
+ ldr r0, =Top_Stack
+
+ msr CPSR_c, #ARM_MODE_IRQ|I_BIT|F_BIT
+ mov r13, r0
+ sub r0, r0, #STACK_SIZE_IRQ
+
+ # Set up Supervisor Mode and set Supervisor Mode Stack (leave interrupts enabled)
+ msr CPSR_c, #ARM_MODE_SVC|F_BIT
+ mov r13, r0
+
+
+/* Perform low-level initialization of the chip using LowLevelInit() */
+/* Initialize the relocate segment */
+
+ ldr r0, =_efixed
+ ldr r1, =_srelocate
+ ldr r2, =_erelocate
+CopyROMtoRAM:
+ cmp r1, r2
+ ldrcc r3, [r0], #4
+ strcc r3, [r1], #4
+ bcc CopyROMtoRAM
+
+/* Clear the zero segment */
+ ldr r0, =_szero
+ ldr r1, =_ezero
+ mov r2, #0
+ZeroBSS:
+ cmp r0, r1
+ strcc r2, [r0], #4
+ bcc ZeroBSS
+
+ /* Call external initialization code */
+ bl TargetResetInit
+
+/* Branch to main()
+ ******************/
+ ldr r0, =main
+ mov lr, pc
+ bx r0
+
+/* Loop indefinitely when program is finished */
+forever:
+ b forever
+
+# enable interrupts
+ .global enable_ints
+enable_ints:
+ stmfd sp!, {r1}
+ mrs r1, CPSR
+ bic r1, r1, #I_BIT
+ msr CPSR_c, r1
+ ldmfd sp!, {r1}
+ mov pc, r14
+
+# disable interrupts
+ .global disable_ints
+disable_ints:
+ stmfd sp!, {r1}
+ mrs r1, CPSR
+ orr r1, r1, #I_BIT
+ msr CPSR_c, r1
+ ldmfd sp!, {r1}
+ mov pc, r14
+
+ .end
+
Added: branches/eagle_mmc/src/platform/lpc24xx/target.c
===================================================================
--- branches/eagle_mmc/src/platform/lpc24xx/target.c 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lpc24xx/target.c 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,196 @@
+/*****************************************************************************
+ * target.c: Target C file for NXP LPC23xx/24xx Family Microprocessors
+ *
+ * Copyright(C) 2006, NXP Semiconductor
+ * All rights reserved.
+ *
+ * History
+ * 2006.07.13 ver 1.00 Prelimnary version, first Release
+ *
+*****************************************************************************/
+#include "LPC23xx.h"
+#include "type.h"
+#include "irq.h"
+#include "target.h"
+
+/******************************************************************************
+** Function name: TargetInit
+**
+** Descriptions: Initialize the target board; it is called in a necessary
+** place, change it as needed
+**
+** parameters: None
+** Returned value: None
+**
+******************************************************************************/
+void TargetInit(void)
+{
+ /* Add your codes here */
+ return;
+}
+
+/******************************************************************************
+** Function name: GPIOResetInit
+**
+** Descriptions: Initialize the target board before running the main()
+** function; User may change it as needed, but may not
+** deleted it.
+**
+** parameters: None
+** Returned value: None
+**
+******************************************************************************/
+void GPIOResetInit( void )
+{
+ /* Reset all GPIO pins to default: primary function */
+ PINSEL0 = 0x00000000;
+ PINSEL1 = 0x00000000;
+ PINSEL2 = 0x00000000;
+ PINSEL3 = 0x00000000;
+ PINSEL4 = 0x00000000;
+ PINSEL5 = 0x00000000;
+ PINSEL6 = 0x00000000;
+ PINSEL7 = 0x00000000;
+ PINSEL8 = 0x00000000;
+ PINSEL9 = 0x00000000;
+ PINSEL10 = 0x00000000;
+
+ IODIR0 = 0x00000000;
+ IODIR1 = 0x00000000;
+ IOSET0 = 0x00000000;
+ IOSET1 = 0x00000000;
+
+ FIO0DIR = 0x00000000;
+ FIO1DIR = 0x00000000;
+ FIO2DIR = 0x00000000;
+ FIO3DIR = 0x00000000;
+ FIO4DIR = 0x00000000;
+
+ FIO0SET = 0x00000000;
+ FIO1SET = 0x00000000;
+ FIO2SET = 0x00000000;
+ FIO3SET = 0x00000000;
+ FIO4SET = 0x00000000;
+ return;
+}
+
+/******************************************************************************
+** Function name: ConfigurePLL
+**
+** Descriptions: Configure PLL switching to main OSC instead of IRC
+** at power up and wake up from power down.
+** This routine is used in TargetResetInit() and those
+** examples using power down and wake up such as
+** USB suspend to resume, ethernet WOL, and power management
+** example
+** parameters: None
+** Returned value: None
+**
+******************************************************************************/
+void ConfigurePLL ( void )
+{
+ DWORD MValue, NValue;
+
+ if ( PLLSTAT & (1 << 25) )
+ {
+ PLLCON = 1; /* Enable PLL, disconnected */
+ PLLFEED = 0xaa;
+ PLLFEED = 0x55;
+ }
+
+ PLLCON = 0; /* Disable PLL, disconnected */
+ PLLFEED = 0xaa;
+ PLLFEED = 0x55;
+
+ SCS |= 0x20; /* Enable main OSC */
+ while( !(SCS & 0x40) ); /* Wait until main OSC is usable */
+
+ CLKSRCSEL = 0x1; /* select main OSC, 12MHz, as the PLL clock source */
+
+ PLLCFG = PLL_MValue | (PLL_NValue << 16);
+ PLLFEED = 0xaa;
+ PLLFEED = 0x55;
+
+ PLLCON = 1; /* Enable PLL, disconnected */
+ PLLFEED = 0xaa;
+ PLLFEED = 0x55;
+
+ CCLKCFG = CCLKDivValue; /* Set clock divider */
+#if USE_USB
+ USBCLKCFG = USBCLKDivValue; /* usbclk = 288 MHz/6 = 48 MHz */
+#endif
+
+ while ( ((PLLSTAT & (1 << 26)) == 0) ); /* Check lock bit status */
+
+ MValue = PLLSTAT & 0x00007FFF;
+ NValue = (PLLSTAT & 0x00FF0000) >> 16;
+ while ((MValue != PLL_MValue) && ( NValue != PLL_NValue) );
+
+ PLLCON = 3; /* enable and connect */
+ PLLFEED = 0xaa;
+ PLLFEED = 0x55;
+ while ( ((PLLSTAT & (1 << 25)) == 0) ); /* Check connect bit status */
+}
+
+/******************************************************************************
+** Function name: TargetResetInit
+**
+** Descriptions: Initialize the target board before running the main()
+** function; User may change it as needed, but may not
+** deleted it.
+**
+** parameters: None
+** Returned value: None
+**
+******************************************************************************/
+void TargetResetInit(void)
+{
+#ifdef __DEBUG_RAM
+ MEMMAP = 0x2; /* remap to internal RAM */
+#endif
+
+#ifdef __DEBUG_FLASH
+ MEMMAP = 0x1; /* remap to internal flash */
+#endif
+
+#if USE_USB
+ PCONP |= 0x80000000; /* Turn On USB PCLK */
+#endif
+ /* Configure PLL, switch from IRC to Main OSC */
+ ConfigurePLL();
+
+ /* Set system timers for each component */
+#if (Fpclk / (Fcclk / 4)) == 1
+ PCLKSEL0 = 0x00000000; /* PCLK is 1/4 CCLK */
+ PCLKSEL1 = 0x00000000;
+#endif
+#if (Fpclk / (Fcclk / 4)) == 2
+ PCLKSEL0 = 0xAAAAAAAA; /* PCLK is 1/2 CCLK */
+ PCLKSEL1 = 0xAAAAAAAA;
+#endif
+#if (Fpclk / (Fcclk / 4)) == 4
+ PCLKSEL0 = 0x55555555; /* PCLK is the same as CCLK */
+ PCLKSEL1 = 0x55555555;
+#endif
+
+ /* Set memory accelerater module*/
+ MAMCR = 0;
+#if Fcclk < 20000000
+ MAMTIM = 1;
+#else
+#if Fcclk < 40000000
+ MAMTIM = 2;
+#else
+ MAMTIM = 3;
+#endif
+#endif
+ MAMCR = 2;
+
+ GPIOResetInit();
+
+ init_VIC();
+}
+
+/******************************************************************************
+** End Of File
+******************************************************************************/
Added: branches/eagle_mmc/src/platform/lpc24xx/target.h
===================================================================
--- branches/eagle_mmc/src/platform/lpc24xx/target.h 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lpc24xx/target.h 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,136 @@
+/*****************************************************************************
+ * target.h: Header file for NXP LPC23xx/24xx Family Microprocessors
+ *
+ * Copyright(C) 2006, NXP Semiconductor
+ * All rights reserved.
+ *
+ * History
+ * 2006.09.20 ver 1.00 Prelimnary version, first Release
+ *
+******************************************************************************/
+#ifndef __TARGET_H
+#define __TARGET_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Only choose one of them below, by default, it's Keil MCB2300 */
+/*#define ENG_BOARD_LPC24XX 0
+#define KEIL_BOARD_LPC23XX 1
+#define EA_BOARD_LPC24XX 0
+#define IAR_BOARD_LPC23XX 0*/
+
+/* On EA and IAR boards, they use Micrel PHY.
+ on ENG and KEIL boards, they use National PHY */
+/*#define NATIONAL_PHY 1
+#define MICREL_PHY 2*/
+
+/* If USB device is used, CCO will be 288Mhz( divided by 6) or 384Mhz( divided by 8)
+to get precise USB clock 48Mhz. If USB is not used, you set any clock you want
+but make sure the divider of the CCO should be an even number. If you want to
+use USB, change "define USE_USB" from 0 to 1 */
+
+#define USE_USB 0
+
+/* PLL Setting Table Matrix */
+/*
+ Main Osc. CCLKCFG Fcco Fcclk M N
+ 12Mhz 29 300Mhz 10Mhz 24 1
+ 12Mhz 35 360Mhz 10Mhz 14 0
+ 12Mhz 27 336Mhz 12Mhz 13 0
+ 12Mhz 17 360Mhz 20Mhz 14 0
+ 12Mhz 13 336Mhz 24Mhz 13 0
+ 12Mhz 11 300Mhz 25Mhz 24 1
+ 12Mhz 9 300Mhz 30Mhz 24 1
+ 12Mhz 11 360Mhz 30Mhz 14 0
+ 12Mhz 9 320Mhz 32Mhz 39 2
+ 12Mhz 9 350Mhz 35Mhz 174 11
+ 12Mhz 7 312Mhz 39Mhz 12 0
+ 12Mhz 7 360Mhz 45Mhz 14 0
+ 12Mhz 5 300Mhz 50Mhz 24 1
+ 12Mhz 5 312Mhz 52Mhz 12 0
+ 12Mhz 5 336Mhz 56Mhz 13 0
+ 12Mhz 3 300Mhz 75Mhz 24 1
+ 12Mhz 3 312Mhz 78Mhz 12 0
+ 12Mhz 3 320Mhz 80Mhz 39 2
+ 12Mhz 3 336Mhz 84Mhz 13 0
+*/
+
+/* These are limited number of Fcco configuration for
+USB communication as the CPU clock and USB clock shares
+the same PLL. The USB clock needs to be multiple of
+48Mhz. */
+#if USE_USB /* 1 is USB, 0 is non-USB related */
+/* Fcck = 48Mhz, Fosc = 288Mhz, and USB 48Mhz */
+#define PLL_MValue 11
+#define PLL_NValue 0
+#define CCLKDivValue 5
+#define USBCLKDivValue 5
+
+/* System configuration: Fosc, Fcclk, Fcco, Fpclk must be defined */
+/* PLL input Crystal frequence range 4KHz~20MHz. */
+#define Fosc 12000000
+/* System frequence,should be less than 80MHz. */
+#define Fcclk 48000000
+#define Fcco 288000000
+
+#else // #if USE_USB
+
+
+// [TODO]: use the PLL calculator XLS to increase frequency a bit
+/* Fcck = 60Mhz, Fosc = 360Mhz, USB can't be divided into 48Mhz
+in this case, so USBCLKDivValue is not needed. */
+#if 0 // 60MHz
+#define PLL_MValue 14
+#define PLL_NValue 0
+#define CCLKDivValue 5
+#define Fcclk 60000000ULL
+#else // 72MHz
+#define PLL_MValue 14
+#define PLL_NValue 0
+#define CCLKDivValue 4
+#define Fcclk 72000000ULL
+#endif
+
+/* System configuration: Fosc, Fcclk, Fcco, Fpclk must be defined */
+/* PLL input Crystal frequence range 4KHz~20MHz. */
+#define Fosc 12000000
+/* System frequence,should be less than 72MHz. */
+#define Fcco 360000000
+
+#endif
+
+/* APB clock frequence , must be 1/2/4 multiples of ( Fcclk/4 ). */
+/* If USB is enabled, the minimum APB must be greater than 16Mhz */
+#if USE_USB
+#define Fpclk (Fcclk / 2)
+#else
+#define Fpclk (Fcclk / 4)
+#endif
+
+#define Fpclk_MHz (Fpclk / 1000000)
+#define Fpclk_UART (Fcclk)
+
+/******************************************************************************
+** Function name: TargetInit
+**
+** Descriptions: Initialize the target board; it is called in a
+** necessary place, change it as needed
+**
+** parameters: None
+** Returned value: None
+**
+******************************************************************************/
+extern void TargetInit(void);
+extern void ConfigurePLL( void );
+extern void TargetResetInit(void);
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* end __TARGET_H */
+/******************************************************************************
+** End Of File
+******************************************************************************/
Added: branches/eagle_mmc/src/platform/lpc24xx/type.h
===================================================================
--- branches/eagle_mmc/src/platform/lpc24xx/type.h 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lpc24xx/type.h 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,29 @@
+#ifndef __TYPE_H__
+#define __TYPE_H__
+
+typedef unsigned char u8;
+typedef signed char s8;
+typedef unsigned short u16;
+typedef signed short s16;
+typedef unsigned long u32;
+typedef signed long s32;
+typedef unsigned long long u64;
+typedef signed long long s64;
+
+#ifndef FALSE
+#define FALSE (0)
+#endif
+
+#ifndef TRUE
+#define TRUE (1)
+#endif
+
+typedef unsigned char BYTE;
+typedef unsigned short WORD;
+typedef unsigned long DWORD;
+typedef unsigned int BOOL;
+
+typedef volatile unsigned long* PREG;
+
+#endif
+
Added: branches/eagle_mmc/src/platform/lpc24xx/uart.h
===================================================================
--- branches/eagle_mmc/src/platform/lpc24xx/uart.h 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/lpc24xx/uart.h 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,59 @@
+/*****************************************************************************
+ * uart.h: Header file for NXP LPC23xx Family Microprocessors
+ *
+ * Copyright(C) 2006, NXP Semiconductor
+ * All rights reserved.
+ *
+ * History
+ * 2006.09.01 ver 1.00 Prelimnary version, first Release
+ *
+ * Modified by BogdanM for eLua
+******************************************************************************/
+
+#ifndef __UART_H
+#define __UART_H
+
+#include "type.h"
+
+#define IER_RBR 0x01
+#define IER_THRE 0x02
+#define IER_RLS 0x04
+
+#define IIR_PEND 0x01
+#define IIR_RLS 0x03
+#define IIR_RDA 0x02
+#define IIR_CTI 0x06
+#define IIR_THRE 0x01
+
+#define LSR_RDR 0x01
+#define LSR_OE 0x02
+#define LSR_PE 0x04
+#define LSR_FE 0x08
+#define LSR_BI 0x10
+#define LSR_THRE 0x20
+#define LSR_TEMT 0x40
+#define LSR_RXFE 0x80
+
+// UART setup constants
+enum
+{
+ UART_DATABITS_5 = 0,
+ UART_DATABITS_6 = 1,
+ UART_DATABITS_7 = 2,
+ UART_DATABITS_8 = 3,
+ UART_STOPBITS_1 = 0,
+ UART_STOPBITS_2 = 4,
+ UART_PARITY_ENABLE = 8,
+ UART_PARITY_ODD = 0,
+ UART_PARITY_EVEN = 1 << 4,
+ UART_DLAB_ENABLE = 1 << 7,
+ UART_FIFO_ENABLE = 1,
+ UART_RXFIFO_RESET = 2,
+ UART_TXFIFO_RESET = 4
+};
+
+#endif /* end __UART_H */
+/*****************************************************************************
+** End Of File
+******************************************************************************/
+
Modified: branches/eagle_mmc/src/platform/str9/conf.py
===================================================================
--- branches/eagle_mmc/src/platform/str9/conf.py 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/str9/conf.py 2009-11-06 02:08:32 UTC (rev 526)
@@ -2,13 +2,13 @@
cpumode = ARGUMENTS.get( 'cpumode', 'arm' ).lower()
-specific_files = "startup912.s startup_generic.s platform.c 91x_scu.c 91x_fmi.c 91x_gpio.c 91x_uart.c 91x_tim.c 91x_vic.c interrupt.c"
+specific_files = "startup912.s startup_generic.s platform.c 91x_scu.c 91x_fmi.c 91x_gpio.c 91x_uart.c 91x_tim.c 91x_vic.c interrupt.c str9_pio.c"
# Check CPU
-if cputype == 'STR912FW44':
+if cputype == 'STR912FAW44':
ldscript = "str912fw44.lds"
else:
- print "Invalid STR9 CPU %s", cputype
+ print "Invalid STR9 CPU %s" % cputype
sys.exit( -1 )
# Check CPU mode
@@ -24,11 +24,16 @@
specific_files = " ".join( [ "src/platform/%s/%s" % ( platform, f ) for f in specific_files.split() ] )
ldscript = "src/platform/%s/%s" % ( platform, ldscript )
+# toolchain 'arm-gcc' requires '-mfpu=fpa' for some reason
+auxm = ''
+if toolchain == 'arm-gcc':
+ auxm = '-mfpu=fpa'
+
# Toolset data
tools[ 'str9' ] = {}
-tools[ 'str9' ][ 'cccom' ] = "%s -mcpu=arm966e-s -mfpu=fpa %s $_CPPINCFLAGS %s -ffunction-sections -fdata-sections %s -Wall -c $SOURCE -o $TARGET" % ( toolset[ 'compile'], opt, modeflag, cdefs )
-tools[ 'str9' ][ 'linkcom' ] = "%s -mcpu=arm966e-s -mfpu=fpa -nostartfiles -nostdlib %s -T %s -Wl,--gc-sections -Wl,-e,_startup -Wl,--allow-multiple-definition -o $TARGET $SOURCES %s -lc -lgcc -lm" % ( toolset[ 'compile' ], modeflag, ldscript, local_libs )
-tools[ 'str9' ][ 'ascom' ] = "%s -x assembler-with-cpp $_CPPINCFLAGS -mcpu=arm966e-s -mfpu=fpa %s %s -Wall -c $SOURCE -o $TARGET" % ( toolset[ 'compile' ], modeflag, cdefs )
+tools[ 'str9' ][ 'cccom' ] = "%s -mcpu=arm966e-s %s %s $_CPPINCFLAGS %s -ffunction-sections -fdata-sections %s -Wall -c $SOURCE -o $TARGET" % ( toolset[ 'compile'], auxm, opt, modeflag, cdefs )
+tools[ 'str9' ][ 'linkcom' ] = "%s -mcpu=arm966e-s %s -nostartfiles -nostdlib %s -T %s -Wl,--gc-sections -Wl,-e,_startup -Wl,--allow-multiple-definition -o $TARGET $SOURCES %s -lc -lgcc -lm" % ( toolset[ 'compile' ], auxm, modeflag, ldscript, local_libs )
+tools[ 'str9' ][ 'ascom' ] = "%s -x assembler-with-cpp $_CPPINCFLAGS %s -mfpu=fpa %s %s -Wall -c $SOURCE -o $TARGET" % ( toolset[ 'compile' ], auxm, modeflag, cdefs )
# Programming function for LPC2888
def progfunc_str9( target, source, env ):
Modified: branches/eagle_mmc/src/platform/str9/platform.c
===================================================================
--- branches/eagle_mmc/src/platform/str9/platform.c 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/str9/platform.c 2009-11-06 02:08:32 UTC (rev 526)
@@ -18,13 +18,11 @@
#include "common.h"
#include "platform_conf.h"
#include "91x_vic.h"
+#include "lrotable.h"
-// We define here the UART used by this porting layer
-#define STR9_UART UART1
-
// ****************************************************************************
// Platform initialization
-static const GPIO_TypeDef* port_data[] = { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7, GPIO8, GPIO9 };
+const GPIO_TypeDef* port_data[] = { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7, GPIO8, GPIO9 };
static const TIM_TypeDef* timer_data[] = { TIM0, TIM1, TIM2, TIM3 };
static void platform_config_scu()
@@ -42,8 +40,8 @@
/* Set the RCLK Clock divider to max speed*/
SCU_RCLKDivisorConfig(SCU_RCLK_Div1);
- /* Set the PCLK Clock to MCLK/8 */
- SCU_PCLKDivisorConfig(SCU_PCLK_Div8);
+ /* Set the PCLK Clock to MCLK/2 */
+ SCU_PCLKDivisorConfig(SCU_PCLK_Div2);
/* Set the HCLK Clock to MCLK */
SCU_HCLKDivisorConfig(SCU_HCLK_Div1);
@@ -64,6 +62,37 @@
SCU_APBPeriphClockConfig(__GPIO_ALL, ENABLE);
}
+// Port/pin definitions of the eLua UART connection for different boards
+#define UART_RX_IDX 0
+#define UART_TX_IDX 1
+
+#ifdef ELUA_BOARD_STRE912
+static const GPIO_TypeDef* uart_port_data[] = { GPIO5, GPIO5 };
+static const u8 uart_pin_data[] = { GPIO_Pin_1, GPIO_Pin_0 };
+#else // STR9-comStick
+static const GPIO_TypeDef* uart_port_data[] = { GPIO3, GPIO3 };
+static const u8 uart_pin_data[] = { GPIO_Pin_2, GPIO_Pin_3 };
+#endif
+
+// Plaform specific GPIO UART setup
+static void platform_gpio_uart_setup()
+{
+ GPIO_InitTypeDef GPIO_InitStructure;
+
+ GPIO_StructInit( &GPIO_InitStructure );
+ // RX
+ GPIO_InitStructure.GPIO_Direction = GPIO_PinInput;
+ GPIO_InitStructure.GPIO_Pin = uart_pin_data[ UART_RX_IDX ];
+ GPIO_InitStructure.GPIO_Type = GPIO_Type_PushPull ;
+ GPIO_InitStructure.GPIO_IPConnected = GPIO_IPConnected_Enable;
+ GPIO_InitStructure.GPIO_Alternate = GPIO_InputAlt1 ;
+ GPIO_Init( ( GPIO_TypeDef* )uart_port_data[ UART_RX_IDX ], &GPIO_InitStructure );
+ // TX
+ GPIO_InitStructure.GPIO_Pin = uart_pin_data[ UART_TX_IDX ];
+ GPIO_InitStructure.GPIO_Alternate = GPIO_OutputAlt3 ;
+ GPIO_Init( ( GPIO_TypeDef* )uart_port_data[ UART_TX_IDX ], &GPIO_InitStructure );
+}
+
int platform_init()
{
unsigned i;
@@ -80,7 +109,8 @@
// Initialize VIC
VIC_DeInit();
- // UART setup (only STR9_UART is used in this example)
+ // UART setup
+ platform_gpio_uart_setup();
platform_uart_setup( CON_UART_ID, CON_UART_SPEED, 8, PLATFORM_UART_PARITY_NONE, PLATFORM_UART_STOPBITS_1 );
// Initialize timers
@@ -159,25 +189,12 @@
// ****************************************************************************
// UART
+static const UART_TypeDef* uarts[] = { UART0, UART1, UART2 };
+
u32 platform_uart_setup( unsigned id, u32 baud, int databits, int parity, int stopbits )
{
UART_InitTypeDef UART_InitStructure;
- GPIO_InitTypeDef GPIO_InitStructure;
-
- id = id;
-
- // First configure GPIO
- // RX: GPIO3.2
- GPIO_InitStructure.GPIO_Direction = GPIO_PinInput;
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
- GPIO_InitStructure.GPIO_Type = GPIO_Type_PushPull ;
- GPIO_InitStructure.GPIO_IPConnected = GPIO_IPConnected_Enable;
- GPIO_InitStructure.GPIO_Alternate = GPIO_InputAlt1 ;
- GPIO_Init (GPIO3, &GPIO_InitStructure);
- // TX: GPIO3.3
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3;
- GPIO_InitStructure.GPIO_Alternate = GPIO_OutputAlt2 ;
- GPIO_Init (GPIO3, &GPIO_InitStructure);
+ UART_TypeDef* p_uart = ( UART_TypeDef* )uarts[ id ];
// Then configure UART parameters
switch( databits )
@@ -212,33 +229,36 @@
UART_InitStructure.UART_TxFIFOLevel = UART_FIFOLevel_1_2; /* FIFO size 16 bytes, FIFO level 8 bytes */
UART_InitStructure.UART_RxFIFOLevel = UART_FIFOLevel_1_2; /* FIFO size 16 bytes, FIFO level 8 bytes */
- UART_DeInit(STR9_UART);
- UART_Init(STR9_UART, &UART_InitStructure);
- UART_Cmd(STR9_UART, ENABLE);
+ UART_DeInit( p_uart );
+ UART_Init( p_uart , &UART_InitStructure );
+ UART_Cmd( p_uart, ENABLE );
return baud;
}
void platform_uart_send( unsigned id, u8 data )
{
- id = id;
+ UART_TypeDef* p_uart = ( UART_TypeDef* )uarts[ id ];
+
// while( UART_GetFlagStatus( STR9_UART, UART_FLAG_TxFIFOFull ) == SET );
- UART_SendData( STR9_UART, data );
- while( UART_GetFlagStatus( STR9_UART, UART_FLAG_TxFIFOFull ) != RESET );
+ UART_SendData( p_uart, data );
+ while( UART_GetFlagStatus( p_uart, UART_FLAG_TxFIFOFull ) != RESET );
}
int platform_s_uart_recv( unsigned id, s32 timeout )
{
+ UART_TypeDef* p_uart = ( UART_TypeDef* )uarts[ id ];
+
if( timeout == 0 )
{
// Return data only if already available
- if( UART_GetFlagStatus( STR9_UART, UART_FLAG_RxFIFOEmpty ) != SET )
- return UART_ReceiveData( STR9_UART );
+ if( UART_GetFlagStatus( p_uart, UART_FLAG_RxFIFOEmpty ) != SET )
+ return UART_ReceiveData( p_uart );
else
return -1;
}
- while( UART_GetFlagStatus( STR9_UART, UART_FLAG_RxFIFOEmpty ) == SET );
- return UART_ReceiveData( STR9_UART );
+ while( UART_GetFlagStatus( p_uart, UART_FLAG_RxFIFOEmpty ) == SET );
+ return UART_ReceiveData( p_uart );
}
// ****************************************************************************
@@ -326,6 +346,66 @@
}
// ****************************************************************************
+// PWM functions
+
+u32 platform_pwm_setup( unsigned id, u32 frequency, unsigned duty )
+{
+ TIM_TypeDef* p_timer = ( TIM_TypeDef* )timer_data[ id ];
+ u32 base = SCU_GetPCLKFreqValue() * 1000;
+ u32 div = ( base / 256 ) / frequency;
+ TIM_InitTypeDef tim;
+
+ TIM_DeInit( p_timer );
+ tim.TIM_Mode = TIM_PWM;
+ tim.TIM_Clock_Source = TIM_CLK_APB;
+ tim.TIM_Prescaler = 0xFF;
+ tim.TIM_Pulse_Level_1 = TIM_HIGH;
+ tim.TIM_Period_Level = TIM_LOW;
+ tim.TIM_Full_Period = div;
+ tim.TIM_Pulse_Length_1 = ( div * duty ) / 100;
+ TIM_Init( p_timer, &tim );
+
+ return base / div;
+}
+
+static u32 platform_pwm_set_clock( unsigned id, u32 clock )
+{
+ TIM_TypeDef* p_timer = ( TIM_TypeDef* )timer_data[ id ];
+ u32 base = ( SCU_GetPCLKFreqValue() * 1000 );
+ u32 div = base / clock;
+
+ TIM_PrescalerConfig( p_timer, ( u8 )div - 1 );
+ return base / div;
+}
+
+u32 platform_pwm_op( unsigned id, int op, u32 data )
+{
+ u32 res = 0;
+ TIM_TypeDef* p_timer = ( TIM_TypeDef* )timer_data[ id ];
+
+ switch( op )
+ {
+ case PLATFORM_PWM_OP_START:
+ TIM_CounterCmd( p_timer, TIM_START );
+ break;
+
+ case PLATFORM_PWM_OP_STOP:
+ TIM_CounterCmd( p_timer, TIM_STOP );
+ break;
+
+ case PLATFORM_PWM_OP_SET_CLOCK:
+ res = platform_pwm_set_clock( id, data );
+ break;
+
+ case PLATFORM_PWM_OP_GET_CLOCK:
+ res = ( SCU_GetPCLKFreqValue() * 1000 ) / ( TIM_GetPrescalerValue( p_timer ) + 1 );
+ break;
+ }
+
+ return res;
+}
+
+// ****************************************************************************
// CPU functions
extern void enable_ints();
@@ -340,3 +420,35 @@
{
disable_ints();
}
+
+// ****************************************************************************
+// Platform specific modules go here
+
+#define MIN_OPT_LEVEL 2
+#include "lrodefs.h"
+extern const LUA_REG_TYPE str9_pio_map[];
+
+const LUA_REG_TYPE platform_map[] =
+{
+#if LUA_OPTIMIZE_MEMORY > 0
+ { LSTRKEY( "pio" ), LROVAL( str9_pio_map ) },
+#endif
+ { LNILKEY, LNILVAL }
+};
+
+LUALIB_API int luaopen_platform( lua_State *L )
+{
+#if LUA_OPTIMIZE_MEMORY > 0
+ return 0;
+#else // #if LUA_OPTIMIZE_MEMORY > 0
+ luaL_register( L, PS_LIB_TABLE_NAME, platform_map );
+
+ // Setup the new tables inside platform table
+ lua_newtable( L );
+ luaL_register( L, NULL, str9_pio_map );
+ lua_setfield( L, -2, "pio" );
+
+ return 1;
+#endif // #if LUA_OPTIMIZE_MEMORY > 0
+}
+
Modified: branches/eagle_mmc/src/platform/str9/platform_conf.h
===================================================================
--- branches/eagle_mmc/src/platform/str9/platform_conf.h 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/str9/platform_conf.h 2009-11-06 02:08:32 UTC (rev 526)
@@ -19,7 +19,12 @@
// *****************************************************************************
// UART/Timer IDs configuration data (used in main.c)
+#ifdef ELUA_BOARD_STRE912
#define CON_UART_ID 0
+#else // STR9-comStick
+#define CON_UART_ID 1
+#endif
+
#define CON_UART_SPEED 115200
#define CON_TIMER_ID 0
#define TERM_LINES 25
@@ -35,9 +40,9 @@
// Number of resources (0 if not available/not implemented)
#define NUM_PIO 10
#define NUM_SPI 0
-#define NUM_UART 1
+#define NUM_UART 3
#define NUM_TIMER 4
-#define NUM_PWM 0
+#define NUM_PWM 4
#define NUM_ADC 0
#define NUM_CAN 0
@@ -63,6 +68,9 @@
// *****************************************************************************
// Auxiliary libraries that will be compiled for this platform
+// The name of the platform specific libs table
+#define PS_LIB_TABLE_NAME "str9"
+
#define LUA_PLATFORM_LIBS_ROM\
_ROM( AUXLIB_PIO, luaopen_pio, pio_map )\
_ROM( AUXLIB_TMR, luaopen_tmr, tmr_map )\
@@ -72,6 +80,8 @@
_ROM( AUXLIB_PACK, luaopen_pack, pack_map )\
_ROM( AUXLIB_BIT, luaopen_bit, bit_map )\
_ROM( AUXLIB_CPU, luaopen_cpu, cpu_map)\
- _ROM( LUA_MATHLIBNAME, luaopen_math, math_map )
+ _ROM( AUXLIB_PWM, luaopen_pwm, pwm_map)\
+ _ROM( LUA_MATHLIBNAME, luaopen_math, math_map )\
+ _ROM( PS_LIB_TABLE_NAME, luaopen_platform, platform_map )
#endif // #ifndef __PLATFORM_CONF_H__
Added: branches/eagle_mmc/src/platform/str9/str9_pio.c
===================================================================
--- branches/eagle_mmc/src/platform/str9/str9_pio.c 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/platform/str9/str9_pio.c 2009-11-06 02:08:32 UTC (rev 526)
@@ -0,0 +1,92 @@
+// STR9 specific PIO support
+
+#include "lua.h"
+#include "lualib.h"
+#include "lauxlib.h"
+#include "platform.h"
+#include "lrotable.h"
+#include "platform_conf.h"
+#include "91x_gpio.h"
+#include "auxmods.h"
+
+#define GPIO_DIR_INPUT GPIO_PinInput
+#define GPIO_DIR_OUTPUT GPIO_PinOutput
+#define GPIO_ALT_INPUT GPIO_InputAlt1
+#define GPIO_ALT_OUTPUT1 GPIO_OutputAlt1
+#define GPIO_ALT_OUTPUT2 GPIO_OutputAlt2
+#define GPIO_ALT_OUTPUT3 GPIO_OutputAlt3
+#define GPIO_OUTPUT_PP GPIO_Type_PushPull
+#define GPIO_OUTPUT_OC GPIO_Type_OpenCollector
+
+// Puin mappings (for GPIO lib)
+static const unsigned str9_pins[] = { GPIO_Pin_0, GPIO_Pin_1, GPIO_Pin_2, GPIO_Pin_3, GPIO_Pin_4, GPIO_Pin_5, GPIO_Pin_6, GPIO_Pin_7 };
+extern const GPIO_TypeDef* port_data[];
+
+// Lua: str9.pio.set_input( pin, direction, type, ipconnected, alternate )
+// direction: INPUT, OUTPUT
+// type: OUTPUT_PUSHPULL, OUTPUT_OC
+// ipconnected: true or false
+// alternate: ALT_INPUT, ALT_OUTPUT1, ALT_OUTPUT2, ALT_OUTPUT3
+static int setpin( lua_State *L )
+{
+ pio_type v = ( pio_type )luaL_checkinteger( L, 1 );
+ int direction = luaL_checkinteger( L, 2 );
+ int type = luaL_checkinteger( L, 3 );
+ int ipconnected = lua_toboolean( L, 4 );
+ int alternate = luaL_checkinteger( L, 5 );
+ GPIO_InitTypeDef GPIO_InitStructure;
+ int port, pin;
+
+ port = PLATFORM_IO_GET_PORT( v );
+ pin = PLATFORM_IO_GET_PIN( v );
+ if( PLATFORM_IO_IS_PORT( v ) || !platform_pio_has_port( port ) || !platform_pio_has_pin( port, pin ) )
+ return luaL_error( L, "invalid pin" );
+
+ GPIO_StructInit( &GPIO_InitStructure );
+ GPIO_InitStructure.GPIO_Pin = str9_pins[ pin ];
+ GPIO_InitStructure.GPIO_Direction = direction;
+ GPIO_InitStructure.GPIO_Type = type;
+ GPIO_InitStructure.GPIO_IPConnected = ipconnected ? GPIO_IPConnected_Enable : GPIO_IPConnected_Disable;
+ GPIO_InitStructure.GPIO_Alternate = alternate;
+ GPIO_Init( ( GPIO_TypeDef* )port_data[ port ], &GPIO_InitStructure );
+
+ return 0;
+}
+
+// Module function map
+#define MIN_OPT_LEVEL 2
+#include "lrodefs.h"
+const LUA_REG_TYPE str9_pio_map[] =
+{
+#if LUA_OPTIMIZE_MEMORY > 0
+ { LSTRKEY( "INPUT" ), LNUMVAL( GPIO_DIR_INPUT ) },
+ { LSTRKEY( "OUTPUT" ), LNUMVAL( GPIO_DIR_OUTPUT ) },
+ { LSTRKEY( "ALT_INPUT" ), LNUMVAL( GPIO_ALT_INPUT ) },
+ { LSTRKEY( "ALT_OUTPUT1" ), LNUMVAL( GPIO_ALT_OUTPUT1 ) },
+ { LSTRKEY( "ALT_OUTPUT2" ), LNUMVAL( GPIO_ALT_OUTPUT2 ) },
+ { LSTRKEY( "ALT_OUTPUT3" ), LNUMVAL( GPIO_ALT_OUTPUT3 ) },
+ { LSTRKEY( "OUTPUT_PUSHPULL" ), LNUMVAL( GPIO_OUTPUT_PP ) },
+ { LSTRKEY( "OUTPUT_OC" ), LNUMVAL( GPIO_OUTPUT_OC ) },
+#endif
+ { LSTRKEY( "setpin" ), LFUNCVAL( setpin) },
+ { LNILKEY, LNILVAL }
+};
+
+LUALIB_API int luaopen_disp( lua_State *L )
+{
+#if LUA_OPTIMIZE_MEMORY > 0
+ return 0;
+#else
+ luaL_register( L, PS_LIB_TABLE_NAME, str9_pio_map );
+ MOD_REG_NUMBER( L, "INPUT", GPIO_DIR_INPUT );
+ MOD_REG_NUMBER( L, "OUTPUT", GPIO_DIR_OUTPUT );
+ MOD_REG_NUMBER( L, "ALT_INPUT", GPIO_ALT_INPUT );
+ MOD_REG_NUMBER( L, "ALT_OUTPUT1", GPIO_ALT_OUTPUT1 );
+ MOD_REG_NUMBER( L, "ALT_OUTPUT2", GPIO_ALT_OUTPUT2 );
+ MOD_REG_NUMBER( L, "ALT_OUTPUT3", GPIO_ALT_OUTPUT3 );
+ MOD_REG_NUMBER( L, "OUTPUT_PUSHPULL", GPIO_OUTPUT_PP );
+ MOD_REG_NUMBER( L, "OUTPUT_OC", GPIO_OUTPUT_OC );
+ return 1;
+#endif
+}
+
Modified: branches/eagle_mmc/src/romfs.c
===================================================================
--- branches/eagle_mmc/src/romfs.c 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/romfs.c 2009-11-06 02:08:32 UTC (rev 526)
@@ -17,7 +17,7 @@
static FS romfs_fd_table[ ROMFS_MAX_FDS ];
static int romfs_num_fd;
-static u8 romfs_read( u16 addr )
+static u8 romfs_read( u32 addr )
{
return romfiles_fs[ addr ];
}
@@ -37,14 +37,13 @@
memset( romfs_fd_table + fd, 0, sizeof( FS ) );
}
-
// Open the given file, returning one of FS_FILE_NOT_FOUND, FS_FILE_ALREADY_OPENED
// or FS_FILE_OK
u8 romfs_open_file( const char* fname, p_read_fs_byte p_read_func, FS* pfs )
{
- u16 i, j;
+ u32 i, j;
char fsname[ MAX_FNAME_LENGTH + 1 ];
- int fsize;
+ u16 fsize;
// Look for the file
i = 0;
@@ -66,7 +65,7 @@
j = i + j + 1;
// And read the size
fsize = p_read_func( j ) + ( p_read_func( j + 1 ) << 8 );
- if( !strncmp( fname, fsname, MAX_FNAME_LENGTH ) )
+ if( !strncasecmp( fname, fsname, MAX_FNAME_LENGTH ) )
{
// Found the file
pfs->baseaddr = j + 2;
@@ -130,7 +129,7 @@
{
struct fd_seek *pseek = ( struct fd_seek* )ptr;
FS* pfs = romfs_fd_table + fd;
- u16 newpos = 0;
+ u32 newpos = 0;
if( request == FDSEEK )
{
@@ -161,7 +160,6 @@
return -1;
}
-
// Our UART device descriptor structure
static DM_DEVICE romfs_device =
{
@@ -178,28 +176,23 @@
return &romfs_device;
}
-
// Retrieves file name and size from ROMFS entry at romfiles[offset]
// Returns the next file entry offset or null on last entry
-u16 romfs_get_dir_entry( u16 offset, char *fname, int *fsize )
+u32 romfs_get_dir_entry( u32 offset, char *fname, u16 *fsize )
{
- u16 i;
- int j;
+ u32 i = offset;
+ unsigned j = 0;
- i = offset;
- j = 0;
if ( romfs_read( i ) != 0 )
{
- while ( ( fname[j++] = romfs_read( i++ )));
- *fsize = (int) ( romfs_read( i ) + ( romfs_read( i+1 ) << 8 ) );
- return (u16) ( i + 2 + *fsize );
+ while( ( fname[ j++ ] = romfs_read( i++ ) ) );
+ *fsize = romfs_read( i ) + ( romfs_read( i + 1 ) << 8 );
+ return i + 2 + *fsize;
}
else
return 0;
}
-
-
#else // #ifdef BUILD_ROMFS
DM_DEVICE* romfs_init()
@@ -208,3 +201,4 @@
}
#endif // #ifdef BUILD_ROMFS
+
Modified: branches/eagle_mmc/src/shell.c
===================================================================
--- branches/eagle_mmc/src/shell.c 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/src/shell.c 2009-11-06 02:08:32 UTC (rev 526)
@@ -179,31 +179,30 @@
// 'ls' and 'dir' handler
static void shell_ls( char* args )
{
- char fname[MAX_FNAME_LENGTH + 1];
- int i, size;
- int total = 0;
-
-#if defined(BUILD_ROMFS)
- u16 offset = 0;
-
+ u32 offset = 0;
+ char fname[ MAX_FNAME_LENGTH + 1 ];
+ unsigned i;
+ u16 size;
+ u32 total = 0;
+
+ args = args;
printf( "\n/rom" );
while ( ( offset = romfs_get_dir_entry( offset, fname, &size ) ) )
{
printf( "\n%s", fname );
for( i = strlen( fname ); i <= MAX_FNAME_LENGTH; i++ )
printf( " " );
- printf( "%d bytes", size );
+ printf( "%u bytes", ( unsigned )size );
total = total + size;
}
- printf( "\n\nTotal = %d bytes\n", total );
-#endif
+ printf( "\n\nTotal = %u bytes\n\n", ( unsigned )total );
#if defined(BUILD_MMCFS)
total = 0;
printf( "\n/mmc" );
if (f_opendir(&mmc_dir, "/") != FR_OK)
{
- printf( "\n\nTotal = %d bytes\n\n", total );
+ printf( "\n\nTotal = %u bytes\n\n", ( unsigned )total );
return;
}
@@ -220,8 +219,6 @@
total = total + size;
}
printf( "\n\nTotal = %d bytes\n\n", total );
-#else
- printf( "\n" );
#endif
}
Modified: branches/eagle_mmc/test/test-rpc.lua
===================================================================
--- branches/eagle_mmc/test/test-rpc.lua 2009-11-06 02:08:17 UTC (rev 525)
+++ branches/eagle_mmc/test/test-rpc.lua 2009-11-06 02:08:32 UTC (rev 526)
@@ -5,8 +5,8 @@
rpc.on_error (error_handler);
--slave,err = rpc.connect ("/dev/tty.usbserial-FTE3HV7L");
-slave,err = rpc.connect ("/dev/tty.usbserial-ftCYPMYJ");
--- slave,err = rpc.connect("/dev/tty.usbserial-04110857B")
+-- slave,err = rpc.connect ("/dev/tty.usbserial-ftCYPMYJ");
+slave,err = rpc.connect("/dev/tty.usbserial-04110857B")
--slave,err = rpc.connect ("/dev/ttys0");
print("Platform: " .. slave.pd.platform())
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